ST STM32F401xB/C and STM32F401xD/E advanced Arm®-based 32-bit MCUs Reference Manual

PCLK

= 8 MHz or f

PCLK

= 12 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Table 75.

PCLK

= 8 MHz or f

PCLK

=12 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

Table 76.

PCLK

= 16 MHz or f

PCLK

= 24 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

Table 77.

Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

PCLK

= 16 MHz or f

PCLK

= 24 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

Table 78.

Table 79.

Error calculation for programmed baud rates at fPCLK = 8 MHz or fPCLK = 16 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Table 80.

Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

Table 81.

Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Table 82.

Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 Hz, oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Table 83.

Error calculation for programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

Table 84.

USART receiver’s tolerance when DIV fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table 85.

USART receiver tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . . 530

Table 86.

Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

Table 87.

USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Table 88.

USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

RM0368 Rev 5

25/847

List of tables RM0368

Table 89.

USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Table 90.

SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Table 91.

Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . . . . . . . . . . . . . . . . . 595

Table 92.

2 S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Table 93.

SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

Table 94.

SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

Table 95.

Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

Table 96.

Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

Table 97.

Long response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

Table 98.

Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

Table 99.

Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

Table 100. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Table 101. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Table 102. Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

Table 103. SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Table 104. Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

Table 105. Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

Table 106. AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Table 107. Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Table 108. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Table 109. Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Table 110. Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

Table 111. Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

Table 112. Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Table 113. Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Table 114. I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

Table 115. Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

Table 116. Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

Table 117. R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

Table 118. R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

Table 119. R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

Table 120. R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

Table 121. R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

Table 122. R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

Table 123. R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Table 124. Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Table 125. SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

Table 126. OTG_FS input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Table 127. Compatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . . 685

Table 128. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

Table 129. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Table 130. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

Table 131. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

Table 132. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

Table 133. TRDT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

Table 134. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

Table 135. OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

Table 136. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

Table 137. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

Table 138. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

Table 139. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 817

Table 140. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

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Table 141. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Table 142. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Table 143. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

Table 144. Cortex

® -M4 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

Table 145. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

Table 146. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

Table 147. Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

Table 148. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

Table 149. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

Table 150. Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

Table 151. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

Table 152. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

Table 153. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

RM0368 Rev 5

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List of figures

List of figures

RM0368

Figure 1.

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 2.

Flash memory interface connection inside system architecture

(STM32F401xB/C and STM32F401xD/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 3.

Sequential 32-bit instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 4.

RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 5.

PCROP levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 6.

CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 7.

Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 8.

Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 9.

BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 10.

PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 11.

Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 12.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 13.

HSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 14.

Frequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 15.

Frequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 102

Figure 16.

Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 17.

Selecting an alternate function on STM32F401xB/C and STM32F401xD/E . . . . . . . . . . 151

Figure 18.

Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 19.

Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 20.

Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 21.

High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 22.

DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 23.

System implementation of the two DMA controllers

(STM32F401xB/C and STM32F401xD/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 24.

Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 25.

Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 26.

Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 27.

Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 28.

FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 29.

External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 30.

External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 31.

Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 32.

Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 33.

Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 34.

Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 35.

Right alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 36.

Left alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 37.

Left alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 38.

Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 226

Figure 39.

Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 40.

Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 247

Figure 41.

Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 247

Figure 42.

Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 43.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 44.

Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 45.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 46.

Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 250

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Figure 47.

Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 250

Figure 48.

Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 49.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 50.

Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 51.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 52.

Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 254

Figure 53.

Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 255

Figure 54.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 55.

Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 256

Figure 56.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 57.

Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 257

Figure 58.

Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 257

Figure 59.

Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 258

Figure 60.

Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 61.

TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 62.

Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 63.

External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 64.

Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 65.

Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 263

Figure 66.

Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 67.

Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 68.

Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 69.

PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 70.

Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 71.

Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 72.

Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 73.

Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 74.

Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 272

Figure 75.

Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 272

Figure 76.

Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 77.

Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 78.

6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 79.

Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Figure 80.

Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 81.

Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 281

Figure 82.

Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 83.

Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Figure 84.

Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Figure 85.

Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 86.

Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 87.

General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 88.

Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 318

Figure 89.

Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 319

Figure 90.

Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 91.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 92.

Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 93.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 94.

Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 321

Figure 95.

Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 322

Figure 96.

Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 97.

Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 98.

Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

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Figure 99.

Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 100. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 101. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 325

Figure 102. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 326

Figure 104. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 105. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 327

Figure 106. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 327

Figure 107. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 108. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Figure 109. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 110. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 111. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Figure 112. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 331

Figure 113. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 114. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 115. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 116. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

Figure 117. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Figure 118. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Figure 119. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 120. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 121. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 122. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 343

Figure 123. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Figure 124. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Figure 125. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Figure 126. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Figure 127. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Figure 128. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Figure 129. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

Figure 130. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Figure 131. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Figure 132. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Figure 133. General-purpose timer block diagram (TIM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Figure 134. General-purpose timer block diagram (TIM10/11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 135. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 380

Figure 136. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 380

Figure 137. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 138. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 139. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 140. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 141. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 383

Figure 142. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 383

Figure 143. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 384

Figure 144. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 145. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 146. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 386

Figure 147. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 148. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 149. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

Figure 150. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

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Figure 151. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Figure 152. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Figure 153. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Figure 154. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Figure 155. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Figure 156. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Figure 157. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Figure 158. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

Figure 159. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Figure 160. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 161. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Figure 162. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Figure 163. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Figure 164. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Figure 165. Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Figure 166. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

Figure 167. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure 168. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Figure 169. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Figure 170. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Figure 171. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Figure 172. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Figure 173. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Figure 174. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Figure 175. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Figure 176. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 534

Figure 177. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 535

Figure 178. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Figure 179. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Figure 180. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Figure 181. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Figure 182. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Figure 183. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Figure 184. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Figure 185. IrDA data modulation (3/16) -Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Figure 186. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure 187. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Figure 188. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Figure 189. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

Figure 190. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Figure 191. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Figure 192. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Figure 193. Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Figure 194. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

Figure 195. TI mode - Slave mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

Figure 196. TI mode - Slave mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

Figure 197. TI mode - master mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

Figure 198. TI mode - master mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

Figure 199. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and

RXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

Figure 200. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,

RXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

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Figure 201. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Figure 202. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Figure 203. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Figure 204. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

Figure 205. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 206. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 207. TI mode frame format error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Figure 208. I

2 S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Figure 209. I2S full duplex block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Figure 210. I

Figure 211. I

S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 588

S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 588

Figure 212. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Figure 213. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

Figure 214. I

2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 589

Figure 215. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

Figure 216. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 590

Figure 217. MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Figure 218. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 590

Figure 219. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 591

Figure 220. LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Figure 221. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Figure 222. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Figure 223. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 592

Figure 224. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 592

Figure 225. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Figure 226. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 593

Figure 227. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 228. I

2 S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 229. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Figure 230. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Figure 231. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Figure 232. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

Figure 233. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

Figure 234. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

Figure 235. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Figure 236. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

Figure 237. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

Figure 238. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

Figure 239. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

Figure 240. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

Figure 241. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

Figure 242. OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Figure 243. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

Figure 244. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

Figure 245. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

Figure 246. SOF connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

Figure 247. Updating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

Figure 248. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 688

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RM0368 Rev 5

RM0368 List of figures

Figure 249. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . . 689

Figure 250. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Figure 251. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

Figure 252. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Figure 253. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

Figure 254. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 769

Figure 255. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

Figure 256. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

Figure 257. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

Figure 258. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785

Figure 259. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

Figure 260. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

Figure 261. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

Figure 262. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802

Figure 263. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

Figure 264. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804

Figure 265. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

Figure 266. Block diagram of STM32 MCU and Cortex ®

-M4 with FPU-level debug support . . . . . . . 808

Figure 267. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Figure 268. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

Figure 269. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

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Documentation conventions RM0368

The STM32F401xx devices have an Arm

® (a) Cortex

-M4 with FPU and an Arm

A7 with FPU cores.

Cortex

1.1 List of abbreviations for registers

The following abbreviations are used in register descriptions: read/write (rw) read-only (r) write-only (w)

Software can read and write to these bits.

Software can only read these bits.

Software can only write to this bit. Reading the bit returns the reset value.

read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value.

read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value.

read/clear by read

(rc_r)

Software can read this bit. Reading this bit automatically clears it to ‘0’.

Writing ‘0’ has no effect on the bit value.

read/set (rs) read-only write trigger (rt_w)

Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.

Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value.

toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.

Reserved (Res.) Reserved bit, must be kept at reset value.

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a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

RM0368 Rev 5

RM0368 Documentation conventions

1.2 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

• The CPU core integrates two debug ports:

– JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the

Joint Test Action Group (JTAG) protocol.

– SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.

For both the JTAG and SWD protocols, please refer to the Cortex

-M4 with FPU

Technical Reference Manual

• Word: data/instruction of 32-bit length.

• Half word: data/instruction of 16-bit length.

• Byte: data of 8-bit length.

• Double word: data of 64-bit length.

• IAP (in-application programming): IAP is the ability to reprogram the Flash memory of a microcontroller while the user program is running.

• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board.

• I-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction interface. Prefetch is performed on this bus.

• D-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU to the Flash data interface.

• Option bytes: product configuration bits stored in the Flash memory.

• OBL: option byte loader.

• AHB: advanced high-performance bus.

• CPU: refers to the Cortex

-M4 with FPU core.

For information on the availability and the number of instances of each peripheral in the various STM32F401xx salestypes, please refer to the STM32F401xB/C and

STM32F401xD/E datasheets.

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Memory and bus architecture

2 Memory and bus architecture

RM0368

In STM32F401xB/C and STM32F401xD/E, the main system consists of 32-bit multilayer

AHB bus matrix that interconnects:

• Six masters:

– Cortex

-M4 with FPU core I-bus, D-bus and S-bus

– DMA1 memory bus

– DMA2 memory bus

– DMA2 peripheral bus

• Five slaves:

– Internal Flash memory ICode bus

– Internal Flash memory DCode bus

– Main internal SRAM

– AHB1 peripherals including AHB to APB bridges and APB peripherals

– AHB2 peripherals

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in

Figure 1 .

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STM32F401xD/E: 384 KBytes / 512KBytes Flash with 96 KBytes SRAM.

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RM0368 Rev 5

RM0368 Memory and bus architecture

2.1.1 I-bus

This bus connects the Instruction bus of the Cortex

-M4 with FPU core to the BusMatrix.

This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM).

2.1.2 D-bus

This bus connects the databus of the Cortex ® -M4 with FPU to the BusMatrix. This bus is used by the core for literal load and debug access. The target of this bus is a memory containing code or data (internal Flash memory/SRAM).

2.1.3 S-bus

This bus connects the system bus of the Cortex

-M4 with FPU core to a BusMatrix. This bus is used to access data located in a peripheral or in SRAM. Instructions may also be fetched on this bus (less efficient than ICode). The targets of this bus are the internal

SRAM, the AHB1 peripherals including the APB peripherals and the AHB2 peripherals.

2.1.4 DMA memory bus

This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the

DMA to perform transfer to/from memories. The targets of this bus are data memories: internal Flash memory, internal SRAM and additionally for S4 the AHB1/AHB2 peripherals including the APB peripherals.

2.1.5 DMA peripheral bus

This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.

The targets of this bus are the AHB and APB peripherals plus data memories: Flash memory and internal SRAM.

2.1.6 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm.

Note:

The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.

Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies, and to

Table 1

for the address mapping of AHB and APB peripherals.

After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash memory interface). Before using a peripheral you have to enable its clock in the

RCC_AHBxENR or RCC_APBxENR register.

When a 16- or an 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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Memory and bus architecture RM0368

Program memory, data memory, registers and I/O ports are organized within the same linear

4 Gbyte address space.

The bytes are coded in memory in little endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte, the word’s most significant.

For the detailed mapping of peripheral registers, please refer to the related chapters.

The addressable memory space is divided into 8 main blocks, each of 512 MB.

All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the memory map figure in the product datasheet.

See the datasheet corresponding to your device for a comprehensive diagram of the memory map.

Table 1

gives the boundary addresses of the peripherals available in

STM32F401xB/C and STM32F401xD/E devices.

Table 1. STM32F401xB/C and STM32F401xD/E register boundary addresses

Boundary address Peripheral Bus Register map

0x5000 0000 - 0x5003 FFFF USB OTG FS AHB2

Section 22.16.6: OTG_FS register map on page 755

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3000 - 0x4002 33FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

DMA2

DMA1

Flash interface register

RCC

CRC

GPIOH

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

AHB1

Section 9.5.11: DMA register map on page 198

Section 3.8: Flash interface registers on page 60

Section 6.3.22: RCC register map on page 137

Section 4.4.4: CRC register map on page 70

Section 8.4.11: GPIO register map on page 164

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RM0368 Rev 5

RM0368 Memory and bus architecture

Table 1. STM32F401xB/C and STM32F401xD/E register boundary addresses (continued)

Boundary address Peripheral Bus Register map

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2000 - 0x4001 23FF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0000 - 0x4001 03FF

0x4000 7000 - 0x4000 73FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

TIM11

TIM10

TIM9

EXTI

SYSCFG

SPI4

SPI1

SDIO

ADC1

USART6

USART1

TIM1

PWR

I2C3

I2C2

I2C1

USART2

I2S3ext

APB2

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

SPI3 / I2S3

SPI2 / I2S2

I2S2ext

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

IWDG

WWDG

0x4000 2800 - 0x4000 2BFF RTC & BKP Registers

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

TIM5

TIM4

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

TIM3

TIM2

APB1

Section 14.5.12: TIM10/11 register map on page 420

Section 14.4.13: TIM9 register map on page 410

Section 10.3.7: EXTI register map on page 212

Section 7.2.8: SYSCFG register map

Section 20.5.10: SPI register map on page 611

Section 21.9.16: SDIO register map on page 667

Section 11.12.16: ADC register map on page 240

Section 19.6.8: USART register map on page 558

Section 12.4.21: TIM1 register map on page 314

Section 5.5: PWR register map on page 90

Section 18.6.11: I2C register map on page 505

Section 19.6.8: USART register map on page 558

Section 20.5.10: SPI register map on page 611

Section 15.4.5: IWDG register map on page 426

Section 16.6.4: WWDG register map on page 433

Section 17.6.21: RTC register map on page 471

Section 13.4.21: TIMx register map on page 374

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Memory and bus architecture RM0368

40/847

STM32F401xB/C devices feature 64 Kbytes and STM32F401xD/E devices feature

96 Kbytes of system SRAM.

The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).

Read and write operations are performed at CPU speed with 0 wait state.

The CPU can access the embedded SRAM through the System Bus or through the I-

Code/D-Code buses when boot from SRAM is selected or when physical remap is selected

(

Section 7.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)

in the SYSCFG controller). To get the max performance on SRAM execution, physical remap should be selected (boot or software selection).

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. It accelerates code execution with a system of instruction prefetch and cache lines.

The Flash memory is organized as follows:

• A main memory block divided into sectors.

• System memory from which the device boots in System memory boot mode

• 512 OTP (one-time programmable) bytes for user data.

• Option bytes to configure read and write protection, BOR level, watchdog software/hardware and reset when the device is in Standby or Stop mode.

Refer to Section 3: Embedded Flash memory interface

for more details.

The Cortex

-M4 with FPU memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

In the STM32F4xx devices both the peripheral registers and the SRAM are mapped to a bitband region, so that single bit-band write and read operations are allowed. The operations are only available for Cortex

-M4 with FPU accesses, and not from other bus masters (e.g.

DMA).

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + ( byte_offset x 32) + ( bit_number × 4) where:

– bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit

– bit_band_base is the starting address of the alias region

– byte_offset is the number of the byte in the bit-band region that contains the targeted bit

– bit_number is the bit position (0-7) of the targeted bit

RM0368 Rev 5

RM0368 Memory and bus architecture

Example

The following example shows how to map bit 2 of the byte located at SRAM address

0x20000300 to the alias region:

0x22006008 = 0x22000000 + (0x300*32) + (2*4)

Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit

2 of the byte at SRAM address 0x20000300.

Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on bit-banding, please refer to the Cortex manual (see

Related documents on page 1

-M4 with FPU programming

Note:

Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address

0x2000 0000 (accessed through the system bus). The Cortex ® -M4 with FPU CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F4xx microcontrollers implement a special mechanism to be able to boot from other memories (like the internal SRAM).

In the STM32F4xx, three different boot modes can be selected through the BOOT[1:0] pins

as shown in Table 2 .

Table 2. Boot modes

Boot mode selection pins

BOOT1 x

BOOT0

Boot mode Aliasing

Main Flash memory Main Flash memory is selected as the boot space

System memory System memory is selected as the boot space

Embedded SRAM Embedded SRAM is selected as the boot space

The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.

BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been sampled, the corresponding GPIO pin is free and can be used for other purposes.

The BOOT pins are also resampled when the device exits the Standby mode. Consequently, they must be kept in the required Boot mode configuration when the device is in the Standby mode. After this startup delay is over, the CPU fetches the top-of-stack value from address

0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.

When the device boots from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and the offset register.

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Memory and bus architecture RM0368

Embedded bootloader

The embedded bootloader mode is used to reprogram the Flash memory using one of the following serial interfaces:

• USART1 (PA9/PA10)

• USART2 (PD5/PD6)

• I2C1 (PB6/PB7)

• I2C2 (PB10/PB3)

• I2C3 (PA8/PB4)

• SPI1 (PA4/PA5/PA6/PA7)

• SPI2 (PB12/PB13/PB14/PB15)

• SPI3 (PA15/PC10/PC11/PC12)

• USB OTG FS (PA11/12) in Device mode (DFU: device firmware upgrade).

The USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency, while the

USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to 26 MHz).

The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606.

Physical remap in STM32F401xB/C and STM32F401xD/E

Once the boot pins are selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in

place of the System bus). This modification is performed by programming the Section 7.2.1:

SYSCFG memory remap register (SYSCFG_MEMRMP)

in the SYSCFG controller.

The following memories can thus be remapped:

• Main Flash memory

• System memory

• Embedded SRAM1

Table 3. Memory mapping vs. Boot mode/physical remap in STM32F401xB/C

Addresses

Boot/Remap in main

Flash memory

Boot/Remap in embedded SRAM

Boot/Remap in

System memory

0x2000 0000 - 0x2000 FFFF

0x1FFF 0000 - 0x1FFF 77FF

0x0804 0000 - 0x1FFE FFFF

0x0800 0000 - 0x0803 FFFF

0x0400 000 - 0x07FF FFFF

0x0000 0000 - 0x0003 FFFF

(1)

SRAM1 (64 KB)

System memory

Reserved

Flash memory

Reserved

Flash (256 KB) Aliased

SRAM1 (64 KB)

System memory

Reserved

Flash memory

Reserved

SRAM1 (64 KB)

Aliased

SRAM1 (64 KB)

System memory

Reserved

Flash memory

Reserved

System memory

(30 KB) Aliased

1. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space.

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Table 4. Memory mapping vs. Boot mode/physical remap in STM32F401xD/E

Addresses

Boot/Remap in main

Flash memory

Boot/Remap in embedded SRAM

Boot/Remap in

System memory

0x2000 0000 - 0x2001 7FFF

0x1FFF 0000 - 0x1FFF 77FF

0x0804 0000 - 0x1FFE FFFF

0x0800 0000 - 0x0807 FFFF

0x0400 000 - 0x07FF FFFF

0x0000 0000 - 0x0007 FFFF

(1)

SRAM1 (96 KB)

System memory

Reserved

Flash memory

Reserved

Flash (512 KB) Aliased

SRAM1 (96KB)

System memory

Reserved

Flash memory

Reserved

SRAM1 (96 KB)

Aliased

SRAM1 (96KB)

System memory

Reserved

Flash memory

Reserved

System memory

(30 KB) Aliased

1. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space.

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Embedded Flash memory interface

3 Embedded Flash memory interface

RM0368

3.1 Introduction

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms.

The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.

• Flash memory read operations

• Flash memory program/erase operations

• Read / write protections

• Prefetch on I-Code

• 64 cache lines of 128 bits on I-Code

• 8 cache lines of 128 bits on D-Code

Figure 2 shows the Flash memory interface connection inside the system architecture.

Figure 2. Flash memory interface connection inside system architecture

(STM32F401xB/C and STM32F401xD/E)

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3.3

Embedded Flash memory interface

Embedded Flash memory in STM32F401xB/C and

STM32F401xD/E

The Flash memory has the following main features:

• Capacity up to 256 Kbytes for STM32F401xB/C and up to 512 KBytes for

STM32F401xD/E

• 128 bits wide data read

• Byte, half-word, word and double word write

• Sector and mass erase

• Memory organization

The Flash memory is organized as follows:

– A main memory block divided into 4 sectors of 16 KBytes, 1 sector of 64 KBytes, 1 sector of 128 KBytes (STM32F401xB/C) or 3 sectors of 128 Kbytes

(STM32F401xD/E)

– System memory from which the device boots in System memory boot mode

– 512 OTP (one-time programmable) bytes for user data

The OTP area contains 16 additional bytes used to lock the corresponding OTP data block .

– Option bytes to configure read and write protection, BOR level, watchdog software/hardware and reset when the device is in Standby or Stop mode.

• Low-power modes (for details refer to the Power control (PWR) section of the reference manual)

Table 5. Flash module organization (STM32F401xB/C and STM32F401xD/E)

Block Name Block base addresses Size

Main memory

Sector 0

Sector 1

Sector 2

Sector 3

Sector 4

Sector 5

Sector 6

Sector 7

System memory

OTP area

Option bytes

0x0800 0000 - 0x0800 3FFF

0x0800 4000 - 0x0800 7FFF

0x0800 8000 - 0x0800 BFFF

0x0800 C000 - 0x0800 FFFF

0x0801 0000 - 0x0801 FFFF

0x0802 0000 - 0x0803 FFFF

0x0804 0000 - 0x0805 FFFF

0x0806 0000 - 0x0807 FFFF

0x1FFF 0000 - 0x1FFF 77FF

0x1FFF 7800 - 0x1FFF 7A0F

0x1FFF C000 - 0x1FFF C00F

16 Kbytes

64 Kbytes

128 Kbytes

30 Kbytes

528 bytes

16 bytes

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Embedded Flash memory interface RM0368

3.4.1 Relation between CPU clock frequency and Flash memory read time

To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.

The prefetch buffer must be disabled when the supply voltage is below 2.1 V. The

correspondence between wait states and CPU clock frequency is given in Table 6

- when VOS[1:0] = 0x01, the maximum value of f

HCLK

= 60 MHz.

- when VOS[1:0] = 0x10, the maximum value of f

HCLK

= 84 MHz.

Table 6. Number of wait states according to CPU clock (HCLK) frequency

HCLK (MHz)

Wait states (WS)

(LATENCY)

Voltage range

2.7 V - 3.6 V

Voltage range

2.4 V - 2.7 V

Voltage range

2.1 V - 2.4 V

Voltage range

1.71 V - 2.1 V

0 WS (1 CPU cycle)

1 WS (2 CPU cycles)

2 WS (3 CPU cycles)

3 WS (4 CPU cycles)

4 WS (5 CPU cycles)

5 WS (6 CPU cycles)

0 < HCLK ≤ 30

30 < HCLK ≤

60 < HCLK ≤

0 < HCLK ≤ 24

24 < HCLK ≤

48 < HCLK ≤

72 < HCLK ≤

0 < HCLK ≤

18 < HCLK ≤

36 < HCLK ≤

54 < HCLK ≤

72 < HCLK ≤

0 < HCLK ≤

16 <HCLK ≤

32 < HCLK ≤

48 < HCLK ≤ 64

64 < HCLK ≤

80 < HCLK ≤

After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the

FLASH_ACR register.

It is highly recommended to use the following software sequences to tune the number of wait states needed to access the Flash memory with the CPU frequency.

Increasing the CPU frequency

Program the new number of wait states to the LATENCY bits in the FLASH_ACR register

2. Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register

3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register

4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR

5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register.

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Note:

Embedded Flash memory interface

Decreasing the CPU frequency

Modify the CPU clock source by writing the SW bits in the RCC_CFGR register

2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR

3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register

4. Program the new number of wait states to the LATENCY bits in FLASH_ACR

5. Check that the new number of wait states is used to access the Flash memory by reading the FLASH_ACR register

A change in CPU clock configuration or wait state (WS) configuration may not be effective straight away. To make sure that the current CPU clock frequency is the one you have configured, you can check the AHB prescaler factor and clock source status values. To make sure that the number of WS you have programmed is effective, you can read the

FLASH_ACR register.

The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard Arm

Cortex

-M4 with FPU processors. It balances the inherent performance advantage of the Arm

Cortex

-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies.

To release the processor full performance, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the

ART accelerator is equivalent to 0 wait state program execution from Flash memory at a

CPU frequency up to 84 MHz.

Instruction prefetch

Each Flash memory read operation provides 128 bits from either four instructions of 32 bits or 8 instructions of 16 bits according to the program launched. So, in case of sequential code, at least four CPU cycles are needed to execute the previous read instruction line.

Prefetch on the I-Code bus can be used to read the next sequential instruction line from the

Flash memory while the current instruction line is being requested by the CPU. Prefetch is enabled by setting the PRFTEN bit in the FLASH_ACR register. This feature is useful if at least one wait state is needed to access the Flash memory.

Figure 3 shows the execution of sequential 32-bit instructions with and without prefetch

when 3 WSs are needed to access the Flash memory.

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Embedded Flash memory interface

Figure 3. Sequential 32-bit instruction execution

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When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states.

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Note:

Embedded Flash memory interface

Instruction cache memory

To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory. This feature can be enabled by setting the instruction cache enable (ICEN) bit in the FLASH_ACR register. Each time a miss occurs (requested data not present in the currently used instruction line, in the prefetched instruction line or in the instruction cache memory), the line read is copied into the instruction cache memory. If some data contained in the instruction cache memory are requested by the CPU, they are provided without inserting any delay. Once all the instruction cache memory lines have been filled, the LRU

(least recently used) policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops.

Data management

Literal pools are fetched from Flash memory through the D-Code bus during the execution stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB databus D-Code have priority over accesses through the AHB instruction bus I-Code.

If some literal pools are frequently used, the data cache memory can be enabled by setting the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.

Data in user configuration sector are not cacheable.

3.5

3.5.1

Note:

Erase and program operations

For any Flash memory program operation (erase or program), the CPU clock frequency

(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a device reset occurs during a Flash memory operation.

Any attempt to read the Flash memory on STM32F4xx while it is being written or erased, causes the bus to stall. Read operations are processed correctly once the program operation has completed. This means that code or data fetches cannot be performed while a write/erase operation is ongoing.

Unlocking the Flash control register

After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the

Flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock this register:

Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)

2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)

Any wrong sequence will return a bus error and lock up the FLASH_CR register until the next reset.

The FLASH_CR register can be locked again by software by setting the LOCK bit in the

FLASH_CR register.

The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_ SR register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared.

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The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the

Flash memory. PSIZE is limited by the supply voltage and by whether the external V

PP supply is used or not. It must therefore be correctly configured in the FLASH_CR register before any programming/erasing operation.

A Flash memory erase operation can only be performed by sector, or for the whole Flash memory (mass erase). The erase time depends on PSIZE programmed value. For more details on the erase time, refer to the electrical characteristics section of the device datasheet.

Table 7 provides the correct PSIZE values.

Parallelism size

PSIZE(1:0)

Table 7. Program/erase parallelism

Voltage range 2.7 - 3.6 V with External V

Voltage range

2.7 - 3.6 V

Voltage range

2.4 - 2.7 V x64

11 x32

10 x16

Voltage range

2.1 - 2.4 V

Voltage range

1.7 V - 2.1 V x8

Note: Any program or erase operation started with inconsistent program parallelism/voltage range settings may lead to unpredicted results. Even if a subsequent read operation indicates that the logical value was effectively written to the memory, this value may not be retained.

To use V

, an external high-voltage supply (between 8 and 9 V) must be applied to the V

PP pad. The external supply must be able to sustain this voltage range even if the DC consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on the factory line. The V

supply must not be applied for more than an hour, otherwise the

Flash memory might be damaged.

3.5.3 Erase

The Flash memory erase operation can be performed at sector level or on the whole Flash memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration sector.

Sector Erase

To erase a sector, follow the procedure below:

Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register

2. Set the SER bit and select the sector out of the 5 sectors (for STM32F401xB/C) and out of 7 (for STM32F401xD/E) in the main memory block you wish to erase (SNB) in the FLASH_CR register

3. Set the STRT bit in the FLASH_CR register

4. Wait for the BSY bit to be cleared

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Note:

Mass Erase

To perform Mass Erase, the following sequence is recommended:

Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register

2. Set the MER bit in the FLASH_CR register

3. Set the STRT bit in the FLASH_CR register

4. Wait for the BSY bit to be cleared

If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.

If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may occur without generating any error flag. This condition should be forbidden.

3.5.4 Programming

Note:

Standard programming

The Flash memory programming sequence is as follows:

Check that no main Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register.

2. Set the PG bit in the FLASH_CR register

3. Perform the data write operation(s) to the desired memory address (inside main memory block or OTP area):

– Byte access in case of x8 parallelism

– Half-word access in case of x16 parallelism

– Word access in case of x32 parallelism

– Double word access in case of x64 parallelism

4. Wait for the BSY bit to be cleared.

Successive write operations are possible without the need of an erase operation when changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.

If an erase and a program operation are requested simultaneously, the erase operation is performed first.

Programming errors

It is not allowed to program data to the Flash memory that would cross the 128-bit row boundary. In such a case, the write operation is not performed and a program alignment error flag (PGAERR) is set in the FLASH_SR register.

The write access type (byte, half-word, word or double word) must correspond to the type of parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and a program parallelism error flag (PGPERR) is set in the FLASH_SR register.

If the standard programming sequence is not respected (for example, if there is an attempt to write to a Flash memory address when the PG bit is not set), the operation is aborted and a program sequence error flag (PGSERR) is set in the FLASH_SR register.

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Note:

Programming and caches

If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache.

If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution. If this cannot be done safely, it is recommended to flush the caches by setting the

DCRST and ICRST bits in the FLASH_CR register.

The I/D cache should be flushed only when it is disabled (I/DCEN = 0).

3.5.5 Interrupts

Note:

Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables interrupt generation when an erase or program operation ends, that is when the busy bit

(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this case, the end of operation (EOP) bit in the FLASH_SR register is set.

If an error occurs during a program, an erase, or a read operation request, one of the following error flags is set in the FLASH_SR register:

• PGAERR, PGPERR, PGSERR (Program error flags)

• WRPERR (Protection error flag)

In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.

If several successive errors are detected (for example, in case of DMA transfer to the Flash memory), the error flags cannot be cleared until the end of the successive write requests.

Interrupt event

End of operation

Write protection error

Programming error

Table 8. Flash interrupt request

Event flag

EOP

WRPERR

PGAERR, PGPERR, PGSERR

Enable control bit

EOPIE

ERRIE

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The option bytes are configured by the end user depending on the application requirements.

Table 9 shows the organization of these bytes inside the user configuration sector.

Address

0x1FFF C000

0x1FFF C008

Table 9. Option byte organization

[63:16] [15:0]

Reserved

ROP & user option bytes ( RDP & USER )

Write protection nWRP bits for 5 (STM32F401xB/C) and for sectors 0 to 7 (STM32F401xD/E)

RM0368 Rev 5

RM0368 Embedded Flash memory interface

Table 10. Description of the option bytes

Option bytes (word, address 0x1FFF C000)

RDP: Read protection option byte.

The read protection is used to protect the software code stored in Flash memory.

Bit 15:8

0xAA: Level 0, no protection

0xCC: Level 2, chip protection (debug and boot from RAM features disabled)

Others: Level 1, read protection of memories (debug features limited)

USER: User option byte

This byte is used to configure the following features:

Select the watchdog event: Hardware or software

Reset event when entering the Stop mode

Reset event when entering the Standby mode

Bit 7

Bit 6

Bit 5

Bit 4

Bits 3:2

Bits 1:0

Bit 15

Bits 14:6 nRST_STDBY

0: Reset generated when entering the Standby mode

1: No reset generated nRST_STOP

0: Reset generated when entering the Stop mode

1: No reset generated

WDG_SW

0: Hardware watchdog

1: Software watchdog

0x0: Not used.For STM32F401xB/C do not change the default value of this bit which is “0” out of fab.

BOR_LEV: BOR reset Level

These bits contain the supply level threshold that activates/releases the reset.

They can be written to program a new BOR level value into Flash memory.

00: BOR Level 3 (VBOR3), brownout threshold level 3

01: BOR Level 2 (VBOR2), brownout threshold level 2

10: BOR Level 1 (VBOR1), brownout threshold level 1

11: BOR off, POR/PDR reset threshold level is applied

For full details on BOR characteristics, refer to the Electrical characteristics section of the product datasheet.

0x1: Not used

Option bytes (word, address 0x1FFF C008)

SPRMOD: Selection of Protection Mode of nWPRi bits

0: nWPRi bits used for sector i write protection (Default)

1: nWPRi bits used for sector i PCROP protection (Sector)

Reserved

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Table 10. Description of the option bytes (continued) nWRP : Flash memory write protection option bytes

Sectors 0 to 5 (STM32F401xB/C) and Sectors 0 to 7 (STM32F401xD/E) can be write protected.

Bits 5:0 nWRPi

If SPRMOD is reset (default value) :

0: Write protection active on sector i.

1: Write protection not active on sector i.

If SPRMOD is set (active):

0: PCROP protection not active on sector i.

1: PCROP protection active on sector i.

3.6.2

Note:

Programming user option bytes

To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have to perform the following sequence:

Write OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)

2. Write OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)

The user option bytes can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.

Modifying user option bytes

To modify the user option value, follow the sequence below:

Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register

2. Write the desired option value in the FLASH_OPTCR register.

3. Set the option start bit (OPTSTRT) in the FLASH_OPTCR register

4. Wait for the BSY bit to be cleared.

The value of an option is automatically modified by first erasing the user configuration sector and then programming all the option bytes with the values contained in the FLASH_OPTCR register.

The user area in the Flash memory can be protected against read operations by an entrusted code. Three read protection levels are defined:

• Level 0: no read protection

When the read protection level is set to Level 0 by writing 0xAA into the read protection option byte (RDP), all read/write operations (if no write protection is set) from/to the

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Note:

Embedded Flash memory interface

Flash memory are possible in all boot configurations (Flash user boot, debug or boot from RAM).

• Level 1: read protection enabled

It is the default read protection level after option byte erase. The read protection Level

1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and

Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:

– No access (read, erase, program) to Flash memory can be performed while the debug feature is connected or while booting from RAM or system memory bootloader. A bus error is generated in case of read request.

– When booting from Flash memory, accesses (read, erase, program) to Flash memory from user code are allowed.

When Level 1 is active, programming the protection option byte (RDP) to Level 0 causes the Flash memory to be mass-erased. As a result the user code area is cleared before the read protection is removed. The mass erase only erases the user code area.

The other option bytes including write protections remain unchanged from before the mass-erase operation. The OTP area is not affected by mass erase and remains unchanged. Mass erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase.

• Level 2: debug/chip read protection disabled

The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When the read protection Level 2 is set:

– All protections provided by Level 1 are active.

– Booting from RAM or system memory bootloader is no more allowed.

– JTAG, SWV (single-wire viewer), ETM, and boundary scan are disabled.

– User option bytes can no longer be changed.

– When booting from Flash memory, accesses (read, erase and program) to Flash memory from user code are allowed.

Memory read protection Level 2 is an irreversible operation. When Level 2 is activated, the level of protection cannot be decreased to Level 0 or Level 1.

The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a consequence, boundary scan cannot be performed. STMicroelectronics is not able to perform analysis on defective parts on which the Level 2 protection has been set.

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Memory area

Table 11. Access versus read protection level

Protection

Level

Debug features, Boot from RAM or from System memory bootloader

Booting from Flash memory

Read Write Erase Read Write Erase

Main Flash Memory

Option Bytes

OTP

Level 1

Level 2

Level 1

Level 2

Level 1

Level 2

YES

(1)

YES

1. The main Flash memory is only erased when the RDP changes from level 1 to 0. The OTP area remains unchanged.

Figure 4 shows how to go from one RDP level to another.

Figure 4. RDP levels

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56/847

Up to 5 (STM32F401xB/C) or up to 7 (STM32F401xD/E) user sectors in Flash memory can be protected against unwanted write operations due to loss of program counter contexts.

When the non-write protection nWRPi bit (0 ≤ i ≤ 7) in the FLASH_OPTCR registers is low, the corresponding sector cannot be erased or programmed. Consequently, a mass erase cannot be performed if one of the sectors is write-protected.

RM0368 Rev 5

RM0368

Note:

Embedded Flash memory interface

If an erase/program operation to a write-protected part of the Flash memory is attempted

(sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the

FLASH_SR register.

When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory sector i if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM, even if nWRPi = 1.

Write protection error flag

If an erase/program operation to a write protected area of the Flash memory is performed, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.

If an erase operation is requested, the WRPERR bit is set when:

• Mass, bank, sector erase are configured (MER and SER = 1)

• A sector erase is requested and the Sector Number SNB field is not valid

• A mass erase is requested while at least one of the user sector is write protected by option bit (MER = 1 and nWRPi = 0 with 0 ≤ ≤

• A sector erase is requested on a write protected sector. (SER = 1, SNB = i and nWRPi = 0 with 0 ≤ i ≤

• The Flash memory is readout protected and an intrusion is detected.

If a program operation is requested, the WRPERR bit is set when:

• A write operation is performed on system memory or on the reserved part of the user specific sector.

• A write operation is performed to the user configuration sector

• A write operation is performed on a sector write protected by option bit.

• A write operation is requested on an OTP area which is already locked

• The Flash memory is read protected and an intrusion is detected.

Flash memory user sectors (0 to 5 for STM32F401xB/C) or up to 7 for STM32F401xD/E) can be protected against D-bus read accesses by using the proprietary readout protection

(PCROP).

The PCROP protection is selected as follows, through the SPRMOD option bit in the

FLASH_OPTCR register:

• SPRMOD = 0: nWRPi control the write protection of respective user sectors

• SPRMOD = 1: nWRPi control the read and write protection (PCROP) of respective user sectors.

When a sector is readout protected (PCROP mode activated), it can only be accessed for code fetch through ICODE Bus on Flash interface:

• Any read access performed through the D-bus triggers a RDERR flag error.

• Any program/erase operation on a PCROPed sector triggers a WRPERR flag error.

RM0368 Rev 5

57/847

Embedded Flash memory interface

Note:

RM0368

Figure 5. PCROP levels

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The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not respected, the user option byte modification is cancelled and the write error WRPERR flag is set. The modification of the users option bytes (BOR_LEV, RST_STDBY, ..) is allowed since none of the active nWRPi bits is reset and SPRMOD is kept active.

The active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).

If SPRMOD = 1 and nWRPi =1, then user sector i of bank 1, respectively bank 2 is read/write protected (PCROP).

58/847

RM0368 Rev 5

RM0368 Embedded Flash memory interface

Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area.

Block

Lock block

[128:96]

OTP0

OTP1

OTP15

LOCKB15 ...

LOCKB12

Table 12. OTP area organization

[95:64] [63:32] [31:0]

OTP0

OTP1

OTP0

OTP1

OTP0

OTP1

OTP15

LOCKB11 ...

LOCKB8

OTP15

LOCKB7 ...

LOCKB4

OTP15

LOCKB3 ...

LOCKB0

Address byte 0

0x1FFF 7800

0x1FFF 7810

0x1FFF 7820

0x1FFF 7830

0x1FFF 79E0

0x1FFF 79F0

0x1FFF 7A00

The OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16 bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes

LOCKBi (0 i ≤ data block can be programmed until the value 0x00 is programmed in the corresponding

OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP bytes might not be taken into account correctly.

RM0368 Rev 5

59/847

Embedded Flash memory interface RM0368

The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency.

Address offset: 0x00

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Reserved

24 23

Reserved

DCRST ICRST DCEN ICEN PRFTEN

7 rw w rw rw rw

22 21

6 5

Reserved

3 rw

18 17

2 1

LATENCY rw rw

0 rw

Bits 31:13 Reserved, must be kept cleared.

Bit 12 DCRST: Data cache reset

0: Data cache is not reset

1: Data cache is reset

This bit can be written only when the D cache is disabled.

Bit 11 ICRST: Instruction cache reset

0: Instruction cache is not reset

1: Instruction cache is reset

This bit can be written only when the I cache is disabled.

Bit 10 DCEN: Data cache enable

0: Data cache is disabled

1: Data cache is enabled

Bit 9 ICEN: Instruction cache enable

0: Instruction cache is disabled

1: Instruction cache is enabled

Bit 8 PRFTEN: Prefetch enable

0: Prefetch is disabled

1: Prefetch is enabled

Bits 7:4 Reserved, must be kept cleared.

Bits 3:0 LATENCY: Latency

These bits represent the ratio of the CPU clock period to the Flash memory access time.

0000: Zero wait state

0001: One wait state

0010: Two wait states

1110: Fourteen wait states

1111: Fifteen wait states

60/847

RM0368 Rev 5

RM0368 Embedded Flash memory interface

3.8.2

31 w

15 w

Flash key register (FLASH_KEYR)

The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations.

Address offset: 0x04

Reset value: 0x0000 0000

Access: no wait state, word access

30 29 w

14 w w

28 w

27 w

26 w

25 w

24 23

KEY[31:16] w

8 w

7 w

KEY[15:0] w

22 w

21 w

20 w

19 w

18 w

17 w

16 w w w w w w w w w w w w

Bits 31:0 FKEYR[31:0] : FPEC key

The following values must be programmed consecutively to unlock the FLASH_CR register and allow programming/erasing it: a) KEY1 0x45670123 b) KEY2 0xCDEF89AB w

3.8.3

31 w

15 w

Flash option key register (FLASH_OPTKEYR)

The Flash option key register is used to allow program and erase operations in the user configuration sector.

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait state, word access

30 29 w

14 w w

28 w

27 w

26 w

25 w

24 23

OPTKEYR[31:16 w

8 w

OPTKEYR[15:0] w w

22 w

6 w

21 w

20 w

19 w

18 w

17 w

1 w w w w w w w w w w

Bits 31:0 OPTKEYR[31:0] : Option byte key

The following values must be programmed consecutively to unlock the FLASH_OPTCR register and allow programming it:

16 w

0 w

RM0368 Rev 5

61/847

Embedded Flash memory interface RM0368

14 status

The Flash status register gives information on ongoing program and erase operations.

Address offset: 0x0C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

29 28 27 26

13 12

Reserved

11 10

24 23

Reserved

22 21 20

8 7 6 5 4

RDERR PGSERR PGPERR PGAERR WRPERR rw rc_w1 rc_w1 rc_w1 rc_w1

3 2

Reserved

18 17 16

BSY r

0 1

OPERR EOP rc_w1 rc_w1

Bits 31:17 Reserved, must be kept cleared.

Bit 16 BSY: Busy

This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a

Flash memory operation and cleared when the operation finishes or an error occurs.

0: no Flash memory operation ongoing

1: Flash memory operation ongoing

Bits 15:9 Reserved, must be kept cleared.

Bit 8 RDERR: Read Protection Error (pcrop)

Set by hardware when an address to be read through the Dbus belongs to a read protected part of the flash.

Reset by writing 1.

Bit 7 PGSERR: Programming sequence error

Set by hardware when a write access to the Flash memory is performed by the code while the control register has not been correctly configured.

Cleared by writing 1.

Bit 6 PGPERR: Programming parallelism error

Set by hardware when the size of the access (byte, half-word, word, double word) during the program sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, x64).

Cleared by writing 1.

Bit 5 PGAERR: Programming alignment error

Set by hardware when the data to program cannot be contained in the same 128-bit Flash memory row.

Cleared by writing 1.

Bit 4 WRPERR: Write protection error

Set by hardware when an address to be erased/programmed belongs to a write-protected part of the Flash memory.

Cleared by writing 1.

62/847

RM0368 Rev 5

RM0368 Embedded Flash memory interface

Bits 3:2 Reserved, must be kept cleared.

Bit 1 OPERR: Operation error

Set by hardware when a flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1).

Bit 0 EOP: End of operation

Set by hardware when one or more Flash memory operations (program/erase) has/have completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).

Cleared by writing a 1.

3.8.5

LOCK rs

Flash control register (FLASH_CR)

The Flash control register is used to configure and start Flash memory operations.

Address offset: 0x10

Reset value: 0x8000 0000

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

29 28

Reserved

11 13 12

Reserved

25 24

ERRIE EOPIE rw rw

9 8

PSIZE[1:0] rw rw

Res.

6 rw

21 20

Reserved

SNB[3:0]

4 rw rw

3 rw

MER rw

SER rw

Bit 31 LOCK: Lock

Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence.

In the event of an unsuccessful unlock operation, this bit remains set until the next reset.

Bits 30:26 Reserved, must be kept cleared.

Bit 25 ERRIE: Error interrupt enable

This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set to 1.

0: Error interrupt generation disabled

1: Error interrupt generation enabled

Bit 24 EOPIE: End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to

0: Interrupt generation disabled

1: Interrupt generation enabled

Bits 23:17 Reserved, must be kept cleared.

Bit 16 STRT: Start

This bit triggers an erase operation when set. It is set only by software and cleared when the

BSY bit is cleared.

Bits 15:10 Reserved, must be kept cleared.

STRT rs

PG rw

RM0368 Rev 5

63/847

Embedded Flash memory interface

Bits 9:8 PSIZE[1:0]: Program size

These bits select the program parallelism.

00 program x8

01 program x16

10 program x32

11 program x64

Bit 7 Reserved, must be kept cleared.

Bits 6:3 SNB[3:0]: Sector number

These bits select the sector to erase.

0000 sector 0

0001 sector 1

...

0101 sector 5

0110 sector 6 (STM32F401xD/E devices only)

0111 sector 7 (STM32F401xE devices only)

1000 not allowed

...

1011 not allowed

1100 user specific sector

1101 user configuration sector

1110 not allowed

1111 not allowed

Bit 2 MER: Mass Erase

Erase activated for all user sectors.

Bit 1 SER: Sector Erase

Sector Erase activated.

Bit 0 PG: Programming

Flash programming activated.

RM0368

The FLASH_OPTCR register is used to modify the user option bytes.

Address offset: 0x14

Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at reset release.

Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access.

SPR

MOD rw

Reserved

RDP[7:0] rw rw rw rw rw rw

1. Available in STM32F401xD/E devices only

9 rw

8 rw

23 22 nWRP[7:6]

(1) rw

7 nRST_

STDBY rw rw

6 nRST_

STOP rw

21 20 rw

WDG_

SW rw rw

Reserve d

19 18 nWRP[5:0] rw

3 rw

BOR_LEV rw rw

17 16 rw

OPTST

RT rs rw

OPTLO

CK rs

64/847

RM0368 Rev 5

RM0368 Embedded Flash memory interface

Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits

0: PCROP disabled, nWPRi bits used for Write Protection on sector i

1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i

Bits 30:24 Reserved, must be kept cleared.

Bits 23:22 nWRP[7:6]: Not write protect

For STM32F401xB/C:

Reserved, must be kept cleared.

For STM32F401xD/E:

These bits contain the value of the write-protection and read-protection (PCROP) option bytes for sectors 6 and 7 after reset. (Refer to Bits 21:16 for more details)

Bits 21:16 nWRP[5:0]: Not write protect

These bits contain the value of the write-protection option bytes of sectors after reset. They can be written to program a new write protect value into Flash memory.

0: Write protection active on selected sector

1: Write protection not active on selected sector

These bits contain the value of the write-protection and read-protection (PCROP) option bytes for sectors 0 to 5 after reset. They can be written to program a new write-protect or

PCROP value into Flash memory.

If SPRMOD is reset:

0: Write protection active on sector i

1: Write protection not active on sector i

If SPRMOD is set:

0: PCROP protection not active on sector i

1: PCROP protection active on sector i

Bits 15:8 RDP[7:0]: Read protect

These bits contain the value of the read-protection option level after reset. They can be written to program a new read protection value into Flash memory.

0xAA: Level 0, read protection not active

0xCC: Level 2, chip read protection active

Others: Level 1, read protection of memories active

Bits 7:5 USER[2:0]: User option bytes

These bits contain the value of the user option byte after reset. They can be written to program a new user option byte value into Flash memory.

Bit 7: nRST_STDBY

Bit 6: nRST_STOP

Bit 5: WDG_SW

Note: When changing the WDG mode from hardware to software or from software to hardware, a system reset is required to make the change effective.

Bit 4 Reserved, must be kept cleared. Always read as “0”.

RM0368 Rev 5

65/847

Embedded Flash memory interface RM0368

Bits 3:2 BOR_LEV[1:0]: BOR reset Level

These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (V

DD drops below the selected BOR level, a device reset is generated.

)

00: BOR Level 3 (VBOR3), brownout threshold level 3

01: BOR Level 2 (VBOR2), brownout threshold level 2

10: BOR Level 1 (VBOR1), brownout threshold level 1

11: BOR off, POR/PDR reset threshold level is applied

Note: For full details about BOR characteristics, refer to the “Electrical characteristics” section in the device datasheet.

Bit 1 OPTSTRT: Option start

This bit triggers a user option operation when set. It is set only by software and cleared when the BSY bit is cleared.

Bit 0 OPTLOCK: Option lock

Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This bit is cleared by hardware after detecting the unlock sequence.

In the event of an unsuccessful unlock operation, this bit remains set until the next reset.

66/847

RM0368 Rev 5

RM0368 Embedded Flash memory interface

3.8.7 Flash interface register map

Table 13. Flash register map and reset values

Offset Register

0x00

0x04

0x08

FLASH_ACR

Reset value

FLASH_KEYR

Reset value

FLASH_

OPTKEYR

Reset value

Reserved

KEY[31:16]

0 0 0 0 0

Reserved

KEY[15:0]

LATENCY

0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OPTKEYR[31:16] OPTKEYR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0C

FLASH_SR

Reset value

Reserved

0 0 0 0 0 0 0

0x10

FLASH_CR

Reset value 1

Reserved

0 0

Reserved

0 0

SNB[3:0]

0 0 0 0 0 0 0

0x14

FLASH_OPTCR

Reset value 0

Reserved nWRP[7:0] RDP[7:0]

1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1

RM0368 Rev 5

67/847

CRC calculation unit

4 CRC calculation unit

RM0368

4.2

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

– X

+ X

+ X + 1

• Single input/output 32-bit data register

• CRC computation done in 4 AHB clock cycles (HCLK)

• General-purpose 8-bit register (can be used for temporary storage)

The block diagram is shown in

Figure 6 .

Figure 6. CRC calculation unit block diagram

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CRC functional description

The CRC calculation unit mainly consists of a single 32-bit data register, which:

• is used as an input register to enter new data in the CRC calculator (when writing into the register)

• holds the result of the previous CRC calculation (when reading the register)

68/847

RM0368 Rev 5

RM0368 CRC calculation unit

Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte).

The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses.

The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the

CRC_CR register. This operation does not affect the contents of the CRC_IDR register.

The CRC calculation unit contains two data registers and a control register.

The peripheral

The CRC registers have to be accessed by words (32 bits).

4.4.1

31 30

Data register (CRC_DR)

Address offset: 0x00

Reset value: 0xFFFF FFFF

29 28 27 26 25 rw

15 rw rw

14 rw

13 rw

12 rw

11 rw

10 rw

24 23

DR [31:16] rw rw

DR [15:0]

7 rw rw

22 rw

21 rw

20 rw

19 rw

3 rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Data register bits

Used as an input register when writing new data into the CRC calculator.

Holds the previous CRC calculation result when it is read.

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

4.4.2

Independent data register (CRC_IDR)

Address offset: 0x04

Reset value: 0x0000 0000

29 28 27 26 25

13 12 11 10 9

24 23

Reserved

8 7

Reserved rw rw

21 20 19 18 17 16

5 rw

IDR[7:0]

3 rw rw

2 rw

1 rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 General-purpose 8-bit data register bits

Can be used as a temporary storage location for one byte.

This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

0 rw

RM0368 Rev 5

69/847

CRC calculation unit

4.4.3

Control register (CRC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

29 28 27 26 25

13 12 11 10 9

24 23

Reserved

8 7

Reserved

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 RESET bit

Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.

This bit can only be set, it is automatically cleared by hardware.

RM0368

1 0

RESET w

4.4.4 CRC register map

The following table provides the CRC register map and reset values.

Table 14. CRC calculation unit register map and reset values

Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1

Data register

0x00

0x04

0x08

CRC_DR

Reset value

CRC_IDR

Reset value

CRC_CR

Reset value

Reserved

0xFFFF FFFF

Reserved

Independent data register

0x00

RESET

70/847

RM0368 Rev 5

RM0368

5 Power controller (PWR)

Power controller (PWR)

Note:

There are two main power supply schemes:

• VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal regulator disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and PDR_ON pins.

• VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins.

The real-time clock (RTC) and the RTC backup registers can be powered from the V

BAT voltage when the main V

supply is powered off.

Depending on the operating power supply range, some peripheral may be used with limited functionality and performance. For more details refer to section “General operating conditions” in STM32F4xx datasheets.

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Figure 7. Power supply overview

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1. V

DDA

and V

SSA must be connected to V

and V

, respectively.

RM0368 Rev 5

71/847

Power controller (PWR)

5.1.1 Independent A/D converter supply and reference voltage

RM0368

To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.

• The ADC voltage supply input is available on a separate V

DDA

pin.

• An isolated supply ground connection is provided on pin V

SSA

To ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage ADC input on V

REF

. The voltage on V

REF

ranges from 1.7 V to V

DDA

Note:

72/847

Backup domain description

To retain the content of the RTC backup registers and supply the RTC when V

DD off, V

BAT another source.

is turned pin can be connected to an optional standby voltage supplied by a battery or by

To allow the RTC to operate even when the main digital supply (V

DD pin powers the following blocks:

) is turned off, the V

BAT

• The RTC

• The LSE oscillator

• PC13 to PC15 I/Os

The switch to the V

BAT block.

supply is controlled by the power-down reset embedded in the Reset

Warning: During t

RSTTEMPO

(temporization at V

startup) or after a PDR is detected, the power switch between V

BAT connected to V

BAT

During the startup phase, if V

DD and V

remains

is established in less than t

RSTTEMPO

(Refer to the datasheet for the value of t

RSTTEMPO

) and V

> V

BAT through an internal diode connected between V

DD power switch (V

+ 0.6 V, a current may be injected into V

BAT

If the power supply/battery connected to the V

BAT

and the

pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the V

BAT

pin.

If no external battery is used in the application, it is recommended to connect the V

BAT

with a 100 nF external decoupling ceramic capacitor in parallel.

pin to

When the backup domain is supplied by V

DD following functions are available:

(analog switch connected to V

), the

• PC14 and PC15 can be used as either GPIO or LSE pins

• PC13 can be used as a GPIO or additional functions can be configured (refer to

Table 26: RTC additional functions

for more details about this pin configuration)

Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of

PC13 to PC15 GPIOs in output mode is restricted: the speed has to be limited to 2 MHz with

RM0368 Rev 5

RM0368 Power controller (PWR) a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).

When the backup domain is supplied by V

BAT

(analog switch connected to V

is not present), the following functions are available:

BAT

because

• PC14 and PC15 can be used as LSE pins only

•

PC13 can be used as the RTC additional function pin (refer to Table 26: RTC additional functions for more details about this pin configuration)

Backup domain access

After reset, the backup domain (RTC registers and RTC backup register) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:

• Access to the RTC and RTC backup registers

Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR

register (see Section 6.3.11: RCC APB1 peripheral clock enable register

(RCC_APB1ENR) )

2. Set the DBP bit in the Section 5.4.1

to enable access to the backup domain

3. Select the RTC clock source: see Section 7.2.8: RTC/AWU clock

4. Enable the RTC clock by programming the RTCEN [15] bit in the Section 7.3.20: RCC

Backup domain control register (RCC_BDCR)

RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)

which are reset when a tamper detection event occurs. For more details refer to Section 17:

Real-time clock (RTC)

An embedded linear voltage regulator supplies all the digital circuitries except for the backup domain and the Standby circuitry. The regulator output voltage is around 1.2 V.

This voltage regulator requires one or two external capacitors to be connected to one or two dedicated pins, V

CAP_1 either to V

SS the package.

or V

DD and for some packages V

CAP_2

. Specific pins must be connected

to activate or deactivate the voltage regulator. These pins depend on

When activated by software, the voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes.

• In Run mode , the regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can be scaled by software to different voltage values:

Scale 2, or scale 3 can be configured through the VOS[1:0] bits of the PWR_CR register (scale 1 is not used in this product). After reset the VOS register is set to scale 2. When the PLL is OFF, the voltage regulator is set to scale 3 independently

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Note:

RM0368 of the VOS register content. The VOS register content is only taken into account once the PLL is activated and the HSI or HSE is selected as clock source.

The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency.

• In Stop mode, the main regulator or the low-power regulator supplies low power to the

1.2 V domain, thus preserving the content of registers and internal SRAM. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR).

The programmed voltage scale remains the same during Stop mode:

Voltage scale 3 is automatically selected when the microcontroller enters Stop mode (see

Section 5.4.1: PWR power control register (PWR_CR)

• In Standby mode , the regulator is powered down. The content of the registers and

SRAM are lost except for the Standby circuitry and the backup domain.

For more details, refer to the voltage regulator section in the STM32F401xB/C datasheet.

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The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8 V.

To use the device below 1.8 V, the internal power supervisor must be switched off using the

PDR_ON pin (please refer to section Power supply supervisor of the STM32F401xB/C datasheet). The device remains in Reset mode when V

DD threshold, V

POR/PDR

DDA is below a specified

, without the need for an external reset circuit. For more details concerning the power on/power-down reset threshold, refer to the electrical characteristics of the datasheet.

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Figure 8. Power-on reset/power-down reset waveform

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RM0368 Rev 5

RM0368 Power controller (PWR)

Note:

During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V

BOR threshold.

BOR

is configured through device option bytes. By default, BOR is off. 3 programmable

threshold levels can be selected:

• BOR Level 3 (VBOR3). Brownout threshold level 3.

• BOR Level 2 (VBOR2). Brownout threshold level 2.

• BOR Level 1 (VBOR1). Brownout threshold level 1.

For full details about BOR characteristics, refer to the "Electrical characteristics" section in the device datasheet.

When the supply voltage (V

DD generated.

) drops below the selected V

BOR

threshold, a device reset is

The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR or by an external power supervisor if the PDR is switched off through the PDR_ON pin (see

Section 5.2.1: Power-on reset (POR)/power-down reset (PDR) ).

The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the supply voltage).

Figure 9. BOR thresholds

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Power controller (PWR) RM0368

You can use the PVD to monitor the V

power supply by comparing it to a threshold selected by the PLS[2:0] bits in the

PWR power control register (PWR_CR)

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the

PWR power control/status register (PWR_CSR) , to indicate

if V

is higher or lower than the PVD threshold. This event is internally connected to the

EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V

drops below the PVD threshold and/or when

rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.

Figure 10. PVD thresholds

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069

By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The devices feature three low-power modes:

• Sleep mode (Cortex ® -M4 with FPU core stopped, peripherals kept running)

• Stop mode (all clocks are stopped)

• Standby mode (1.2 V domain powered off)

RM0368 Rev 5

RM0368 Power controller (PWR)

In addition, the power consumption in Run mode can be reduce by one of the following means:

• Slowing down the system clocks

• Gating the clocks to the APBx and AHBx peripherals when they are unused.

Entering low-power mode

Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or

WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex ® -M4 with

FPU System Control register is set on Return from ISR.

Entering Low-power mode through WFI or WFE will be executed only if no interrupt is pending or no event is pending.

Exiting low-power mode

The MCU exits from Sleep and Stop modes low-power mode depending on the way the lowpower mode was entered:

• If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.

• If the WFE instruction is used to enter the low-power mode, the MCU exits the lowpower mode as soon as an event occurs. The wakeup event can be generated either by:

– NVIC IRQ interrupt:

When SEVONPEND = 0 in the Cortex

-M4 with FPU System Control register: by enabling an interrupt in the peripheral control register and in the NVIC. When the

MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

When SEVONPEND = 1 in the Cortex ® -M4 with FPU System Control register: by enabling an interrupt in the peripheral control register and optionally in the NVIC.

When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the disabled ones.Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

– Event

This is done by configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.

The MCU exits from Standby low-power mode through an external reset (NRST pin), an

IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see

Figure 159: RTC block diagram

After waking up from Standby mode, program execution restarts in the same way as after a

Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

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Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

Mode name Entry

Table 15. Low-power mode summary

Wakeup

Effect on 1.2 V domain clocks

Effect on

DD domain clocks

Voltage regulator

Sleep

(Sleep now or

Sleep-onexit)

Stop

Standby

WFI or Return from ISR

WFE

Any interrupt

Wakeup event

CPU CLK OFF no effect on other clocks or analog clock sources

None

PDDS bit +

STOP mode configuration +

SLEEPDEEP bit

+ WFI, Return from ISR or WFE

Any EXTI line (configured in the EXTI registers, internal and external lines)

PDDS bit +

SLEEPDEEP bit

+ WFI, Return from ISR or WFE

WKUP pin rising edge,

RTC alarm (Alarm A or

Alarm B), RTC Wakeup event, RTC tamper events, RTC time stamp event, external reset in

NRST pin, IWDG reset

All 1.2 V domain clocks OFF

HSI and

HSE oscillator s OFF

Main regulator or

Low-Power regulator (depends on

PWR power control register

(PWR_CR)

OFF

5.3.2

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 7.3.3: RCC clock configuration register (RCC_CFGR) .

Peripheral clock gating

In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB1 peripheral clock enable register

(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR) (see

Section 7.3.10: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) ,

Section 7.3.11: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) ).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.

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Note:

Entering Sleep mode

The Sleep mode is entered according to

Section : Entering low-power mode

, when the

SLEEPDEEP bit in the Cortex ® -M4 with FPU System Control register is cleared.

Refer to Table 16

and

Table 17 for details on how to enter Sleep mode.

All interrupt pending bits must be cleared before the sleep mode entry.

Exiting Sleep mode

The Sleep mode is exited according to

Section : Exiting low-power mode .

Refer to Table 16

and

Table 17 for more details on how to exit Sleep mode.

Sleep-now mode

Mode entry

Mode exit

Wakeup latency

Table 16. Sleep-now entry and exit

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0, and

– No interrupt (for WFI) or event (for WFE) is pending.

Refer to the Cortex ® -M4 with FPU System Control register.

On Return from ISR while:

– SLEEPDEEP = 0 and

– SLEEPONEXIT = 1,

– No interrupt is pending.

Refer to the Cortex

-M4 with FPU System Control register.

If WFI or Return from ISR was used for entry:

Interrupt: Refer to Table 38: Vector table for

STM32F401xB/CSTM32F401xD/E

If WFE was used for entry and SEVONPEND = 0

Wakeup event: Refer to

Section 10.2.3: Wakeup event management

f WFE was used for entry and SEVONPEND = 1

Interrupt even when disabled in NVIC: refer to Table 38: Vector table for

STM32F401xB/CSTM32F401xD/E

or Wakeup event (see

Section 10.2.3: Wakeup event management ).

None

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Power controller (PWR)

Sleep-on-exit

Mode entry

Mode exit

Wakeup latency

Table 17. Sleep-on-exit entry and exit

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0, and

– No interrupt (for WFI) or event (for WFE) is pending.

Refer to the Cortex ® -M4 with FPU System Control register.

On Return from ISR while:

– SLEEPDEEP = 0, and

– SLEEPONEXIT = 1, and

– No interrupt is pending.

Refer to the Cortex

-M4 with FPU System Control register.

Interrupt: refer to Table 38: Vector table for

STM32F401xB/CSTM32F401xD/E

None

RM0368

The Stop mode is based on the Cortex

-M4 with FPU deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or lowpower mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.

Some settings in the PWR_CR register allow to further reduce the power consumption.

When the Flash memory is in power-down mode, an additional startup delay is incurred when waking up from Stop mode (see

Table 18: Stop operating modes and

Section 5.4.1:

PWR power control register (PWR_CR)

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RM0368 Power controller (PWR)

Stop mode

STOP MR

STOP MRFPD

STOP LP

STOP LPFPD

STOP MRLV

STOP LPLV

Table 18. Stop operating modes

MRLV bit LPLV bit FPDS bit LPDS bit

0 0 0

Wakeup latency

HSI RC startup time

HSI RC startup time +

Flash wakeup time from Deep

Power Down mode

HSI RC startup time + regulator wakeup time from LP mode

HSI RC startup time +

Flash wakeup time from Deep

Power Down mode + regulator wakeup time from LP mode

HSI RC startup time +

Flash wakeup time from Deep

Power Down mode +

Main regulator from low voltage mode

HSI RC startup time +

Flash wakeup time from Deep

Power Down mode + regulator wakeup time from Low

Voltage LP mode

Entering Stop mode

The Stop mode is entered according to

Section : Entering low-power mode

, when the

SLEEPDEEP bit in the Cortex ® -M4 with FPU System Control register is set.

Refer to Table 19

for details on how to enter the Stop mode.

To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit

of the PWR power control register

(PWR_CR) .

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.

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In Stop mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See

Section 15.3

in Section 15: Independent watchdog (IWDG)

• Real-time clock (RTC): this is configured by the RTCEN bit in the Section 7.3.20: RCC

Backup domain control register (RCC_BDCR)

• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the

Section 7.3.21: RCC clock control & status register (RCC_CSR) .

• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

Section 7.3.20: RCC Backup domain control register (RCC_BDCR) .

The ADC can also consume power during the Stop mode, unless it is disabled before entering it. To disable it, the ADON bit in the ADC_CR2 register must be written to 0.

If the application needs to disable the external clock before entering Stop mode, the HSEON bit must first be disabled and the system clock switched to HSI.

Otherwise, if the HSEON bit is kept enabled while the external clock (external oscillator) can be removed before entering stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering stop mode.

Exiting Stop mode

The Stop mode is exited according to

Section : Exiting low-power mode .

Refer to Table 19

for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

Stop mode

Mode entry

Table 19. Stop mode entry and exit

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– No interrupt (for WFI) or event (for WFE) is pending,

– SLEEPDEEP bit is set in Cortex

-M4 with FPU System Control register,

– PDDS bit is cleared in Power Control register (PWR_CR),

– Select the voltage regulator mode by configuring LPDS bit in PWR_CR.

On Return from ISR:

– No interrupt is pending,

– SLEEPDEEP bit is set in Cortex

-M4 with FPU System Control register,

– SLEEPONEXIT = 1,

– PDDS bit is cleared in Power Control register (PWR_CR).

Note: To enter Stop mode, all EXTI Line pending bits (in

Pending register

(EXTI_PR) ), all peripheral interrupts pending bits, the RTC Alarm

(Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time stamp flags, must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues.

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Stop mode

Mode exit

Wakeup latency

Table 19. Stop mode entry and exit (continued)

Description

If WFI or Return from ISR was used for entry:

Any EXTI lines configured in Interrupt mode (the corresponding EXTI

Interrupt vector must be enabled in the NVIC). The interrupt source can

be external interrupts or peripherals with wakeup capability. Refer to

Table 38: Vector table for STM32F401xB/CSTM32F401xD/E .

If WFE was used for entry and SEVONPEND = 0

Any EXTI lines configured in event mode. Refer to

Section 10.2.3:

Wakeup event management on page 206 .

If WFE was used for entry and SEVONPEND = 1:

– Any EXTI lines configured in Interrupt mode (even if the corresponding

EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be an external interrupt or a peripheral with wakeup capability. Refer to

Table 38: Vector table for STM32F401xB/CSTM32F401xD/E .

– Wakeup event: refer to Section 10.2.3: Wakeup event management on page 206 .

Table 18: Stop operating modes

The Standby mode allows to achieve the lowest power consumption. It is based on the

Cortex

-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the backup domain (RTC registers and RTC backup register), and Standby circuitry (see

Figure 7 ).

Entering Standby mode

The Standby mode is entered according to

Section : Entering low-power mode

, when the

SLEEPDEEP bit in the Cortex

-M4 with FPU System Control register is set.

Refer to Table 20

for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See

Section 15.3

in Section 15: Independent watchdog (IWDG)

• Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain control register (RCC_BDCR)

• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).

• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the backup domain control register (RCC_BDCR)

Exiting Standby mode

The Standby mode is exited according to

Section : Exiting low-power mode

. The SBF status flag in PWR_CR (see

Section 5.4.2: PWR power control/status register (PWR_CSR) )

indicates that the MCU was in Standby mode. All registers are reset after wakeup from

Standby except for PWR_CR.

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5.3.6

RM0368

Refer to Table 20

for more details on how to exit Standby mode.

Standby mode

Mode entry

Mode exit

Wakeup latency

Table 20. Standby mode entry and exit

Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP is set in Cortex

-M4 with FPU System Control register,

– PDDS bit is set in Power Control register (PWR_CR),

– No interrupt (for WFI) or event (for WFE) is pending,

– WUF bit is cleared in Power Control register (PWR_CR),

– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,

RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared

On return from ISR while:

– SLEEPDEEP bit is set in Cortex

-M4 with FPU System Control register, and

– SLEEPONEXIT = 1, and

– PDDS bit is set in Power Control register (PWR_CR), and

– No interrupt is pending,

– WUF bit is cleared in Power Control/Status register (PWR_SR),

– The RTC flag corresponding to the chosen wakeup source (RTC Alarm

A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared.

WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.

Reset phase.

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:

• Reset pad (still available)

• RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out

• WKUP pin (PA0), if enabled

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex ® -M4 with

FPU core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to

Section 23.16.1: Debug support for low-power modes

Programming the RTC alternate functions to wake up the device from the Stop and Standby modes

The MCU can be woken up from a low-power mode by an RTC alternate function.

The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection.

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These RTC alternate functions can wake up the system from the Stop and Standby lowpower modes.

The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.

The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.

For this purpose, two of the three alternate RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Section 7.3.20: RCC Backup domain control register (RCC_BDCR) :

• Low-power 32.768 kHz external crystal oscillator (LSE OSC)

This clock source provides a precise time base with a very low-power consumption

(additional consumption of less than 1 µA under typical conditions)

• Low-power internal RC oscillator (LSI RC)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC oscillator is designed to use minimum power.

RTC alternate functions to wake up the device from the Stop mode

• To wake up the device from the Stop mode with an RTC alarm event, it is necessary to: a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC Alarm Interrupt in the RTC_CR register c) Configure the RTC to generate the RTC alarm

• To wake up the device from the Stop mode with an RTC tamper or time stamp event, it is necessary to: a) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register c) Configure the RTC to detect the tamper or time stamp event

• To wake up the device from the Stop mode with an RTC wakeup event, it is necessary to: a) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC wakeup interrupt in the RTC_CR register c) Configure the RTC to generate the RTC Wakeup event

RTC alternate functions to wake up the device from the Standby mode

• To wake up the device from the Standby mode with an RTC alarm event, it is necessary to: a) Enable the RTC alarm interrupt in the RTC_CR register b) Configure the RTC to generate the RTC alarm

• To wake up the device from the Standby mode with an RTC tamper or time stamp event, it is necessary to: a) Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register

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Power controller (PWR) RM0368 b) Configure the RTC to detect the tamper or time stamp event

• To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to: a) Enable the RTC wakeup interrupt in the RTC_CR register b) Configure the RTC to generate the RTC wakeup event

Safe RTC alternate function wakeup flag clearing sequence

If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared, it will not be detected on the next event as detection is made once on the rising edge.

To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit correctly from the Stop and Standby modes, it is recommended to follow the sequence below before entering the Standby mode:

• When using RTC alarm to wake up the device from the low-power modes: a) Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register) b) Clear the RTC alarm (ALRAF/ALRBF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC alarm interrupt e) Re-enter the low-power mode

• When using RTC wakeup to wake up the device from the low-power modes: a) Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register) b) Clear the RTC Wakeup (WUTF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC Wakeup interrupt e) Re-enter the low-power mode

• When using RTC tamper to wake up the device from the low-power modes: a) Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register) b) Clear the Tamper (TAMP1F/TSF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC tamper interrupt e) Re-enter the low-power mode

• When using RTC time stamp to wake up the device from the low-power modes: a) Disable the RTC time stamp interrupt (TSIE bit in RTC_CR) b) Clear the RTC time stamp (TSF) flag c) Clear the PWR Wakeup (WUF) flag d) Enable the RTC TimeStamp interrupt e) Re-enter the low-power mode

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RM0368 Power controller (PWR)

5.4.1 PWR power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 8000 (reset by wakeup from Standby mode)

31 30 29

VOS

14 rw rw

ADCDC1 rw

Res

27 26 25

MRLV

DS rw

LPLV

DS rw

FPDS rw

24 23

Reserved

DBP

7 rw rw

PLS[2:0] rw

5 rw

20 19 18 17 16

4 3 2 1 0

PVDE CSBF CWUF PDDS LPDS rw w w rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 VOS[1:0] : Regulator voltage scaling output selection

These bits control the main internal voltage regulator output voltage to achieve a trade-off between performance and power consumption when the device does not operate at the maximum frequency (refer to the corresponding datasheet for more details).

These bits can be modified only when the PLL is OFF. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage regulator is set to scale 3 independently of the VOS register content.

00: Reserved (Scale 3 mode selected)

01: Scale 3 mode

10: Scale 2 mode

11: Reserved (Scale 2 mode selected)

Bit 13 ADCDC1 :

0: No effect.

1: Refer to AN4073 for details on how to use this bit.

Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when the Prefetch is OFF.

Bit 12 Reserved, must be kept at reset value.

Bit 11 MRLVDS : Main regulator Low Voltage in Deep Sleep

0: Main regulator in Voltage scale 3 when the device is in Stop mode.

1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode.

Bit 10 LPLVDS : Low-power regulator Low Voltage in Deep Sleep

0: Low-power regulator on if LPDS bit is set when the device is in Stop mode.

1: Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is set when device is in Stop mode.

Bit 9 FPDS : Flash power-down in Stop mode

When set, the Flash memory enters power-down mode when the device enters Stop mode.

This allows to achieve a lower consumption in stop mode but a longer restart time.

0: Flash memory not in power-down when the device is in Stop mode

1: Flash memory in power-down when the device is in Stop mode

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Power controller (PWR) RM0368

Bit 8 DBP : Disable backup domain write protection

In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This bit must be set to enable write access to these registers.

0: Access to RTC and RTC Backup registers.

1: Access to RTC and RTC Backup registers.

Bits 7:5 PLS[2:0]: PVD level selection

These bits are written by software to select the voltage threshold detected by the Power

Voltage Detector

000: 2.2 V

001: 2.3 V

010: 2.4 V

011: 2.5 V

100: 2.6 V

101: 2.7 V

110: 2.8 V

111: 2.9 V

Note: Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE: Power voltage detector enable

This bit is set and cleared by software.

0: PVD disabled

1: PVD enabled

Bit 3 CSBF : Clear standby flag

This bit is always read as 0.

0: No effect.

1: Clear the SBF Standby Flag (write).

Bit 2 CWUF: Clear wakeup flag

This bit is always read as 0.

0: No effect.

1: Clear the WUF Wakeup Flag after 2 System clock cycles.

Bit 1 PDDS : Power-down deepsleep

This bit is set and cleared by software. It works together with the LPDS bit.

0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the

LPDS bit.

1: Enter Standby mode when the CPU enters deepsleep.

Bit 0 LPDS: Low-power deepsleep

This bit is set and cleared by software. It works together with the PDDS bit.

0: Voltage regulator on during Stop mode.

1: Low-power Voltage regulator on during Stop mode.

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RM0368 Rev 5

RM0368 Power controller (PWR)

5.4.2

Res

PWR power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

30 29

VOS

RDY r

Reserved

24 23

Reserved

BRE EWUP

7 rw rw

Reserved

19 18 17

3 2

BRR PVDO r r

SBF r

WUF r

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 VOSRDY : Regulator voltage scaling output selection ready bit

0: Not ready

1: Ready

Bits 13:10 Reserved, must be kept at reset value.

Bit 9 BRE : Backup regulator enable

When set, the Backup regulator (used to maintain the backup domain content) is enabled. If

BRE is reset, the backup regulator is switched off. Once set, the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the backup registers will be maintained in the Standby and V

BAT

0: Backup regulator disabled

modes.

1: Backup regulator enabled

Note: This bit is not reset when the device wakes up from Standby mode, by a system reset, or by a power reset.

Bit 8 EWUP : Enable WKUP pin

This bit is set and cleared by software.

0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode.

1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 BRR : Backup regulator ready

Set by hardware to indicate that the Backup Regulator is ready.

0: Backup Regulator not ready

1: Backup Regulator ready

Note: This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.

Bit 2 PVDO: PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

0: V

is higher than the PVD threshold selected with the PLS[2:0] bits.

1: V

is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after

Standby or reset until the PVDE bit is set.

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Power controller (PWR)

5.5

RM0368

Bit 1 SBF: Standby flag

This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR_CR register.

0: Device has not been in Standby mode

1: Device has been in Standby mode

Bit 0 WUF: Wakeup flag

This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in the PWR_CR register.

0: No wakeup event occurred

1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or

Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).

Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the

EWUP bit) when the WKUP pin level is already high.

PWR register map

The following table summarizes the PWR registers.

Table 21. PWR - register map and reset values

Offset Register

0x000

0x004

PWR_CR

Reset value

Reserved

1 1 0

PLS[2:0]

0 0 0 0 0 0 0 0 0 0 0 0

PWR_CSR

Reserved Reserved

Reset value 0

Refer to Table 3 on page 42

for the register boundary addresses.

0 0

Reserved

0 0 0 0

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RM0368

6

Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

6.1 Reset

There are three types of reset, defined as system Reset, power Reset and backup domain

Reset.

A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain.

A system reset is generated when one of the following events occurs:

A low level on the NRST pin (external reset)

2. Window watchdog end of count condition (WWDG reset)

3. Independent watchdog end of count condition (IWDG reset)

4. A software reset (SW reset) (see Software reset )

5. Low-power management reset (see

Low-power management reset

)

Software reset

The reset source can be identified by checking the reset flags in the RCC clock control & status register (RCC_CSR)

The SYSRESETREQ bit in Cortex

-M4 with FPU Application Interrupt and Reset Control

-M4 with

FPU technical reference manual for more details.

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Low-power management reset

There are two ways of generating a low-power management reset:

Reset generated when entering the Standby mode:

This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.

In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering the Standby mode.

2. Reset when entering the Stop mode:

This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.

In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode.

For further information on the user option bytes, refer to the STM32F401xB/C and

STM32F401xD/E Flash programming manual available from your ST sales office.

A power reset is generated when one of the following events occurs:

Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset

2. When exiting the Standby mode

A power reset sets all registers to their reset values except the Backup domain.

These sources act on the NRST pin and it is always kept low during the delay phase. The

RESET service routine vector is fixed at address 0x0000_0004 in the memory map.

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

Figure 11. Simplified diagram of the reset circuit

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RM0368 Rev 5

RM0368 Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values.

A backup domain reset is generated when one of the following events occurs:

Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR)

2. V

or V

BAT

power on, if both supplies have previously been powered off.

6.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

• HSI oscillator clock

• HSE oscillator clock

• Main PLL (PLL) clock

The devices have the two following secondary clock sources:

• 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.

• 32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC clock (RTCCLK)

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

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Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

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1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet.

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RM0368 Rev 5

RM0368 Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like USB

OTG FS, I2S and SDIO.

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is

84 MHz. The maximum allowed frequency of the high-speed APB2 domain is 84 MHz. The maximum allowed frequency of the low-speed APB1 domain is 42 MHz

All peripheral clocks are derived from the system clock (SYSCLK) except for:

• The USB OTG FS clock (48 MHz) and the SDIO clock ( ≤ 48 MHz) which are coming from a specific output of PLL (PLL48CLK)

• The I2S clock

To achieve high-quality audio performance, the I2S clock can be derived either from a specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For

more information about I2S clock frequency and precision, refer to Section 20.4.4:

Clock generator .

The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock

(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock

(HCLK), configurable in the SysTick control and status register.

The timer clock frequencies for STM32F401xB/C and STM32F401xD/E are automatically set by hardware. There are two cases:

If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.

2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected.

The timer clock frequencies are automatically set by hardware. There are two cases depending on the value of TIMPRE bit in RCC_DCKCFGR register:

• If TIMPRE bit is reset:

If the APB prescaler is configured to a division factor of 1, the timer clock frequencies

(TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies are twice the frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.

• If TIMPRE bit is set:

If the APB prescaler is configured to a division factor of 1 or 2, the timer clock frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four times the frequency of the APB domain to which the timers are connected: TIMxCLK =

4xPCLKx.

FCLK acts as Cortex

-M4 with FPU free-running clock. For more details, refer to the

Cortex

-M4 with FPU technical reference manual.

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The high speed external clock signal (HSE) can be generated from two possible clock sources:

• HSE external crystal/ceramic resonator

• HSE external user clock

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Figure 13. HSE/ LSE clock sources

Hardware configuration

External clock

External source

OSC_OUT

(HI-Z)

OSC_IN OSC_OUT

Crystal/ceramic resonators

Load capacitors

External source (HSE bypass)

In this mode, an external clock source must be provided. You select this mode by setting the

HSEBYP and HSEON

bits in the RCC clock control register (RCC_CR) . The external clock

signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the

OSC_OUT pin should be left HI-Z. See Figure 13 .

External crystal/ceramic resonator (HSE crystal)

The HSE has the advantage of producing a very accurate rate on the main clock.

The associated hardware configuration is shown in

Figure 13

. Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag in the

RCC clock control register (RCC_CR)

indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by

hardware. An interrupt can be generated if enabled in the RCC clock interrupt register

(RCC_CIR) .

The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control register (RCC_CR) .

RM0368 Rev 5

RM0368 Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used directly as a system clock, or used as PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T

= 25 °C.

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the

RCC clock control register (RCC_CR) .

If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the

RCC clock control register (RCC_CR) .

The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is

stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the

RCC clock control register (RCC_CR) .

The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to

Section 6.2.7: Clock security system (CSS) on page 99 .

The STM32F401xB/C and STM32F401xD/E devices feature two PLLs:

• A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different output clocks:

– The first output is used to generate the high speed system clock (up to 84 MHz)

– The second output is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator ( ≤ 48 MHz) and the SDIO ( 48 MHz).

• A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality audio performance on the I2S interface.

Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as

PLL clock source, and configuration of division factors M, P, Q and multiplication factor N).

The PLLI2S uses the same input clock as the main PLL (PLLM[5:0] and PLLSRC bits are common to both PLLs). However, the PLLI2S has dedicated enable/disable and division

factors configuration bits. Refer to Section 6.3.1: RCC clock control register (RCC_CR) ,

Section 6.3.2: RCC PLL configuration register (RCC_PLLCFGR)

and

Section 6.3.20: RCC

PLLI2S configuration register (RCC_PLLI2SCFGR) . Once the PLLI2S is enabled, the

configuration parameters cannot be changed.

The two PLLs are disabled by hardware when entering Stop and Standby modes, or when

an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC

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PLL configuration register (RCC_PLLCFGR)

and RCC clock configuration register

(RCC_CFGR)

can be used to configure PLL and PLLI2S, respectively.

RM0368

The LSE clock is generated using a 32.768kHz low speed external crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The LSE oscillator is switched on and off using the LSEON bit in

RCC Backup domain control register (RCC_BDCR) .

The LSERDY flag in the RCC Backup domain control register (RCC_BDCR)

indicates if the

LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the

RCC clock interrupt register (RCC_CIR) .

External source (LSE bypass)

In this mode, an external clock source must be provided. It must have a frequency up to

1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the

RCC Backup domain control register (RCC_BDCR) . The external clock signal (square, sinus or triangle)

with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be

left HI-Z. See Figure 13 .

6.2.6

The LSI RC acts as an low-power clock source that can be kept running in Stop and

Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the

RCC clock control & status register (RCC_CSR)

The LSIRDY flag in the

RCC clock control & status register (RCC_CSR) indicates if the low-

speed internal oscillator is stable or not. At startup, the clock is not released until this bit is

set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register

(RCC_CIR) .

System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as the system clock. When a clock source is used directly or through PLL as the system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready

(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is

selected, the switch occurs when the clock source is ready. Status bits in the RCC clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently

used as the system clock.

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RM0368

6.2.7

Note:

Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock failure event is sent to the break inputs of advanced-control timer TIM1, and an interrupt is generated to inform the software about the failure (clock security system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex

-M4 with

FPU NMI (non-maskable interrupt) exception vector.

When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt, which causes the automatic generation of an NMI. The NMI is executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the

CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register

(RCC_CIR).

If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.

If the HSE oscillator clock was the clock source of PLL used as the system clock when the failure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also disabled when the HSE fails.

Once the RTCCLK clock source has been selected, the only possible way of modifying the selection is to reset the power domain.

The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits in the

RCC Backup domain control register (RCC_BDCR)

and the RTCPRE[4:0] bits in

RCC clock configuration register (RCC_CFGR) . This selection cannot be modified without

resetting the Backup domain.

If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not guaranteed if the system supply disappears. If the HSE oscillator divided by a value between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup or the system supply disappears.

The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a consequence:

• If LSE is selected as the RTC clock:

– The RTC continues to work even if the V

BAT

supply is maintained.

supply is switched off, provided the

• If LSI is selected as the Auto-wakeup unit (AWU) clock:

– The AWU state is not guaranteed if the V

supply is powered off. Refer to

Section 6.2.5: LSI clock on page 98

for more details on LSI calibration.

• If the HSE clock is used as the RTC clock:

– The RTC state is not guaranteed if the V

supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.2 V domain).

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Note:

RM0368

To read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (f

APB1

< 7xf

RTCLCK

), the software must read the calendar time and date registers twice. The data are correct if the second read access to RTC_TR gives the same result than the first one. Otherwise a third read access must be performed.

If the independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

Two microcontroller clock output (MCO) pins are available:

• MCO1

You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5):

– HSI clock

– LSE clock

– HSE clock

– PLL clock

The desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in the

RCC clock configuration register (RCC_CFGR)

• MCO2

You can output four different clock sources onto the MCO2 pin (PC9) using the configurable prescaler (from 1 to 5):

– HSE clock

– PLL clock

– System clock (SYSCLK)

– PLLI2S clock

The desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the

RCC clock configuration register (RCC_CFGR)

For the different MCO pins, the corresponding GPIO port has to be programmed in alternate function mode.

The selected clock to output onto MCO must not exceed 100 MHz (the maximum I/O speed).

100/847

It is possible to indirectly measure the frequencies of all on-board clock source generators by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in

Figure 14

and Figure 15

Internal/external clock measurement using TIM5 channel4

TIM5 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits in the TIM5_OR register.

RM0368 Rev 5

RM0368 Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

The primary purpose of having the LSE connected to the channel4 input capture is to be able to precisely measure the HSI (this requires to have the HSI used as the system clock source). The number of HSI clock counts between consecutive edges of the LSE signal provides a measurement of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltage-related frequency deviations.

The HSI oscillator has dedicated, user-accessible calibration bits for this purpose.

The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement.

It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal. The ultralow-power LSI oscillator has a large manufacturing process deviation: by measuring it versus the HSI clock source, it is possible to determine its frequency with the precision of the HSI. The measured value can be used to have more accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an

IWDG timeout with an acceptable accuracy.

Use the following procedure to measure the LSI frequency:

Enable the TIM5 timer and configure channel4 in Input capture mode.

2. Set the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI clock internally to TIM5 channel4 input capture for calibration purposes.

3. Measure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.

4. Use the measured LSI frequency to update the prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout.

Figure 14. Frequency measurement with TIM5 in Input capture mode

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Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E RM0368

Internal/external clock measurement using TIM11 channel1

TIM11 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in the TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is connected to channel 1 input capture to have a rough indication of the external crystal frequency. This requires that the HSI is the system clock source. This can be useful for instance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be able to determine harmonic or subharmonic frequencies (–50/+100% deviations).

Figure 15. Frequency measurement with TIM11 in Input capture mode

4)-

'0)/

4)?2-0;=

(3%?24#-(Z

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Refer to Section 1.1: List of abbreviations for registers

for a list of abbreviations used in register descriptions.

15 r

Address offset: 0x00

Reset value: 0x0000 XX81 where X is undefined.

Access: no wait state, word, half-word and byte access

30 29

Reserved

14 13

PLLI2S

RDY r

HSICAL[7:0]

26 25 24

PLLI2S

PLLRDY PLLON rw r rw

10 9 8 r r r r r

22 21

Reserved

6 5

HSITRIM[4:0]

4 rw rw rw

CSS

ON rw

HSE

BYP rw

2 rw

Res.

HSE

RDY r

HSI

RDY r

HSE ON rw

HSION rw r r rw

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 PLLI2SRDY : PLLI2S clock ready flag

Set by hardware to indicate that the PLLI2S is locked.

0: PLLI2S unlocked

1: PLLI2S locked

Bit 26 PLLI2SON : PLLI2S enable

Set and cleared by software to enable PLLI2S.

Cleared by hardware when entering Stop or Standby mode.

0: PLLI2S OFF

1: PLLI2S ON

Bit 25 PLLRDY : Main PLL (PLL) clock ready flag

Set by hardware to indicate that PLL is locked.

0: PLL unlocked

1: PLL locked

Bit 24 PLLON : Main PLL (PLL) enable

Set and cleared by software to enable PLL.

Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL clock is used as the system clock.

0: PLL OFF

1: PLL ON

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 CSSON : Clock security system enable

Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure is detected.

0: Clock security system OFF (Clock detector OFF)

1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)

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Bit 18 HSEBYP : HSE clock bypass

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device.

The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: HSE oscillator not bypassed

1: HSE oscillator bypassed with an external clock

Bit 17 HSERDY : HSE clock ready flag

Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared,

HSERDY goes low after 6 HSE oscillator clock cycles.

0: HSE oscillator not ready

1: HSE oscillator ready

Bit 16 HSEON : HSE clock enable

Set and cleared by software.

Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.

0: HSE oscillator OFF

1: HSE oscillator ON

Bits 15:8 HSICAL[7:0] : Internal high-speed clock calibration

These bits are initialized automatically at startup.

Bits 7:3 HSITRIM[4:0] : Internal high-speed clock trimming

These bits provide an additional user-programmable trimming value that is added to the

HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.

Bit 2 Reserved, must be kept at reset value.

Bit 1 HSIRDY : Internal high-speed clock ready flag

Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared,

HSIRDY goes low after 6 HSI clock cycles.

0: HSI oscillator not ready

1: HSI oscillator ready

Bit 0 HSION : Internal high-speed clock enable

Set and cleared by software.

Set by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in case of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit cannot be cleared if the HSI is used directly or indirectly as the system clock.

0: HSI oscillator OFF

1: HSI oscillator ON

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6.3.2

Reserv ed

RCC PLL configuration register (RCC_PLLCFGR)

Address offset: 0x04

Reset value: 0x2400 3010

Access: no wait state, word, half-word and byte access.

This register is used to configure the PLL clock outputs according to the formulas:

• f

(VCO clock)

= f

(PLL clock input)

× (PLLN / PLLM)

• f

(PLL general clock output)

= f

(VCO clock)

/ PLLP

• f

(USB OTG FS, SDIO, RNG clock output)

= f

(VCO clock)

/ PLLQ

29 28

Reserved

14 rw

13 rw

12 rw

27 26

PLLN

25 24 23

PLLQ3 PLLQ2 PLLQ1 PLLQ0 Reserv rw rw rw rw ed

11 9 8 7 rw rw rw rw rw

PLLSRC rw

21 20 19

Reserved

18 17

PLLP1 rw

PLLP0 rw

5 4 3 2 1 0

PLLM5 PLLM4 PLLM3 PLLM2 PLLM1 PLLM0 rw rw rw rw rw rw rw

Bit 31:28 Reserved, must be kept at reset value.

Bits 27:24 PLLQ: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

Set and cleared by software to control the frequency of USB OTG FS clock, the random number generator clock and the SDIO clock. These bits should be written only if PLL is disabled.

Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the random number generator need a frequency lower than or equal to 48 MHz to work correctly.

USB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15

0000: PLLQ = 0, wrong configuration

0001: PLLQ = 1, wrong configuration

0010: PLLQ = 2

0011: PLLQ = 3

0100: PLLQ = 4

...

1111: PLLQ = 15

Bit 23 Reserved, must be kept at reset value.

Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written only when PLL and PLLI2S are disabled.

0: HSI clock selected as PLL and PLLI2S clock entry

1: HSE oscillator clock selected as PLL and PLLI2S clock entry

Bits 21:18 Reserved, must be kept at reset value.

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Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock

Set and cleared by software to control the frequency of the general PLL output clock. These bits can be written only if PLL is disabled.

Caution: The software has to set these bits correctly not to exceed 84 MHz on this domain.

PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8

00: PLLP = 2

01: PLLP = 4

10: PLLP = 6

11: PLLP = 8

Bits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when PLL is disabled. Only half-word and word accesses are allowed to write these bits.

Caution: The software has to set these bits correctly to ensure that the VCO output

frequency is between 192 and 432 MHz. (check also Section 6.3.20: RCC PLLI2S configuration register (RCC_PLLI2SCFGR) )

VCO output frequency = VCO input frequency × PLLN with 192 PLLN 432

000000000: PLLN = 0, wrong configuration

000000001: PLLN = 1, wrong configuration

...

110110000: PLLN = 432

110110001: PLLN = 433, wrong configuration

...

111111111: PLLN = 511, wrong configuration

Bits 5:0 PLLM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.

These bits can be written only when the PLL and PLLI2S are disabled.

Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit

PLL jitter.

VCO input frequency = PLL input clock frequency / PLLM with 2 PLLM 63

000000: PLLM = 0, wrong configuration

000001: PLLM = 1, wrong configuration

000010: PLLM = 2

000011: PLLM = 3

000100: PLLM = 4

...

111110: PLLM = 62

111111: PLLM = 63

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Address offset: 0x08

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2, word, half-word and byte access

1 or 2 wait states inserted only if the access occurs during a clock source switch.

31 30 29 28 27 26 25 24

MCO2 rw rw

15 14

PPRE2[2:0]

13 rw rw rw

MCO2 PRE[2:0] rw rw rw

12 11

PPRE1[2:0]

10 rw rw rw

MCO1 PRE[2:0] rw

9 rw

Reserved

I2SSC

R rw

7 rw

22 21

MCO1 rw

6 5

HPRE[3:0] rw rw

20 rw

4 rw

19 18 17

RTCPRE[4:0] rw rw rw

3 2 1

SWS1 SWS0 SW1 r r rw

16 rw

SW0 rw

Bits 31:30 MCO2[1:0]: Microcontroller clock output 2

Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset before enabling the external oscillators and the PLLs.

00: System clock (SYSCLK) selected

01: PLLI2S clock selected

10: HSE oscillator clock selected

11: PLL clock selected

Bits 29:27 MCO2PRE: MCO2 prescaler

Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLLs.

0xx: no division

100: division by 2

101: division by 3

110: division by 4

111: division by 5

Bits 26:24 MCO1PRE: MCO1 prescaler

Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLL.

0xx: no division

100: division by 2

101: division by 3

110: division by 4

111: division by 5

Bit 23 I2SSRC : I2S clock selection

Set and cleared by software. This bit allows to select the I2S clock source between the

PLLI2S clock and the external clock. It is highly recommended to change this bit only after reset and before enabling the I2S module.

0: PLLI2S clock used as I2S clock source

1: External clock mapped on the I2S_CKIN pin used as I2S clock source

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Bits 22:21 MCO1: Microcontroller clock output 1

Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset before enabling the external oscillators and PLL.

00: HSI clock selected

01: LSE oscillator selected

10: HSE oscillator clock selected

11: PLL clock selected

Bits 20:16 RTCPRE: HSE division factor for RTC clock

Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock for RTC.

Caution: The software has to set these bits correctly to ensure that the clock supplied to the

RTC is 1 MHz. These bits must be configured if needed before selecting the RTC clock source.

00000: no clock

00001: no clock

00010: HSE/2

00011: HSE/3

00100: HSE/4

...

11110: HSE/30

11111: HSE/31

Bits 15:13 PPRE2: APB high-speed prescaler (APB2)

Set and cleared by software to control APB high-speed clock division factor.

Caution: The software has to set these bits correctly not to exceed 84 MHz on this domain.

The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after

PPRE2 write.

0xx: AHB clock not divided

100: AHB clock divided by 2

101: AHB clock divided by 4

110: AHB clock divided by 8

111: AHB clock divided by 16

Bits 12:10 PPRE1: APB Low speed prescaler (APB1)

Set and cleared by software to control APB low-speed clock division factor.

Caution: The software has to set these bits correctly not to exceed 42 MHz on this domain.

The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after

PPRE1 write.

0xx: AHB clock not divided

100: AHB clock divided by 2

101: AHB clock divided by 4

110: AHB clock divided by 8

111: AHB clock divided by 16

Bits 9:8 Reserved, must be kept at reset value.

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Bits 7:4 HPRE: AHB prescaler

Set and cleared by software to control AHB clock division factor.

Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after

HPRE write.

0xxx: system clock not divided

1000: system clock divided by 2

1001: system clock divided by 4

1010: system clock divided by 8

1011: system clock divided by 16

1100: system clock divided by 64

1101: system clock divided by 128

1110: system clock divided by 256

1111: system clock divided by 512

Bits 3:2 SWS: System clock switch status

Set and cleared by hardware to indicate which clock source is used as the system clock.

00: HSI oscillator used as the system clock

01: HSE oscillator used as the system clock

10: PLL used as the system clock

11: not applicable

Bits 1:0 SW: System clock switch

Set and cleared by software to select the system clock source.

Set by hardware to force the HSI selection when leaving the Stop or Standby mode or in case of failure of the HSE oscillator used directly or indirectly as the system clock.

00: HSI oscillator selected as system clock

01: HSE oscillator selected as system clock

10: PLL selected as system clock

11: not allowed

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Address offset: 0x0C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Reserved

29 28 27

Reserved

26 25 24

13 12

PLLI2S

RDYIE

PLL

RDYIE

11 10

HSE

RDYIE

HSI

RDYIE rw rw rw rw

LSE

RDYIE rw

LSI

RDYIE rw

CSSC w

CSSF r

22 21

Reserved

PLLI2S

RDYF r

Reserved

PLLI2S

RDYC

PLL

RDYC w w

PLL

RDYF r

HSE

RDYC w

HSE

RDYF r

HSI

RDYC w

HSI

RDYF r

LSE

RDYC w

LSE

RDYF r

LSI

RDYC w

LSI

RDYF r

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 CSSC: Clock security system interrupt clear

This bit is set by software to clear the CSSF flag.

0: No effect

1: Clear CSSF flag

Bit 22 Reserved, must be kept at reset value.

Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear

This bit is set by software to clear the PLLI2SRDYF flag.

0: No effect

1: PLLI2SRDYF cleared

Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear

This bit is set by software to clear the PLLRDYF flag.

0: No effect

1: PLLRDYF cleared

Bit 19 HSERDYC: HSE ready interrupt clear

This bit is set by software to clear the HSERDYF flag.

0: No effect

1: HSERDYF cleared

Bit 18 HSIRDYC: HSI ready interrupt clear

This bit is set software to clear the HSIRDYF flag.

0: No effect

1: HSIRDYF cleared

Bit 17 LSERDYC: LSE ready interrupt clear

This bit is set by software to clear the LSERDYF flag.

0: No effect

1: LSERDYF cleared

Bit 16 LSIRDYC: LSI ready interrupt clear

This bit is set by software to clear the LSIRDYF flag.

0: No effect

1: LSIRDYF cleared

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Bits 15:14 Reserved, must be kept at reset value.

Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by PLLI2S lock.

0: PLLI2S lock interrupt disabled

1: PLLI2S lock interrupt enabled

Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by PLL lock.

0: PLL lock interrupt disabled

1: PLL lock interrupt enabled

Bit 11 HSERDYIE: HSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.

0: HSE ready interrupt disabled

1: HSE ready interrupt enabled

Bit 10 HSIRDYIE: HSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization.

0: HSI ready interrupt disabled

1: HSI ready interrupt enabled

Bit 9 LSERDYIE: LSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.

0: LSE ready interrupt disabled

1: LSE ready interrupt enabled

Bit 8 LSIRDYIE: LSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by LSI oscillator stabilization.

0: LSI ready interrupt disabled

1: LSI ready interrupt enabled

Bit 7 CSSF: Clock security system interrupt flag

Set by hardware when a failure is detected in the HSE oscillator.

Cleared by software setting the CSSC bit.

0: No clock security interrupt caused by HSE clock failure

1: Clock security interrupt caused by HSE clock failure

Bit 6 Reserved, must be kept at reset value.

Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag

Set by hardware when the PLLI2S locks and PLLI2SRDYDIE is set.

Cleared by software setting the PLLRI2SDYC bit.

0: No clock ready interrupt caused by PLLI2S lock

1: Clock ready interrupt caused by PLLI2S lock

Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag

Set by hardware when PLL locks and PLLRDYDIE is set.

Cleared by software setting the PLLRDYC bit.

0: No clock ready interrupt caused by PLL lock

1: Clock ready interrupt caused by PLL lock

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Bit 3 HSERDYF: HSE ready interrupt flag

Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set.

Cleared by software setting the HSERDYC bit.

0: No clock ready interrupt caused by the HSE oscillator

1: Clock ready interrupt caused by the HSE oscillator

Bit 2 HSIRDYF: HSI ready interrupt flag

Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set.

Cleared by software setting the HSIRDYC bit.

0: No clock ready interrupt caused by the HSI oscillator

1: Clock ready interrupt caused by the HSI oscillator

Bit 1 LSERDYF: LSE ready interrupt flag

Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set.

Cleared by software setting the LSERDYC bit.

0: No clock ready interrupt caused by the LSE oscillator

1: Clock ready interrupt caused by the LSE oscillator

Bit 0 LSIRDYF: LSI ready interrupt flag

Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.

Cleared by software setting the LSIRDYC bit.

0: No clock ready interrupt caused by the LSI oscillator

1: Clock ready interrupt caused by the LSI oscillator

6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x10

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

31 30 29 28 27

Reserved

15 14

Reserved

13 12

CRCRST rw

Reserved

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DMA2RST: DMA2 reset

Set and cleared by software.

0: does not reset DMA2

1: resets DMA2

Bit 21 DMA1RST: DMA1 reset

Set and cleared by software.

0: does not reset DMA1

1: resets DMA1

Bits 20:13 Reserved, must be kept at reset value.

GPIOH

RST rw

DMA2

RST rw

DMA1

RST rw

Reserved

20 19 18

Reserved

GPIOE

RST rw

GPIOD

RST rw

GPIOC

RST rw

GPIOB

RST rw

GPIOA

RST rw

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Bit 12 CRCRST: CRC reset

Set and cleared by software.

0: does not reset CRC

1: resets CRC

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 GPIOHRST: IO port H reset

Set and cleared by software.

0: does not reset IO port H

1: resets IO port H

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 GPIOERST: IO port E reset

Set and cleared by software.

0: does not reset IO port E

1: resets IO port E

Bit 3 GPIODRST: IO port D reset

Set and cleared by software.

0: does not reset IO port D

1: resets IO port D

Bit 2 GPIOCRST: IO port C reset

Set and cleared by software.

0: does not reset IO port C

1: resets IO port C

Bit 1 GPIOBRST: IO port B reset

Set and cleared by software.

0: does not reset IO port B

1:resets IO port B

Bit 0 GPIOARST: IO port A reset

Set and cleared by software.

0: does not reset IO port A

1: resets IO port A

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6.3.6

RCC AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x14

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

30 29

14 13

Reserved

24 23

Reserved

8 7

OTGFS

RST rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 6:0 Reserved, must be kept at reset value.

Reserved

RM0368

6.3.7 RCC APB1 peripheral reset register for (RCC_APB1RSTR)

Address offset: 0x20

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

SPI3

RST rw

Reserved

SPI2

RST rw

PWR

RST rw

Reserved

WWDG

RST rw

Reserved

I2C3

RST rw

Reserved

I2C2

RST rw

I2C1

RST rw

Reserved

TIM5

RST rw

TIM4

RST rw

17 16

USART2

RST Reserved rw

TIM3

RST rw

TIM2

RST rw

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 PWRRST: Power interface reset

Set and cleared by software.

0: does not reset the power interface

1: resets the power interface

Bits 27:24 Reserved, must be kept at reset value.

Bit 23 I2C3RST: I2C3 reset

Set and cleared by software.

0: does not reset I2C3

1: resets I2C3

Bit 22 I2C2RST: I2C2 reset

Set and cleared by software.

0: does not reset I2C2

1: resets I2C2

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Bit 21 I2C1RST: I2C1 reset

Set and cleared by software.

0: does not reset I2C1

1: resets I2C1

Bits 20:18 Reserved, must be kept at reset value.

Bit 17 USART2RST: USART2 reset

Set and cleared by software.

0: does not reset USART2

1: resets USART2

Bit 16 Reserved, must be kept at reset value.

Bit 15 SPI3RST: SPI3 reset

Set and cleared by software.

0: does not reset SPI3

1: resets SPI3

Bit 14 SPI2RST: SPI2 reset

Set and cleared by software.

0: does not reset SPI2

1: resets SPI2

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGRST: Window watchdog reset

Set and cleared by software.

0: does not reset the window watchdog

1: resets the window watchdog

Bits 10:4 Reserved, must be kept at reset value.

Bit 3 TIM5RST: TIM5 reset

Set and cleared by software.

0: does not reset TIM5

1: resets TIM5

Bit 2 TIM4RST: TIM4 reset

Set and cleared by software.

0: does not reset TIM4

1: resets TIM4

Bit 1 TIM3RST: TIM3 reset

Set and cleared by software.

0: does not reset TIM3

1: resets TIM3

Bit 0 TIM2RST: TIM2 reset

Set and cleared by software.

0: does not reset TIM2

1: resets TIM2

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6.3.8 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

31 30 29 28 27

Reserved

SYSCFG

RST rw

SPI4

RST rw

SPI1

RST rw

SDIO

RST rw

Reserved

ADC1

RST rw

Reserved

21 20

USART6

RST rw

USART1

RST rw

TIM11

RST rw

TIM10

RST rw

Reserved

TIM9

RST rw

TIM1

RST rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM11RST: TIM11 reset

Set and cleared by software.

0: does not reset TIM11

1: resets TIM11

Bit 17 TIM10RST: TIM10 reset

Set and cleared by software.

0: does not reset TIM10

1: resets TIM10

Bit 16 TIM9RST: TIM9 reset

Set and cleared by software.

0: does not reset TIM9

1: resets TIM9

Bit 15 Reserved, must be kept at reset value.

Bit 14 SYSCFGRST: System configuration controller reset

Set and cleared by software.

0: does not reset the System configuration controller

1: resets the System configuration controller

Bit 13 SPI4RST: SPI4 reset

Set and reset by software.

0: does not reset SPI4

1: resets SPI4

Bit 12 SPI1RST: SPI1 reset

Set and cleared by software.

0: does not reset SPI1

1: resets SPI1

Bit 11 SDIORST: SDIO reset

Set and cleared by software.

0: does not reset the SDIO module

1: resets the SDIO module

Bits 10:9 Reserved, must be kept at reset value.

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Bit 8 ADC1RST: ADC interface reset

Set and cleared by software.

0: does not reset the ADC interface

1: resets the ADC interface

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 USART6RST: USART6 reset

Set and cleared by software.

0: does not reset USART6

1: resets USART6

Bit 4 USART1RST: USART1 reset

Set and cleared by software.

0: does not reset USART1

1: resets USART1

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 TIM1RST: TIM1 reset

Set and cleared by software.

0: does not reset TIM1

1: resets TIM1

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6.3.9 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x30

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

31 30 29 28 27

Reserved

10 15 14

Reserved

13 12

CRCEN rw

Reserved

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DMA2EN: DMA2 clock enable

Set and cleared by software.

0: DMA2 clock disabled

1: DMA2 clock enabled

Bit 21 DMA1EN: DMA1 clock enable

Set and cleared by software.

0: DMA1 clock disabled

1: DMA1 clock enabled

Bits 20:13 Reserved, must be kept at reset value.

Bit 12 CRCEN: CRC clock enable

Set and cleared by software.

0: CRC clock disabled

1: CRC clock enabled

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 GPIOHEN : IO port H clock enable

Set and reset by software.

0: IO port H clock disabled

1: IO port H clock enabled

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 GPIOEEN: IO port E clock enable

Set and cleared by software.

0: IO port E clock disabled

1: IO port E clock enabled

Bit 3 GPIODEN: IO port D clock enable

Set and cleared by software.

0: IO port D clock disabled

1: IO port D clock enabled

Bit 2 GPIOCEN: IO port C clock enable

Set and cleared by software.

0: IO port C clock disabled

1: IO port C clock enabled

GPIOH

EN rw

22 21

DMA2EN DMA1EN rw

6 rw

Reserved

GPIOEEN rw

19 18

Reserved

GPIOD

EN rw

GPIOC

GPIOB

GPIOA

EN rw rw rw

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Bit 1 GPIOBEN: IO port B clock enable

Set and cleared by software.

0: IO port B clock disabled

1: IO port B clock enabled

Bit 0 GPIOAEN: IO port A clock enable

Set and cleared by software.

0: IO port A clock disabled

1: IO port A clock enabled

6.3.10 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x34

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

30 29

14 13

Reserved

24 23

Reserved

8 7

OTGFS

EN rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSEN: USB OTG FS clock enable

Set and cleared by software.

0: USB OTG FS clock disabled

1: USB OTG FS clock enabled

Bits 6:0 Reserved, must be kept at reset value.

Reserved

6.3.11 RCC APB1 peripheral clock enable register (RCC_APB1ENR)

Address offset: 0x40

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

SPI3

EN rw

Reserved

SPI2

EN rw

PWR

EN rw

Reserved

WWDG

EN rw

Reserved

I2C3

EN rw

I2C2

EN rw

I2C1

EN rw

Reserved

TIM5

EN rw

TIM4

EN rw

USART2

EN rw

TIM3

EN rw

Reserved

TIM2

EN rw

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Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 PWREN: Power interface clock enable

Set and cleared by software.

0: Power interface clock disabled

1: Power interface clock enable

Bits 27:24 Reserved, must be kept at reset value.

Bit 23 I2C3EN: I2C3 clock enable

Set and cleared by software.

0: I2C3 clock disabled

1: I2C3 clock enabled

Bit 22 I2C2EN: I2C2 clock enable

Set and cleared by software.

0: I2C2 clock disabled

1: I2C2 clock enabled

Bit 21 I2C1EN: I2C1 clock enable

Set and cleared by software.

0: I2C1 clock disabled

1: I2C1 clock enabled

Bits 20:18 Reserved, must be kept at reset value.

Bit 17 USART2EN: USART2 clock enable

Set and cleared by software.

0: USART2 clock disabled

1: USART2 clock enabled

Bit 16 Reserved, must be kept at reset value.

Bit 15 SPI3EN: SPI3 clock enable

Set and cleared by software.

0: SPI3 clock disabled

1: SPI3 clock enabled

Bit 14 SPI2EN: SPI2 clock enable

Set and cleared by software.

0: SPI2 clock disabled

1: SPI2 clock enabled

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGEN: Window watchdog clock enable

Set and cleared by software.

0: Window watchdog clock disabled

1: Window watchdog clock enabled

Bits 10:4 Reserved, must be kept at reset value.

Bit 3 TIM5EN: TIM5 clock enable

Set and cleared by software.

0: TIM5 clock disabled

1: TIM5 clock enabled

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RM0368

RM0368 Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

Bit 2 TIM4EN: TIM4 clock enable

Set and cleared by software.

0: TIM4 clock disabled

1: TIM4 clock enabled

Bit 1 TIM3EN: TIM3 clock enable

Set and cleared by software.

0: TIM3 clock disabled

1: TIM3 clock enabled

Bit 0 TIM2EN: TIM2 clock enable

Set and cleared by software.

0: TIM2 clock disabled

1: TIM2 clock enabled

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Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E RM0368

(RCC_APB2ENR)

Address offset: 0x44

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

31 30 29 28

Reserved

14 13

SYSCF

G EN

SPI4EN rw rw

SPI1

EN rw

SDIO

EN rw

Reserved

ADC1

EN rw

Reserved

21 20

5 4

USART6

USART1

EN rw rw

TIM11

EN rw

TIM10

EN rw

Reserved

TIM9

EN rw

TIM1

EN rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM11EN: TIM11 clock enable

Set and cleared by software.

0: TIM11 clock disabled

1: TIM11 clock enabled

Bit 17 TIM10EN: TIM10 clock enable

Set and cleared by software.

0: TIM10 clock disabled

1: TIM10 clock enabled

Bit 16 TIM9EN: TIM9 clock enable

Set and cleared by software.

0: TIM9 clock disabled

1: TIM9 clock enabled

Bit 15 Reserved, must be kept at reset value.

Bit 14 SYSCFGEN: System configuration controller clock enable

Set and cleared by software.

0: System configuration controller clock disabled

1: System configuration controller clock enabled

Bit 13 SPI4EN: SPI4 clock enable

Set and reset by software.

0: SPI4 clock disabled

1: SPI4 clock enable

Bit 12 SPI1EN: SPI1 clock enable

Set and cleared by software.

0: SPI1 clock disabled

1: SPI1 clock enabled

Bit 11 SDIOEN: SDIO clock enable

Set and cleared by software.

0: SDIO module clock disabled

1: SDIO module clock enabled

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Bit 8 ADC1EN: ADC1 clock enable

Set and cleared by software.

0: ADC1 clock disabled

1: ADC1 clock disabled

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 USART6EN: USART6 clock enable

Set and cleared by software.

0: USART6 clock disabled

1: USART6 clock enabled

Bit 4 USART1EN: USART1 clock enable

Set and cleared by software.

0: USART1 clock disabled

1: USART1 clock enabled

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 TIM1EN: TIM1 clock enable

Set and cleared by software.

0: TIM1 clock disabled

1: TIM1 clock enabled

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FLITF

LPEN rw

(RCC_AHB1LPENR)

Address offset: 0x50

Reset value: 0x0061 900F

Access: no wait state, word, half-word and byte access.

30 29

Reserved

CRC

LPEN rw

Reserved

GPIOH

LPEN rw

DMA2

LPEN rw

DMA1

LPEN rw

Reserved

20 19

GPIOE

LPEN rw

GPIOD

LPEN rw

Reserved

GPIOC

LPEN rw

17 16

SRAM1

LPEN rw

1 0

GPIOB

LPEN

GPIOA

LPEN rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode

Set and cleared by software.

0: DMA2 clock disabled during Sleep mode

1: DMA2 clock enabled during Sleep mode

Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode

Set and cleared by software.

0: DMA1 clock disabled during Sleep mode

1: DMA1 clock enabled during Sleep mode

Bits 20:17 Reserved, must be kept at reset value.

Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode

Set and cleared by software.

0: SRAM1 interface clock disabled during Sleep mode

1: SRAM1 interface clock enabled during Sleep mode

Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode

Set and cleared by software.

0: Flash interface clock disabled during Sleep mode

1: Flash interface clock enabled during Sleep mode

Bits 14:13 Reserved, must be kept at reset value.

Bit 12 CRCLPEN: CRC clock enable during Sleep mode

Set and cleared by software.

0: CRC clock disabled during Sleep mode

1: CRC clock enabled during Sleep mode

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode

Set and reset by software.

0: IO port H clock disabled during sleep mode

1: IO port H clock enabled during sleep mode

Bits 6:5 Reserved, must be kept at reset value.

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Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode

Set and cleared by software.

0: IO port E clock disabled during Sleep mode

1: IO port E clock enabled during Sleep mode

Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode

Set and cleared by software.

0: IO port D clock disabled during Sleep mode

1: IO port D clock enabled during Sleep mode

Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode

Set and cleared by software.

0: IO port C clock disabled during Sleep mode

1: IO port C clock enabled during Sleep mode

Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode

Set and cleared by software.

0: IO port B clock disabled during Sleep mode

1: IO port B clock enabled during Sleep mode

Bit 0 GPIOALPEN: IO port A clock enable during sleep mode

Set and cleared by software.

0: IO port A clock disabled during Sleep mode

1: IO port A clock enabled during Sleep mode

(RCC_AHB2LPENR)

Address offset: 0x54

Reset value: 0x0000 0080

Access: no wait state, word, half-word and byte access.

30 29

14 13

Reserved

24 23

Reserved

8 7

OTGFS

LPEN rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode

Set and cleared by software.

0: USB OTG FS clock disabled during Sleep mode

1: USB OTG FS clock enabled during Sleep mode

Bits 6:0 Reserved, must be kept at reset value.

Reserved

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6.3.15 RCC APB1 peripheral clock enable in low power mode register

(RCC_APB1LPENR)

Address offset: 0x60

Reset value: 0x10E2 C80F

Access: no wait state, word, half-word and byte access.

SPI3

LPEN rw

Reserved

SPI2

LPEN rw

PWR

LPEN rw

Reserved

WWDG

LPEN rw

Reserved

I2C3

LPEN rw

I2C2

LPEN rw

I2C1

LPEN rw

Reserved

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 PWRLPEN: Power interface clock enable during Sleep mode

Set and cleared by software.

0: Power interface clock disabled during Sleep mode

1: Power interface clock enabled during Sleep mode

Bits 27:24 Reserved, must be kept at reset value.

Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode

Set and cleared by software.

0: I2C3 clock disabled during Sleep mode

1: I2C3 clock enabled during Sleep mode

Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode

Set and cleared by software.

0: I2C2 clock disabled during Sleep mode

1: I2C2 clock enabled during Sleep mode

Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode

Set and cleared by software.

0: I2C1 clock disabled during Sleep mode

1: I2C1 clock enabled during Sleep mode

Bits 20:18 Reserved, must be kept at reset value.

Bit 17 USART2LPEN: USART2 clock enable during Sleep mode

Set and cleared by software.

0: USART2 clock disabled during Sleep mode

1: USART2 clock enabled during Sleep mode

Bit 16 Reserved, must be kept at reset value.

Bit 15 SPI3LPEN: SPI3 clock enable during Sleep mode

Set and cleared by software.

0: SPI3 clock disabled during Sleep mode

1: SPI3 clock enabled during Sleep mode

Reserved

TIM5

LPEN rw

TIM4

LPEN rw

USART2

LPEN rw

TIM3

LPEN rw

Reserved

TIM2

LPEN rw

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Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode

Set and cleared by software.

0: SPI2 clock disabled during Sleep mode

1: SPI2 clock enabled during Sleep mode

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode

Set and cleared by software.

0: Window watchdog clock disabled during sleep mode

1: Window watchdog clock enabled during sleep mode

Bits 10:4 Reserved, must be kept at reset value.

Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode

Set and cleared by software.

0: TIM5 clock disabled during Sleep mode

1: TIM5 clock enabled during Sleep mode

Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode

Set and cleared by software.

0: TIM4 clock disabled during Sleep mode

1: TIM4 clock enabled during Sleep mode

Bit 1 TIM3LPEN: TIM3 clock enable during Sleep mode

Set and cleared by software.

0: TIM3 clock disabled during Sleep mode

1: TIM3 clock enabled during Sleep mode

Bit 0 TIM2LPEN: TIM2 clock enable during Sleep mode

Set and cleared by software.

0: TIM2 clock disabled during Sleep mode

1: TIM2 clock enabled during Sleep mode

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6.3.16 RCC APB2 peripheral clock enabled in low power mode register

(RCC_APB2LPENR)

Address offset: 0x64

Reset value: 0x0007 7930

Access: no wait state, word, half-word and byte access.

31 30 29 28 27

Reserved

SYSC

LPEN rw

SPI4LP

EN rw

SPI1

LPEN rw

SDIO

LPEN rw

Reserved

ADC1

LPEN rw

Reserved

21 20

5 4

USART6

LPEN

USART1

LPEN rw rw

TIM11

LPEN rw

TIM10

LPEN rw

Reserved

TIM9

LPEN rw

TIM1

LPEN rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode

Set and cleared by software.

0: TIM11 clock disabled during Sleep mode

1: TIM11 clock enabled during Sleep mode

Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode

Set and cleared by software.

0: TIM10 clock disabled during Sleep mode

1: TIM10 clock enabled during Sleep mode

Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode

Set and cleared by software.

0: TIM9 clock disabled during Sleep mode

1: TIM9 clock enabled during Sleep mode

Bit 15 Reserved, must be kept at reset value.

Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode

Set and cleared by software.

0: System configuration controller clock disabled during Sleep mode

1: System configuration controller clock enabled during Sleep mode

Bit 13 SPI4LPEN: SPI4 clock enable during sleep mode

Set and reset by software.

0: SPI4 clock disabled during sleep mode

1: SPI4 clock enabled during sleep mode

Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode

Set and cleared by software.

0: SPI1 clock disabled during Sleep mode

1: SPI1 clock enabled during Sleep mode

Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode

Set and cleared by software.

0: SDIO module clock disabled during Sleep mode

1: SDIO module clock enabled during Sleep mode

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Bits 10:9 Reserved, must be kept at reset value.

Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode

Set and cleared by software.

0: ADC1 clock disabled during Sleep mode

1: ADC1 clock disabled during Sleep mode

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 USART6LPEN: USART6 clock enable during Sleep mode

Set and cleared by software.

0: USART6 clock disabled during Sleep mode

1: USART6 clock enabled during Sleep mode

Bit 4 USART1LPEN: USART1 clock enable during Sleep mode

Set and cleared by software.

0: USART1 clock disabled during Sleep mode

1: USART1 clock enabled during Sleep mode

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode

Set and cleared by software.

0: TIM1 clock disabled during Sleep mode

1: TIM1 clock enabled during Sleep mode

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Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E RM0368

Address offset: 0x70

Reset value: 0x0000 0000, reset by Backup domain reset.

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

The LSEON, LSEBYP, RTCSEL and RTCEN bits in the

RCC Backup domain control register (RCC_BDCR)

are in the Backup domain. As a result, after Reset, these bits are write-protected and the DBP bit in the

PWR power control register (PWR_CR) has to be set

before these can be modified. Refer to

Section 5.1.2 on page 72 for further information.

These bits are only reset after a Backup domain Reset (see

Section 6.1.3: Backup domain reset

). Any internal or external Reset will not have any effect on these bits.

RTCEN rw

30 29 28 27

13 12

Reserved

25 24

Reserved

9 8

RTCSEL[1:0] rw rw

22 21 20

6 5

Reserved

18 17 16

BDRST rw

0 2 1

LSEBYP LSERDY LSEON rw r rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 BDRST: Backup domain software reset

Set and cleared by software.

0: Reset not activated

1: Resets the entire Backup domain

Bit 15 RTCEN: RTC clock enable

Set and cleared by software.

0: RTC clock disabled

1: RTC clock enabled

Bits 14:10 Reserved, must be kept at reset value.

Bits 9:8 RTCSEL[1:0]: RTC clock source selection

Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them.

00: No clock

01: LSE oscillator clock used as the RTC clock

10: LSI oscillator clock used as the RTC clock

11: HSE oscillator clock divided by a programmable prescaler (selection through the

RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 LSEBYP: External low-speed oscillator bypass

Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE clock is disabled.

0: LSE oscillator not bypassed

1: LSE oscillator bypassed

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Bit 1 LSERDY: External low-speed oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.

0: LSE clock not ready

1: LSE clock ready

Bit 0 LSEON: External low-speed oscillator enable

Set and cleared by software.

0: LSE clock OFF

1: LSE clock ON

6.3.18 RCC clock control & status register (RCC_CSR)

Address offset: 0x74

Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

LPWR

RSTF r

WWDG

RSTF r

IWDG

RSTF r

14 13

SFT

RSTF r

POR

RSTF r

BORRS

TF r

RMVF rt_w

Reserved

17 16

1 0

LSIRDY LSION r rw

Bit 31 LPWRRSTF: Low-power reset flag

Set by hardware when a Low-power management reset occurs.

Cleared by writing to the RMVF bit.

0: No Low-power management reset occurred

1: Low-power management reset occurred

For further information on Low-power management reset, refer to Low-power management reset

Bit 30 WWDGRSTF: Window watchdog reset flag

Set by hardware when a window watchdog reset occurs.

Cleared by writing to the RMVF bit.

0: No window watchdog reset occurred

1: Window watchdog reset occurred

Bit 29 IWDGRSTF: Independent watchdog reset flag

Set by hardware when an independent watchdog reset from V

domain occurs.

Cleared by writing to the RMVF bit.

0: No watchdog reset occurred

1: Watchdog reset occurred

Bit 28 SFTRSTF: Software reset flag

Set by hardware when a software reset occurs.

Cleared by writing to the RMVF bit.

0: No software reset occurred

1: Software reset occurred

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Bit 27 PORRSTF: POR/PDR reset flag

Set by hardware when a POR/PDR reset occurs.

Cleared by writing to the RMVF bit.

0: No POR/PDR reset occurred

1: POR/PDR reset occurred

Bit 26 PINRSTF: PIN reset flag

Set by hardware when a reset from the NRST pin occurs.

Cleared by writing to the RMVF bit.

0: No reset from NRST pin occurred

1: Reset from NRST pin occurred

Bit 25 BORRSTF: BOR reset flag

Cleared by software by writing the RMVF bit.

Set by hardware when a POR/PDR or BOR reset occurs.

0: No POR/PDR or BOR reset occurred

1: POR/PDR or BOR reset occurred

Bit 24 RMVF: Remove reset flag

Set by software to clear the reset flags.

0: No effect

1: Clear the reset flags

Bits 23:2 Reserved, must be kept at reset value.

Bit 1 LSIRDY: Internal low-speed oscillator ready

Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.

After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.

0: LSI RC oscillator not ready

1: LSI RC oscillator ready

Bit 0 LSION: Internal low-speed oscillator enable

Set and cleared by software.

0: LSI RC oscillator OFF

1: LSI RC oscillator ON

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6.3.19 RCC spread spectrum clock generation register (RCC_SSCGR)

Note:

Address offset: 0x80

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

The spread spectrum clock generation is available only for the main PLL.

The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.

For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to the “Electrical characteristics” section in your device datasheet.

SSCG

EN rw

15 rw

SPR

EAD

SEL rw

INCSTEP rw

Reserved

13 rw

12 rw

27 rw

11 rw

26 rw

10 rw

25 rw

9 rw

8 rw

23 22 21

INCSTEP rw

7 rw rw

MODPER rw rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

Bit 31 SSCGEN: Spread spectrum modulation enable

Set and cleared by software.

0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)

1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)

Bit 30 SPREADSEL: Spread Select

Set and cleared by software.

To write before to set CR[24]=PLLON bit.

0: Center spread

1: Down spread

Bits 29:28 Reserved, must be kept at reset value.

Bits 27:13 INCSTEP: Incrementation step

Set and cleared by software. To write before setting CR[24]=PLLON bit.

Configuration input for modulation profile amplitude.

Bits 12:0 MODPER: Modulation period

Set and cleared by software. To write before setting CR[24]=PLLON bit.

Configuration input for modulation profile period.

16 rw

0 rw

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Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E RM0368

Address offset: 0x84

Reset value: 0x2400 3000

Access: no wait state, word, half-word and byte access.

This register is used to configure the PLLI2S clock outputs according to the formulas:

• f

(VCO clock)

= f

(PLLI2S clock input)

× (PLLI2SN / PLLM)

• f

(PLL I2S clock output)

= f

(VCO clock)

/ PLLI2SR

31 30

PLLI2S

Reserved

Reserved rw

PLLI2SN

8 rw

PLLI2S

R1 rw

PLLI2SN

7 rw

PLLI2S

R0 rw

PLLI2SN

6 rw

27 26

PLLI2SN

5 rw

PLLI2SN

4 rw

25 24 23

Reserved

PLLI2SN

3 rw

PLLI2SN

2 rw

PLLI2SN

1 rw

PLLI2S

N0 rw

21 20 19 18 17 16

5 4 3 2

Reserved

1 0

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks

Set and cleared by software to control the I2S clock frequency. These bits should be written only if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler values inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0% error with audio crystals. For more information about I2S clock frequency and precision, refer to

Section 20.4.4: Clock generator

in the I2S chapter.

Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.

I2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7

000: PLLR = 0, wrong configuration

001: PLLR = 1, wrong configuration

010: PLLR = 2

...

111: PLLR = 7

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RM0368 Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

Bits 27:15 Reserved, must be kept at reset value.

Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to write these bits.

Caution: The software has to set these bits correctly to ensure that the VCO output frequency is between 192 and 432 MHz. With VCO input frequency ranges from 1 to 2 MHz (refer to

Figure 13

and divider factor M of the RCC PLL configuration register (RCC_PLLCFGR) )

VCO output frequency = VCO input frequency × PLLI2SN with 192 PLLI2SN 432

000000000: PLLI2SN = 0, wrong configuration

000000001: PLLI2SN = 1, wrong configuration

...

011000000: PLLI2SN = 192

011000001: PLLI2SN = 193

011000010: PLLI2SN = 194

...

110110000: PLLI2SN = 432

110110000: PLLI2SN = 433, wrong configuration

...

111111111: PLLI2SN = 511, wrong configuration

Bits 5:0 Reserved, must be kept at reset value.

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139

Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E RM0368

6.3.21 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)

Address offset: 0x8C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Reserved

12 11

TIMPRE

23 rw

8 7

Reserved

20 19

Reserved

4 3

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 TIMPRE : Timers clocks prescalers selection

Set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domain.

0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1, TIMxCLK = HCKL . Otherwise, the timer clock frequencies are set to twice to the frequency of the APB domain to which the timers are connected:

TIMxCLK = 2xPCLKx.

1:If the APB prescaler ( PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1 or 2, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set to four times to the frequency of the APB domain to which the timers are connected:

TIMxCLK = 4xPCLKx.

Bits 23: 0 Reserved, must be kept at reset value.

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RM0368 Rev 5

RM0368 Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

6.3.22 RCC register map

Table 22 gives the register map and reset values

Table 22. RCC register map and reset values for STM32F401xB/C and STM32F401xD/E

Addr. offset

Register name

0x00 RCC_CR Reserved

0x04

RCC_

PLLCFGR

Reserved

0x08 RCC_CFGR

0x0C RCC_CIR

0x10

RCC_

AHB1RSTR

0x14

RCC_

AHB2RSTR

0x18

0x1C

Reserved

0x20

RCC_

APB1RSTR

0x24

RCC_

APB2RSTR

0x28

0x2C

0x30

Reserved

RCC_

AHB1ENR

0x34

0x38

0x3C

RCC_

AHB2ENR

Reserved

Reser ved

Reserved

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Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

Table 22. RCC register map and reset values for STM32F401xB/C and STM32F401xD/E (continued)

Addr. offset

Register name

RM0368

0x40

RCC_APB1E

0x44

RCC_APB2E

0x48

0x4C

Reserved

0x50

RCC_AHB1L

PENR

0x54

RCC_AHB2L

PENR

0x58

0x5C

Reserved

0x60

RCC_APB1L

PENR

Reserved

Reserved Reserved

Reserved

0x64

RCC_APB2L

PENR

0x68

0x6C

Reserved

0x70 RCC_BDCR

0x74 RCC_CSR

0x78

0x7C

Reserved

0x80 RCC_SSCGR

0x84

RCC_PLLI2S

CFGR

PLLI2SRx

Reserved

INCSTEP

Reserved

PLLI2SNx

Reserved

MODPER

Reserved

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RM0368 Rev 5

RM0368

Addr. offset

Register name

Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

Table 22. RCC register map and reset values for STM32F401xB/C and STM32F401xD/E (continued)

0x88

0x8C

RCC_DCKCF

Reserved

Refer to Table 1

for the register boundary addresses.

Reserved

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139

System configuration controller (SYSCFG)

7 System configuration controller (SYSCFG)

RM0368

The system configuration controller is mainly used to remap the memory accessible in the code area and manage the external interrupt line connection to the GPIOs.

7.1 I/O compensation cell

By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O t f(IO)out supply.

)/t r(IO)out

commutation to reduce the I/O noise on power

When the compensation cell is enabled, a READY flag is set to indicate that the compensation cell is ready and can be used. The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V.

7.2.1

SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap:

• Two bits are used to configure the type of memory accessible at address 0x0000 0000.

These bits are used to select the physical remap by software and so, bypass the BOOT pins.

• After reset these bits take the value selected by the BOOT pins. When booting from main Flash memory with BOOT0 pin set to 0 this register takes the value 0x00.

In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance.

Address offset: 0x00

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)

)

29 28 27 26 22 21 20 19 18 17 16

14 13 12 11 10

Reserved

24 23

Reserved

8 7 6 5 4 3 2 1 0

MEM_MODE rw rw

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RM0368 System configuration controller (SYSCFG)

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 MEM_MODE: Memory mapping selection

Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins .

00: Main Flash memory mapped at 0x0000 0000

01: System Flash memory mapped at 0x0000 0000

11: Embedded SRAM mapped at 0x0000 0000

Note: Refer to

Section 2.3: Memory map

for details about the memory mapping at address 0x0000 0000.

7.2.2

SYSCFG peripheral mode configuration register (SYSCFG_PMC)

Address offset: 0x04

Reset value: 0x0000 0000

30 29 28 27 26 25 24 23 22 21 20 19 18

14 13 12 11 10 9

Reserved

7 6 5 4 3 2

ADC1D

C2 rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 ADCxDC2 :

0: No effect.

1: Refer to AN4073 on how to use this bit .

Note: These bits can be set only if the following conditions are met:

- ADC clock higher or equal to 30 MHz.

- Only one ADCxDC2 bit must be selected if ADC conversions do not start at the same time and the sampling times differ.

- These bits must not be set when the ADCDC1 bit is set in PWR_CR register.

Bits 15:0 Reserved, must be kept at reset value.

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145

System configuration controller (SYSCFG) RM0368

7.2.3

15 rw

SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

30 29 28 27 26 25 22 21 20

12 11

24 23

Reserved

8 7 4 14 13

EXTI3[3:0] rw rw rw rw

10 9

EXTI2[3:0] rw rw rw rw

6 5

EXTI1[3:0] rw rw rw

3 rw

18 17

2 1

EXTI0[3:0] rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 0 to 3)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: Reserved

0110: Reserved

0111: PH[x] pin

0 rw

7.2.4

15 rw

SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

30 29 28 27 26 25 22 21 20

12 11

24 23

Reserved

8 7 4 14 13

EXTI7[3:0] rw rw rw rw

10 9

EXTI6[3:0] rw rw rw rw

6 5

EXTI5[3:0] rw rw rw

3 rw

18 17

2 1

EXTI4[3:0] rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 4 to 7)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: Reserved

0110: Reserved

0111: PH[x] pin

0 rw

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RM0368 Rev 5

RM0368 System configuration controller (SYSCFG)

7.2.5

15 rw

SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000 0000

30 29 28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

14 13

EXTI11[3:0] rw rw

12 rw

11 rw

10 9

EXTI10[3:0] rw rw rw rw

6 5

EXTI9[3:0] rw rw

4 rw

3 rw

2 1

EXTI8[3:0] rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: Reserved

0110: Reserved

0111: PH[x] pin

0 rw

7.2.6 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

15 rw

30 29 28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

14 13

EXTI15[3:0] rw rw

12 rw

11 rw

10 9

EXTI14[3:0] rw rw rw rw

6 5

EXTI13[3:0] rw rw

4 rw

3 rw

2 1

EXTI12[3:0] rw rw

0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: Reserved

0110: Reserved

0111: PH[x] pin

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System configuration controller (SYSCFG)

7.2.7

Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20

Reset value: 0x0000 0000

30 29 28 27 26 25 22 21 20 19

14 13 12

Reserved

11 10 9

24 23

Reserved

8 7

READY r

6 5 4

Reserved

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY: Compensation cell ready flag

0: I/O compensation cell not ready

1: O compensation cell ready

Bits 7:2 Reserved, must be kept at reset value.

Bit 0 CMP_PD: Compensation cell power-down

0: I/O compensation cell power-down mode

1: I/O compensation cell enabled

RM0368

17 16

1 0

CMP_PD rw

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RM0368 System configuration controller (SYSCFG)

7.2.8

Offset

SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 23. SYSCFG register map and reset values

Register

0x00

SYSCFG_

MEMRMP

Reset value

0x04

SYSCFG_PMC

0x08

0x0C

0x10

0x14

0x20

Reset value

SYSCFG_

EXTICR1

Reset value

SYSCFG_

EXTICR2

Reset value

SYSCFG_

EXTICR3

Reset value

SYSCFG_

EXTICR4

Reset value

SYSCFG_

CMPCR

Reset value

Reserved x x

Reserved

EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

0 0

show the basic structure of a 5 V tolerant I/O port bit. Table 27

for the register boundary addresses.

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General-purpose I/Os (GPIO)

8 General-purpose I/Os (GPIO)

RM0368

GPIO F/G/H/I/J/K (except GPIOH0 and GPIOH1) are not available in STM32F401xB/C and

STM32F401xD/E.

8.2

8.3

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Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers

(GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).

GPIO main features

• Up to 16 I/Os under control

• Output states: push-pull or open drain + pull-up/down

• Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)

• Speed selection for each I/O

• Input states: floating, pull-up/down, analog

• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)

• Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR

• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration

• Analog function

• Alternate function input/output selection registers (at most 16 AFs per I/O)

• Fast toggle capable of changing every two clock cycles

• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:

• Input floating

• Input pull-up

• Input-pull-down

• Analog

• Output open-drain with pull-up or pull-down capability

• Output push-pull with pull-up or pull-down capability

• Alternate function push-pull with pull-up or pull-down capability

• Alternate function open-drain with pull-up or pull-down capability

RM0368 Rev 5

RM0368 General-purpose I/Os (GPIO)

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

gives the possible port bit configurations.

Figure 16. Basic structure of a five-volt tolerant I/O port bit

4OONCHIP

PERIPHERAL

!NALOG

!LTERNATEFUNCTIONINPUT

ONOFF

2EAD

7RITE

44,3CHMITT

TRIGGER

)NPUTDRIVER

/UTPUTDRIVER

ONOFF

6$$?&4

0ULL

0ROTECTION

DIODE

)/PIN

/UTPUT

CONTROL

0-/3

ONOFF

0ULL

DOWN

0ROTECTION

DIODE

2EADWRITE

&ROMONCHIP

PERIPHERAL

!LTERNATEFUNCTIONOUTPUT

.-/3

0USHPULL

OPENDRAINOR

DISABLED

!NALOG

AIB

1. V

DD_FT is a potential specific to five-volt tolerant I/Os and different from V

Table 24. Port bit configuration table (1)

MODER(i)

[1:0]

OTYPER(i)

OSPEEDR(i)

[B:A]

PUPDR(i)

[1:0]

I/O configuration

SPEED

[B:A]

GP output

Reserved

PP + PU

PP + PD

GP output

OD + PU

GP output OD + PD

Reserved (GP output OD)

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165

General-purpose I/Os (GPIO) RM0368

MODER(i)

[1:0]

Table 24. Port bit configuration table (1) (continued)

OTYPER(i)

OSPEEDR(i)

[B:A]

PUPDR(i)

[1:0]

I/O configuration

1 x x x x x x x x x x x x x x x x

SPEED

[B:A] x x x x x x x x

Reserved

Input

PP + PU

PP + PD

OD + PU

OD + PD

Floating

Reserved (input floating)

Input/output Analog

Reserved

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

During and just after reset, the alternate functions are not active and the I/O ports are configured in input floating mode.

The debug pins are in AF pull-up/pull-down after reset:

• PA15: JTDI in pull-up

• PA14: JTCK/SWCLK in pull-down

• PA13: JTMS/SWDAT in pull-up

• PB4: NJTRST in pull-up

• PB3: JTDO in floating state

When the pin is configured as output, the value written to the output data register

(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the N-MOS is activated when 0 is output).

The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.

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RM0368 Rev 5

RM0368 General-purpose I/Os (GPIO)

Note:

The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.

Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:

• After reset all I/Os are connected to the system’s alternate function 0 (AF0)

• The peripherals’ alternate functions are mapped from AF1 to AF13

• Cortex ® -M4 with FPU EVENTOUT is mapped on AF15

This structure is shown in Figure 17 below.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, proceed as follows:

• System function

Connect the I/O to AF0 and configure it depending on the function used:

– JTAG/SWD, after each device reset these pins are assigned as dedicated pins immediately usable by the debugger host (not controlled by the GPIO controller)

– RTC_REFIN: this pin should be configured in Input floating mode

– MCO1 and MCO2: these pins have to be configured in alternate function mode.

The user can disable some or all of the JTAG/SWD pins and so release the associated pins for GPIO usage (released pins highlighted in gray in the table).

For more details please refer to Section 6.2.10: Clock-out capability

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165

General-purpose I/Os (GPIO)

Note:

RM0368

Table 25. Flexible SWJ-DP pin assignment

SWJ I/O pin assigned

Available debug ports

Full SWJ (JTAG-DP + SW-DP) - Reset state

Full SWJ (JTAG-DP + SW-DP) but without

NJTRST

JTAG-DP Disabled and SW-DP Enabled

JTAG-DP Disabled and SW-DP Disabled

PA13 /

JTMS/

SWDIO

PA14 /

JTCK/

SWCLK

PA15 /

JTDI

PB3 /

JTDO

PB4/

NJTRST

Released

• GPIO

Configure the desired I/O as output or input in the GPIOx_MODER register.

• Peripheral alternate function

For the ADC, configure the desired I/O as analog in the GPIOx_MODER register.

For other peripherals:

– Configure the desired I/O as an alternate function in the GPIOx_MODER register

– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively

– Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

• EVENTOUT

Configure the I/O pin used to output the Cortex

-M4 with FPU EVENTOUT signal by connecting it to AF15

EVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0 and PH1.

Please refer to the “Alternate function mapping” table in the datasheets for the detailed mapping of the system and peripherals’ alternate function I/O pins.

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RM0368 Rev 5

RM0368 General-purpose I/Os (GPIO)

Figure 17. Selecting an alternate function on STM32F401xB/C and STM32F401xD/E

!&SYSTEM

!&4)-4)-

!&4)-

!&)#

!&30)

!&53!24

!&)#

!&/4'?&3

!&3$)/

!&%6%.4/54

0INXX

!&2,;=

&ORPINSTOTHE'0)/X?!&2(;=REGISTERSELECTSTHEDEDICATEDALTERNATEFUNCTION

!&SYSTEM

!&4)-4)-

!&4)-

!&)#

!&30)

!&53!24

!&)#

!&/4'?&3

!&3$)/

!&%6%.4/54

0INXX

!&2(;=

-36

1. Configured in FS.

RM0368 Rev 5

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165

General-purpose I/Os (GPIO)

8.3.3

8.3.4

8.3.5

I/O port control registers

RM0368

Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER,

GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os.

The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog).

The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type

(push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction). The

GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.

I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers

(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register

(GPIOx_IDR), a read-only register.

See

Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A..E and H) and

Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A..E and H) for the register

descriptions.

I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR.

To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BSRR(i) and

BSRR(i+SIZE). When written to 1, bit BSRR(i) sets the corresponding ODR(i) bit. When written to 1, bit BSRR(i+SIZE) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in

GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a

“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB1 write access.

It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,

GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU or peripheral reset. Each GPIOx_LCKR bit

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RM0368 Rev 5

RM0368 General-purpose I/Os (GPIO) freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER,

GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).

The LOCK sequence (refer to

Section 8.4.8: GPIO port configuration lock register

(GPIOx_LCKR) (x = A..E and H) ) can only be performed using a word (32-bit long) access

to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.

For more details please refer to LCKR register description in

Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H)

Note:

8.3.8

Two registers are provided to select one out of the sixteen alternate function inputs/outputs available for each I/O. With these registers, you can connect an alternate function to some other pin as required by your application.

This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of one I/O.

To know which functions are multiplexed on each GPIO pin, refer to the datasheets.

The application is allowed to select one of the possible peripheral functions for each I/O at a time.

External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode, refer to

Section 10.2: External interrupt/event controller (EXTI)

and Section 10.2.3: Wakeup event management .

When the I/O port is programmed as Input:

• the output buffer is disabled

• the Schmitt trigger input is activated

• the pull-up and pull-down resistors are activated depending on the value in the

GPIOx_PUPDR register

• The data present on the I/O pin are sampled into the input data register every AHB clock cycle

• A read access to the input data register provides the I/O State

Figure 18

shows the input configuration of the I/O port bit.

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Figure 18. Input floating/pull up/pull down configurations

RM0368

2EAD

7RITE

2EADWRITE

INPUTDRIVER

OUTPUTDRIVER

44,3CHMITT

TRIGGER

6$$

ONOFF

6$$

PULL

PROTECTION

DIODE

)/PIN

ONOFF

PULL

DOWN

633 633

PROTECTION

DIODE

AIB

When the I/O port is programmed as output:

• The output buffer is enabled:

– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)

– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS

• The Schmitt trigger input is activated

• The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register

• The data present on the I/O pin are sampled into the input data register every AHB clock cycle

• A read access to the input data register gets the I/O state

• A read access to the output data register gets the last written value

Figure 19

shows the output configuration of the I/O port bit.

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RM0368 General-purpose I/Os (GPIO)

Figure 19. Output configuration

2EAD

7RITE

2EADWRITE

)NPUTDRIVER

/UTPUTDRIVER

44,3CHMITT

TRIGGER

/UTPUT

CONTROL

0-/3

.-/3

0USHPULLOR

/PENDRAIN

ONOFF

PROTECTION

DIODE

PULL

)/PIN

ONOFF

PULL

DOWN

PROTECTION

DIODE

AIB

8.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:

• The output buffer can be configured as open-drain or push-pull

• The output buffer is driven by the signal coming from the peripheral (transmitter enable and data)

• The Schmitt trigger input is activated

• The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register

• The data present on the I/O pin are sampled into the input data register every AHB clock cycle

• A read access to the input data register gets the I/O state

Figure 20

shows the Alternate function configuration of the I/O port bit.

Figure 20. Alternate function configuration

4OONCHIP

PERIPHERAL

!LTERNATEFUNCTIONINPUT

2EAD

7RITE

2EADWRITE

&ROMONCHIP

PERIPHERAL !LTERNATEFUNCTIONOUTPUT

44,3CHMITT

TRIGGER

)NPUTDRIVER

/UTPUTDRIVER

/UTPUT

CONTROL

0-/3

.-/3

PUSHPULLOR

OPENDRAIN

ONOFF

0ULL

PROTECTION

DIODE

)/PIN

ONOFF

0ULL

DOWN

PROTECTION

DIODE

AIB

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Note:

When the I/O port is programmed as analog configuration:

• The output buffer is disabled

• The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).

• The weak pull-up and pull-down resistors are disabled

• Read access to the input data register gets the value “0”

In the analog configuration, the I/O pins cannot be 5 Volt tolerant.

Figure 21

shows the high-impedance, analog-input configuration of the I/O port bit.

Figure 21. High impedance-analog configuration

4OONCHIP

PERIPHERAL

2EAD

!NALOG

OFF

7RITE

)NPUTDRIVER

44,3CHMITT

TRIGGER

PROTECTION

DIODE

)/PIN

PROTECTION

DIODE

2EADWRITE

&ROMONCHIP

PERIPHERAL

!NALOG

8.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins

Note:

The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose

PC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os are only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE oscillator is ON. This is done by setting the LSEON bit in the RCC_BDCR register. The LSE has priority over the GPIO function.

The PC14/PC15 GPIO functionality is lost when the 1.2 V domain is powered off (by the device entering the standby mode) or when the backup domain is supplied by V more supplied). In this case the I/Os are set in analog input mode.

BAT

8.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins

The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1

I/Os, respectively, when the HSE oscillator is OFF. (after reset, the HSE oscillator is off). The

PH0/PH1 I/Os are only configured as OSC_IN/OSC_OUT HSE oscillator pins when the

HSE oscillator is ON. This is done by setting the HSEON bit in the RCC_CR register. The

HSE has priority over the GPIO function.

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RM0368 General-purpose I/Os (GPIO)

8.3.15 Selection of RTC functions

The STM32F4xx feature one GPIO pins RTC_AF1 that can be used for the detection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs.

• The RTC_AF1 (PC13) can be used for the following purposes:

RTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup depending on the OSEL[1:0] bits in the RTC_CR register

• RTC_CALIB output: this feature is enabled by setting the COE[23] in the RTC_CR register

• RTC_TAMP1: tamper event detection

• RTC_TS: time stamp event detection

The selection of the corresponding pin is performed through the RTC_TAFCR register as follows:

• TAMP1INSEL is used to select which pin is used as the RTC_TAMP1 tamper input

• TSINSEL is used to select which pin is used as the RTC_TS time stamp input

• ALARMOUTTYPE is used to select whether the RTC_ALARM is output in push-pull or open-drain mode

The output mechanism follows the priority order listed in

Table 26 .

Table 26. RTC additional functions (1)

Pin configuration and function

RTC_ALARM enabled

RTC_CALIB enabled

Tamper enabled

Time stamp enabled

TAMP1INSEL

TAMPER1 pin selection

TSINSEL

TIMESTAMP pin selection

ALARMOUTTYPE

RTC_ALARM configuration

Alarm out output OD

Alarm out output PP

Calibration out output PP

TAMPER1 input floating

TIMESTAMP and

TAMPER1 input floating

TIMESTAMP input floating

Standard

GPIO

1. OD: open drain; PP: push-pull.

Don’t care

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General-purpose I/Os (GPIO) RM0368

This section gives a detailed description of the GPIO registers.

For a summary of register bits, register address offsets and reset values, refer to

Table 27 .

The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits).

8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..E and H)

Address offset: 0x00

Reset values:

• 0x0C00 0000 for port A

• 0x0000 0280 for port B

• 0x0000 0000 for other ports

31 30 29 28 27 26 25 24

MODER15[1:0] MODER14[1:0] MODER13[1:0] MODER12[1:0] rw

15 rw

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

MODER7[1:0] rw rw

MODER6[1:0] rw rw

MODER5[1:0] rw rw

MODER4[1:0] rw rw

23 22

MODER11[1:0] rw

7 rw

MODER3[1:0] rw rw

21 20

MODER10[1:0] rw

5 rw

MODER2[1:0] rw rw

19 18

MODER9[1:0] rw

3 rw

MODER1[1:0] rw rw

Bits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O direction mode.

00: Input (reset state)

01: General purpose output mode

10: Alternate function mode

11: Analog mode

17 16

MODER8[1:0] rw

1 rw

MODER0[1:0] rw rw

8.4.2 GPIO port output type register (GPIOx_OTYPER)

(x = A..E and H)

Address offset: 0x04

Reset value: 0x0000 0000

31 30 29 28 27 26

15 14 13 12 11 10

OT15 OT14 OT13 OT12 OT11 OT10 rw rw rw rw rw rw

OT9 rw

24 23

Reserved

OT8 rw

OT7 rw

OT6 rw

OT5 rw

OT4 rw

OT3 rw

OT2 rw

OT1 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OTy : Port x configuration bits (y = 0..15)

These bits are written by software to configure the output type of the I/O port.

0: Output push-pull (reset state)

1: Output open-drain

OT0 rw

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8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A..E and H)

Address offset: 0x08

Reset values:

• 0x0C00 0000 for port A

• 0x0000 00C0 for port B

• 0x0000 0000 for other ports

31 rw

OSPEEDR15

[1:0] rw

OSPEEDR14

[1:0] rw rw

27 26

OSPEEDR13

[1:0] rw rw

11 10

25 24

OSPEEDR12

[1:0] rw

9 rw

OSPEEDR11

[1:0] rw

22 rw

OSPEEDR10

[1:0] rw rw

OSPEEDR7[1:0] OSPEEDR6[1:0] OSPEEDR5[1:0] OSPEEDR4[1:0] OSPEEDR3[1:0] OSPEEDR2[1:0] rw rw rw rw rw rw rw rw rw rw rw rw

19 18

OSPEEDR9

[1:0] rw rw

3 2

OSPEEDR1

[1:0] rw rw

17 16

OSPEEDR8

[1:0] rw rw

1 0

OSPEEDR0

1:0] rw rw

Bits 2y:2y+1 OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: High speed

11: Very high speed

Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V

DD range and external load.

8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A..E and H)

Address offset: 0x0C

Reset values:

• 0x6400 0000 for port A

• 0x0000 0100 for port B

• 0x0000 0000 for other ports

31 30 29 28 27 26 25 24

PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] rw

15 rw

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

PUPDR7[1:0] rw rw

PUPDR6[1:0] rw rw

PUPDR5[1:0] rw rw

PUPDR4[1:0] rw rw

23 22

PUPDR11[1:0] rw

7 rw

PUPDR3[1:0] rw rw

21 20

PUPDR10[1:0] rw

5 rw

PUPDR2[1:0] rw rw

19 18

PUPDR9[1:0] rw

3 rw

PUPDR1[1:0] rw rw

17 16

PUPDR8[1:0] rw

1 rw

PUPDR0[1:0] rw rw

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General-purpose I/Os (GPIO) RM0368

Bits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O pull-up or pull-down

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..E and H)

Address offset: 0x10

Reset value: 0x0000 XXXX (where X means undefined)

31 30 29 28 27 26 25

15 14 13 12 11 10 9

IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 r r r r r r r

24 23

Reserved

IDR8 r

IDR7 r

IDR6 r

IDR5 r

IDR4 r

IDR3 r

IDR2 r

IDR1 r

IDR0 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDRy : Port input data (y = 0..15)

These bits are read-only and can be accessed in word mode only. They contain the input value of the corresponding I/O port.

8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..E and H)

Address offset: 0x14

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

15 14 13 12 11 10 9 6 5 4 3 2 1 0

ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODRy : Port output data (y = 0..15)

These bits can be read and written by software.

Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the

GPIOx_BSRR register (x = A..E and H).

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RM0368 General-purpose I/Os (GPIO)

8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H)

Address offset: 0x18

Reset value: 0x0000 0000

BR15 w

BS15 w

BR14

BR13 w

BS14 w w

BS13 w

BR12 w

BS12 w

BR11 w

BS11 w

BR10 w

BS10 w

BR9 w

BS9 w

BR8 w

BS8 w

BR7 w

BS7 w

BR6 w

BS6 w

BR5 w

BS5 w

BR4 w

BS4 w

BR3 w

BS3 w

BR2 w

BS2 w

BR1 w

BS1 w

Bits 31:16 BRy: Port x reset bit y (y = 0..15)

These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Resets the corresponding ODRx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BSy: Port x set bit y (y= 0..15)

These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Sets the corresponding ODRx bit

BR0 w

BS0 w

8.4.8

Note:

GPIO port configuration lock register (GPIOx_LCKR)

(x = A..E and H)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the

GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the

LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU or peripheral reset.

A specific write sequence is used to write to the GPIOx_LCKR register. Only word access

(32-bit long) is allowed during this write sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Address offset: 0x1C

Reset value: 0x0000 0000

Access: 32-bit word only, read/write register

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

LCKK rw

0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK[16]: Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset or a peripheral reset occurs.

LOCK key write sequence:

WR LCKR[16] = ‘1’ + LCKR[15:0]

WR LCKR[16] = ‘0’ + LCKR[15:0]

WR LCKR[16] = ‘1’ + LCKR[15:0]

RD LCKR

RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit will return ‘1’ until the next CPU reset.

Bits 15:0 LCKy: Port x lock bit y (y= 0..15)

These bits are read/write but can only be written when the LCKK bit is ‘0.

0: Port configuration not locked

1: Port configuration locked

8.4.9

31 rw

15 rw

GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H)

Address offset: 0x20

Reset value: 0x0000 0000

30 29

AFRL7[3:0] rw

14 rw

AFRL3[3:0] rw rw

28 rw

12 rw

27 rw

11 rw

26 25

AFRL6[3:0] rw

10 rw

AFRL2[3:0] rw rw

24 rw

8 rw

23 rw

7 rw

22 21

AFRL5[3:0] rw

6 rw

AFRL1[3:0] rw rw

20 rw

4 rw

19 rw

3 rw

Bits 31:0 AFRLy: Alternate function selection for port x bit y (y = 0..7)

These bits are written by software to configure alternate function I/Os

AFRLy selection:

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

1000: AF8

1001: AF9

1010: AF10

1011: AF11

1100: AF12

1101: AF13

1110: AF14

1111: AF15

18 17

AFRL4[3:0] rw

2 rw

AFRL0[3:0] rw rw

16 rw

0 rw

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31 rw

15 rw

(x = A..E and H)

Address offset: 0x24

Reset value: 0x0000 0000

30 29

AFRH15[3:0] rw

14 rw

AFRH11[3:0] rw rw

28 rw

12 rw

27 rw

11 rw

26 25

AFRH14[3:0] rw

10 rw

AFRH10[3:0] rw rw

24 rw

8 rw

23 rw

7 rw

22 21

AFRH13[3:0] rw

6 rw

AFRH9[3:0] rw rw

20 rw

4 rw

19 rw

3 rw

Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15)

These bits are written by software to configure alternate function I/Os

AFRHy selection:

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

1000: AF8

1001: AF9

1010: AF10

1011: AF11

1100: AF12

1101: AF13

1110: AF14

1111: AF15

18 17

AFRH12[3:0] rw

2 rw

AFRH8[3:0] rw rw

16 rw

0 rw

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8.4.11 GPIO register map

The following table gives the GPIO register map and the reset values.

Table 27. GPIO register map and reset values

Offset Register

RM0368

0x00

GPIOA_

MODER

Reset value 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x00

GPIOB_

MODER

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0

0x00

GPIOx_MODER

(where x = C..E and H)

0x04

Reset value

GPIOx_

OTYPER

(where x = A..E and H)

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOx_

OSPEEDR

(where x = C..E and H )

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOA_

OSPEEDER

Reset value 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x08

GPIOB_

OSPEEDR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

0x0C

GPIOA_PUPDR

Reset value 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Offset Register

General-purpose I/Os (GPIO)

Table 27. GPIO register map and reset values (continued)

0x0C

GPIOB_PUPDR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

0x0C

GPIOx_PUPDR

(where x = C..E and H)

0x10

0x14

0x18

0x1C

0x20

0x24

Reset value

GPIOx_IDR

(where x = A..E and H)

Reset value

GPIOx_ODR

(where x = A..E and H)

Reset value

GPIOx_BSRR

(where x = A..E and H)

Reset value

GPIOx_LCKR

(where x = A..E and H)

Reset value

GPIOx_AFRL

(where x = A..E and H)

Reset value

GPIOx_AFRH

(where x = A..E and H)

Reset value

AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0]

AFRL7[3:0]

Reserved

AFRL6[3:0]

0 0

AFRL5[3:0]

0 0

AFRL4[3:0]

0 0

0 0 x x

0 0

0 0 x

0 0

AFRL3[3:0]

0 0

0 0 x

0 0

0 0 x x

0 0

0 0 0 0 0 0 0 0 0 0 x

AFRL2[3:0]

0 0

0 0 x x x x x x x x x

0 0 0 0 0 0 0 0 0 0

AFRL1[3:0] AFRL0[3:0]

0 0 0 0 0 0 0 0 0 0

Table 30 describes the corresponding source and destination addresses.

for the register boundary addresses.

RM0368 Rev 5

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DMA controller (DMA)

9 DMA controller (DMA)

RM0368

9.2

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by

DMA without any CPU action. This keeps CPU resources free for other operations.

The DMA controller combines a powerful dual AHB master bus architecture with independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix architecture.

The two DMA controllers have 16 streams in total (8 for each controller), each dedicated to managing memory access requests from one or more peripherals. Each stream can have up to 8 channels (requests) in total. And each has an arbiter for handling the priority between DMA requests.

DMA main features

The main DMA features are:

• Dual AHB master bus architecture, one dedicated to memory accesses and one dedicated to peripheral accesses

• AHB slave programming interface supporting only 32-bit accesses

• 8 streams for each DMA controller, up to 8 channels (requests) per stream

• Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be used in FIFO mode or direct mode:

– FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the

FIFO size

– Direct mode

Each DMA request immediately initiates a transfer from/to the memory. When it is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads only one data from the memory to the internal

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FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.

• Each stream can be configured by hardware to be:

– a regular channel that supports peripheral-to-memory, memory-to-peripheral and memory-to-memory transfers

– a double buffer channel that also supports double buffering on the memory side

• Each of the 8 streams are connected to dedicated hardware DMA channels (requests)

• Priorities between DMA stream requests are software-programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 0 has priority over request 1, etc.)

• Each stream also supports software trigger for memory-to-memory transfers (only available for the DMA2 controller)

• Each stream request can be selected among up to 8 possible channel requests. This selection is software-configurable and allows several peripherals to initiate DMA requests

• The number of data items to be transferred can be managed either by the DMA controller or by the peripheral:

– DMA flow controller: the number of data items to be transferred is softwareprogrammable from 1 to 65535

– Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware

• Independent source and destination transfer width (byte, half-word, word): when the data widths of the source and destination are not equal, the DMA automatically packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only available in FIFO mode

• Incrementing or non-incrementing addressing for source and destination

• Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is software-configurable, usually equal to half the FIFO size of the peripheral

• Each stream supports circular buffer management

• 5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA

FIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for each stream

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9.3 DMA functional description

RM0368

Figure 22

shows the block diagram of a DMA.

Figure 22. DMA block diagram

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The DMA controller performs direct memory transfer: as an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions.

It can carry out the following transactions:

• peripheral-to-memory

• memory-to-peripheral

• memory-to-memory

The DMA controller provides two AHB master ports: the AHB memory port , intended to be connected to memories and the AHB peripheral port , intended to be connected to peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must also have access to the memories.

The AHB slave port is used to program the DMA controller (it supports only 32-bit accesses).

RM0368 Rev 5

RM0368 DMA controller (DMA)

See

Figure 23

for the implementation of the system of two DMA controllers.

Figure 23. System implementation of the two DMA controllers

(STM32F401xB/C and STM32F401xD/E)

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1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like DMA2 controller. As a result, only DMA2 streams are able to perform memory-to-memory transfers.

A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable.

Each DMA transfer consists of three operations:

• A loading from the peripheral data register or a location in memory, addressed through the DMA_SxPAR or DMA_SxM0AR register

• A storage of the data loaded to the peripheral data register or a location in memory addressed through the DMA_SxPAR or DMA_SxM0AR register

• A post-decrement of the DMA_SxNDTR register, which contains the number of transactions that still have to be performed

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After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the

DMA controller. The peripheral releases its request as soon as it gets the Acknowledge signal from the DMA controller. Once the request has been deasserted by the peripheral, the DMA controller releases the Acknowledge signal. If there are more requests, the peripheral can initiate the next transaction.

Each stream is associated with a DMA request that can be selected out of 8 possible channel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR register.

Figure 24. Channel selection

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The 8 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently connected to each channel and their connection depends on the product implementation.

See the following table(s) for examples of DMA request mappings.

Table 28. DMA1 request mapping (STM32F401xB/C and STM32F401xD/E)

Peripheral requests

Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

SPI3_RX

I2C1_RX

TIM4_CH1

I2S3_EXT_RX

I2C3_RX

TIM2_UP

TIM2_CH3

SPI3_RX

SPI2_TX

SPI3_TX

I2C1_RX

I2C1_TX

I2S3_EXT_RX

I2C3_RX

TIM4_CH2

I2S2_EXT_RX

I2S2_EXT_TX I2S3_EXT_TX

I2C3_TX

TIM2_CH1

TIM4_UP

TIM2_CH2

TIM2_CH4

USART2_RX USART2_TX

TIM3_CH4

TIM3_UP

SPI2_RX

TIM3_CH1

TIM3_TRIG

TIM3_CH2

SPI3_TX

I2C1_TX

TIM4_CH3

TIM2_UP

TIM2_CH4

TIM3_CH3

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Table 28. DMA1 request mapping (STM32F401xB/C and STM32F401xD/E) (continued)

Peripheral requests

Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7

Channel 6

Channel 7

TIM5_CH3

TIM5_UP

TIM5_CH4

TIM5_TRIG

TIM5_CH1

I2C2_RX

TIM5_CH4

TIM5_TRIG

I2C2_RX

TIM5_CH2

I2C3_TX

TIM5_UP

I2C2_TX

Table 29. DMA2 request mapping (STM32F401xB/C and STM32F401xD/E)

Peripheral requests

Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

ADC1

SPI1_RX

SPI4_RX

TIM1_TRIG

SPI4_TX

USART6_RX

TIM1_CH1

SPI1_RX

USART1_RX

USART6_RX

TIM1_CH2

SPI1_TX

SDIO

SPI4_RX

TIM1_CH1

ADC1

SPI4_TX

TIM1_CH4

TIM1_TRIG

TIM1_COM

SPI1_TX

USART1_RX

TIM1_UP

TIM1_CH1

TIM1_CH2

TIM1_CH3

SDIO

USART1_TX

USART6_TX USART6_TX

TIM1_CH3

9.3.4 Arbiter

An arbiter manages the 8 DMA stream requests based on their priority for each of the two

AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences.

Priorities are managed in two stages:

• Software: each stream priority can be configured in the DMA_SxCR register. There are four levels:

– Very high priority

– High priority

– Medium priority

– Low priority

• Hardware: If two requests have the same software priority level, the stream with the lower number takes priority over the stream with the higher number. For example,

Stream 2 takes priority over Stream 4.

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Each of the 8 DMA controller streams provides a unidirectional transfer link between a source and a destination.

Each stream can be configured to perform:

• Regular type transactions: memory-to-peripherals, peripherals-to-memory or memoryto-memory transfers

• Double-buffer type transactions: double buffer transfers using two memory pointers for the memory (while the DMA is reading/writing from/to a buffer, the application can write/read to/from the other buffer).

The amount of data to be transferred (up to 65535) is programmable and related to the source width of the peripheral that requests the DMA transfer connected to the peripheral

AHB port. The register that contains the amount of data items to be transferred is decremented after each transaction.

Both source and destination transfers can address peripherals and memories in the entire

4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.

The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory transfers.

Table 30. Source and destination address

Direction Source address Destination address

Bits DIR[1:0] of the

DMA_SxCR register

Peripheral-to-memory

Memory-to-peripheral

Memory-to-memory reserved -

DMA_SxPAR

DMA_SxM0AR

DMA_SxPAR

DMA_SxM0AR

DMA_SxPAR

DMA_SxM0AR

When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the

DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively.

Peripheral-to-memory mode

Figure 25

describes this mode.

When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.

When the threshold level of the FIFO is reached, the contents of the FIFO are drained and stored into the destination.

The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software.

RM0368 Rev 5

RM0368 DMA controller (DMA)

In direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO, the corresponding data are immediately drained and stored into the destination.

The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register.

Figure 25. Peripheral-to-memory mode

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1. For double-buffer mode.

Memory-to-peripheral mode

Figure 26

describes this mode.

When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream immediately initiates transfers from the source to entirely fill the FIFO.

Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined threshold level, the FIFO is fully reloaded with data from the memory.

In direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold level of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA transfers the preloaded value into the configured destination. It then reloads again the

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$-!CONTROLLER

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Figure 26. Memory-to-peripheral mode

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1. For double-buffer mode.

Memory-to-memory mode

Note:

The DMA channels can also work without being triggered by a request from a peripheral.

This is the memory-to-memory mode, described in Figure 27 .

When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the stream immediately starts to fill the FIFO up to the threshold level. When the threshold level is reached, the FIFO contents are drained and stored into the destination.

The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the

DMA_SxCR register is cleared by software.

When memory-to-memory mode is used, the Circular and direct modes are not allowed.

Only the DMA2 controller is able to perform memory-to-memory transfers.

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Figure 27. Memory-to-memory mode

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1. For double-buffer mode.

Peripheral and memory pointers can optionally be automatically post-incremented or kept constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR register.

Disabling the Increment mode is useful when the peripheral source or destination data are accessed through a single register.

If the Increment mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.

In order to optimize the packing operation, it is possible to fix the increment offset size for the peripheral address whatever the size of the data transferred on the AHB peripheral port.

The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with the data size on the peripheral AHB port, or on a 32-bit address (the address is then incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.

If PINCOS bit is set, the address of the next transfer is the address of the previous one incremented by 4 (automatically aligned on a 32-bit address) whatever the PSIZE value.

The AHB memory port, however, is not impacted by this operation.

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Note:

9.3.9

Note:

The Circular mode is available to handle circular buffers and continuous data flows (e.g.

ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register.

When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.

In the circular mode, it is mandatory to respect the following rule in case of a burst mode configured for memory:

DMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:

– (Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR register)

– ((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and

PSIZE bits in the DMA_SxCR register. They are byte dependent)

– DMA_SxNDTR = Number of data items to transfer on the AHB peripheral port

For example: Mburst beat = 8 (INCR8), MSIZE = ‘00’ (byte) and PSIZE = ‘01’ (half-word), in this case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).

If this formula is not respected, the DMA behavior and data integrity are not guaranteed.

NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data size, otherwise this could result in a bad DMA behavior.

Double buffer mode

This mode is available for all the DMA1 and DMA2 streams.

The Double buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.

A double-buffer stream works as a regular (single buffer) stream with the difference that it has two memory pointers. When the Double buffer mode is enabled, the Circular mode is automatically enabled (CIRC bit in DMA_SxCR is don’t care) and at each end of transaction, the memory pointers are swapped.

In this mode, the DMA controller swaps from one memory target to another at each end of transaction. This allows the software to process one memory area while the second memory area is being filled/used by the DMA transfer. The double-buffer stream can work in both directions (the memory can be either the source or the destination) as described in

Table 31: Source and destination address registers in Double buffer mode (DBM=1) .

In Double buffer mode, it is possible to update the base address for the AHB memory port on-the-fly ( DMA_SxM0AR or DMA_SxM1AR ) when the stream is enabled, by respecting the following conditions:

• When the CT bit is ‘0’ in the DMA_SxCR register, the DMA_SxM1AR register can be written. Attempting to write to this register while CT = '1' sets an error flag (TEIF) and the stream is automatically disabled.

• When the CT bit is ‘1’ in the DMA_SxCR register, the DMA_SxM0AR register can be written. Attempting to write to this register while CT = '0', sets an error flag (TEIF) and the stream is automatically disabled.

To avoid any error condition, it is advised to change the base address as soon as the TCIF flag is asserted because, at this point, the targeted memory must have changed from

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For all the other modes (except the Double buffer mode), the memory address registers are write-protected as soon as the stream is enabled.

Table 31. Source and destination address registers in Double buffer mode (DBM=1)

Bits DIR[1:0] of the

DMA_SxCR register

Direction Source address Destination address

00 Peripheral-to-memory DMA_SxPAR

DMA_SxM0AR /

DMA_SxM1AR

01 Memory-to-peripheral

DMA_SxM0AR /

DMA_SxM1AR

DMA_SxPAR

Not allowed

Reserved

(1)

1. When the Double buffer mode is enabled, the Circular mode is automatically enabled. Since the memoryto-memory mode is not compatible with the Circular mode, when the Double buffer mode is enabled, it is not allowed to configure the memory-to-memory mode.

9.3.10 Programmable data width, packing/unpacking, endianess

The number of data items to be transferred has to be programmed into DMA_SxNDTR

(number of data items to transfer bit, NDT) before enabling the stream (except when the flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).

When using the internal FIFO, the data widths of the source and destination data are programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-,

16- or 32-bit).

When PSIZE and MSIZE are not equal:

• The data width of the number of data items to transfer, configured in the DMA_SxNDTR register is equal to the width of the peripheral bus (configured by the PSIZE bits in the

DMA_SxCR register). For instance, in case of peripheral-to-memory, memory-toperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for half-word, the number of bytes to be transferred is equal to 2 × NDT.

• The DMA controller only copes with little-endian addressing for both source and

destination. This is described in Table 32: Packing/unpacking & endian behavior (bit

PINC = MINC = 1)

This packing/unpacking procedure may present a risk of data corruption when the operation is interrupted before the data are completely packed/unpacked. So, to ensure data coherence, the stream may be configured to generate burst transfers: in this case, each group of transfers belonging to a burst are indivisible (refer to

Section 9.3.11: Single and burst transfers ).

In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is not possible. In this case, it is not allowed to have different source and destination transfer data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR MSIZE bits are don’t care).

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Table 32. Packing/unpacking & endian behavior (bit PINC = MINC = 1)

AHB memory port width

AHB peripheral port width

Number of data items to transfer

(NDT)

Memory transfer number

Memory port address / byte lane

Peripher al transfer number

Peripheral port address / byte lane

PINCOS = 1 PINCOS = 0

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 / B1|B0[15:0]

0x0 / B0[7:0]

0x4 / B1[7:0]

0x8 / B2[7:0]

0xC / B3[7:0]

0x0 / B1|B0[15:0]

0x4 / B3|B2[15:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 / B3|B2|B1|B0[31:0] 0x0 / B3|B2|B1|B0[31:0]

0x0 / B0[7:0]

0x4 / B1[7:0]

0x8 / B2[7:0]

0xC / B3[7:0]

0x0 / B1|B0[15:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x2 / B1|B0[15:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 / B3|B2|B1|B0[31:0] 1

0x0 /B3|B2|B1|B0[31:0] 1

0x0 /B3|B2|B1|B0 [31:0] 1

0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0]

0x0 / B3|B2|B1|B0[31:0] 0x0 / B3|B2|B1|B0[31:0]

0x0 / B0[7:0]

0x4 / B1[7:0]

0x8 / B2[7:0]

0xC / B3[7:0]

0x0 / B0[7:0]

0x1 / B1[7:0]

0x2 / B2[7:0]

0x3 / B3[7:0]

0x0 / B1|B0[15:0]

0x4 / B3|B2[15:0]

0x0 / B1|B0[15:0]

0x2 / B3|B2[15:0]

0x0 /B3|B2|B1|B0 [31:0] 0x0 / B3|B2|B1|B0[31:0]

Note: Peripheral port may be the source or the destination (it could also be the memory source in the case of memory-to-memory transfer).

PSIZE, MSIZE and NDT[15:0] have to be configured so as to ensure that the last transfer will not be incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is lower than the data width of the memory port (MSIZE bits). This constraint is summarized in

Table 33 .

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Table 33. Restriction on NDT versus PSIZE and MSIZE

PSIZE[1:0] of DMA_SxCR MSIZE[1:0] of DMA_SxCR NDT[15:0] of DMA_SxNDTR

00 (8-bit)

01 (16-bit)

10 (32-bit)

10 (32-bit) must be a multiple of 2 must be a multiple of 4 must be a multiple of 2

9.3.11 Single and burst transfers

The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats.

The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.

The burst size indicates the number of beats in the burst, not the number of bytes transferred.

To ensure data coherence, each group of transfers that form a burst are indivisible: AHB transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master during the sequence of the burst transfer.

Depending on the single or burst configuration, each DMA request initiates a different number of transfers on the AHB peripheral port:

• When the AHB peripheral port is configured for single transfers, each DMA request generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits in the DMA_SxCR register

• When the AHB peripheral port is configured for burst transfers, each DMA request generates 4,8 or 16 beats of byte, half word or word transfers depending on the

PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.

The same as above has to be considered for the AHB memory port considering the

MBURST and MSIZE bits.

In direct mode, the stream can only generate single transfers and the MBURST[1:0] and

PBURST[1:0] bits are forced by hardware.

The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to ensure that all transfers within a burst block are aligned on the address boundary equal to the size of the transfer.

The burst configuration has to be selected in order to respect the AHB protocol, where bursts must not cross the 1 KB address boundary because the minimum address space that can be allocated to a single slave is 1 KB. This means that the 1 KB address boundary should not be crossed by a burst block transfer, otherwise an AHB error would be generated, that is not reported by the DMA registers.

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9.3.12 FIFO

FIFO structure

The FIFO is used to temporarily store data coming from the source before transmitting them to the destination.

Each stream has an independent 4-word FIFO and the threshold level is softwareconfigurable between 1/4, 1/2, 3/4 or full.

To enable the use of the FIFO threshold level, the direct mode must be disabled by setting the DMDIS bit in the DMA_SxFCR register.

The structure of the FIFO differs depending on the source and destination data widths, and is described in

Figure 28: FIFO structure

Figure 28. FIFO structure

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RM0368 Rev 5

RM0368

Note:

DMA controller (DMA)

FIFO threshold and burst configuration

Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match to an integer number of memory burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or

DMA_LISR register) will be generated when the stream is enabled, then the stream will be automatically disabled. The allowed and forbidden configurations are described in the

Table 34: FIFO threshold configurations .

MSIZE

Byte

Half-word

Word

1/2

3/4

Full

1/4

1/2

1/4

1/2

3/4

Full

1/4

3/4

Full

Table 34. FIFO threshold configurations

FIFO level MBURST = INCR4 MBURST = INCR8

1 burst of 4 beats

2 bursts of 4 beats

3 bursts of 4 beats

4 bursts of 4 beats forbidden

1 burst of 4 beats forbidden

2 bursts of 4 beats forbidden

1 burst of 8 beats forbidden

2 bursts of 8 beats forbidden

1 burst of 8 beats forbidden

1 burst of 4 beats forbidden

MBURST = INCR16 forbidden

1 burst of 16 beats forbidden

In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data size can be: 1 (byte), 2 (half-word) or 4 (word)).

Incomplete Burst transfer at the end of a DMA transfer may happen if one of the following conditions occurs:

• For the AHB peripheral port configuration: the total number of data items (set in the

DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size

• For the AHB memory port configuration: the number of remaining data items in the

FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the data size

In such cases, the remaining data to be transferred will be managed in single mode by the

DMA, even if a burst transaction was requested during the DMA stream configuration.

When burst transfers are requested on the peripheral AHB port and the FIFO is used

(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to avoid permanent underrun or overrun conditions, depending on the DMA stream direction:

If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with

PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.

This rule ensures that enough FIFO space at a time will be free to serve the request from the peripheral.

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FIFO flush

The FIFO can be flushed when the stream is disabled by resetting the EN bit in the

DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers: If some data are still present in the FIFO when the stream is disabled, the DMA controller continues transferring the remaining data to the destination

(even though stream is effectively disabled). When this flush is completed, the transfer complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.

The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how many data items are currently available in the destination memory.

Note that during the FIFO flush operation, if the number of remaining data items in the FIFO to be transferred to memory (in bytes) is less than the memory data width (for example 2 bytes in FIFO while MSIZE is configured to word), data will be sent with the data width set in the MSIZE bit in the DMA_SxCR register. This means that memory will be written with an undesired value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address).

If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions will be generated to complete the FIFO flush.

Direct mode

By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and the FIFO threshold level is not used. This mode is useful when the system requires an immediate and single transfer to or from the memory after each DMA request.

When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads one data from the memory to the internal FIFO to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.

To avoid saturating the FIFO, it is recommended to configure the corresponding stream with a high priority.

This mode is restricted to transfers where:

• The source and destination transfer widths are equal and both defined by the

PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are don’t care)

• Burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR are don’t care)

Direct mode must not be used when implementing memory-to-memory transfers.

Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR or DMA_HISR status register:

• In DMA flow controller mode:

– The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode

– The stream is disabled before the end of transfer (by clearing the EN bit in the

DMA_SxCR register) and (when transfers are peripheral-to-memory or memory-

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DMA controller (DMA) to-memory) all the remaining data have been flushed from the FIFO into the memory

• In Peripheral flow controller mode:

– The last external burst or single request has been generated from the peripheral and (when the DMA is operating in peripheral-to-memory mode) the remaining data have been transferred from the FIFO into the memory

– The stream is disabled by software, and (when the DMA is operating in peripheralto-memory mode) the remaining data have been transferred from the FIFO into the memory

The transfer completion is dependent on the remaining data in FIFO to be transferred into memory only in the case of peripheral-to-memory mode. This condition is not applicable in memory-to-peripheral mode.

If the stream is configured in noncircular mode, after the end of the transfer (that is when the number of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is cleared by Hardware) and no DMA request is served unless the software reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).

Note:

At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer.

There are two cases:

• The stream disables the transfer with no later-on restart from the point where it was stopped. There is no particular action to do, except to clear the EN bit in the

DMA_SxCR register to disable the stream. The stream may take time to be disabled

(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the

DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The value of the EN bit in DMA_SxCR is now ‘0’ to confirm the stream interruption. The

DMA_SxNDTR register contains the number of remaining data items at the moment when the stream was stopped so that the software can determine how many data items have been transferred before the stream was interrupted.

• The stream suspends the transfer before the number of remaining data items to be transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer later by re-enabling the stream. In order to restart from the point where the transfer was stopped, the software has to read the DMA_SxNDTR register after disabling the stream by writing the EN bit in DMA_SxCR register (and then checking that it is at ‘0’) to know the number of data items already collected. Then:

– The peripheral and/or memory addresses have to be updated in order to adjust the address pointers

– The SxNDTR register has to be updated with the remaining number of data items to be transferred (the value read when the stream was disabled)

– The stream may then be re-enabled to restart the transfer from the point it was stopped

Note that a Transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to indicate the end of transfer due to the stream interruption.

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Note:

The entity that controls the number of data to be transferred is known as the flow controller.

This flow controller is configured independently for each stream using the PFCTRL bit in the

DMA_SxCR register.

The flow controller can be:

• The DMA controller: in this case, the number of data items to be transferred is programmed by software into the DMA_SxNDTR register before the DMA stream is enabled.

• The peripheral source or destination: this is the case when the number of data items to be transferred is unknown. The peripheral indicates by hardware to the DMA controller when the last data are being transferred. This feature is only supported for peripherals which are able to signal the end of the transfer, that is:

– SDIO

When the peripheral flow controller is used for a given stream, the value written into the

DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it will be forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following schemes:

• Anticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the software to stop the stream before the last data hardware signal (single or burst) is sent by the peripheral. In such a case, the stream is switched off and the FIFO flush is triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the

DMA_SxNDTR register and apply the following formula:

– Number_of_data_transferred = 0xFFFF – DMA_SxNDTR

• Normal stream interruption due to the reception of a last data hardware signal: the stream is automatically interrupted when the peripheral requests the last transfer

(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding stream is set in the status register to indicate the DMA transfer completion. To know the number of data items transferred, read the DMA_SxNDTR register and apply the same formula as above.

• The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is set in the status register to indicate the forced DMA transfer completion. The stream is automatically switched off even though the last data hardware signal (single or burst) has not been yet asserted. The already transferred data will not be lost. This means that a maximum of 65535 data items can be managed by the DMA in a single transaction, even in peripheral flow control mode.

When configured in memory-to-memory mode, the DMA is always the flow controller and the PFCTRL bit is forced to 0 by hardware.

The Circular mode is forbidden in the peripheral flow controller mode.

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9.3.16 Summary of the possible DMA configurations

Table 35 summarizes the different possible DMA configurations.

DMA transfer mode

Source

Peripheral-tomemory

Memory-toperipheral

Memory-tomemory

Table 35. Possible DMA configurations

Destination

Flow controller

Circular mode

Transfer type

Direct mode

AHB peripheral port

AHB memory port

AHB peripheral port

DMA possible

Peripheral forbidden

AHB peripheral port

AHB memory port

DMA possible

Peripheral forbidden

DMA only forbidden single burst single burst single burst single burst single burst possible forbidden possible forbidden possible forbidden possible forbidden

Double buffer mode possible forbidden possible forbidden forbidden forbidden

The following sequence should be followed to configure a DMA stream x (where x is the stream number):

If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, then read this bit in order to confirm that there is no ongoing stream operation. Writing this bit to 0 is not immediately effective since it is actually written to 0 once all the current transfers have finished. When the EN bit is read as 0, this means that the stream is ready to be configured. It is therefore necessary to wait for the EN bit to be cleared before starting any stream configuration. All the stream dedicated bits set in the status register (DMA_LISR and DMA_HISR) from the previous data block DMA transfer should be cleared before the stream can be re-enabled.

2. Set the peripheral port register address in the DMA_SxPAR register. The data will be moved from/ to this address to/ from the peripheral port after the peripheral event.

3. Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R register in the case of a double buffer mode). The data will be written to or read from this memory after the peripheral event.

4. Configure the total number of data items to be transferred in the DMA_SxNDTR register. After each peripheral event or each beat of the burst, this value is decremented.

5. Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.

6. If the peripheral is intended to be the flow controller and if it supports this feature, set the PFCTRL bit in the DMA_SxCR register.

7. Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.

8. Configure the FIFO usage (enable or disable, threshold in transmission and reception)

9. Configure the data transfer direction, peripheral and memory incremented/fixed mode, single or burst transactions, peripheral and memory data widths, Circular mode,

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Double buffer mode and interrupts after half and/or full transfer, and/or errors in the

DMA_SxCR register.

10. Activate the stream by setting the EN bit in the DMA_SxCR register.

As soon as the stream is enabled, it can serve any DMA request from the peripheral connected to the stream.

Once half the data have been transferred on the AHB destination port, the half-transfer flag

(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is generated if the transfer complete interrupt enable bit (TCIE) is set.

Warning: To switch off a peripheral connected to a DMA stream request, it is mandatory to, first, switch off the DMA stream to which the peripheral is connected, then to wait for EN bit = 0.

Only then can the peripheral be safely disabled.

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The DMA controller can detect the following errors:

• Transfer error : the transfer error interrupt flag (TEIFx) is set when:

– A bus error occurs during a DMA read or a write access

– A write access is requested by software on a memory address register in Double buffer mode whereas the stream is enabled and the current target memory is the one impacted by the write into the memory address register (refer to

Section 9.3.9:

Double buffer mode

)

• FIFO error : the FIFO error interrupt flag (FEIFx) is set if:

– A FIFO underrun condition is detected

– A FIFO overrun condition is detected (no detection in memory-to-memory mode because requests and transfers are internally managed by the DMA)

– The stream is enabled while the FIFO threshold level is not compatible with the size of the memory burst (refer to

Table 34: FIFO threshold configurations

)

• Direct mode error : the direct mode error interrupt flag (DMEIFx) can only be set in the peripheral-to-memory mode while operating in direct mode and when the MINC bit in the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while the previous data have not yet been fully transferred into the memory (because the memory bus was not granted). In this case, the flag indicates that 2 data items were be transferred successively to the same destination address, which could be an issue if the destination is not able to manage this situation

In direct mode, the FIFO error flag can also be set under the following conditions:

• In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory bus is not granted for several peripheral requests

• In the memory-to-peripheral mode, an underrun condition may occur if the memory bus has not been granted before a peripheral request occurs

If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO threshold level, the faulty stream is automatically disabled through a hardware clear of its

EN bit in the corresponding stream configuration register (DMA_SxCR).

RM0368 Rev 5

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Note:

DMA controller (DMA)

If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss when this kind of errors occur.

When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE,

FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.

When a FIFO overrun or underrun condition occurs, the data are not lost because the peripheral request is not acknowledged by the stream until the overrun or underrun condition is cleared. If this acknowledge takes too much time, the peripheral itself may detect an overrun or underrun condition of its internal buffer and data might be lost.

Note:

For each DMA stream, an interrupt can be produced on the following events:

• Half-transfer reached

• Transfer complete

• Transfer error

• Fifo error (overrun, underrun or FIFO level error)

• Direct mode error

Separate interrupt enable control bits are available for flexibility as shown in Table 36

Interrupt event

Half-transfer

Transfer complete

Transfer error

FIFO overrun/underrun

Direct mode error

Table 36. DMA interrupt requests

Event flag

HTIF

TCIF

TEIF

FEIF

DMEIF

Enable control bit

HTIE

TCIE

TEIE

FEIE

DMEIE

Before setting an Enable control bit to ‘1’, the corresponding event flag should be cleared, otherwise an interrupt is immediately generated.

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The DMA registers have to be accessed by words (32 bits).

9.5.1

31 r

15 r

DMA low interrupt status register (DMA_LISR)

Address offset: 0x00

30 29

Reserved r r

14 13

Reserved r r

Reset value: 0x0000 0000

28 r

12 r

27 26 25 24 23

TCIF3 HTIF3 TEIF3 DMEIF3 Reserv r r r r ed

11 10 9 8 7

TCIF1 HTIF1 TEIF1 DMEIF1 Reserv r r r r ed

22 21

FEIF3 TCIF2 r r

6 5

FEIF1 TCIF0 r r

20 19 18 17

HTIF2 TEIF2 DMEIF2 Reserv r r r ed

4 3 2 1

HTIF0 TEIF0 DMEIF0 Reserv r r r ed

FEIF2 r

FEIF0 r

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 TCIFx : Stream x transfer complete interrupt flag (x = 3..0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: No transfer complete event on stream x

1: A transfer complete event occurred on stream x

Bits 26, 20, 10, 4 HTIFx : Stream x half transfer interrupt flag (x=3..0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: No half transfer event on stream x

1: A half transfer event occurred on stream x

Bits 25, 19, 9, 3 TEIFx : Stream x transfer error interrupt flag (x=3..0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: No transfer error on stream x

1: A transfer error occurred on stream x

Bits 24, 18, 8, 2 DMEIFx : Stream x direct mode error interrupt flag (x=3..0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: No Direct Mode Error on stream x

1: A Direct Mode Error occurred on stream x

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 FEIFx : Stream x FIFO error interrupt flag (x=3..0)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_LIFCR register.

0: No FIFO Error event on stream x

1: A FIFO Error event occurred on stream x

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9.5.2

DMA high interrupt status register (DMA_HISR)

Address offset: 0x04

Reset value: 0x0000 0000

30 29

Reserved

14 13

Reserved

27 26 25 24 23 22 21 20 19 18 17

TCIF7 HTIF7 TEIF7 DMEIF7 Reserv ed r r r r

11 10 9 8 7

FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Reserv ed r r r r r

6 5 4 3 2 1

TCIF5 HTIF5 TEIF5 DMEIF5 Reserv ed r r r r

FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4 Reserv ed r r r r r

FEIF6 r

FEIF4 r

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 TCIFx : Stream x transfer complete interrupt flag (x=7..4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: No transfer complete event on stream x

1: A transfer complete event occurred on stream x

Bits 26, 20, 10, 4 HTIFx : Stream x half transfer interrupt flag (x=7..4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: No half transfer event on stream x

1: A half transfer event occurred on stream x

Bits 25, 19, 9, 3 TEIFx : Stream x transfer error interrupt flag (x=7..4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: No transfer error on stream x

1: A transfer error occurred on stream x

Bits 24, 18, 8, 2 DMEIFx : Stream x direct mode error interrupt flag (x=7..4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: No Direct mode error on stream x

1: A Direct mode error occurred on stream x

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 FEIFx : Stream x FIFO error interrupt flag (x=7..4)

This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the

DMA_HIFCR register.

0: No FIFO error event on stream x

1: A FIFO error event occurred on stream x

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9.5.3 DMA low interrupt flag clear register (DMA_LIFCR)

Address offset: 0x08

Reset value: 0x0000 0000

31 30 29 28

Reserved

15 14 13 12

Reserved

27 26 25 24

CTCIF3 CHTIF3 CTEIF3 CDMEIF3 w

11 w

10 w

9 w

23 22 21 20 19 18

Reserved

CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 w w w w w

7 6 5 4 3 2

Reserved

CFEIF2 w

1 0

CTCIF1 CHTIF1 CTEIF1 CDMEIF1 w w w w

Reserved

CFEIF1 CTCIF0 CHTIF0 CTEIF0 CDMEIF0 w w w w w

Reserved

CFEIF0 w

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 CTCIFx : Stream x clear transfer complete interrupt flag (x = 3..0)

Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register

Bits 26, 20, 10, 4 CHTIFx : Stream x clear half transfer interrupt flag (x = 3..0)

Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register

Bits 25, 19, 9, 3 CTEIFx : Stream x clear transfer error interrupt flag (x = 3..0)

Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register

Bits 24, 18, 8, 2 CDMEIFx : Stream x clear direct mode error interrupt flag (x = 3..0)

Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 CFEIFx : Stream x clear FIFO error interrupt flag (x = 3..0)

Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register

9.5.4 DMA high interrupt flag clear register (DMA_HIFCR)

Address offset: 0x0C

31 30 29 28

Reserved

Reset value: 0x0000 0000

15 14 13 12

27 26 25 24 23 22 21 20 19 18 17 16

CTCIF7 CHTIF7 CTEIF7 CDMEIF7 w w w w

Reserved

CFEIF7 CTCIF6 CHTIF6 CTEIF6 CDMEIF6 w w w w w

Reserved

CFEIF6 w

11 10 9 8

CTCIF5 CHTIF5 CTEIF5 CDMEIF5 w w w w

7 6 5 4 3 2

Reserved

CFEIF5 CTCIF4 CHTIF4 CTEIF4 CDMEIF4 w w w w w

Reserved

CFEIF4 w

Bits 31:28, 15:12 Reserved, must be kept at reset value.

Bits 27, 21, 11, 5 CTCIFx : Stream x clear transfer complete interrupt flag (x = 7..4)

Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register

Bits 26, 20, 10, 4 CHTIFx : Stream x clear half transfer interrupt flag (x = 7..4)

Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register

Bits 25, 19, 9, 3 CTEIFx : Stream x clear transfer error interrupt flag (x = 7..4)

Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register

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Bits 24, 18, 8, 2 CDMEIFx : Stream x clear direct mode error interrupt flag (x = 7..4)

Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register

Bits 23, 17, 7, 1 Reserved, must be kept at reset value.

Bits 22, 16, 6, 0 CFEIFx : Stream x clear FIFO error interrupt flag (x = 7..4)

Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register

9.5.5 DMA stream x configuration register (DMA_SxCR) (x = 0..7)

This register is used to configure the concerned stream.

Address offset: 0x10 + 0x18 × stream number

Reset value: 0x0000 0000

31 30 29

Reserved

PINCOS rw

14 13

MSIZE[1:0] rw rw

28 27 rw

12 11

PSIZE[1:0] rw rw

CHSEL[2:0] rw

25 rw

10 9

MINC PINC rw rw

24 23

MBURST [1:0] rw rw

CIRC rw

DIR[1:0] rw

6 rw

22 21

PBURST[1:0] rw rw

PFCTRL rw

Reserved

TCIE rw

CT rw

HTIE rw

DBM rw

TEIE rw

17 16 rw

PL[1:0] rw

DMEIE rw

EN rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:25 CHSEL[2:0] : Channel selection

These bits are set and cleared by software.

000: channel 0 selected

001: channel 1 selected

010: channel 2 selected

011: channel 3 selected

100: channel 4 selected

101: channel 5 selected

110: channel 6 selected

111: channel 7 selected

These bits are protected and can be written only if EN is ‘0’

Bits 24:23 MBURST : Memory burst transfer configuration

These bits are set and cleared by software.

00: single transfer

01: INCR4 (incremental burst of 4 beats)

10: INCR8 (incremental burst of 8 beats)

11: INCR16 (incremental burst of 16 beats)

These bits are protected and can be written only if EN is ‘0’

In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.

Bits 22:21 PBURST[1:0] : Peripheral burst transfer configuration

These bits are set and cleared by software.

00: single transfer

01: INCR4 (incremental burst of 4 beats)

10: INCR8 (incremental burst of 8 beats)

11: INCR16 (incremental burst of 16 beats)

These bits are protected and can be written only if EN is ‘0’

In direct mode, these bits are forced to 0x0 by hardware.

Bit 20 Reserved, must be kept at reset value.

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Bit 19 CT : Current target (only in double buffer mode)

This bits is set and cleared by hardware. It can also be written by software.

0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer)

1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer)

This bit can be written only if EN is ‘0’ to indicate the target memory area of the first transfer.

Once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target.

Bit 18 DBM : Double buffer mode

This bits is set and cleared by software.

0: No buffer switching at the end of transfer

1: Memory target switched at the end of the DMA transfer

This bit is protected and can be written only if EN is ‘0’.

Bits 17:16 PL[1:0] : Priority level

These bits are set and cleared by software.

00: Low

01: Medium

10: High

11: Very high

These bits are protected and can be written only if EN is ‘0’.

Bit 15 PINCOS : Peripheral increment offset size

This bit is set and cleared by software

0: The offset size for the peripheral address calculation is linked to the PSIZE

1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).

This bit has no meaning if bit PINC = '0'.

This bit is protected and can be written only if EN = '0'.

This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or if PBURST are different from “00”.

Bits 14:13 MSIZE[1:0] : Memory data size

These bits are set and cleared by software.

00: byte (8-bit)

01: half-word (16-bit)

10: word (32-bit)

11: reserved

These bits are protected and can be written only if EN is ‘0’.

In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as bit EN

= '1'.

Bits 12:11 PSIZE[1:0] : Peripheral data size

These bits are set and cleared by software.

00: Byte (8-bit)

01: Half-word (16-bit)

10: Word (32-bit)

11: reserved

These bits are protected and can be written only if EN is ‘0’

Bit 10 MINC : Memory increment mode

This bit is set and cleared by software.

0: Memory address pointer is fixed

1: Memory address pointer is incremented after each data transfer (increment is done according to MSIZE)

This bit is protected and can be written only if EN is ‘0’.

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RM0368 DMA controller (DMA)

Bit 9 PINC : Peripheral increment mode

This bit is set and cleared by software.

0: Peripheral address pointer is fixed

1: Peripheral address pointer is incremented after each data transfer (increment is done according to PSIZE)

This bit is protected and can be written only if EN is ‘0’.

Bit 8 CIRC : Circular mode

This bit is set and cleared by software and can be cleared by hardware.

0: Circular mode disabled

1: Circular mode enabled

When the peripheral is the flow controller (bit PFCTRL=1) and the stream is enabled (bit

EN=1), then this bit is automatically forced by hardware to 0.

It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is enabled (bit EN ='1').

Bits 7:6 DIR[1:0] : Data transfer direction

These bits are set and cleared by software.

00: Peripheral-to-memory

01: Memory-to-peripheral

10: Memory-to-memory

11: reserved

These bits are protected and can be written only if EN is ‘0’.

Bit 5 PFCTRL : Peripheral flow controller

This bit is set and cleared by software.

0: The DMA is the flow controller

1: The peripheral is the flow controller

This bit is protected and can be written only if EN is ‘0’.

When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is automatically forced to 0 by hardware.

Bit 4 TCIE : Transfer complete interrupt enable

This bit is set and cleared by software.

0: TC interrupt disabled

1: TC interrupt enabled

Bit 3 HTIE : Half transfer interrupt enable

This bit is set and cleared by software.

0: HT interrupt disabled

1: HT interrupt enabled

Bit 2 TEIE : Transfer error interrupt enable

This bit is set and cleared by software.

0: TE interrupt disabled

1: TE interrupt enabled

Bit 1 DMEIE : Direct mode error interrupt enable

This bit is set and cleared by software.

0: DME interrupt disabled

1: DME interrupt enabled

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Bit 0 EN : Stream enable / flag stream ready when read low

This bit is set and cleared by software.

0: Stream disabled

1: Stream enabled

This bit may be cleared by hardware:

– on a DMA end of transfer (stream ready to be configured)

– if a transfer error occurs on the AHB master buses

– when the FIFO threshold on memory AHB port is not compatible with the size of the burst

When this bit is read as 0, the software is allowed to program the Configuration and FIFO bits registers. It is forbidden to write these registers when the EN bit is read as 1.

Note: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the stream in DMA_LISR or DMA_HISR register must be cleared.

9.5.6

15 rw

DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)

Address offset: 0x14 + 0x18 × stream number

Reset value: 0x0000 0000

30 29

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

24 23

Reserved

8 7

NDT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0] : Number of data items to transfer

Number of data items to be transferred (0 up to 65535). This register can be written only when the stream is disabled. When the stream is enabled, this register is read-only, indicating the remaining data items to be transmitted. This register decrements after each

DMA transfer.

Once the transfer has completed, this register can either stay at zero (when the stream is in normal mode) or be reloaded automatically with the previously programmed value in the following cases:

– when the stream is configured in Circular mode.

– when the stream is enabled again by setting EN bit to '1'

If the value of this register is zero, no transaction can be served even if the stream is enabled.

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RM0368 DMA controller (DMA)

9.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)

Address offset: 0x18 + 0x18 × stream number

Reset value: 0x0000 0000

31 rw

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

PAR[31:16] rw

8 rw

7 rw

PAR[15:0] rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PAR[31:0] : Peripheral address

Base address of the peripheral data register from/to which the data will be read/written.

These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.

9.5.8

31 rw

15 rw

DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)

Address offset: 0x1C + 0x18 × stream number

Reset value: 0x0000 0000

30 29 rw

14 rw

28 rw

27 rw

26 rw

25 rw

24 23

M0A[31:16] rw rw

8 7

M0A[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

1 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 M0A[31:0] : Memory 0 address

Base address of Memory area 0 from/to which the data will be read/written.

These bits are write-protected. They can be written only if:

– the stream is disabled (bit EN= '0' in the DMA_SxCR register) or

– the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '1' in the

DMA_SxCR register (in Double buffer mode).

16 rw

0 rw

9.5.9

31 rw

15 rw

DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)

Address offset: 0x20 + 0x18 × stream number

Reset value: 0x0000 0000

30 29 28 27 26 25 22 21 20 19 18 17 rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

M1A[31:16] rw rw

8 7

M1A[15:0] rw rw rw

6 rw rw

5 rw rw

4 rw rw

3 rw rw

2 rw rw

1 rw

16 rw

0 rw

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Bits 31:0 M1A[31:0] : Memory 1 address (used in case of Double buffer mode)

Base address of Memory area 1 from/to which the data will be read/written.

This register is used only for the Double buffer mode.

These bits are write-protected. They can be written only if:

– the stream is disabled (bit EN= '0' in the DMA_SxCR register) or

– the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '0' in the

DMA_SxCR register.

9.5.10 DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)

Address offset: 0x24 + 0x24 × stream number

Reset value: 0x0000 0021

29 28 27 26 25

13 12 11

Reserved

10 9

Reserved

FEIE rw

Reser ved

5 r

FS[2:0] r

3 r

DMDIS rw

17 16

1 0 rw

FTH[1:0] rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 FEIE : FIFO error interrupt enable

This bit is set and cleared by software.

0: FE interrupt disabled

1: FE interrupt enabled

Bit 6 Reserved, must be kept at reset value.

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RM0368 DMA controller (DMA)

Bits 5:3 FS[2:0] : FIFO status

These bits are read-only.

000: 0 < fifo_level < 1/4

001: 1/4 ≤ fifo_level < 1/2

010: 1/2 ≤ fifo_level < 3/4

011: 3/4 ≤ fifo_level < full

100: FIFO is empty

101: FIFO is full others: no meaning

These bits are not relevant in the direct mode (DMDIS bit is zero).

Bit 2 DMDIS : Direct mode disable

This bit is set and cleared by software. It can be set by hardware.

0: Direct mode enabled

1: Direct mode disabled

This bit is protected and can be written only if EN is ‘0’.

This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in

DMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’ because the direct mode is not allowed in the memory-to-memory configuration.

Bits 1:0 FTH[1:0] : FIFO threshold selection

These bits are set and cleared by software.

00: 1/4 full FIFO

01: 1/2 full FIFO

10: 3/4 full FIFO

11: full FIFO

These bits are not used in the direct mode when the DMIS value is zero.

These bits are protected and can be written only if EN is ‘0’.

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Offset

Table 37 summarizes the DMA registers.

Table 37. DMA register map and reset values

Register

0x0000

0x0004

DMA_LISR

Reset value

DMA_HISR

Reset value

DMA_LIFCR

0x0008

Reset value

Reserved

0 0 0 0

0 0 0 0 0 0

0 0 0

Reserved

0 0 0 0 0 0 0 0 0

0x000C

DMA_HIFCR

Reset value

Reserved

0 0 0 0

0 0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0

0x0010

DMA_S0CR

Reserved

0x0014

Reset value

DMA_S0NDTR

Reset value

0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDT[15:.]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0018

DMA_S0PAR

Reset value 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x001C

DMA_S0M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0020

DMA_S0M1AR

Reset value

0x0024

DMA_S0FCR

Reset value

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

0 1 0 0 0 0 1

0x0028

DMA_S1CR

0x002C

Reset value

DMA_S1NDTR

Reset value

Reserved

0 0 0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDT[15:.]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 37. DMA register map and reset values (continued)

Offset Register

DMA_S1PAR

0x0030

0x0034

Reset value

DMA_S1M0A R

Reset value

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0038

DMA_S1M1AR

Reset value

0x003C

DMA_S1FCR

Reset value

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

1 0 0 0 0 1

0x0040

DMA_S2CR

Reserved

0x0044

Reset value

DMA_S2NDTR

Reset value

0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDT[15:.]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0048

DMA_S2PAR

Reset value 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x004C

DMA_S2M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0050

DMA_S2M1AR

Reset value

0x0054

DMA_S2FCR

Reset value

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

1 0 0 0 0 1

0x0058

DMA_S3CR

Reserved

0x005C

Reset value

DMA_S3NDTR

Reset value

0x0060

DMA_S3PAR

Reset value

0 0 0 0 0

Reserved

0 0 0 0 0 0 0

NDT[15:.]

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0064

DMA_S3M0AR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 37. DMA register map and reset values (continued)

Offset Register

0x0068

DMA_S3M1AR

Reset value

0x006C

DMA_S3FCR

Reset value

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

0 1 0 0 0 0 1

0x0070

DMA_S4C R

Reserved

0x0074

0x0078

0x007C

0x0080

0x0084

Reset value

DMA_S4NDTR

Reset value

DMA_S4PAR

Reset value

DMA_S4M0AR

Reset value

DMA_S4M1AR

Reset value

DMA_S4FCR

Reset value

0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDT[15:.]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

1 0 0 0 0 1

0x0088

DMA_S5CR

Reserved

0x008C

0x0090

0x0094

0x0098

0x009C

Reset value

DMA_S5NDTR

Reset value

DMA_S5PAR

Reset value

DMA_S5M0AR

Reset value

DMA_S5M1AR

Reset value

DMA_S5FCR

Reset value

0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDT[15:.]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

1 0 0 0 0 1

0x00A0

DMA_S6CR

Reserved

0x00A4

0x00A8

Reset value

DMA_S6NDTR

Reset value

DMA_S6PAR

Reset value

0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NDT[15:.]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0368 DMA controller (DMA)

Table 37. DMA register map and reset values (continued)

Offset Register

0x00AC

0x00B0

DMA_S6M0AR

Reset value

DMA_S6M1AR

Reset value

0x00B4

DMA_S6FCR

Reset value

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

1 0 0 0 0 1

0x00B8

DMA_S7CR

Reserved

0x00BC

0x00C0

0x00C4

0x00C8

Reset value

DMA_S7NDTR

Reset value

DMA_S7PAR

Reset value

DMA_S7M0AR

Reset value

DMA_S7M1AR

Reset value

0x00CC

DMA_S7FCR

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

NDT[15:.]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M0A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M1A[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

FS[2:0]

FTH

[1:0]

1 0 0 0 0 1

Table 38 , for the vector table for the STM32F401xB/C and STM32F401xD/E devices.

for the register boundary addresses.

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10 Interrupts and events

10.1 Nested vectored interrupt controller (NVIC)

RM0368

The nested vector interrupt controller NVIC includes the following features:

• 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex ®

FPU)

-M4 with

• 16 programmable priority levels (4 bits of interrupt priority are used)

• low-latency exception and interrupt handling

• power management control

• implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214.

The SysTick calibration value is fixed to 10500, which gives a reference time base of 1 ms with the SysTick clock set to 10.5 MHz (HCLK/8, with HCLK set to 84 MHz).

10.1.3 Interrupt and exception vectors

See

The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type

(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests.

Table 38. Vector table for STM32F401xB/CSTM32F401xD/E

Type of priority

Acronym Description Address

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-3

fixed

Reset

RM0368 Rev 5

Reserved

Reset

0x0000 0000

0x0000 0004

RM0368 Interrupts and events

Table 38. Vector table for STM32F401xB/CSTM32F401xD/E (continued)

Type of priority

Acronym Description Address

-2

-1

21 fixed fixed settable settable settable

settable settable

settable settable settable settable settable settable settable settable settable settable settable settable settable settable settable settable

NMI

HardFault

MemManage

BusFault

UsageFault

SVCall

Debug Monitor

PendSV

Systick

WWDG

EXTI16 / PVD settable EXTI21 / TAMP_STAMP

EXTI22 / RTC_WKUP

FLASH

RCC

EXTI0

EXTI1

EXTI2

EXTI3

EXTI4

DMA1_Stream0

DMA1_Stream1

DMA1_Stream2

DMA1_Stream3

Non maskable interrupt, Clock Security

System

All class of fault

Memory management

Pre-fetch fault, memory access fault

Undefined instruction or illegal state

Reserved

System Service call via SWI instruction

Debug Monitor

Reserved

Pendable request for system service

System tick timer

Window Watchdog interrupt

EXTI Line 16 interrupt / PVD through EXTI line detection interrupt

EXTI Line 21 interrupt /

Tamper and TimeStamp interrupts through the EXTI line

EXTI Line 22 interrupt /

RTC Wakeup interrupt through the EXTI line

Flash global interrupt

RCC global interrupt

EXTI Line0 interrupt

EXTI Line1 interrupt

EXTI Line2 interrupt

EXTI Line3 interrupt

EXTI Line4 interrupt

DMA1 Stream0 global interrupt

DMA1 Stream1 global interrupt

DMA1 Stream2 global interrupt

DMA1 Stream3 global interrupt

0x0000 0008

0x0000 000C

0x0000 0010

0x0000 0014

0x0000 0018

0x0000 001C -

0x0000 002B

0x0000 002C

0x0000 0030

0x0000 0034

0x0000 0038

0x0000 003C

0x0000 0040

0x0000 0044

0x0000 0048

0x0000 004C

0x0000 0050

0x0000 0054

0x0000 0058

0x0000 005C

0x0000 0060

0x0000 0064

0x0000 0068

0x0000 006C

0x0000 0070

0x0000 0074

0x0000 0078

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Table 38. Vector table for STM32F401xB/CSTM32F401xD/E (continued)

RM0368

Type of priority

Acronym Description Address

32 settable settable settable settable settable settable settable

DMA1_Stream4

DMA1_Stream5

DMA1_Stream6

ADC

EXTI9_5 settable TIM1_TRG_COM_TIM11 settable settable settable settable settable settable settable settable settable settable settable settable settable settable settable settable settable settable settable

TIM1_BRK_TIM9

TIM1_UP_TIM10

TIM1_CC

TIM2

TIM3

TIM4

I2C1_EV

I2C1_ER

I2C2_EV

I2C2_ER

SPI1

SPI2

USART1

USART2

EXTI15_10

EXTI17 / RTC_Alarm

EXTI18 /

OTG_FS_WKUP

DMA1_Stream7

SDIO

TIM5

SPI3

DMA1 Stream4 global interrupt

DMA1 Stream5 global interrupt

DMA1 Stream6 global interrupt

ADC1 global interrupts

EXTI Line[9:5] interrupts

TIM1 Break interrupt and TIM9 global interrupt

TIM1 Update interrupt and TIM10 global interrupt

TIM1 Trigger and Commutation interrupts and TIM11 global interrupt

TIM1 Capture Compare interrupt

TIM2 global interrupt

TIM3 global interrupt

TIM4 global interrupt

C1 event interrupt

C1 error interrupt

C2 event interrupt

C2 error interrupt

SPI1 global interrupt

SPI2 global interrupt

USART1 global interrupt

USART2 global interrupt

EXTI Line[15:10] interrupts

EXTI Line 17 interrupt / RTC Alarms (A and

B) through EXTI line interrupt

EXTI Line 18 interrupt / USB On-The-Go

FS Wakeup through EXTI line interrupt

DMA1 Stream7 global interrupt

SDIO global interrupt

TIM5 global interrupt

SPI3 global interrupt

0x0000 007C

0x0000 0080

0x0000 0084

0x0000 0088

0x0000 009C

0x0000 00A0

0x0000 00A4

0x0000 00A8

0x0000 00AC

0x0000 00B0

0x0000 00B4

0x0000 00B8

0x0000 00BC

0x0000 00C0

0x0000 00C4

0x0000 00C8

0x0000 00CC

0x0000 00D0

0x0000 00D4

0x0000 00D8

0x0000 00E0

0x0000 00E4

0x0000 00E8

0x0000 00FC

0x0000 0104

0x0000 0108

0x0000 010C

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RM0368 Interrupts and events

Table 38. Vector table for STM32F401xB/CSTM32F401xD/E (continued)

Type of priority

Acronym Description Address

80 settable settable settable

88 Settable

91 settable settable settable settable settable settable settable settable settable settable

DMA2_Stream0

DMA2_Stream1

DMA2_Stream2

DMA2_Stream3

DMA2_Stream4

OTG_FS

DMA2_Stream5

DMA2_Stream6

DMA2_Stream7

USART6

I2C3_EV

I2C3_ER

FPU

SPI4

DMA2 Stream0 global interrupt

DMA2 Stream1 global interrupt

DMA2 Stream2 global interrupt

DMA2 Stream3 global interrupt

DMA2 Stream4 global interrupt

USB On The Go FS global interrupt

DMA2 Stream5 global interrupt

DMA2 Stream6 global interrupt

DMA2 Stream7 global interrupt

USART6 global interrupt

C3 event interrupt

C3 error interrupt

FPU global interrupt

SPI 4 global interrupt

0x0000 0120

0x0000 0124

0x0000 0128

0x0000 012C

0x0000 0130

0x0000 014C

0x0000 0150

0x0000 0154

0x0000 0158

0x0000 015C

0x0000 0160

0x0000 0164

0x0000 0184

0x0000 0190

10.2.1 EXTI main features

The main features of the EXTI controller are the following:

• independent trigger and mask on each interrupt/event line

• dedicated status bit for each interrupt line

• generation of up to 23 software event/interrupt requests

• detection of external signals with a pulse width lower than the APB2 clock period. Refer to the electrical characteristics section of the STM32F4xx datasheets for details on this parameter.

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Interrupts and events

Figure 29

shows the block diagram.

Figure 29. External interrupt/event controller block diagram

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RM0368

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The STM32F4xx are able to handle external or internal events in order to wake up the core

(WFE). The wakeup event can be generated either by:

• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex ® -M4 with FPU System Control register. When the

MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC

IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

• or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC

IRQ channel pending bit as the pending bit corresponding to the event line is not set.

To use an external line as a wakeup event, refer to

Section 10.2.4: Functional description

206/847

To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.

When the selected edge occurs on the external interrupt line, an interrupt request is

RM0368 Rev 5

RM0368 Interrupts and events generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register.

To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set.

An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register.

Hardware interrupt selection

To configure the 23 lines as interrupt sources, use the following procedure:

• Configure the mask bits of the 23 interrupt lines (EXTI_IMR)

• Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)

• Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines can be correctly acknowledged.

Hardware event selection

To configure the 23 lines as event sources, use the following procedure:

• Configure the mask bits of the 23 event lines (EXTI_EMR)

• Configure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

The 23 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.

• Configure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)

• Set the required bit in the software interrupt register (EXTI_SWIER)

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Interrupts and events RM0368

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Up to 81 GPIOs (STM32F401xB/C and STM32F401xD/E) are connected to the 16 external interrupt/event lines in the following manner:

Figure 30. External interrupt/event GPIO mapping

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The five other EXTI lines are connected as follows:

• EXTI line 16 is connected to the PVD output

• EXTI line 17 is connected to the RTC Alarm event

• EXTI line 18 is connected to the USB OTG FS Wakeup event

• EXTI line 21 is connected to the RTC Tamper and TimeStamp events

• EXTI line 22 is connected to the RTC Wakeup event

RM0368 Rev 5

RM0368 Interrupts and events

10.3

EXTI

registers

Refer to Section 1.1: List of abbreviations for registers

for a list of abbreviations used in register descriptions.

10.3.1 Interrupt mask register (EXTI_IMR)

Address offset: 0x00

Reset value: 0x0000 0000

31 30 29 28 27

Reserved

15 14 13 12 11 10

MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw

MR9 rw

MR8 rw

MR7 rw

22 21

MR22 MR21 rw rw

6 5

MR6 MR5 rw rw

20 19

Reserved

MR4 rw

MR3 rw

18 17 16

MR18 MR17 MR16 rw rw rw

2 1 0

MR2 MR1 MR0 rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 MRx: Interrupt mask on line x

0: Interrupt request from line x is masked

1: Interrupt request from line x is not masked

Address offset: 0x04

Reset value: 0x0000 0000

31 30 29 28 27

Reserved

15 14 13 12 11 10

MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw

MR9 rw

MR8 rw

MR7 rw

22 21

MR22 MR21 rw rw

6 5

MR6 rw

MR5 rw

20 19

Reserved

MR4 rw

MR3 rw

18 17 16

MR18 MR17 MR16 rw rw rw

2 1 0

MR2 rw

MR1 rw

MR0 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 MRx: Event mask on line x

0: Event request from line x is masked

1: Event request from line x is not masked

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Interrupts and events RM0368

Address offset: 0x08

Reset value: 0x0000 0000

31 30 29 28 27

Reserved

15 14 13 12 11 10

TR15 TR14 TR13 TR12 TR11 TR10 rw rw rw rw rw rw

TR9 rw

TR8 rw

TR7 rw

22 21

TR22 TR21 rw

6 rw

TR6 rw

TR5 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 TRx: Rising trigger event configuration bit of line x

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

20 19

Reserved

TR4 rw

TR3 rw

TR18 rw

TR2 rw

TR17 rw

TR1 rw

TR16 rw

TR0 rw

Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.

If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register, the pending bit is be set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

Address offset: 0x0C

Reset value: 0x0000 0000

31 30 29 28 27 26

Reserved

15 14 13 12 11 10

TR15 TR14 TR13 TR12 TR11 TR10 rw rw rw rw rw rw

TR9 rw

TR8 rw

TR7 rw

22 21

TR22 TR21 rw

6 rw

TR6 rw

TR5 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 TRx: Falling trigger event configuration bit of line x

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

20 19

Reserved

TR4 rw

TR3 rw

TR18 rw

TR2 rw

TR17 rw

TR1 rw

TR16 rw

TR0 rw

Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines.

If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

210/847

RM0368 Rev 5

RM0368 Interrupts and events

Address offset: 0x10

Reset value: 0x0000 0000

31 30 29 28 27

Reserved

26 25

SWIER

15 rw

SWIER

14 rw

SWIER

13 rw

SWIER

12 rw

SWIER

11 rw

SWIER

10 rw

SWIER

9 rw

SWIER

8 rw

SWIER

7 rw

SWIER

22 rw

SWIER

21 rw

SWIER

6 rw

SWIER

5 rw

SWIER

4 rw

Reserved

SWIER

3 rw

SWIER

18 rw

SWIER

2 rw

SWIER

17 rw

SWIER

1 rw

SWIER

16 rw

SWIER

0 rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 SWIERx: Software Interrupt on line x

If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).

10.3.6 Pending register (EXTI_PR)

Address offset: 0x14

Reset value: undefined

31 30 29 28 27

Reserved

PR10

PR9

PR8

PR7

22 21

PR22 PR21 rc_w1 rc_w1

6 5

Reserved

PR4

PR3

PR18

PR17

PR16 rc_w1 rc_w1 rc_w1

2 1 0 15

PR15

PR14

PR13

PR12

PR11 PR6 PR5 PR2 PR1 PR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 PRx: Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by programming it to ‘1’.

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Interrupts and events

10.3.7 EXTI register map

Table 39 gives the EXTI register map and the reset values.

Table 39. External interrupt/event controller register map and reset values

RM0368

Offset Register

0x00

0x04

0x08

0x0C

0x10

0x14

EXTI_IMR

Reset value

EXTI_EMR

Reset value

EXTI_RTSR

Reset value

EXTI_FTSR

Reset value

EXTI_SWIER

Reset value

EXTI_PR

Reset value

Reserved

[22:21] Reser ved

0 0

MR[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[22:21] Reser ved

0 0

MR[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[22:21] Reser ved

0 0

TR[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[22:21] Reser ved

0 0

TR[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SWIER

[22:21] Reser ved

0 0

SWIER[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[22:21] Reser ved

0 0

PR[18:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

shows a single ADC block diagram and Table 40

for the register boundary addresses.

212/847

RM0368 Rev 5

RM0368

11

Analog-to-digital converter (ADC)

Analog-to-digital converter (ADC)

ADC2 and ADC3 are not available in STM32F401xB/C and STM32F401xD/E.

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V

BAT

channel. The A/D conversion of the channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored into a left- or right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes beyond the user-defined, higher or lower thresholds.

11.2 ADC main features

Note:

• 12-bit, 10-bit, 8-bit or 6-bit configurable resolution

• Interrupt generation at the end of conversion, end of injected conversion, and in case of analog watchdog or overrun events

• Single and continuous conversion modes

• Scan mode for automatic conversion of channel 0 to channel ‘n’

• Data alignment with in-built data coherency

• Channel-wise programmable sampling time

• External trigger option with configurable polarity for both regular and injected conversions

• Discontinuous mode

• ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed

• ADC input range: V

REF –

≤

REF+

• DMA request generation during regular channel conversion

Figure 31

shows the block diagram of the ADC.

REF–

, if available (depending on package), must be tied to V

SSA

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Analog-to-digital converter (ADC) RM0368

11.3 ADC functional description

Figure 31

gives the ADC pin description.

Figure 31. Single ADC block diagram

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214/847

RM0368 Rev 5

RM0368 Analog-to-digital converter (ADC)

REF+

DDA

Name Signal type

Input, analog reference positive

Input, analog supply

Table 40. ADC pins

REF–

SSA

Input, analog reference negative

Input, analog supply ground

ADCx_IN[15:0] Analog input signals

Remarks

The higher/positive reference voltage for the ADC,

1.8 V ≤ V

REF+

≤

DDA

Analog power supply equal to V

2.4 V

1.8 V

≤

DDA

≤

and

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(3.6 V) for reduced speed

The lower/negative reference voltage for the ADC,

REF–

= V

SSA

Ground for analog power supply equal to V

16 analog input channels

The ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from the Power-down mode.

Conversion starts when either the SWSTART or the JSWSTART bit is set.

You can stop conversion and put the ADC in power down mode by clearing the ADON bit. In this mode the ADC consumes almost no power (only a few µA).

The ADC features two clock schemes:

• Clock for the analog circuitry: ADCCLK

This clock is generated from the APB2 clock divided by a programmable prescaler that allows the ADC to work at f

PCLK2 maximum value of ADCCLK.

/2, /4, /6 or /8. Refer to the datasheets for the

• Clock for the digital interface (used for registers read/write access)

This clock is equal to the APB2 clock. The digital interface clock can be enabled/disabled individually for each ADC through the RCC APB2 peripheral clock enable register (RCC_APB2ENR).

There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0,

ADC_IN2, ADC_IN2, ADC_IN15.

• A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the

ADC_SQR1 register.

• An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register.

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Analog-to-digital converter (ADC) RM0368

Note:

The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register.

If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.

Temperature sensor, V

REFINT

and V

BAT

internal channels

• The temperature sensor is internally connected to ADC1_IN18 channel which is shared with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a time. When the temperature sensor and VBAT conversion are set simultaneously, only the VBAT conversion is performed.

The internal reference voltage VREFINT is connected to ADC1_IN17.

The V

BAT channel (connected to channel ADC1_IN18) can also be converted as an injected or regular channel.

The temperature sensor, V

REFINT

ADC1 peripheral.

and the V

BAT channel are available only on the master

11.3.4 Single conversion mode

In Single conversion mode the ADC does one conversion. This mode is started with the

CONT bit at 0 by either:

• setting the SWSTART bit in the ADC_CR2 register (for a regular channel only)

• setting the JSWSTART bit (for an injected channel)

• external trigger (for a regular or injected channel)

Once the conversion of the selected channel is complete:

• If a regular channel was converted:

– The converted data are stored into the 16-bit ADC_DR register

– The EOC (end of conversion) flag is set

– An interrupt is generated if the EOCIE bit is set

• If an injected channel was converted:

– The converted data are stored into the 16-bit ADC_JDR1 register

– The JEOC (end of conversion injected) flag is set

– An interrupt is generated if the JEOCIE bit is set

Then the ADC stops.

11.3.5 Continuous conversion mode

In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one.

This mode is started with the CONT bit at 1 either by external trigger or by setting the

SWSTRT bit in the ADC_CR2 register (for regular channels only).

After each conversion:

• If a regular group of channels was converted:

– The last converted data are stored into the 16-bit ADC_DR register

– The EOC (end of conversion) flag is set

– An interrupt is generated if the EOCIE bit is set

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RM0368 Rev 5

RM0368

Note:

Analog-to-digital converter (ADC)

Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous

mode (using JAUTO bit), refer to Auto-injection

section)

.

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Figure 32

, the ADC needs a stabilization time of t

STAB

before it starts converting accurately. After the start of the ADC conversion and after 15 clock cycles, the

EOC flag is set and the 16-bit ADC data register contains the result of the conversion.

Figure 32. Timing diagram

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The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register.

The threshold value is independent of the alignment selected by the ALIGN bit in the

ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds before alignment.

Table 41 shows how the ADC_CR1 register should be configured to enable the analog

watchdog on one or more channels.

Figure 33. Analog watchdog’s guarded area

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RM0368 Rev 5

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242

Analog-to-digital converter (ADC) RM0368

Table 41. Analog watchdog channel selection

ADC_CR1 register control bits (x = don’t care)

Channels guarded by the analog watchdog

AWDSGL bit AWDEN bit JAWDEN bit

None

All injected channels

All regular channels

All regular and injected channels

Single

(1)

injected channel

Single

(1) regular or injected channel

regular channel

Single

1. Selected by the AWDCH[4:0] bits

1 x

This mode is used to scan a group of analog channels.

The Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit has been set, the ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR register (for injected channels). A single conversion is performed for each channel of the group. After each end of conversion, the next channel in the group is converted automatically. If the CONT bit is set, regular channel conversion does not stop at the last selected channel in the group but continues again from the first selected channel.

If the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data converted from the regular group of channels (stored in the ADC_DR register) to SRAM after each regular channel conversion.

The EOC bit is set in the ADC_SR register:

• At the end of each regular group sequence if the EOCS bit is cleared to 0

• At the end of each regular channel conversion if the EOCS bit is set to 1

The data converted from an injected channel are always stored into the ADC_JDRx registers.

11.3.9 Injected channel management

Triggered injection

To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.

Start the conversion of a group of regular channels either by external trigger or by setting the SWSTART bit in the ADC_CR2 register.

2. If an external injected trigger occurs or if the JSWSTART bit is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches to Scan-once mode.

3. Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion.

If a regular event occurs during an injected conversion, the injected conversion is not

218/847

RM0368 Rev 5

RM0368

Note:

Analog-to-digital converter (ADC) interrupted but the regular sequence is executed at the end of the injected sequence.

Figure 34

shows the corresponding timing diagram.

When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 30 ADC clock cycles (that is two conversions with a sampling time of 3 clock periods), the minimum interval between triggers must be 31 ADC clock cycles.

Auto-injection

If the JAUTO bit is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers.

In this mode, external trigger on injected channels must be disabled.

If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted.

It is not possible to use both the auto-injected and discontinuous modes simultaneously.

Figure 34. Injected conversion latency

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1. The maximum latency value can be found in the electrical characteristics of the STM32F401xB/C and

STM32F401xD/E datasheets.

Regular group

This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADC_SQRx registers. The value of n is specified by writing to the

DISCNUM[2:0] bits in the ADC_CR1 register.

When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register.

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Analog-to-digital converter (ADC)

Note:

RM0368

Example:

• n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10

• 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion.

• 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion

• 3rd trigger: sequence converted 9, 10.An EOC event is generated at each conversion

• 4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion

When a regular group is converted in discontinuous mode, no rollover occurs.

When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the

1st subgroup.

Injected group

This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event.

When an external trigger occurs, it starts the next channel conversions selected in the

ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register.

Example: n = 1, channels to be converted = 1, 2, 3

1st trigger: channel 1 converted

2nd trigger: channel 2 converted

3rd trigger: channel 3 converted and JEOC event generated

4th trigger: channel 1

When all injected channels are converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel

It is not possible to use both the auto-injected and discontinuous modes simultaneously.

Discontinuous mode must not be set for regular and injected groups at the same time.

Discontinuous mode must be enabled only for the conversion of one group.

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RM0368 Rev 5

RM0368 Analog-to-digital converter (ADC)

The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in

Figure 35

and

Figure 36

The converted data value from the injected group of channels is decreased by the userdefined offset written in the ADC_JOFRx registers so the result can be a negative value.

The SEXT bit represents the extended sign value.

For channels in a regular group, no offset is subtracted so only twelve bits are significant.

Figure 35. Right alignment of 12-bit data

)NJECTEDGROUP

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2EGULARGROUP

$ $ $ $ $ $ $ $ $ $ $ $

Figure 36. Left alignment of 12-bit data

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3%84 $ $ $ $ $ $ $

2EGULARGROUP

$ $ $ $ $ $ $ $

$ $ $ $ $

$ $ $ $

Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in

Figure 37

Figure 37. Left alignment of 6-bit data

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Analog-to-digital converter (ADC) RM0368

11.5 Channel-wise programmable sampling time

The ADC samples the input voltage for a number of ADCCLK cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sampling time.

The total conversion time is calculated as follows:

T conv

= Sampling time + 12 cycles

Example:

With ADCCLK = 30 MHz and sampling time = 3 cycles:

T conv

= 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz

11.6 Conversion on external trigger and trigger polarity

Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the

EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from “0b00”, then external events are able to trigger a conversion

with the selected polarity. Table 42

provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity.

Table 42. Configuring the trigger polarity

Source EXTEN[1:0] / JEXTEN[1:0]

Trigger detection disabled

Detection on the rising edge

Detection on the falling edge

Detection on both the rising and falling edges

Note: The polarity of the external trigger can be changed on the fly.

The EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible events can trigger conversion for the regular and injected groups.

Table 43 gives the possible external trigger for regular conversion.

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Source

TIM1_CH1 event

TIM1_CH2 event

TIM1_CH3 event

TIM2_CH2 event

TIM2_CH3 event

TIM2_CH4 event

TIM2_TRGO event

TIM3_CH1 event

TIM3_TRGO event

TIM4_CH4 event

TIM5_CH1 event

TIM5_CH2 event

TIM5_CH3 event

Reserved

EXTI line11

Table 43. External trigger for regular channels

Type EXTSEL[3:0]

Internal signal from on-chip timers

External pin

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

Table 44 gives the possible external trigger for injected conversion.

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Note:

RM0368

Source

Table 44. External trigger for injected channels

Connection type JEXTSEL[3:0]

TIM1_CH4 event

TIM1_TRGO event

TIM2_CH1 event

TIM2_TRGO event

TIM3_CH2 event

TIM3_CH4 event

TIM4_CH1 event

TIM4_CH2 event

TIM4_CH3 event

TIM4_TRGO event

TIM5_CH4 event

TIM5_TRGO event

Reserved

EXTI line15

Internal signal from on-chip timers

External pin

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

Software source trigger events can be generated by setting SWSTART (for regular conversion) or JSWSTART (for injected conversion) in ADC_CR2.

A regular group conversion can be interrupted by an injected trigger.

The trigger selection can be changed on the fly. However, when the selection changes, there is a time frame of 1 APB clock cycle during which the trigger detection is disabled.

This is to avoid spurious detection during transitions.

11.7 Fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution. The RES bits are used to select the number of bits available in the data register. The minimum conversion time for each resolution is then as follows:

• 12 bits: 3 + 12 = 15 ADCCLK cycles

• 10 bits: 3 + 10 = 13 ADCCLK cycles

• 8 bits: 3 + 8 = 11 ADCCLK cycles

• 6 bits: 3 + 6 = 9 ADCCLK cycles

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11.8.1 Using the DMA

Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.

When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each conversion of a regular channel, a DMA request is generated. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

Despite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an interrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and

DMA requests are no longer accepted. In this case, if a DMA request is made, the regular conversion in progress is aborted and further regular triggers are ignored. It is then necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to reinitialize both the DMA and the ADC to have the wanted converted channel data transferred to the right memory location. Only then can the conversion be resumed and the data transfer, enabled again. Injected channel conversions are not impacted by overrun errors.

When OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have been transferred, which means that all the data transferred to the RAM can be considered as valid.

At the end of the last DMA transfer (number of transfers configured in the DMA controller’s

DMA_SxNTR register):

• No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the

ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is not cleared by hardware. It must be written to 0, then to 1 to start a new transfer.

• Requests can continue to be generated if the DDS bit is set to 1. This allows configuring the DMA in double-buffer circular mode.

To recover the ADC from OVR state when the DMA is used, follow the steps below:

Reinitialize the DMA (adjust destination address and NDTR counter)

2. Clear the ADC OVR bit in ADC_SR register

3. Trigger the ADC to start the conversion.

11.8.2 Managing a sequence of conversions without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status bit to be set at the end of each conversion, and not only at the end of the sequence. When

EOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is complete, EOC is set and the ADC_DR register can be read. The overrun management is the same as when the DMA is used.

To recover the ADC from OVR state when the EOCS is set, follow the steps below:

Clear the ADC OVR bit in ADC_SR register

2. Trigger the ADC to start the conversion.

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11.8.3 Conversions without DMA and without overrun detection

It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled

(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this configuration, overrun detection is disabled.

Note:

The temperature sensor can be used to measure the ambient temperature (T

A device.

) of the

Figure 38

shows the block diagram of the temperature sensor.

When not in use, the sensor can be put in power down mode.

The TSVREFE bit must be set to enable the conversion of both internal channels: the

ADC1_IN16 or ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT).

Main features

• Supported temperature range: –40 to 125 °C

• Precision: ±1.5 °C

Figure 38. Temperature sensor and V

REFINT

channel block diagram

4362%&%CONTROLBIT

4EMPERATURE

SENSOR

)NTERNAL

POWERBLOCK

63%.3%

!$#?).

!$#

62%&).4

!$#?).

CONVERTEDDATA

-36

1. V

SENSE

is input to ADC1_IN18

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Reading the temperature

To use the sensor:

3. Select ADC1_IN16 or ADC1_IN18 input channel.

4. Select a sampling time greater than the minimum sampling time specified in the datasheet.

5. Set the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor from power down mode

6. Start the ADC conversion by setting the SWSTART bit (or by external trigger)

7. Read the resulting V

SENSE

data in the ADC data register

8. Calculate the temperature using the following formula:

Temperature (in °C) = {(V

SENSE

– V

) / Avg_Slope} + 25

Where:

– V

= V

SENSE

value for 25° C

– Avg_Slope = average slope of the temperature vs. V

SENSE or µV/°C)

curve (given in mV/°C

Refer to the datasheet’s electrical characteristics section for the actual values of V

25 and Avg_Slope.

The sensor has a startup time after waking from power down mode before it can output

SENSE

at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADON and TSVREFE bits should be set at the same time.

The temperature sensor output voltage changes linearly with temperature. The offset of this linear function depends on each chip due to process variation (up to 45 °C from one chip to another).

The internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. If accurate temperature reading is required, an external temperature sensor should be used.

11.10 Battery charge monitoring

Note:

The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the

BAT

voltage could be higher than V

DDA

, to ensure the correct operation of the ADC, the

pin is internally connected to a bridge divider.

When the VBATE is set, the bridge is automatically enabled to connect:

• VBAT/4 to the ADC1_IN18 input channel

The VBAT and temperature sensor are connected to the same ADC internal channel

(ADC1_IN18). Only one conversion, either temperature sensor or VBAT, must be selected at a time. When both conversion are enabled simultaneously, only the VBAT conversion is performed.

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An interrupt can be produced on the end of conversion for regular and injected groups, when the analog watchdog status bit is set and when the overrun status bit is set. Separate interrupt enable bits are available for flexibility.

Two other flags are present in the ADC_SR register, but there is no interrupt associated with them:

• JSTRT (Start of conversion for channels of an injected group)

• STRT (Start of conversion for channels of a regular group)

Table 45. ADC interrupts

Interrupt event Event flag

End of conversion of a regular group

End of conversion of an injected group

Analog watchdog status bit is set

Overrun

EOC

JEOC

AWD

OVR

Enable control bit

EOCIE

JEOCIE

AWDIE

OVRIE

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Refer to

Section 1.1: List of abbreviations for registers for registers

for a list of abbreviations used in register descriptions.

The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

11.12.1 ADC status register (ADC_SR)

Address offset: 0x00

Reset value: 0x0000 0000

30 29

28 27 26

11 10

Reserved

25 24 23

Reserved

8 7

22 21 20 19 18 17 16

13 12 9 6 5

OVR

STRT

JSTRT

2 1

JEOC EOC

AWD rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 OVR: Overrun

This bit is set by hardware when data are lost . It is cleared by software. Overrun detection is enabled only when DMA = 1 or EOCS = 1.

0: No overrun occurred

1: Overrun has occurred

Bit 4 STRT: Regular channel start flag

This bit is set by hardware when regular channel conversion starts. It is cleared by software.

0: No regular channel conversion started

1: Regular channel conversion has started

Bit 3 JSTRT: Injected channel start flag

This bit is set by hardware when injected group conversion starts. It is cleared by software.

0: No injected group conversion started

1: Injected group conversion has started

Bit 2 JEOC: Injected channel end of conversion

This bit is set by hardware at the end of the conversion of all injected channels in the group.

It is cleared by software.

0: Conversion is not complete

1: Conversion complete

Bit 1 EOC: Regular channel end of conversion

This bit is set by hardware at the end of the conversion of a regular group of channels. It is cleared by software or by reading the ADC_DR register.

0: Conversion not complete (EOCS=0), or sequence of conversions not complete (EOCS=1)

1: Conversion complete (EOCS=0), or sequence of conversions complete (EOCS=1)

Bit 0 AWD: Analog watchdog flag

This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software.

0: No analog watchdog event occurred

1: Analog watchdog event occurred

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Address offset: 0x04

Reset value: 0x0000 0000

15 rw

Reserved

DISCNUM[2:0] rw

13 rw

JDISCE

N rw

DISC

EN rw

OVRIE rw

25 rw

RES

JAUTO rw

AWDSG

L rw

24 rw

23 rw

AWDEN JAWDEN rw

SCAN JEOCIE AWDIE EOCIE rw rw rw

5 rw

19 18

Reserved

3 2 1 rw

AWDCH[4:0] rw rw

0 rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the Overrun interrupt.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Bits 25:24 RES[1:0]: Resolution

These bits are written by software to select the resolution of the conversion.

00: 12-bit (15 ADCCLK cycles)

01: 10-bit (13 ADCCLK cycles)

10: 8-bit (11 ADCCLK cycles)

11: 6-bit (9 ADCCLK cycles)

Bit 23 AWDEN: Analog watchdog enable on regular channels

This bit is set and cleared by software.

0: Analog watchdog disabled on regular channels

1: Analog watchdog enabled on regular channels

Bit 22 JAWDEN: Analog watchdog enable on injected channels

This bit is set and cleared by software.

0: Analog watchdog disabled on injected channels

1: Analog watchdog enabled on injected channels

Bits 21:16 Reserved, must be kept at reset value.

Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger.

000: 1 channel

001: 2 channels

...

111: 8 channels

Bit 12 JDISCEN: Discontinuous mode on injected channels

This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group.

0: Discontinuous mode on injected channels disabled

1: Discontinuous mode on injected channels enabled

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Bit 11 DISCEN: Discontinuous mode on regular channels

This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels.

0: Discontinuous mode on regular channels disabled

1: Discontinuous mode on regular channels enabled

Bit 10 JAUTO: Automatic injected group conversion

This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.

0: Automatic injected group conversion disabled

1: Automatic injected group conversion enabled

Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode

This bit is set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits.

0: Analog watchdog enabled on all channels

1: Analog watchdog enabled on a single channel

Bit 8 SCAN: Scan mode

This bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.

0: Scan mode disabled

1: Scan mode enabled

Note: An EOC interrupt is generated if the EOCIE bit is set:

– At the end of each regular group sequence if the EOCS bit is cleared to 0

– At the end of each regular channel conversion if the EOCS bit is set to 1

Note: A JEOC interrupt is generated only on the end of conversion of the last channel if the

JEOCIE bit is set.

Bit 7 JEOCIE: Interrupt enable for injected channels

This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels.

0: JEOC interrupt disabled

1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.

Bit 6 AWDIE: Analog watchdog interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled

1: Analog watchdog interrupt enabled

Bit 5 EOCIE: Interrupt enable for EOC

This bit is set and cleared by software to enable/disable the end of conversion interrupt.

0: EOC interrupt disabled

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

Note: 00000: ADC analog input Channel0

00001: ADC analog input Channel1

...

01111: ADC analog input Channel15

10000: ADC analog input Channel16

10001: ADC analog input Channel17

10010: ADC analog input Channel18

Other values reserved

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Address offset: 0x08

Reset value: 0x0000 0000

31 reserved

SWST

ART rw

29 rw

EXTEN

28 rw

12 reserved

27 26 25

EXTSEL[3:0] rw

11 rw

10 rw

ALIGN EOCS DDS rw rw rw

24 rw

DMA rw

23 reserved

JSWST

ART rw

JEXTEN

20 rw

5 rw

Reserved

19 rw

18 17

JEXTSEL[3:0] rw

16 rw

1 rw

CONT ADON rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 SWSTART: Start conversion of regular channels

This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.

0: Reset state

1: Starts conversion of regular channels

Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.

Bits 29:28 EXTEN: External trigger enable for regular channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group.

00: Trigger detection disabled

01: Trigger detection on the rising edge

10: Trigger detection on the falling edge

11: Trigger detection on both the rising and falling edges

Bits 27:24 EXTSEL[3:0]: External event select for regular group

These bits select the external event used to trigger the start of conversion of a regular group:

0000: Timer 1 CC1 event

0001: Timer 1 CC2 event

0010: Timer 1 CC3 event

0011: Timer 2 CC2 event

0100: Timer 2 CC3 event

0101: Timer 2 CC4 event

0110: Timer 2 TRGO event

0111: Timer 3 CC1 event

1000: Timer 3 TRGO event

1001: Timer 4 CC4 event

1010: Timer 5 CC1 event

1011: Timer 5 CC2 event

1100: Timer 5 CC3 event

1101: Reserved

1110: Reserved

1111: EXTI line11

Bit 23 Reserved, must be kept at reset value.

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Bit 22 JSWSTART: Start conversion of injected channels

This bit is set by software and cleared by hardware as soon as the conversion starts.

0: Reset state

1: Starts conversion of injected channels

Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.

Bits 21:20 JEXTEN: External trigger enable for injected channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.

00: Trigger detection disabled

01: Trigger detection on the rising edge

10: Trigger detection on the falling edge

11: Trigger detection on both the rising and falling edges

Bits 19:16 JEXTSEL[3:0]: External event select for injected group

These bits select the external event used to trigger the start of conversion of an injected group.

0000: Timer 1 CC4 event

0001: Timer 1 TRGO event

0010: Timer 2 CC1 event

0011: Timer 2 TRGO event

0100: Timer 3 CC2 event

0101: Timer 3 CC4 event

0110: Timer 4 CC1 event

0111: Timer 4 CC2 event

1000: Timer 4 CC3 event

1001: Timer 4 TRGO event

1010: Timer 5 CC4 event

1011: Timer 5 TRGO event

1100: Reserved

1101: Reserved

1110: Reserved

1111: EXTI line15

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 ALIGN: Data alignment

This bit is set and cleared by software. Refer to Figure 35 and Figure 36

0: Right alignment

1: Left alignment

Bit 10 EOCS: End of conversion selection

This bit is set and cleared by software.

0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection is enabled only if DMA=1.

1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.

Bit 9 DDS: DMA disable selection (for single ADC mode)

This bit is set and cleared by software.

0: No new DMA request is issued after the last transfer (as configured in the DMA controller)

1: DMA requests are issued as long as data are converted and DMA=1

Bit 8 DMA: Direct memory access mode (for single ADC mode)

This bit is set and cleared by software. Refer to the DMA controller chapter for more details.

0: DMA mode disabled

1: DMA mode enabled

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Bits 7:2 Reserved, must be kept at reset value.

Bit 1 CONT: Continuous conversion

This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Bit 0 ADON: A/D Converter ON / OFF

This bit is set and cleared by software.

Note: 0: Disable ADC conversion and go to power down mode

1: Enable ADC

Address offset: 0x0C

Reset value: 0x0000 0000

SMP15_0 rw

30 29 28

Reserved

14 13

SMP14[2:0]

12 rw rw rw

11 rw

26 rw

SMP18[2:0] rw

SMP13[2:0] rw rw

24 rw

8 rw

23 rw

SMP17[2:0] rw

SMP12[2:0] rw rw

21 rw

5 rw

20 rw

SMP16[2:0] rw

SMP11[2:0] rw rw

18 rw

2 rw

SMP10[2:0]

SMP15[2:1] rw rw

0 rw rw

Bits 31: 27 Reserved, must be kept at reset value.

Bits 26:0 SMPx[2:0]: Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel.

During sampling cycles, the channel selection bits must remain unchanged.

Note: 000: 3 cycles

001: 15 cycles

010: 28 cycles

011: 56 cycles

100: 84 cycles

101: 112 cycles

110: 144 cycles

111: 480 cycles

Address offset: 0x10

Reset value: 0x0000 0000

SMP

5_0 rw

Reserved

29 rw

SMP9[2:0] rw

27 rw

11 rw

SMP4[2:0] rw rw rw

26 rw

SMP8[2:0] rw

SMP3[2:0] rw rw

24 rw

8 rw

23 rw

SMP2[2:0] rw

SMP7[2:0] rw

6 rw

21 rw

5 rw

20 rw

SMP1[2:0] rw

SMP6[2:0] rw

3 rw

18 rw

2 rw

17 16

SMP5[2:1] rw

1 rw

SMP0[2:0] rw rw

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Bits 31:30 Reserved, must be kept at reset value.

Bits 29:0 SMPx[2:0]: Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel.

During sample cycles, the channel selection bits must remain unchanged.

Note: 000: 3 cycles

001: 15 cycles

010: 28 cycles

011: 56 cycles

100: 84 cycles

101: 112 cycles

110: 144 cycles

111: 480 cycles

11.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)

Address offset: 0x14-0x20

Reset value: 0x0000 0000

30 29

14 13

Reserved

28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

12 11 rw

10 rw

9 rw rw rw

6 5

JOFFSETx[11:0] rw rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x

These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers.

11.12.7 ADC watchdog higher threshold register (ADC_HTR)

Address offset: 0x24

Reset value: 0x0000 0FFF

30 29

14 13

Reserved

28 27 26 25 24 23

Reserved

22 21 20 19 18 17 16

12 11 rw

10 rw

9 rw rw rw

6 5 rw

HT[11:0] rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 HT[11:0]: Analog watchdog higher threshold

These bits are written by software to define the higher threshold for the analog watchdog.

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Note: The software can write to these registers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed.

11.12.8 ADC watchdog lower threshold register (ADC_LTR)

Address offset: 0x28

Reset value: 0x0000 0000

30 29

14 13

Reserved

28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

12 11 rw

10 rw

9 rw rw rw

LT[11:0]

5 rw rw

4 rw

3 rw

2 rw

1 rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 LT[11:0]: Analog watchdog lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

0 rw

Address offset: 0x2C

Reset value: 0x0000 0000

SQ16_0 rw

14 rw

29 28 27

Reserved

13 rw

SQ15[4:0] rw

11 rw

23 rw

SQ14[4:0]

L[3:0]

21 rw

6 rw

5 rw

20 rw

19 rw

3 rw

SQ13[4:0]

SQ16[4:1] rw rw

1 rw rw

16 rw

0 rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 L[3:0]: Regular channel sequence length

These bits are written by software to define the total number of conversions in the regular channel conversion sequence.

0000: 1 conversion

0001: 2 conversions

...

1111: 16 conversions

Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence

These bits are written by software with the channel number (0..18) assigned as the 16th in the conversion sequence.

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Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence

Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence

Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence

Analog-to-digital converter (ADC)

Address offset: 0x30

Reset value: 0x0000 0000

SQ10_0 rw

Reserved

14 rw

29 rw

13 rw

28 rw

SQ9[4:0]

SQ12[4:0] rw

11 rw rw

26 rw

10 rw

25 rw

24 rw

8 rw

23 rw

SQ8[4:0]

SQ11[4:0] rw

6 rw rw

21 rw

5 rw

20 rw

19 rw

3 rw

SQ7[4:0]

SQ10[4:1] rw rw

1 rw rw

16 rw

0 rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence

These bits are written by software with the channel number (0..18

) assigned as the 12th in the sequence to be converted.

Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence

Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence

Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence

Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence

Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence

Address offset: 0x34

Reset value: 0x0000 0000

31 30

Reserved

SQ4_0 rw

14 rw

29 rw

13 rw

28 rw

SQ3[4:0]

SQ6[4:0] rw

11 rw rw

26 rw

10 rw

25 rw

24 rw

8 rw

23 rw

SQ2[4:0]

SQ5[4:0] rw

6 rw rw

21 rw

5 rw

20 rw

19 rw

3 rw

SQ1[4:0]

SQ4[4:1] rw rw

1 rw rw

16 rw

0 rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence

These bits are written by software with the channel number (0..18) assigned as the 6th in the sequence to be converted.

Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence

RM0368 Rev 5

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Analog-to-digital converter (ADC) RM0368

Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence

Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence

Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence

Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence

11.12.12 ADC injected sequence register (ADC_JSQR)

Address offset: 0x38

Reset value: 0x0000 0000

JSQ4[0] rw

14 rw

29 28

13 rw

JSQ3[4:0] rw

11 rw

27 26

Reserved

10 rw

24 23 22

8 rw

JSQ2[4:0] rw

6 rw

JL[1:0]

20 rw

5 rw

19 rw

3 rw

18 17

JSQ4[4:1] rw

2 rw

JSQ1[4:0] rw rw

16 rw

0 rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:20 JL[1:0]: Injected sequence length

These bits are written by software to define the total number of conversions in the injected channel conversion sequence.

00: 1 conversion

01: 2 conversions

10: 3 conversions

11: 4 conversions

Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below)

These bits are written by software with the channel number (0..18) assigned as the 4th in the sequence to be converted.

Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below)

Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below)

Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below)

Note: When JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels in the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].

When JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the following order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].

When JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in starting from JSQ3[4:0], and then JSQ4[4:0].

When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel.

238/847

RM0368 Rev 5

RM0368 Analog-to-digital converter (ADC)

11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)

Address offset: 0x3C - 0x48

Reset value: 0x0000 0000

15 r

30 29

14 r

13 r

12 r

11 r

10 r

9 r

24 23

Reserved

8 7

JDATA[15:0] r r

6 r

5 r

4 r

3 r

2 r

1 r

0 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 JDATA[15:0]: Injected data

These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in

Figure 35 and Figure 36 .

11.12.14 ADC regular data register (ADC_DR)

Address offset: 0x4C

Reset value: 0x0000 0000

31 30 29 28 27 26 25

15 r

14 r

13 r

12 r

11 r

10 r

9 r

24 23

Reserved

8 7

DATA[15:0] r r

6 r

5 r

4 r

3 r

2 r

1 r

0 r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0]: Regular data

These bits are read-only. They contain the conversion result from the regular

channels. The data are left- or right-aligned as shown in Figure 35

and

Figure 36

Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)

Reset value: 0x0000 0000

Reserved

TSVREFE VBATE rw rw

20 19

Reserved

4 3

17 16 rw

ADCPRE rw

1 0

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Analog-to-digital converter (ADC) RM0368

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 TSVREFE: Temperature sensor and V

REFINT

enable

This bit is set and cleared by software to enable/disable the temperature sensor and the

REFINT

channel.

0: Temperature sensor and V

REFINT

1: Temperature sensor and V

REFINT

channel disabled

channel enabled

Note: VBATE must be disabled when TSVREFE is set. If both bits are set, only the VBAT conversion is performed.

Bit 22 VBATE: V

BAT enable

This bit is set and cleared by software to enable/disable the V

BAT

0: V

BAT

1: V

BAT

channel disabled

channel enabled

channel.

Bits 21:18 Reserved, must be kept at reset value.

Bits 17:16 ADCPRE: ADC prescaler

Set and cleared by software to select the frequency of the clock to the ADC. .

Note: 00: PCLK2 divided by 2

01: PCLK2 divided by 4

10: PCLK2 divided by 6

11: PCLK2 divided by 8

Bits 15:0 Reserved, must be kept at reset value.

11.12.16 ADC register map

The following table summarizes the ADC registers.

Offset

0x000 - 0x04C

0x050 - 0x0FC

0x100 - 0x14C

0x118 - 0x1FC

0x200 - 0x24C

0x250 - 0x2FC

0x300 - 0x308

Table 46. ADC global register map

Register

ADC1

Reserved

Common registers

240/847

RM0368 Rev 5

RM0368 Analog-to-digital converter (ADC)

Table 47. ADC register map and reset values for each ADC

Offset Register

0x38

0x3C

0x40

0x44

0x48

0x4C

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x00

0x04

0x08

0x30

0x34

ADC_SR

Reset value

Reserved

0 0 0 0 0 0

ADC_CR1

Reset value

ADC_CR2

Reset value

ADC_SMPR1

Reset value

ADC_SMPR2

Reset value

ADC_JOFR1

Reset value

ADC_JOFR2

Reset value

ADC_JOFR3

Reset value

ADC_JOFR4

Reset value

ADC_HTR

Reset value

ADC_LTR

Reset value

ADC_SQR1

Reset value

ADC_SQR2

Reset value

ADC_SQR3

Reset value

ADC_JSQR

Reset value

ADC_JDR1

Reset value

ADC_JDR2

Reset value

ADC_JDR3

Reset value

ADC_JDR4

Reset value

ADC_DR

Reset value

Reserved Reserved

DISC

NUM [2:0]

AWDCH[4:0]

Re se rv ed

0 0 0 0 0

EXTSEL [3:0]

Re se rv ed

JEXTSEL

[3:0]

0 0 0

Reserved

0 0 0 0 0 0 0 0 0

Reserved

0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

Sample time bits SMPx_x

0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Sample time bits SMPx_x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

JOFFSET1[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

JOFFSET2[11:0]

Reserved

0 0 0 0 0 0 0 0 0 0 0 0

JOFFSET3[11:0]

Reserved

0 0 0 0 0 0 0 0 0 0 0 0

JOFFSET4[11:0]

0 0 0 0 0 0 0 0 0 0 0 0

HT[11:0]

Reserved

1 1 1 1 1 1 1 1 1 1 1 1

LT[11:0]

Reserved

L[3:0]

0 0 0 0 0 0 0 0 0 0 0 0

Regular channel sequence SQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Regular channel sequence SQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Regular channel sequence SQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

JL[1:0] Injected channel sequence JSQx_x bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Regular DATA[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0368 Rev 5

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242

Analog-to-digital converter (ADC)

Table 48. ADC register map and reset values (common ADC registers)

Offset Register

0x04

ADC_CCR

Reset value

Reserved Reserved Reserved

0 0 0 0

Figure 41 give some examples of the counter behavior when the prescaler

for the register boundary addresses.

RM0368

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RM0368 Rev 5

RM0368

12 Advanced-control timer (TIM1)

Advanced-control timer (TIM1)

TIM8 is not available in STM32F401xB/C and STM32F401xD/E.

The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a programmable prescaler.

It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

The advanced-control (TIM1) and general-purpose (TIMx) timers are completely independent, and do not share any resources. They can be synchronized together as described in

Section 12.3.20

RM0368 Rev 5

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Advanced-control timer (TIM1) RM0368

12.2 TIM1 main features

TIM1 timer features include:

• 16-bit up, down, up/down auto-reload counter.

• 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536.

• Up to 4 independent channels for:

– Input Capture

– Output Compare

– PWM generation (Edge and Center-aligned Mode)

– One-pulse mode output

• Complementary outputs with programmable dead-time

• Synchronization circuit to control the timer with external signals and to interconnect several timers together.

• Repetition counter to update the timer registers only after a given number of cycles of the counter.

• Break input to put the timer’s output signals in reset state or in a known state.

• Interrupt/DMA generation on the following events:

– Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)

– Trigger event (counter start, stop, initialization or count by internal/external trigger)

– Input capture

– Output compare

– Break input

• Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes

• Trigger input for external clock or cycle-by-cycle current management

244/847

RM0368 Rev 5

RM0368

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Figure 39. Advanced-control timer block diagram

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12.3 TIM1 functional description

RM0368

The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)

• Prescaler register (TIMx_PSC)

• Auto-reload register (TIMx_ARR)

• Repetition counter register (TIMx_RCR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the

TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 40

and

ratio is changed on the fly:

246/847

RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Figure 40. Counter timing diagram with prescaler division change from 1 to 2

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315

Advanced-control timer (TIM1) RM0368

248/847

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register

(TIMx_RCR). Else the update event is generated at each counter overflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0.

However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in

TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The repetition counter is reloaded with the content of TIMx_RCR register,

• The auto-reload shadow register is updated with the preload value (TIMx_ARR),

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 42. Counter timing diagram, internal clock divided by 1

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RM0368 Advanced-control timer (TIM1)

Figure 43. Counter timing diagram, internal clock divided by 2

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Figure 44. Counter timing diagram, internal clock divided by 4

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Figure 45. Counter timing diagram, internal clock divided by N

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Figure 46. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

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Figure 47. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.

If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one

(TIMx_RCR+1). Else the update event is generated at each counter underflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0.

However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The repetition counter is reloaded with the content of TIMx_RCR register

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)

• The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

RM0368 Rev 5

251/847

315

Advanced-control timer (TIM1)

Figure 48. Counter timing diagram, internal clock divided by 1

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Figure 49. Counter timing diagram, internal clock divided by 2

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RM0368 Advanced-control timer (TIM1)

Figure 50. Counter timing diagram, internal clock divided by 4

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Figure 52. Counter timing diagram, update event when repetition counter is not used

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Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to

'00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,

CMS = "11").

In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from

0, as well as the counter of the prescaler.

The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0.

However, the counter continues counting up and down, based on the current auto-reload value.

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The repetition counter is reloaded with the content of TIMx_RCR register

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)

• The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock frequencies.

Figure 53. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

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Figure 54. Counter timing diagram, internal clock divided by 2

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RM0368 Rev 5

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Figure 55. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

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Figure 56. Counter timing diagram, internal clock divided by N

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Figure 57. Counter timing diagram, update event with ARPE=1 (counter underflow)

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Figure 58. Counter timing diagram, Update event with ARPE=1 (counter overflow)

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Section 12.3.1: Time-base unit

describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.

This means that data are transferred from the preload registers to the shadow registers

(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N+1 counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register.

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Advanced-control timer (TIM1) RM0368

The repetition counter is decremented:

• At each counter overflow in upcounting mode,

• At each counter underflow in downcounting mode,

• At each counter overflow and at each counter underflow in center-aligned mode.

Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is

2xT ck

, due to the symmetry of the pattern.

The repetition counter is an auto-reload type; the repetition rate is maintained as defined by

the TIMx_RCR register value (refer to Figure 59

). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.

In center-aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was started. If the RCR was written before starting the counter, the UEV occurs on the overflow. If the RCR was written after starting the counter, the UEV occurs on the underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or underflow event depending on when RCR was written.

Figure 59. Update rate examples depending on mode and TIMx_RCR register settings

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

The counter clock can be provided by the following clock sources:

• Internal clock (CK_INT)

• External clock mode1: external input pin

• External clock mode2: external trigger input ETR

• Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, the user can configure Timer 1 to act as a prescaler for Timer 2. Refer to

Using one timer as prescaler for another timer for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 60

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Figure 60. Control circuit in normal mode, internal clock divided by 1

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This mode is selected when SMS=111 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on a selected input.

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Advanced-control timer (TIM1) RM0368

Figure 61. TI2 external clock connection example

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For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.

2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).

3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register.

4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.

6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The capture prescaler is not used for triggering, so the user does not need to configure it.

When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Figure 62. Control circuit in external clock mode 1

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This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input ETR.

Figure 63

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Figure 63. External trigger input block

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RM0368 Rev 5

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For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register

4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.

Figure 64. Control circuit in external clock mode 2

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Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).

Figure 65

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The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Figure 65. Capture/compare channel (example: channel 1 input stage)

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The output stage generates an intermediate waveform that is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

Figure 66. Capture/compare channel 1 main circuit

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The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Note:

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the

TIMx_CCRx register. CCxOF is cleared when written to ‘0’.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

• Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only.

• Program the needed input filter duration with respect to the signal connected to the timer (by programming ICxF bits in the TIMx_CCMRx register if the input is a TIx input).

Let’s imagine that, when toggling, the input signal is not stable during at must five internal clock cycles. We must program a filter duration longer than these five clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at f

DTS the TIMx_CCMR1 register.

frequency). Then write IC1F bits to 0011 in

• Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case).

• Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the

TIMx_CCMR1 register).

• Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

• If needed, enable the related interrupt request by setting the CC1IE bit in the

TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the

TIMx_DIER register.

When an input capture occurs:

• The TIMx_CCR1 register gets the value of the counter on the active transition.

• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

• An interrupt is generated depending on the CC1IE bit.

• A DMA request is generated depending on the CC1DE bit.

In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.

IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

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Advanced-control timer (TIM1) RM0368

12.3.7 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:

• Two ICx signals are mapped on the same TIx input.

• These 2 ICx signals are active on edges with opposite polarity.

• One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, user can measure the period (in TIMx_CCR1 register) and the duty cycle (in

TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):

• Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).

• Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge).

• Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).

• Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to ‘1’ (active on falling edge).

• Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register

(TI1FP1 selected).

• Configure the slave mode controller in reset mode: write the SMS bits to 100 in the

TIMx_SMCR register.

• Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

Figure 69. PWM input mode timing

12.3.8 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (OCXREF/OCx) to its active level, the user just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1) forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

For example: CCxP=0 (OCx active high) => OCx is forced to high level.

The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below.

This function is used to control an output waveform or indicating when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

• Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.

• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the

TIMx_DIER register).

• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the

TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the

OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on OCxREF and OCx output.

The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode).

Procedure:

Select the counter clock (internal, external, prescaler).

2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3. Set the CCxIE bit if an interrupt request is to be generated.

4. Select the output mode. For example:

– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx

– Write OCxPE = 0 to disable preload register

– Write CCxP = 0 to select active high polarity

– Write CCxE = 1 to enable the output

5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in

Figure 70

RM0368 Rev 5

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Advanced-control timer (TIM1)

Figure 70. Output compare mode, toggle on OC1.

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Pulse Width Modulation mode allows generating a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. The corresponding preload register must be enabled by setting the

OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, the user must initialize all the registers by setting the UG bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).

Refer to the TIMx_CCER register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter).

The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

• Upcounting configuration

Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to

Upcounting mode

In the following example, we consider PWM mode 1. The reference PWM signal

OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the

RM0368 Rev 5

RM0368 Advanced-control timer (TIM1) compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.

Figure 71

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TIMx_ARR=8.

Figure 71. Edge-aligned PWM waveforms (ARR=8)

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• Downcounting configuration

Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to

Downcounting mode

In PWM mode 1, the reference signal OCxRef is low as long as

TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from

‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).

The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the

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TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to

Center-aligned mode (up/down counting)

Figure 72

shows some center-aligned PWM waveforms in an example where:

• TIMx_ARR=8,

• PWM mode is the PWM mode 1,

• The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.

Figure 72. Center-aligned PWM waveforms (ARR=8)

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Hints on using center-aligned mode:

• When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit

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• Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:

– The direction is not updated if the user writes a value in the counter greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it will continue to count up.

– The direction is updated if the user writes 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated.

• The safest way to use center-aligned mode is to generate an update by software

(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

12.3.11 Complementary outputs and dead-time insertion

The advanced-control timers (TIM1) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs.

This time is generally known as dead-time and it has to be adjust it depending on the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...)

User can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the

TIMx_CCER register.

The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,

OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 51

for more details. In particular, the dead-time is activated when switching to the IDLE state

(MOE falling down to 0).

Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the dead-time generation for all channels. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:

• The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge.

• The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.

If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.

The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,

CCxE=1 and CCxNE=1 in these examples)

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Figure 73. Complementary output with dead-time insertion.

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Figure 74. Dead-time waveforms with delay greater than the negative pulse.

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Figure 75. Dead-time waveforms with delay greater than the positive pulse.

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The dead-time delay is the same for each of the channels and is programmable with the

DTG bits in the TIMx_BDTR register. Refer to Section 12.4.18: TIM1 break and dead-time register (TIMx_BDTR) for delay calculation.

Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.

This allows the user to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other possibilities are to

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Note: have both outputs at inactive level or both outputs active and complementary with dead-time.

When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when

OCxREF is low.

12.3.12 Using the break function

When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,

OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time. Refer to

Table 51 for more details.

The break source can be either the break input pin or a clock failure event, generated by the

Clock Security System (CSS), from the Reset Clock Controller. For further information on the Clock Security System, refer to

Section 6.2.7: Clock security system (CSS) .

When exiting from reset, the break circuit is disabled and the MOE bit is low. User can enable the break function by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1

APB clock period to correctly read back the bit after the write operation.

Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit

(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if MOE is written to 1 whereas it was low, a delay

(dummy instruction) must be inserted before reading it correctly. This is because the user writes an asynchronous signal, but reads a synchronous signal.

When a break occurs (selected level on the break input):

• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.

• Each output channel is driven with the level programmed in the OISx bit in the

TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable output else the enable output remains high.

• When complementary outputs are used:

– The outputs are first put in reset state inactive state (depending on the polarity).

This is done asynchronously so that it works even if no clock is provided to the timer.

– If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their

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Note:

RM0368 active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).

– If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.

• The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set.

• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance.

Else, MOE remains low until it is written to ‘1’ again. In this case, it can be used for security and the break input can be connected to an alarm from power drivers, thermal sensors or any security components.

The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.

The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register.

There are two solutions to generate a break:

• By using the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR register

• By software through the BG bit of the TIMx_EGR register.

In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows freezing the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The user can choose from three levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to

Section 12.4.18: TIM1 break and dead-time register (TIMx_BDTR)

. The LOCK bits can be written only once after an MCU reset.

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Figure 76

shows an example of behavior of the outputs in response to a break.

Figure 76. Output behavior in response to a break.

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The OCxREF signal for a given channel can be driven Low by applying a High level to the

ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The

OCxREF signal remains Low until the next update event, UEV, occurs.

This function can only be used in output compare and PWM modes, and does not work in forced mode.

For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, the ETR must be configured as follow:

The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’.

2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to

‘0’.

3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs.

Figure 77

shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in

PWM mode.

Figure 77. Clearing TIMx OCxREF

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When complementary outputs are used on a channel, preload bits are available on the

OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the

COM commutation event. The user can thus program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on

TRGI rising edge).

A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request

(if the COMDE bit is set in the TIMx_DIER register).

Figure 78

describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations.

Figure 78. 6-step generation, COM example (OSSR=1)

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One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.

Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. Select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

• In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)

• In downcounting: CNT > CCRx

Figure 79. Example of one pulse mode.

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For example the user may want to generate a positive pulse on OC1 with a length of t

PULSE and after a delay of t

DELAY

as soon as a positive edge is detected on the TI2 input pin.

Let’s use TI2FP2 as trigger 1:

• Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.

• TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register.

• Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register.

• TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register

(trigger mode).

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The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

• The t

DELAY is defined by the value written in the TIMx_CCR1 register.

• The t

PULSE

is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).

• Let us say the user wants to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this, enable PWM mode 2 by writing OC1M=111 in the

TIMx_CCMR1 register. The user can optionally enable the preload registers by writing

OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case the compare value must be written in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.

The user only wants one pulse (Single mode), so '1’ must be written in the OPM bit in the

TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected.

Particular case: OCx fast enable:

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay t

DELAY

min we can get.

If the user wants to output a waveform with the minimum delay, the OCxFE bit in the

TIMx_CCMRx register must be set. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and

SMS=’011’ if it is counting on both TI1 and TI2 edges.

Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, the user can program the input filter as well. CC1NP and CC2NP must be kept low.

The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to

Table 49 . The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2

after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,

TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in

TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.

Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the

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TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So user must configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and

External clock mode 2 are not compatible and must not be selected together.

In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor.

Table 49 summarizes the possible combinations, assuming TI1 and TI2 do not switch at the

same time.

Active edge

Counting on

TI1 only

Counting on

TI2 only

Counting on

TI1 and TI2

Table 49. Counting direction versus encoder signals

TI1FP1 signal

Level on opposite signal

(TI1FP1 for TI2, TI2FP2 for TI1)

Rising Falling

TI2FP2 signal

Rising Falling

High

Low

High

Low

High

Low

Down Up

Up Down

No Count No Count

Down Up

Up Down

No Count No Count

Up Down

Down

An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.

Figure 80

gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:

• CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).

• CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).

• CC1P=’0’, CC1NP=’0’, and IC1F = ‘0000’ (TIMx_CCER register, TI1FP1 non-inverted,

TI1FP1=TI1).

• CC2P=’0’, CC2NP=’0’, and IC2F = ‘0000’ (TIMx_CCER register, TI1FP2 non-inverted,

TI1FP2= TI2).

• SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges).

• CEN=’1’ (TIMx_CR1 register, Counter enabled).

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Figure 80. Example of counter operation in encoder interface mode.

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Figure 81

gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’).

Figure 81. Example of encoder interface mode with TI1FP1 polarity inverted.

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The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.The user can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. This can be done by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a

DMA request generated by a real-time clock.

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12.3.17 Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and

TIMx_CH3.

The XOR output can be used with all the timer input functions such as trigger or input capture. An example of this feature used to interface Hall sensors is given in

Section 12.3.18

12.3.18 Interfacing with Hall sensors

This is done using the advanced-control timers (TIM1) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as “interfacing timer” in

Figure 82 . The “interfacing timer” captures the 3 timer input pins (TIMx_CH1, TIMx_CH2,

and TIMx_CH3) connected through a XOR to the TI1 input channel (selected by setting the

TI1S bit in the TIMx_CR2 register).

The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs.

On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC (see

Figure 65

). The captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives information about motor speed.

The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advancedcontrol timer (TIM1) through the TRGO output.

Example: the user wants to change the PWM configuration of the advanced-control timer

TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers.

• Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the

TIMx_CR2 register to ‘1’,

• Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors,

• Program channel 1 in capture mode (TRC selected): write the CC1S bits in the

TIMx_CCMR1 register to ‘11’. The user can also program the digital filter if needed,

• Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,

• Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’,

In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF).

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Figure 82

describes this example.

Figure 82. Example of Hall sensor interface

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12.3.19 TIMx and external trigger synchronization

The TIMx timer can be synchronized with an external trigger in several modes: Reset mode,

Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on TI1 input:

• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so there’s no need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write

CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edges only).

• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

• Start the counter by writing CEN=1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.

Figure 83. Control circuit in reset mode

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. The

CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.

Write CC1P=1 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only).

• Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

• Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level).

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.

Figure 84. Control circuit in gated mode

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Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on TI2 input:

• Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so there’s no need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity

(and detect low level only).

• Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI2 as the input source by writing TS=110 in TIMx_SMCR register.

When a rising edge occurs on TI2, the counter starts counting on the internal clock and the

TIF flag is set.

The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.

Figure 85. Control circuit in trigger mode

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Slave mode: external clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of

TIMx_SMCR register.

In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:

Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:

– ETF = 0000: no filter

– ETPS = 00: prescaler disabled

– ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.

2. Configure the channel 1 as follows, to detect rising edges on TI:

– IC1F=0000: no filter.

– The capture prescaler is not used for triggering and does not need to be configured.

– CC1S=01 in TIMx_CCMR1 register to select only the input capture source

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– CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and detect rising edge only).

3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on

ETR rising edges.

The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.

Figure 86. Control circuit in external clock mode 2 + trigger mode

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Note:

The TIM timers are linked together internally for timer synchronization or chaining. Refer to

Section 13.3.15: Timer synchronization for details.

The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

When the microcontroller enters debug mode (Cortex ® -M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to

Section 23.16.2: Debug support for timers, watchdog and I2C .

For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1 in

DBGMCU_APBx_FZ register), the outputs are disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state (OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force them to Hi-Z.

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Refer to Section 2.2

for a list of abbreviations used in register descriptions.

The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).

12.4.1 TIM1 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

15 14 13 12

Reserved

11 10 9 8

CKD[1:0] rw rw

ARPE rw

6 5

CMS[1:0] rw rw

DIR rw

OPM rw

URS rw

UDIS rw

CEN rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD[1:0] : Clock division

This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t

DTS

)used by the dead-time generators and the digital filters

(ETR, TIx),

00: t

DTS

CK_INT

01: t

DTS

=2*t

CK_INT

10: t

DTS

=4*t

CK_INT

11: Reserved, do not program this value

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:5 CMS[1:0] : Center-aligned mode selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit

(DIR).

01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.

10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.

11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.

Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)

Bit 4 DIR : Direction

0: Counter used as upcounter

1: Counter used as downcounter

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

Bit 3 OPM : One pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generate an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

12.4.2 TIM1 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

Res.

14 13 12 11 10 9 8

OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 rw rw rw rw rw rw rw

TI1S rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 OIS4 : Output Idle state 4 (OC4 output) refer to OIS1 bit

Bit 13 OIS3N : Output Idle state 3 (OC3N output) refer to OIS1N bit

Bit 12 OIS3 : Output Idle state 3 (OC3 output) refer to OIS1 bit

Bit 11 OIS2N : Output Idle state 2 (OC2N output) refer to OIS1N bit

Bit 10 OIS2 : Output Idle state 2 (OC2 output) refer to OIS1 bit

6 rw

MMS[2:0] rw

4 rw

3 2

CCDS CCUS rw rw

Res.

CCPC rw

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Bit 9 OIS1N : Output Idle state 1 (OC1N output)

0: OC1N=0 after a dead-time when MOE=0

1: OC1N=1 after a dead-time when MOE=0

Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

Bit 8 OIS1 : Output Idle state 1 (OC1 output)

0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0

1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

Bit 7 TI1S : TI1 selection

0: The TIMx_CH1 pin is connected to TI1 input

1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Bits 6:4 MMS[2:0] : Master mode selection

These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.

(TRGO).

100: Compare - OC1REF signal is used as trigger output (TRGO)

101: Compare - OC2REF signal is used as trigger output (TRGO)

110: Compare - OC3REF signal is used as trigger output (TRGO)

111: Compare - OC4REF signal is used as trigger output (TRGO)

Note: The clock of the slave timer and ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bit 3 CCDS : Capture/compare DMA selection

0: CCx DMA request sent when CCx event occurs

1: CCx DMA requests sent when update event occurs

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Bit 2 CCUS : Capture/compare control update selection

0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only

1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

Note: This bit acts only on channels that have a complementary output.

Bit 1 Reserved, must be kept at reset value.

Bit 0 CCPC : Capture/compare preloaded control

0: CCxE, CCxNE and OCxM bits are not preloaded

1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on

TRGI, depending on the CCUS bit).

Note: This bit acts only on channels that have a complementary output.

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12.4.3 TIM1 slave mode control register (TIMx_SMCR)

Address offset: 0x08

Reset value: 0x0000

RM0368

ETP rw

ECE rw

13 12

ETPS[1:0] rw rw

11 rw

ETF[3:0]

9 rw rw

8 rw

MSM rw

6 rw

TS[2:0] rw

4 rw

Res.

2 rw

SMS[2:0] rw

0 rw

Bit 15 ETP : External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations

0: ETR is non-inverted, active at high level or rising edge.

1: ETR is inverted, active at low level or falling edge.

Bit 14 ECE : External clock enable

This bit enables External clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with

TRGI connected to ETRF (SMS=111 and TS=111).

2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111).

3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.

Bits 13:12 ETPS[1:0] : External trigger prescaler

External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.

00: Prescaler OFF

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

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Bits 11:8 ETF[3:0] : External trigger filter

This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

CK_INT

, N=2

, N=4

, N=8

/2, N=6 0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/2, N=8

/4, N=6

/4, N=8

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8 1100: f

SAMPLING

1101: f

SAMPLING

1110: f

SAMPLING

DTS

1111: f

SAMPLING

DTS

/32, N=5

/32, N=6

/32, N=8

Bit 7 MSM: Master/slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

Bits 6:4 TS[2:0]: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

000: Internal Trigger 0 (ITR0)

001: Internal Trigger 1 (ITR1)

010: Internal Trigger 2 (ITR2)

011: Internal Trigger 3 (ITR3)

100: TI1 Edge Detector (TI1F_ED)

101: Filtered Timer Input 1 (TI1FP1)

110: Filtered Timer Input 2 (TI2FP2)

111: External Trigger input (ETRF)

See

Table 50 for more details on ITRx meaning for each Timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

Bit 3 Reserved, must be kept at reset value.

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Bits 2:0 SMS: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.

000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.

001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.

010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.

011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

Note: The gated mode must not be used if TI1F_ED is selected as the trigger input

(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.

The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Slave TIM

TIM1

Table 50. TIMx Internal trigger connection

ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010)

TIM5_TRGO TIM2_TRGO TIM3_TRGO

ITR3 (TS = 011)

TIM4_TRGO

12.4.4 TIM1 DMA/interrupt enable register (TIMx_DIER)

Res.

Address offset: 0x0C

Reset value: 0x0000

14 13 12 11 10 9 8

TDE COMDE CC4DE CC3DE CC2DE CC1DE UDE rw rw rw rw rw rw rw

BIE rw

TIE rw

5 4 3 2 1

COMIE CC4IE CC3IE CC2IE CC1IE rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE : Trigger DMA request enable

0: Trigger DMA request disabled

1: Trigger DMA request enabled

Bit 13 COMDE : COM DMA request enable

0: COM DMA request disabled

1: COM DMA request enabled

UIE rw

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Bit 12 CC4DE : Capture/Compare 4 DMA request enable

0: CC4 DMA request disabled

1: CC4 DMA request enabled

Bit 11 CC3DE : Capture/Compare 3 DMA request enable

0: CC3 DMA request disabled

1: CC3 DMA request enabled

Bit 10 CC2DE : Capture/Compare 2 DMA request enable

0: CC2 DMA request disabled

1: CC2 DMA request enabled

Bit 9 CC1DE : Capture/Compare 1 DMA request enable

0: CC1 DMA request disabled

1: CC1 DMA request enabled

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled

1: Update DMA request enabled

Bit 7 BIE : Break interrupt enable

0: Break interrupt disabled

1: Break interrupt enabled

Bit 6 TIE : Trigger interrupt enable

0: Trigger interrupt disabled

1: Trigger interrupt enabled

Bit 5 COMIE : COM interrupt enable

0: COM interrupt disabled

1: COM interrupt enabled

Bit 4 CC4IE : Capture/Compare 4 interrupt enable

0: CC4 interrupt disabled

1: CC4 interrupt enabled

Bit 3 CC3IE : Capture/Compare 3 interrupt enable

0: CC3 interrupt disabled

1: CC3 interrupt enabled

Bit 2 CC2IE : Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled

1: CC2 interrupt enabled

Bit 1 CC1IE : Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled

1: Update interrupt enabled

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15 14

Reserved

Address offset: 0x10

Reset value: 0x0000

13 12 11 10 9 8

CC4OF CC3OF CC2OF CC1OF Res.

rc_w0 rc_w0 rc_w0 rc_w0 Res.

BIF

TIF

5 4

COMIF CC4IF

CC3IF

CC2IF

CC1IF

UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CC4OF : Capture/Compare 4 overcapture flag refer to CC1OF description

Bit 11 CC3OF : Capture/Compare 3 overcapture flag refer to CC1OF description

Bit 10 CC2OF : Capture/Compare 2 overcapture flag refer to CC1OF description

Bit 9 CC1OF : Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bit 8 Reserved, must be kept at reset value.

Bit 7 BIF : Break interrupt flag

This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.

0: No break event occurred.

1: An active level has been detected on the break input.

Bit 6 TIF : Trigger interrupt flag

This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected.It is cleared by software.

0: No trigger event occurred.

1: Trigger interrupt pending.

Bit 5 COMIF : COM interrupt flag

This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,

CCxNE, OCxM - have been updated). It is cleared by software.

0: No COM event occurred.

1: COM interrupt pending.

Bit 4 CC4IF : Capture/Compare 4 interrupt flag refer to CC1IF description

Bit 3 CC3IF : Capture/Compare 3 interrupt flag refer to CC1IF description

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Bit 2 CC2IF : Capture/Compare 2 interrupt flag refer to CC1IF description

Bit 1 CC1IF : Capture/Compare 1 interrupt flag

If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software.

0: No match.

1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.

When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode)

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the

TIMx_CCR1 register.

0: No input capture occurred

1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity)

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value (update if repetition counter

= 0) and if the UDIS=0 in the TIMx_CR1 register.

– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and

UDIS=0 in the TIMx_CR1 register.

– When CNT is reinitialized by a trigger event (refer to

Section 12.4.3: TIM1 slave mode control register (TIMx_SMCR) ), if URS=0 and UDIS=0 in the TIMx_CR1 register.

15 14

Address offset: 0x14

Reset value: 0x0000

13 12 11 10

Reserved

9 8 7

BG w

TG w

5 4 3 2 1

COMG CC4G CC3G CC2G CC1G w w w w w

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 BG : Break generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or

DMA transfer can occur if enabled.

Bit 6 TG : Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

UG w

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Bit 5 COMG : Capture/Compare control update generation

This bit can be set by software, it is automatically cleared by hardware

0: No action

1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits

Note: This bit acts only on channels having a complementary output.

Bit 4 CC4G : Capture/Compare 4 generation refer to CC1G description

Bit 3 CC3G : Capture/Compare 3 generation refer to CC1G description

Bit 2 CC2G : Capture/Compare 2 generation refer to CC1G description

Bit 1 CC1G : Capture/Compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.

If channel CC1 is configured as input:

The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the

CC1IF flag was already high.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

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OC2

CE rw

Address offset: 0x18

Reset value: 0x0000

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit,

OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So the user must take care that the same bit can have a different meaning for the input stage and for the output stage.

14 13

OC2M[2:0]

IC2F[3:0] rw rw rw

OC2

IC2PSC[1:0] rw rw

Output compare mode:

CC2S[1:0] rw

8 rw

OC1

CE rw

6 5

OC1M[2:0]

IC1F[3:0] rw rw

4 rw

OC1

IC1PSC[1:0] rw rw

CC1S[1:0] rw

0 rw

Bit 15 OC2CE: Output Compare 2 clear enable

Bits 14:12 OC2M[2:0] : Output Compare 2 mode

Bit 11 OC2PE : Output Compare 2 preload enable

Bit 10 OC2FE : Output Compare 2 fast enable

Bits 9:8 CC2S[1:0] : Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

Bit 7 OC1CE: Output Compare 1 clear enable

OC1CE: Output Compare 1 Clear Enable

0: OC1Ref is not affected by the ETRF Input

1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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Advanced-control timer (TIM1) RM0368

Bits 6:4 OC1M : Output Compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and

OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.

000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter

TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

100: Force inactive level - OC1REF is forced low.

101: Force active level - OC1REF is forced high.

110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as

TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).

111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.

Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed

(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).

2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.

3: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated.

Bit 3 OC1PE : Output Compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed

(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).

2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Bit 2 OC1FE : Output Compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is

ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is

5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

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RM0368 Advanced-control timer (TIM1)

Bits 1:0 CC1S : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

Input capture mode

Bits 15:12 IC2F : Input capture 2 filter

Bits 11:10 IC2PSC[1:0] : Input capture 2 prescaler

Bits 9:8 CC2S : Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).

Bits 7:4 IC1F[3:0] : Input capture 1 filter

This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

CK_INT

, N=2

, N=4

, N=8

/2, N=6 0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/2, N=8

/4, N=6

/4, N=8

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8 1100: f

SAMPLING

1101: f

SAMPLING

1110: f

SAMPLING

DTS

1111: f

SAMPLING

DTS

/32, N=5

/32, N=6

/32, N=8

Bits 3:2 IC1PSC : Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).

The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).

00: no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

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Bits 1:0 CC1S : Capture/Compare 1 Selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).

OC4

CE rw

Address offset: 0x1C

Reset value: 0x0000

Refer to the above CCMR1 register description.

OC4M[2:0]

IC4F[3:0] rw rw

12 rw

OC4

IC4PSC[1:0] rw rw

9 8

CC4S[1:0] rw rw

OC3

CE.

6 5

OC3M[2:0]

IC3F[3:0] rw rw

4 rw

Output compare mode

OC3

IC3PSC[1:0] rw rw

CC3S[1:0] rw

0 rw

Bit 15 OC4CE: Output compare 4 clear enable

Bits 14:12 OC4M : Output compare 4 mode

Bit 11 OC4PE : Output compare 4 preload enable

Bit 10 OC4FE : Output compare 4 fast enable

Bits 9:8 CC4S : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).

Bit 7 OC3CE: Output compare 3 clear enable

Bits 6:4 OC3M : Output compare 3 mode

Bit 3 OC3PE : Output compare 3 preload enable

Bit 2 OC3FE : Output compare 3 fast enable

Bits 1:0 CC3S : Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

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RM0368 Advanced-control timer (TIM1)

Input capture mode

Bits 15:12 IC4F : Input capture 4 filter

Bits 11:10 IC4PSC : Input capture 4 prescaler

Bits 9:8 CC4S : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).

Bits 7:4 IC3F : Input capture 3 filter

Bits 3:2 IC3PSC : Input capture 3 prescaler

Bits 1:0 CC3S : Capture/compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

15 14

Reserved

Address offset: 0x20

Reset value: 0x0000

13 12 11 10 9 8 7 6 5 4 3 2 1 0

CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 CC4P : Capture/Compare 4 output polarity refer to CC1P description

Bit 12 CC4E : Capture/Compare 4 output enable refer to CC1E description

Bit 11 CC3NP : Capture/Compare 3 complementary output polarity refer to CC1NP description

Bit 10 CC3NE : Capture/Compare 3 complementary output enable refer to CC1NE description

Bit 9 CC3P : Capture/Compare 3 output polarity refer to CC1P description

Bit 8 CC3E : Capture/Compare 3 output enable refer to CC1E description

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Bit 7 CC2NP : Capture/Compare 2 complementary output polarity refer to CC1NP description

Bit 6 CC2NE : Capture/Compare 2 complementary output enable refer to CC1NE description

Bit 5 CC2P : Capture/Compare 2 output polarity refer to CC1P description

Bit 4 CC2E : Capture/Compare 2 output enable refer to CC1E description

Bit 3 CC1NP : Capture/Compare 1 complementary output polarity

CC1 channel configured as output:

0: OC1N active high.

1: OC1N active low.

CC1 channel configured as input:

This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description.

Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).

Bit 2 CC1NE : Capture/Compare 1 complementary output enable

0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,

OSSR, OIS1, OIS1N and CC1E bits.

Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated.

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Bit 1 CC1P : Capture/Compare 1 output polarity

CC1 channel configured as output:

0: OC1 active high

1: OC1 active low

CC1 channel configured as input:

CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.

00: non-inverted/rising edge

The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode).

01: inverted/falling edge

The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode).

10: reserved, do not use this configuration.

11: non-inverted/both edges

The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode.

Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.

Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 0 CC1E : Capture/Compare 1 output enable

CC1 channel configured as output:

0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.

1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,

OSSR, OIS1, OIS1N and CC1NE bits.

CC1 channel configured as input:

This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled.

1: Capture enabled.

Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated.

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Advanced-control timer (TIM1) RM0368

Table 51. Output control bits for complementary OCx and OCxN channels with break feature

Control bits Output states

(1)

MOE bit

OSSI bit

OSSR bit

CCxE bit

CCxNE bit

OCx output state OCxN output state

1 X

Output Disabled (not driven by the timer), OCx=0, OCx_EN=0

Output Disabled (not driven by the timer), OCxN=0, OCxN_EN=0

Output Disabled (not driven by the timer), OCx=0, OCx_EN=0

OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1

OCxREF + Polarity

OCx=OCxREF xor CCxP,

OCx_EN=1

OCREF + Polarity + dead-time

OCx_EN=1

Output Disabled (not driven by the timer)

OCxN=0, OCxN_EN=0

Complementary to OCREF (not

OCREF) + Polarity + dead-time

OCxN_EN=1

Output Disabled (not driven by the timer)

OCx=CCxP, OCx_EN=0

Output Disabled (not driven by the timer)

OCxN=CCxNP, OCxN_EN=0

Off-State (output enabled with inactive state)

OCx=CCxP, OCx_EN=1

OCxREF + Polarity

OCx=OCxREF xor CCxP,

OCx_EN=1

OCREF + Polarity + dead-time

OCx_EN=1

OCxREF + Polarity

OCxN=OCxREF xor CCxNP,

OCxN_EN=1

Off-State (output enabled with inactive state)

OCxN=CCxNP, OCxN_EN=1

Complementary to OCREF (not

OCREF) + Polarity + dead-time

OCxN_EN=1

0 X

Output disabled (not driven by the timer anymore). The output state is defined by the GPIO controller and can be High, Low or Hi-Z.

Off-State (output enabled with inactive state)

Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,

OCxN_EN=1

Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state

1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers.

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

15 rw

Address offset: 0x24

Reset value: 0x0000

13 12 11 10 9 rw rw rw rw rw rw

Bits 15:0 CNT[15:0] : Counter value

8 7

CNT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

15 rw

Address offset: 0x28

Reset value: 0x0000

13 12 11 10 rw

9 8 7

PSC[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

15 rw

Address offset: 0x2C

Reset value: 0xFFFF

13 12 11 10 rw

9 8 7

ARR[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to Section 12.3.1: Time-base unit for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

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Advanced-control timer (TIM1) RM0368

12.4.13 TIM1 repetition counter register (TIMx_RCR)

15 14

Address offset: 0x30

Reset value: 0x0000

13 12 11 10 9 8 7 6 5

Reserved rw rw rw

REP[7:0]

3 rw rw

2 rw

1 rw

0 rw

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 REP[7:0] : Repetition counter value

These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.

Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event.

It means in PWM mode (REP+1) corresponds to:

– the number of PWM periods in edge-aligned mode

– the number of half PWM period in center-aligned mode.

15 rw/ro

Address offset: 0x34

Reset value: 0x0000

13 12 11 10 9 8 7

CCR1[15:0] rw/ro rw/ro

6 5 4 3 2 1 0 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

Bits 15:0 CCR1[15:0] : Capture/Compare 1 value

If channel CC1 is configured as output :

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register

(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input :

CCR1 is the counter value transferred by the last input capture 1 event (IC1). The

TIMx_CCR1 register is read-only and cannot be programmed.

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RM0368 Advanced-control timer (TIM1)

15 rw/ro

Address offset: 0x38

Reset value: 0x0000

13 12 11 10 9 8 7

CCR2[15:0] rw/ro rw/ro

6 5 4 3 2 1 0 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

Bits 15:0 CCR2[15:0] : Capture/Compare 2 value

If channel CC2 is configured as output :

CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register

(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC2 output.

If channel CC2 is configured as input :

CCR2 is the counter value transferred by the last input capture 2 event (IC2). The

TIMx_CCR2 register is read-only and cannot be programmed.

15 rw/ro

Address offset: 0x3C

Reset value: 0x0000

13 12 11 10 9 8 7

CCR3[15:0] rw/ro rw/ro

6 5 4 3 2 1 0 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

Bits 15:0 CCR3[15:0] : Capture/Compare value

If channel CC3 is configured as output :

CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register

(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC3 output.

If channel CC3 is configured as input :

CCR3 is the counter value transferred by the last input capture 3 event (IC3). The

TIMx_CCR3 register is read-only and cannot be programmed.

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15 rw/ro

Address offset: 0x40

Reset value: 0x0000

13 12 11 10 9 8 7

CCR4[15:0] rw/ro rw/ro

6 5 4 3 2 1 0 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

Bits 15:0 CCR4[15:0] : Capture/Compare value

If channel CC4 is configured as output :

CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register

(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC4 output.

If channel CC4 is configured as input :

CCR4 is the counter value transferred by the last input capture 4 event (IC4). The

TIMx_CCR3 register is read-only and cannot be programmed.

12.4.18 TIM1 break and dead-time register (TIMx_BDTR)

MOE rw

Address offset: 0x44

AOE rw

Reset value: 0x0000

BKP rw

12 11 10

BKE OSSR OSSI rw rw rw

9 8

LOCK[1:0] rw rw

7 rw

6 rw

5 rw

4 3

DTG[7:0] rw rw

Note:

2 1 0 rw rw rw

As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Bit 15 MOE : Main output enable

This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.

0: OC and OCN outputs are disabled or forced to idle state.

1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in

TIMx_CCER register).

See OC/OCN enable description for more details ( Section 12.4.9: TIM1 capture/compare enable register (TIMx_CCER)

Bit 14 AOE : Automatic output enable

0: MOE can be set only by software

1: MOE can be set by software or automatically at the next update event (if the break input is not be active)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

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RM0368 Advanced-control timer (TIM1)

Bit 13 BKP : Break polarity

0: Break input BRK is active low

1: Break input BRK is active high

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 12 BKE : Break enable

0: Break inputs (BRK and CSS clock failure event) disabled

1; Break inputs (BRK and CSS clock failure event) enabled

Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in

TIMx_BDTR register).

Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Bit 11 OSSR : Off-state selection for Run mode

This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.

See OC/OCN enable description for more details ( Section 12.4.9: TIM1 capture/compare enable register (TIMx_CCER)

0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).

1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

Bit 10 OSSI : Off-state selection for Idle mode

This bit is used when MOE=0 on channels configured as outputs.

See OC/OCN enable description for more details ( Section 12.4.9: TIM1 capture/compare enable register (TIMx_CCER)

0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).

1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or

CCxNE=1. OC/OCN enable output signal=1)

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

Bits 9:8 LOCK[1:0] : Lock configuration

These bits offer a write protection against software errors.

00: LOCK OFF - No bit is write protected.

01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.

10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.

11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in

TIMx_CCMRx registers, as long as the related channel is configured in output through the

CCxS bits) can no longer be written.

Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

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Advanced-control timer (TIM1) RM0368

Bits 7:0 DTG[7:0] : Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.

DTG[7:5]=0xx => DT=DTG[7:0]x t dtg

with t dtg

DTS

DTG[7:5]=10x => DT=(64+DTG[5:0])xt dtg

with T dtg

DTG[7:5]=110 => DT=(32+DTG[4:0])xt

DTG[7:5]=111 => DT=(32+DTG[4:0])xt dtg

Example if T

DTS

0 to 15875 ns by 125 ns steps, dtg

with T

with T dtg dtg

=2xt

DTS

=8xt

DTS

=16xt

DTS

=125ns (8MHz), dead-time possible values are:

16 us to 31750 ns by 250 ns steps,

32 us to 63us by 1 us steps,

64 us to 126 us by 2 us steps

Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

Address offset: 0x48

Reserved

Reset value: 0x0000

13 12 11 rw rw

DBL[4:0] rw

9 rw

8 7 6

Reserved

5 4 3 rw

DBA[4:0] rw

1 rw

0 rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0] : DMA burst length

This 5-bit vector defines the number of DMA transfers (the timer detects a burst transfer when a read or a write access to the TIMx_DMAR register address is performed). the TIMx_DMAR address)

00000: 1 transfer

00001: 2 transfers

00010: 3 transfers

...

10001: 18 transfers

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DBA[4:0] : DMA base address

This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.

Example:

00000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR,

...

Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

12.4.20 TIM1 DMA address for full transfer (TIMx_DMAR)

31 30

Address offset: 0x4C

Reset value: 0x0000 0000

29 28 27 26 25 22 21 20 rw

15 rw rw

14 rw rw

13 rw rw

12 rw rw

11 rw rw

10 rw rw

9 rw

24 23

DMAB[31:16] rw

8 rw

DMAB[15:0] rw rw rw

6 rw rw

5 rw rw

4 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw

Bits 31:0 DMAB[31:0] : DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address

(TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the

DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

Note:

Example of how to use the DMA burst feature

In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.

This is done in the following steps:

Configure the corresponding DMA channel as follows:

– DMA channel peripheral address is the DMAR register address

– DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.

– Number of data to transfer = 3 (See note below).

– Circular mode disabled.

2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:

DBL = 3 transfers, DBA = 0xE.

3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).

5. Enable the DMA channel

This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to

CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

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Advanced-control timer (TIM1) RM0368

12.4.21 TIM1 register map

TIM1 registers are mapped as 16-bit addressable registers as described in the table below:

Table 52. TIM1 register map and reset values

Offset Register

0x00

0x04

0x08

TIMx_CR1

Reset value

TIMx_CR2

Reset value

TIMx_SMCR

Reset value

TIMx_DIER

0x0C

Reset value

TIMx_SR

0x10

Reset value

TIMx_EGR

0x14

0x18

0x1C

Reset value

TIMx_CCMR1

Output

Compare mode

Reset value

TIMx_CCMR1

Input Capture mode

Reset value

TIMx_CCMR2

Output

Compare mode

Reset value

TIMx_CCMR2

Input Capture mode

Reset value

TIMx_CCER

0x20

0x24

0x28

Reset value

TIMx_CNT

Reset value

TIMx_PSC

Reset value

Reserved

CKD

[1:0]

CMS

[1:0]

0 0 0 0 0 0 0 0 0 0

MMS[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

ETP

[1:0]

ETF[3:0] TS[2:0]

0 0 0 0 0 0 0 0 0 0 0 0

SMS[2:0]

0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

OC2M

[2:0]

CC2S

[1:0]

0 0 0 0 0 0 0 0

OC1M

[2:0]

CC1

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IC2F[3:0]

IC2

PSC

[1:0]

CC2S

[1:0]

IC1F[3:0]

IC1

PSC

[1:0]

CC1

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OC4M

[2:0]

CC4S

[1:0]

OC3M

[2:0]

CC3

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IC4F[3:0]

IC4

PSC

[1:0]

CC4S

[1:0]

IC3F[3:0]

IC3

PSC

[1:0]

CC3

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

CNT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSC[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0368 Rev 5

RM0368 Advanced-control timer (TIM1)

Table 52. TIM1 register map and reset values (continued)

Offset Register

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x4C

TIMx_ARR

Reset value

TIMx_RCR

Reset value

TIMx_CCR1

Reset value

TIMx_CCR2

Reset value

TIMx_CCR3

Reset value

TIMx_CCR4

Reset value

TIMx_BDTR

Reset value

TIMx_DCR

Reset value

TIMx_DMAR

Reset value

ARR[15:0]

Reserved

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

REP[7:0]

0 0 0 0 0 0 0 0

CCR1[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR2[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR3[15:0]

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR4[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOCK

[1:0]

DT[7:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

DBL[4:0]

0 0 0 0 0

Reserved

DBA[4:0]

0 0 0 0 0

DMAB[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 3.3: Memory map for the register boundary addresses.

RM0368 Rev 5

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General-purpose timers (TIM2 to TIM5)

13 General-purpose timers (TIM2 to TIM5)

RM0368

13.1 TIM2 to TIM5 introduction

The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler.

They may be used for a variety of purposes, including measuring the pulse lengths of input signals ( input capture ) or generating output waveforms ( output compare and PWM ).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

The timers are completely independent, and do not share any resources. They can be synchronized together as described in

Section 13.3.15

13.2 TIM2 to TIM5 main features

General-purpose TIMx timer features include:

• 16-bit (TIM3 and TIM4) or 32-bit (TIM2 and TIM5) up, down, up/down auto-reload counter.

• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536.

• Up to 4 independent channels for:

– Input capture

– Output compare

– PWM generation (Edge- and Center-aligned modes)

– One-pulse mode output

• Synchronization circuit to control the timer with external signals and to interconnect several timers.

• Interrupt/DMA generation on the following events:

– Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)

– Trigger event (counter start, stop, initialization or count by internal/external trigger)

– Input capture

– Output compare

• Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes

• Trigger input for external clock or cycle-by-cycle current management

316/847

RM0368 Rev 5

RM0368

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Figure 87. General-purpose timer block diagram

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13.3 TIM2 to TIM5 functional description

The main block of the programmable timer is a 16-bit/32-bit counter with its related autoreload register. The counter can count up. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)

• Prescaler Register (TIMx_PSC):

• Auto-Reload Register (TIMx_ARR)

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General-purpose timers (TIM2 to TIM5) RM0368

TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 88

and

Figure 89 give some examples of the counter behavior when the prescaler

ratio is changed on the fly:

Figure 88. Counter timing diagram with prescaler division change from 1 to 2

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Figure 89. Counter timing diagram with prescaler division change from 1 to 4

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Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An Update event can be generated at each counter overflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.

This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)

• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

RM0368 Rev 5

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375

General-purpose timers (TIM2 to TIM5)

Figure 90. Counter timing diagram, internal clock divided by 1

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Figure 91. Counter timing diagram, internal clock divided by 2

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Figure 92. Counter timing diagram, internal clock divided by 4

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Figure 93. Counter timing diagram, internal clock divided by N

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Figure 94. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)

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RM0368 Rev 5

321/847

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General-purpose timers (TIM2 to TIM5) RM0368

Figure 95. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)

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Downcounting mode

In downcounting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.

An Update event can be generate at each counter underflow or by setting the UG bit in the

TIMx_EGR register (by software or by using the slave mode controller)

However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

• The auto-reload active register is updated with the preload value (content of the

TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

322/847

RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Figure 96. Counter timing diagram, internal clock divided by 1

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Figure 97. Counter timing diagram, internal clock divided by 2

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Figure 98. Counter timing diagram, internal clock divided by 4

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RM0368 Rev 5

323/847

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General-purpose timers (TIM2 to TIM5)

Figure 99. Counter timing diagram, internal clock divided by N

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Figure 100. Counter timing diagram, Update event

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Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to

CMS = "11").

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter.

0, as well as the counter of the prescaler.

However, the counter continues counting up and down, based on the current auto-reload value.

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

• The auto-reload active register is updated with the preload value (content of the

The following figures show some examples of the counter behavior for different clock frequencies.

Figure 101. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

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1. Here, center-aligned mode 1 is used, for more details refer to Section 13.4.1: TIMx control register 1 (TIMx_CR1)

RM0368 Rev 5

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375

General-purpose timers (TIM2 to TIM5)

Figure 102. Counter timing diagram, internal clock divided by 2

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Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

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Figure 104. Counter timing diagram, internal clock divided by N

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Figure 105. Counter timing diagram, Update event with ARPE=1 (counter underflow)

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Figure 106. Counter timing diagram, Update event with ARPE=1 (counter overflow)

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The counter clock can be provided by the following clock sources:

• Internal clock (CK_INT)

• External clock mode1: external input pin (TIx)

• External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 only.

• Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, Timer can be configured to act as a prescaler for Timer 2. Refer to

Using one timer as prescaler for another timer

for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the

CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 107 shows the behavior of the control circuit and the upcounter in normal mode,

without prescaler.

Figure 107. Control circuit in normal mode, internal clock divided by 1

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External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on a selected input.

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RM0368 General-purpose timers (TIM2 to TIM5)

Figure 108. TI2 external clock connection example

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For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the

TIMx_CCMR1 register.

2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).

The capture prescaler is not used for triggering, so there’s no need to configure it.

3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register.

4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.

5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.

6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.

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General-purpose timers (TIM2 to TIM5)

Figure 109. Control circuit in external clock mode 1

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External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input ETR.

Figure 110 gives an overview of the external trigger input block.

Figure 110. External trigger input block

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For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register

4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.

Figure 111. Control circuit in external clock mode 2

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Each Capture/Compare channel (see Figure 112 ) is built around a capture/compare register

(including a shadow register), an input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Figure 112. Capture/compare channel (example: channel 1 input stage)

TI1F_ED to the slave mode controller

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The output stage generates an intermediate waveform which is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

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Figure 113. Capture/compare channel 1 main circuit

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The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

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RM0368 General-purpose timers (TIM2 to TIM5)

Note:

TIMx_CCRx register. CCxOF is cleared when written to 0.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

• Program the needed input filter duration with respect to the signal connected to the timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at must five internal clock cycles. We must program a filter duration longer than these five clock cycles. We can validate a transition on TI1 when eight consecutive samples with the new level have been detected (sampled at f

DTS

0011 in the TIMx_CCMR1 register.

frequency). Then write IC1F bits to

• Select the edge of the active transition on the TI1 channel by writing the CC1P and

CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).

• Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the

TIMx_CCMR1 register).

• Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

• If needed, enable the related interrupt request by setting the CC1IE bit in the

TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the

TIMx_DIER register.

When an input capture occurs:

• The TIMx_CCR1 register gets the value of the counter on the active transition.

• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

• An interrupt is generated depending on the CC1IE bit.

• A DMA request is generated depending on the CC1DE bit.

IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

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13.3.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:

• Two ICx signals are mapped on the same TIx input.

• These 2 ICx signals are active on edges with opposite polarity.

• One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle

(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure

(depending on CK_INT frequency and prescaler value):

• Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).

• Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).

• Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).

• Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).

• Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register

(TI1FP1 selected).

• Configure the slave mode controller in reset mode: write the SMS bits to 100 in the

TIMx_SMCR register.

• Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.

Figure 115. PWM input mode timing

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13.3.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (ocxref/OCx) to its active level, the user just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.

ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.

This function is used to control an output waveform or indicating when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the

TIMx_DIER register).

• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the

TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the

OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on ocxref and OCx output.

The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).

Procedure:

Select the counter clock (internal, external, prescaler).

2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated.

4. Select the output mode. For example, the user must write OCxM=011, OCxPE=0,

CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high.

5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

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The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in

Figure 116 .

Figure 116. Output compare mode, toggle on OC1

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Pulse width modulation mode allows generating a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. The user must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, the user has to initialize all the registers by setting the

UG bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). However, to comply with the ETRF (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only:

• When the result of the comparison changes, or

• When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes

(OCxM=‘110 or ‘111).

This forces the PWM by software while the timer is running.

RM0368 Rev 5

069

RM0368 General-purpose timers (TIM2 to TIM5)

The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration

Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to

Upcounting mode

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in

TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.

If the compare value is 0 then OCxREF is held at ‘0.

Figure 117

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PWM waveforms in an example where TIMx_ARR=8.

Figure 117. Edge-aligned PWM waveforms (ARR=8)

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Downcounting configuration

Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode

In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in

TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from

‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts

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General-purpose timers (TIM2 to TIM5) RM0368 up and down depending on the CMS bits configuration. The direction bit (DIR) in the

TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to

Center-aligned mode (up/down counting)

Figure 118 shows some center-aligned PWM waveforms in an example where:

• TIMx_ARR=8,

• PWM mode is the PWM mode 1,

• The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.

Figure 118. Center-aligned PWM waveforms (ARR=8)

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Hints on using center-aligned mode:

• When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit

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RM0368 General-purpose timers (TIM2 to TIM5) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.

• Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:

– The direction is not updated if the user writes a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up.

– The direction is updated if the user writes 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated.

• The safest way to use center-aligned mode is to generate an update by software

(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

• In upcounting: CNT<CCRx ≤ ARR (in particular, 0<CCRx),

• In downcounting: CNT>CCRx.

Figure 119. Example of one-pulse mode

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For example the user may want to generate a positive pulse on OC1 with a length of t

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Let’s use TI2FP2 as trigger 1:

• Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.

• TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register.

• Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.

• TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register

(trigger mode).

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

• The t

DELAY is defined by the value written in the TIMx_CCR1 register.

• The t

PULSE

is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR + 1).

• Let us say user wants to build a waveform with a transition from ‘0 to ‘1 when a compare match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload value. To do this enable PWM mode 2 by writing OC1M=111 in the

TIMx_CCMR1 register. The user can optionally enable the preload registers by writing

OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case write the compare value in the TIMx_CCR1 register, the auto-reload value in the

TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0 in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.

User only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the

Repetitive Mode is selected.

Particular case: OCx fast enable:

DELAY

min we can get.

To output a waveform with the minimum delay, the user can set the OCxFE bit in the

TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

The OCxREF signal for a given channel can be driven Low by applying a High level to the

ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The

OCxREF signal remains Low until the next update event, UEV, occurs.

This function can only be used in output compare and PWM modes, and does not work in forced mode.

For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, ETR must be configured as follows:

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The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00.

2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0.

3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.

Figure 120 shows the behavior of the OCxREF signal when the ETRF input becomes high,

for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in

PWM mode.

Figure 120. Clearing TIMx OCxREF

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1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow.

To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.

Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, program the input filter as well.

The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to

Table 53 . The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2

after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,

TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in

TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.

Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the

TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the user must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal.

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The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time.

Active edge

Counting on

TI1 only

Counting on

TI2 only

Counting on

TI1 and TI2

Table 53. Counting direction versus encoder signals

Level on opposite signal (TI1FP1 for

TI2, TI2FP2 for TI1)

TI1FP1 signal

Rising Falling

TI2FP2 signal

Rising Falling

High

Low

High

Low

High

Low

Down

No Count

Down

No Count

Down

No Count

Down

No Count

Down

Figure 121 gives an example of counter operation, showing count signal generation and

direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:

• CC1S= ‘01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1)

• CC2S= ‘01’ (TIMx_CCMR2 register, TI2FP2 mapped on TI2)

• CC1P= ‘0’, CC1NP = ‘0’, IC1F =’0000’ (TIMx_CCER register, TI1FP1 noninverted,

TI1FP1=TI1)

• CC2P= ‘0’, CC2NP = ‘0’, IC2F =’0000’ (TIMx_CCER register, TI2FP2 noninverted,

TI2FP2=TI2)

• SMS= ‘011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges)

• CEN = 1 (TIMx_CR1 register, Counter is enabled)

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Figure 121. Example of counter operation in encoder interface mode

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Figure 122 gives an example of counter behavior when TI1FP1 polarity is inverted (same

configuration as above except CC1P=1).

Figure 122. Example of encoder interface mode with TI1FP1 polarity inverted

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The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. The user can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. The user can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a

DMA request generated by a Real-Time clock.

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13.3.13 Timer input XOR function

The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.

The XOR output can be used with all the timer input functions such as trigger or input capture.

13.3.14 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on TI1 input:

• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. The

CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity

(and detect rising edges only).

• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

• Start the counter by writing CEN=1 in the TIMx_CR1 register.

Figure 123 shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay

between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.

Figure 123. Control circuit in reset mode

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. The

CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.

Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).

• Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

• Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level).

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.

Figure 124. Control circuit in gated mode

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1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect in gated mode because gated mode acts on a level and not on an edge.

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on TI2 input:

• Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so the user does not need to configure it. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write

CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only).

• Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI2 as the input source by writing TS=110 in TIMx_SMCR register.

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When a rising edge occurs on TI2, the counter starts counting on the internal clock and the

TIF flag is set.

The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.

Figure 125. Control circuit in trigger mode

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Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register.

In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:

Configure the external trigger input circuit by programming the TIMx_SMCR register as follows:

– ETF = 0000: no filter

– ETPS = 00: prescaler disabled

– ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.

2. Configure the channel 1 as follows, to detect rising edges on TI:

– IC1F = 0000: no filter.

– The capture prescaler is not used for triggering and does not need to be configured.

– CC1S = 01 in TIMx_CCMR1 register to select only the input capture source

– CC1P = 0 in TIMx_CCER register to validate the polarity (and detect rising edge only).

3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=101 in TIMx_SMCR register.

A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on

ETR rising edges.

The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.

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Figure 126. Control circuit in external clock mode 2 + trigger mode

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Note:

The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.

Figure 127 presents an overview of the trigger selection and the master mode selection

blocks.

The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Using one timer as prescaler for another timer

Figure 127. Master/Slave timer example

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Note:

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For example, the user can configure Timer 1 to act as a prescaler for Timer 2 (see

Figure 127 ). To do this:

• Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is output on TRGO1 each time an update event is generated.

• To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in slave mode using ITR0 as internal trigger. You select this through the TS bits in the

TIM2_SMCR register (writing TS=000).

• Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the

TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).

• Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register).

If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer 2.

Using one timer to enable another timer

In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.

Refer to Figure 127

for connections. Timer 2 counts on the divided internal clock only when

OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f

CK_CNT

= f

CK_INT

/3).

• Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).

• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).

• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).

• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).

• Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).

• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 counter enable signal.

Figure 128. Gating timer 2 with OC1REF of timer 1

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In the example in Figure 128 , the Timer 2 counter and prescaler are not initialized before

being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer 1. You can then write any value

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In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 register:

• Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).

• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).

• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).

• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).

• Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).

• Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).

• Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).

• Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).

• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

• Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).

Figure 129. Gating timer 2 with Enable of timer 1

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Using one timer to start another timer

In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to

Figure 127 for connections. Timer 2 starts counting from its current value (which can be

nonzero) on the divided internal clock as soon as the update event is generated by Timer 1.

When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f

CK_CNT

= f

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/3).

• Configure Timer 1 master mode to send its Update Event (UEV) as trigger output

(MMS=010 in the TIM1_CR2 register).

• Configure the Timer 1 period (TIM1_ARR registers).

• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).

• Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).

• Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).

Figure 130. Triggering timer 2 with update of timer 1

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As in the previous example, the user can initialize both counters before starting counting.

Figure 131 shows the behavior with the same configuration as in

Figure 130

but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register).

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Note:

General-purpose timers (TIM2 to TIM5)

Figure 131. Triggering timer 2 with Enable of timer 1

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Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of

Timer 2 with the enable of Timer 1. Refer to

Figure 127 for connections. To ensure the

counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2):

• Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the

TIM1_CR2 register).

• Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the

TIM1_SMCR register).

• Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).

• Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).

• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register).

• Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).

When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set.

In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer 1.

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Figure 132. Triggering timer 1 and 2 with timer 1 TI1 input

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When the microcontroller enters debug mode (Cortex ® -M4 with FPU core - halted), the

TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP

configuration bit in DBGMCU module. For more details, refer to Section 23.16.2: Debug support for timers, watchdog and I2C .

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13.4 TIM2 to TIM5 registers

Refer to Section 2.2

for a list of abbreviations used in register descriptions.

The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

13.4.1 TIMx control register 1 (TIMx_CR1)

15 14

Address offset: 0x00

Reset value: 0x0000

13 12 11 10

Reserved

9 8

CKD[1:0] rw rw

ARPE rw

6 5 rw

CMS rw

DIR rw

OPM rw

URS rw

UDIS rw

CEN rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD : Clock division

This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),

00: t

DTS

= t

CK_INT

01: t

DTS

= 2 × t

CK_INT

10: t

DTS

= 4 × t

CK_INT

11: Reserved

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:5 CMS : Center-aligned mode selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit

(DIR).

Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)

Bit 4 DIR : Direction

0: Counter used as upcounter

1: Counter used as downcounter

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generate an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow

– Setting the UG bit

– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

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13.4.2 TIMx control register 2 (TIMx_CR2)

15 14

Address offset: 0x04

Reset value: 0x0000

13 12 11 10 9 8

Reserved

TI1S rw

6 rw

MMS[2:0] rw

4 rw

CCDS rw

2 1

Reserved

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TI1S : TI1 selection

0: The TIMx_CH1 pin is connected to TI1 input

1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)

Bits 6:4 MMS[2:0] : Master mode selection

These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.

(TRGO)

100: Compare - OC1REF signal is used as trigger output (TRGO)

101: Compare - OC2REF signal is used as trigger output (TRGO)

110: Compare - OC3REF signal is used as trigger output (TRGO)

111: Compare - OC4REF signal is used as trigger output (TRGO)

Note: The clock of the slave timer and ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bit 3 CCDS : Capture/compare DMA selection

0: CCx DMA request sent when CCx event occurs

1: CCx DMA requests sent when update event occurs

Bits 2:0 Reserved, must be kept at reset value.

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13.4.3 TIMx slave mode control register (TIMx_SMCR)

ETP rw

Address offset: 0x08

ECE rw

Reset value: 0x0000

13 12

ETPS[1:0] rw rw

11 rw

ETF[3:0]

9 rw rw

8 rw

MSM rw

6 rw

TS[2:0] rw

4 rw

Res.

2 rw

SMS[2:0] rw

0 rw

Bit 15 ETP : External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations

0: ETR is noninverted, active at high level or rising edge

1: ETR is inverted, active at low level or falling edge

Bit 14 ECE : External clock enable

This bit enables External clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111).

2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to

ETRF in this case (TS bits must not be 111).

3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.

Bits 13:12 ETPS : External trigger prescaler

External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.

00: Prescaler OFF

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

Bits 11:8 ETF[3:0] : External trigger filter

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

0100: f

SAMPLING

CK_INT

DTS

, N=2

, N=4

, N=8

/2, N=6

/2, N=8 0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/4, N=6

/4, N=8

1000: f

SAMPLING

DTS

/8, N=6

/8, N=8 1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

1100: f

SAMPLING

DTS

/16, N=5

/16, N=6

/16, N=8

/32, N=5 1101: f

SAMPLING

1110: f

SAMPLING

1111: f

SAMPLING

DTS

/32, N=6

/32, N=8

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Bit 7 MSM: Master/Slave mode

0: No action

Bits 6:4 TS: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

000: Internal Trigger 0 (ITR0).

001: Internal Trigger 1 (ITR1).

010: Internal Trigger 2 (ITR2).

011: Internal Trigger 3 (ITR3).

100: TI1 Edge Detector (TI1F_ED)

101: Filtered Timer Input 1 (TI1FP1)

110: Filtered Timer Input 2 (TI2FP2)

111: External Trigger input (ETRF)

See

Table 54: TIMx internal trigger connection on page 358 for more details on ITRx

meaning for each Timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 SMS: Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.

000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.

001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.

010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.

011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.

100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.

110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.

111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).

Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.

The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

RM0368 Rev 5

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General-purpose timers (TIM2 to TIM5) RM0368

Slave TIM

TIM2

TIM3

TIM4

TIM5

Table 54. TIMx internal trigger connection

ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010)

TIM1_TRGO

TIM2_TRGO

Reserved

TIM2_TRGO

TIM3_TRGO

TIM5_TRGO

TIM3_TRGO

TIM4_TRGO

ITR3 (TS = 011)

TIM4_TRGO

Reserved

13.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)

Res.

TDE rw

Address offset: 0x0C

Reset value: 0x0000

Res

12 11 10 9 8

CC4DE CC3DE CC2DE CC1DE UDE rw rw rw rw rw

Res.

TIE rw

Res

4 3 2 1

CC4IE CC3IE CC2IE CC1IE rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE : Trigger DMA request enable

0: Trigger DMA request disabled.

1: Trigger DMA request enabled.

Bit 13 Reserved, always read as 0

Bit 12 CC4DE : Capture/Compare 4 DMA request enable

0: CC4 DMA request disabled.

1: CC4 DMA request enabled.

Bit 11 CC3DE : Capture/Compare 3 DMA request enable

0: CC3 DMA request disabled.

1: CC3 DMA request enabled.

Bit 10 CC2DE : Capture/Compare 2 DMA request enable

0: CC2 DMA request disabled.

1: CC2 DMA request enabled.

Bit 9 CC1DE : Capture/Compare 1 DMA request enable

0: CC1 DMA request disabled.

1: CC1 DMA request enabled.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bit 7 Reserved, must be kept at reset value.

Bit 6 TIE : Trigger interrupt enable

0: Trigger interrupt disabled.

1: Trigger interrupt enabled.

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4IE : Capture/Compare 4 interrupt enable

0: CC4 interrupt disabled.

1: CC4 interrupt enabled.

UIE rw

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Bit 3 CC3IE : Capture/Compare 3 interrupt enable

0: CC3 interrupt disabled.

1: CC3 interrupt enabled.

Bit 2 CC2IE : Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled

1: CC2 interrupt enabled

Bit 1 CC1IE : Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled

1: Update interrupt enabled

13.4.5 TIMx status register (TIMx_SR)

Address offset: 0x10

Reserved

Reset value: 0x0000

13 12 11 10 9

CC4OF CC3OF CC2OF CC1OF rc_w0 rc_w0 rc_w0 rc_w0

8 7

Reserved

TIF rc_w0

Res

4 3 2 1

CC4IF CC3IF CC2IF CC1IF

UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CC4OF : Capture/Compare 4 overcapture flag refer to CC1OF description

Bit 11 CC3OF : Capture/Compare 3 overcapture flag refer to CC1OF description

Bit 10 CC2OF : Capture/compare 2 overcapture flag refer to CC1OF description

Bit 9 CC1OF : Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0.

0: No overcapture has been detected

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 TIF : Trigger interrupt flag

0: No trigger event occurred

1: Trigger interrupt pending

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4IF : Capture/Compare 4 interrupt flag refer to CC1IF description

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Bit 3 CC3IF : Capture/Compare 3 interrupt flag refer to CC1IF description

Bit 2 CC2IF : Capture/Compare 2 interrupt flag refer to CC1IF description

Bit 1 CC1IF : Capture/compare 1 interrupt flag

If channel CC1 is configured as output:

0: No match

1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.

When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow

(in downcounting mode)

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the

TIMx_CCR1 register.

0: No input capture occurred

1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity)

Bit 0 UIF : Update interrupt flag

″ This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

″

At overflow or underflow (for TIM2 to TIM5) and if UDIS=0 in the TIMx_CR1 register.

When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.

When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

15 14

Address offset: 0x14

Reset value: 0x0000

13 12 11 10

Reserved

9 8 7 6

TG w

Res.

4 3 2 1

CC4G CC3G CC2G CC1G w w w w

UG w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG : Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

Bit 5 Reserved, must be kept at reset value.

Bit 4 CC4G : Capture/compare 4 generation refer to CC1G description

Bit 3 CC3G : Capture/compare 3 generation refer to CC1G description

Bit 2 CC2G : Capture/compare 2 generation refer to CC1G description

Bit 1 CC1G : Capture/compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.

If channel CC1 is configured as input:

The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the

CC1IF flag was already high.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).

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General-purpose timers (TIM2 to TIM5) RM0368

OC2CE rw

Address offset: 0x18

Reset value: 0x0000

OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. Take care that the same bit can have a different meaning for the input stage and for the output stage.

14 13

OC2M[2:0]

IC2F[3:0] rw rw

12 rw

11 10

OC2PE OC2FE

IC2PSC[1:0] rw rw

Output compare mode

9 8

CC2S[1:0] rw rw

OC1CE rw

6 5

OC1M[2:0]

IC1F[3:0] rw rw

4 rw

3 2

OC1PE OC1FE

IC1PSC[1:0] rw rw

1 0

CC1S[1:0] rw rw

Bit 15 OC2CE: Output compare 2 clear enable

Bits 14:12 OC2M[2:0] : Output compare 2 mode

Bit 11 OC2PE : Output compare 2 preload enable

Bit 10 OC2FE : Output compare 2 fast enable

Bits 9:8 CC2S[1:0] : Capture/Compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bit 7 OC1CE: Output compare 1 clear enable

OC1CE: Output Compare 1 Clear Enable

0: OC1Ref is not affected by the ETRF input

1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Bits 6:4 OC1M : Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and

OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.

000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter

TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

100: Force inactive level - OC1REF is forced low.

101: Force active level - OC1REF is forced high.

110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as

TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).

111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.

Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.

Bit 3 OC1PE : Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed

(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).

2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Bit 2 OC1FE : Output compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is

ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is

5 clock cycles.

Bits 1:0 CC1S : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output.

01: CC1 channel is configured as input, IC1 is mapped on TI1.

10: CC1 channel is configured as input, IC1 is mapped on TI2.

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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Input capture mode

Bits 15:12 IC2F : Input capture 2 filter

Bits 11:10 IC2PSC[1:0] : Input capture 2 prescaler

Bits 9:8 CC2S : Capture/compare 2 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output.

01: CC2 channel is configured as input, IC2 is mapped on TI2.

10: CC2 channel is configured as input, IC2 is mapped on TI1.

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bits 7:4 IC1F : Input capture 1 filter

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

CK_INT

, N=2

, N=4

, N=8

/2, N=6 0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/2, N=8

/4, N=6

/4, N=8

1000: f

SAMPLING

1001: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5 1010: f

SAMPLING

1011: f

SAMPLING

DTS

/16, N=6

/16, N=8 1100: f

SAMPLING

1101: f

SAMPLING

1110: f

SAMPLING

DTS

1111: f

SAMPLING

DTS

/32, N=5

/32, N=6

/32, N=8

Bits 3:2 IC1PSC : Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).

The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).

00: no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

OC4CE rw

Address offset: 0x1C

Reset value: 0x0000

Refer to the above CCMR1 register description.

14 13

OC4M[2:0]

IC4F[3:0] rw rw

12 rw

11 10

OC4PE OC4FE

IC4PSC[1:0] rw rw

9 8

CC4S[1:0] rw rw

OC3CE rw

6 5

OC3M[2:0]

IC3F[3:0] rw rw

4 rw

Output compare mode

3 2

OC3PE OC3FE

IC3PSC[1:0] rw rw

1 0

CC3S[1:0] rw rw

Bit 15 OC4CE : Output compare 4 clear enable

Bits 14:12 OC4M : Output compare 4 mode

Bit 11 OC4PE : Output compare 4 preload enable

Bit 10 OC4FE : Output compare 4 fast enable

Bits 9:8 CC4S : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).

Bit 7 OC3CE: Output compare 3 clear enable

Bits 6:4 OC3M : Output compare 3 mode

Bit 3 OC3PE : Output compare 3 preload enable

Bit 2 OC3FE : Output compare 3 fast enable

Bits 1:0 CC3S : Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

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General-purpose timers (TIM2 to TIM5) RM0368

Input capture mode

Bits 15:12 IC4F : Input capture 4 filter

Bits 11:10 IC4PSC : Input capture 4 prescaler

Bits 9:8 CC4S : Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC4 channel is configured as output

01: CC4 channel is configured as input, IC4 is mapped on TI4

10: CC4 channel is configured as input, IC4 is mapped on TI3

11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).

Bits 7:4 IC3F : Input capture 3 filter

Bits 3:2 IC3PSC : Input capture 3 prescaler

Bits 1:0 CC3S : Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC3 channel is configured as output

01: CC3 channel is configured as input, IC3 is mapped on TI3

10: CC3 channel is configured as input, IC3 is mapped on TI4

11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

13.4.9 TIMx capture/compare enable register (TIMx_CCER)

Address offset: 0x20

Reset value: 0x0000

CC4NP rw

Res.

13 12 11

CC4P CC4E CC3NP rw rw rw

Res.

9 8 7

CC3P CC3E CC2NP rw rw rw

Res.

5 4 3

CC2P CC2E CC1NP rw rw rw

Res.

1 0

CC1P CC1E rw rw

Bit 15 CC4NP : Capture/Compare 4 output Polarity.

Refer to CC1NP description

Bit 14 Reserved, must be kept at reset value.

Bit 13 CC4P : Capture/Compare 4 output Polarity.

refer to CC1P description

Bit 12 CC4E : Capture/Compare 4 output enable.

refer to CC1E description

Bit 11 CC3NP : Capture/Compare 3 output Polarity.

refer to CC1NP description

Bit 10 Reserved, must be kept at reset value.

Bit 9 CC3P : Capture/Compare 3 output Polarity.

refer to CC1P description

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Bit 8 CC3E : Capture/Compare 3 output enable.

refer to CC1E description

Bit 7 CC2NP : Capture/Compare 2 output Polarity.

refer to CC1NP description

Bit 6 Reserved, must be kept at reset value.

Bit 5 CC2P : Capture/Compare 2 output Polarity.

refer to CC1P description

Bit 4 CC2E : Capture/Compare 2 output enable.

refer to CC1E description

Bit 3 CC1NP : Capture/Compare 1 output Polarity.

CC1 channel configured as output:

CC1NP must be kept cleared in this case.

CC1 channel configured as input:

This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CC1P : Capture/Compare 1 output Polarity.

CC1 channel configured as output:

0: OC1 active high

1: OC1 active low

CC1 channel configured as input:

CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.

00: noninverted/rising edge

Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).

01: inverted/falling edge

Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).

10: reserved, do not use this configuration.

11: noninverted/both edges

Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode.

Bit 0 CC1E : Capture/Compare 1 output enable.

CC1 channel configured as output:

0: Off - OC1 is not active

1: On - OC1 signal is output on the corresponding output pin

CC1 channel configured as input:

This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled

1: Capture enabled

CCxE bit

Table 55. Output control bit for standard OCx channels

OCx output state

Output Disabled (OCx=0, OCx_EN=0)

OCx=OCxREF + Polarity, OCx_EN=1

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General-purpose timers (TIM2 to TIM5)

Note:

RM0368

The state of the external IO pins connected to the standard OCx channels depends on the

OCx channel state and the GPIO registers.

31 rw

15 rw

30 rw

14 rw

Address offset: 0x24

Reset value: 0x0000 0000

29 28 27 26 rw

13 rw rw

12 rw rw

11 rw rw

10 rw

25 24 23 22

CNT[31:16] (depending on timers) rw

9 rw

8 rw

7 rw

6 rw

CNT[15:0] rw rw rw

21 rw

Bits 31:16 CNT[31:16] : High counter value (on TIM2 and TIM5).

Bits 15:0 CNT[15:0] : Counter value rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

15 rw

Address offset: 0x28

Reset value: 0x0000

13 12 11 10 rw

9 8 7

PSC[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency CK_CNT is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

13.4.12 TIMx auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF FFFF

31 rw

15 rw

30 rw

14 rw

29 rw

13 rw

28 rw

12 rw

27 rw

11 rw

26 rw

10 rw

25 24

ARR[15:0]

ARR[31:16] (depending on timers) rw rw rw rw

9 6 rw rw rw rw

21 rw

5 rw

20 rw

4 rw

19 rw

3 rw

18 rw

2 rw

17 rw

1 rw

16 rw

0 rw

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 13.3.1: Time-base unit for more details about ARR update and

behavior.

The counter is blocked while the auto-reload value is null.

13.4.13 TIMx capture/compare register 1 (TIMx_CCR1)

31 rw/ro

Address offset: 0x34

30 rw/ro

Reset value: 0x0000 0000

29 28 27 26 rw/ro rw/ro rw/ro rw/ro

25 24 23 22

CCR1[31:16] (depending on timers) rw/ro rw/ro rw/ro rw/ro

21 rw/ro

20 rw/ro

19 18 17 rw/ro rw/ro rw/ro

16 rw/ro

15 rw/ro

14 rw/ro

13 rw/ro

12 rw/ro

11 rw/ro

10 rw/ro

9 rw/ro

8 7

CCR1[15:0] rw/ro rw/ro

6 rw/ro

5 rw/ro

4 rw/ro

3 rw/ro

2 rw/ro

1 rw/ro

0 rw/ro

Bits 31:16 CCR1[31:16] : High Capture/Compare 1 value (on TIM2 and TIM5).

Bits 15:0 CCR1[15:0] : Low Capture/Compare 1 value

If channel CC1 is configured as output :

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register

(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input :

CCR1 is the counter value transferred by the last input capture 1 event (IC1). The

TIMx_CCR1 register is read-only and cannot be programmed.

13.4.14 TIMx capture/compare register 2 (TIMx_CCR2)

31 rw/ro

Address offset: 0x38

30 rw/ro

Reset value: 0x0000 0000

29 28 27 26 rw/ro rw/ro rw/ro rw/ro

25 24 23 22

CCR2[31:16] (depending on timers) rw/ro rw/ro rw/ro rw/ro

21 rw/ro

20 rw/ro

19 18 17 rw/ro rw/ro rw/ro

16 rw/ro

15 14 13 12 rw/ro rw/ro rw/ro rw/ro

11 10 rw/ro rw/ro

9 rw/ro

8 7

CCR2[15:0] rw/ro rw/ro

6 rw/ro

5 4 3 2 1 0 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

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General-purpose timers (TIM2 to TIM5) RM0368

Bits 31:16 CCR2[31:16] : High Capture/Compare 2 value (on TIM2 and TIM5).

Bits 15:0 CCR2[15:0] : Low Capture/Compare 2 value

If channel CC2 is configured as output:

CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit

OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC2 output.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 2 event (IC2). The

TIMx_CCR2 register is read-only and cannot be programmed.

13.4.15 TIMx capture/compare register 3 (TIMx_CCR3)

31 rw/ro

Address offset: 0x3C

30 rw/ro

Reset value: 0x0000 0000

29 28 27 26 rw/ro rw/ro rw/ro rw/ro

25 24 23 22

CCR3[31:16] (depending on timers) rw/ro rw/ro rw/ro rw/ro

21 rw/ro

20 rw/ro

19 18 17 rw/ro rw/ro rw/ro

16 rw/ro

15 rw/ro

14 rw/ro

13 rw/ro

12 rw/ro

11 rw/ro

10 rw/ro

9 rw/ro

8 7

CCR3[15:0] rw/ro rw/ro

6 rw/ro

5 rw/ro

4 rw/ro

3 rw/ro

2 rw/ro

1 rw/ro

0 rw/ro

Bits 31:16 CCR3[31:16] : High Capture/Compare 3 value (on TIM2 and TIM5).

Bits 15:0 CCR3[15:0] : Low Capture/Compare value

If channel CC3 is configured as output:

CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit

OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC3 output.

If channel CC3 is configured as input:

CCR3 is the counter value transferred by the last input capture 3 event (IC3). The

TIMx_CCR3 register is read-only and cannot be programmed.

13.4.16 TIMx capture/compare register 4 (TIMx_CCR4)

31 rw/ro

15 rw/ro

Address offset: 0x40

30 rw/ro

14 rw/ro

Reset value: 0x0000 0000

29 28 27 26 rw/ro

13 rw/ro rw/ro

12 rw/ro rw/ro

11 rw/ro rw/ro

10 rw/ro

25 24

CCR4[15:0]

CCR4[31:16] (depending on timers) rw/ro rw/ro rw/ro rw/ro

9 6 rw/ro rw/ro rw/ro rw/ro

21 rw/ro

5 rw/ro

20 rw/ro

4 rw/ro

19 18 17 rw/ro

3 rw/ro

2 rw/ro

1 rw/ro rw/ro rw/ro

16 rw/ro

0 rw/ro

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RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Bits 31:16 CCR4[31:16] : High Capture/Compare 4 value (on TIM2 and TIM5).

Bits 15:0 CCR4[15:0] : Low Capture/Compare value

if CC4 channel is configured as output (CC4S bits):

CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register

(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signalled on OC4 output.

2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):

CCR4 is the counter value transferred by the last input capture 4 event (IC4). The

TIMx_CCR4 register is read-only and cannot be programmed.

13.4.17 TIMx DMA control register (TIMx_DCR)

Address offset: 0x48

Reserved

Reset value: 0x0000

13 12 11 rw rw

DBL[4:0] rw

9 rw

8 rw

7 6

Reserved

5 4 3 rw

DBA[4:0] rw

1 rw

0 rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0] : DMA burst length

This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).

00000: 1 transfer,

00001: 2 transfers,

00010: 3 transfers,

...

10001: 18 transfers.

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DBA[4:0] : DMA base address

This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.

Example:

00000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR,

...

Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

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General-purpose timers (TIM2 to TIM5) RM0368

13.4.18 TIMx DMA address for full transfer (TIMx_DMAR)

15 14

Address offset: 0x4C

Reset value: 0x0000

13 12 11 10 9 6 5 4 rw rw rw rw rw rw rw

8 7

DMAB[15:0] rw rw rw rw rw

3 2 1 0 rw rw rw rw

Bits 15:0 DMAB[15:0] : DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address

DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

Note:

Example of how to use the DMA burst feature

In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.

This is done in the following steps:

Configure the corresponding DMA channel as follows:

– DMA channel peripheral address is the DMAR register address

– DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.

– Number of data to transfer = 3 (See note below).

– Circular mode disabled.

2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:

DBL = 3 transfers, DBA = 0xE.

3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).

5. Enable the DMA channel

CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

372/847

RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

13.4.19 TIM2 option register (TIM2_OR)

Address offset: 0x50

Reset value: 0x0000

15 14 13

Reserved

12 11 10

ITR1_RMP rw rw

9 8 7 6 5 4

Reserved

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:10 ITR1_RMP: Internal trigger 1 remap

Set and cleared by software.

00: Reserved

01: PTP trigger output is connected to TIM2_ITR1

10: OTG FS SOF is connected to the TIM2_ITR1 input

11: OTG HS SOF is connected to the TIM2_ITR1 input

Bits 9:0 Reserved, must be kept at reset value.

3 2 1 0

13.4.20 TIM5 option register (TIM5_OR)

Address offset: 0x50

Reset value: 0x0000

15 14 13 12 11

Reserved

10 9 8 7 6

TI4_RMP rw rw

5 4 3 2

Reserved

1 0

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:6 TI4_RMP: Timer Input 4 remap

Set and cleared by software.

00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table in the datasheets.

01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes

10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes

11: the RTC wakeup interrupt is connected to TIM5_CH4 input for calibration purposes.

Wakeup interrupt should be enabled.

Bits 5:0 Reserved, must be kept at reset value.

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375

General-purpose timers (TIM2 to TIM5) RM0368

13.4.21 TIMx register map

TIMx registers are mapped as described in the table below:

Table 56. TIM2 to TIM5 register map and reset values

Offset Register

0x00

0x04

0x08

TIMx_CR1

Reset value

TIMx_CR2

Reset value

TIMx_SMCR

Reset value

TIMx_DIER

0x0C

Reset value

TIMx_SR

0x10

0x14

0x18

0x1C

Reset value

TIMx_EGR

Reset value

TIMx_CCMR1

Output Compare mode

Reset value

TIMx_CCMR1

Input Capture mode

Reset value

TIMx_CCMR2

Output Compare mode

Reset value

TIMx_CCMR2

Input Capture mode

Reset value

Reserved

CKD

[1:0]

CMS

[1:0]

0 0 0 0 0 0 0 0 0 0

MMS[2:0]

Reserved

0 0 0 0 0

ETPS

[1:0]

ETF[3:0] TS[2:0]

0 0 0 0 0 0 0 0 0 0 0 0

SMS[2:0]

0 0 0

0 0 0 0 0 0 0

0 0 0 0

0 0 0 0 0

OC2M

[2:0]

CC2S

[1:0]

OC1M

[2:0]

0 0 0 0 0

CC1S

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IC2F[3:0]

IC2

PSC

[1:0]

CC2S

[1:0]

IC1F[3:0]

IC1

PSC

[1:0]

CC1S

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OC4M

[2:0]

CC4S

[1:0]

OC3M

[2:0]

CC3S

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IC4F[3:0]

IC4

PSC

[1:0]

CC4S

[1:0]

IC3F[3:0]

IC3

PSC

[1:0]

CC3S

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x20

0x24

0x28

TIMx_CCER

Reset value

TIMx_CNT

Reset value

TIMx_PSC

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0

CNT[31:16]

(TIM2 and TIM5 only, reserved on the other timers)

CNT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

PSC[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

374/847

RM0368 Rev 5

RM0368 General-purpose timers (TIM2 to TIM5)

Offset

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

Register

Table 56. TIM2 to TIM5 register map and reset values (continued)

TIMx_ARR

Reset value

TIMx_CCR1

Reset value

TIMx_CCR2

Reset value

TIMx_CCR3

Reset value

TIMx_CCR4

Reset value

ARR[31:16]

(TIM2 and TIM5 only, reserved on the other timers)

ARR[15:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Reserved

CCR1[31:16]

(TIM2 and TIM5 only, reserved on the other timers)

CCR1[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR2[31:16]

(TIM2 and TIM5 only, reserved on the other timers)

CCR2[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR3[31:16]

(TIM2 and TIM5 only, reserved on the other timers)

CCR3[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR4[31:16]

(TIM2 and TIM5 only, reserved on the other timers)

CCR4[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

0x48

0x4C

0x50

TIMx_DCR

Reset value

TIMx_DMAR

Reset value

TIM2_OR

Reset value

TIM5_OR

Reset value

Reserved

DBL[4:0]

0 0 0 0 0

Reserved

DBA[4:0]

0 0 0 0 0

DMAB[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

ITR1_

RMP

0 0

Reserved

IT4_

RMP

0 0

Reserved

Refer to Section 3.3: Memory map for the register boundary addresses.

RM0368 Rev 5

375/847

375

General-purpose timers (TIM9 to TIM11)

14 General-purpose timers (TIM9 to TIM11)

RM0368

TIM12, TIM13 and TIM14 are not available in STM32F401xB/C and STM32F401xD/E.

The TIM9/10/11 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

The TIM9/10/11 timers are completely independent, and do not share any resources. They can be synchronized together as described in

Section 14.3.12

14.2.1 TIM9 main features

The features of the TIM9 general-purpose timer include:

• 16-bit auto-reload upcounter

• 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”)

• Up to 2 independent channels for:

– Input capture

– Output compare

– PWM generation (edge-aligned mode)

– One-pulse mode output

• Synchronization circuit to control the timer with external signals and to interconnect several timers together

• Interrupt generation on the following events:

– Update: counter overflow, counter initialization (by software or internal trigger)

– Trigger event (counter start, stop, initialization or count by internal trigger)

– Input capture

– Output compare

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RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

Figure 133. General-purpose timer block diagram (TIM9)

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14.2.2 TIM10/TIM11 main features

The features of general-purpose timers TIM10/TIM11 include:

• 16-bit auto-reload upcounter

• 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”)

• independent channel for:

– Input capture

– Output compare

– PWM generation (edge-aligned mode)

– One-pulse mode output

• Interrupt generation on the following events:

– Update: counter overflow, counter initialization (by software)

– Input capture

– Output compare

RM0368 Rev 5

377/847

421

General-purpose timers (TIM9 to TIM11)

Figure 134. General-purpose timer block diagram (TIM10/11)

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RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

14.3 TIM9 to TIM11 functional description

The main block of the timer is a 16-bit counter with its related auto-reload register.

The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)

• Prescaler register (TIMx_PSC)

• Auto-reload register (TIMx_ARR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in details for each configuration.

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 135 and Figure 136 give some examples of the counter behavior when the prescaler

ratio is changed on the fly.

RM0368 Rev 5

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421

General-purpose timers (TIM9 to TIM11) RM0368

Figure 135. Counter timing diagram with prescaler division change from 1 to 2

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Figure 136. Counter timing diagram with prescaler division change from 1 to 4

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RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

Upcounting mode

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

Setting the UG bit in the TIMx_EGR register (by software ) also generates an update event.

However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in

TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR register) is set (depending on the URS bit):

• The auto-reload shadow register is updated with the preload value (TIMx_ARR),

• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 137. Counter timing diagram, internal clock divided by 1

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Figure 138. Counter timing diagram, internal clock divided by 2

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Figure 139. Counter timing diagram, internal clock divided by 4

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Figure 140. Counter timing diagram, internal clock divided by N

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RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

Figure 141. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

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Figure 142. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

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General-purpose timers (TIM9 to TIM11) RM0368

The counter clock can be provided by the following clock sources:

• Internal clock (CK_INT)

• External clock mode1 (for TIM9 ): external input pin (TIx)

• Internal trigger inputs (ITRx) (for TIM9 ): connecting the trigger output from another

timer. Refer to Using one timer as prescaler for another timer

for more details.

Internal clock source (CK_INT)

The internal clock source is the default clock source for TIM10/TIM11.

For TIM9, the internal clock source is selected when the slave mode controller is disabled

(SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR register are then used as control bits and can be changed only by software (except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 143 shows the behavior of the control circuit and of the upcounter in normal mode,

without prescaler.

Figure 143. Control circuit in normal mode, internal clock divided by 1

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TIM9)

This mode is selected when SMS=’111’ in the TIMx_SMCR register.

The counter can count at each rising or falling edge on a selected input.

384/847

RM0368 Rev 5

RM0368

Note:

General-purpose timers (TIM9 to TIM11)

Figure 144. TI2 external clock connection example

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For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:

Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.

2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=’0000’).

3. Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register.

4. Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR register.

5. Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register.

6. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register.

The capture prescaler is not used for triggering, so no need to configure it.

When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.

Figure 145. Control circuit in external clock mode 1

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Figure 146

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give an overview of a capture/compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Figure 146. Capture/compare channel (example: channel 1 input stage)

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The output stage generates an intermediate waveform which is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

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Figure 147. Capture/compare channel 1 main circuit

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Figure 148. Output stage of capture/compare channel (channel 1)

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The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

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Note:

RM0368 cleared by software by writing it to ‘0’ or by reading the captured data stored in the

TIMx_CCRx register. CCxOF is cleared when the user writes it to ‘0’.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, the channel is configured in input mode and the TIMx_CCR1 register becomes readonly.

2. Program the needed input filter duration with respect to the signal connected to the timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at f

DTS

‘0011’ in the TIMx_CCMR1 register.

frequency). Then write IC1F bits to

3. Select the edge of the active transition on the TI1 channel by programming CC1P and

CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).

4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the

TIMx_CCMR1 register).

5. Enable capture from the counter into the capture register by setting the CC1E bit in the

TIMx_CCER register.

6. If needed, enable the related interrupt request by setting the CC1IE bit in the

TIMx_DIER register.

When an input capture occurs:

• The TIMx_CCR1 register gets the value of the counter on the active transition.

• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.

• An interrupt is generated depending on the CC1IE bit.

IC interrupt requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

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14.3.6 PWM input mode (only for TIM9)

This mode is a particular case of input capture mode. The procedure is the same except:

• Two ICx signals are mapped on the same TIx input.

• These 2 ICx signals are active on edges with opposite polarity.

• One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, the user can measure the period (in TIMx_CCR1 register) and the duty cycle

(in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure

(depending on CK_INT frequency and prescaler value):

Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected).

2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge).

3. Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1 register (TI1 selected).

4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the

CC2P and CC2NP bits to ‘11’ (active on falling edge).

5. Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register

(TI1FP1 selected).

6. Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the

TIMx_SMCR register.

7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

Figure 149. PWM input mode timing

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TI1FP1 and TI2FP2 are connected to the slave mode controller.

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14.3.7 Forced output mode

In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (OCXREF/OCx) to its active level, the user just needs to write ‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.

The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the

TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below.

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This function is used to control an output waveform or indicating when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on match.

2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).

3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the

TIMx_DIER register).

The TIMx_CCRx registers can be programmed with or without preload registers using the

OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on OCxREF and OCx output.

The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode).

Procedure:

Select the counter clock (internal, external, prescaler).

2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.

3. Set the CCxIE bit if an interrupt request is to be generated.

4. Select the output mode. For example:

– Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx

– Write OCxPE = ‘0’ to disable preload register

– Write CCxP = ‘0’ to select active high polarity

– Write CCxE = ‘1’ to enable the output

5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

Figure 150 .

Figure 150. Output compare mode, toggle on OC1.

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Pulse Width Modulation mode allows the user to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. Enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register by setting the

ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, the user has to initialize all the registers by setting the

UG bit in the TIMx_EGR register.

The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.

It can be programmed as active high or active low. The OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CNT ≤ TIMx_CCRx.

The timer is able to generate PWM in edge-aligned mode only since the counter is upcounting.

PWM edge-aligned mode

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in

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TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at

‘1’. If the compare value is 0 then OCxRef is held at ‘0’.

Figure 151 shows some edge-

aligned PWM waveforms in an example where TIMx_ARR=8.

Figure 151. Edge-aligned PWM waveforms (ARR=8)

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A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be as follows:

CNT < CCRx ≤ ARR (in particular, 0 < CCRx)

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Figure 152. Example of one pulse mode.

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For example the user may want to generate a positive pulse on OC1 with a length of t

PULSE and after a delay of t

DELAY

as soon as a positive edge is detected on the TI2 input pin.

Use TI2FP2 as trigger 1:

Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.

2. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER register.

3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register.

4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register

(trigger mode).

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

• The t

DELAY is defined by the value written in the TIMx_CCR1 register.

• The t

PULSE

is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1).

TIMx_CCMR1 register. The user can optionally enable the preload registers by writing

OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case the user has to write the compare value in the TIMx_CCR1 register, the autoreload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example.

The user only wants one pulse (Single mode), so write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the

Repetitive Mode is selected.

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Particular case: OCx fast enable

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If the user wants to output a waveform with the minimum delay, set the OCxFE bit in the

TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

14.3.11 TIM9 external trigger synchronization

The TIM9 timer can be synchronized with an external trigger in several modes: Reset mode,

Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on TI1 input:

Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so there’s no need to configure it. The CC1S bits select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register.

Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and detect rising edges only).

2. Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select

TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.

3. Start the counter by writing CEN=’1’ in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.

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Figure 153. Control circuit in reset mode

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect low level only).

2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register.

Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.

3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=’0’, whatever is the trigger input level).

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input.

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Figure 154. Control circuit in gated mode

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Slave mode: Trigger mode

The counter can start in response to an event on a selected input.

In the following example, the upcounter starts in response to a rising edge on TI2 input:

Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture prescaler is not used for triggering, so there’s no need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register. Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only).

2. Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register.

Select TI2 as the input source by writing TS=’110’ in TIMx_SMCR register.

When a rising edge occurs on TI2, the counter starts counting on the internal clock and the

TIF flag is set.

The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input.

Figure 155. Control circuit in trigger mode

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Note:

The TIM timers are linked together internally for timer synchronization or chaining. Refer to

Section 13.3.15: Timer synchronization for details.

The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Section 23.16.2: Debug support for timers, watchdog and I2C .

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Refer to Section 2.2

for a list of abbreviations used in register descriptions.

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

14.4.1 TIM9 control register 1 (TIMx_CR1)

15 14

Address offset: 0x00

Reset value: 0x0000

13 12 11 10

Reserved

9 8

CKD[1:0] rw rw

ARPE rw

6 5

Reserved

4 3

OPM rw

URS rw

UDIS rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD : Clock division

This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),

00: t

DTS

= t

CK_INT

01: t

DTS

= 2 × t

CK_INT

10: t

DTS

= 4 × t

CK_INT

11: Reserved

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped on the update event

1: Counter stops counting on the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt if enabled:

– Counter overflow

– Setting the UG bit

1: Only counter overflow generates an update interrupt if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable update event (UEV) generation.

0: UEV enabled. An UEV is generated by one of the following events:

– Counter overflow

– Setting the UG bit

Buffered registers are then loaded with their preload values.

1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,

CCRx). The counter and the prescaler are reinitialized if the UG bit is set.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

CEN is cleared automatically in one-pulse mode, when an update event occurs.

CEN rw

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14.4.2 TIM9 slave mode control register (TIMx_SMCR)

Address offset: 0x08

Reset value: 0x0000

15 14 13 12 11

Reserved

10 9 8 7

MSM rw

6 rw

TS[2:0] rw

4 rw

Res.

2 rw

SMS[2:0] rw

0 rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 MSM: Master/Slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful in order to synchronize several timers on a single external event.

Bits 6:4 TS: Trigger selection

This bit field selects the trigger input to be used to synchronize the counter.

000: Internal Trigger 0 (ITR0)

001: Internal Trigger 1 (ITR1)

010: Internal Trigger 2 (ITR2)

011: Internal Trigger 3 (ITR3)

100: TI1 Edge Detector (TI1F_ED)

101: Filtered Timer Input 1 (TI1FP1)

110: Filtered Timer Input 2 (TI2FP2)

111: Reserved.

See Table 57 for more details on the meaning of ITRx for each timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to avoid wrong edge detections at the transition.

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Bit 3 Reserved, must be kept at reset value.

Bits 2:0 SMS: Slave mode selection

When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input control register and Control register descriptions.

000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock

001: Reserved

010: Reserved

011: Reserved

100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers

101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops are both controlled

110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled

111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter

Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input

(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the

Gated mode checks the level of the trigger signal.

Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Slave TIM

TIM9

Table 57. TIMx internal trigger connection

ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010)

TIM2_TRGO TIM3_TRGO TIM10_OC

ITR3 (TS = 011)

TIM11_OC

14.4.3 TIM9 Interrupt enable register (TIMx_DIER)

15 14

Address offset: 0x0C

Reset value: 0x0000

13 12 11 10 9 8 7

Reserved

TIE rw

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TIE : Trigger interrupt enable

0: Trigger interrupt disabled.

1: Trigger interrupt enabled.

Bit 5:3 Reserved, must be kept at reset value.

Res

3 2 1

CC2IE CC1IE rw rw

UIE rw

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Bit 2 CC2IE : Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled.

1: CC2 interrupt enabled.

Bit 1 CC1IE : Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled.

1: CC1 interrupt enabled.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

General-purpose timers (TIM9 to TIM11)

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15 14

Address offset: 0x10

Reset value: 0x0000

13 12 11

Reserved

10 9

CC2OF CC1OF rc_w0 rc_w0

8 7

Reserved

TIF rc_w0

5 4

Reserved

3 2 1

CC2IF CC1IF

UIF rc_w0 rc_w0 rc_w0

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 CC2OF : Capture/compare 2 overcapture flag refer to CC1OF description

Bit 9 CC1OF : Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 TIF : Trigger interrupt flag

0: No trigger event occurred.

1: Trigger interrupt pending.

Bits 5:3 Reserved, must be kept at reset value.

Bit 2 CC2IF : Capture/Compare 2 interrupt flag refer to CC1IF description

Bit 1 CC1IF : Capture/compare 1 interrupt flag

If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value. It is cleared by software.

0: No match.

1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.

When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow.

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the

TIMx_CCR1 register.

0: No input capture occurred.

1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity).

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Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow and if UDIS=’0’ in the TIMx_CR1 register.

– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and

UDIS=’0’ in the TIMx_CR1 register.

– When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.

15 14

Address offset: 0x14

Reset value: 0x0000

13 12 11 10

Reserved

9 8 7 6

TG w

5 4

Reserved

3 2 1

CC2G CC1G w w

UG w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG : Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled

Bits 5:3 Reserved, must be kept at reset value.

Bit 2 CC2G : Capture/compare 2 generation refer to CC1G description

Bit 1 CC1G : Capture/compare 1 generation

This bit is set by software to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled.

If channel CC1 is configured as input:

The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared.

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Res.

Address offset: 0x18

Reset value: 0x0000

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes. For a given bit, OCxx describes its function when the channel is configured in output mode, ICxx describes its function when the channel is configured in input mode. Take care that the same bit can have different meanings for the input stage and the output stage.

14 13

OC2M[2:0]

IC2F[3:0] rw rw

12 rw

11 10

OC2PE OC2FE

IC2PSC[1:0] rw rw

CC2S[1:0] rw

8 rw

Res.

6 5

OC1M[2:0]

IC1F[3:0] rw rw

4 rw

3 2

OC1PE OC1FE

IC1PSC[1:0] rw rw

CC1S[1:0] rw

0 rw

Output compare mode

Bits 14:12 OC2M[2:0] : Output compare 2 mode

Bit 11 OC2PE : Output compare 2 preload enable

Bit 10 OC2FE : Output compare 2 fast enable

Bits 9:8 CC2S[1:0] : Capture/Compare 2 selection

This bitfield defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register

Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bits 6:4 OC1M : Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and

OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.

000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

001: Set channel 1 to active level on match. The OC1REF signal is forced high when the

TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).

010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the

TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).

011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1

100: Force inactive level - OC1REF is forced low

101: Force active level - OC1REF is forced high

110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else it is inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as

TIMx_CNT>TIMx_CCR1, else it is active (OC1REF=’1’)

111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else it is active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else it is inactive.

Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.

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Bit 3 OC1PE : Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event

Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed.

Bit 2 OC1FE : Output compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles

1: An active edge on the trigger input acts like a compare match on the CC1 output. Then,

OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S : Capture/Compare 1 selection

This bitfield defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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Input capture mode

Bits 15:12 IC2F : Input capture 2 filter

Bits 11:10 IC2PSC[1:0] : Input capture 2 prescaler

Bits 9:8 CC2S : Capture/compare 2 selection

This bitfield defines the direction of the channel (input/output) as well as the used input.

00: CC2 channel is configured as output

01: CC2 channel is configured as input, IC2 is mapped on TI2

10: CC2 channel is configured as input, IC2 is mapped on TI1

11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bits 7:4 IC1F : Input capture 1 filter

This bitfield defines the frequency used to sample the TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

CK_INT

, N=2

, N=4

, N=8

/2, N=6 0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/2, N=8

/4, N=6

/4, N=8

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8 1100: f

SAMPLING

1101: f

SAMPLING

1110: f

SAMPLING

DTS

1111: f

SAMPLING

DTS

/32, N=5

/32, N=6

/32, N=8

Bits 3:2 IC1PSC : Input capture 1 prescaler

This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).

The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).

00: no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S : Capture/Compare 1 selection

This bitfield defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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15 14

Address offset: 0x20

Reset value: 0x0000

13 12 11 10

Reserved

9 8 7

CC2NP rw

Res.

5 4 3

CC2P CC2E CC1NP rw rw rw

Res.

1 0

CC1P CC1E rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 CC2NP : Capture/Compare 2 output Polarity refer to CC1NP description

Bits 6 Reserved, must be kept at reset value.

Bit 5 CC2P : Capture/Compare 2 output Polarity refer to CC1P description

Bit 4 CC2E : Capture/Compare 2 output enable refer to CC1E description

Bit 3 CC1NP : Capture/Compare 1 complementary output Polarity

CC1 channel configured as output: CC1NP must be kept cleared

CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define

TI1FP1/TI2FP1 polarity (refer to CC1P description).

Bit 2 Reserved, must be kept at reset value.

Bit 1 CC1P : Capture/Compare 1 output Polarity .

CC1 channel configured as output:

0: OC1 active high.

1: OC1 active low.

CC1 channel configured as input:

CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.

00: noninverted/rising edge

Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).

01: inverted/falling edge

Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).

10: reserved, do not use this configuration.

Note: 11: noninverted/both edges

Bit 0 CC1E : Capture/Compare 1 output enable .

CC1 channel configured as output:

0: Off - OC1 is not active.

1: On - OC1 signal is output on the corresponding output pin.

CC1 channel configured as input:

This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled.

1: Capture enabled.

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Note:

CCxE bit

Table 58. Output control bit for standard OCx channels

OCx output state

Output disabled (OCx=’0’, OCx_EN=’0’)

OCx=OCxREF + Polarity, OCx_EN=’1’

RM0368

The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.

15 rw

Address offset: 0x24

Reset value: 0x0000

13 12 11 10 9 rw rw rw rw rw rw

Bits 15:0 CNT[15:0] : Counter value

8 7

CNT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

15 rw

Address offset: 0x28

Reset value: 0x0000

13 12 11 10 rw

9 8 7

PSC[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency CK_CNT is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

15 rw

Address offset: 0x2C

Reset value: 0xFFFF

13 12 11 10 9 8 7

ARR[15:0] rw rw

6 5 4 3 2 1 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to the Section 14.3.1: Time-base unit for more details about ARR update and

behavior.

The counter is blocked while the auto-reload value is null.

0 rw

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15 rw/ro

Address offset: 0x34

Reset value: 0x0000

13 12 11 10 9 8 7

CCR1[15:0] rw/ro rw/ro

6 5 4 3 2 1 0 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

Bits 15:0 CCR1[15:0] : Capture/Compare 1 value

If channel CC1 is configured as output :

CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register

(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output.

If channel CC1is configured as input :

CCR1 is the counter value transferred by the last input capture 1 event (IC1). The

TIMx_CCR1 register is read-only and cannot be programmed.

15 rw/ro

Address offset: 0x38

Reset value: 0x0000

13 12 11 10 9 8 7

CCR2[15:0] rw/ro rw/ro

6 5 4 3 2 1 0 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

Bits 15:0 CCR2[15:0] : Capture/Compare 2 value

If channel CC2 is configured as output:

CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register

(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register when an update event occurs.

The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signalled on the OC2 output.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 2 event (IC2). The

TIMx_CCR2 register is read-only and cannot be programmed.

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14.4.13 TIM9 register map

TIM9 registers are mapped as 16-bit addressable registers as described below. The reserved memory areas are highlighted in gray in the table.

Table 59. TIM9 register map and reset values

Offset Register

0x00

0x08

0x0C

TIMx_CR1

Reset value

TIMx_SMCR

Reset value

TIMx_DIER

Reset value

0x10

0x14

0x18

TIMx_SR

Reset value

TIMx_EGR

Reset value

TIMx_CCMR1

Output Compare mode

Reset value

TIMx_CCMR1

Input Capture mode

Reset value

0x1C

0x20

0x24

0x28

0x2C

TIMx_CCER

Reset value

TIMx_CNT

Reset value

TIMx_PSC

Reset value

TIMx_ARR

Reset value

0x30

Reserved

CKD

[1:0]

0 0 0

Reserved

0 0 0 0

TS[2:0]

0 0 0 0

SMS[2:0]

0 0 0

0 0

Reserved

0 0 0

Reserved

0 0 0

Reserved

OC2M

[2:0]

CC2S

[1:0]

OC1M

[2:0]

0 0 0

CC1

[1:0]

0 0 0 0 0 0 0

IC2F[3:0]

IC2

PSC

[1:0]

CC2S

[1:0]

0 0

IC1F[3:0]

0 0 0

IC1

PSC

[1:0]

0 0

CC1

[1:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CNT[15:0]

0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSC[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ARR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x34

TIMx_CCR1

Reset value

Reserved

CCR1[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 59. TIM9 register map and reset values (continued)

Offset

0x38

Register

TIMx_CCR2

Reset value

0x3C to

0x4C

Reserved

CCR2[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 3.3: Memory map for the register boundary addresses.

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The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

15 14

Address offset: 0x00

Reset value: 0x0000

13 12 11 10

Reserved

9 8

CKD[1:0] rw rw

ARPE rw

6 5

Reserved

4 3

OPM rw

URS rw

UDIS rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD : Clock division

This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),

00: t

DTS

= t

CK_INT

01: t

DTS

= 2 × t

CK_INT

10: t

DTS

= 4 × t

CK_INT

11: Reserved

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped on the update event

1: Counter stops counting on the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the update interrupt (UEV) sources.

0: Any of the following events generate an UEV if enabled:

– Counter overflow

– Setting the UG bit

1: Only counter overflow generates an UEV if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation.

0: UEV enabled. An UEV is generated by one of the following events:

– Counter overflow

– Setting the UG bit.

Buffered registers are then loaded with their preload values.

1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,

CCRx). The counter and the prescaler are reinitialized if the UG bit is set.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

CEN rw

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14.5.2 TIM10/11 Interrupt enable register (TIMx_DIER)

15 14

Address offset: 0x0C

Reset value: 0x0000

13 12 11 10 9 8 7 6 5 4

Reserved

Bits 15:2 Reserved, must be kept at reset value.

Bit 1 CC1IE : Capture/Compare 1 interrupt enable

0: CC1 interrupt disabled

1: CC1 interrupt enabled

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled

1: Update interrupt enabled

3 2 1

CC1IE rw

UIE rw

14.5.3 TIM status register (TIMx_SR)

15 14

Address offset: 0x10

Reset value: 0x0000

13 12 11 10 8

Reserved

CC1OF rc_w0

7 6 5

Reserved

4 3 2 1 0

CC1IF UIF rc_w0 rc_w0

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 CC1OF : Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bits 8:2 Reserved, must be kept at reset value.

Bit 1 CC1IF : Capture/compare 1 interrupt flag

If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value. It is cleared by software.

0: No match.

1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.

When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow.

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the

TIMx_CCR1 register.

0: No input capture occurred.

1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity).

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Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow and if UDIS=’0’ in the TIMx_CR1 register.

– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if

URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.

15 14

Address offset: 0x14

Reset value: 0x0000

13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1

CC1G w

UG w

Bits 15:2 Reserved, must be kept at reset value.

Bit 1 CC1G : Capture/compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If channel CC1 is configured as output:

CC1IF flag is set, Corresponding interrupt or is sent if enabled.

If channel CC1 is configured as input:

The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.

15 14

Address offset: 0x18

Reset value: 0x0000

OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So take care that the same bit can have a different meaning for the input stage and for the output stage.

13 12 11

Reserved

10 9 8 7 rw

6 5

OC1M[2:0]

IC1F[3:0] rw rw

4 rw

3 2

OC1PE OC1FE

IC1PSC[1:0] rw rw

CC1S[1:0] rw

0 rw

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Output compare mode

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 OC1M : Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit.

000: Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.

001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter

TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.

100: Force inactive level - OC1REF is forced low.

101: Force active level - OC1REF is forced high.

110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.

111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.

Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode.

Bit 3 OC1PE : Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Bit 2 OC1FE : Output compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is

ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is

5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output.

01: CC1 channel is configured as input, IC1 is mapped on TI1.

10:

11:

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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General-purpose timers (TIM9 to TIM11) RM0368

Input capture mode

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:4 IC1F : Input capture 1 filter

0000: No filter, sampling is done at f

DTS

0001: f

SAMPLING

0010: f

SAMPLING

0011: f

SAMPLING

CK_INT

, N=2

, N=4

, N=8

/2, N=6 0100: f

SAMPLING

0101: f

SAMPLING

0110: f

SAMPLING

DTS

0111: f

SAMPLING

DTS

/2, N=8

/4, N=6

/4, N=8

1000: f

SAMPLING

1001: f

SAMPLING

1010: f

SAMPLING

1011: f

SAMPLING

DTS

/8, N=6

/8, N=8

/16, N=5

/16, N=6

/16, N=8 1100: f

SAMPLING

1101: f

SAMPLING

1110: f

SAMPLING

DTS

1111: f

SAMPLING

DTS

/32, N=5

/32, N=6

/32, N=8

Bits 3:2 IC1PSC : Input capture 1 prescaler

This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).

The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).

00: no prescaler, capture is done each time an edge is detected on the capture input

01: capture is done once every 2 events

10: capture is done once every 4 events

11: capture is done once every 8 events

Bits 1:0 CC1S : Capture/Compare 1 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: Reserved

11: Reserved

Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

15 14

Address offset: 0x20

Reset value: 0x0000

13 12 11 10 9

Reserved

8 7 6 5 4 3

CC1NP rw

Res.

1 0

CC1P CC1E rw rw

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 CC1NP : Capture/Compare 1 complementary output Polarity.

CC1 channel configured as output: CC1NP must be kept cleared.

CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define

TI1FP1 polarity (refer to CC1P description).

Bit 2 Reserved, must be kept at reset value.

Bit 1 CC1P : Capture/Compare 1 output Polarity.

CC1 channel configured as output:

0: OC1 active high

1: OC1 active low

CC1 channel configured as input:

The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations.

00: noninverted/rising edge

Circuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted.

01: inverted/falling edge

Circuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted.

10: reserved, do not use this configuration.

11: noninverted/both edges

Circuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not inverted.

Bit 0 CC1E : Capture/Compare 1 output enable.

CC1 channel configured as output:

0: Off - OC1 is not active

1: On - OC1 signal is output on the corresponding output pin

CC1 channel configured as input:

This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled

1: Capture enabled

Note:

CCxE bit

Table 60. Output control bit for standard OCx channels

OCx output state

Output Disabled (OCx=’0’, OCx_EN=’0’)

OCx=OCxREF + Polarity, OCx_EN=’1’

The state of the external I/O pins connected to the standard OCx channels depends on the

OCx channel state and the GPIO registers.

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General-purpose timers (TIM9 to TIM11) RM0368

15 rw

Address offset: 0x24

Reset value: 0x0000

13 12 11 10 9 rw rw rw rw rw rw

Bits 15:0 CNT[15:0] : Counter value

8 7

CNT[15:0] rw rw

6 rw

5 rw

4 rw

3 rw

2 rw

1 rw

0 rw

15 rw

Address offset: 0x28

Reset value: 0x0000

13 12 11 10 9 8 7

PSC[15:0] rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency CK_CNT is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

15 rw

Address offset: 0x2C

Reset value: 0xFFFF

13 12 11 10 9 8 7

ARR[15:0] rw rw

6 5 4 3 2 1 rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.

Refer to

Section 14.3.1: Time-base unit for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

0 rw

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RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

14.5.10 TIM10/11 capture/compare register 1 (TIMx_CCR1)

15 14

Address offset: 0x34

Reset value: 0x0000

13 12 11 10 9 6 5 4 rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro rw/ro

8 7

CCR1[15:0] rw/ro rw/ro rw/ro rw/ro rw/ro

3 rw/ro

2 1 0 rw/ro rw/ro rw/ro

Bits 15:0 CCR1[15:0] : Capture/Compare 1 value

If channel CC1 is configured as output :

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).

It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit

OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter

TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input :

CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed.

15 14

Address offset: 0x50

Reset value: 0x0x0000

13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

TI1_RMP[1:0] rw

Bits 15:2 Reserved, must be kept at reset value.

Bits 1:0 TI1_RMP[1:0] : TIM11 Input 1 remapping capability

Set and cleared by software.

00,01,11: TIM11 Channel1 is connected to the GPIO (refer to the Alternate function mapping table in the datasheets).

10: HSE_RTC clock (HSE divided by programmable prescaler) is connected to the

TIM11_CH1 input for measurement purposes.

RM0368 Rev 5

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General-purpose timers (TIM9 to TIM11) RM0368

14.5.12 TIM10/11 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below.

Table 61. TIM10/11 register map and reset values

Offset Register

0x00

0x08

0x0C

0x10

0x14

0x18

TIMx_CR1

Reset value

TIMx_SMCR

Reset value

TIMx_DIER

Reset value

TIMx_SR

Reset value

TIMx_EGR

Reset value

TIMx_CCMR1

Output compare mode

Reset value

TIMx_CCMR1

Input capture mode

Reset value

0x1C

0x20

0x24

0x28

0x2C

TIMx_CCER

Reset value

TIMx_CNT

Reset value

TIMx_PSC

Reset value

TIMx_ARR

Reset value

0x30

0x34

TIMx_CCR1

Reset value

0x38 to

0x4C

Reserved

CKD

[1:0]

0 0 0

Reserve d

0 0 0 0

0 0

Reserved Reserved

Reserved

0 0 0

Reserved

OC1M

[2:0]

0 0

CC1S

[1:0]

0 0 0 0 0 0 0

IC1F[3:0]

IC1

PSC

[1:0]

CC1S

[1:0]

0 0 0 0 0 0 0 0

Reserved

0 0 0

CNT[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSC[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ARR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

CCR1[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

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RM0368 Rev 5

RM0368 General-purpose timers (TIM9 to TIM11)

Offset Register

Table 61. TIM10/11 register map and reset values (continued)

0x50

TIMx_OR

Reset value

Reserved

Refer to Section 3.3: Memory map for the register boundary addresses.

0 0

RM0368 Rev 5

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Independent watchdog (IWDG)

15 Independent watchdog (IWDG)

RM0368

The devices have two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.

The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. The window watchdog (WWDG) clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior.

The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. The WWDG is best suited to applications which require the watchdog to react within an accurate timing window. For further information on the window watchdog, refer to

Section 16 on page 427

• Free-running downcounter

• clocked from an independent RC oscillator (can operate in Standby and Stop modes)

• Reset (if watchdog activated) when the downcounter value of 0x000 is reached

422/847

Figure 156 shows the functional blocks of the independent watchdog module.

When the independent watchdog is started by writing the value 0xCCCC in the Key register

(IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).

Whenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.

If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and will generate a reset unless the Key register is written by the software before the counter reaches end of count.

Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, first write the code 0x5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0xAAAA).

RM0368 Rev 5

RM0368 Independent watchdog (IWDG)

A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going.

Note:

When the microcontroller enters debug mode (Cortex

-M4 with FPU core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. For more details, refer to

Section 23.16.2: Debug support for timers, watchdog and I2C .

Figure 156. Independent watchdog block diagram

#/2%

0RESCALERREGISTER

)7$'?02

3TATUSREGISTER

)7$'?32

2ELOADREGISTER

)7$'?2,2

+EYREGISTER

)7$'?+2

BITRELOADVALUE

,3)

BIT

K(Z

PRESCALER

BITDOWNCOUNTER )7$'RESET

6$$VOLTAGEDOMAIN

-36

The watchdog function is implemented in the V

Standby modes.

voltage domain, still functional in Stop and

Table 62. Min/max IWDG timeout period (in ms) at 32 kHz (LSI) (1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF

/16

/32

/64

/128

/256

0.125

0.25

0.5

512

1024

2048

4096

8192

16384

32768

1. These timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Refer to the LSI oscillator characteristics table in the device datasheet for maximum and minimum values.

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426

Independent watchdog (IWDG) RM0368

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).

15.4.1 Key register (IWDG_KR)

Address offset: 0x00

Reset value: 0x0000 0000 (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

KEY[15:0] w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 KEY[15:0]: Key value (write only, read 0000h)

These bits must be written by software at regular intervals with the key value AAAAh, otherwise the watchdog generates a reset when the counter reaches 0.

Writing the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers

(see Section 15.3.2

)

Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected)

15.4.2 Prescaler register (IWDG_PR)

Address offset: 0x04

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

PR[2:0] rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 PR[2:0]: Prescaler divider

These bits are write access protected see Section 15.3.2

. They are written by software to

select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider.

000: divider /4

001: divider /8

010: divider /16

011: divider /32

100: divider /64

101: divider /128

110: divider /256

111: divider /256

Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset.

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RM0368 Rev 5

RM0368 Independent watchdog (IWDG)

15.4.3 Reload register (IWDG_RLR)

Address offset: 0x08

Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RL[11:0]

Reserved rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits11:0 RL[11:0]: Watchdog counter reload value

These bits are write access protected see

Section 15.3.2

. They are written by software to define the value to be loaded in the watchdog counter each time the value AAAAh is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout

period is a function of this value and the clock prescaler. Refer to Table 62.

The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value.

Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset.

Address offset: 0x0C

Reset value: 0x0000 0000 (not reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

Reserved

1 0

RVU PVU r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 RVU: Watchdog counter reload value update

This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V

(takes up to 5 RC 40 kHz cycles).

voltage domain

Reload value can be updated only when RVU bit is reset.

Bit 0 PVU: Watchdog prescaler value update

This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the V

DD domain (takes up to 5 RC 40 kHz cycles).

voltage

Prescaler value can be updated only when PVU bit is reset.

Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete)

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Independent watchdog (IWDG) RM0368

15.4.5 IWDG register map

The following table gives the IWDG register map and reset values.

Table 63. IWDG register map and reset values

Offset Register

0x00

0x04

0x08

0x0C

IWDG_KR

Reset value

IWDG_PR

Reset value

IWDG_RLR

Reset value

IWDG_SR

Reset value

Reserved

KEY[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PR[2:0]

0 0 0

RL[11:0]

1 1 1 1 1 1 1 1 1 1 1 1

Reserved

0 0

Refer to Section 3.3: Memory map for the register boundary addresses.

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RM0368 Rev 5

RM0368

16 Window watchdog (WWDG)

Window watchdog (WWDG)

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an

MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window.

16.2 WWDG main features

• Programmable free-running downcounter

• Conditional reset

– Reset (if watchdog activated) when the downcounter value becomes less than

0x40

– Reset (if watchdog activated) if the downcounter is reloaded outside the window

(see Figure 158 )

• Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter is equal to 0x40.

16.3 WWDG functional description

If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the

7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated.

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433

Window watchdog (WWDG)

Note:

RM0368

5(6(7

Figure 157. Watchdog block diagram

FRPSDUDWRU

ZKHQ

7!:

:DWFKGRJFRQILJXUDWLRQUHJLVWHU::'*B&)5

: : : : : : :

:ULWH::'*B&5

3&/.

IURP5&&FORFNFRQWUROOHU

:'*$ 7

:DWFKGRJFRQWUROUHJLVWHU::'*B&5

7 7 7 7

ELWGRZQFRXQWHU&17

7 7

:'*SUHVFDOHU

:'*7%

06Y9

The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0.

Enabling the watchdog

The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the

WWDG_CR register, then it cannot be disabled again except by a reset.

Controlling the downcounter

This downcounter is free-running, counting down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.

The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see

Figure 158 ). The Configuration register (WWDG_CFR) contains the high limit of the window:

To prevent a reset, the downcounter must be reloaded when its value is lower than the

window register value and greater than 0x3F. Figure 158

describes the window watchdog process.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).

Advanced watchdog interrupt feature

The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value

0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.

428/847

RM0368 Rev 5

RM0368

Note:

Window watchdog (WWDG)

In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.

The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.

When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated.

16.4 How to program the watchdog timeout

Warning: When writing to the WWDG_CR register, always write 1 in the

T6 bit to avoid generating an immediate reset.

Figure 158. Window watchdog timing diagram

4;=#.4DOWNCOUNTER

7;=

2EFRESHNOTALLOWED 2EFRESHALLOWED

4IME

4BIT

2%3%4

The formula to calculate the WWDG timeout value is given by:

× 2

WDGTB[1:0]

× ( T[5:0] 1 ) where: t

WWDG

: WWDG timeout t

PCLK1

: APB1 clock period measured in ms

4096: value corresponding to internal divider

( ms )

AIC

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Window watchdog (WWDG) RM0368

As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63:

× 4096 × 2

× ( ) = 21.85ms

Refer to Table 64

for the minimum and maximum values of the t

WWDG

Table 64. Minimum and maximum timeout values at 30 MHz (f

PCLK1

)

Prescaler WDGTB

Min timeout (µs)

T[5:0] = 0x00

Max timeout (ms)

T[5:0] = 0x3F

136.53

273.07

546.13

1092.27

8.74

17.48

34.95

69.91

When the microcontroller enters debug mode (Cortex ® -M4 with FPU core halted), the

WWDG counter either continues to work normally or stops, depending on

DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to

Section 23.16.2: Debug support for timers, watchdog and I2C .

430/847

RM0368 Rev 5

RM0368 Window watchdog (WWDG)

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).

16.6.1 Control register (WWDG_CR)

Address offset: 0x00

Reset value: 0x0000 007F

30 29

14 13

28 27

12 11

Reserved

24 23

Reserved

WDGA rs

T[6:0] rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WDGA: Activation bit

This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)

These bits contain the value of the watchdog counter. It is decremented every (4096 x

2 WDGTB[1:0] ) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6 becomes cleared).

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433

Window watchdog (WWDG) RM0368

Address offset: 0x04

Reset value: 0x0000 007F

30 29

13 12

Reserved

EWI rs

24 23

Reserved

8 7

WDGTB[1:0] rw

W[6:0] rw

Bit 31:10 Reserved, must be kept at reset value.

Bit 9 EWI: Early wakeup interrupt

When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.

Bits 8:7 WDGTB[1:0]: Timer base

The time base of the prescaler can be modified as follows:

00: CK Counter Clock (PCLK1 div 4096) div 1

01: CK Counter Clock (PCLK1 div 4096) div 2

10: CK Counter Clock (PCLK1 div 4096) div 4

11: CK Counter Clock (PCLK1 div 4096) div 8

Bits 6:0 W[6:0]: 7-bit window value

These bits contain the window value to be compared to the downcounter.

Address offset: 0x08

Reset value: 0x0000 0000

30 29

14 13

24 23

Reserved

EWIF rc_w0

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EWIF: Early wakeup interrupt flag

This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not enabled.

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RM0368 Rev 5

RM0368 Window watchdog (WWDG)

The following table gives the WWDG register map and reset values.

Table 65. WWDG register map and reset values

Offset Register

0x00

WWDG_CR

Reset value

0x04

WWDG_CFR

0x08

Reset value

WWDG_SR

Reset value

Reserved

T[6:0]

0 1 1 1 1 1 1 1

W[6:0]

0 0 0 1 1 1 1 1 1 1

Refer to Section 3.3: Memory map for the register boundary addresses.

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17.1 Introduction

Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format

(BCD). The sub-seconds value is also available in binary format.

Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed.

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy.

After backup domain reset, all RTC registers are protected against possible parasitic write accesses.

As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).

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17.2 RTC main features

The RTC unit main features are the following (see

Figure 159: RTC block diagram ):

• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year.

• Daylight saving compensation programmable by software.

• Two programmable alarms with interrupt function. The alarms can be triggered by any combination of the calendar fields.

• Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Accurate synchronization with an external clock using the subsecond shift feature.

• Maskable interrupts/events:

– Alarm A

– Alarm B

– Wakeup interrupt

– Timestamp

– Tamper detection

• Digital calibration circuit (periodic counter correction)

– 5 ppm accuracy

– 0.95 ppm accuracy, obtained in a calibration window of several seconds

• Timestamp function for event saving (1 event)

• Tamper detection:

– Tamper event with configurable filter and internal pull-up.

• 20 backup registers (80 bytes). The backup registers are reset when a tamper detection event occurs.

• Alternate function output (RTC_OUT) which selects one of the following two outputs:

– RTC_CALIB: 512 Hz or 1 Hz clock output (with an LSE frequency of 32.768 kHz).

This output is enabled by setting the COE bit in the RTC_CR register. It is routed to the device RTC_AF1 function.

– RTC_ALARM (Alarm A, Alarm B or wakeup).

This output is selected by configuring the OSEL[1:0] bits in the RTC_CR register.

It is routed to the device RTC_AF1 function.

• RTC additional function inputs:

– RTC_TS: timestamp event detection. It is routed to the device RTC_AF1 function.

– RTC_TAMP1: TAMPER1 event detection. It is routed to the device RTC_AF1 function.

– RTC_REFIN: reference clock input (usually the mains, 50 or 60 Hz).

Refer to Section 8.3.15: Selection of RTC functions and the STM32F401xx datasheet pin

definition table.

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Figure 159. RTC block diagram

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1. The RTC_AF1 additional function is connected to PC13.

17.3 RTC functional description

17.3.1 Clock and prescalers

Note:

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to

Section 6: Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E

A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see

Figure 159: RTC block diagram ):

• A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the

RTC_PRER register.

• A 15-bit synchronous prescaler configured through the PREDIV_S bits of the

RTC_PRER register.

When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption.

The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz.

The minimum division factor is 1 and the maximum division factor is 2 22 .

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This corresponds to a maximum input frequency of around 4 MHz. f ck_apre

is given by the following formula: f

CK_APRE

= f

RTCCLK

The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S. f ck_spre

is given by the following formula: f

CK_SPRE

( f

RTCCLK

) × ( PREDIV_A 1 )

The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous

prescaler (see Section 17.3.4: Periodic auto-wakeup

for details).

17.3.2 Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK1 (APB1 clock). They can also be accessed directly in order to avoid waiting for the synchronization duration.

• RTC_SSR for the subseconds

• RTC_TR for the time

• RTC_DR for the date

Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see

Section 17.6.4

). The copy is not performed

in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods.

When the application reads the calendar registers, it accesses the content of the shadow registers. t is possible to make a direct access to the calendar registers by setting the

BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers.

When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock (f

APB

RTCCLK

) must be at least 7 times the frequency of the RTC clock

The shadow registers are reset by system reset.

The RTC unit provides two programmable alarms, Alarm A and Alarm B.

The programmable alarm functions are enabled through the ALRAIE and ALRBIE bits in the

RTC_CR register. The ALRAF and ALRBF flags are set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers

RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR, respectively.

Each calendar field can be independently selected through the MSKx bits of the

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RTC_ALRMAR and RTC_ALRMBR registers, and through the MASKSSx bits of the

RTC_ALRMASSR and RTC_ALRMBSSR registers. The alarm interrupts are enabled through the ALRAIE and ALRBIE bits in the RTC_CR register.

Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the

RTC_ALARM output. RTC_ALARM polarity can be configured through bit POL in the

RTC_CR register.

Caution: If the seconds field is selected (MSK0 bit reset in RTC_ALRMAR or RTC_ALRMBR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.

The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter.

The wakeup timer range can be extended to 17 bits.

The wakeup function is enabled through the WUTE bit in the RTC_CR register.

The wakeup timer clock input can be:

• RTC clock (RTCCLK) divided by 2, 4, 8, or 16.

When RTCCLK is LSE(32.768kHz), this allows configuring the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61µs.

• ck_spre (usually 1 Hz internal clock)

When ck_spre frequency is 1Hz, this allows achieving a wakeup time from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts:

– from 1s to 18 hours when WUCKSEL [2:1] = 10

– and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 2 16 is added to the 16-bit counter current value.When the initialization sequence is

complete (see Programming the wakeup timer on page 440 ), the timer starts

counting down.When the wakeup function is enabled, the down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).

The WUTF flag must then be cleared by software.

When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low-power modes.

The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARMpolarity can be configured through the POL bit in the RTC_CR register.

System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on the wakeup timer.

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17.3.5 RTC initialization and configuration

Note:

RTC register access

The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when

BYPSHAD=0.

RTC register write protection

After system reset, the RTC registers are protected against parasitic write access with the

DBP bit of the PWR power control register (PWR_CR). The DBP bit must be set to enable

RTC registers write access.

After backup domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR.

The following steps are required to unlock the write protection on all the RTC registers except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR.

Write ‘0xCA’ into the RTC_WPR register.

2. Write ‘0x53’ into the RTC_WPR register.

Writing a wrong key reactivates the write protection.

The protection mechanism is not affected by system reset.

Calendar initialization and configuration

To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required:

Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated.

2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when

INITF is set to 1. It takes from 1 to 2 RTCCLK clock cycles (due to clock synchronization).

3. To generate a 1 Hz clock for the calendar counter, program first the synchronous prescaler factor in RTC_PRER register, and then program the asynchronous prescaler factor. Even if only one of the two fields needs to be changed, 2 separate write accesses must be performed to the RTC_PRER register.

4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.

5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.

When the initialization sequence is complete, the calendar starts counting.

After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its backup domain reset default value (0x00).

To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register.

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Note:

RM0368

Daylight saving time

The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register.

Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure.

In addition, the software can use the BKP bit to memorize this operation.

Programming the alarm

A similar procedure must be followed to program or update the programmable alarm (Alarm

A or Alarm B):

Clear ALRAE or ALRBIE in RTC_CR to disable Alarm A or Alarm B.

2. Poll ALRAWF or ALRBWF in RTC_ISR until it is set to make sure the access to alarm registers is allowed. This takes 1 to 2 RTCCLK clock cycles (due to clock synchronization).

3. Program the Alarm A or Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR or

RTC_ALRMBSSR/RTC_ALRMBR).

4. Set ALRAE or ALRBIE in the RTC_CR register to enable Alarm A or Alarm B again.

Each change of the RTC_CR register is taken into account after 1 to 2 RTCCLK clock cycles due to clock synchronization.

Programming the wakeup timer

The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR):

Clear WUTE in RTC_CR to disable the wakeup timer.

2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes 1 to 2 RTCCLK clock cycles

(due to clock synchronization).

3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection

(WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the timer again.

The wakeup timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK clocks cycles after WUTE is cleared, due to clock synchronization.

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To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (f

PCLK1

) must be equal to or greater than seven times the f

RTCCLK

RTC clock frequency. This ensures a secure behavior of the synchronization mechanism.

If the APB1 clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB1 clock frequency must never be lower than the RTC clock frequency.

The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the

RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two

RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or

RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is

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Note:

Real-time clock (RTC) read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers.

After waking up from low-power mode (Stop or Standby), RSF must be cleared by software.

The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and

RTC_DR registers.

The RSF bit must be cleared after wakeup and not before entering low-power mode.

After a system reset, the software must wait until RSF is set before reading the RTC_SSR,

RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values.

After an initialization (refer to

Calendar initialization and configuration on page 439 ): the

software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.

After synchronization (refer to

Section 17.3.8: RTC synchronization

): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.

When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers)

Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting from low-power modes (STOP or Standby), since the shadow registers are not updated during these modes.

When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register.

While BYPSHAD=1, instructions which read the calendar registers require one extra APB cycle to complete.

The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the

RTC status register (RTC_ISR) are reset to their default values by all available system reset sources.

On the contrary, the following registers are resetted to their default values by a backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function configuration register (RTC_TAFCR), the RTC backup registers

(RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers

(RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR).

In addition, when the RTC is clocked by the LSE, it goes on running under system reset if the reset source is different from a backup domain reset one. Refer to section RTC clock of

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When a backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values.

The RTC can be synchronized to a remote clock with a high degree of precision. After reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The

RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR.

RTC_SSR contains the value of the synchronous prescaler’s counter. This allows one to calculate the exact time being maintained by the RTC down to a resolution of

1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 μ s with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.

However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler’s output at 1 Hz. In this way, the frequency of the asynchronous prescaler’s output increases, which may increase the RTC dynamic consumption.

The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the

SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock.

If at the same time the ADD1S bit is set, this results in adding one second and at the same time subtracting a fraction of second, so this will advance the clock.

Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that no overflow will occur.

As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed.

Caution: This synchronization feature is not compatible with the reference clock detection feature: firmware must not write to RTC_SHIFTR when REFCKON=1.

17.3.9 RTC reference clock detection

The RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually the mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz).

Each 1 Hz clock edge is compared to the nearest reference clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock.

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The RTC detects if the reference clock source is present by using the 256 Hz clock

(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time window around each of the calendar updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge. A smaller window of 3 ck_apre periods is used for subsequent calendar updates.

Each time the reference clock is detected in the window, the synchronous prescaler which outputs the ck_spre clock is forced to reload. This has no effect when the reference clock and the 1 Hz clock are aligned because the prescaler is being reloaded at the same moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little for them to be aligned with the reference clock.

If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large 7 ck_apre period detection window centered on the ck_spre edge.

When the reference clock detection is enabled, PREDIV_A and PREDIV_S must be set to their default values:

• PREDIV_A = 0x007F

• PREDIV_S = 0x00FF

The reference clock detection is not available in Standby mode.

Note:

Caution: The reference clock detection feature cannot be used in conjunction with the coarse digital calibration: RTC_CALIBR must be kept at 0x0000 0000 when REFCKON=1.

17.3.10 RTC coarse digital calibration

Two digital calibration methods are available: coarse and smooth calibration. To perform

coarse calibration refer to Section 17.6.7: RTC calibration register (RTC_CALIBR) .

The two calibration methods are not intended to be used together, the application must select one of the two methods. Coarse calibration is provided for compatibly reasons. To

perform smooth calibration refer to Section 17.3.11: RTC smooth digital calibration

and the

Section 17.6.16: RTC calibration register (RTC_CALR)

The coarse digital calibration can be used to compensate crystal inaccuracy by adding

(positive calibration) or masking (negative calibration) clock cycles at the output of the asynchronous prescaler (ck_apre).

Positive and negative calibration are selected by setting the DCS bit in RTC_CALIBR register to ‘0’ and ‘1’, respectively.

When positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute

(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated sooner, thereby adjusting the effective RTC frequency to be a bit higher.

When negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute

(around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated later, thereby adjusting the effective RTC frequency to be a bit lower.

DC is configured through bits DC[4:0] of RTC_CALIBR register. This number ranges from 0 to 31 corresponding to a time interval (2xDC) ranging from 0 to 62.

The coarse digital calibration can be configured only in initialization mode, and starts when the INIT bit is cleared. The full calibration cycle lasts 64 minutes. The first 2xDC minutes of the 64 -minute cycle are modified as just described.

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Negative calibration can be performed with a resolution of about 2 ppm while positive calibration can be performed with a resolution of about 4 ppm. The maximum calibration ranges from -63 ppm to 126 ppm.

The calibration can be performed either on the LSE or on the HSE clock.

Caution: Digital calibration may not work correctly if PREDIV_A < 6.

Case of RTCCLK=32.768 kHz and PREDIV_A+1=128

The following description assumes that ck_apre frequency is 256 Hz obtained with an LSE clock nominal frequency of 32.768 kHz, and PREDIV_A set to 127 (default value).

The ck_spre clock frequency is only modified during the first 2xDC minutes of the 64-minute cycle. For example, when DC equals 1, only the first 2 minutes are modified. This means that the first 2xDC minutes of each 64-minute cycle have, once per minute, one second either shortened by 256 or lengthened by 128 RTCCLK cycles, given that each ck_apre cycle represents 128 RTCCLK cycles (with PREDIV_A+1=128).

Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125829120 RTCCLK cycles (64min x 60 s/min x 32768 cycles/s). This is equivalent to +4.069 ppm or -2.035 ppm per calibration step. As a result, the calibration resolution is +10.5 or -5.27 seconds per month, and the total calibration ranges from +5.45 to -2.72 minutes per month.

In order to measure the clock deviation, a 512 Hz clock is output for calibration.Refer to

Section 17.3.14: Calibration clock output

17.3.11 RTC smooth digital calibration

Note:

RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC is well calibrated even when observed over short durations of time.

The smooth digital calibration is performed during a cycle of about 2

RTCCLK pulses, or

32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit counter, cal_cnt[19:0], clocked by RTCCLK.

The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle:

• Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32second cycle.

• Setting CALM[1] to 1 causes two additional cycles to be masked

• Setting CALM[2] to 1 causes four additional cycles to be masked

• and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.

CALM[8:0] (RTC_CALRx) specifies the number of RTCCLK pulses to be masked during the

32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000 ; CALM[1]=1 causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000) ; CALM[2]=1 causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000) ; and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800) .

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While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP to ‘1’ effectively inserts an extra RTCCLK pulse every 2 11 RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle.

Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm to +488.5 ppm with a resolution of about 0.954 ppm.

The formula to calculate the effective calibrated frequency (F CAL ) given the input frequency

(F RTCCLK ) is as follows:

CAL

= F

RTCCLK

x [1 + (CALP x 512 - CALM) / (2

+ CALM - CALP x 512)]

Calibration when PREDIV_A<3

The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in

RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0.

To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value

(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to

244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.

With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less).

If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is as follows:

CAL

= F

RTCCLK

x [1 + (256 - CALM) / (2

+ CALM - 256)]

In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly 32768.00 Hz.

Verifying the RTC calibration

RTC precision is performed by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision.Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.

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However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration.

• By default, the calibration cycle period is 32 seconds.

Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution).

• CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration cycle period.

In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.

• CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration cycle period.

In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.

Re-calibration on-the-fly

The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the follow process:

Poll the RTC_ISR/RECALPF (re-calibration pending flag).

2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1

3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take effect.

Timestamp is enabled by setting the TSE bit of RTC_CR register to 1.

The calendar is saved in the timestamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a timestamp event is detected on the pin to which the TIMESTAMP additional function is mapped. When a timestamp event occurs, the timestamp flag bit (TSF) in RTC_ISR register is set.

By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp event occurs.

Note:

If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and

RTC_TSDR) maintain the results of the previous event.

TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization process.

There is no delay in the setting of TSOVF. This means that if two timestamp events are close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is recommended to poll TSOVF only after TSF has been set.

Caution: If a timestamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the

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‘1’.

Optionally, a tamper event can cause a timestamp to be recorded. See the description of the

TAMPTS control bit in

Section 17.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR) . If the timestamp event is on the same pin as a tamper event

configured in filtered mode (TAMPFLT set to a non-zero value), the timestamp on tamper detection event mode must be selected by setting TAMPTS='1' in RTC_TAFCR register.

TIMESTAMP additional function

The TIMESTAMP additional function is mapped to RTC_AF1.

One tamper detection input is available. It can be configured either for edge detection, or for level detection with filtering.

RTC backup registers

The backup registers (RTC_BKPxR) are twenty 32-bit registers for storing 80 bytes of user application data. They are implemented in the backup domain that remains powered-on by

BAT when the V

DD power is switched off. They are not reset by system reset or when the device wakes up from Standby mode. They are reset by a backup domain reset

The backup registers are reset when a tamper detection event occurs (see

Section 17.6.20:

RTC backup registers (RTC_BKPxR)

and Tamper detection initialization on page 447 .

Tamper detection initialization

The tamper detection input is associated with the TAMP1F flag in the RTC_ISR register. The input can be enabled by setting the TAMP1E bit to 1 in the RTC_TAFCR register.

A tamper detection event resets all backup registers (RTC_BKPxR).

By setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a tamper detection event occurs.

Timestamp on tamper event

With TAMPTS set to ‘1 , any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs. The tamper flag register (TAMP1F) is set at the same time that

TSF or TSOVF is set.

Edge detection on tamper inputs

If the TAMPFLT bits are “00”, the TAMPER pin generates tamper detection events

(RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the

TAMPER input are deactivated when edge detection is selected.

Caution: To avoid losing tamper detection events, the signal used for edge detection is logically

ANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the

TAMPERx pin is enabled.

• When TAMPxTRG = 0: if the TAMPERx additional function is already high before tamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon

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Note:

Note: as TAMPERx is enabled, even if there was no rising edge on TAMPERx after TAMPxE was set.

• When TAMPxTRG = 1: if the TAMPERx additional function is already low before tamper detection is enabled, a tamper event is detected as soon as TAMPERx is enabled (even if there was no falling edge on TAMPERx after TAMPxE was set.

After a tamper event has been detected and cleared, the TAMPERx additional function should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (RTC_BKPxR). This prevents the application from writing to the backup registers while the TAMPERx value still indicates a tamper detection. This is equivalent to a level detection on the TAMPERx additional function.

Tamper detection is still active when V

power is switched off. To avoid unwanted resetting of the backup registers, the pin to which the TAMPER additional function is mapped should be externally tied to the correct level.

Level detection with filtering on tamper input

Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level designated by the TAMPxTRG bits (TAMP1TRG).

The TAMPER input is pre-charged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper inputs.

The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection.

Refer to the datasheets for the electrical characteristics of the pull-up resistors.

TAMPER additional function detection

The TAMPER1 addtional function is mapped to the RTC_AF1 pin.

17.3.14 Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the

RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and

PREDIV_A = 0x7F, the RTC_CALIB frequency is f

RTCCLK /64

. This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz.

The RTC_CALIB output is not impacted by the calibration value programmed in

RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges.

If COSEL is set and (PREDIV_S+1) is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] =

0xFF), the RTC_CALIB frequency is f RTCCLK /(256 * (PREDIV_A+1)). This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = 0x7F, PREDIV_S =

0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift operation is on going and may toggle during the shift operation (SHPF=1).

Calibration alternate function output

When the COE bit in the RTC_CR register is set to 1, the calibration alternate function

(RTC_CALIB) is enabled on RTC_OUT.

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When RTC_CALIB or RTC_ALARM is selected, RTC_OUT is automatically configured in output alternate function.

Note:

Three functions can be selected on Alarm output: ALRAF. These functions reflect the contents of the corresponding flags in the RTC_ISR register.

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate function output (RTC_ALARM) in RTC_AF1, and to select the function which is output on

RTC_ALARM.

The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the selected flag bit is output when POL is set to 1.

Alarm alternate function output

RTC_ALARM can be configured in output open drain or output push-pull using the control bit ALARMOUTTYPE in the RTC_TAFCR register.

Once RTC_ALARM is enabled, it has priority over RTC_CALIB ( COE bit is don't care on

RTC_AF1 ).

When RTC_CALIB or RTC_ALARM is selected, RTC_OUT is automatically configured in output alternate function.

17.4 RTC and low-power modes

Table 66. Effect of low-power modes on RTC

Mode Description

Sleep

Stop

Standby

No effect

RTC interrupts cause the device to exit the Sleep mode.

The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper event, RTC time stamp event, and RTC Wakeup cause the device to exit the Stop mode.

The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper event, RTC time stamp event, and RTC Wakeup cause the device to exit the

Standby mode.

All RTC interrupts are connected to the EXTI controller.

To enable the RTC Alarm interrupt, the following sequence is required:

Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity.

2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.

3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).

To enable the RTC Wakeup interrupt, the following sequence is required:

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Configure and enable the EXTI Line 22 in interrupt mode and select the rising edge sensitivity.

2. Configure and enable the RTC_WKUP IRQ channel in the NVIC.

3. Configure the RTC to generate the RTC wakeup timer event.

To enable the RTC Tamper interrupt, the following sequence is required:

Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity.

2. Configure and Enable the TAMP_STAMP IRQ channel in the NVIC.

3. Configure the RTC to detect the RTC tamper event.

To enable the RTC TimeStamp interrupt, the following sequence is required:

Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity.

2. Configure and Enable the TAMP_STAMP IRQ channel in the NVIC.

3. Configure the RTC to detect the RTC timestamp event.

Alarm A

Alarm B

Wakeup

TimeStamp

Interrupt event

Tamper1 detection

Table 67. Interrupt control bits

Event flag

ALRAF

ALRBF

WUTF

TSF

Enable control bit

ALRAIE

ALRBIE

WUTIE

TSIE

TAMP1F TAMPIE

Exit the

Sleep mode yes yes yes yes yes

Exit the

Stop mode yes

(1) yes

(1)

Exit the

Standby mode yes

(1) yes

(1)

1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.

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Refer to

Section 1.1: List of abbreviations for registers for registers

for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32 bits).

17.6.1 RTC time register (RTC_TR)

The RTC_TR is the calendar time shadow register. This register must be written in

initialization mode only. Refer to Calendar initialization and configuration on page 439

and

Reading the calendar on page 440 .

Address offset: 0x00

Backup domain reset value: 0x0000 0000

System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

Res.

30 29

14 rw

MNT[2:0] rw

12 rw

28 27

Reserved

11 rw

MNU[3:0]

9 rw rw

8 rw

Bits 31-24 Reserved

Bit 23 Reserved, must be kept at reset value.

Bit 22 PM : AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0] : Hour tens in BCD format

Bits 19:16 HU[3:0] : Hour units in BCD format

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 MNT[2:0] : Minute tens in BCD format

Bit 11:8 MNU[3:0] : Minute units in BCD format

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ST[2:0] : Second tens in BCD format

Bits 3:0 SU[3:0] : Second units in BCD format

Res.

PM rw

6 rw

ST[2:0]

20 rw

HT[1:0] rw

4 rw rw

19 rw

3 rw

18 17 rw

HU[3:0] rw

SU[3:0]

1 rw rw

16 rw

0 rw

Note: This register is write protected. The write access procedure is described in

initialization mode only. Refer to Calendar initialization and configuration on page 439

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17.6.2 RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in

and

Reading the calendar on page 440 .

Address offset: 0x04

Backup domain reset value: 0x0000 2101

System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29

15 rw

WDU[2:0] rw

13 rw

28 27

Reserved

MT rw

11 rw

26 25

10 9 rw

MU[3:0] rw

8 rw

Bits 31-24 Reserved

Bits 23:20 YT[3:0] : Year tens in BCD format

Bits 19:16 YU[3:0] : Year units in BCD format

Bits 15:13 WDU[2:0] : Week day units

000: forbidden

001: Monday

...

111: Sunday

Bit 12 MT : Month tens in BCD format

Bits 11:8 MU : Month units in BCD format

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 DT[1:0] : Date tens in BCD format

Bits 3:0 DU[3:0] : Date units in BCD format

23 rw

YT[3:0]

21 rw

6 rw

Reserved

20 rw

4 rw

DT[1:0] rw

19 rw

3 rw

YU[3:0]

17 rw

2 rw

1 rw

DU[3:0] rw

16 rw

0 rw

Note: This register is write protected. The write access procedure is described in

values (PREDIV_A=127 and PREDIV_S=255). Refer to Section 17.3.14: Calibration clock output

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Address offset: 0x08

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30 29 28 27

Reserved

15 14 13 12 11

TSIE WUTIE ALRBIE ALRAIE TSE rw rw rw rw rw

COE rw

WUTE ALRBE ALRAE DCE rw rw rw rw

22 21

OSEL[1:0] rw

6 rw

FMT rw

POL rw

19 rw

BYPS

HAD rw

REFCKON TSEDGE rw rw

18 17 16

BKP SUB1H ADD1H rw

2 w

1 w

0 rw

WUCKSEL[2:0] rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 COE : Calibration output enable

This bit enables the RTC_CALIB output

0: Calibration output disabled

1: Calibration output enabled

Bits 22:21 OSEL[1:0] : Output selection

These bits are used to select the flag to be routed to RTC_ALARM output

00: Output disabled

01: Alarm A output enabled

10:Alarm B output enabled

11: Wakeup output enabled

Bit 20 POL : Output polarity

This bit is used to configure the polarity of RTC_ALARM output

0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).

Bit 19 COSEL : Calibration output selection

When COE=1, this bit selects which signal is output on RTC_CALIB.

0: Calibration output is 512 Hz

1: Calibration output is 1 Hz

These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default

Bit 18 BKP : Backup

This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.

Bit 17 SUB1H : S ubtract 1 hour (winter time change)

When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0.

Setting this bit has no effect when current hour is 0.

0: No effect

1: Subtracts 1 hour to the current time. This can be used for winter time change.

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Bit 16 ADD1H : Add 1 hour (summer time change)

When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.

0: No effect

1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode.

Bit 15 TSIE : Timestamp interrupt enable

0: Timestamp Interrupt disable

1: Timestamp Interrupt enable

Bit 14 WUTIE : Wakeup timer interrupt enable

0: Wakeup timer interrupt disabled

1: Wakeup timer interrupt enabled

Bit 13 ALRBIE : Alarm B interrupt enable

0: Alarm B Interrupt disable

1: Alarm B Interrupt enable

Bit 12 ALRAIE : Alarm A interrupt enable

0: Alarm A interrupt disabled

1: Alarm A interrupt enabled

Bit 11 TSE : Time stamp enable

0: Time stamp disable

1: Time stamp enable

Bit 10 WUTE : Wakeup timer enable

0: Wakeup timer disabled

1: Wakeup timer enabled

Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.

Bit 9 ALRBE : Alarm B enable

0: Alarm B disabled

1: Alarm B enabled

Bit 8 ALRAE: Alarm A enable

0: Alarm A disabled

1: Alarm A enabled

Bit 7 DCE: Coarse digital calibration enable

0: Digital calibration disabled

1: Digital calibration enabled

PREDIV_A must be 6 or greater

Bit 6 FMT : Hour format

0: 24 hour/day format

1: AM/PM hour format

Bit 5 BYPSHAD : Bypass the shadow registers

0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles.

1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters.

Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,

BYPSHAD must be set to ‘1’.

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Bit 4 REFCKON : Reference clock detection enable (50 or 60 Hz)

0: Reference clock detection disabled

1: Reference clock detection enabled

Note: PREDIV_S must be 0x00FF.

Bit 3 TSEDGE : Timestamp event active edge

0: TIMESTAMP rising edge generates a timestamp event

1: TIMESTAMP falling edge generates a timestamp event

TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting

Bits 2:0 WUCKSEL[2:0] : Wakeup clock selection

000: RTC/16 clock is selected

001: RTC/8 clock is selected

010: RTC/4 clock is selected

011: RTC/2 clock is selected

10x: ck_spre (usually 1 Hz) clock is selected

11x: ck_spre (usually 1 Hz) clock is selected and 2

(see note below) is added to the WUT counter value

WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when

WUCKSEL[2:1 = 11].

Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).

Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR

WUTWF bit = 1.

It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour.

ADD1H and SUB1H changes are effective in the next second.

To avoid spuriously setting of TSF, TSE must be reset when TSEDGE is changed.

This register is write protected. The write access procedure is described in

Res.

Address offset: 0x0C

Backup domain reset value: 0x0000 0007

System reset value: Not affected except INIT, INITF and RSF which are cleared to 0.

30 29 28 27 26 25 24 23

Res.

Reserved

TAMP

TSOVF

TSF

10 9 8

WUTF ALRBF ALRAF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

INIT rw

22 21 20 19

INITF r

RSF rc_w0

4 3

INITS SHPF r r

WUT

WF r

ALRB

WF r

RECAL

PF r

ALRA

WF r

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Bits 31:17 Reserved

Bit 16 RECALPF : Recalibration pending Flag

The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to ‘0’. Refer to Section : Re-calibration on-thefly .

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 TAMP1F : Tamper detection flag

This flag is set by hardware when a tamper detection event is detected.

It is cleared by software writing 0.

Bit 12 TSOVF : Timestamp overflow flag

This flag is set by hardware when a timestamp event occurs while TSF is already set.

This flag is cleared by software by writing 0. It is recommended to check and then clear

TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.

Bit 11 TSF : Timestamp flag

This flag is set by hardware when a timestamp event occurs.

This flag is cleared by software by writing 0.

Bit 10 WUTF : Wakeup timer flag

This flag is set by hardware when the wakeup auto-reload counter reaches 0.

This flag is cleared by software by writing 0.

This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.

Bit 9 ALRBF : Alarm B flag

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the

Alarm B register (RTC_ALRMBR).

This flag is cleared by software by writing 0.

Bit 8 ALRAF : Alarm A flag

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the

Alarm A register (RTC_ALRMAR).

This flag is cleared by software by writing 0.

Bit 7 INIT : Initialization mode

0: Free running mode

1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

Bit 6 INITF : Initialization flag

When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.

0: Calendar registers update is not allowed

1: Calendar registers update is allowed.

Bit 5 RSF : Registers synchronization flag

This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software.

0: Calendar shadow registers not yet synchronized

1: Calendar shadow registers synchronized

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Bit 4 INITS : Initialization status flag

This bit is set by hardware when the calendar year field is different from 0 (backup domain reset value state).

0: Calendar has not been initialized

1: Calendar has been initialized

Bit 3 SHPF : Shift operation pending

0: No shift operation is pending

1: A shift operation is pending

This flag is set by hardware as soon as a shift operation is initiated by a write to the

RTC_SHIFTR. It is cleared by hardware when the corresponding shift operation has been executed. Writing to SHPF has no effect.

Bit 2 WUTWF : Wakeup timer write flag

This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in

RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.

0: Wakeup timer configuration update not allowed

1: Wakeup timer configuration update allowed

Bit 1 ALRBWF : Alarm B write flag

This bit is set by hardware when Alarm B values can be changed, after the ALRBIE bit has been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm B update not allowed

1: Alarm B update allowed.

Bit 0 ALRAWF : Alarm A write flag

This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm A update not allowed

1: Alarm A update allowed

The ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming them to 0.

This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in

Calendar initialization and configuration on page 439

Res.

Address offset: 0x10

Backup domain reset value: 0x007F 00FF

System reset: not affected

30 29 25 24

14 rw

13 rw

28 27

Reserved

12 11 10 rw rw rw

9 rw

23 22

8 7 rw

6 rw

PREDIV_S[14:0] rw rw

21 rw

5 rw

20 19

PREDIV_A[6:0]

18 rw

4 rw

3 rw

2 rw rw rw

17 rw

1 rw

16 rw

0 rw

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Note:

Bits 31:24 Reserved

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 PREDIV_A[6:0] : Asynchronous prescaler factor

This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)

Bit 15 Reserved, must be kept at reset value.

Bits 14:0 PREDIV_S[14:0] : Synchronous prescaler factor

This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)

This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to

This register is write protected. The write access procedure is described in

15 rw

Note:

Address offset: 0x14

Backup domain reset value: 0x0000 FFFF

System reset: not affected

30 29 28 27 26 25

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

24 23

Reserved

8 7

WUT[15:0] rw rw

0 rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 WUT[15:0] : Wakeup auto-reload value bits

When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]

+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the

RTC_CR register

When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer.

Note: The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting

WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.

This register can be written only when WUTWF is set to 1 in RTC_ISR.

This register is write protected. The write access procedure is described in

Refer to Case of RTCCLK=32.768 kHz and PREDIV_A+1=128 on page 444 for the exact

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RM0368 Rev 5

RM0368 Real-time clock (RTC)

Address offset: 0x18

Backup domain reset value: 0x0000 0000

System reset: not affected

30 29 28 27 26 25 24 23

Reserved

14 13 12 11

Reserved

10 9 8 7

DCS rw

22 21 20 19 18 17 16

6 5

Reserved

4 3 2

DC[4:0] rw

1 rw

0 rw rw rw

Bits 31:8 Reserved

Bit 7 DCS : Digital calibration sign

0: Positive calibration: calendar update frequency is increased

1: Negative calibration: calendar update frequency is decreased

Bits 6:5 Reserved, must be kept at reset value.

Bits 4:0 DC[4:0] : Digital calibration

DCS = 0 (positive calibration)

00000: + 0 ppm

00001: + 4 ppm (rounded value)

00010: + 8 ppm (rounded value)

11111: + 126 ppm (rounded value)

DCS = 1 (negative calibration)

00000: − 0 ppm

00001: − 2 ppm (rounded value)

00010: − 4 ppm (rounded value)

11111: − 63 ppm (rounded value)

step value.

Note: This register can be written in initialization mode only (RTC_ISR/INITF = ‘1’).

This register is write protected. The write access procedure is described in

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Real-time clock (RTC)

17.6.8 RTC alarm A register (RTC_ALRMAR)

Address offset: 0x1C

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30

MSK4 WDSEL rw

15 rw

MSK2 rw rw

29 rw

DT[1:0]

MNT[2:0] rw

28 rw

12 rw

27 rw

11 rw

DU[3:0]

25 rw

10 rw

MNU[3:0] rw rw

24 rw

8 rw

MSK3 rw

MSK1 rw

PM rw

6 rw

HT[1:0]

20 rw

5 rw

ST[2:0] rw rw

Bit 31 MSK4 : Alarm A date mask

0: Alarm A set if the date/day match

1: Date/day don’t care in Alarm A comparison

Bit 30 WDSEL : Week day selection

0: DU[3:0] represents the date units

1: DU[3:0] represents the week day. DT[1:0] is don’t care.

Bits 29:28 DT[1:0] : Date tens in BCD format.

Bits 27:24 DU[3:0] : Date units or day in BCD format.

Bit 23 MSK3 : Alarm A hours mask

0: Alarm A set if the hours match

1: Hours don’t care in Alarm A comparison

Bit 22 PM: AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0] : Hour tens in BCD format.

Bits 19:16 HU[3:0] : Hour units in BCD format.

Bit 15 MSK2 : Alarm A minutes mask

0: Alarm A set if the minutes match

1: Minutes don’t care in Alarm A comparison

Bits 14:12 MNT[2:0] : Minute tens in BCD format.

Bits 11:8 MNU[3:0] : Minute units in BCD format.

Bit 7 MSK1 : Alarm A seconds mask

0: Alarm A set if the seconds match

1: Seconds don’t care in Alarm A comparison

Bits 6:4 ST[2:0] : Second tens in BCD format.

Bits 3:0 SU[3:0] : Second units in BCD format.

RM0368

19 rw

3 rw

HU[3:0]

17 rw

2 rw

1 rw

SU[3:0] rw

16 rw

0 rw

Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.

This register is write protected. The write access procedure is described in

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RM0368 Rev 5

RM0368 Real-time clock (RTC)

17.6.9 RTC alarm B register (RTC_ALRMBR)

Address offset: 0x20

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30

MSK4 WDSEL rw rw

DT[1:0]

28 rw rw

27 rw

DU[3:0]

25 rw rw

24 rw

MSK3 rw

PM rw

MSK2 rw

14 rw

MNT[2:0] rw

12 rw

11 rw

10 9

MNU[3:0] rw rw

8 rw

MSK1 rw

HT[1:0]

20 rw rw

6 rw

ST[2:0] rw

Bit 31 MSK4 : Alarm B date mask

0: Alarm B set if the date and day match

1: Date and day don’t care in Alarm B comparison

Bit 30 WDSEL : Week day selection

0: DU[3:0] represents the date units

1: DU[3:0] represents the week day. DT[1:0] is don’t care.

Bits 29:28 DT[1:0] : Date tens in BCD format

Bits 27:24 DU[3:0] : Date units or day in BCD format

Bit 23 MSK3 : Alarm B hours mask

0: Alarm B set if the hours match

1: Hours don’t care in Alarm B comparison

Bit 22 PM: AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0] : Hour tens in BCD format

Bits 19:16 HU[3:0] : Hour units in BCD format

Bit 15 MSK2 : Alarm B minutes mask

0: Alarm B set if the minutes match

1: Minutes don’t care in Alarm B comparison

Bits 14:12 MNT[2:0] : Minute tens in BCD format

Bits 11:8 MNU[3:0] : Minute units in BCD format

Bit 7 MSK1 : Alarm B seconds mask

0: Alarm B set if the seconds match

1: Seconds don’t care in Alarm B comparison

Bits 6:4 ST[2:0] : Second tens in BCD format

Bits 3:0 SU[3:0] : Second units in BCD format

4 rw

3 rw

19 rw

HU[3:0]

17 rw rw

2 1 rw

SU[3:0] rw

16 rw

0 rw

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Real-time clock (RTC) RM0368

Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.

This register is write protected. The write access procedure is described in

Refer to RTC register write protection

17.6.10 RTC write protection register (RTC_WPR)

Address offset: 0x24

Backup domain reset value: 0x0000 0000

30 29 28 27 26 25 24 23

Reserved

8 7

22 21 20 19 18 17 16

14 13 12 11

Reserved

10 9 6 5 4 w

KEY

3 w

2 1 0 w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY : Write protection key

This byte is written by software.

Reading this byte always returns 0x00.

for a description of how to unlock RTC register write protection.

17.6.11 RTC sub second register (RTC_SSR)

Address offset: 0x28

Backup domain reset value: 0x0000 0000

System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 22 21 20 19 18 17 r r r r r r r

24 23

Reserved r r r r r r r r

16 r

15 r

14 r

13 r

12 r

11 r

10 r

9 r

8 7 r

SS[15:0] r

6 r

5 r

4 r

3 r

2 r

1 r

0 r

Bits 31:16 Reserved

Bits 15:0 SS : Sub second value

SS[15:0] is the value in the synchronous prescaler’s counter. The fraction of a second is given by the formula below:

Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 )

Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.

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RM0368 Real-time clock (RTC)

17.6.12 RTC shift control register (RTC_SHIFTR)

Address offset: 0x2C

Backup domain reset value: 0x0000 0000

System reset: not affected

30 29 28 27 26 25 31

ADD1S w r r r r r r

24 r

Reserved r

22 r

21 r

Res.

20 19 18 17 16 r r r r r

14 w

13 w

12 w

11 w

10 w

9 w

8 w

SUBFS[14:0] w

6 w

5 w

4 w

3 w

2 w

1 w

0 w

Bit 31 ADD1S : Add one second

0: No effect

1: Add one second to the clock/calendar

This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR).

This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.

Bits 30:15 Reserved

Bits 14:0 SUBFS : Subtract a fraction of a second

These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR).

The value which is written to SUBFS is added to the synchronous prescaler’s counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by:

Delay (seconds) = SUBFS / ( PREDIV_S + 1 )

A fraction of a second can effectively be added to the clock (advancing the clock) when the

ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:

Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .

Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time.

Refer to Section 17.3.8: RTC synchronization .

Note: This register is write protected. The write access procedure is described in

RTC register write protection on page 439

17.6.13 RTC time stamp time register (RTC_TSTR)

Address offset: 0x30

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30 29 25 24 23 28 27

Reserved

26 22

PM r

HT[1:0]

20 r r

19 r

HU[3:0]

17 r r

16 r

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Res.

14 r

MNT[2:0] r

12 r

11 r

10 9 r

MNU[3:0] r

8 r

Res.

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0] : Hour tens in BCD format.

Bits 19:16 HU[3:0] : Hour units in BCD format.

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 MNT[2:0] : Minute tens in BCD format.

Bits 11:8 MNU[3:0] : Minute units in BCD format.

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ST[2:0] : Second tens in BCD format.

Bits 3:0 SU[3:0] : Second units in BCD format.

6 r

ST[2:0] r

4 r

3 r

2 r

SU[3:0] r

0 r

Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when

TSF bit is reset.

17.6.14 RTC time stamp date register (RTC_TSDR)

Address offset: 0x34

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30 29

15 r

WDU[1:0] r

13 r

MT r

11 r

26 25

MU[3:0]

9 r r

24 23

Reserved

8 7

Reserved r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 WDU[1:0] : Week day units

Bit 12 MT : Month tens in BCD format

Bits 11:8 MU[3:0] : Month units in BCD format

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 DT[1:0] : Date tens in BCD format

Bit 3:0 DU[3:0] : Date units in BCD format

21 20

DT[1:0]

4 r r

3 r

18 17

DU[3:0]

1 r r

0 r

Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when

TSF bit is reset.

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RM0368 Real-time clock (RTC)

31 r

15 r

Address offset: 0x38

Backup domain reset value: 0x0000 0000

System reset: not affected

30 29 28 27 26 25 r r r r r r

24 23

Reserved r r

22 21 20 19 18 17 16 r r r r r r

14 r

13 r

12 r

11 r

10 r

9 r

8 7 r

SS[15:0] r

6 r

5 r

4 r

3 r

2 r

1 r

Bits 31:16 Reserved

Bits 15:0 SS : Sub second value

SS[15:0] is the value of the synchronous prescaler’s counter when the timestamp event occurred.

0 r r

Note: The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the

RTC_ISR/TSF bit is reset.

17.6.16 RTC calibration register (RTC_CALR)

Address offset: 0x3C

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30 29 28 27 26 25 r r r r r r r

24 23 r

Reserved r

22 r

21 r

20 r

19 r

18 r

17 r

16 r

15 14 13

CALP CALW8 CALW16 rw rw rw

12 r

11 10

Reserved r r

9 r

8 rw

7 rw

6 rw

5 rw

CALM[8:0]

3 rw rw

2 rw

1 rw

0 rw

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Note:

Bits 31:16 Reserved

Bit 15 CALP: Increase frequency of RTC by 488.5 ppm

0: No RTCCLK pulses are added.

1: One RTCCLK pulse is effectively inserted every 2

pulses (frequency increased by

488.5 ppm).

This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of

RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) -

CALM.

Refer to Section 17.3.11: RTC smooth digital calibration .

Bit 14 CALW8: Use an 8-second calibration cycle period

When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.

CALM[1:0] are stuck at “00” when CALW8=’1’.

Refer to

Section 17.3.11: RTC smooth digital calibration .

Bit 13 CALW16: Use a 16-second calibration cycle period

When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected. This bit must not be set to ‘1’ if CALW8=1.

Note: CALM[0] is stuck at ‘0’ when CALW16=’1’.

Refer to

Section 17.3.11: RTC smooth digital calibration .

Bits 12:9 Reserved

Bits 8:0 CALM[8:0] : Calibration minus

The frequency of the calendar is reduced by masking CALM out of 2

RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm.

To increase the frequency of the calendar, this feature should be used in conjunction with

CALP.

See

Section 17.3.11: RTC smooth digital calibration on page 444

This register is write protected. The write access procedure is described in

RTC register write protection on page 439

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RM0368 Real-time clock (RTC)

17.6.17 RTC tamper and alternate function configuration register

(RTC_TAFCR)

Address offset: 0x40

Backup domain reset value: 0x0000 0000

System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20

TAMP-

PUDIS rw

14 13

TAMP-

PRCH[1:0] rw rw

12 11

TAMPFLT[1:0] rw rw

Reserved

10 9 8 rw

TAMPFREQ[2:0] rw rw

TAMPT

S rw

6 5 4

Reserved

ALARMOUT

TYPE rw

TAMPIE rw

TSIN

SEL rw

TAMP1

INSEL rw

TAMP1

TRG rw

TAMP1

E rw

Bits 31:19 Reserved. Always read as 0.

Bit 18 ALARMOUTTYPE : RTC_ALARM output type

0: RTC_ALARM is an open-drain output

1: RTC_ALARM is a push-pull output

Bit 17 TSINSEL : TIMESTAMP mapping

0: RTC_AF1 used as TIMESTAMP

1: Reserved

Bit 16 TAMP1INSEL : TAMPER1 mapping

0: RTC_AF1 used as TAMPER1

1: Reserved

Bit 15 TAMPPUDIS : TAMPER pull-up disable

This bit determines if each of the tamper pins are pre-charged before each sample.

0: Precharge tamper pins before sampling (enable internal pull-up)

1: Disable precharge of tamper pins

Note:

Bits 14:13 TAMPPRCH[1:0] : Tamper precharge duration

These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the tamper inputs.

0x0: 1 RTCCLK cycle

0x1: 2 RTCCLK cycles

0x2: 4 RTCCLK cycles

0x3: 8 RTCCLK cycles

Bits 12:11 TAMPFLT[1:0] : Tamper filter count

These bits determines the number of consecutive samples at the specified level

(TAMP*TRG) necessary to activate a Tamper event. TAMPFLT is valid for each of the tamper inputs.

0x0: Tamper is activated on edge of tamper input transitions to the active level (no internal pull-up on tamper input).

0x1: Tamper is activated after 2 consecutive samples at the active level.

0x2: Tamper is activated after 4 consecutive samples at the active level.

0x3: Tamper is activated after 8 consecutive samples at the active level.

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Bits 10:8 TAMPFREQ[2:0] : Tamper sampling frequency

Determines the frequency at which each of the tamper inputs are sampled.

0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)

0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)

0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)

0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)

0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)

0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)

0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)

0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)

Bit 7 TAMPTS : Activate timestamp on tamper detection event

0: Tamper detection event does not cause a timestamp to be saved

1: Save timestamp on tamper detection event

TAMPTS is valid even if TSE=0 in the RTC_CR register.

Bits 6:3 Reserved. Always read as 0.

Bit 2 TAMPIE : Tamper interrupt enable

0: Tamper interrupt disabled

1: Tamper interrupt enabled

Bit 1 TAMP1TRG : Active level for tamper 1 if TAMPFLT != 00

0: TAMPER1 staying low triggers a tamper detection event.

1: TAMPER1 staying high triggers a tamper detection event.

if TAMPFLT = 00:

0: TAMPER1 rising edge triggers a tamper detection event.

1: TAMPER1 falling edge triggers a tamper detection event.

Caution: When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid spuriously setting TAMPxF.

Bit 0 TAMP1E : Tamper 1 detection enable

0: Tamper 1 detection disabled

1: Tamper 1 detection enabled

17.6.18 RTC alarm A sub second register (RTC_ALRMASSR)

Address offset: 0x44

Backup domain reset value: 0x0000 0000

System reset: not affected

31 r

30 29 r

Reserved r

28 r

27 rw

26 25

MASKSS[3:0] rw rw

24 rw

23 r

22 r

21 r

20 19 r

Reserved r

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

8 rw

SS[14:0] rw

6 rw

5 rw

4 rw

3 rw

2 w

18 r rw

1 r

0 r rw

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RM0368 Rev 5

RM0368 Real-time clock (RTC)

Bits 31:28 Reserved

Bits 27:24 MASKSS[3:0] : Mask the most-significant bits starting at this bit

0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).

1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.

2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared.

3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared.

...

12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.

13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.

14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.

15: All 15 SS bits are compared and must match to activate alarm.

The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.

Bits 23:15 Reserved

Bits 14:0 SS[14:0] : Sub seconds value

This value is compared with the contents of the synchronous prescaler’s counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.

Note: This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.

This register is write protected. The write access procedure is described in

RTC register write protection on page 439

17.6.19 RTC alarm B sub second register (RTC_ALRMBSSR)

Address offset: 0x48

Backup domain reset value: 0x0000 0000

System reset: not affected

31 r

30 29 r

Reserved r

28 r

27 rw

26 25

MASKSS[3:0] rw rw

24 rw

23 r

22 r

21 r

20 19 r

Reserved r

18 r

17 r

16 r

Reserved r

14 rw

13 rw

12 rw

11 rw

10 rw

9 rw

8 rw

SS[14:0] rw

6 rw

5 rw

4 rw

3 rw

2 w

1 rw

0 rw

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Note:

Bits 31:28 Reserved

Bits 27:24 MASKSS[3:0] : Mask the most-significant bits starting at this bit

0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).

0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared.

0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared.

0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared.

...

0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared.

0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared.

0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared.

0xF: All 15 SS bits are compared and must match to activate alarm.

The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.

Bits 23:15 Reserved

Bits 14:0 SS[14:0] : Sub seconds value

This value is compared with the contents of the synchronous prescaler’s counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.

This register can be written only when ALRBIE is reset in RTC_CR register, or in initialization mode.

This register is write protected.The write access procedure is described in Section : RTC register write protection

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RM0368 Real-time clock (RTC)

17.6.20 RTC backup registers (RTC_BKPxR)

Address offset: 0x50 to 0x9C

Backup domain reset value: 0x0000 0000

System reset: not affected

31 rw

15 rw

30 29 rw

14 rw rw

28 rw

27 rw

26 rw

25 rw

24 23

BKP[31:16] rw

8 rw

BKP[15:0] rw rw

22 rw

21 rw

20 rw

19 rw

18 rw

17 rw

16 rw

0 rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:0 BKP[31:0]

The application can write or read data to and from these registers.

They are powered-on by V

BAT

when V

is switched off, so that they are not reset by

System reset, and their contents remain valid when the device operates in low-power mode.

This register is reset on a tamper detection event, as long as TAMPxF=1

Offset

0x00

0x04

Register

RTC_TR

Reset value

RTC_DR

Reset value

RTC_CR

0x08

Reset value

RTC_ISR

0x0C

0x10

0x14

0x18

Reset value

RTC_PRER

Reset value

RTC_WUTR

Reset value

RTC_CALIBR

Reset value

Table 68. RTC register map and reset values

Reserved

[1:0]

HU[3:0]

0 0 0 0 0 0 0

YT[3:0] YU[3:0]

MNT[2:0]

0 0

MNU[3:0]

0 0 0 0 0

WDU[2:0] MU[3:0]

0 0 1 0 0 0 0 1

ST[2:0] SU[3:0]

0 0 0 0 0 0 0

[1:0]

DU[3:0]

0 0 0 0 0 1

OSEL

[1:0]

WCKSEL

[2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

PREDIV_A[6:0]

1 1 1 1 1 1 1

Reserved

0 0 0 0 0 0 0 0 0 0 0 1 0 1

PREDIV_S[14:0]

0 0

0 0 0 0 0 1 1 1 1 1 1 1 1

WUT[15:0]

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DC[4:0]

0 0 0 0 0 0

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Real-time clock (RTC) RM0368

Table 68. RTC register map and reset values (continued)

Offset Register

0x1C

0x20

0x24

0x28

RTC_ALRMAR

[1:0]

DU[3:0]

[1:0]

HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]

Reset value

RTC_ALRMBR

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[1:0]

DU[3:0]

[1:0]

HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_WPR

Reset value

Reserved

KEY[7:0]

0 0 0 0 0 0 0 0

RTC_SSR

Reset value

Reserved

SS[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_TSTR HU[3:0] MNU[3:0] ST[2:0] SU[3:0]

0x30 Reserved

0x38

0x3C

Reset value

RTC_TSSSR

Reset value

RTC_ CALR

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0

SS[15:0]

0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CALM[8:0]

Reserved

0 0 0 0 0 0 0 0 0 0 0 0

0x40

RTC_TAFCR

Reserved

0x44

0x48

Reset value

RTC_

ALRMASSR

Reset value

RTC_

ALRMBSSR

Reset value

RTC_BKP0R

Reserved

MASKSS[3:0]

0 0 0 0 0 0 0 0 0 0 0 0

SS[14:0]

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

SS[14:0]

0 0 0 0 0 0 0 0 0 0

BKP[31:0]

0x50 to 0x9C

Reset value to

RTC_BKP19R

Reset value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP[31:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to

Section 2.3: Memory map

for the register boundary addresses.

Caution: In

Table 68 , the reset value is the value after a backup domain reset. The majority of the

registers are not affected by a system reset. For more information, please refer to

Section 17.3.7: Resetting the RTC

472/847

RM0368 Rev 5

RM0368

18

Inter-integrated circuit (I2C) interface

Inter-integrated circuit (I2C) interface

18.1 I

2 C introduction

C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I

C bus. It provides multimaster capability, and controls all I

C bus-specific sequencing, protocol, arbitration and timing. It supports the standard mode (Sm, up to

100 kHz) and Fm mode (Fm, up to 400 kHz). The I2C bus frequency can be increased up to

1 MHz. For more details about the complete solution, please contact your local ST sales representative.

It may be used for a variety of purposes, including CRC generation and verification, SMBus

(system management bus) and PMBus (power management bus).

18.2 I 2 C main features

• Parallel-bus/I 2 C protocol converter

• Multimaster capability: the same interface can act as Master or Slave

• I 2 C Master features:

– Clock generation

– Start and Stop generation

• I

C Slave features:

– Programmable I 2 C Address detection

– Dual Addressing Capability to acknowledge 2 slave addresses

– Stop bit detection

• Generation and detection of 7-bit/10-bit addressing and General Call

• Supports different communication speeds:

– Standard Speed (up to 100 kHz)

– Fast Speed (up to 400 kHz)

– The I2C bus frequency can be increased up to 1 MHz. For more details about the complete solution, please contact your local ST sales representative

• Analog noise filter

• Programmable digital noise filter

• Status flags:

– Transmitter/Receiver mode flag

– End-of-Byte transmission flag

– I

C busy flag

• Error flags:

– Arbitration lost condition for master mode

– Acknowledgment failure after address/ data transmission

– Detection of misplaced start or stop condition

– Overrun/Underrun if clock stretching is disabled

• 2 Interrupt vectors:

– 1 Interrupt for successful address/ data communication

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Inter-integrated circuit (I2C) interface

Note:

RM0368

– 1 Interrupt for error condition

• Optional clock stretching

• 1-byte buffer with DMA capability

• Configurable PEC (packet error checking) generation or verification:

– PEC value can be transmitted as last byte in Tx mode

– PEC error checking for last received byte

• SMBus 2.0 Compatibility:

– 25 ms clock low timeout delay

– 10 ms master cumulative clock low extend time

– 25 ms slave cumulative clock low extend time

– Hardware PEC generation/verification with ACK control

– Address Resolution Protocol (ARP) supported

• PMBus Compatibility

Some of the above features may not be available in certain products. The user should refer to the product data sheet, to identify the specific features supported by the I 2 C interface implementation.

18.3 I

2 C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I

C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz) or fast (up to 400 kHz) I

C bus.

474/847

The interface can operate in one of the four following modes:

• Slave transmitter

• Slave receiver

• Master transmitter

• Master receiver

By default, it operates in slave mode. The interface automatically switches from slave to master, after it generates a START condition and from master to slave, if an arbitration loss or a Stop generation occurs, allowing multimaster capability.

Communication flow

In Master mode, the I 2 C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.

In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode.

RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to

Figure 160

Figure 160. I 2 C bus protocol

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C interface addresses (dual addressing 7-bit/ 10-bit and/or general call address) can be selected by software.

The block diagram of the I

C interface is shown in

Figure 161 .

RM0368 Rev 5

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505

Inter-integrated circuit (I2C) interface

Figure 161. I 2 C block diagram

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1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.

18.3.2 I

C slave mode

By default the I 2 C interface operates in Slave mode. To switch from default Slave mode to

Master mode a Start condition generation is needed.

Note:

The peripheral input clock must be programmed in the I2C_CR2 register in order to generate correct timings. The peripheral input clock frequency must be at least:

• 2 MHz in Sm mode

• 4 MHz in Fm mode

As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register. Then it is compared with the address of the interface (OAR1) and with

OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).

In 10-bit addressing mode, the comparison includes the header sequence (11110xx0), where xx denotes the two most significant bits of the address.

476/847

RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

Header or address not matched : the interface ignores it and waits for another Start condition.

Header matched (10-bit mode only): the interface generates an acknowledge pulse if the

ACK bit is set and waits for the 8-bit slave address.

Address matched : the interface generates in sequence:

• An acknowledge pulse if the ACK bit is set

• The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.

• If ENDUAL=1, the software has to read the DUALF bit to check which slave address has been acknowledged.

In 10-bit mode, after receiving the address sequence the slave is always in Receiver mode.

It will enter Transmitter mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1).

The TRA bit indicates whether the slave is in Receiver or Transmitter mode.

Slave transmitter

Following the address reception and after clearing ADDR, the slave sends bytes from the

DR register to the SDA line via the internal shift register.

The slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent

(see Figure 162 Transfer sequencing EV1 EV3).

When the acknowledge pulse is received:

• The TxE bit is set by hardware with an interrupt if the ITEVFEN and the ITBUFEN bits are set.

If TxE is set and some data were not written in the I2C_DR register before the end of the next data transmission, the BTF bit is set and the interface waits until BTF is cleared by a read to I2C_SR1 followed by a write to the I2C_DR register, stretching SCL low.

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Inter-integrated circuit (I2C) interface RM0368

Figure 162. Transfer sequence diagram for slave transmitter

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1. The EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence.

2. The EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte transmission.

Slave receiver

Following the address reception and after clearing ADDR, the slave receives bytes from the

SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

• An acknowledge pulse if the ACK bit is set

• The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and

ITBUFEN bit is set.

If RxNE is set and the data in the DR register is not read before the end of the next data reception, the BTF bit is set and the interface waits until BTF is cleared by a read from the

I2C_DR register, stretching SCL low (see Figure 163

Transfer sequencing).

478/847

RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

Figure 163. Transfer sequence diagram for slave receiver

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1. The EV1 event stretches SCL low until the end of the corresponding software sequence.

2. The EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte reception.

3. After checking the SR1 register content, the user should perform the complete clearing sequence for each flag found set.

Thus, for ADDR and STOPF flags, the following sequence is required inside the I2C interrupt routine:

READ SR1 if (ADDR == 1) {READ SR1; READ SR2} if (STOPF == 1) {READ SR1; WRITE CR1}

The purpose is to make sure that both ADDR and STOPF flags are cleared if both are found set.

Closing slave communication

After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets:

• The STOPF bit and generates an interrupt if the ITEVFEN bit is set.

The STOPF bit is cleared by a read of the SR1 register followed by a write to the CR1 register (see EV4 in

Figure 163

18.3.3 I

C master mode

In Master mode, the I 2 C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a Start condition and ends with a Stop condition.

Master mode is selected as soon as the Start condition is generated on the bus with a

START bit.

The following is the required sequence in master mode.

• Program the peripheral input clock in I2C_CR2 Register in order to generate correct timings

• Configure the clock control registers

• Configure the rise time register

• Program the I2C_CR1 register to enable the peripheral

• Set the START bit in the I2C_CR1 register to generate a Start condition

The peripheral input clock frequency must be at least:

• 2 MHz in Sm mode

• 4 MHz in Fm mode

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Inter-integrated circuit (I2C) interface

Note:

RM0368

SCL master clock generation

The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in

TRISE bits after rising edge generation.

• If the SCL line is low, it means that a slave is stretching the bus, and the high level counter stops until the SCL line is detected high. This allows to guarantee the minimum

HIGH period of the SCL clock parameter.

• If the SCL line is high, the high level counter keeps on counting.

Indeed, the feedback loop from the SCL rising edge generation by the peripheral to the SCL rising edge detection by the peripheral takes time even if no slave stretches the clock. This loopback duration is linked to the SCL rising time (impacting SCL VIH input detection), plus delay due to the noise filter present on the SCL input path, plus delay due to internal SCL input synchronization with APB clock. The maximum time used by the feedback loop is programmed in the TRISE bits, so that the SCL frequency remains stable whatever the SCL rising time.

Start condition

Setting the START bit causes the interface to generate a Start condition and to switch to

Master mode (MSL bit set) when the BUSY bit is cleared.

In master mode, setting the START bit causes the interface to generate a ReStart condition at the end of the current byte transfer.

Once the Start condition is sent:

• The SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register

with the Slave address (see Figure 164

and Figure 165 Transfer sequencing EV5).

Slave address transmission

Then the slave address is sent to the SDA line via the internal shift register.

• In 10-bit addressing mode, sending the header sequence causes the following event:

– The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register with the second address byte (see

Figure 164

and

Figure 165

Transfer sequencing).

– The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.

Then the master waits for a read of the SR1 register followed by a read of the SR2

register (see Figure 164

and Figure 165

Transfer sequencing).

• In 7-bit addressing mode, one address byte is sent.

As soon as the address byte is sent,

– The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.

Then the master waits for a read of the SR1 register followed by a read of the SR2

register (see Figure 164

and Figure 165

Transfer sequencing).

480/847

RM0368 Rev 5

RM0368

Note:

Inter-integrated circuit (I2C) interface

The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent.

• In 7-bit addressing mode,

– To enter Transmitter mode, a master sends the slave address with LSB reset.

– To enter Receiver mode, a master sends the slave address with LSB set.

• In 10-bit addressing mode,

– To enter Transmitter mode, a master sends the header (11110xx0) and then the slave address, (where xx denotes the two most significant bits of the address).

– To enter Receiver mode, a master sends the header (11110xx0) and then the slave address. Then it should send a repeated Start condition followed by the header (11110xx1), (where xx denotes the two most significant bits of the address).

The TRA bit indicates whether the master is in Receiver or Transmitter mode.

Master transmitter

Following the address transmission and after clearing ADDR, the master sends bytes from the DR register to the SDA line via the internal shift register.

The master waits until the first data byte is written into I2C_DR (see Figure 164 Transfer

sequencing EV8_1).

When the acknowledge pulse is received, the TxE bit is set by hardware and an interrupt is generated if the ITEVFEN and ITBUFEN bits are set.

If TxE is set and a data byte was not written in the DR register before the end of the last data transmission, BTF is set and the interface waits until BTF is cleared by a write to I2C_DR, stretching SCL low.

Closing the communication

After the last byte is written to the DR register, the STOP bit is set by software to generate a

Stop condition (see

Figure 164

Transfer sequencing EV8_2). The interface automatically goes back to slave mode (MSL bit cleared).

Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.

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505

Inter-integrated circuit (I2C) interface

Figure 164. Transfer sequence diagram for master transmitter

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1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence.

2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission.

Master receiver

Following the address transmission and after clearing ADDR, the I

C interface enters

Master Receiver mode. In this mode the interface receives bytes from the SDA line into the

DR register via the internal shift register. After each byte the interface generates in sequence:

An acknowledge pulse if the ACK bit is set

2. The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are

set (see Figure 165

Transfer sequencing EV7).

If the RxNE bit is set and the data in the DR register is not read before the end of the last data reception, the BTF bit is set by hardware and the interface waits until BTF is cleared by a read in the DR register, stretching SCL low.

Closing the communication

The master sends a NACK for the last byte received from the slave. After receiving this

NACK, the slave releases the control of the SCL and SDA lines. Then the master can send a Stop/Restart condition.

To generate the nonacknowledge pulse after the last received data byte, the ACK bit must be cleared just after reading the second last data byte (after second last RxNE event).

2. In order to generate the Stop/Restart condition, software must set the STOP/START bit after reading the second last data byte (after the second last RxNE event).

3. In case a single byte has to be received, the Acknowledge disable is made during EV6

(before ADDR flag is cleared) and the STOP condition generation is made after EV6.

After the Stop condition generation, the interface goes automatically back to slave mode

(MSL bit cleared).

482/847

RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

Figure 165. Transfer sequence diagram for master receiver

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1. If a single byte is received, it is NA.

2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.

3. The EV7 event stretches SCL low if the software sequence is not completed before the end of the next byte reception.

4. The EV7_1 software sequence must be completed before the ACK pulse of the current byte transfer.

The procedures described below are recommended if the EV7-1 software sequence is not completed before the ACK pulse of the current byte transfer.

These procedures must be followed to make sure:

• The ACK bit is set low on time before the end of the last data reception

• The STOP bit is set high after the last data reception without reception of supplementary data.

For 2-byte reception:

• Wait until ADDR = 1 (SCL stretched low until the ADDR flag is cleared)

• Set ACK low, set POS high

• Clear ADDR flag

• Wait until BTF = 1 (Data 1 in DR, Data2 in shift register, SCL stretched low until a data

1 is read)

• Set STOP high

• Read data 1 and 2

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505

Inter-integrated circuit (I2C) interface RM0368

For N >2 -byte reception, from N-2 data reception

• Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read)

• Set ACK low

• Read data N-2

• Wait until BTF = 1 (data N-1 in DR, data N in shift register, SCL stretched low until a data N-1 is read)

• Set STOP high

• Read data N-1 and N

The following are the error conditions which may cause communication to fail.

Bus error (BERR)

This error occurs when the I

C interface detects an external Stop or Start condition during an address or a data transfer. In this case:

• the BERR bit is set and an interrupt is generated if the ITERREN bit is set

• in Slave mode: data are discarded and the lines are released by hardware:

– in case of a misplaced Start, the slave considers it is a restart and waits for an address, or a Stop condition

– in case of a misplaced Stop, the slave behaves like for a Stop condition and the lines are released by hardware

• In Master mode: the lines are not released and the state of the current transmission is not affected. It is up to the software to abort or not the current transmission

Acknowledge failure (AF)

This error occurs when the interface detects a nonacknowledge bit. In this case:

• the AF bit is set and an interrupt is generated if the ITERREN bit is set

• a transmitter which receives a NACK must reset the communication:

– If Slave: lines are released by hardware

– If Master: a Stop or repeated Start condition must be generated by software

Arbitration lost (ARLO)

This error occurs when the I 2 C interface detects an arbitration lost condition. In this case

• the ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is set)

• the I 2 the I 2

C Interface goes automatically back to slave mode (the MSL bit is cleared). When

C loses the arbitration, it is not able to acknowledge its slave address in the same transfer, but it can acknowledge it after a repeated Start from the winning master.

• lines are released by hardware

484/847

RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

Overrun/underrun error (OVR)

An overrun error can occur in slave mode when clock stretching is disabled and the I 2 C interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface. In this case,

• The last received byte is lost.

• In case of Overrun error, software should clear the RxNE bit and the transmitter should re-transmit the last received byte.

Underrun error can occur in slave mode when clock stretching is disabled and the I 2 C interface is transmitting data. The interface has not updated the DR with the next byte

(TxE=1), before the clock comes for the next byte. In this case,

• The same byte in the DR register will be sent again

• The user should make sure that data received on the receiver side during an underrun error are discarded and that the next bytes are written within the clock low time specified in the I 2 C bus standard.

For the first byte to be transmitted, the DR must be written after ADDR is cleared and before the first SCL rising edge. If not possible, the receiver must discard the first data.

18.3.5 Programmable noise filter

In Fm mode, the I

C standard requires that spikes are suppressed to a length of 50 ns on

SDA and SCL lines.

Note:

An analog noise filter is implemented in the SDA and SCL I/Os. This filter is enabled by default and can be disabled by setting the ANOFF bit in the I2C_FLTR register.

A digital noise filter can be enabled by configuring the DNF[3:0] bits to a non-zero value.

This suppresses the spikes on SDA and SCL inputs with a length of up to DNF[3:0] *

PCLK1

Enabling the digital noise filter increases the SDA hold time by (DNF[3:0] +1)* T

PCLK

To be compliant with the maximum hold time of the I

C-bus specification version 2.1

(Thd:dat), the DNF bits must be programmed using the constraints shown in

Table 69 , and

assuming that the analog filter is disabled.

DNF[3:0] must only be configured when the I

C is disabled (PE = 0). If the analog filter is also enabled, the digital filter is added to the analog filter.

Table 69. Maximum DNF[3:0] value to be compliant with Thd:dat(max)

Maximum DNF value

PCLK1 frequency

Sm mode Fm mode

2 <= F

PCLK1

<= 5

5 < F

PCLK1

<= 10

10 < F

PCLK1

<= 20

20 < F

PCLK1

<= 30

30 < F

PCLK1

<= 40

40 < F

PCLK1

<= 50

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Note: For each frequency range, the constraint is given based on the worst case which is the minimum frequency of the range. Greater DNF values can be used if the system can support maximum hold time violation.

18.3.6 SDA/SCL line control

• If clock stretching is enabled:

– Transmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data

– Receiver mode: If RxNE=1 and BTF=1: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register (both buffer and shift register are full).

• If clock stretching is disabled in Slave mode:

– Overrun Error in case of RxNE=1 and no read of DR has been done before the next byte is received. The last received byte is lost.

– Underrun Error in case TxE=1 and no write into DR has been done before the next byte must be transmitted. The same byte will be sent again.

– Write Collision not managed.

18.3.7 SMBus

Introduction

The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on I

C principles of operation. SMBus provides a control bus for system and power management related tasks. A system may use SMBus to pass messages to and from devices instead of toggling individual control lines.

The System Management Bus Specification refers to three types of devices. A slave is a device that is receiving or responding to a command. A master is a device that issues commands, generates the clocks, and terminates the transfer. A host is a specialized master that provides the main interface to the system's CPU. A host must be a master-slave and must support the SMBus host notify protocol. Only one host is allowed in a system.

Similarities between SMBus and I

C

• 2-wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional

• Master-slave communication, Master provides clock

• Multi master capability

• SMBus data format similar to I 2 C 7-bit addressing format (

Figure 160

Differences between SMBus and I

C

The following table describes the differences between SMBus and I 2 C.

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Table 70. SMBus vs. I 2 C

SMBus I

Max. speed 100 kHz

Min. clock speed 10 kHz

Max. speed 400 kHz

No minimum clock speed

35 ms clock low timeout No timeout

Logic levels are fixed Logic levels are V

dependent

Different address types (reserved, dynamic etc.) 7-bit, 10-bit and general call slave address types

Different bus protocols (quick command, process call etc.)

No bus protocols

SMBus application usage

With System Management Bus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status. SMBus provides a control bus for system and power management related tasks.

Device identification

Any device that exists on the System Management Bus as a slave has a unique address called the Slave Address. For the list of reserved slave addresses, refer to the SMBus specification version. 2.0 ( http://smbus.org/ ).

Bus protocols

The SMBus specification supports up to nine bus protocols. For more details of these protocols and SMBus address types, refer to SMBus specification version. 2.0. These protocols should be implemented by the user software.

Address resolution protocol (ARP)

SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device. The Address Resolution Protocol (ARP) has the following attributes:

• Address assignment uses the standard SMBus physical layer arbitration mechanism

• Assigned addresses remain constant while device power is applied; address retention through device power loss is also allowed

• No additional SMBus packet overhead is incurred after address assignment. (i.e. subsequent accesses to assigned slave addresses have the same overhead as accesses to fixed address devices.)

• Any SMBus master can enumerate the bus

Unique device identifier (UDID)

In order to provide a mechanism to isolate each device for the purpose of address assignment, each device must implement a unique device identifier (UDID).

For the details on 128-bit UDID and more information on ARP, refer to SMBus specification version 2.0.

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SMBus alert mode

SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are.

SMBA is used in conjunction with the SMBus General Call Address. Messages invoked with the SMBus are two bytes long.

A slave-only device can signal the host through SMBA that it wants to talk by setting ALERT bit in I2C_CR1 register. The host processes the interrupt and simultaneously accesses all

SMBA devices through the Alert Response Address (known as ARA having a value 0001

100X). Only the device(s) which pulled SMBA low will acknowledge the Alert Response

Address. This status is identified using SMBALERT Status flag in I2C_SR1 register. The host performs a modified Receive Byte operation. The 7 bit device address provided by the slave transmit device is placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one.

If more than one device pulls SMBA low, the highest priority (lowest address) device will win communication rights via standard arbitration during the slave address transfer. After acknowledging the slave address the device must disengage its SMBA pull-down. If the host still sees SMBA low when the message transfer is complete, it knows to read the ARA again.

A host which does not implement the SMBA signal may periodically access the ARA.

For more details on SMBus Alert mode, refer to SMBus specification version 2.0.

Timeout error

There are differences in the timing specifications between I 2 C and SMBus.

SMBus defines a clock low timeout, TIMEOUT of 35 ms. Also SMBus specifies TLOW:

SEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW:

MEXT as the cumulative clock low extend time for a master device. For more details on these timeouts, refer to SMBus specification version 2.0.

The status flag Timeout or Tlow Error in I2C_SR1 shows the status of this feature.

How to use the interface in SMBus mode

To switch from I 2 C mode to SMBus mode, the following sequence should be performed.

• Set the SMBus bit in the I2C_CR1 register

• Configure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the application

If you want to configure the device as a master, follow the Start condition generation

procedure in Section 18.3.3

. Otherwise, follow the sequence in

Section 18.3.2

The application has to control the various SMBus protocols by software.

• SMB Device Default Address acknowledged if ENARP=1 and SMBTYPE=0

• SMB Host Header acknowledged if ENARP=1 and SMBTYPE=1

• SMB Alert Response Address acknowledged if SMBALERT=1

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Note:

DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. The DMA must be initialized and enabled before the I2C data transfer. The

DMAEN bit must be set in the I2C_CR2 register before the ADDR event. In master mode or in slave mode when clock stretching is enabled, the DMAEN bit can also be set during the

ADDR event, before clearing the ADDR flag. The DMA request must be served before the end of the current byte transfer. When the number of data transfers which has been programmed for the corresponding DMA stream is reached, the DMA controller sends an

End of Transfer EOT signal to the I

C interface and generates a Transfer Complete interrupt if enabled:

• Master transmitter: In the interrupt routine after the EOT interrupt, disable DMA requests then wait for a BTF event before programming the Stop condition.

• Master receiver

– When the number of bytes to be received is equal to or greater than two, the DMA controller sends a hardware signal, EOT_1, corresponding to the last but one data byte (number_of_bytes – 1). If, in the I2C_CR2 register, the LAST bit is set, I 2 C automatically sends a NACK after the next byte following EOT_1. The user can generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.

– When a single byte must be received: the NACK must be programmed during EV6 event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag. Then the user can program the STOP condition either after clearing ADDR flag, or in the

DMA Transfer Complete interrupt routine.

Transmission using DMA

DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2 register. Data will be loaded from a Memory area configured using the DMA peripheral (refer to the DMA specification) to the I2C_DR register whenever the TxE bit is set. To map a DMA stream x for I

C transmission (where x is the stream number), perform the following sequence:

Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved to this address from the memory after each TxE event.

2. Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register in the case of a bouble buffer mode). The data will be loaded into I2C_DR from this memory after each TxE event.

3. Configure the total number of bytes to be transferred in the DMA_SxNDTR register.

After each TxE event, this value will be decremented.

4. Configure the DMA stream priority using the PL[0:1] bits in the DMA_SxCR register

5. Set the DIR bit in the DMA_SxCR register and configure interrupts after half transfer or full transfer depending on application requirements.

6. Activate the stream by setting the EN bit in the DMA_SxCR register.

When the number of data transfers which has been programmed in the DMA Controller

I registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the

C interface and the DMA generates an interrupt, if enabled, on the DMA stream interrupt vector.

Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.

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Note:

Reception using DMA

DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.

Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA stream x for I 2 C reception (where x is the stream number), perform the following sequence:

Set the I2C_DR register address in DMA_SxPAR register. The data will be moved from this address to the memory after each RxNE event.

2. Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register in the case of a bouble buffer mode). The data will be loaded from the I2C_DR register to this memory area after each RxNE event.

3. Configure the total number of bytes to be transferred in the DMA_SxNDTR register.

After each RxNE event, this value will be decremented.

4. Configure the stream priority using the PL[0:1] bits in the DMA_SxCR register

5. Reset the DIR bit and configure interrupts in the DMA_SxCR register after half transfer or full transfer depending on application requirements.

6. Activate the stream by setting the EN bit in the DMA_SxCR register.

When the number of data transfers which has been programmed in the DMA Controller

I registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the

2 C interface and DMA generates an interrupt, if enabled, on the DMA stream interrupt vector.

Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.

18.3.9 Packet error checking

A PEC calculator has been implemented to improve the reliability of communication. The

PEC is calculated by using the C(x) = x

+ x

+ x + 1 CRC-8 polynomial serially on each bit.

• PEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a

CRC-8 calculated on all message bytes including addresses and R/W bits.

– In transmission: set the PEC transfer bit in the I2C_CR1 register after the TxE event corresponding to the last byte. The PEC will be transferred after the last transmitted byte.

– In reception: set the PEC bit in the I2C_CR1 register after the RxNE event corresponding to the last byte so that the receiver sends a NACK if the next received byte is not equal to the internally calculated PEC. In case of Master-

Receiver, a NACK must follow the PEC whatever the check result. The PEC must

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• A PECERR error flag/interrupt is also available in the I2C_SR1 register.

• If DMA and PEC calculation are both enabled:-

– In transmission: when the I

C interface receives an EOT signal from the DMA controller, it automatically sends a PEC after the last byte.

– In reception: when the I 2 C interface receives an EOT_1 signal from the DMA controller, it will automatically consider the next byte as a PEC and will check it. A

DMA request is generated after PEC reception.

• To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register

(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA request for a master receiver, a NACK is automatically sent after the last received byte.

• PEC calculation is corrupted by an arbitration loss.

18.4 I

2 C interrupts

The table below gives the list of I

C interrupt requests.

Table 71. I

C Interrupt requests

Interrupt event Event flag

Start bit sent (Master)

Address sent (Master) or Address matched (Slave)

10-bit header sent (Master)

Stop received (Slave)

Data byte transfer finished

Receive buffer not empty

Transmit buffer empty

Bus error

Arbitration loss (Master)

Acknowledge failure

Overrun/Underrun

PEC error

Timeout/Tlow error

SMBus Alert

ADDR

ADD10

STOPF

BTF

RxNE

TxE

BERR

ARLO

OVR

PECERR

TIMEOUT

SMBALERT

Enable control bit

ITEVFEN

ITEVFEN and ITBUFEN

ITERREN

Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically OR-ed on the same interrupt channel.

BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically OR-ed on the same interrupt channel.

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Figure 166. I 2 C interrupt mapping diagram

ITEVFEN

ADDR

ADD10

STOPF

BTF

TxE

ITBUFEN

RxNE

ITERREN

BERR

ARLO

OVR

PECERR

TIMEOUT

SMBALERT it_event it_error

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18.5 I

2 C debug mode

When the microcontroller enters the debug mode (Cortex

-M4 with FPU core halted), the

SMBUS timeout either continues to work normally or stops, depending on the

DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to

Section 23.16.2: Debug support for timers, watchdog and I2C

18.6 I 2 C registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).

18.6.1 I

C Control register 1 (I2C_CR1)

15 14

SWRST

Res.

Address offset: 0x00

Reset value: 0x0000

13 12 11 10

ALERT PEC POS rw rw rw

ACK STOP START rw

9 rw

8 rw

STRETCH rw

ENGC ENPEC ENARP rw

5 rw

4 rw

SMB

TYPE rw

Res.

SMBU

S rw

PE rw

Bit 15 SWRST : Software reset

When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are released and the bus is free.

0: I

1: I

C Peripheral not under reset

C Peripheral under reset state

Note: This bit can be used to reinitialize the peripheral after an error or a locked state. As an example, if the BUSY bit is set and remains locked due to a glitch on the bus, the

SWRST bit can be used to exit from this state.

Bit 14 Reserved, must be kept at reset value

Bit 13 ALERT : SMBus alert

This bit is set and cleared by software, and cleared by hardware when PE=0.

0: Releases SMBA pin high. Alert Response Address Header followed by NACK.

1: Drives SMBA pin low. Alert Response Address Header followed by ACK.

Bit 12 PEC : Packet error checking

This bit is set and cleared by software, and cleared by hardware when PEC is transferred or by a START or Stop condition or when PE=0.

0: No PEC transfer

1: PEC transfer (in Tx or Rx mode)

Note: PEC calculation is corrupted by an arbitration loss.

Bit 11 POS : Acknowledge/PEC Position (for data reception)

This bit is set and cleared by software and cleared by hardware when PE=0.

0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The

PEC bit indicates that current byte in shift register is a PEC.

1: ACK bit controls the (N)ACK of the next byte which will be received in the shift register.

The PEC bit indicates that the next byte in the shift register is a PEC

Note: The POS bit must be used only in 2-byte reception configuration in master mode. It must be configured before data reception starts, as described in the 2-byte reception

procedure recommended in Section : Master receiver on page 482 .

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Bit 10 ACK : Acknowledge enable

This bit is set and cleared by software and cleared by hardware when PE=0.

0: No acknowledge returned

1: Acknowledge returned after a byte is received (matched address or data)

Bit 9 STOP : Stop generation

The bit is set and cleared by software, cleared by hardware when a Stop condition is detected, set by hardware when a timeout error is detected.

In Master Mode:

0: No Stop generation.

1: Stop generation after the current byte transfer or after the current Start condition is sent.

In Slave mode:

0: No Stop generation.

1: Release the SCL and SDA lines after the current byte transfer.

Bit 8 START : Start generation

This bit is set and cleared by software and cleared by hardware when start is sent or PE=0.

In Master Mode:

0: No Start generation

1: Repeated start generation

In Slave mode:

0: No Start generation

1: Start generation when the bus is free

Bit 7 NOSTRETCH : Clock stretching disable (Slave mode)

This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until it is reset by software.

0: Clock stretching enabled

1: Clock stretching disabled

Bit 6 ENGC : General call enable

0: General call disabled. Address 00h is NACKed.

1: General call enabled. Address 00h is ACKed.

Bit 5 ENPEC: PEC enable

0: PEC calculation disabled

1: PEC calculation enabled

Bit 4 ENARP : ARP enable

0: ARP disable

1: ARP enable

SMBus Device default address recognized if SMBTYPE=0

SMBus Host address recognized if SMBTYPE=1

Bit 3 SMBTYPE : SMBus type

0: SMBus Device

1: SMBus Host

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Bit 2 Reserved, must be kept at reset value

Bit 1 SMBUS : SMBus mode

0: I 2 C mode

1: SMBus mode

Bit 0 PE : Peripheral enable

0: Peripheral disable

1: Peripheral enable

Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.

All bit resets due to PE=0 occur at the end of the communication.

In master mode, this bit must not be reset before the end of the communication.

Note: When the STOP, START or PEC bit is set, the software must not perform any write access to I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of setting a second STOP, START or PEC request.

18.6.2 I

C Control register 2 (I2C_CR2)

15 14

Address offset: 0x04

Reset value: 0x0000

13 12 11 10 9 8

Reserved

LAST DMAEN ITBUFEN ITEVTEN ITERREN rw rw rw rw rw

7 6

Reserved

5 4 3 2

FREQ[5:0] rw rw

1 0 rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value

Bit 12 LAST : DMA last transfer

0: Next DMA EOT is not the last transfer

1: Next DMA EOT is the last transfer

Note: This bit is used in master receiver mode to permit the generation of a NACK on the last received data.

Bit 11 DMAEN : DMA requests enable

0: DMA requests disabled

1: DMA request enabled when TxE=1 or RxNE =1

Bit 10 ITBUFEN : Buffer interrupt enable

0: TxE = 1 or RxNE = 1 does not generate any interrupt.

1: TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)

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Bit 9 ITEVTEN : Event interrupt enable

0: Event interrupt disabled

1: Event interrupt enabled

This interrupt is generated when:

– SB = 1 (Master)

– ADDR = 1 (Master/Slave)

– ADD10= 1 (Master)

– STOPF = 1 (Slave)

– BTF = 1 with no TxE or RxNE event

– TxE event to 1 if ITBUFEN = 1

– RxNE event to 1if ITBUFEN = 1

Bit 8 ITERREN : Error interrupt enable

0: Error interrupt disabled

1: Error interrupt enabled

This interrupt is generated when:

– BERR = 1

– ARLO = 1

– AF = 1

– OVR = 1

– PECERR = 1

– TIMEOUT = 1

– SMBALERT = 1

Bits 7:6 Reserved, must be kept at reset value

Bits 5:0 FREQ[5:0] : Peripheral clock frequency

The FREQ bits must be configured with the APB clock frequency value (I2C peripheral connected to APB). The FREQ field is used by the peripheral to generate data setup and hold times compliant with the I2C specifications. The minimum allowed frequency is 2 MHz, the maximum frequency is limited by the maximum APB1 frequency and cannot exceed

50 MHz (peripheral intrinsic maximum limit).

0b000000: Not allowed

0b000001: Not allowed

0b000010: 2 MHz

...

0b110010: 50 MHz

Higher than 0b100100: Not allowed

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18.6.3 I

C Own address register 1 (I2C_OAR1)

Address offset: 0x08

Reset value: 0x0000

13 12 11 10 9 8 7 6 15

ADD

MODE rw

Reserved

ADD[9:8] rw rw rw rw

5 4

ADD[7:1] rw rw

Bit 15 ADDMODE Addressing mode (slave mode)

0: 7-bit slave address (10-bit address not acknowledged)

1: 10-bit slave address (7-bit address not acknowledged)

Bit 14 Should always be kept at 1 by software.

Bits 13:10 Reserved, must be kept at reset value

Bits 9:8 ADD[9:8] : Interface address

7-bit addressing mode: don’t care

10-bit addressing mode: bits9:8 of address

Bits 7:1 ADD[7:1] : Interface address bits 7:1 of address

Bit 0 ADD0 : Interface address

7-bit addressing mode: don’t care

10-bit addressing mode: bit 0 of address

3 rw

2 rw

1 rw

ADD0 rw

18.6.4 I 2 C Own address register 2 (I2C_OAR2)

15 14

Address offset: 0x0C

Reset value: 0x0000

13 12 11 10 9 8 7 6

Reserved rw rw

5 rw

ADD2[7:1] rw

3 rw

Bits 15:8 Reserved, must be kept at reset value

Bits 7:1 ADD2[7:1] : Interface address bits 7:1 of address in dual addressing mode

Bit 0 ENDUAL : Dual addressing mode enable

0: Only OAR1 is recognized in 7-bit addressing mode

1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode

2 rw

1 rw

ENDUAL rw

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18.6.5 I

C Data register (I2C_DR)

15 14

Address offset: 0x10

Reset value: 0x0000

13 12 11 10 9 8

Reserved

7 rw

6 rw

5 rw

4 3

DR[7:0] rw rw

2 rw

1 rw

0 rw

Bits 15:8 Reserved, must be kept at reset value

Bits 7:0 DR[7:0] 8-bit data register

Byte received or to be transmitted to the bus.

– Transmitter mode: Byte transmission starts automatically when a byte is written in the DR register. A continuous transmit stream can be maintained if the next data to be transmitted is put in DR once the transmission is started (TxE=1)

– Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream can be maintained if DR is read before the next data byte is received (RxNE=1).

Note: In slave mode, the address is not copied into DR.

Write collision is not managed (DR can be written if TxE=0).

If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so cannot be read.

18.6.6 I

C Status register 1 (I2C_SR1)

SMB

ALERT

TIME

OUT rc_w0 rc_w0

Address offset: 0x14

Reset value: 0x0000

Res.

PEC

ERR

OVR

9 8

ARLO BERR rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

TxE r

RxNE r

Res.

4 3 2

STOPF ADD10 BTF r r r

ADDR r

Bit 15 SMBALERT : SMBus alert

In SMBus host mode:

0: no SMBALERT

1: SMBALERT event occurred on pin

In SMBus slave mode:

0: no SMBALERT response address header

1: SMBALERT response address header to SMBALERT LOW received

– Cleared by software writing 0, or by hardware when PE=0.

SB r

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Bit 14 TIMEOUT : Timeout or Tlow error

0: No timeout error

1: SCL remained LOW for 25 ms (Timeout) or

Master cumulative clock low extend time more than 10 ms (Tlow:mext) or

Slave cumulative clock low extend time more than 25 ms (Tlow:sext)

– When set in slave mode: slave resets the communication and lines are released by hardware

– When set in master mode: Stop condition sent by hardware

– Cleared by software writing 0, or by hardware when PE=0.

Note: This functionality is available only in SMBus mode.

Bit 13 Reserved, must be kept at reset value

Bit 12 PECERR : PEC Error in reception

0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)

1: PEC error: receiver returns NACK after PEC reception (whatever ACK)

– Cleared by software writing 0, or by hardware when PE=0.

Note: When the received CRC is wrong, PECERR is not set in slave mode if the PEC control bit is not set before the end of the CRC reception. Nevertheless, reading the PEC value determines whether the received CRC is right or wrong.

Bit 11 OVR : Overrun/Underrun

0: No overrun/underrun

1: Overrun or underrun

– Set by hardware in slave mode when NOSTRETCH=1 and:

– In reception when a new byte is received (including ACK pulse) and the DR register has not been read yet. New received byte is lost.

– In transmission when a new byte should be sent and the DR register has not been written yet. The same byte is sent twice.

– Cleared by software writing 0, or by hardware when PE=0.

Note: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a hold timing error occurs

Bit 10 AF : Acknowledge failure

0: No acknowledge failure

1: Acknowledge failure

– Set by hardware when no acknowledge is returned.

– Cleared by software writing 0, or by hardware when PE=0.

Bit 9 ARLO : Arbitration lost (master mode)

0: No Arbitration Lost detected

1: Arbitration Lost detected

Set by hardware when the interface loses the arbitration of the bus to another master

– Cleared by software writing 0, or by hardware when PE=0.

After an ARLO event the interface switches back automatically to Slave mode (MSL=0).

Note: In SMBUS, the arbitration on the data in slave mode occurs only during the data phase, or the acknowledge transmission (not on the address acknowledge).

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Bit 8 BERR : Bus error

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

– Set by hardware when the interface detects an SDA rising or falling edge while SCL is high, occurring in a non-valid position during a byte transfer.

– Cleared by software writing 0, or by hardware when PE=0.

Bit 7 TxE : Data register empty (transmitters)

0: Data register not empty

1: Data register empty

– Set when DR is empty in transmission. TxE is not set during address phase.

– Cleared by software writing to the DR register or by hardware after a start or a stop condition or when PE=0.

TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)

Note: TxE is not cleared by writing the first data being transmitted, or by writing data when

BTF is set, as in both cases the data register is still empty.

Bit 6 RxNE : Data register not empty (receivers)

0: Data register empty

1: Data register not empty

– Set when data register is not empty in receiver mode. RxNE is not set during address phase.

– Cleared by software reading or writing the DR register or by hardware when PE=0.

RxNE is not set in case of ARLO event.

Note: RxNE is not cleared by reading data when BTF is set, as the data register is still full.

Bit 5 Reserved, must be kept at reset value

Bit 4 STOPF : Stop detection (slave mode)

0: No Stop condition detected

1: Stop condition detected

– Set by hardware when a Stop condition is detected on the bus by the slave after an acknowledge (if ACK=1).

– Cleared by software reading the SR1 register followed by a write in the CR1 register, or by hardware when PE=0

Note: The STOPF bit is not set after a NACK reception.

It is recommended to perform the complete clearing sequence (READ SR1 then

WRITE CR1) after the STOPF is set. Refer to

Figure 163 .

Bit 3 ADD10 : 10-bit header sent (Master mode)

0: No ADD10 event occurred.

1: Master has sent first address byte (header).

– Set by hardware when the master has sent the first byte in 10-bit address mode.

– Cleared by software reading the SR1 register followed by a write in the DR register of the second address byte, or by hardware when PE=0.

Note: ADD10 bit is not set after a NACK reception

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RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

Bit 2 BTF : Byte transfer finished

0: Data byte transfer not done

1: Data byte transfer succeeded

– Set by hardware when NOSTRETCH=0 and:

– In reception when a new byte is received (including ACK pulse) and DR has not been read yet (RxNE=1).

– In transmission when a new byte should be sent and DR has not been written yet (TxE=1).

– Cleared by software by either a read or write in the DR register or by hardware after a start or a stop condition in transmission or when PE=0.

Note: The BTF bit is not set after a NACK reception

The BTF bit is not set if next byte to be transmitted is the PEC (TRA=1 in I2C_SR2 register and PEC=1 in I2C_CR1 register)

Bit 1 ADDR : Address sent (master mode)/matched (slave mode)

This bit is cleared by software reading SR1 register followed reading SR2, or by hardware when PE=0.

Address matched (Slave)

0: Address mismatched or not received.

1: Received address matched.

– Set by hardware as soon as the received slave address matched with the OAR registers content or a general call or a SMBus Device Default Address or SMBus Host or SMBus Alert is recognized. (when enabled depending on configuration).

Note: In slave mode, it is recommended to perform the complete clearing sequence (READ

SR1 then READ SR2) after ADDR is set. Refer to

Figure 163

Address sent (Master)

0: No end of address transmission

1: End of address transmission

– For 10-bit addressing, the bit is set after the ACK of the 2nd byte.

– For 7-bit addressing, the bit is set after the ACK of the byte.

Note: ADDR is not set after a NACK reception

Bit 0 SB : Start bit (Master mode)

0: No Start condition

1: Start condition generated.

– Set when a Start condition generated.

– Cleared by software by reading the SR1 register followed by writing the DR register, or by hardware when PE=0

18.6.7 I

C Status register 2 (I2C_SR2)

Note:

Address offset: 0x18

Reset value: 0x0000

Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.

15 14 13 10 9 8 r r r

12 11

PEC[7:0] r r r r r

DUALF r

SMB

HOST r

SMBDE

FAULT r

GEN

CALL r

Res.

TRA r

BUSY r

MSL r

RM0368 Rev 5

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505

Inter-integrated circuit (I2C) interface RM0368

Note:

Bits 15:8 PEC[7:0] Packet error checking register

This register contains the internal PEC when ENPEC=1.

Bit 7 DUALF : Dual flag (Slave mode)

0: Received address matched with OAR1

1: Received address matched with OAR2

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 6 SMBHOST : SMBus host header (Slave mode)

0: No SMBus Host address

1: SMBus Host address received when SMBTYPE=1 and ENARP=1.

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 5 SMBDEFAULT : SMBus device default address (Slave mode)

0: No SMBus Device Default address

1: SMBus Device Default address received when ENARP=1

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 4 GENCALL : General call address (Slave mode)

0: No General Call

1: General Call Address received when ENGC=1

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 3 Reserved, must be kept at reset value

Bit 2 TRA : Transmitter/receiver

0: Data bytes received

1: Data bytes transmitted

This bit is set depending on the R/W bit of the address byte, at the end of total address phase.

It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.

Bit 1 BUSY : Bus busy

0: No communication on the bus

1: Communication ongoing on the bus

– Set by hardware on detection of SDA or SCL low

– cleared by hardware on detection of a Stop condition.

It indicates a communication in progress on the bus. This information is still updated when the interface is disabled (PE=0).

Bit 0 MSL : Master/slave

0: Slave Mode

1: Master Mode

– Set by hardware as soon as the interface is in Master mode (SB=1).

– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration

(ARLO=1), or by hardware when PE=0.

502/847

RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

18.6.8 I

C Clock control register (I2C_CCR)

Note:

Address offset: 0x1C

Reset value: 0x0000 f

PCLK1

must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4

MHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the

400 kHz maximum I²C Fm mode clock.

The CCR register must be configured only when the I2C is disabled (PE = 0).

F/S rw

DUTY rw

13 12

Reserved

11 rw

10 rw

9 rw

8 rw

7 rw

6 5

CCR[11:0] rw rw

4 rw

3 rw

2 rw

1 rw

0 rw

Bit 15 F/S: I2C master mode selection

0: Sm mode I2C

1: Fm mode I2C

Bit 14 DUTY: Fm mode duty cycle

0: Fm mode t low

/t high

1: Fm mode t low

/t high

= 2

= 16/9 (see CCR)

Bits 13:12 Reserved, must be kept at reset value

Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)

Controls the SCL clock in master mode.

Sm mode or SMBus:

T high

= CCR * T

PCLK1

T low

= CCR * T

PCLK1

Fm mode:

If DUTY = 0:

T high

= CCR * T

PCLK1

T low

= 2 * CCR * T

PCLK1

If DUTY = 1: (to reach 400 kHz)

T high

= 9 * CCR * T

PCLK1

T low

= 16 * CCR * T

PCLK1

For instance: in Sm mode, to generate a 100 kHz SCL frequency:

If FREQR = 08, T

PCLK1

= 125 ns so CCR must be programmed with 0x28

(0x28 <=> 40d x 125 ns = 5000 ns.)

Note: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum allowed value is 0x01 t high t low

= t r(SCL)

= t f(SCL)

+ t w(SCLH)

+ t w(SCLL)

. See device datasheet for the definitions of parameters.

I2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to the analog noise filter input delay.

The CCR register must be configured only when the I

C is disabled (PE = 0).

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Inter-integrated circuit (I2C) interface RM0368

18.6.9 I

C TRISE register (I2C_TRISE)

15 14

Address offset: 0x20

Reset value: 0x0002

13 12 11 10 9 8 7

Reserved

6 5 rw

4 rw

3 2

TRISE[5:0] rw rw

1 rw

0 rw

Bits 15:6 Reserved, must be kept at reset value

Bits 5:0 TRISE[5:0] : Maximum rise time in Fm/Sm mode (Master mode)

These bits should provide the maximum duration of the SCL feedback loop in master mode.

The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.

These bits must be programmed with the maximum SCL rise time given in the I

C bus specification, incremented by 1.

For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.

If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T

PCLK1

= 125 ns therefore the TRISE[5:0] bits must be programmed with 09h.

(1000 ns / 125 ns = 8 + 1)

The filter value can also be added to TRISE[5:0].

If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order to respect the t

HIGH

parameter.

Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).

18.6.10 I

C FLTR register (I2C_FLTR)

Address offset: 0x24

Reset value: 0x0000

15 14 13 12 11 10

Reserved

9 8 7 6 5 4

ANOFF rw

3 rw

2 1

DNF[3:0] rw rw

0 rw

Bits 15:5 Reserved, must be kept at reset value

Bit 4 ANOFF : Analog noise filter OFF

0: Analog noise filter enable

1: Analog noise filter disable

Note: ANOFF must be configured only when the I2C is disabled (PE = 0).

Bits 3:0 DNF[3:0] : Digital noise filter

These bits are used to configure the digital noise filter on SDA and SCL inputs. The digital filter will suppress the spikes with a length of up to DNF[3:0] * TPCLK1.

0000: Digital noise filter disable

0001: Digital noise filter enabled and filtering capability up to 1* TPCLK1.

...

1111: Digital noise filter enabled and filtering capability up to 15* TPCLK1.

Note: DNF[3:0] must be configured only when the I2C is disabled (PE = 0). If the analog filter is also enabled, the digital filter is added to the analog filter.

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RM0368 Rev 5

RM0368 Inter-integrated circuit (I2C) interface

18.6.11 I

C register map

The table below provides the I 2 C register map and reset values.

Table 72. I 2 C register map and reset values

Offset Register

I2C_CR1

0x00

0x04

0x08

0x0C

0x10

0x14

Reset value

I2C_CR2

Reset value

I2C_OAR1

Reset value

I2C_OAR2

Reset value

I2C_DR

Reset value

I2C_SR1

Reset value

Reserved

0 0 0 0 0 0 0 0 0 0 0 0

FREQ[5:0]

0 0

0 0 0 0 0 0 0 0 0 0 0

Reserved

ADD[9:8] ADD[7:1]

0 0 0 0 0 0 0 0 0 0

ADD2[7:1]

0 0 0 0 0 0 0 0

DR[7:0]

0 0 0 0 0 0 0 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x18

0x1C

0x20

0x24

I2C_SR2 PEC[7:0]

Reserved

Reset value

I2C_CCR

Reset value

I2C_TRISE

Reset value

I2C_FLTR

Reset value

Reserved

0 0 0 0 0 0 0

0 0 0 0 0

CCR[11:0]

0 0 0

0 0 0 0 0 0 0 0 0

TRISE[5:0]

0 0 0 0 1 0

DNF[3:0]

0 0 0 0 0

Refer to Section 3.3: Memory map for the register boundary addresses table.

RM0368 Rev 5

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505

Universal synchronous asynchronous receiver transmitter (USART)

19 Universal synchronous asynchronous receiver transmitter (USART)

RM0368

The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard

NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate generator.

It supports synchronous one-way communication and half-duplex single wire communication. It also supports the LIN (local interconnection network), Smartcard Protocol and IrDA (infrared data association) SIR ENDEC specifications, and modem operations

(CTS/RTS). It allows multiprocessor communication.

High speed data communication is possible by using the DMA for multibuffer configuration.

19.2 USART main features

• Full duplex, asynchronous communications

• NRZ standard format (Mark/Space)

• Configurable oversampling method by 16 or by 8 to give flexibility between speed and clock tolerance

• Fractional baud rate generator systems

– Common programmable transmit and receive baud rate (refer to the datasheets for the value of the baud rate at the maximum APB frequency.

• Programmable data word length (8 or 9 bits)

• Configurable stop bits - support for 1 or 2 stop bits

• LIN Master Synchronous Break send capability and LIN slave break detection capability

– 13-bit break generation and 10/11 bit break detection when USART is hardware configured for LIN

• Transmitter clock output for synchronous transmission

• IrDA SIR encoder decoder

– Support for 3/16 bit duration for normal mode

• Smartcard emulation capability

– The Smartcard interface supports the asynchronous protocol Smartcards as defined in the ISO 7816-3 standards

– 0.5, 1.5 stop bits for Smartcard operation

• Single-wire half-duplex communication

• Configurable multibuffer communication using DMA (direct memory access)

– Buffering of received/transmitted bytes in reserved SRAM using centralized DMA

• Separate enable bits for transmitter and receiver

• Transfer detection flags:

– Receive buffer full

506/847

RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

– Transmit buffer empty

– End of transmission flags

• Parity control:

– Transmits parity bit

– Checks parity of received data byte

• Four error detection flags:

– Overrun error

– Noise detection

– Frame error

– Parity error

• Ten interrupt sources with flags:

– CTS changes

– LIN break detection

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error

– Framing error

– Noise error

– Parity error

• Multiprocessor communication - enter into mute mode if address match does not occur

• Wake up from mute mode (by idle line detection or address mark detection)

• Two receiver wakeup modes: Address bit (MSB, 9 th

bit), Idle line

19.3 USART functional description

The interface is externally connected to another device by three pins (see

Figure 167

). Any

USART bidirectional communication requires a minimum of two pins: Receive Data In (RX) and Transmit Data Out (TX):

RX: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

TX: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high level. In single-wire and smartcard modes, this I/O is used to transmit and receive the data (at USART level, data are then received on SW_RX).

RM0368 Rev 5

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558

Universal synchronous asynchronous receiver transmitter (USART) RM0368

Through these pins, serial data is transmitted and received in normal USART mode as frames comprising:

• An Idle Line prior to transmission or reception

• A start bit

• A data word (8 or 9 bits) least significant bit first

• 0.5,1, 1.5, 2 Stop bits indicating that the frame is complete

• This interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit fraction

• A status register (USART_SR)

• Data Register (USART_DR)

• A baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.

• A Guardtime Register (USART_GTPR) in case of Smartcard mode.

Refer to Section 19.6: USART registers on page 548 for the definitions of each bit.

The following pin is required to interface in synchronous mode:

• CK: Transmitter clock output. This pin outputs the transmitter data clock for synchronous transmission corresponding to SPI master mode (no clock pulses on start bit and stop bit, and a software option to send a clock pulse on the last data bit). In parallel data can be received synchronously on RX. This can be used to control peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity are software programmable. In smartcard mode, CK can provide the clock to the smartcard.

The following pins are required in Hardware flow control mode:

• CTS: Clear To Send blocks the data transmission at the end of the current transfer when high

• RTS: Request to send indicates that the USART is ready to receive a data (when low).

508/847

RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Figure 167. USART block diagram

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

Word length may be selected as being either 8 or 9 bits by programming the M bit in the

USART_CR1 register (see Figure 168

The TX pin is in low state during the start bit. It is in high state during the stop bit.

An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1” ‘s will include the number of stop bits).

A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the start bit.

Transmission and reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter and receiver.

The details of each block is given below.

Figure 168. Word length programming

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510/847

RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

19.3.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status.

When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.

Note:

Character transmission

During an USART transmission, data shifts out least significant bit first on the TX pin. In this mode, the USART_DR register consists of a buffer (TDR) between the internal bus and the

transmit shift register (see Figure 167

Every character is preceded by a start bit which is a logic level low for one bit period. The character is terminated by a configurable number of stop bits.

The following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.

The TE bit should not be reset during transmission of data. Resetting the TE bit during the transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.

The current data being transmitted will be lost.

An idle frame will be sent after the TE bit is enabled.

Configurable stop bits

The number of stop bits to be transmitted with every character can be programmed in

Control register 2, bits 13,12.

• 1 stop bit : This is the default value of number of stop bits.

• 2 Stop bits : This will be supported by normal USART, single-wire and modem modes.

• 0.5 stop bit : To be used when receiving data in Smartcard mode.

• 1.5 stop bits : To be used when transmitting and receiving data in Smartcard mode.

An idle frame transmission will include the stop bits.

A break transmission will be 10 low bits followed by the configured number of stop bits

(when m = 0) and 11 low bits followed by the configured number of stop bits (when m = 1). It is not possible to transmit long breaks (break of length greater than 10/11 low bits).

RM0368 Rev 5

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558

Universal synchronous asynchronous receiver transmitter (USART) RM0368

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Figure 169. Configurable stop bits

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Procedure:

Enable the USART by writing the UE bit in USART_CR1 register to 1.

2. Program the M bit in USART_CR1 to define the word length.

3. Program the number of stop bits in USART_CR2.

4. Select DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take place. Configure the DMA register as explained in multibuffer communication.

5. Select the desired baud rate using the USART_BRR register.

6. Set the TE bit in USART_CR1 to send an idle frame as first transmission.

7. Write the data to send in the USART_DR register (this clears the TXE bit). Repeat this for each data to be transmitted in case of single buffer.

8. After writing the last data into the USART_DR register, wait until TC=1. This indicates that the transmission of the last frame is complete. This is required for instance when the USART is disabled or enters the Halt mode to avoid corrupting the last transmission.

Single byte communication

Clearing the TXE bit is always performed by a write to the data register.

The TXE bit is set by hardware and it indicates:

• The data has been moved from TDR to the shift register and the data transmission has started.

• The TDR register is empty.

• The next data can be written in the USART_DR register without overwriting the previous data.

This flag generates an interrupt if the TXEIE bit is set.

512/847

RM0368 Rev 5

RM0368

Note:

Universal synchronous asynchronous receiver transmitter (USART)

When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is taking place, a write instruction to the USART_DR register places the data directly in the shift register, the data transmission starts, and the TXE bit is immediately set.

If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the USART_CR1 register.

After writing the last data into the USART_DR register, it is mandatory to wait for TC=1 before disabling the USART or causing the microcontroller to enter the low-power mode

(see Figure 170: TC/TXE behavior when transmitting ).

The TC bit is cleared by the following software sequence:

A read from the USART_SR register

2. A write to the USART_DR register

The TC bit can also be cleared by writing a ‘0 to it. This clearing sequence is recommended only for Multibuffer communication.

Figure 170. TC/TXE behavior when transmitting

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Break characters

Setting the SBK bit transmits a break character. The break frame length depends on the M

bit (see Figure 168 ).

If the SBK bit is set to ‘1 a break character is sent on the TX line after completing the current character transmission. This bit is reset by hardware when the break character is completed

(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.

If the software resets the SBK bit before the commencement of break transmission, the break character will not be transmitted. For two consecutive breaks, the SBK bit should be set after the stop bit of the previous break.

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

Idle characters

Setting the TE bit drives the USART to send an idle frame before the first data frame.

19.3.3 Receiver

The USART can receive data words of either 8 or 9 bits depending on the M bit in the

USART_CR1 register.

Start bit detection

The start bit detection sequence is the same when oversampling by 16 or by 8.

In the USART, the start bit is detected when a specific sequence of samples is recognized.

This sequence is: 1 1 1 0 X 0 X 0 X 0 0 0 0.

Figure 171. Start bit detection when oversampling by 16 or 8

Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the idle state (no flag is set) where it waits for a falling edge.

The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).

The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NE noise flag is set if, for both samplings, at least 2 out of the 3 sampled bits are at 0 (sampling on the

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RM0368

Note:

Universal synchronous asynchronous receiver transmitter (USART)

3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits). If this condition is not met, the start detection aborts and the receiver returns to the idle state (no flag is set).

If, for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th and 10th bits), 2 out of the 3 bits are found at 0, the start bit is validated but the NE noise flag bit is set.

Character reception

During an USART reception, data shifts in least significant bit first through the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the received shift register.

Procedure:

Enable the USART by writing the UE bit in USART_CR1 register to 1.

2. Program the M bit in USART_CR1 to define the word length.

3. Program the number of stop bits in USART_CR2.

4. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take place. Configure the DMA register as explained in multibuffer communication. STEP 3

5. Select the desired baud rate using the baud rate register USART_BRR

6. Set the RE bit USART_CR1. This enables the receiver which begins searching for a start bit.

When a character is received

• The RXNE bit is set. It indicates that the content of the shift register is transferred to the

RDR. In other words, data has been received and can be read (as well as its associated error flags).

• An interrupt is generated if the RXNEIE bit is set.

• The error flags can be set if a frame error, noise or an overrun error has been detected during reception.

• In multibuffer, RXNE is set after every byte received and is cleared by the DMA read to the Data Register.

• In single buffer mode, clearing the RXNE bit is performed by a software read to the

USART_DR register. The RXNE flag can also be cleared by writing a zero to it. The

RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error.

The RE bit should not be reset while receiving data. If the RE bit is disabled during reception, the reception of the current byte will be aborted.

Break character

When a break character is received, the USART handles it as a framing error.

Idle character

When an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the IDLEIE bit is set.

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Universal synchronous asynchronous receiver transmitter (USART)

Note:

RM0368

Overrun error

An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.

The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs:

• The ORE bit is set.

• The RDR content will not be lost. The previous data is available when a read to

USART_DR is performed.

• The shift register will be overwritten. After that point, any data received during overrun is lost.

• An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits are set.

• The ORE bit is reset by a read to the USART_SR register followed by a USART_DR register read operation.

The ORE bit, when set, indicates that at least 1 data has been lost. There are two possibilities:

• if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,

• if RXNE=0, then it means that the last valid data has already been read and thus there is nothing to be read in the RDR. This case can occur when the last valid data is read in the RDR at the same time as the new (and lost) data is received. It may also occur when the new data is received during the reading sequence (between the USART_SR register read access and the USART_DR read access).

Selecting the proper oversampling method

The receiver implements different user-configurable oversampling techniques (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise.

The oversampling method can be selected by programming the OVER8 bit in the

USART_CR1 register and can be either 16 or 8 times the baud rate clock (

Figure 172 and

Figure 173 ).

Depending on the application:

• select oversampling by 8 (OVER8=1) to achieve higher speed (up to f

PCLK

/8). In this case the maximum receiver tolerance to clock deviation is reduced (refer to

Section 19.3.5: USART receiver tolerance to clock deviation on page 529

)

• select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to maximum f

PCLK

/16

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Note:

Universal synchronous asynchronous receiver transmitter (USART)

Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options:

• the majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set

• a single sample in the center of the received bit

Depending on the application:

– select the three samples’ majority vote method (ONEBIT=0) when operating in a noisy environment and reject the data when a noise is detected (refer to

Figure 73

) because this indicates that a glitch occurred during the sampling.

– select the single sample method (ONEBIT=1) when the line is noise-free to increase the receiver’s tolerance to clock deviations (see

Section 19.3.5: USART receiver tolerance to clock deviation on page 529

). In this case the NF bit will never be set.

When noise is detected in a frame:

• The NF bit is set at the rising edge of the RXNE bit.

• The invalid data is transferred from the Shift register to the USART_DR register.

• No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. In case of multibuffer communication an interrupt will be issued if the EIE bit is set in the

USART_CR3 register.

The NF bit is reset by a USART_SR register read operation followed by a USART_DR register read operation.

Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes, the OVER8 bit is forced to ‘0 by hardware.

Figure 172. Data sampling when oversampling by 16

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RM0368 Rev 5

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Universal synchronous asynchronous receiver transmitter (USART)

Figure 173. Data sampling when oversampling by 8

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Table 73. Noise detection from sampled data

Sampled value NE status Received bit value

000

001

010

011

100

101

110

111

Framing error

A framing error is detected when:

The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise.

When the framing error is detected:

• The FE bit is set by hardware

• The invalid data is transferred from the Shift register to the USART_DR register.

USART_CR3 register.

The FE bit is reset by a USART_SR register read operation followed by a USART_DR register read operation.

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RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Configurable stop bits during reception

The number of stop bits to be received can be configured through the control bits of Control

0.5 stop bit (reception in Smartcard mode) : No sampling is done for 0.5 stop bit. As a consequence, no framing error and no break frame can be detected when 0.5 stop bit is selected.

2. 1 stop bit : Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.

3. 1.5 stop bits (Smartcard mode) : When transmitting in smartcard mode, the device must check that the data is correctly sent. Thus the receiver block must be enabled (RE

=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has detected a parity error. In the event of a parity error, the smartcard forces the data signal low during the sampling - NACK signal-, which is flagged as a framing error.

Then, the FE flag is set with the RXNE at the end of the 1.5 stop bit. Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the beginning of the stop bit). The 1.5 stop bit can be decomposed into 2 parts: one 0.5 baud clock period during which nothing happens, followed by 1 normal stop bit period

during which sampling occurs halfway through. Refer to Section 19.3.11: Smartcard on page 538

for more details.

4. 2 stop bits : Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first stop bit. If a framing error is detected during the first stop bit the framing error flag will be set. The second stop bit is not checked for framing error. The RXNE flag will be set at the end of the first stop bit.

19.3.4 Fractional baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the Mantissa and Fraction values of USARTDIV.

Equation 1: Baud rate for standard USART (SPI mode included)

Tx/Rx baud =

8 × ( f

2 OVER8 ) × USARTDIV

Note:

Equation 2: Baud rate in Smartcard, LIN and IrDA modes

Tx/Rx baud

16 × f

USARTDIV

USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.

• When OVER8=0, the fractional part is coded on 4 bits and programmed by the

DIV_fraction[3:0] bits in the USART_BRR register

• When OVER8=1, the fractional part is coded on 3 bits and programmed by the

DIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction[3] must be kept cleared.

The baud counters are updated to the new value in the baud registers after a write operation to USART_BRR. Hence the baud rate register value should not be changed during communication.

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

How to derive USARTDIV from USART_BRR register values when OVER8=0

Example 1 :

If DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then

Mantissa (USARTDIV) = 0d27

Fraction (USARTDIV) = 12/16 = 0d0.75

Therefore USARTDIV = 0d27.75

Example 2 :

To program USARTDIV = 0d25.62

This leads to:

DIV_Fraction = 16*0d0.62 = 0d9.92

The nearest real number is 0d10 = 0xA

DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19

Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625

Example 3 :

To program USARTDIV = 0d50.99

This leads to:

DIV_Fraction = 16*0d0.99 = 0d15.84

The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be added up to the mantissa

DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33

Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000

How to derive USARTDIV from USART_BRR register values when OVER8=1

Example 1:

If DIV_Mantissa = 0x27 and DIV_Fraction[2:0]= 0d6 (USART_BRR = 0x1B6), then

Mantissa (USARTDIV) = 0d27

Fraction (USARTDIV) = 6/8 = 0d0.75

Therefore USARTDIV = 0d27.75

Example 2 :

To program USARTDIV = 0d25.62

This leads to:

DIV_Fraction = 8*0d0.62 = 0d4.96

The nearest real number is 0d5 = 0x5

DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19

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RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Then, USART_BRR = 0x195 => USARTDIV = 0d25.625

Example 3 :

To program USARTDIV = 0d50.99

This leads to:

DIV_Fraction = 8*0d0.99 = 0d7.92

The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be added up to the mantissa

DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33

Then, USART_BRR = 0x0330 => USARTDIV = 0d51.000

Table 74. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f oversampling by 16 (1)

PCLK

= 12 MHz,

Oversampling by 16 (OVER8=0)

Baud rate7

S.No

Desired Actual f

PCLK

= 8 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired) B.rate /

Desired B.rate

Actual f

PCLK

= 12 MHz

Value programmed in the baud rate register

% Error

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.4 KBps

57.6 KBps

1.2 KBps

2.4 KBps

9.604 KBps

19.185 KBps

38.462 KBps

57.554 KBps

115.2 KBps 115.942 KBps

230.4 KBps 228.571 KBps

9 460.8 KBps 470.588 KBps

10 921.6 KBps NA

2 MBps

3 MBps

416.6875

208.3125

52.0625

26.0625

8.6875

4.3125

2.1875

1.0625

0.01

0.04

0.08

0.16

0.08

0.64

0.79

2.12

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.339 KBps

57.692 KBps

115.385 KBps

230.769 KBps

461.538 KBps

625

312.5

78.125

39.0625

19.5625

6.5

3.25

1.625

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

0.16

RM0368 Rev 5

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

Table 75. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f oversampling by 8 (1)

PCLK

=12 MHz,

Oversampling by 8 (OVER8 = 1)

S.No

Baud rate

Desired Actual f

PCLK

= 8 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)

B.rate /

Desired

B.rate

Actual f

PCLK

= 12 MHz

Value programmed in the baud rate register

% Error

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.4 KBps

57.6 KBps

115.2 KBps 115.942 KBps

230.4 KBps 228.571 KBps

460.8 KBps 470.588 KBps

921.6 KBps 888.889 KBps

2 MBps

3 MBps

1.2 KBps

2.4 KBps

9.604 KBps

19.185 KBps

38.462 KBps

57.554 KBps

833.375

416.625

104.125

52.125

17.375

8.625

4.375

2.125

1.125

0.01

0.04

0.08

0.16

0.08

0.64

0.79

2.12

3.55

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.339 KBps

57.692 KBps

115.385 KBps

230.769 KBps

461.538 KBps

923.077 KBps

1250

625

156.25

78.125

39.125

6.5

3.25

1.625

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

0.16

S.No

Table 76. Error calculation for programmed baud rates at f

PCLK

= 16 MHz or f oversampling by 16 (1)

PCLK

= 24 MHz,

Oversampling by 16 (OVER8 = 0)

Baud rate

Desired

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.4 KBps

57.6 KBps

Actual

1.2 KBps

2.4 KBps

9.598 KBps

19.208 KBps

38.369 KBps

57.554 KBps fPCLK = 16 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired) B.rate /

Desired B.rate

833.3125

416.6875

104.1875

52.0625

26.0625

17.375

0.02

0.04

0.08

Actual fPCLK = 24 MHz

Value programmed in the baud rate register

% Error

1.2

2.4

9.6

19.2

38.4

57.554

1250

625

156.25

78.125

39.0625

26.0625

0.08

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RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Table 76. Error calculation for programmed baud rates at f

PCLK oversampling by 16 (1) (continued)

= 16 MHz or f

PCLK

= 24 MHz,

Oversampling by 16 (OVER8 = 0)

S.No

Baud rate

Desired Actual fPCLK = 16 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired) B.rate /

Desired B.rate

Actual fPCLK = 24 MHz

Value programmed in the baud rate register

% Error

115.2 KBps

230.4 KBps

460.8 KBps

921.6 KBps

2 MBps

3 MBps

115.108 KBps

231.884 KBps

457.143 KBps

941.176 KBps

8.6875

4.3125

2.1875

1.0625

0.08

0.64

0.79

2.12

115.385

230.769

461.538

923.077

6.5

3.25

1.625

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

0.16

Table 77. Error calculation for programmed baud rates at f

PCLK

= 16 MHz or f oversampling by 8 (1)

PCLK

= 24 MHz,

Oversampling by 8 (OVER8=1)

Baud rate

S.No

Desired Actual f

PCLK

= 16 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired) B.rate /

Desired B.rate

Actual f

PCLK

= 24 MHz

Value programmed in the baud rate register

% Error

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.4 KBps

57.6 KBps

115.2 KBps

230.4 KBps

1.2 KBps

2.4 KBps

9.598 KBps

19.208 KBps

38.369 KBps

57.554 KBps

115.108 KBps

231.884 KBps

9 460.8 KBps 457.143 KBps

10 921.6 KBps 941.176 KBps

2 MBps

3 MBps

2000 KBps

1666.625

833.375

208.375

104.125

52.125

34.75

17.375

8.625

4.375

2.125

0.02

0.04

0.08

0.64

0.79

2.12

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.4 KBps

57.554 KBps

115.385 KBps

230.769 KBps

461.538 KBps

923.077 KBps

2000 KBps

3000 KBps

2500

1250

312.5

156.25

78.125

52.125

6.5

3.25

1.5

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

0.08

0.16

RM0368 Rev 5

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

Table 78. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f oversampling by 16 (1)

PCLK

= 16 MHz,

Oversampling by 16 (OVER8=0)

S.No

Baud rate

Desired Actual f

PCLK

= 8 MHz

Value programme d in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

Actual f

PCLK

= 16 MHz

Value programmed in the baud rate register

% Error

2.4 KBps

9.6 KBps

19.2 KBps

57.6 KBps

2.400 KBps

9.604 KBps

19.185 KBps

57.554 KBps

208.3125

52.0625

26.0625

8.6875

115.2 KBps 115.942 KBps 4.3125

230.4 KBps

228.571

KBps

2.1875

460.8 KBps

470.588

KBps

NA 8.

896 KBps

921.6 KBps NA

10.

1.792 MBps NA

11.

1.8432 MBps NA

12.

3.584 MBps NA

13.

3.6864 MBps NA

14.

7.168 MBps NA

15.

7.3728 MBps NA

1.0625

0.00%

0.04%

0.08%

0.64%

0.79%

2.12%

2.400 KBps

9.598 KBps

19.208 KBps

57.554 KBps

115.108 KBps

231.884 KBps

457.143 KBps

416.6875

104.1875

52.0625

17.3750

8.6875

4.3125

2.1875

888.889 KBps 1.1250

941.176 KBps 1.0625

NA NA

0.00%

0.02%

0.04%

0.08%

0.64%

0.79%

2.12%

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

S.No

Table 79. Error calculation for programmed baud rates at f

PCLK

= 8 MHz or f

PCLK

= 16 MHz, oversampling by 8 (1)

Oversampling by 8 (OVER8=1)

Baud rate

Desired

2.4 KBps

9.6 KBps

19.2 KBps

Actual

2.400 KBps

9.604 KBps f

PCLK

= 8 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

416.625

104.125

19.185 KBps 52.125

0.01%

0.04%

0.08%

Actual f

PCLK

= 16 MHz

Value programmed in the baud rate register

2.400 KBps

9.598 KBps

833.375

208.375

19.208 KBps 104.125

Error

0.00%

0.02%

0.04%

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RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Table 79. Error calculation for programmed baud rates at f

PCLK oversampling by 8 (1) (continued)

= 8 MHz or f

PCLK

= 16 MHz,

Oversampling by 8 (OVER8=1)

S.No

Baud rate

Desired Actual f

PCLK

= 8 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

Actual f

PCLK

= 16 MHz

Value programmed in the baud rate register

Error

10.

11.

12.

13.

14.

15.

57.6 KBps

115.2 KBps

230.4 KBps

460.8 KBps

896 KBps

921.6 KBps

57.557 KBps 17.375

115.942 KBps 8.625

228.571 KBps 4.375

470.588 KBps 2.125

888.889 KBps 1.125

1.792 MBps NA

1.8432 MBps NA

3.584 MBps NA

3.6864 MBps NA

7.168 MBps NA

7.3728 MBps NA

0.08%

0.64%

0.79%

2.12%

0.79%

3.55%

57.554 KBps 34.750

115.108 KBps 17.375

231.884 KBps 8.625

457.143 KBps 4.375

888.889 KBps 2.250

941.176 KBps 2.125

1.7777 MBps 1.125

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

0.08%

0.64%

0.79%

2.12%

0.79%

3.55%

Table 80. Error calculation for programmed baud rates at f

PCLK

= 30 MHz or f oversampling by 16 (1)(2)

PCLK

= 60 MHz,

Oversampling by 16 (OVER8=0)

S.No

Baud rate

Desired Actual f

PCLK

= 30 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

2.4 KBps

9.6 KBps

2.400 KBps

9.600 KBps

781.2500

195.3125

19.2 KBps 19.194 KBps 97.6875

57.6 KBps 57.582KBps

32.5625

115.2 KBps 115.385 KBps 16.2500

230.4 KBps 230.769 KBps 8.1250

460.8 KBps 461.538 KBps 4.0625

896 KBps 909.091 KBps 2.0625

0.00%

0.03%

0.16%

1.46%

Actual f

PCLK

= 60 MHz

Value programmed in the baud rate register

2.400 KBps

9.600 KBps

1562.5000

390.6250

19.200 KBps 195.3125

57.582 KBps 65.1250

115.163 KBps 32.5625

230.769KBps 16.2500

461.538 KBps 8.1250

895.522 KBps 4.1875

Error

0.00%

0.03%

0.16%

0.05%

RM0368 Rev 5

525/847

558

Universal synchronous asynchronous receiver transmitter (USART) RM0368

Table 80. Error calculation for programmed baud rates at f

PCLK oversampling by 16 (1)(2) (continued)

= 30 MHz or f

PCLK

= 60 MHz,

Oversampling by 16 (OVER8=0)

S.No

Baud rate

Desired Actual f

PCLK

= 30 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

Actual f

PCLK

= 60 MHz

Value programmed in the baud rate register

Error

10.

11.

12.

13.

14.

15.

921.6 KBps 909.091 KBps 2.0625

1.792 MBps 1.1764 MBps 1.0625

1.8432

MBps

1.8750 MBps

3.584 MBps NA

1.0000

3.6864

MBps

7.168 MBps NA

7.3728

MBps

1.36%

1.52%

1.73%

923.077 KBps 4.0625

1.8182 MBps

3.2594 MBps

3.7500 MBps

2.0625

1.0625

1.0000

0.16%

1.36%

1.52%

1.73%

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device datasheets for the maximum values for PCLK1 and PCLK2.

S.No

10.

Table 81. Error calculation for programmed baud rates at f

PCLK

= 30 MHz or f

PCLK

= 60 MHz, oversampling by 8

(1) (2)

Oversampling by 8 (OVER8=1)

Baud rate

Desired

2.4 KBps

9.6 KBps

19.2 KBps

57.6 KBps

115.2 KBps

230.4 KBps

460.8 KBps

896 KBps

921.6 KBps

1.792 MBps f

PCLK

= 30 MHz f

PCLK

=60 MHz

Actual

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

2.400 KBps 1562.5000

9.600 KBps 390.6250

19.194 KBps 195.3750

57.582 KBps 65.1250

115.385 KBps 32.5000

230.769 KBps 16.2500

461.538 KBps 8.1250

909.091 KBps 4.1250

1.7647 MBps 2.1250

0.00%

0.03%

0.16%

1.46%

1.36%

1.52%

Actual

Value programmed in the baud rate register

2.400 KBps 3125.0000

9.600 KBps 781.2500

19.200 KBps 390.6250

57.582 KBps 130.2500

115.163 KBps 65.1250

230.769 KBps 32.5000

461.538 KBps 16.2500

895.522 KBps 8.3750

923.077 KBps 8.1250

1.8182 MBps 4.1250

Error

0.00%

0.03%

0.16%

0.05%

0.16%

1.46%

526/847

RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Table 81. Error calculation for programmed baud rates at f

PCLK oversampling by 8 (1) (2) (continued)

= 30 MHz or f

PCLK

= 60 MHz,

Oversampling by 8 (OVER8=1)

S.No

Baud rate

Desired Actual f

PCLK

= 30 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

Actual f

PCLK

=60 MHz

Value programmed in the baud rate register

Error

11.

12.

13.

14.

15.

1.8432 MBps

3.584 MBps

1.8750 MBps 2.0000

3.7500 MBps 1.0000

3.6864 MBps 3.7500 MBps 1.0000

7.168 MBps

7.3728 MBps

1.73%

4.63%

1.73%

1.8182 MBps

7.5000 MBps

4.1250

3.5294 MBps 2.1250

3.7500 MBps 2.0000

7.5000 MBps 1.0000

1.0000

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device datasheets for the maximum values for PCLK1 and PCLK2.

1.36%

1.52%

1.73%

4.63%

1.73%

Table 82. Error calculation for programmed baud rates at f

PCLK

= 42 MHz or f oversampling by 16 (1)(2)

PCLK

= 84 Hz,

Oversampling by 16 (OVER8=0)

10.

11.

12.

13.

14.

S.No

Baud rate

Desired Actual f

PCLK

= 42 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

1.2 KBps

2.4 KBps

9.6 KBps

19.2 KBps

38.4 KBps

57.6 KBps

1.2 KBps

2.4 KBps

9.6 KBps

19.195 KBps

38.391 KBps

57.613 KBps

2187.5

1093.75

273.4375

136.75

68.375

45.5625

115.2 KBps 115.068 KBps 22.8125

230.4 KBps 230.769 KBps 11.375

460.8 KBps 461.538 KBps 5.6875

921.6 KBps 913.043 KBps 2.875

1.792 MBps 1.826 MBps 1.4375

1.8432 MBps 1.826 MBps 1.4375

3.584 MBps N.A

3.6864 MBps N.A

N.A

0.02

0.11

0.16

0.93

1.9

0.93

N.A

Actual f

PCLK

= 84 MHz

Value programmed in the baud rate register

1.2 KBps

2.4 KBps

9.6 KBps

2187.5

546.875

19.2 KBps 273.4375

38.391 KBps 136.75

57.613 KBps 91.125

115.226 KBps 45.5625

230.137 KBps 22.8125

461.538 KBps 11.375

923.076 KBps 5.6875

1.787 MBps 2.9375

1.826 MBps 2.875

3.652 MBps 1.4375

Error

0.93

0.27

0.93

1.9

0.93

0.02

0.11

0.16

RM0368 Rev 5

527/847

558

Universal synchronous asynchronous receiver transmitter (USART) RM0368

Table 82. Error calculation for programmed baud rates at f

PCLK oversampling by 16 (1)(2) (continued)

= 42 MHz or f

PCLK

= 84 Hz,

Oversampling by 16 (OVER8=0)

S.No

Baud rate

Desired Actual f

PCLK

= 42 MHz

Value programmed in the baud rate register

% Error =

(Calculated -

Desired)B.Rate

/Desired B.Rate

Actual f

PCLK

= 84 MHz

Value programmed in the baud rate register

Error

15.

16.

17.

18.

7.168 MBps N.A

7.3728 MBps N.A

9 MBps

10.5 MBps

N.A

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device datasheets for the maximum values for PCLK1 and PCLK2.

Table 83. Error calculation for programmed baud rates at f

PCLK

= 42 MHz or f oversampling by 8

(1)(2)

PCLK

= 84 MHz,

Oversampling by 8 (OVER8=1)

Baud rate f

PCLK

= 42 MHz f

PCLK

= 84 MHz

10.

11.

12.

13.

14.

15.

S.No

Desired Actual

Value programmed in the baud rate register

2.4 KBps

9.6 KBps

19.2 KBps

38.4 KBps

57.6 KBps

115.2 KBps

230.4 KBps

460.8 KBps

921.6 KBps

1.792 MBps

1.8432 MBps 1.826 MBps

3.584 MBps 3.5 MBps

3.6864 MBps 3.82 MBps

7.168 MBps N.A

7.3728 MBps N.A

2.4 KBps 2187.5

9.6 KBps 546.875

19.195 KBps 273.5

38.391 KBps 136.75

57.613 KBps 91.125

115.068 KBps 45.625

230.769 KBps 22.75

461.538 KBps 11.375

913.043 KBps 5.75

1.826 MBps 2.875

2.875

1.5

1.375

N.A

0.02

0.11

0.16

0.93

1.9

0.02

0.93

2.34

3.57

N.A

Value programmed in the baud rate register

Actual

Value programmed in the baud rate register

2.4 KBps NA

9.6 KBps

19.2 KBps

1093.75

546.875

38.391 KBps 273.5

57.613 KBps 182.25

115.226 KBps 91.125

230.137 KBps 45.625

461.538 KBps 22.75

923.076 KBps 11.375

1.787Mbps

5.875

1.826 MBps 5.75

3.652 MBps 2.875

7 MBps 1.5

7.636 MBps 1.375

Error

0.02

0.11

0.16

0.93

0.27

0.02

0.93

1.9

0.93

2.34

3.57

528/847

RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Table 83. Error calculation for programmed baud rates at f

PCLK oversampling by 8 (1)(2) (continued)

= 42 MHz or f

PCLK

= 84 MHz,

Oversampling by 8 (OVER8=1)

S.No

Baud rate

Desired Actual f

PCLK

= 42 MHz

Value programmed in the baud rate register

Actual f

PCLK

= 84 MHz

Value programmed in the baud rate register

Error

16.

17.

9 MBps

10.5 MBps

N.A

9.333 MBps

10.5 MBps

1.125

3.7

1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data.

2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device datasheets for the maximum values for PCLK1 and PCLK2.

The USART asynchronous receiver works correctly only if the total clock system deviation is smaller than the USART receiver’s tolerance. The causes which contribute to the total deviation are:

• DTRA: Deviation due to the transmitter error (which also includes the deviation of the transmitter’s local oscillator)

• DQUANT: Error due to the baud rate quantization of the receiver

• DREC: Deviation of the receiver’s local oscillator

• DTCL: Deviation due to the transmission line (generally due to the transceivers which can introduce an asymmetry between the low-to-high transition timing and the high-tolow transition timing)

DTRA + DQUANT + DREC + DTCL < USART receiver’s tolerance

The USART receiver’s tolerance to properly receive data is equal to the maximum tolerated deviation and depends on the following choices:

• 10- or 11-bit character length defined by the M bit in the USART_CR1 register

• oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register

• use of fractional baud rate or not

• use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in the USART_CR3 register

M bit

Table 84. USART receiver’s tolerance when DIV fraction is 0

OVER8 bit = 0 OVER8 bit = 1

ONEBIT=0

3.75%

3.41%

ONEBIT=1

4.375%

3.97%

ONEBIT=0

2.50%

2.27%

ONEBIT=1

3.75%

3.41%

RM0368 Rev 5

529/847

558

Universal synchronous asynchronous receiver transmitter (USART)

Note:

RM0368

Table 85. USART receiver tolerance when DIV_Fraction is different from 0

OVER8 bit = 0

M bit

OVER8 bit = 1

ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1

0 3.33% 3.88% 2% 3%

1 3.03% 3.53% 1.82% 2.73%

The figures specified in Table 84

and

Table 85

may slightly differ in the special case when the received frames contain some Idle frames of exactly 10-bit times when M=0 (11-bit times when M=1).

There is a possibility of performing multiprocessor communication with the USART (several

USARTs connected in a network). For instance one of the USARTs can be the master, its TX output is connected to the RX input of the other USART. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master.

In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant USART service overhead for all non addressed receivers.

The non addressed devices may be placed in mute mode by means of the muting function.

In mute mode:

• None of the reception status bits can be set.

• All the receive interrupts are inhibited.

• The RWU bit in USART_CR1 register is set to 1. RWU can be controlled automatically by hardware or written by the software under certain conditions.

The USART can enter or exit from mute mode using one of two methods, depending on the

WAKE bit in the USART_CR1 register:

• Idle Line detection if the WAKE bit is reset,

• Address Mark detection if the WAKE bit is set.

Idle line detection (WAKE=0)

The USART enters mute mode when the RWU bit is written to 1.

It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_SR register. RWU can also be written to 0 by software.

An example of mute mode behavior using Idle line detection is given in Figure 174

530/847

RM0368 Rev 5

RM0368

Universal synchronous asynchronous receiver transmitter (USART)

Figure 174. Mute mode using Idle line detection

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Address mark detection (WAKE=1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1 else they are considered as data. In an address byte, the address of the targeted receiver is put on the 4

LSB. This 4-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the USART_CR2 register.

The USART enters mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt nor DMA request is issued as the

USART would have entered mute mode.

It exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for the address character since the RWU bit has been cleared.

The RWU bit can be written to as 0 or 1 when the receiver buffer contains no data (RXNE=0 in the USART_SR register). Otherwise the write attempt is ignored.

An example of mute mode behavior using address mark detection is given in

Figure 175

Figure 175. Mute mode using address mark detection

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RM0368 Rev 5

531/847

558

Universal synchronous asynchronous receiver transmitter (USART) RM0368

Note:

Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame

length defined by the M bit, the possible USART frame formats are as listed in Table 86

M bit PCE bit

Table 86. Frame formats

USART frame

(1)

1. Legends: SB: start bit, STB: stop bit, PB: parity bit.

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data PB | STB |

Even parity

The parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

E.g.: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit in

USART_CR1 = 0).

Odd parity

The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or

8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

E.g.: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in

USART_CR1 = 1).

Parity checking in reception

If the parity check fails, the PE flag is set in the USART_SR register and an interrupt is generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software sequence (a read from the status register followed by a read or write access to the

USART_DR data register).

In case of wakeup by an address mark: the MSB bit of the data is taken into account to identify an address but not the parity bit. And the receiver does not check the parity of the address data (PE is not set in case of a parity error).

Parity generation in transmission

If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected

(PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).

The software routine that manages the transmission can activate the software sequence which clears the PE flag (a read from the status register followed by a read or write access to the data register). When operating in half-duplex mode, depending on the software, this can cause the PE flag to be unexpectedly cleared.

532/847

RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

19.3.8 LIN (local interconnection network) mode

The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared:

• STOP[1:0] and CLKEN in the USART_CR2 register

• SCEN, HDSEL and IREN in the USART_CR3 register.

LIN transmission

The same procedure explained in

Section 19.3.2

has to be applied for LIN Master

transmission than for normal USART transmission with the following differences:

• Clear the M bit to configure 8-bit word length.

• Set the LINEN bit to enter LIN mode. In this case, setting the SBK bit sends 13 ‘0 bits as a break character. Then a bit of value ‘1 is sent to allow the next start detection.

LIN reception

A break detection circuit is implemented on the USART interface. The detection is totally independent from the normal USART receiver. A break can be detected whenever it occurs, during Idle state or during a frame.

When the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a start signal. The method for detecting start bits is the same when searching break characters or data. After a start bit has been detected, the circuit samples the next bits exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in

USART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as ‘0, and are followed by a delimiter character, the LBD flag is set in USART_SR. If the LBDIE bit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it signifies that the RX line has returned to a high level.

If a ‘1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the current detection and searches for a start bit again.

If the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART, without taking into account the break detection.

If the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (i.e. stop bit detected at ‘0, which will be the case for any break frame), the receiver stops until the break detection circuit receives either a ‘1, if the break word was not complete, or a delimiter character if a break has been detected.

The behavior of the break detector state machine and the break flag is shown on the

Figure 176: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 534 .

Examples of break frames are given on

Figure 177: Break detection in LIN mode vs.

Framing error detection on page 535

RM0368 Rev 5

533/847

558

Universal synchronous asynchronous receiver transmitter (USART) RM0368

Figure 176. Break detection in LIN mode (11-bit break length - LBDL bit is set)

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RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Figure 177. Break detection in LIN mode vs. Framing error detection

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19.3.9 USART synchronous mode

Note:

The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to

1. In synchronous mode, the following bits must be kept cleared:

• LINEN bit in the USART_CR2 register,

• SCEN, HDSEL and IREN bits in the USART_CR3 register.

The USART allows the user to control a bidirectional synchronous serial communications in master mode. The CK pin is the output of the USART transmitter clock. No clock pulses are sent to the CK pin during start bit and stop bit. Depending on the state of the LBCL bit in the

USART_CR2 register clock pulses will or will not be generated during the last valid data bit

(address mark). The CPOL bit in the USART_CR2 register allows the user to select the clock polarity, and the CPHA bit in the USART_CR2 register allows the user to select the phase of the external clock (see

Figure 178

Figure 179

Figure 180

During the Idle state, preamble and send break, the external CK clock is not activated.

In synchronous mode the USART transmitter works exactly like in asynchronous mode. But as CK is synchronized with TX (according to CPOL and CPHA), the data on TX is synchronous.

In this mode the USART receiver works in a different manner compared to the asynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending on CPOL and CPHA), without any oversampling. A setup and a hold time must be respected (which depends on the baud rate: 1/16 bit time).

The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR

RM0368 Rev 5

535/847

558

Universal synchronous asynchronous receiver transmitter (USART) RM0368 has been written). This means that it is not possible to receive a synchronous data without transmitting data.

The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These bits should not be changed while the transmitter or the receiver is enabled.

It is advised that TE and RE are set in the same instruction in order to minimize the setup and the hold time of the receiver.

The USART supports master mode only: it cannot receive or send data related to an input clock (CK is always an output).

Figure 178. USART example of synchronous transmission

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Figure 179. USART data clock timing diagram (M=0)

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RM0368 Rev 5

RM0368

Note:

Universal synchronous asynchronous receiver transmitter (USART)

Figure 180. USART data clock timing diagram (M=1)

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Figure 181. RX data setup/hold time

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The function of CK is different in Smartcard mode. Refer to the Smartcard mode chapter for more details.

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared:

• LINEN and CLKEN bits in the USART_CR2 register,

• SCEN and IREN bits in the USART_CR3 register.

The USART can be configured to follow a single-wire half-duplex protocol where the TX and

RX lines are internally connected. The selection between half- and full-duplex communication is made with a control bit ‘HALF DUPLEX SEL’ (HDSEL in USART_CR3).

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

As soon as HDSEL is written to 1:

• the TX and RX lines are internally connected

• the RX pin is no longer used

• the TX pin is always released when no data is transmitted. Thus, it acts as a standard

I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as floating input (or output high open-drain) when not driven by the USART.

Apart from this, the communications are similar to what is done in normal USART mode.

The conflicts on the line must be managed by the software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TE bit is set.

19.3.11 Smartcard

Note:

The Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In smartcard mode, the following bits must be kept cleared:

• LINEN bit in the USART_CR2 register,

• HDSEL and IREN bits in the USART_CR3 register.

Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.

The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO 7816-3 standard. The USART should be configured as:

• 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register

• 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

It is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop bits for both transmitting and receiving to avoid switching between the two configurations.

Figure 182 shows examples of what can be seen on the data line with and without parity

error.

Figure 182. ISO 7816-3 asynchronous protocol

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When connected to a Smartcard, the TX output of the USART drives a bidirectional line that is also driven by the Smartcard. The TX pin must be configured as open-drain.

Smartcard is a single wire half duplex communication protocol.

• Transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. In normal operation a full transmit shift register will start

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Note:

Universal synchronous asynchronous receiver transmitter (USART) shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock.

• If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame. This is to indicate to the Smartcard that the data transmitted to USART has not been correctly received. This NACK signal (pulling transmit line low for 1 baud clock) will cause a framing error on the transmitter side

(configured with 1.5 stop bits). The application can handle re-sending of data according to the protocol. A parity error is ‘NACK’ed by the receiver if the NACK control bit is set, otherwise a NACK is not transmitted.

• The assertion of the TC flag can be delayed by programming the Guard Time register.

In normal operation, TC is asserted when the transmit shift register is empty and no further transmit requests are outstanding. In Smartcard mode an empty transmit shift register triggers the guard time counter to count up to the programmed value in the

Guard Time register. TC is forced low during this time. When the guard time counter reaches the programmed value TC is asserted high.

• The de-assertion of TC flag is unaffected by Smartcard mode.

• If a framing error is detected on the transmitter end (due to a NACK from the receiver), the NACK will not be detected as a start bit by the receive block of the transmitter.

According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud clock periods.

• On the receiver side, if a parity error is detected and a NACK is transmitted the receiver will not detect the NACK as a start bit.

A break character is not significant in Smartcard mode. A 0x00 data with a framing error will be treated as data and not as a break.

No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the other configurations) is not defined by the ISO protocol.

Figure 183 details how the NACK signal is sampled by the USART. In this example the

USART is transmitting a data and is configured with 1.5 stop bits. The receiver part of the

USART is enabled in order to check the integrity of the data and the NACK signal.

Figure 183. Parity error detection using the 1.5 stop bits

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The USART can provide a clock to the smartcard through the CK output. In smartcard mode, CK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. The division ratio is configured in the

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Universal synchronous asynchronous receiver transmitter (USART) RM0368 prescaler register USART_GTPR. CK frequency can be programmed from f

CK where f

is the peripheral input clock.

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19.3.12 IrDA SIR ENDEC block

The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared:

• LINEN, STOP and CLKEN bits in the USART_CR2 register,

• SCEN and HDSEL bits in the USART_CR3 register.

The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation scheme that represents logic 0 as an infrared light pulse (see

Figure 184 ).

The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream output from USART. The output pulse stream is transmitted to an external output driver and infrared LED. USART supports only bit rates up to 115.2Kbps for the SIR ENDEC. In normal mode the transmitted pulse width is specified as 3/16 of a bit period.

The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to USART. The decoder input is normally HIGH (marking state) in the Idle state. The transmit encoder output has the opposite polarity to the decoder input. A start bit is detected when the decoder input is low.

• IrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the USART is sending data to the IrDA encoder), any data on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy (USART is receiving decoded data from the USART), data on the TX from the USART to IrDA will not be encoded by IrDA.

While receiving data, transmission should be avoided as the data to be transmitted could be corrupted.

• A ‘0 is transmitted as a high pulse and a ‘1 is transmitted as a ‘0. The width of the pulse

is specified as 3/16th of the selected bit period in normal mode (see Figure 185 ).

• The SIR decoder converts the IrDA compliant receive signal into a bit stream for

USART.

• The SIR receive logic interprets a high state as a logic one and low pulses as logic zeros.

• The transmit encoder output has the opposite polarity to the decoder input. The SIR output is in low state when Idle.

• The IrDA specification requires the acceptance of pulses greater than 1.41 us. The acceptable pulse width is programmable. Glitch detection logic on the receiver end filters out pulses of width less than 2 PSC periods (PSC is the prescaler value programmed in the IrDA low-power Baud Register, USART_GTPR). Pulses of width less than 1 PSC period are always rejected, but those of width greater than one and less than two periods may be accepted or rejected, those greater than 2 periods will be accepted as a pulse. The IrDA encoder/decoder doesn’t work when PSC=0.

• The receiver can communicate with a low-power transmitter.

• In IrDA mode, the STOP bits in the USART_CR2 register must be configured to “1 stop bit”.

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Universal synchronous asynchronous receiver transmitter (USART)

IrDA low-power mode

Transmitter :

In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz.

Generally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode programmable divisor divides the system clock to achieve this value.

Receiver :

Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the

USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in

USART_GTPR).

A pulse of width less than two and greater than one PSC period(s) may or may not be rejected.

The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and reception (IrDA is a half duplex protocol).

Figure 184. IrDA SIR ENDEC- block diagram

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Figure 185. IrDA data modulation (3/16) -Normal mode

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

The USART is capable of continuous communication using the DMA. The DMA requests for

Rx buffer and Tx buffer are generated independently.

Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the

DMA specification) to the USART_DR register whenever the TXE bit is set. To map a DMA channel for USART transmission, use the following procedure (x denotes the channel number):

Write the USART_DR register address in the DMA control register to configure it as the destination of the transfer. The data will be moved to this address from memory after each TXE event.

2. Write the memory address in the DMA control register to configure it as the source of the transfer. The data will be loaded into the USART_DR register from this memory area after each TXE event.

3. Configure the total number of bytes to be transferred to the DMA control register.

4. Configure the channel priority in the DMA register

5. Configure DMA interrupt generation after half/ full transfer as required by the application.

6. Clear the TC bit in the SR register by writing 0 to it.

7. Activate the channel in the DMA register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector.

In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART communication is complete. This is required to avoid corrupting the last transmission before disabling the USART or entering the Stop mode. The software must wait until TC=1. The TC flag remains cleared during all data transfers and it is set by hardware at the last frame’s end of transmission.

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Figure 186. Transmission using DMA

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Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.

Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA channel for USART reception, use the following procedure:

Write the USART_DR register address in the DMA control register to configure it as the source of the transfer. The data will be moved from this address to the memory after each RXNE event.

2. Write the memory address in the DMA control register to configure it as the destination of the transfer. The data will be loaded from USART_DR to this memory area after each

RXNE event.

3. Configure the total number of bytes to be transferred in the DMA control register.

4. Configure the channel priority in the DMA control register

5. Configure interrupt generation after half/ full transfer as required by the application.

6. Activate the channel in the DMA control register.

When the number of data transfers programmed in the DMA Controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector. The DMAR bit should be cleared by software in the USART_CR3 register during the interrupt subroutine.

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Error flagging and interrupt generation in multibuffer communication

In case of multibuffer communication if any error occurs during the transaction the error flag will be asserted after the current byte. An interrupt will be generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which if set will issue an interrupt after the current byte with either of these errors.

It is possible to control the serial data flow between 2 devices by using the CTS input and the RTS output. The

Figure 188 shows how to connect 2 devices in this mode:

Figure 188. Hardware flow control between 2 USARTs

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RTS and CTS flow control can be enabled independently by writing respectively RTSE and

CTSE bits to 1 (in the USART_CR3 register).

RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

RTS flow control

If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the

USART receiver is ready to receive a new data. When the receive register is full, RTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.

Figure 189

shows an example of communication with RTS flow control enabled.

Figure 189. RTS flow control

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CTS flow control

If the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input before transmitting the next frame. If CTS is asserted (tied low), then the next data is transmitted (assuming that a data is to be transmitted, in other words, if TXE=0), else the transmission does not occur. When CTS is deasserted during a transmission, the current transmission is completed before the transmitter stops.

When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS input toggles. It indicates when the receiver becomes ready or not ready for communication.

An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure below shows an example of communication with CTS flow control enabled.

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Universal synchronous asynchronous receiver transmitter (USART)

Figure 190. CTS flow control

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Special behavior of break frames: when the CTS flow is enabled, the transmitter does not check the CTS input state to send a break.

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RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Table 87. USART interrupt requests

Interrupt event

Transmit Data Register Empty

CTS flag

Transmission Complete

Received Data Ready to be Read

Overrun Error Detected

Idle Line Detected

Parity Error

Break Flag

Noise Flag, Overrun error and Framing Error in multibuffer communication

Event flag

TXE

CTS

RXNE

ORE

IDLE

LBD

Enable control bit

TXEIE

CTSIE

TCIE

RXNEIE

IDLEIE

PEIE

LBDIE

NF or ORE or FE EIE

The USART interrupt events are connected to the same interrupt vector (see Figure 191 ).

• During transmission: Transmission Complete, Clear to Send or Transmit Data Register empty interrupt.

• While receiving: Idle Line detection, Overrun error, Receive Data register not empty,

Parity error, LIN break detection, Noise Flag (only in multi buffer communication) and

Framing Error (only in multi buffer communication).

These events generate an interrupt if the corresponding Enable Control Bit is set.

Figure 191. USART interrupt mapping diagram

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19.5 USART mode configuration

USART modes

Table 88. USART mode configuration (1)

USART1 USART2

Asynchronous mode

Hardware flow control

Multibuffer communication (DMA)

Multiprocessor communication

Synchronous

Smartcard

Half-duplex (single-wire mode)

IrDA

LIN

1. X = supported; NA = not applicable.

RM0368

USART6

Refer to

Section 1.1: List of abbreviations for registers for registers

for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).

Address offset: 0x00

Reset value: 0x00C0 0000

29 28 27 26

13 12

Reserved

11 10

25 24 23

Reserved

8 7 9

CTS LBD rc_w0 rc_w0

TXE r

22 21 20

6 5 4

TC RXNE IDLE rc_w0 rc_w0 r

ORE r

NF r

FE r

PE r

Bits 31:10 Reserved, must be kept at reset value

Bit 9 CTS : CTS flag

This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3 register.

Note: 0: No change occurred on the CTS status line

1: A change occurred on the CTS status line

Bit 8 LBD : LIN break detection flag

This bit is set by hardware when the LIN break is detected. It is cleared by software (by writing it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.

0: LIN Break not detected

1: LIN break detected

Note: An interrupt is generated when LBD=1 if LBDIE=1

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Bit 7 TXE : Transmit data register empty

This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It is cleared by a write to the USART_DR register.

0: Data is not transferred to the shift register

1: Data is transferred to the shift register)

Note: This bit is used during single buffer transmission.

Bit 6 TC : Transmission complete

This bit is set by hardware if the transmission of a frame containing data is complete and if

TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by a software sequence (a read from the USART_SR register followed by a write to the

USART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing sequence is recommended only for multibuffer communication.

0: Transmission is not complete

1: Transmission is complete

Bit 5 RXNE : Read data register not empty

This bit is set by hardware when the content of the RDR shift register has been transferred to the USART_DR register. An interrupt is generated if RXNEIE=1 in the USART_CR1 register. It is cleared by a read to the USART_DR register. The RXNE flag can also be cleared by writing a zero to it. This clearing sequence is recommended only for multibuffer communication.

0: Data is not received

1: Received data is ready to be read.

Bit 4 IDLE : IDLE line detected

This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the

IDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the

USART_SR register followed by a read to the USART_DR register).

0: No Idle Line is detected

1: Idle Line is detected

Note: The IDLE bit will not be set again until the RXNE bit has been set itself (i.e. a new idle line occurs).

Bit 3 ORE : Overrun error

This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if

RXNEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the

USART_SR register followed by a read to the USART_DR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set, the RDR register content will not be lost but the shift register will be overwritten. An interrupt is generated on ORE flag in case of Multi Buffer communication if the EIE bit is set.

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Bit 2 NF : Noise detected flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the

USART_DR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit which itself generates an interrupting interrupt is generated on NF flag in case of Multi

Buffer communication if the EIE bit is set.

Note: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to

Section 19.3.5: USART receiver tolerance to clock deviation on page 529

Bit 1 FE : Framing error

This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the USART_DR register).

0: No Framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the ORE bit will be set.

An interrupt is generated on FE flag in case of Multi Buffer communication if the EIE bit is set.

Bit 0 PE : Parity error

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read from the status register followed by a read or write access to the

USART_DR data register). The software must wait for the RXNE flag to be set before clearing the PE bit.

An interrupt is generated if PEIE = 1 in the USART_CR1 register.

0: No parity error

1: Parity error

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19.6.2 Data register (USART_DR)

Address offset: 0x04

Reset value: 0xXXXX XXXX

Bits 31:9 Reserved, must be kept at reset value

Bits 8:0 DR[8:0] : Data value

Contains the Received or Transmitted data character, depending on whether it is read from or written to.

The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR)

The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 1).

The RDR register provides the parallel interface between the input shift register and the internal bus.

When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity.

When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.

19.6.3 Baud rate register (USART_BRR)

Note:

15 rw

14 rw

The baud counters stop counting if the TE or RE bits are disabled respectively.

Address offset: 0x08

Reset value: 0x0000 0000

29 28 27 26 25 22 21 20 19 18

13 12 11

24 23

Reserved

8 7 6 5 4 3 rw rw rw

10 9

DIV_Mantissa[11:0] rw rw rw rw rw rw rw rw

2 1

DIV_Fraction[3:0] rw rw

0 rw

Bits 31:16 Reserved, must be kept at reset value

Bits 15:4 DIV_Mantissa[11:0] : mantissa of USARTDIV

These 12 bits define the mantissa of the USART Divider (USARTDIV)

Bits 3:0 DIV_Fraction[3:0] : fraction of USARTDIV

These 4 bits define the fraction of the USART Divider (USARTDIV). When OVER8=1, the

DIV_Fraction3 bit is not considered and must be kept cleared.

19.6.4 Control register 1 (USART_CR1)

Address offset: 0x0C

Reset value: 0x0000 0000

29 28 27 26 25

15 14 13

OVER8 Reserved UE rw Res.

M rw

WAKE rw

PCE rw

PS rw

24 23

Reserved

8 7

22 21 20

6 5 4

PEIE TXEIE TCIE RXNEIE IDLEIE rw rw rw rw rw

TE rw

18 17 16

RE rw

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Bits 31:16 Reserved, must be kept at reset value

Bit 15 OVER8 : Oversampling mode

0: oversampling by 16

1: oversampling by 8

Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when

SCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to ‘0 by hardware.

Bit 14 Reserved, must be kept at reset value

Bit 13 UE : USART enable

When this bit is cleared, the USART prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption. This bit is set and cleared by software.

0: USART prescaler and outputs disabled

1: USART enabled

Bit 12 M : Word length

This bit determines the word length. It is set or cleared by software.

0: 1 Start bit, 8 Data bits, n Stop bit

1: 1 Start bit, 9 Data bits, n Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and reception)

Bit 11 WAKE : Wakeup method

This bit determines the USART wakeup method, it is set or cleared by software.

0: Idle Line

1: Address Mark

Bit 10 PCE : Parity control enable

This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software.

Once it is set, PCE is active after the current byte (in reception and in transmission).

0: Parity control disabled

1: Parity control enabled

Bit 9 PS : Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 8 PEIE : PE interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An USART interrupt is generated whenever PE=1 in the USART_SR register

Bit 7 TXEIE : TXE interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An USART interrupt is generated whenever TXE=1 in the USART_SR register

Bit 6 TCIE : Transmission complete interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An USART interrupt is generated whenever TC=1 in the USART_SR register

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RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Bit 5 RXNEIE : RXNE interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_SR register

Bit 4 IDLEIE : IDLE interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An USART interrupt is generated whenever IDLE=1 in the USART_SR register

Bit 3 TE : Transmitter enable

This bit enables the transmitter. It is set and cleared by software.

0: Transmitter is disabled

1: Transmitter is enabled

Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble

(idle line) after the current word, except in smartcard mode.

When TE is set, there is a 1 bit-time delay before the transmission starts.

Bit 2 RE : Receiver enable

This bit enables the receiver. It is set and cleared by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

Bit 1 RWU : Receiver wakeup

This bit determines if the USART is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wakeup sequence is recognized.

0: Receiver in active mode

1: Receiver in mute mode

Note: Before selecting Mute mode (by setting the RWU bit) the USART must first receive a data byte, otherwise it cannot function in Mute mode with wakeup by Idle line detection.

In Address Mark Detection wakeup configuration (WAKE bit=1) the RWU bit cannot be modified by software while the RXNE bit is set.

Bit 0 SBK : Send break

This bit set is used to send break characters. It can be set and cleared by software. It should be set by software, and will be reset by hardware during the stop bit of break.

0: No break character is transmitted

1: Break character will be transmitted

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

19.6.5 Control register 2 (USART_CR2)

Res.

Address offset: 0x10

LINEN rw

Reset value: 0x0000 0000

29 28

13 12

STOP[1:0] rw rw

11 10 9 8

CLKEN CPOL CPHA LBCL rw

26 rw

25 rw

24 23

Reserved rw

Res.

LBDIE LBDL rw

5 rw

20 19 18 17 16

Res.

3 rw

ADD[3:0]

1 rw rw

0 rw

Bits 31:15 Reserved, must be kept at reset value

Bit 14 LINEN : LIN mode enable

This bit is set and cleared by software.

0: LIN mode disabled

1: LIN mode enabled

The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBK bit in the USART_CR1 register, and to detect LIN Sync breaks.

Bits 13:12 STOP : STOP bits

These bits are used for programming the stop bits.

00: 1 Stop bit

01: 0.5 Stop bit

10: 2 Stop bits

Note: 11: 1.5 Stop bit

Bit 11 CLKEN : Clock enable

This bit allows the user to enable the CK pin.

0: CK pin disabled

1: CK pin enabled

Bit 10 CPOL : Clock polarity

This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode.

It works in conjunction with the CPHA bit to produce the desired clock/data relationship

0: Steady low value on CK pin outside transmission window.

1: Steady high value on CK pin outside transmission window.

Bit 9 CPHA : Clock phase

This bit allows the user to select the phase of the clock output on the CK pin in synchronous mode.

It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see figures

179

180

)

Note: 0: The first clock transition is the first data capture edge

1: The second clock transition is the first data capture edge

Bit 8 LBCL : Last bit clock pulse

This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode.

0: The clock pulse of the last data bit is not output to the CK pin

1: The clock pulse of the last data bit is output to the CK pin

1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by the M bit in the USART_CR1 register.

Bit 7 Reserved, must be kept at reset value

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RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

Bit 6 LBDIE : LIN break detection interrupt enable

Break interrupt mask (break detection using break delimiter).

0: Interrupt is inhibited

1: An interrupt is generated whenever LBD=1 in the USART_SR register

Bit 5 LBDL : lin break detection length

This bit is for selection between 11 bit or 10 bit break detection.

0: 10-bit break detection

1: 11-bit break detection

Bit 4 Reserved, must be kept at reset value

Bits 3:0 ADD[3:0] : Address of the USART node

This bit-field gives the address of the USART node.

This is used in multiprocessor communication during mute mode, for wake up with address mark detection.

Note: These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.

19.6.6 Control register 3 (USART_CR3)

Address offset: 0x14

Reset value: 0x0000 0000

Reserved

27 26 25 24 23

Reserved

22 21 20 19 18

11 10 9 8 7 6 5 4 3 2

ONEBIT CTSIE CTSE RTSE DMAT DMAR SCEN NACK HDSEL IRLP rw rw rw rw rw rw rw rw rw rw

17 16

IREN rw

EIE rw

Bits 31:12 Reserved, must be kept at reset value

Bit 11 ONEBIT : One sample bit method enable

This bit allows the user to select the sample method. When the one sample bit method is selected the noise detection flag (NF) is disabled.

0: Three sample bit method

1: One sample bit method

Note: The ONEBIT feature applies only to data bits. It does not apply to START bit.

Bit 10 CTSIE : CTS interrupt enable

Note: 0: Interrupt is inhibited

1: An interrupt is generated whenever CTS=1 in the USART_SR register

Bit 9 CTSE : CTS enable

0: CTS hardware flow control disabled

Note: 1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to

0). If the CTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping. If a data is written into the data register while CTS is deasserted, the transmission is postponed until CTS is asserted.

Bit 8 RTSE : RTS enable

0: RTS hardware flow control disabled

Note: 1: RTS interrupt enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is asserted (tied to 0) when a data can be received.

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Universal synchronous asynchronous receiver transmitter (USART) RM0368

Bit 7 DMAT : DMA enable transmitter

This bit is set/reset by software

1: DMA mode is enabled for transmission.

0: DMA mode is disabled for transmission.

Bit 6 DMAR : DMA enable receiver

This bit is set/reset by software

1: DMA mode is enabled for reception

0: DMA mode is disabled for reception

Bit 5 SCEN : Smartcard mode enable

This bit is used for enabling Smartcard mode.

Note: 0: Smartcard Mode disabled

1: Smartcard Mode enabled

Bit 4 NACK : Smartcard NACK enable

Note: 0: NACK transmission in case of parity error is disabled

1: NACK transmission during parity error is enabled

Bit 3 HDSEL : Half-duplex selection

Selection of Single-wire Half-duplex mode

0: Half duplex mode is not selected

1: Half duplex mode is selected

Bit 2 IRLP : IrDA low-power

This bit is used for selecting between normal and low-power IrDA modes

0: Normal mode

1: Low-power mode

Bit 1 IREN : IrDA mode enable

This bit is set and cleared by software.

0: IrDA disabled

1: IrDA enabled

Bit 0 EIE : Error interrupt enable

Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).

0: Interrupt is inhibited

1: An interrupt is generated whenever DMAR=1 in the USART_CR3 register and FE=1 or

ORE=1 or NF=1 in the USART_SR register.

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RM0368 Rev 5

RM0368 Universal synchronous asynchronous receiver transmitter (USART)

19.6.7 Guard time and prescaler register (USART_GTPR)

31 30

Address offset: 0x18

Reset value: 0x0000 0000

29 28 27 26 25 22 21 20

15 14 13 10 9

24 23

Reserved

8 7 6 5 rw rw rw

GT[7:0]

11 rw rw rw rw rw rw rw rw

PSC[7:0]

3 rw rw

0 rw rw rw

Bits 31:16 Reserved, must be kept at reset value

Bits 15:8 GT[7:0] : Guard time value

This bit-field gives the Guard time value in terms of number of baud clocks.

Note: This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value.

Bits 7:0 PSC[7:0] : Prescaler value

– In IrDA Low-power mode:

PSC[7:0] = IrDA Low-Power Baud Rate

Used for programming the prescaler for dividing the system clock to achieve the low-power frequency:

The source clock is divided by the value given in the register (8 significant bits):

00000000: Reserved - do not program this value

00000001: divides the source clock by 1

00000010: divides the source clock by 2

...

– In normal IrDA mode: PSC must be set to 00000001.

– In smartcard mode:

PSC[4:0] : Prescaler value

Used for programming the prescaler for dividing the system clock to provide the smartcard clock.

The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency:

00000: Reserved - do not program this value

00001: divides the source clock by 2

00010: divides the source clock by 4

00011: divides the source clock by 6

...

Note: 1: Bits [7:5] have no effect if Smartcard mode is used.

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Universal synchronous asynchronous receiver transmitter (USART)

19.6.8 USART register map

The table below gives the USART register map and reset values.

Table 89. USART register map and reset values

Offset Register

0x00

0x04

0x08

USART_SR

Reset value

USART_DR

Reset value

USART_BRR

Reset value

0x0C

USART_CR1

0x10

Reset value

USART_CR2

Reset value

USART_CR3

0x14

Reset value

0x18

USART_GTPR

Reset value

Reserved

RM0368

0 0 1 1 0 0 0 0 0 0

DR[8:0]

0 0 0 0 0 0 0 0 0

DIV_Mantissa[15:4]

DIV_Fraction

[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STOP

[1:0]

ADD[3:0]

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

GT[7:0] PSC[7:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

interface pins, please refer to Section 8.3.2: I/O pin multiplexer and mapping .

for the register boundary addresses.

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RM0368 Rev 5

RM0368

20 Serial peripheral interface (SPI)

Serial peripheral interface (SPI)

The SPI interface provides two main functions, supporting either the SPI protocol or the I

S audio protocol. By default, it is the SPI function that is selected. It is possible to switch the interface from SPI to I

S by software.

The serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial communication with external devices. The interface can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster configuration.

It may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

The I

S is also a synchronous serial communication interface. It can address four different audio standards including the I

S Philips standard, the MSB- and LSB-justified standards, and the PCM standard. It can operate as a slave or a master device in full-duplex mode

(using 4 pins) or in half-duplex mode (using 3 pins). Master clock can be provided by the interface to an external slave component when the I

S is configured as the communication master.

Warning: Since some SPI1 and SPI3/I2S3 pins may be mapped onto some pins used by the JTAG interface (SPI1_NSS onto JTDI,

SPI3_NSS/I2S3_WS onto JTDI and SPI3_SCK/I2S3_CK onto

JTDO), you may either:

– map SPI/I2S onto other pins

– disable the JTAG and use the SWD interface prior to configuring the pins listed as SPI I/Os (when debugging the application) or

– disable both JTAG/SWD interfaces (for standalone applications).

For more information on the configuration of the JTAG/SWD

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Serial peripheral interface (SPI)

20.2 SPI and I

2 S main features

RM0368

• Full-duplex synchronous transfers on three lines

• Simplex synchronous transfers on two lines with or without a bidirectional data line

• 8- or 16-bit transfer frame format selection

• Master or slave operation

• Multimaster mode capability

• 8 master mode baud rate prescalers (f

PCLK

/2 max.)

• Slave mode frequency (f

PCLK

/2 max)

• Faster communication for both master and slave

• NSS management by hardware or software for both master and slave: dynamic change of master/slave operations

• Programmable clock polarity and phase

• Programmable data order with MSB-first or LSB-first shifting

• Dedicated transmission and reception flags with interrupt capability

• SPI bus busy status flag

• SPI TI mode

• Hardware CRC feature for reliable communication:

– CRC value can be transmitted as last byte in Tx mode

– Automatic CRC error checking for last received byte

• Master mode fault, overrun and CRC error flags with interrupt capability

• 1-byte transmission and reception buffer with DMA capability: Tx and Rx requests

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RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

20.2.2 I

S features

• Full duplex communication

• Half-duplex communication (only transmitter or receiver)

• Master or slave operations

• 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from

8 kHz to 192 kHz)

• Data format may be 16-bit, 24-bit or 32-bit

• Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data frame) by audio channel

• Programmable clock polarity (steady state)

• Underrun flag in slave transmission mode, overrun flag in reception mode (master and slave), and Frame Error flag in reception and transmission mode (slave only)

• 16-bit register for transmission and reception with one data register for both channel sides

• Supported I 2 S protocols:

– I 2 S Phillps standard

– MSB-justified standard (left-justified)

– LSB-justified standard (right-justified)

– PCM standard (with short and long frame synchronization on 16-bit channel frame or 16-bit data frame extended to 32-bit channel frame)

• Data direction is always MSB first

• DMA capability for transmission and reception (16-bit wide)

• Master clock may be output to drive an external audio component. Ratio is fixed at

256 × F

(where F

is the audio sampling frequency)

• Both I 2 S (I2S2 and I2S3) have a dedicated PLL (PLLI2S) to generate an even more accurate clock.

• I 2 S (I2S2 and I2S3) clock can be derived from an external clock mapped on the

I2S_CKIN pin.

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Serial peripheral interface (SPI)

20.3 SPI functional description

RM0368

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The block diagram of the SPI is shown in

Figure 192

Figure 192. SPI block diagram

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Usually, the SPI is connected to external devices through four pins:

• MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode and receive data in master mode.

• MOSI: Master Out / Slave In data. This pin can be used to transmit data in master mode and receive data in slave mode.

• SCK: Serial Clock output for SPI masters and input for SPI slaves.

• NSS: Slave select. This is an optional pin to select a slave device. This pin acts as a

‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave NSS inputs can be driven by standard IO ports on the master device. The NSS pin may also be used as an output if enabled (SSOE bit) and driven low if the SPI is in master configuration. In this manner, all NSS pins from devices connected to the Master NSS pin see a low level and become slaves when they are configured in NSS hardware mode. When configured in master mode with

NSS configured as an input (MSTR=1 and SSOE=0) and if NSS is pulled low, the SPI enters the master mode fault state: the MSTR bit is automatically cleared and the device is configured in slave mode (refer to

Section 20.3.10

A basic example of interconnections between a single master and a single slave is

illustrated in Figure 193 .

RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

Figure 193. Single master/ single slave application

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1. Here, the NSS pin is configured as an input.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits data to a slave device via the MOSI pin, the slave device responds via the MISO pin. This implies full-duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

Slave select (NSS) pin management

Hardware or software slave select management can be set using the SSM bit in the

SPI_CR1 register.

• Software NSS management (SSM = 1)

The slave select information is driven internally by the value of the SSI bit in the

SPI_CR1 register. The external NSS pin remains free for other application uses.

• Hardware NSS management (SSM = 0)

Two configurations are possible depending on the NSS output configuration (SSOE bit in register SPI_CR2).

– NSS output enabled (SSM = 0, SSOE = 1)

This configuration is used only when the device operates in master mode. The

NSS signal is driven low when the master starts the communication and is kept low until the SPI is disabled.

– NSS output disabled (SSM = 0, SSOE = 0)

This configuration allows multimaster capability for devices operating in master mode. For devices set as slave, the NSS pin acts as a classical NSS input: the slave is selected when NSS is low and deselected when NSS high.

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Serial peripheral interface (SPI)

Note:

RM0368

Clock phase and clock polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. If

CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a high-level idle state.

If the CPHA (clock phase) bit is set, the second edge on the SCK pin (falling edge if the

CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data are latched on the occurrence of the second clock transition. If the CPHA bit is reset, the first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the

MSBit capture strobe. Data are latched on the occurrence of the first clock transition.

The combination of the CPOL (clock polarity) and CPHA (clock phase) bits selects the data capture clock edge.

Figure 194 , shows an SPI transfer with the four combinations of the CPHA and CPOL bits.

The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device.

Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.

Master and slave must be programmed with the same timing mode.

The idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

The Data Frame Format (8- or 16-bit) is selected through the DFF bit in SPI_CR1 register, and determines the data length during transmission/reception.

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RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

Figure 194. Data clock timing diagram

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1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.

Data frame format

Data can be shifted out either MSB-first or LSB-first depending on the value of the

LSBFIRST bit in the SPI_CR1 Register.

Each data frame is 8 or 16 bits long depending on the size of the data programmed using the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for transmission and/or reception.

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Serial peripheral interface (SPI) RM0368

20.3.2 Configuring the SPI in slave mode

Note:

In the slave configuration, the serial clock is received on the SCK pin from the master device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer rate.

It is recommended to enable the SPI slave before the master sends the clock. If not, undesired data transmission might occur. The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication. It is mandatory to have the polarity of the communication clock set to the steady state value before the slave and the master are enabled.

Follow the procedure below to configure the SPI in slave mode:

Procedure

Set the DFF bit to define 8- or 16-bit data frame format

2. Select the CPOL and CPHA bits to define one of the four relationships between the

data transfer and the serial clock (see Figure 194 ). For correct data transfer, the CPOL

and CPHA bits must be configured in the same way in the slave device and the master device. This step is not required when the TI mode is selected through the FRF bit in the SPI_CR2 register.

3. The frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in the SPI_CR1 register) must be the same as the master device. This step is not required when TI mode is selected.

4. In Hardware mode (refer to

Slave select (NSS) pin management ), the NSS pin must be

connected to a low level signal during the complete byte transmit sequence. In NSS software mode, set the SSM bit and clear the SSI bit in the SPI_CR1 register. This step is not required when TI mode is selected.

5. Set the FRF bit in the SPI_CR2 register to select the TI mode protocol for serial communications.

6. Clear the MSTR bit and set the SPE bit (both in the SPI_CR1 register) to assign the pins to alternate functions.

In this configuration the MOSI pin is a data input and the MISO pin is a data output.

Transmit sequence

The data byte is parallel-loaded into the Tx buffer during a write cycle.

The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. The remaining bits (the 7 bits in 8-bit data frame format, and the 15 bits in 16-bit data frame format) are loaded into the shift-register. The

TXE flag in the SPI_SR register is set on the transfer of data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.

Receive sequence

For the receiver, when data transfer is complete:

• The Data in shift register is transferred to Rx Buffer and the RXNE flag (SPI_SR register) is set

• An Interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register.

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RM0368 Rev 5

.33

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RM0368

Note:

Serial peripheral interface (SPI)

After the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI peripheral returns this buffered value.

Clearing of the RXNE bit is performed by reading the SPI_DR register.

SPI TI protocol in slave mode

In slave mode, the SPI interface is compatible with the TI protocol. The FRF bit of the

SPI_CR2 register can be used to configure the slave SPI serial communications to be compliant with this protocol.

The clock polarity and phase are forced to conform to the TI protocol requirements whatever the values set in the SPI_CR1 register. NSS management is also specific to the TI protocol which makes the configuration of NSS management through the SPI_CR1 and SPI_CR2 registers (such as SSM, SSI, SSOE) transparent for the user.

In Slave mode (

Figure 195: TI mode - Slave mode, single transfer

and Figure 196: TI mode

- Slave mode, continuous transfer

), the SPI baud rate prescaler is used to control the moment when the MISO pin state changes to HI-Z. Any baud rate can be used thus allowing to determine this moment with optimal flexibility. However, the baud rate is generally set to the external master clock baud rate. The time for the MISO signal to become HI-Z (t release

) depends on internal resynchronizations and on the baud rate value set in through BR[2:0] of

SPI_CR1 register. It is given by the formula: tbaud_rate

+ 4 × tpclk < trelease < tbaud_rate

+ 6 × tpclk

This feature is not available for Motorola SPI communications (FRF bit set to 0).

To detect TI frame errors in Slave transmitter only mode by using the Error interrupt (ERRIE

= 1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and

BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupt are always generated, while when

BIDIMODE is set to 1, data are not received and OVR is never set.

Figure 195. TI mode - Slave mode, single transfer

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Serial peripheral interface (SPI)

Figure 196. TI mode - Slave mode, continuous transfer

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In the master configuration, the serial clock is generated on the SCK pin.

Procedure

Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).

2. Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see

Figure 194

). This step is not required when the

TI mode is selected.

3. Set the DFF bit to define 8- or 16-bit data frame format

4. Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format. This step is not required when the TI mode is selected.

5. If the NSS pin is required in input mode, in hardware mode, connect the NSS pin to a high-level signal during the complete byte transmit sequence. In NSS software mode, set the SSM and SSI bits in the SPI_CR1 register. If the NSS pin is required in output mode, the SSOE bit only should be set. This step is not required when the TI mode is selected.

6. Set the FRF bit in SPI_CR2 to select the TI protocol for serial communications.

7. The MSTR and SPE bits must be set (they remain set only if the NSS pin is connected to a high-level signal).

In this configuration the MOSI pin is a data output and the MISO pin is a data input.

Transmit sequence

The transmit sequence begins when a byte is written in the Tx Buffer.

The data byte is parallel-loaded into the shift register (from the internal bus) during the first bit transmission and then shifted out serially to the MOSI pin MSB first or LSB first depending on the LSBFIRST bit in the SPI_CR1 register. The TXE flag is set on the transfer of data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.

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Receive sequence

For the receiver, when data transfer is complete:

• The data in the shift register is transferred to the RX Buffer and the RXNE flag is set

• An interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register

At the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI peripheral returns this buffered value.

Clearing the RXNE bit is performed by reading the SPI_DR register.

A continuous transmit stream can be maintained if the next data to be transmitted is put in the Tx buffer once the transmission is started. Note that TXE flag should be ‘1 before any attempt to write the Tx buffer is made.

When a master is communicating with SPI slaves which need to be de-selected between transmissions, the NSS pin must be configured as GPIO or another GPIO must be used and toggled by software.

SPI TI protocol in master mode

In master mode, the SPI interface is compatible with the TI protocol. The FRF bit of the

SPI_CR2 register can be used to configure the master SPI serial communications to be compliant with this protocol.

Figure 197: TI mode - master mode, single transfer

and Figure 198: TI mode - master mode, continuous transfer

) show the SPI master communication waveforms when the TI mode is selected in master mode.

Figure 197. TI mode - master mode, single transfer

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20.3.4 Configuring the SPI for half-duplex communication

The SPI is capable of operating in half-duplex mode in 2 configurations.

• 1 clock and 1 bidirectional data wire

• 1 clock and 1 data wire (receive-only or transmit-only)

1 clock and 1 bidirectional data wire (BIDIMODE = 1)

This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register. In this mode

SCK is used for the clock and MOSI in master or MISO in slave mode is used for data communication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the

SPI_CR1 register. When this bit is 1, the data line is output otherwise it is input.

1 clock and 1 unidirectional data wire (BIDIMODE = 0)

In this mode, the application can use the SPI either in transmit-only mode or in receive-only mode.

• Transmit-only mode is similar to full-duplex mode (BIDIMODE=0, RXONLY=0): the data are transmitted on the transmit pin (MOSI in master mode or MISO in slave mode) and the receive pin (MISO in master mode or MOSI in slave mode) can be used as a general-purpose IO. In this case, the application just needs to ignore the Rx buffer (if the data register is read, it does not contain the received value).

• In receive-only mode, the application can disable the SPI output function by setting the

RXONLY bit in the SPI_CR1 register. In this case, it frees the transmit IO pin (MOSI in master mode or MISO in slave mode), so it can be used for other purposes.

To start the communication in receive-only mode, configure and enable the SPI:

• In master mode, the communication starts immediately and stops when the SPE bit is cleared and the current reception stops. There is no need to read the BSY flag in this mode. It is always set when an SPI communication is ongoing.

• In slave mode, the SPI continues to receive as long as the NSS is pulled down (or the

SSI bit is cleared in NSS software mode) and the SCK is running.

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RM0368 Serial peripheral interface (SPI)

20.3.5 Data transmission and reception procedures

Rx and Tx buffers

In reception, data are received and then stored into an internal Rx buffer while In transmission, data are first stored into an internal Tx buffer before being transmitted.

A read access of the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer.

Start sequence in master mode

• In full-duplex (BIDIMODE=0 and RXONLY=0)

– The sequence begins when data are written into the SPI_DR register (Tx buffer).

– The data are then parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission and then shifted out serially to the MOSI pin.

– At the same time, the received data on the MISO pin is shifted in serially to the 8bit shift register and then parallel loaded into the SPI_DR register (Rx buffer).

• In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)

– The sequence begins as soon as SPE=1

– Only the receiver is activated and the received data on the MISO pin are shifted in serially to the 8-bit shift register and then parallel loaded into the SPI_DR register

(Rx buffer).

• In bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)

– The sequence begins when data are written into the SPI_DR register (Tx buffer).

– The data are then parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission and then shifted out serially to the MOSI pin.

– No data are received.

• In bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)

– The sequence begins as soon as SPE=1 and BIDIOE=0.

– The received data on the MOSI pin are shifted in serially to the 8-bit shift register and then parallel loaded into the SPI_DR register (Rx buffer).

– The transmitter is not activated and no data are shifted out serially to the MOSI pin.

Start sequence in slave mode

• In full-duplex mode (BIDIMODE=0 and RXONLY=0)

– The sequence begins when the slave device receives the clock signal and the first bit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift register.

– At the same time, the data are parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission, and then shifted out serially to the MISO

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RM0368 pin. The software must have written the data to be sent before the SPI master device initiates the transfer.

• In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)

– The sequence begins when the slave device receives the clock signal and the first bit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift register.

– The transmitter is not activated and no data are shifted out serially to the MISO pin.

• In bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)

– The sequence begins when the slave device receives the clock signal and the first bit in the Tx buffer is transmitted on the MISO pin.

– The data are then parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission and then shifted out serially to the MISO pin. The software must have written the data to be sent before the SPI master device initiates the transfer.

– No data are received.

• In bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)

– The sequence begins when the slave device receives the clock signal and the first bit of the data on its MISO pin.

– The received data on the MISO pin are shifted in serially to the 8-bit shift register and then parallel loaded into the SPI_DR register (Rx buffer).

– The transmitter is not activated and no data are shifted out serially to the MISO pin.

Handling data transmission and reception

The TXE flag (Tx buffer empty) is set when the data are transferred from the Tx buffer to the shift register. It indicates that the internal Tx buffer is ready to be loaded with the next data.

An interrupt can be generated if the TXEIE bit in the SPI_CR2 register is set. Clearing the

TXE bit is performed by writing to the SPI_DR register.

The software must ensure that the TXE flag is set to 1 before attempting to write to the Tx buffer. Otherwise, it overwrites the data previously written to the Tx buffer.

The RXNE flag (Rx buffer not empty) is set on the last sampling clock edge, when the data are transferred from the shift register to the Rx buffer. It indicates that data are ready to be read from the SPI_DR register. An interrupt can be generated if the RXNEIE bit in the

SPI_CR2 register is set. Clearing the RXNE bit is performed by reading the SPI_DR register.

For some configurations, the BSY flag can be used during the last data transfer to wait until the completion of the transfer.

Full-duplex transmit and receive procedure in master or slave mode (BIDIMODE=0 and

RXONLY=0)

The software has to follow this procedure to transmit and receive data (see

Figure 199

and

Figure 200 ):

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Figure 199. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and

RXONLY=0) in case of continuous transfers

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Enable the SPI by setting the SPE bit to 1.

2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag).

3. Wait until TXE=1 and write the second data item to be transmitted. Then wait until

RXNE=1 and read the SPI_DR to get the first received data item (this clears the RXNE bit). Repeat this operation for each data item to be transmitted/received until the n–1 received data.

4. Wait until RXNE=1 and read the last received data.

5. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI.

This procedure can also be implemented using dedicated interrupt subroutines launched at each rising edges of the RXNE or TXE flag.

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Figure 200. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,

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Transmit-only procedure (BIDIMODE=0 RXONLY=0)

In this mode, the procedure can be reduced as described below and the BSY bit can be used to wait until the completion of the transmission (see

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Figure 202

Enable the SPI by setting the SPE bit to 1.

2. Write the first data item to send into the SPI_DR register (this clears the TXE bit).

3. Wait until TXE=1 and write the next data item to be transmitted. Repeat this step for each data item to be transmitted.

4. After writing the last data item into the SPI_DR register, wait until TXE=1, then wait until

BSY=0, this indicates that the transmission of the last data is complete.

This procedure can be also implemented using dedicated interrupt subroutines launched at each rising edge of the TXE flag.

During discontinuous communications, there is a 2 APB clock period delay between the write operation to SPI_DR and the BSY bit setting. As a consequence, in transmit-only mode, it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data.

After transmitting two data items in transmit-only mode, the OVR flag is set in the SPI_SR register since the received data are never read.

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Figure 201. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers

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Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)

In this mode, the procedure is similar to the procedure in Transmit-only mode except that the BIDIMODE and BIDIOE bits both have to be set in the SPI_CR2 register before enabling the SPI.

Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)

In this mode, the procedure can be reduced as described below (see

Figure 203 ):

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Set the RXONLY bit in the SPI_CR1 register.

2. Enable the SPI by setting the SPE bit to 1: a) In master mode, this immediately activates the generation of the SCK clock, and data are serially received until the SPI is disabled (SPE=0).

b) In slave mode, data are received when the SPI master device drives NSS low and generates the SCK clock.

3. Wait until RXNE=1 and read the SPI_DR register to get the received data (this clears the RXNE bit). Repeat this operation for each data item to be received.

This procedure can also be implemented using dedicated interrupt subroutines launched at each rising edge of the RXNE flag.

If it is required to disable the SPI after the last transfer, follow the recommendation described in

Section 20.3.8

Figure 203. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers

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Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0)

In this mode, the procedure is similar to the Receive-only mode procedure except that the

BIDIMODE bit has to be set and the BIDIOE bit cleared in the SPI_CR2 register before enabling the SPI.

Continuous and discontinuous transfers

When transmitting data in master mode, if the software is fast enough to detect each rising edge of TXE (or TXE interrupt) and to immediately write to the SPI_DR register before the ongoing data transfer is complete, the communication is said to be continuous. In this case, there is no discontinuity in the generation of the SPI clock between each data item and the

BSY bit is never cleared between each data transfer.

On the contrary, if the software is not fast enough, this can lead to some discontinuities in the communication. In this case, the BSY bit is cleared between each data transmission

(see Figure 204 ).

In Master receive-only mode (RXONLY=1), the communication is always continuous and the BSY flag is always read at 1.

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In slave mode, the continuity of the communication is decided by the SPI master device. In any case, even if the communication is continuous, the BSY flag goes low between each transfer for a minimum duration of one SPI clock cycle (see

Figure 202

Figure 204. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers

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Note:

A CRC calculator has been implemented for communication reliability. Separate CRC calculators are implemented for transmitted data and received data. The CRC is calculated using a programmable polynomial serially on each bit. It is calculated on the sampling clock edge defined by the CPHA and CPOL bits in the SPI_CR1 register.

This SPI offers two kinds of CRC calculation standard which depend directly on the data frame format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data

(CRC16).

CRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action resets the CRC registers (SPI_RXCRCR and SPI_TXCRCR). In full duplex or transmitter only mode, when the transfers are managed by the software (CPU mode), it is necessary to write the bit CRCNEXT immediately after the last data to be transferred is written to the

SPI_DR. At the end of this last data transfer, the SPI_TXCRCR value is transmitted.

In receive only mode and when the transfers are managed by software (CPU mode), it is necessary to write the CRCNEXT bit after the second last data has been received. The CRC is received just after the last data reception and the CRC check is then performed.

At the end of data and CRC transfers, the CRCERR flag in the SPI_SR register is set if corruption occurs during the transfer.

If data are present in the TX buffer, the CRC value is transmitted only after the transmission of the data byte. During CRC transmission, the CRC calculator is switched off and the register value remains unchanged.

SPI communication using the CRC is possible through the following procedure:

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Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values.

2. Program the polynomial in the SPI_CRCPR register.

3. Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also clears the SPI_RXCRCR and SPI_TXCRCR registers.

4. Enable the SPI by setting the SPE bit in the SPI_CR1 register.

5. Start the communication and sustain the communication until all but one byte or halfword have been transmitted or received.

– In full duplex or transmitter-only mode, when the transfers are managed by software, when writing the last byte or half word to the Tx buffer, set the

CRCNEXT bit in the SPI_CR1 register to indicate that the CRC will be transmitted after the transmission of the last byte.

– In receiver only mode, set the bit CRCNEXT just after the reception of the second to last data to prepare the SPI to enter in CRC Phase at the end of the reception of the last data. CRC calculation is frozen during the CRC transfer.

6. After the transfer of the last byte or half word, the SPI enters the CRC transfer and check phase. In full duplex mode or receiver-only mode, the received CRC is compared to the SPI_RXCRCR value. If the value does not match, the CRCERR flag in

SPI_SR is set and an interrupt can be generated when the ERRIE bit in the SPI_CR2 register is set.

When the SPI is in slave mode, be careful to enable CRC calculation only when the clock is stable, that is, when the clock is in the steady state. If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive to the SCK slave input clock as soon as CRCEN is set, and this, whatever the value of the SPE bit.

With high bitrate frequencies, be careful when transmitting the CRC. As the number of used

CPU cycles has to be as low as possible in the CRC transfer phase, it is forbidden to call software functions in the CRC transmission sequence to avoid errors in the last data and

CRC reception. In fact, CRCNEXT bit has to be written before the end of the transmission/reception of the last data.

For high bit rate frequencies, it is advised to use the DMA mode to avoid the degradation of the SPI speed performance due to CPU accesses impacting the SPI bandwidth.

When the devices are configured as slaves and the NSS hardware mode is used, the NSS pin needs to be kept low between the data phase and the CRC phase.

When the SPI is configured in slave mode with the CRC feature enabled, CRC calculation takes place even if a high level is applied on the NSS pin. This may happen for example in case of a multislave environment where the communication master addresses slaves alternately.

Between a slave deselection (high level on NSS) and a new slave selection (low level on

NSS), the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation.

To clear the CRC, follow the procedure below:

Disable SPI (SPE = 0)

2. Clear the CRCEN bit

3. Set the CRCEN bit

4. Enable the SPI (SPE = 1)

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Note:

Four status flags are provided for the application to completely monitor the state of the SPI bus.

Tx buffer empty flag (TXE)

When it is set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can be loaded into the buffer. The TXE flag is cleared when writing to the

SPI_DR register.

Rx buffer not empty (RXNE)

When set, this flag indicates that there are valid received data in the Rx buffer. It is cleared when SPI_DR is read.

BUSY flag

This BSY flag is set and cleared by hardware (writing to this flag has no effect). The BSY flag indicates the state of the communication layer of the SPI.

When BSY is set, it indicates that the SPI is busy communicating. There is one exception in master mode / bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0) where the

BSY flag is kept low during reception.

The BSY flag is useful to detect the end of a transfer if the software wants to disable the SPI and enter Halt mode (or disable the peripheral clock). This avoids corrupting the last transfer. For this, the procedure described below must be strictly respected.

The BSY flag is also useful to avoid write collisions in a multimaster system.

The BSY flag is set when a transfer starts, with the exception of master mode / bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0).

It is cleared:

• when a transfer is finished (except in master mode if the communication is continuous)

• when the SPI is disabled

• when a master mode fault occurs (MODF=1)

When communication is not continuous, the BSY flag is low between each communication.

When communication is continuous:

• in master mode, the BSY flag is kept high during all the transfers

• in slave mode, the BSY flag goes low for one SPI clock cycle between each transfer

Do not use the BSY flag to handle each data transmission or reception. It is better to use the

TXE and RXNE flags instead.

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20.3.8 Disabling the SPI

When a transfer is terminated, the application can stop the communication by disabling the

SPI peripheral. This is done by clearing the SPE bit.

For some configurations, disabling the SPI and entering the Halt mode while a transfer is ongoing can cause the current transfer to be corrupted and/or the BSY flag might become unreliable.

To avoid any of those effects, it is recommended to respect the following procedure when disabling the SPI:

In master or slave full-duplex mode (BIDIMODE=0, RXONLY=0)

Wait until RXNE=1 to receive the last data

2. Wait until TXE=1

3. Then wait until BSY=0

4. Disable the SPI (SPE=0) and, eventually, enter the Halt mode (or disable the peripheral clock)

Note:

In master or slave unidirectional transmit-only mode (BIDIMODE=0,

RXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1)

After the last data is written into the SPI_DR register:

Wait until TXE=1

2. Then wait until BSY=0

3. Disable the SPI (SPE=0) and, eventually, enter the Halt mode (or disable the peripheral clock)

In master unidirectional receive-only mode (MSTR=1, BIDIMODE=0,

RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0)

This case must be managed in a particular way to ensure that the SPI does not initiate a new transfer. The sequence below is valid only for SPI Motorola configuration (FRF bit set to

0):

Wait for the second to last occurrence of RXNE=1 (n–1)

2. Then wait for one SPI clock cycle (using a software loop) before disabling the SPI

(SPE=0)

3. Then wait for the last RXNE=1 before entering the Halt mode (or disabling the peripheral clock)

When the SPI is configured in TI mode (Bit FRF set to 1), the following procedure has to be respected to avoid generating an undesired pulse on NSS when the SPI is disabled:

Wait for the second to last occurrence of RXNE = 1 (n-1).

2. Disable the SPI (SPE = 0) in the following window frame using a software loop:

– After at least one SPI clock cycle,

– Before the beginning of the LSB data transfer.

In master bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0), the BSY flag is kept low during transfers.

580/847

RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0)

You can disable the SPI (write SPE=1) at any time: the current transfer will complete before the SPI is effectively disabled

2. Then, if you want to enter the Halt mode, you must first wait until BSY = 0 before entering the Halt mode (or disabling the peripheral clock).

Note:

To operate at its maximum speed, the SPI needs to be fed with the data for transmission and the data received on the Rx buffer should be read to avoid overrun. To facilitate the transfers, the SPI features a DMA capability implementing a simple request/acknowledge protocol.

A DMA access is requested when the enable bit in the SPI_CR2 register is enabled.

Separate requests must be issued to the Tx and Rx buffers (see Figure 205

and

Figure 206 ):

• In transmission, a DMA request is issued each time TXE is set to 1. The DMA then writes to the SPI_DR register (this clears the TXE flag).

• In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads the SPI_DR register (this clears the RXNE flag).

When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA channel. In this case, the OVR flag is set because the data received are not read.

When the SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel.

In transmission mode, when the DMA has written all the data to be transmitted (flag TCIF is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI communication is complete. This is required to avoid corrupting the last transmission before disabling the SPI or entering the Stop mode. The software must first wait until TXE=1 and then until BSY=0.

During discontinuous communications, there is a 2 APB clock period delay between the write operation to SPI_DR and the BSY bit setting. As a consequence, it is mandatory to wait first until TXE=1 and then until BSY=0 after writing the last data.

RM0368 Rev 5

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Serial peripheral interface (SPI) RM0368

Figure 205. Transmission using DMA

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582/847

RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

DMA capability with CRC

When SPI communication is enabled with CRC communication and DMA mode, the transmission and reception of the CRC at the end of communication are automatic that is without using the bit CRCNEXT. After the CRC reception, the CRC must be read in the

SPI_DR register to clear the RXNE flag.

At the end of data and CRC transfers, the CRCERR flag in SPI_SR is set if corruption occurs during the transfer.

Master mode fault (MODF)

Master mode fault occurs when the master device has its NSS pin pulled low (in NSS hardware mode) or SSI bit low (in NSS software mode), this automatically sets the MODF bit. Master mode fault affects the SPI peripheral in the following ways:

• The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.

• The SPE bit is cleared. This blocks all output from the device and disables the SPI interface.

• The MSTR bit is cleared, thus forcing the device into slave mode.

Use the following software sequence to clear the MODF bit:

Make a read or write access to the SPI_SR register while the MODF bit is set.

2. Then write to the SPI_CR1 register.

To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can be restored to their original state after this clearing sequence.

As a security, hardware does not allow the setting of the SPE and MSTR bits while the

MODF bit is set.

In a slave device the MODF bit cannot be set. However, in a multimaster configuration, the device can be in slave mode with this MODF bit set. In this case, the MODF bit indicates that there might have been a multimaster conflict for system control. An interrupt routine can be used to recover cleanly from this state by performing a reset or returning to a default state.

Overrun condition

An overrun condition occurs when the master device has sent data bytes and the slave device has not cleared the RXNE bit resulting from the previous data byte transmitted.

When an overrun condition occurs:

• the OVR bit is set and an interrupt is generated if the ERRIE bit is set.

In this case, the receiver buffer contents will not be updated with the newly received data from the master device. A read from the SPI_DR register returns this byte. All other subsequently transmitted bytes are lost.

Clearing the OVR bit is done by a read from the SPI_DR register followed by a read access to the SPI_SR register.

RM0368 Rev 5

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.33

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Serial peripheral interface (SPI) RM0368

CRC error

This flag is used to verify the validity of the value received when the CRCEN bit in the

SPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value received in the shift register does not match the receiver SPI_RXCRCR value.

TI mode frame format error

A TI mode frame format error is detected when an NSS pulse occurs during an ongoing communication when the SPI is acting in slave mode and configured to conform to the TI mode protocol. When this error occurs, the FRE flag is set in the SPI_SR register. The SPI is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the next NSS pulse before starting a new transfer. The data may be corrupted since the error detection may result in the lost of two data bytes.

The FRE flag is cleared when SPI_SR register is read. If the bit ERRIE is set, an interrupt is generated on the NSS error detection. In this case, the SPI should be disabled because data consistency is no more guaranteed and communications should be reinitiated by the master when the slave SPI is re-enabled.

Figure 207. TI mode frame format error detection

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Table 90. SPI interrupt requests

Interrupt event Event flag

Transmit buffer empty flag

Receive buffer not empty flag

Master Mode fault event

Overrun error

CRC error flag

TI frame format error

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584/847

RM0368 Rev 5

RM0368

20.4 I

2 S functional description

20.4.1 I

S general description

The block diagram of the I 2

S is shown in Figure 208

Figure 208. I 2 S block diagram

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1. I2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I 2 S full duplex mode.

The SPI could function as an audio I 2 S interface when the I 2 S capability is enabled (by setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same pins, flags and interrupts as the SPI.

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Serial peripheral interface (SPI) RM0368

The I 2 S shares three common pins with the SPI:

• SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two timemultiplexed data channels (in half-duplex mode only).

• WS: Word Select (mapped on the NSS pin) is the data control signal output in master mode and input in slave mode.

• CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode and serial clock input in slave mode.

• I2S2ext_SD and I2S3ext_SD: additional pins (mapped on the MISO pin) to control the

I 2 S full duplex mode.

An additional pin could be used when a master clock output is needed for some external audio devices:

• MCK: Master Clock (mapped separately) is used, when the I

S is configured in master mode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this additional clock generated at a preconfigured frequency rate equal to 256 × F

is the audio sampling frequency.

, where

The I

S uses its own clock generator to produce the communication clock when it is set in master mode. This clock generator is also the source of the master clock output. Two additional registers are available in I

S mode. One is linked to the clock generator configuration SPI_I2SPR and the other one is a generic I

S configuration register

SPI_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock polarity, etc.).

The SPI_CR1 register and all CRC registers are not used in the I

S mode. Likewise, the

SSOE bit in the SPI_CR2 register and the MODF and CRCERR bits in the SPI_SR are not used.

The I

S uses the same SPI register for data transfer (SPI_DR) in 16-bit wide mode.

Note:

To support I2S full duplex mode, two extra I 2 S instances called extended I2Ss (I2S2_ext,

I2S3_ext) are available in addition to I2S2 and I2S3 (see Figure 209 ). The first I2S full-

duplex interface is consequently based on I2S2 and I2S2_ext, and the second one on I2S3 and I2S3_ext.

I2S2_ext an I2S3_ext are used only in full-duplex mode.

Figure 209. I2S full duplex block diagram

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586/847

RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

I2Sx can operate in master mode. As a result:

• Only I2Sx can output SCK and WS in half duplex mode

• Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full duplex mode.

The extended I2Ss (I2Sx_ext) can be used only in full duplex mode. The I2Sx_ext operate always in slave mode.

Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.

20.4.3 Supported audio protocols

The four-line bus has to handle only audio data generally time-multiplexed on two channels: the right channel and the left channel. However there is only one 16-bit register for the transmission and the reception. So, it is up to the software to write into the data register the adequate value corresponding to the considered channel side, or to read the data from the data register and to identify the corresponding channel by checking the CHSIDE bit in the

SPI_SR register. Channel Left is always sent first followed by the channel right (CHSIDE has no meaning for the PCM protocol).

Four data and packet frames are available. Data may be sent with a format of:

• 16-bit data packed in 16-bit frame

• 16-bit data packed in 32-bit frame

• 24-bit data packed in 32-bit frame

• 32-bit data packed in 32-bit frame

When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only one read/write operation).

The 24-bit and 32-bit data frames need two CPU read or write operations to/from the

SPI_DR or two DMA operations if the DMA is preferred for the application. For 24-bit data frame specifically, the 8 nonsignificant bits are extended to 32 bits with 0-bits (by hardware).

For all data formats and communication standards, the most significant bit is always sent first (MSB first).

The I

S interface supports four audio standards, configurable using the I2SSTD[1:0] and

PCMSYNC bits in the SPI_I2SCFGR register.

I

S Philips standard

For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available.

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Figure 210. I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)

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Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver). The WS signal is also latched on the falling edge of CK.

Figure 211. I 2 S Philips standard waveforms (24-bit frame with CPOL = 0)

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This mode needs two write or read operations to/from the SPI_DR.

• In transmission mode: if 0x8EAA33 has to be sent (24-bit):

Figure 212. Transmitting 0x8EAA33

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• In reception mode: if data 0x8EAA33 is received:

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RM0368 Serial peripheral interface (SPI)

Figure 213. Receiving 0x8EAA33

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Figure 214. I

S Philips standard (16-bit extended to 32-bit packet frame with

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When 16-bit data frame extended to 32-bit channel frame is selected during the I 2 S configuration phase, only one access to SPI_DR is required. The 16 remaining bits are forced by hardware to 0x0000 to extend the data to 32-bit format.

If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the operation shown in

Figure 215 is required.

Figure 215. Example

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For transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its interrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.

For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first

16 MSB half-word is received.

In this way, more time is provided between two write or read operations, which prevents underrun or overrun conditions (depending on the direction of the data transfer).

MSB justified standard

For this standard, the WS signal is generated at the same time as the first data bit, which is the MSBit.

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Serial peripheral interface (SPI) RM0368

Figure 216. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0

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Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge

(for the receiver).

Figure 217. MSB justified 24-bit frame length with CPOL = 0

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Figure 218. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

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LSB justified standard

This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats).

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RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

Figure 219. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0

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Figure 220. LSB justified 24-bit frame length with CPOL = 0

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• In transmission mode:

If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register are required from software or by DMA. The operations are shown below.

Figure 221. Operations required to transmit 0x3478AE

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• In reception mode:

If data 0x3478AE are received, two successive read operations from SPI_DR are required on each RXNE event.

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Figure 222. Operations required to receive 0x3478AE

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Figure 223. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

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When 16-bit data frame extended to 32-bit channel frame is selected during the I

S configuration phase, Only one access to SPI_DR is required. The 16 remaining bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds to the half-word MSB.

If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit), the operation shown in

Figure 224 is required.

Figure 224. Example of LSB justified 16-bit extended to 32-bit packet frame

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In transmission mode, when TXE is asserted, the application has to write the data to be transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).

TXE is asserted again as soon as the effective data (0x76A3) is sent on SD.

In reception mode, RXNE is asserted as soon as the significant half-word is received (and not the 0x0000 field).

In this way, more time is provided between two write or read operations to prevent underrun or overrun conditions.

592/847

RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

PCM standard

For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in

SPI_I2SCFGR.

Figure 225. PCM standard waveforms (16-bit)

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For long frame synchronization, the WS signal assertion time is fixed 13 bits in master mode.

For short frame synchronization, the WS synchronization signal is only one cycle long.

Figure 226. PCM standard waveforms (16-bit extended to 32-bit packet frame)

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For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data (and so two synchronization signals) needs to be specified (DATLEN and CHLEN bits in the SPI_I2SCFGR register) even in slave mode.

The I 2 S bitrate determines the dataflow on the I 2 S data line and the I 2 S clock signal frequency.

I 2 S bitrate = number of bits per channel × number of channels × sampling audio frequency

For a 16-bit audio, left and right channel, the I 2 S bitrate is calculated as follows:

I 2 S bitrate = 16 × 2 × F

It will be: I 2 S bitrate = 32 x 2 x F

if the packet length is 32-bit wide.

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Serial peripheral interface (SPI)

Figure 227. Audio sampling frequency definition

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When the master mode is configured, a specific action needs to be taken to properly program the linear divider in order to communicate with the desired audio frequency.

Figure 228. I 2 S clock generator architecture

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Figure 227

presents the communication clock architecture. To achieve high-quality audio performance, the I2SxCLK clock source can be either the PLLI2S output (through R division factor) or an external clock (mapped to I2S_CKIN pin).

The audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the desired frequency, the linear divider needs to be programmed according to the formulas below:

When the master clock is generated (MCKOE in the SPI_I2SPR register is set):

= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide

= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide

When the master clock is disabled (MCKOE bit cleared):

= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide

= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide

Table 91 provides example precision values for different clock configurations.

Other configurations are possible that allow optimum clock precision.

594/847

RM0368 Rev 5

RM0368 Serial peripheral interface (SPI)

Master clock

Table 91. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) (1)

Target f

(Hz)

Data format

PLLI2SN PLLI2SR I2SDIV I2SODD Real f

(Hz) Error

Disabled

Enabled

8000

16000

32000

48000

96000

22050

44100

192000

8000

16000

32000

48000

96000

22050

44100

32-bit

16-bit

32-bit

16-bit

32-bit

16-bit

32-bit

16-bit

32-bit

16-bit

32-bit

16-bit

32-bit

16-bit

32-bit don't care don't care don't care don't care don't care don't care don't care

192

256

192

384

424

290

302

429

424

258

256

213

258

344

429

271

187

1. This table gives only example values for different clock configurations. Other configurations allowing optimum clock precision are possible.

8000

16000

32000

48000

96000

96014.49219

22049.87695

22050.23438

44100.46875

44099.50781

192028.9844

191964.2813

8000

16000.60059

32001.20117

47991.07031

95982.14063

22049.75391

44108.07422

0.0000%

0.0151%

0.0006%

0.0011%

0.0151%

0.0186%

0.0000%

0.0038%

0.0186%

0.0011%

0.0183%

20.4.5 I

S master mode

The I 2 S can be configured as follows:

• In master mode for transmission or reception (half-duplex mode using I2Sx)

• In master mode transmission and reception (full duplex mode using I2Sx and

I2Sx_ext).

This means that the serial clock is generated on the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not, thanks to the MCKOE bit in the

SPI_I2SPR register.

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Procedure

Select the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud rate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR register also has to be defined.

2. Select the CKPOL bit to define the steady level for the communication clock. Set the

MCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to the external DAC/ADC audio component (the I2SDIV and ODD values should be computed depending on the state of the MCK output, for more details refer to

Section 20.4.4: Clock generator ).

3. Set the I2SMOD bit in SPI_I2SCFGR to activate the I 2 S functionalities and choose the

I 2 S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the

DATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit.

Select also the I 2 S master mode and direction (Transmitter or Receiver) through the

I2SCFG[1:0] bits in the SPI_I2SCFGR register.

4. If needed, select all the potential interruption sources and the DMA capabilities by writing the SPI_CR2 register.

5. The I2SE bit in SPI_I2SCFGR register must be set.

WS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in

SPI_I2SPR is set.

Transmission sequence

The transmission sequence begins when a half-word is written into the Tx buffer.

Assumedly, the first data written into the Tx buffer correspond to the channel Left data.

When data are transferred from the Tx buffer to the shift register, TXE is set and data corresponding to the channel Right have to be written into the Tx buffer. The CHSIDE flag indicates which channel is to be transmitted. It has a meaning when the TXE flag is set because the CHSIDE flag is updated when TXE goes high.

A full frame has to be considered as a Left channel data transmission followed by a Right channel data transmission. It is not possible to have a partial frame where only the left channel is sent.

The data half-word is parallel loaded into the 16-bit shift register during the first bit transmission, and then shifted out, serially, to the MOSI/SD pin, MSB first. The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.

For more details about the write operations depending on the I 2 S standard mode selected, refer to

Section 20.4.3: Supported audio protocols ).

To ensure a continuous audio data transmission, it is mandatory to write the SPI_DR with the next data to transmit before the end of the current transmission.

To switch off the I 2 S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.

Reception sequence

The operating mode is the same as for the transmission mode except for the point 3 (refer to the procedure described in

Section 20.4.5: I2S master mode ), where the configuration

should set the master reception mode through the I2SCFG[1:0] bits.

Whatever the data or channel length, the audio data are received by 16-bit packets. This means that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated

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Note: if the RXNEIE bit is set in SPI_CR2 register. Depending on the data and channel length configuration, the audio value received for a right or left channel may result from one or two receptions into the Rx buffer.

Clearing the RXNE bit is performed by reading the SPI_DR register.

CHSIDE is updated after each reception. It is sensitive to the WS signal generated by the

2 S cell.

For more details about the read operations depending on the I 2 S standard mode selected, refer to

Section 20.4.3: Supported audio protocols .

If data are received while the previously received data have not been read yet, an overrun is generated and the OVR flag is set. If the ERRIE bit is set in the SPI_CR2 register, an interrupt is generated to indicate the error.

To switch off the I 2 S, specific actions are required to ensure that the I 2 S completes the transfer cycle properly without initiating a new data transfer. The sequence depends on the configuration of the data and channel lengths, and on the audio protocol mode selected. In the case of:

• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) using the LSB justified mode (I2SSTD = 10) a) Wait for the second to last RXNE = 1 (n – 1) b) Then wait 17 I

S clock cycles (using a software loop) c) Disable the I 2 S (I2SE = 0)

• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in

MSB justified, I

S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11, respectively) a) Wait for the last RXNE b) Then wait 1 I

S clock cycle (using a software loop) c) Disable the I 2 S (I2SE = 0)

• For all other combinations of DATLEN and CHLEN, whatever the audio mode selected through the I2SSTD bits, carry out the following sequence to switch off the I

S: a) Wait for the second to last RXNE = 1 (n – 1) b) Then wait one I

S clock cycle (using a software loop) c) Disable the I 2 S (I2SE = 0)

The BSY flag is kept low during transfers.

20.4.6 I

S slave mode

The I 2 S can be configured as follows:

• In slave mode for transmission or reception (half-duplex mode using I2Sx)

• In slave mode transmission and reception (full duplex mode using I2Sx and I2Sx_ext).

The operating mode is following mainly the same rules as described for the I 2 S master configuration. In slave mode, there is no clock to be generated by the I 2 S interface. The clock and WS signals are input from the external master connected to the I 2 S interface.

There is then no need, for the user, to configure the clock.

The configuration steps to follow are listed below:

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RM0368

Set the I2SMOD bit in the SPI_I2SCFGR register to reach the I 2 S functionalities and choose the I 2 S standard through the I2SSTD[1:0] bits, the data length through the

DATLEN[1:0] bits and the number of bits per channel for the frame configuring the

CHLEN bit. Select also the mode (transmission or reception) for the slave through the

I2SCFG[1:0] bits in SPI_I2SCFGR register.

2. If needed, select all the potential interrupt sources and the DMA capabilities by writing the SPI_CR2 register.

3. The I2SE bit in SPI_I2SCFGR register must be set.

Transmission sequence

The transmission sequence begins when the external master device sends the clock and when the NSS_WS signal requests the transfer of data. The slave has to be enabled before the external master starts the communication. The I 2 S data register has to be loaded before the master initiates the communication.

For the I 2 S, MSB justified and LSB justified modes, the first data item to be written into the data register corresponds to the data for the left channel. When the communication starts, the data are transferred from the Tx buffer to the shift register. The TXE flag is then set in order to request the right channel data to be written into the I 2 S data register.

The CHSIDE flag indicates which channel is to be transmitted. Compared to the master transmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the external master. This means that the slave needs to be ready to transmit the first data before the clock is generated by the master. WS assertion corresponds to left channel transmitted first.

The I2SE has to be written at least two PCLK cycles before the first clock of the master comes on the CK line.

The data half-word is parallel-loaded into the 16-bit shift register (from the internal bus) during the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first.

The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.

Note that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer.

For more details about the write operations depending on the I 2 S standard mode selected, refer to

Section 20.4.3: Supported audio protocols .

To secure a continuous audio data transmission, it is mandatory to write the SPI_DR register with the next data to transmit before the end of the current transmission. An underrun flag is set and an interrupt may be generated if the data are not written into the

SPI_DR register before the first clock edge of the next data communication. This indicates to the software that the transferred data are wrong. If the ERRIE bit is set into the SPI_CR2 register, an interrupt is generated when the UDR flag in the SPI_SR register goes high. In this case, it is mandatory to switch off the I 2 S and to restart a data transfer starting from the left channel.

To switch off the I

BSY = 0.

2 S, by clearing the I2SE bit, it is mandatory to wait for TXE = 1 and

Reception sequence

The operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in

Section 20.4.6: I2S slave mode

), where the configuration should set the master reception mode using the I2SCFG[1:0] bits in the SPI_I2SCFGR register.

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Serial peripheral interface (SPI)

Whatever the data length or the channel length, the audio data are received by 16-bit packets. This means that each time the RX buffer is full, the RXNE flag in the SPI_SR register is set and an interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register.

Depending on the data length and channel length configuration, the audio value received for a right or left channel may result from one or two receptions into the RX buffer.

The CHSIDE flag is updated each time data are received to be read from SPI_DR. It is sensitive to the external WS line managed by the external master component.

Clearing the RXNE bit is performed by reading the SPI_DR register.

For more details about the read operations depending the I 2 S standard mode selected, refer to

Section 20.4.3: Supported audio protocols .

If data are received while the precedent received data have not yet been read, an overrun is generated and the OVR flag is set. If the bit ERRIE is set in the SPI_CR2 register, an interrupt is generated to indicate the error.

To switch off the I 2 the last RXNE = 1.

S in reception mode, I2SE has to be cleared immediately after receiving

The external master components should have the capability of sending/receiving data in 16bit or 32-bit packets via an audio channel.

Note:

Three status flags are provided for the application to fully monitor the state of the I

S bus.

Busy flag (BSY)

The BSY flag is set and cleared by hardware (writing to this flag has no effect). It indicates the state of the communication layer of the I

When BSY is set, it indicates that the I

S is busy communicating. There is one exception in master receive mode (I2SCFG = 11) where the BSY flag is kept low during reception.

The BSY flag is useful to detect the end of a transfer if the software needs to disable the I

This avoids corrupting the last transfer. For this, the procedure described below must be strictly respected.

The BSY flag is set when a transfer starts, except when the I

S is in master receiver mode.

The BSY flag is cleared:

• when a transfer completes (except in master transmit mode, in which the communication is supposed to be continuous)

• when the I

S is disabled

When communication is continuous:

• In master transmit mode, the BSY flag is kept high during all the transfers

• In slave mode, the BSY flag goes low for one I

S clock cycle between each transfer

Do not use the BSY flag to handle each data transmission or reception. It is better to use the

TXE and RXNE flags instead.

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Tx buffer empty flag (TXE)

When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to be transmitted. It is also reset when the I 2 S is disabled (I2SE bit is reset).

RX buffer not empty (RXNE)

When set, this flag indicates that there are valid received data in the RX Buffer. It is reset when SPI_DR register is read.

Channel Side flag (CHSIDE)

In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel side to which the data to transfer on SD has to belong. In case of an underrun error event in slave transmission mode, this flag is not reliable and I 2 S needs to be switched off and switched on before resuming the communication.

In reception mode, this flag is refreshed when data are received into SPI_DR. It indicates from which channel side data have been received. Note that in case of error (like OVR) this flag becomes meaningless and the I 2 S should be reset by disabling and then enabling it

(with configuration if it needs changing).

This flag has no meaning in the PCM standard (for both Short and Long frame modes).

When the OVR or UDR flag in the SPI_SR is set and the ERRIE bit in SPI_CR2 is also set, an interrupt is generated. This interrupt can be cleared by reading the SPI_SR status register (once the interrupt source has been cleared).

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There are three error flags for the I

S cell.

Underrun flag (UDR)

In slave transmission mode this flag is set when the first clock for data transmission appears while the software has not yet loaded any value into SPI_DR. It is available when the

I2SMOD bit in SPI_I2SCFGR is set. An interrupt may be generated if the ERRIE bit in

SPI_CR2 is set.

The UDR bit is cleared by a read operation on the SPI_SR register.

Overrun flag (OVR)

This flag is set when data are received and the previous data have not yet been read from

SPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE bit is set in SPI_CR2.

In this case, the receive buffer contents are not updated with the newly received data from the transmitter device. A read operation to the SPI_DR register returns the previous correctly received data. All other subsequently transmitted half-words are lost.

Clearing the OVR bit is done by a read operation on the SPI_DR register followed by a read access to the SPI_SR register.

Frame error flag (FRE)

This flag can be set by hardware only if the I2S is configured in Slave mode. It is set if the external master is changing the WS line at a moment when the slave is not expected this

RM0368 Rev 5

RM0368 Serial peripheral interface (SPI) change. If the synchronization is lost, to recover from this state and resynchronize the external master device with the I2S slave device, follow the steps below:

Disable the I2S

2. Re-enable it when the correct level is detected on the WS line (WS line is high in I2S mode, or low for MSB- or LSB-justified or PCM modes).

Desynchronization between the master and slave device may be due to noisy environment on the SCK communication clock or on the WS frame synchronization line. An error interrupt can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by software when the status register is read.

20.4.9 I

S interrupts

Table 92 provides the list of I

2 S interrupts.

Interrupt event

Transmit buffer empty flag

Receive buffer not empty flag

Overrun error

Underrun error

Frame error flag

Table 92. I 2 S interrupt requests

Event flag

TXE

RXNE

OVR

UDR

FRE

Enable Control bit

TXEIE

RXNEIE

ERRIE

DMA is working in exactly the same way as for the SPI mode. There is no difference on the

2 S. Only the CRC feature is not available in I 2 S mode since there is no data transfer protection system.

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20.5 SPI and I

2 S registers

The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).

20.5.1 SPI control register 1 (SPI_CR1)(not used in I

S mode)

BIDI

MODE rw

BIDI

OE rw

Address offset: 0x00

Reset value: 0x0000

CRC

EN rw

CRC

NEXT rw

DFF rw

ONLY rw

SSM rw

SSI rw

LSB

FIRST rw

SPE rw

5 rw

BR [2:0] rw

3 rw

2 1 0

MSTR CPOL CPHA rw rw rw

Bit 15 BIDIMODE: Bidirectional data mode enable

0: 2-line unidirectional data mode selected

1: 1-line bidirectional data mode selected

Note: This bit is not used in I

S mode

Bit 14 BIDIOE: Output enable in bidirectional mode

This bit combined with the BIDImode bit selects the direction of transfer in bidirectional mode

0: Output disabled (receive-only mode)

1: Output enabled (transmit-only mode)

Note: This bit is not used in I

S mode.

In master mode, the MOSI pin is used while the MISO pin is used in slave mode.

Bit 13 CRCEN: Hardware CRC calculation enable

0: CRC calculation disabled

1: CRC calculation enabled

Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.

It is not used in I

S mode.

Bit 12 CRCNEXT: CRC transfer next

0: Data phase (no CRC phase)

1: Next transfer is CRC (CRC phase)

Note: When the SPI is configured in full duplex or transmitter only modes, CRCNEXT must be written as soon as the last data is written to the SPI_DR register.

When the SPI is configured in receiver only mode, CRCNEXT must be set after the second last data reception.

This bit should be kept cleared when the transfers are managed by DMA.

It is not used in I

S mode.

Bit 11 DFF: Data frame format

0: 8-bit data frame format is selected for transmission/reception

1: 16-bit data frame format is selected for transmission/reception

Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.

It is not used in I

S mode.

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Bit 10 RXONLY: Receive only

This bit combined with the BIDImode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted.

0: Full duplex (Transmit and receive)

1: Output disabled (Receive-only mode)

Note: This bit is not used in I 2 S mode

Bit 9 SSM: Software slave management

When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.

0: Software slave management disabled

1: Software slave management enabled

Note: This bit is not used in I

S mode and SPI TI mode

Bit 8 SSI: Internal slave select

This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the

NSS pin and the IO value of the NSS pin is ignored.

Note: This bit is not used in I

S mode and SPI TI mode

Bit 7 LSBFIRST: Frame format

0: MSB transmitted first

1: LSB transmitted first

Note: This bit should not be changed when communication is ongoing.

It is not used in I

S mode and SPI TI mode

Bit 6 SPE: SPI enable

0: Peripheral disabled

1: Peripheral enabled

Note: This bit is not used in I

S mode.

When disabling the SPI, follow the procedure described in Section 20.3.8

Bits 5:3 BR[2:0]: Baud rate control

000: f

PCLK

001: f

PCLK

010: f

PCLK

011: f

PCLK

100: f

PCLK

101: f

110: f

111: f

PCLK

/16

/32

/64

/128

/256

Note: These bits should not be changed when communication is ongoing.

They are not used in I

S mode.

Bit 2 MSTR: Master selection

0: Slave configuration

1: Master configuration

Note: This bit should not be changed when communication is ongoing.

It is not used in I

S mode.

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Bit1 CPOL: Clock polarity

0: CK to 0 when idle

1: CK to 1 when idle

Note: This bit should not be changed when communication is ongoing.

It is not used in I

S mode and SPI TI mode.

Bit 0 CPHA: Clock phase

0: The first clock transition is the first data capture edge

1: The second clock transition is the first data capture edge

Note: This bit should not be changed when communication is ongoing.

It is not used in I

S mode and SPI TI mode.

20.5.2 SPI control register 2 (SPI_CR2)

15 14

Address offset: 0x04

Reset value: 0x0000

13 12 11 10 9 8 7 6 5 4

TXEIE RXNEIE ERRIE FRF

Reserved rw rw rw rw

Res.

2 1 0

SSOE TXDMAEN RXDMAEN rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TXEIE: Tx buffer empty interrupt enable

0: TXE interrupt masked

1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.

Bit 6 RXNEIE: RX buffer not empty interrupt enable

0: RXNE interrupt masked

1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set.

Bit 5 ERRIE: Error interrupt enable

This bit controls the generation of an interrupt when an error condition occurs )(CRCERR,

OVR, MODF in SPI mode, FRE in TI mode and UDR, OVR, and FRE in I

S mode).

0: Error interrupt is masked

1: Error interrupt is enabled

Bit 4 FRF : Frame format

0: SPI Motorola mode

1 SPI TI mode

Note: This bit is not used in I

S mode.

Bit 3 Reserved. Forced to 0 by hardware.

Bit 2 SSOE: SS output enable

0: SS output is disabled in master mode and the cell can work in multimaster configuration

1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.

Note: This bit is not used in I

S mode and SPI TI mode.

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Bit 1 TXDMAEN: Tx buffer DMA enable

When this bit is set, the DMA request is made whenever the TXE flag is set.

0: Tx buffer DMA disabled

1: Tx buffer DMA enabled

Bit 0 RXDMAEN: Rx buffer DMA enable

When this bit is set, the DMA request is made whenever the RXNE flag is set.

0: Rx buffer DMA disabled

1: Rx buffer DMA enabled

20.5.3 SPI status register (SPI_SR)

15 14

Address offset: 0x08

Reset value: 0x0002

13 12 11 10

Reserved

9 8

FRE r

BSY r

6 5

OVR MODF r r

CRC

ERR rc_w0

3 2 1

UDR CHSIDE TXE r r r

RXNE r

Bits 15:9 Reserved. Forced to 0 by hardware.

Bit 8 FRE: Frame format error

0: No frame format error

1: A frame format error occurred

This flag is set by hardware and cleared by software when the SPIx_SR register is read.

Note: This flag is used when the SPI operates in TI slave mode or I2S slave mode (refer to

Section 20.3.10

Bit 7 BSY: Busy flag

0: SPI(or I2S) not busy

1: SPI(or I2S)is busy in communication or Tx buffer is not empty

This flag is set and cleared by hardware.

Note: BSY flag must be used with caution: refer to

Section 20.3.7

and Section 20.3.8

Bit 6 OVR: Overrun flag

0: No overrun occurred

1: Overrun occurred

This flag is set by hardware and reset by a software sequence.Refer to

Section 20.4.8:

Error flags

for the software sequence.

Bit 5 MODF: Mode fault

0: No mode fault occurred

1: Mode fault occurred

This flag is set by hardware and reset by a software sequence. Refer to Section 20.4.8:

Error flags

for the software sequence.

Note: This bit is not used in I

S mode

Bit 4 CRCERR: CRC error flag

0: CRC value received matches the SPI_RXCRCR value

1: CRC value received does not match the SPI_RXCRCR value

This flag is set by hardware and cleared by software writing 0.

Note: This bit is not used in I

S mode.

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Bit 3 UDR: Underrun flag

0: No underrun occurred

1: Underrun occurred

This flag is set by hardware and reset by a software sequence. Refer to Section 20.4.8:

Error flags

for the software sequence.

Note: This bit is not used in SPI mode.

Bit 2 CHSIDE : Channel side

0: Channel Left has to be transmitted or has been received

1: Channel Right has to be transmitted or has been received

Note: This bit is not used for SPI mode and is meaningless in PCM mode.

Bit 1 TXE: Transmit buffer empty

0: Tx buffer not empty

1: Tx buffer empty

Bit 0 RXNE: Receive buffer not empty

0: Rx buffer empty

1: Rx buffer not empty

20.5.4 SPI data register (SPI_DR)

Address offset: 0x0C

Reset value: 0x0000

15 rw

14 13 12 11 10 9 8

DR[15:0]

7 rw rw

6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DR[15:0]: Data register

Data received or to be transmitted.

The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer). A write to the data register will write into the Tx buffer and a read from the data register will return the value held in the Rx buffer.

Note: These notes apply to SPI mode:

Depending on the data frame format selection bit (DFF in SPI_CR1 register), the data sent or received is either 8-bit or 16-bit. This selection has to be made before enabling the SPI to ensure correct operation.

For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register

(SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the MSB of the register (SPI_DR[15:8]) is forced to 0.

For a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is used for transmission/reception.

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20.5.5 SPI CRC polynomial register (SPI_CRCPR)(not used in I

S mode)

15 14

Address offset: 0x10

Reset value: 0x0007

13 12 11 10 9 6 5 4 3 rw rw rw rw rw rw rw

8 7

CRCPOLY[15:0] rw rw rw rw rw rw

2 rw

1 0 rw rw

Bits 15:0 CRCPOLY[15:0]: CRC polynomial register

This register contains the polynomial for the CRC calculation.

The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required.

Note: These bits are not used for the I

S mode.

20.5.6 SPI RX CRC register (SPI_RXCRCR)(not used in I

S mode)

15 14

Address offset: 0x14

Reset value: 0x0000

13 12 11 10 9 6 5 4 3 r r r r r r r

8 7

RXCRC[15:0] r r r r r r

2 r

1 0 r r

Bits 15:0 RXCRC[15:0]: Rx CRC register

When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register.

Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.

The entire 16-bits of this register are considered when a 16-bit data frame format is selected

(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard.

Note: A read to this register when the BSY Flag is set could return an incorrect value.

These bits are not used for I

S mode

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20.5.7 SPI TX CRC register (SPI_TXCRCR)(not used in I

S mode)

15 14

Address offset: 0x18

Reset value: 0x0000

13 12 11 10 9 6 5 4 3 r r r r r r r

8 7

TXCRC[15:0] r r r r r r

2 r

1 0 r r

Bits 15:0 TXCRC[15:0]: Tx CRC register

When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the

SPI_CRCPR register.

Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.

The entire 16-bits of this register are considered when a 16-bit data frame format is selected

(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard.

Note: A read to this register when the BSY flag is set could return an incorrect value.

These bits are not used for I

S mode.

20.5.8 SPI_I

S configuration register (SPI_I2SCFGR)

15 14

Address offset: 0x1C

Reset value: 0x0000

13 12 11 10 9 8 6 5

Reserved

I2SMOD I2SE rw rw rw

I2SCFG rw

PCMSY

NC rw

Res.

I2SSTD

4 rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 I2SMOD : I2S mode selection

0: SPI mode is selected

1: I2S mode is selected

Note: This bit should be configured when the SPI or I

S is disabled

Bit 10 I2SE : I2S Enable

0: I

1: I

S peripheral is disabled

S peripheral is enabled

Note: This bit is not used in SPI mode.

Bits 9:8 I2SCFG : I2S configuration mode

00: Slave - transmit

01: Slave - receive

10: Master - transmit

11: Master - receive

Note: This bit should be configured when the I

S is disabled.

It is not used in SPI mode.

CKPOL rw

DATLEN

1 rw rw

CHLEN rw

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Bit 7 PCMSYNC : PCM frame synchronization

0: Short frame synchronization

1: Long frame synchronization

Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)

It is not used in SPI mode.

Bit 6 Reserved: forced at 0 by hardware

Bits 5:4 I2SSTD : I2S standard selection

00: I

S Philips standard.

01: MSB justified standard (left justified)

10: LSB justified standard (right justified)

11: PCM standard

For more details on I in SPI mode.

S standards, refer to Section 20.4.3: Supported audio protocols .

Not used

Note: For correct operation, these bits should be configured when the I

S is disabled.

Bit 3 CKPOL : Steady state clock polarity

0: I

1: I

S clock steady state is low level

S clock steady state is high level

Note: For correct operation, this bit should be configured when the I

S is disabled.

This bit is not used in SPI mode

Bits 2:1 DATLEN : Data length to be transferred

00: 16-bit data length

01: 24-bit data length

10: 32-bit data length

11: Not allowed

Note: For correct operation, these bits should be configured when the I 2 S is disabled.

This bit is not used in SPI mode.

Bit 0 CHLEN : Channel length (number of bits per audio channel)

0: 16-bit wide

1: 32-bit wide

The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to

32-bit by hardware whatever the value filled in. Not used in SPI mode.

Note: For correct operation, this bit should be configured when the I

S is disabled.

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20.5.9 SPI_I

S prescaler register (SPI_I2SPR)

15 14

Address offset: 0x20

Reset value: 0000 0010 (0x0002)

13 12

Reserved

11 10 9 8

MCKOE ODD rw rw

7 6 5 4

I2SDIV rw

3 2 1 0

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 MCKOE : Master clock output enable

0: Master clock output is disabled

1: Master clock output is enabled

Note: This bit should be configured when the I

2 mode.

S is disabled. It is used only when the I

S is in master

This bit is not used in SPI mode.

Bit 8 ODD : Odd factor for the prescaler

0: real divider value is = I2SDIV *2

1: real divider value is = (I2SDIV * 2)+1

Refer to

Section 20.4.4: Clock generator .

Not used in SPI mode.

Note: This bit should be configured when the I

2 mode.

S is disabled. It is used only when the I

S is in master

Bits 7:0 I2SDIV : I2S Linear prescaler

I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.

Refer to Section 20.4.4: Clock generator

. Not used in SPI mode.

Note: These bits should be configured when the I

S is disabled. It is used only when the I master mode.

S is in

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Offset

The table provides shows the SPI register map and reset values.

Table 93. SPI register map and reset values

Register

SPI_CR1

0x00

0x0C

0x10

0x14

0x18

0x08

Reset value

SPI_SR

Reset value

SPI_DR

Reset value

SPI_CRCPR

Reset value

SPI_RXCRCR

Reset value

SPI_TXCRCR

Reset value

0x1C

SPI_I2SCFGR

0x20

Reset value

SPI_I2SPR

Reset value

Reserved

BR [2:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0

DR[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CRCPOLY[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

RxCRC[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TxCRC[15:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0

I2SDIV

0 0 0 0 0 0 0 0 1 0

Refer to Section 3.3: Memory map for the register boundary addresses.

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21 Secure digital input/output interface (SDIO)

RM0368

21.1 SDIO main features

Note:

The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 peripheral bus and MultiMediaCards (MMCs), SD memory cards, SDIO cards and CE-ATA devices.

The MultiMediaCard system specifications are available through the MultiMediaCard

Association website at http://www.jedec.org/, published by the MMCA technical committee.

SD memory card and SD I/O card system specifications are available through the SD card

Association website at http://www.sdcard.org.

CE-ATA system specifications are available through the CE-ATA workgroup website.

The SDIO features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.2

. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit

• Full compatibility with previous versions of MultiMediaCards (forward compatibility)

• Full compliance with SD Memory Card Specifications Version 2.0

• Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit

• Full support of the CE-ATA features (full compliance with CE-ATA digital protocol

Rev1.1

)

• Data transfer up to 50 MHz for the 8 bit mode

• Data and command output enable signals to control external bidirectional drivers.

The SDIO does not have an SPI-compatible communication mode.

The SD memory card protocol is a superset of the MultiMediaCard protocol as defined in the

MultiMediaCard system specification V2.11. Several commands required for SD memory devices are not supported by either SD I/O-only cards or the I/O portion of combo cards.

Some of these commands have no use in SD I/O devices, such as erase commands, and thus are not supported in the SDIO. In addition, several commands are different between

SD memory cards and SD I/O cards and thus are not supported in the SDIO. For details refer to SD I/O card Specification Version 1.0. CE-ATA is supported over the MMC electrical interface using a protocol that utilizes the existing MMC access primitives. The interface electrical and signaling definition is as defined in the MMC reference.

The MultiMediaCard/SD bus connects cards to the controller.

The current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

21.2 SDIO bus topology

Communication over the bus is based on command and data transfers.

The basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response transaction. These types of bus transaction transfer their information directly within the command or response structure. In addition, some operations have a data token.

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Data transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers to/from MMC are done data blocks or streams. Data transfers to/from the CE-ATA Devices are done in data blocks.

Figure 229. SDIO “no response” and “no data” operations

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Figure 231. SDIO (multiple) block write operation

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The SDIO will not send any data as long as the Busy signal is asserted (SDIO_D0 pulled low).

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Figure 232. SDIO sequential read operation

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Figure 233. SDIO sequential write operation

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21.3 SDIO functional description

The SDIO consists of two parts:

• The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer.

• The APB2 interface accesses the SDIO adapter registers, and generates interrupt and

DMA request signals.

Figure 234. SDIO block diagram

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RM0368 Secure digital input/output interface (SDIO)

By default SDIO_D0 is used for data transfer. After initialization, the host can change the databus width.

If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 can be used.

If an SD or SD I/O card is connected to the bus, data transfer can be configured by the host to use SDIO_D0 or SDIO_D[3:0]. All data lines are operating in push-pull mode.

SDIO_CMD has two operational modes:

• Open-drain for initialization (only for MMCV3.31 or previous)

• Push-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for initialization)

SDIO_CK is the clock to the card: one bit is transferred on both command and data lines with each clock cycle.

The SDIO uses two clock signals:

• SDIO adapter clock SDIOCLK up to 50 MHz (48 MHz when in use with USB)

• APB2 bus clock (PCLK2)

PCLK2 and SDIO_CK clock frequencies must respect the following condition:

Frequenc PCLK2 ) ≥ 3 ⁄ 8 × )

The signals shown in Table 94

are used on the MultiMediaCard/SD/SD I/O card bus.

Pin

SDIO_CK

SDIO_CMD

SDIO_D[7:0]

Direction

Table 94. SDIO I/O definitions

Description

Output

Bidirectional

MultiMediaCard/SD/SDIO card clock. This pin is the clock from host to card.

MultiMediaCard/SD/SDIO card command. This pin is the bidirectional command/response signal.

MultiMediaCard/SD/SDIO card data. These pins are the bidirectional databus.

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Figure 235 shows a simplified block diagram of an SDIO adapter.

Figure 235. SDIO adapter

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The SDIO adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. It consists of five subunits:

• Adapter register block

• Control unit

• Command path

• Data path

• Data FIFO

The adapter registers and FIFO use the APB2 bus clock domain ( PCLK2 ). The control unit, command path and data path use the SDIO adapter clock domain (SDIOCLK).

Adapter register block

The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the multimedia card. The clear signals are generated when 1 is written into the corresponding bit location in the SDIO Clear register.

Control unit

The control unit contains the power management functions and the clock divider for the memory card clock.

There are three power phases:

• power-off

• power-up

• power-on

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Figure 236. Control unit

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The control unit is illustrated in

Figure 236

. It consists of a power management subunit and a clock management subunit.

The power management subunit disables the card bus output signals during the power-off and power-up phases.

The clock management subunit generates and controls the SDIO_CK signal. The SDIO_CK output can use either the clock divide or the clock bypass mode. The clock output is inactive:

• after reset

• during the power-off or power-up phases

• if the power saving mode is enabled and the card bus is in the Idle state (eight clock periods after both the command and data path subunits enter the Idle phase)

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Command path

The command path unit sends commands to and receives responses from the cards.

Figure 237. SDIO adapter command path

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• Command path state machine (CPSM)

– When the command register is written to and the enable bit is set, command transfer starts. When the command has been sent, the command path state machine (CPSM) sets the status flags and enters the Idle state if a response is not required. If a response is required, it waits for the response (see

Figure 238 on page 619

). When the response is received, the received CRC code and the internally generated code are compared, and the appropriate status flags are set.

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Figure 238. Command path state machine (CPSM)

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When the Wait state is entered, the command timer starts running. If the timeout is reached before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is entered.

The command timeout has a fixed value of 64 SDIO_CK clock periods.

If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits for an interrupt request from one of the cards. If a pending bit is set in the command register, the CPSM enters the Pend state, and waits for a CmdPend signal from the data path subunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the data counter to trigger the stop command transmission.

The CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the N

timing constraints. N

is the minimum delay between two host commands, and N the minimum delay between the host command and the card response.

and

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Note:

RM0368

Figure 239. SDIO command transfer

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• Command format

– Command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available for MMC V3.31 or previous). Commands are transferred serially on the CMD line. All commands have a fixed length of 48 bits. The general format for a command token for MultiMediaCards, SD-Memory cards and SDIO-Cards is shown in

Table 95

. CE-ATA commands are an extension of MMC commands V4.2, and so have the same format.

The command path operates in a half-duplex mode, so that commands and responses can either be sent or received. If the CPSM is not in the Send state, the

SDIO_CMD output is in the Hi-Z state, as shown in

Figure 239 on page 620

. Data

on SDIO_CMD are synchronous with the rising edge of SDIO_CK. Table

shows the command format.

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Bit position

[45:40]

[39:8]

[7:1]

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Width Value

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Description

Start bit

Transmission bit

Command index

Argument

CRC7

End bit

– Response: a response is a token that is sent from an addressed card (or synchronously from all connected cards for MMC V3.31 or previous), to the host as an answer to a previously received command. Responses are transferred serially on the CMD line.

The SDIO supports two response types. Both use CRC error checking:

• 48 bit short response

• 136 bit long response

If the response does not contain a CRC (CMD1 response), the device driver must ignore the

CRC failed status.

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Bit position

[45:40]

[39:8]

[7:1]

32 -

Secure digital input/output interface (SDIO)

Table 96. Short response format

Width Value Description

Start bit

Transmission bit

Command index

Argument

CRC7(or 1111111)

End bit

Bit position

135

134

[133:128]

[127:1]

127

Table 97. Long response format

Width Value

111111

Description

Start bit

Transmission bit

Reserved

CID or CSD (including internal CRC7)

End bit

The command register contains the command index (six bits sent to a card) and the command type. These determine whether the command requires a response, and whether

the response is 48 or 136 bits long (see Section 21.9.4 on page 655 ). The command path

implements the status flags shown in

Table 98 :

Flag

CMDREND

CCRCFAIL

CMDSENT

CTIMEOUT

CMDACT

Table 98. Command path status flags

Description

Set if response CRC is OK.

Set if response CRC fails.

Set when command (that does not require response) is sent

Response timeout.

Command transfer in progress.

The CRC generator calculates the CRC checksum for all bits before the CRC code. This includes the start bit, transmitter bit, command index, and command argument (or card status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long response format. Note that the start bit, transmitter bit and the six reserved bits are not used in the CRC calculation.

The CRC checksum is a 7-bit value:

CRC[6:0] = Remainder [(M(x) * x

) / G(x)]

G(x) = x 7 + x 3 + 1

M(x) = (start bit) * x

+ ... + (last bit before CRC) * x

, or

M(x) = (start bit) * x 119 + ... + (last bit before CRC) * x 0

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Data path

The data path subunit transfers data to and from cards. Figure 240

shows a block diagram of the data path.

Figure 240. Data path

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The card databus width can be programmed using the clock control register. If the 4-bit wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals

(SDIO_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per clock cycle over all eight data signals (SDIO_D[7:0]). If the wide bus mode is not enabled, only one bit per clock cycle is transferred over SDIO_D0.

Depending on the transfer direction (send or receive), the data path state machine (DPSM) moves to the Wait_S or Wait_R state when it is enabled:

• Send: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the

DPSM moves to the Send state, and the data path subunit starts sending data to a card.

• Receive: the DPSM moves to the Wait_R state and waits for a start bit. When it receives a start bit, the DPSM moves to the Receive state, and the data path subunit starts receiving data from a card.

Data path state machine (DPSM)

The DPSM operates at SDIO_CK frequency. Data on the card bus signals is synchronous to the rising edge of SDIO_CK. The DPSM has six states, as shown in

Figure 241: Data path state machine (DPSM) .

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Figure 241. Data path state machine (DPSM)

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• Wait_R: if the data counter equals zero, the DPSM moves to the Idle state when the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start bit on

SDIO_D. The DPSM moves to the Receive state if it receives a start bit before a timeout, and loads the data block counter. If it reaches a timeout before it detects a start bit, or a start bit error occurs, it moves to the Idle state and sets the timeout status flag.

• Receive: serial data received from a card is packed in bytes and written to the data

FIFO. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream:

– In block mode, when the data block counter reaches zero, the DPSM waits until it receives the CRC code. If the received code matches the internally generated

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RM0368

CRC code, the DPSM moves to the Wait_R state. If not, the CRC fail status flag is set and the DPSM moves to the Idle state.

– In stream mode, the DPSM receives data while the data counter is not zero. When the counter is zero, the remaining data in the shift register is written to the data

FIFO, and the DPSM moves to the Wait_R state.

If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the

Idle state:

• Wait_S: the DPSM moves to the Idle state if the data counter is zero. If not, it waits until the data FIFO empty flag is deasserted, and moves to the Send state.

The DPSM remains in the Wait_S state for at least two clock periods to meet the N

WR requirements, where N

WR response and the start of the data transfer from the host.

timing

is the number of clock cycles between the reception of the card

• Send: the DPSM starts sending data to a card. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream:

– In block mode, when the data block counter reaches zero, the DPSM sends an internally generated CRC code and end bit, and moves to the Busy state.

– In stream mode, the DPSM sends data to a card while the enable bit is high and the data counter is not zero. It then moves to the Idle state.

If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the

Idle state.

• Busy: the DPSM waits for the CRC status flag:

– If it does not receive a positive CRC status, it moves to the Idle state and sets the

CRC fail status flag.

– If it receives a positive CRC status, it moves to the Wait_S state if SDIO_D0 is not low (the card is not busy).

If a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and moves to the Idle state.

The data timer is enabled when the DPSM is in the Wait_R or Busy state, and generates the data timeout error:

– When transmitting data, the timeout occurs if the DPSM stays in the Busy state for longer than the programmed timeout period

– When receiving data, the timeout occurs if the end of the data is not true, and if the

DPSM stays in the Wait_R state for longer than the programmed timeout period.

• Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines . They are stored in a FIFO of 32 words , each word is 32 bits wide.

Description

Block Data

Stream Data

Table 99. Data token format

Start bit Data CRC16

yes no

End bit

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Data FIFO

The data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit.

The FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic.

Because the data FIFO operates in the APB2 clock domain (PCLK2), all signals from the subunits in the SDIO clock domain (SDIOCLK) are resynchronized.

Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive:

– The transmit FIFO refers to the transmit logic and data buffer when TXACT is asserted

– The receive FIFO refers to the receive logic and data buffer when RXACT is asserted

• Transmit FIFO:

Data can be written to the transmit FIFO through the APB2 interface when the SDIO is enabled for transmission.

The transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO contains a data output register that holds the data word pointed to by the read pointer.

When the data path subunit has loaded its shift register, it increments the read pointer and drives new data out.

If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit asserts TXACT when it transmits data.

Flag

TXFIFOF

TXFIFOE

TXFIFOHE

TXDAVL

TXUNDERR

Table 100. Transmit FIFO status flags

Description

Set to high when all 32 transmit FIFO words contain valid data.

Set to high when the transmit FIFO does not contain valid data.

Set to high when 8 or more transmit FIFO words are empty. This flag can be used as a DMA request.

Set to high when the transmit FIFO contains valid data. This flag is the inverse of the TXFIFOE flag.

Set to high when an underrun error occurs. This flag is cleared by writing to the

SDIO Clear register.

• Receive FIFO

When the data path subunit receives a word of data, it drives the data on the write databus. The write pointer is incremented after the write operation completes. On the read side, the contents of the FIFO word pointed to by the current value of the read pointer is driven onto the read databus. If the receive FIFO is disabled, all status flags are deasserted, and the read and write pointers are reset. The data path subunit

asserts RXACT when it receives data. Table 101

lists the receive FIFO status flags.

The receive FIFO is accessible via 32 sequential addresses.

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Flag

RXFIFOF

RXFIFOE

RXFIFOHF

RXDAVL

RXOVERR

Table 101. Receive FIFO status flags

Description

Set to high when all 32 receive FIFO words contain valid data

Set to high when the receive FIFO does not contain valid data.

Set to high when 8 or more receive FIFO words contain valid data. This flag can be used as a DMA request.

Set to high when the receive FIFO is not empty. This flag is the inverse of the

RXFIFOE flag.

Set to high when an overrun error occurs. This flag is cleared by writing to the SDIO

Clear register.

21.3.2 SDIO APB2 interface

The APB2 interface generates the interrupt and DMA requests, and accesses the SDIO adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt/DMA logic.

SDIO interrupts

The interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high. A mask register is provided to allow selection of the conditions that will generate an interrupt. A status flag generates the interrupt request if a corresponding mask flag is set.

SDIO/DMA interface - procedure for data transfers between the SDIO and memory

In the example shown, the transfer is from the SDIO host controller to an MMC (512 bytes using CMD24 (WRITE_BLOCK). The SDIO FIFO is filled by data stored in a memory using the DMA controller.

Do the card identification process

2. Increase the SDIO_CK frequency

3. Select the card by sending CMD7

4. Configure the DMA2 as follows: a) Enable DMA2 controller and clear any pending interrupts.

b) Program the DMA2_Stream3 or DMA2_Stream6 Channel4 source address register with the memory location’s base address and DMA2_Stream3 or

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DMA2_Stream6 Channel4 destination address register with the SDIO_FIFO register address.

c) Program DMA2_Stream3 or DMA2_Stream6 Channel4 control register (memory increment, not peripheral increment, peripheral and source width is word size).

d) Program DMA2_Stream3 or DMA2_Stream6 Channel4 to select the peripheral as flow controller (set PFCTRL bit in DMA_S3CR or DMA_S6CR configuration register).

e) Configure the incremental burst transfer to 4 beats (at least from peripheral side) in DMA2_Stream3 or DMA2_Stream6 Channel4.

f) Enable DMA2_Stream3 or DMA2_Stream6 Channel4

5. Send CMD24 (WRITE_BLOCK) as follows: a) Program the SDIO data length register (SDIO data timer register should be already programmed before the card identification process).

b) Program the SDIO argument register with the address location of the card where data is to be transferred.

c) Program the SDIO command register: CmdIndex with 24 (WRITE_BLOCK);

WaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO card host enabled to send a command). Other fields are at their reset value.

d) Wait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control register: DTEN with ‘1’ (SDIO card host enabled to send data); DTDIR with ‘0’

(from controller to card); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’

(DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care.

e) Wait for SDIO_STA[10] = DBCKEND.

6. Check that no channels are still enabled by polling the DMA Enabled Channel Status register.

21.4 Card functional description

While in card identification mode the host resets all cards, validates the operation voltage range, identifies cards and sets a relative card address (RCA) for each card on the bus. All data communications in the card identification mode use the command line (CMD) only.

The

GO_IDLE_STATE

command (CMD0) is the software reset command and it puts the

MultiMediaCard and SD memory in the Idle state. The

IO_RW_DIRECT

command (CMD52) resets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the highimpedance state and the cards are initialized with a default relative card address

(RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving current capability).

21.4.3 Operating voltage range validation

All cards can communicate with the SDIO card host using any operating voltage within the specification range. The supported minimum and maximum V operation conditions register (OCR) on the card.

values are defined in the

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Cards that store the card identification number (CID) and card specific data (CSD) in the payload memory are able to communicate this information only under data-transfer V

DD conditions. When the SDIO card host module and the card have incompatible V

ranges, the card is not able to complete the identification cycle and cannot send CSD data. For this purpose, the special commands,

SEND_OP_COND

(CMD1),

SD_APP_OP_COND

(ACMD41 for SD Memory), and

IO_SEND_OP_COND

(CMD5 for SD I/O), are designed to provide a mechanism to identify and reject cards that do not match the V

SDIO card host. The SDIO card host sends the required V

range desired by the

voltage window as the operand of these commands. Cards that cannot perform data transfer in the specified range disconnect from the bus and go to the inactive state.

By using these commands without including the voltage range as the operand, the SDIO card host can query each card and determine the common voltage range before placing outof-range cards in the inactive state. This query is used when the SDIO card host is able to select a common voltage range or when the user requires notification that cards are not usable.

The card identification process differs for MultiMediaCards and SD cards. For

MultiMediaCard cards, the identification process starts at clock rate F od

. The SDIO_CMD line output drivers are open-drain and allow parallel card operation during this process. The registration process is accomplished as follows:

The bus is activated.

2. The SDIO card host broadcasts

SEND_OP_COND

(CMD1) to receive operation conditions.

3. The response is the wired AND operation of the operation condition registers from all cards.

4. Incompatible cards are placed in the inactive state.

5. The SDIO card host broadcasts

ALL_SEND_CID

(CMD2) to all active cards.

6. The active cards simultaneously send their CID numbers serially. Cards with outgoing

CID bits that do not match the bits on the command line stop transmitting and must wait for the next identification cycle. One card successfully transmits a full CID to the SDIO card host and enters the Identification state.

7. The SDIO card host issues

SET_RELATIVE_ADDR

(CMD3) to that card. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state, it does not react to further identification cycles, and its output switches from open-drain to push-pull.

8. The SDIO card host repeats steps 5 through 7 until it receives a timeout condition.

For the SD card, the identification process starts at clock rate F od

, and the SDIO_CMD line output drives are push-pull drivers instead of open-drain. The registration process is accomplished as follows:

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The bus is activated.

2. The SDIO card host broadcasts

SD_APP_OP_COND

(ACMD41).

3. The cards respond with the contents of their operation condition registers.

4. The incompatible cards are placed in the inactive state.

5. The SDIO card host broadcasts

ALL_SEND_CID

(CMD2) to all active cards.

6. The cards send back their unique card identification numbers (CIDs) and enter the

Identification state.

7. The SDIO card host issues

SET_RELATIVE_ADDR

(CMD3) to an active card with an address. This new address is called the relative card address (RCA); it is shorter than the CID and addresses the card. The assigned card changes to the Standby state. The

SDIO card host can reissue this command to change the RCA. The RCA of the card is the last assigned value.

8. The SDIO card host repeats steps 5 through 7 with all active cards.

For the SD I/O card, the registration process is accomplished as follows:

The bus is activated.

2. The SDIO card host sends

IO_SEND_OP_COND

(CMD5).

3. The cards respond with the contents of their operation condition registers.

4. The incompatible cards are set to the inactive state.

5. The SDIO card host issues

SET_RELATIVE_ADDR

SDIO card host can reissue this command to change the RCA. The RCA of the card is the last assigned value.

During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host. A card supporting block write is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails, the card indicates the failure on the SDIO_D line and the transferred data are discarded and not written, and all further transmitted blocks (in multiple block write mode) are ignored.

If the host uses partial blocks whose accumulated length is not block aligned and, block misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment error before the beginning of the first misaligned block.

(ADDRESS_ERROR error bit is set in the status register). The write operation will also be aborted if the host tries to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit.

Programming of the CID and CSD registers does not require a previous block length setting.

The transferred data is also CRC protected. If a part of the CSD or CID register is stored in

ROM, then this unchangeable part must match the corresponding part of the receive buffer.

If this match fails, then the card reports an error and does not change any register contents.

Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card begins writing and holds the SDIO_D line low if its write buffer is full and unable to accept new data from a new

WRITE_BLOCK

command. The host may poll the status of the card with a

SEND_STATUS command (CMD13) at any time, and the card will respond with its status. The

READY_FOR_DATA status bit indicates whether the card can accept new data or whether the write process is still in progress. The host may deselect the card by issuing CMD7 (to

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SDIO_D line(s) without interrupting the write operation. When selecting the card again, it will reactivate busy indication by pulling SDIO_D to low if programming is still in progress and the write buffer is unavailable.

In Block read mode the basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and end addresses are entirely contained within one physical block (as defined by

READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block, ensuring data transfer integrity. CMD17 (

READ_SINGLE_BLOCK

) initiates a block read and after completing the transfer, the card returns to the Transfer state.

CMD18 (

READ_MULTIPLE_BLOCK

) starts a transfer of several consecutive blocks.

The host can abort reading at any time, within a multiple block operation, regardless of its type. Transaction abort is done by sending the stop transmission command.

If the card detects an error (for example, out of range, address misalignment or internal error) during a multiple block read operation (both types) it stops the data transmission and remains in the data state. The host must than abort the operation by sending the stop transmission command. The read error is reported in the response to the stop transmission command.

If the host sends a stop transmission command after the card transmits the last block of a multiple block operation with a predefined number of blocks, it is responded to as an illegal command, since the card is no longer in the data state. If the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block

(ADDRESS_ERROR error bit is set in the status register).

21.4.7 Stream access, stream write and stream read

(MultiMediaCard only)

In stream mode, data is transferred in bytes and no CRC is appended at the end of each block.

Stream write (MultiMediaCard only)

WRITE_DAT_UNTIL_STOP

(CMD20) starts the data transfer from the SDIO card host to the card, beginning at the specified address and continuing until the SDIO card host issues a stop command. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is set), the data stream can start and stop at any address within the card address space, otherwise it can only start and stop at block boundaries. Because the amount of data to be transferred is not determined in advance, a CRC cannot be used. When the end of the memory range is reached while sending data and no stop command is sent by the SD card host, any additional transferred data are discarded.

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The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register:

Maximumspeed

( ,

) ( –

NSAC

TAAC R2WFACTOR

)

• Maximumspeed = maximum write frequency

• TRANSPEED = maximum data transfer rate

• writebllen = maximum write data block length

• NSAC = data read access time 2 in CLK cycles

• TAAC = data read access time 1

• R2WFACTOR = write speed factor

If the host attempts to use a higher frequency, the card may not be able to process the data and stop programming, set the OVERRUN error bit in the status register, and while ignoring all further data transfer, wait (in the receive data state) for a stop command. The write operation is also aborted if the host tries to write over a write-protected area. In this case, however, the card sets the WP_VIOLATION bit.

Stream read (MultiMediaCard only)

READ_DAT_UNTIL_STOP

(CMD11) controls a stream-oriented data transfer.

This command instructs the card to send its data, starting at a specified address, until the

SDIO card host sends

STOP_TRANSMISSION

(CMD12). The stop command has an execution delay due to the serial command transmission and the data transfer stops after the end bit of the stop command. When the end of the memory range is reached while sending data and no stop command is sent by the SDIO card host, any subsequent data sent are considered undefined.

The maximum clock frequency for a stream read operation is given by the following equation and uses fields of the card specific data register.

Maximumspeed = ( ,

TAAC ×

) (

–

NSAC

R2WFACTOR

)

• Maximumspeed = maximum read frequency

• TRANSPEED = maximum data transfer rate

• readbllen = maximum read data block length

• writebllen = maximum write data block length

• NSAC = data read access time 2 in CLK cycles

• TAAC = data read access time 1

• R2WFACTOR = write speed factor

If the host attempts to use a higher frequency, the card is not able to sustain data transfer. If this happens, the card sets the UNDERRUN error bit in the status register, aborts the transmission and waits in the data state for a stop command.

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21.4.8 Erase: group erase and sector erase

The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in the CSD.

The host can erase a contiguous range of Erase Groups. Starting the erase process is a three-step sequence.

First the host defines the start address of the range using the

ERASE_GROUP_START

(CMD35) command, next it defines the last address of the range using the

ERASE_GROUP_END

(CMD36) command and, finally, it starts the erase process by issuing the

ERASE

(CMD38) command. The address field in the erase commands is an Erase

Group address in byte units. The card ignores all LSBs below the Erase Group size, effectively rounding the address down to the Erase Group boundary.

If an erase command is received out of sequence, the card sets the ERASE_SEQ_ERROR bit in the status register and resets the whole sequence.

If an out-of-sequence (neither of the erase commands, except SEND_STATUS) command received, the card sets the ERASE_RESET status bit in the status register, resets the erase sequence and executes the last command.

If the erase range includes write protected blocks, they are left intact and only unprotected blocks are erased. The WP_ERASE_SKIP status bit in the status register is set.

The card indicates that an erase is in progress by holding SDIO_D low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card.

21.4.9 Wide bus selection or deselection

Wide bus (4-bit bus width) operation mode is selected or deselected using

SET_BUS_WIDTH

(ACMD6). The default bus width after power-up or

GO_IDLE_STATE

(CMD0) is 1 bit.

SET_BUS_WIDTH

(ACMD6) is only valid in a transfer state, which means that the bus width can be changed only after a card is selected by

SELECT/DESELECT_CARD

(CMD7).

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Three write protection methods for the cards are supported in the SDIO card host module:

internal card write protection (card responsibility)

2. mechanical write protection switch (SDIO card host module responsibility only)

Internal card write protection

Card data can be protected against write and erase. By setting the permanent or temporary write-protect bits in the CSD, the entire card can be permanently write-protected by the manufacturer or content provider. For cards that support write protection of groups of sectors by setting the

WP_GRP_ENABLE

bit in the CSD, portions of the data can be protected, and the write protection can be changed by the application. The write protection is in units of

WP_GRP_SIZE

sectors as specified in the CSD. The

SET_WRITE_PROT

and

CLR_WRITE_PROT

commands control the protection of the addressed group. The

SEND_WRITE_PROT command is similar to a single block read command. The card sends a data block containing 32 write protection bits (representing 32 write protect groups starting

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The card ignores all LSBs below the group size.

Mechanical write protect switch

A mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card. When the sliding tab is positioned with the window open, the card is write-protected, and when the window is closed, the card contents can be changed. A matched switch on the socket side indicates to the SDIO card host module that the card is write-protected. The SDIO card host module is responsible for protecting the card. The position of the write protect switch is unknown to the internal circuitry of the card.

Password protect

The password protection feature enables the SDIO card host module to lock and unlock a card with a password. The password is stored in the 128-bit PWD register and its size is set in the 8-bit PWD_LEN register. These registers are nonvolatile so that a power cycle does not erase them. Locked cards respond to and execute certain commands. This means that the SDIO card host module is allowed to reset, initialize, select, and query for status, however it is not allowed to access data on the card. When the password is set (as indicated by a nonzero value of PWD_LEN), the card is locked automatically after power-up. As with the CSD and CID register write commands, the lock/unlock commands are available in the transfer state only. In this state, the command does not include an address argument and the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required information for the command (the password setting mode, the PWD itself, and card lock/unlock). The command data block size is defined by the SDIO card host module before it sends the card lock/unlock

command, and has the structure shown in Table 115 .

The bit settings are as follows:

• ERASE: setting it forces an erase operation. All other bits must be zero, and only the command byte is sent

• LOCK_UNLOCK: setting it locks the card. LOCK_UNLOCK can be set simultaneously with SET_PWD, however not with CLR_PWD

• CLR_PWD: setting it clears the password data

• SET_PWD: setting it saves the password data to memory

• PWD_LEN: it defines the length of the password in bytes

• PWD: the password (new or currently used, depending on the command)

The following sections list the command sequences to set/reset a password, lock/unlock the card, and force an erase.

Setting the password

Select a card (

SELECT/DESELECT_CARD

, CMD7), if none is already selected.

2. Define the block length (

SET_BLOCKLEN

, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit PWD_LEN, and the number of bytes of the new password.

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When a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command.

3. Send (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (SET_PWD = 1), the length (PWD_LEN), and the password (PWD) itself. When a password replacement is done, the length value (PWD_LEN) includes the length of both passwords, the old and the new one, and the PWD field includes the old password (currently used) followed by the new password.

4. When the password is matched, the new password and its size are saved into the PWD and PWD_LEN fields, respectively. When the old password sent does not correspond

(in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the password is not changed.

The password length field (PWD_LEN) indicates whether a password is currently set. When this field is nonzero, there is a password set and the card locks itself after power-up. It is possible to lock the card immediately in the current power session by setting the

LOCK_UNLOCK bit (while setting the password) or sending an additional command for card locking.

Resetting the password

Select a card (

SELECT/DESELECT_CARD

, CMD7), if none is already selected.

2. Define the block length (

SET_BLOCKLEN

, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit

PWD_LEN

, and the number of bytes in the currently used password.

3. Send (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (CLR_PWD = 1), the length (PWD_LEN) and the password (PWD) itself. The LOCK_UNLOCK bit is ignored.

4. When the password is matched, the PWD field is cleared and PWD_LEN is set to 0.

When the password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the password is not changed.

Locking a card

Select a card (

SELECT/DESELECT_CARD

, CMD7), if none is already selected.

2. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode (byte 0 in

Table 115 ), the 8-bit PWD_LEN, and the number of bytes

of the current password.

3. Send (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 1), the length (PWD_LEN), and the password (PWD) itself.

4. When the password is matched, the card is locked and the CARD_IS_LOCKED status bit is set in the card status register. When the password sent does not correspond (in size and/or content) to the expected password, the LOCK_UNLOCK_FAILED error bit is set in the card status register, and the lock fails.

It is possible to set the password and to lock the card in the same sequence. In this case, the SDIO card host module performs all the required steps for setting the password (see

Setting the password on page 633

), however it is necessary to set the LOCK_UNLOCK bit in Step 3 when the new password command is sent.

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When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power-on reset. An attempt to lock a locked card or to lock a card that does not have a password fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.

Unlocking the card

Select a card (

SELECT/DESELECT_CARD

, CMD7), if none is already selected.

2. Define the block length (

SET_BLOCKLEN

, CMD16) to send, given by the 8-bit cardlock/unlock mode (byte 0 in

Table 115 ), the 8-bit PWD_LEN, and the number of

bytes of the current password.

3. Send (CMD42) with the appropriate data block size on the data line including the 16-bit CRC. The data block indicates the mode (LOCK_UNLOCK = 0), the length (PWD_LEN), and the password (PWD) itself.

4. When the password is matched, the card is unlocked and the CARD_IS_LOCKED status bit is cleared in the card status register. When the password sent is not correct in size and/or content and does not correspond to the expected password, the

LOCK_UNLOCK_FAILED error bit is set in the card status register, and the card remains locked.

The unlocking function is only valid for the current power session. When the PWD field is not clear, the card is locked automatically on the next power-up.

An attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.

Forcing erase

If the user has forgotten the password (PWD content), it is possible to access the card after clearing all the data on the card. This forced erase operation erases all card data and all password data.

Select a card (

SELECT/DESELECT_CARD

, CMD7), if none is already selected.

2. Set the block length (

SET_BLOCKLEN

, CMD16) to 1 byte. Only the 8-bit card

lock/unlock byte (byte 0 in Table 115 ) is sent.

3. Send (CMD42) with the appropriate data byte on the data line including the 16-bit CRC. The data block indicates the mode (ERASE = 1). All other bits must be zero.

4. When the ERASE bit is the only bit set in the data field, all card contents are erased, including the PWD and PWD_LEN fields, and the card is no longer locked. When any other bits are set, the LOCK_UNLOCK_FAILED error bit is set in the card status register and the card retains all of its data, and remains locked.

An attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.

The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card status information (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previously issued command.

Table 102

defines the different entries of the status. The type and clear condition fields in the table are abbreviated as follows:

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Type:

• E: error bit

• S: status bit

• R: detected and set for the actual command response

• X: detected and set during command execution. The SDIO card host must poll the card by issuing the status command to read these bits.

Clear condition:

• A: according to the card current state

• B: always related to the previous command. Reception of a valid command clears it

(with a delay of one command)

• C: clear by read

Bits

Identifier

ADDRESS_

OUT_OF_RANGE

E R X

’0’= no error

’1’= error

ADDRESS_MISALIGN -

BLOCK_LEN_ERROR -

ERASE_SEQ_ERROR -

Table 102. Card status

Type Value

’0’= no error

’1’= error

’0’= no error

’1’= error

’0’= no error

’1’= error

Description

The command address argument was out of the allowed range for this card.

A multiple block or stream read/write operation is (although started in a valid address) attempting to read or write beyond the card capacity.

The commands address argument (in accordance with the currently set block length) positions the first data block misaligned to the card physical blocks.

A multiple block read/write operation

(although started with a valid address/block-length combination) is attempting to read or write a data block which is not aligned with the physical blocks of the card.

An error in the sequence of erase commands occurred.

Either the argument of a

SET_BLOCKLEN command exceeds the maximum value allowed for the card, or the previously defined block length is illegal for the current command (e.g. the host issues a write command, the current block length is smaller than the maximum allowed value for the card and it is not allowed to write partial blocks)

An invalid selection of erase groups for erase occurred.

Attempt to program a write-protected block. C

Clear condition

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Bits

Table 102. Card status (continued)

Identifier Type Value Description

LOCK_UNLOCK_

FAILED

E X

‘0’ = card

‘1’ = card locked

When set, signals that the card is locked by the host

’0’= no error

’1’= error

Set when a sequence or password error has been detected in lock/unlock card command

The CRC check of the previous command failed.

B COM_CRC_ERROR E

’0’= no error

’1’= error

’0’= no error

’1’= error

’0’= success

’1’= failure

Command not legal for the card state B

Card internal ECC was applied but failed to correct the data.

(Undefined by the standard) A card error occurred, which is not related to the host command.

(Undefined by the standard) A generic card error related to the (and detected during) execution of the last host command (e.g. read or write failures).

Reserved

’0’= no error ‘1’= error

Can be either of the following errors:

– The CID register has already been written and cannot be overwritten

– The read-only section of the CSD does not match the card contents

– An attempt to reverse the copy (set as original) or permanent WP

(unprotected) bits was made

Clear condition

CARD_ECC_DISABLED S X

ERASE_RESET -

’0’= enabled

’1’= disabled

’0’= cleared

’1’= set

Set when only partial address space was erased due to existing write

The command has been executed without using the internal ECC.

An erase sequence was cleared before executing because an out of erase sequence command was received

(commands other than CMD35, CMD36,

CMD38 or CMD13)

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Table 102. Card status (continued)

Bits Identifier Type Value Description

0 = Idle

1 = Ready

2 = Ident

3 = Stby

4 = Tran

12:9 5 = Data

6 = Rcv

7 = Prg

8 = Dis

9 = Btst

10-15 = reserved

The state of the card when receiving the command. If the command execution causes a state change, it will be visible to the host in the response on the next command. The four bits are interpreted as a binary number between 0 and 15.

READY_FOR_DATA S

’0’= not ready ‘1’

= ready

Corresponds to buffer empty signalling on the bus

If set, the card did not switch to the expected mode as requested by the

SWITCH command

6 Reserved

The card will expect ACMD, or an indication that the command has been interpreted as ACMD

Reserved for SD I/O Card

AKE_SEQ_ERROR E R

’0’= no error

’1’= error

Reserved for application specific commands

Error in the sequence of the authentication process

Reserved for manufacturer test mode

Clear condition

21.4.12 SD status register

The SD status contains status bits that are related to the SD memory card proprietary features and may be used for future application-specific usage. The size of the SD Status is one data block of 512 bits. The contents of this register are transmitted to the SDIO card host if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a card in transfer state only (card is selected).

Table 103

defines the different entries of the SD status register. The type and clear condition fields in the table are abbreviated as follows:

Type:

• E: error bit

• S: status bit

• R: detected and set for the actual command response

• X: detected and set during command execution. The SDIO card Host must poll the card by issuing the status command to read these bits

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Clear condition:

• A: according to the card current state

• B: always related to the previous command. Reception of a valid command clears it

(with a delay of one command)

• C: clear by read

Table 103. SD status

Bits

509

Identifier Type

511: 510 DAT_BUS_WIDTH S R

SECURED_MODE S R

’00’= 1 (default)

‘01’= reserved

‘10’= 4 bit width

‘11’= reserved

Value

’0’= Not in the mode

’1’= In Secured Mode

Description

Shows the currently defined databus width that was defined by

SET_BUS_WIDTH command

Card is in Secured Mode of operation (refer to the “SD

Security Specification”).

Clear condition

508: 496 Reserved

495: 480 SD_CARD_TYPE

479: 448

439: 432

SIZE_OF_PROTE

CT ED_AREA

447: 440 SPEED_CLASS

PERFORMANCE_

MOVE

431:428 AU_SIZE

S R

’00xxh’= SD Memory Cards as defined in Physical Spec Ver1.01-

2.00 (’x’= don’t care). The following cards are currently defined:

’0000’= Regular SD RD/WR Card.

’0001’= SD ROM Card

In the future, the 8 LSBs will be used to define different variations of an SD memory card (each bit will define different SD types). The 8

MSBs will be used to define

SD Cards that do not comply with current SD physical layer specification.

Size of protected area (See below)

(See below) A

Speed Class of the card (See below)

Size of AU

(See below)

Performance of move indicated by

1 [MB/s] step.

(See below)

427:424 Reserved

423:408 ERASE_SIZE

407:402 ERASE_TIMEOUT S R

401:400 ERASE_OFFSET

S R

399:312 Reserved

311:0 Reserved for Manufacturer

Number of AUs to be erased at a time

(See below)

Timeout value for erasing areas specified by

UNIT_OF_ERASE_AU

(See below)

Fixed offset value added to erase time.

(See below)

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SIZE_OF_PROTECTED_AREA

Setting this field differs between standard- and high-capacity cards. In the case of a standard-capacity card, the capacity of protected area is calculated as follows:

Protected area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN.

SIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN.

In the case of a high-capacity card, the capacity of protected area is specified in this field:

Protected area = SIZE_OF_PROTECTED_AREA

SIZE_OF_PROTECTED_AREA is specified by the unit in bytes.

SPEED_CLASS

This 8-bit field indicates the speed class and the value can be calculated by P

is the write performance).

/2 (where

00h

01h

02h

03h

04h – FFh

SPEED_CLASS

Table 104. Speed class code field

Value definition

Class 0

Class 2

Class 4

Class 6

Reserved

PERFORMANCE_MOVE

This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps. If the card does not move used RUs (recording units), Pm should be considered as infinity. Setting the field to FFh means infinity.

00h

01h

02h

---------

FEh

FFh

Table 105. Performance move field

PERFORMANCE_MOVE Value definition

Not defined

1 [MB/sec]

02h 2 [MB/sec]

---------

254 [MB/sec]

Infinity

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04h

05h

06h

07h

00h

01h

02h

03h

08h

09h

Ah – Fh

AU_SIZE

This 4-bit field indicates the AU size and the value can be selected in the power of 2 base from 16 KB.

AU_SIZE

Table 106. AU_SIZE field

Value definition

Not defined

16 KB

32 KB

64 KB

128 KB

256 KB

512 KB

1 MB

2 MB

4 MB

Reserved

The maximum AU size, which depends on the card capacity, is defined in

Table 107 . The

card can be set to any AU size between RU size and maximum AU size.

Capacity

Maximum AU Size

Table 107. Maximum AU size

16 MB-64 MB 128 MB-256 MB 512 MB

512 KB 1 MB 2 MB

1 GB-32 GB

4 MB

ERASE_SIZE

This 16-bit field indicates NERASE. When NERASE numbers of AUs are erased, the timeout value is specified by ERASE_TIMEOUT (Refer to

ERASE_TIMEOUT ). The host

should determine the proper number of AUs to be erased in one operation so that the host can show the progress of the erase operation. If this field is set to 0, the erase timeout calculation is not supported.

0000h

ERASE_SIZE

Table 108. Erase size field

Value definition

Erase timeout calculation is not supported.

0002h

0003h

---------

FFFFh

2 AU

3 AU

---------

65535 AU

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ERASE_TIMEOUT

This 6-bit field indicates TERASE and the value indicates the erase timeout from offset when multiple AUs are being erased as specified by ERASE_SIZE. The range of

ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation. Determining ERASE_TIMEOUT determines the ERASE_SIZE.

ERASE_TIMEOUT

Table 109. Erase timeout field

Value definition

Erase timeout calculation is not supported.

---------

2 [sec]

3 [sec]

---------

63 [sec]

ERASE_OFFSET

This 2-bit field indicates T

OFFSET and one of four values can be selected. This field is meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0.

ERASE_OFFSET

Table 110. Erase offset field

Value definition

2 [sec]

3 [sec]

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SD I/O interrupts

To allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is available on a pin on the SD interface. Pin 8, used as SDIO_D1 when operating in the 4-bit

SD mode, signals the cards interrupt to the MultiMediaCard/SD module. The use of the interrupt is optional for each card or function within a card. The SD I/O interrupt is levelsensitive, which means that the interrupt line must be held active (low) until it is either recognized and acted upon by the MultiMediaCard/SD module or deasserted due to the end of the interrupt period. After the MultiMediaCard/SD module has serviced the interrupt, the interrupt status bit is cleared via an I/O write to the appropriate bit in the SD I/O card’s internal registers. The interrupt output of all SD I/O cards is active low and the application must provide external pull-up resistors on all data lines (SDIO_D[3:0]). The

MultiMediaCard/SD module samples the level of pin 8 (SDIO_D/IRQ) into the interrupt detector only during the interrupt period. At all other times, the MultiMediaCard/SD module ignores this value.

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The interrupt period is applicable for both memory and I/O operations. The definition of the interrupt period for operations with single blocks is different from the definition for multipleblock data transfers.

SD I/O suspend and resume

Within a multifunction SD I/O or a card with both I/O and memory functions, there are multiple devices (I/O and memory) that share access to the MMC/SD bus. To share access to the MMC/SD module among multiple devices, SD I/O and combo cards optionally implement the concept of suspend/resume. When a card supports suspend/resume, the

MMC/SD module can temporarily halt a data transfer operation to one function or memory

(suspend) to free the bus for a higher-priority transfer to a different function or memory. After this higher-priority transfer is complete, the original transfer is resumed (restarted) where it left off. Support of suspend/resume is optional on a per-card basis. To perform the suspend/resume operation on the MMC/SD bus, the MMC/SD module performs the following steps:

Determines the function currently using the SDIO_D [3:0] line(s)

2. Requests the lower-priority or slower transaction to suspend

3. Waits for the transaction suspension to complete

4. Begins the higher-priority transaction

5. Waits for the completion of the higher priority transaction

6. Restores the suspended transaction

SD I/O ReadWait

The optional ReadWait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The

ReadWait operation allows the MMC/SD module to signal a card that it is reading multiple registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within the SD I/O device. To determine when a card supports the ReadWait protocol, the MMC/SD module must test capability bits in the internal card registers. The timing for ReadWait is based on the interrupt period.

21.4.14 Commands and responses

Application-specific and general commands

The SD card host module system is designed to provide a standard interface for a variety of applications types. In this environment, there is a need for specific customer/application features. To implement these features, two types of generic commands are defined in the standard: application-specific commands (ACMD) and general commands (GEN_CMD).

When the card receives the APP_CMD (CMD55) command, the card expects the next command to be an application-specific command. ACMDs have the same structure as regular MultiMediaCard commands and can have the same CMD number. The card recognizes it as ACMD because it appears after APP_CMD (CMD55). When the command immediately following the APP_CMD (CMD55) is not a defined application-specific command, the standard command is used. For example, when the card has a definition for

SD_STATUS (ACMD13), and receives CMD13 immediately following APP_CMD (CMD55), this is interpreted as SD_STATUS (ACMD13). However, when the card receives CMD7 immediately following APP_CMD (CMD55) and the card does not have a definition for

ACMD7, this is interpreted as the standard (SELECT/DESELECT_CARD) CMD7.

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To use one of the manufacturer-specific ACMDs the SD card Host must perform the following steps:

Send APP_CMD (CMD55)

The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and an ACMD is now expected.

2. Send the required ACMD

The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and that the accepted command is interpreted as an ACMD. When a nonACMD is sent, it is handled by the card as a normal MultiMediaCard command and the

APP_CMD bit in the card status register stays clear.

When an invalid command is sent (neither ACMD nor CMD) it is handled as a standard

MultiMediaCard illegal command error.

The bus transaction for a GEN_CMD is the same as the single-block read or write commands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the argument denotes the direction of the data transfer rather than the address, and the data block has vendor-specific format and meaning.

The card must be selected (in transfer state) before sending GEN_CMD (CMD56). The data block size is defined by SET_BLOCKLEN (CMD16). The response to GEN_CMD (CMD56) is in R1b format.

Command types

Both application-specific and general commands are divided into the four following types:

• broadcast command (BC) : sent to all cards; no responses returned.

• broadcast command with response (BCR): sent to all cards; responses received from all cards simultaneously.

• addressed (point-to-point) command (AC): sent to the card that is selected; does not include a data transfer on the SDIO_D line(s).

• addressed (point-to-point) data transfer command (ADTC): sent to the card that is selected; includes a data transfer on the SDIO_D line(s).

Command formats

See

Table 95 on page 620

for command formats.

Commands for the MultiMediaCard/SD module

CMD index

Type Argument

Table 111. Block-oriented write commands

Response format

Abbreviation

CMD23 ac

CMD24 adtc

[31:16] set to 0

[15:0] number of blocks

[31:0] data address

SET_BLOCK_COUNT

WRITE_BLOCK

Description

Defines the number of blocks which are going to be transferred in the multiple-block read or write command that follows.

Writes a block of the size selected by the SET_BLOCKLEN command.

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CMD index

Table 111. Block-oriented write commands (continued)

Type Argument

Response format

Abbreviation Description

CMD25 adtc

[31:0] data address

CMD26 adtc [31:0] stuff bits R1

CMD27 adtc [31:0] stuff bits R1

WRITE_MULTIPLE_BLOCK

Continuously writes blocks of data until a STOP_TRANSMISSION follows or the requested number of blocks has been received.

PROGRAM_CID

Programming of the card identification register. This command must be issued only once per card. The card contains hardware to prevent this operation after the first programming.

Normally this command is reserved for manufacturer.

PROGRAM_CSD

Programming of the programmable bits of the CSD.

CMD index

CMD28 ac

CMD29 ac

CMD30 adtc

Type

Table 112. Block-oriented write protection commands

Argument

Response format

Abbreviation Description

[31:0] data address

[31:0] write protect data address

R1b

SET_WRITE_PROT

CLR_WRITE_PROT

SEND_WRITE_PROT

If the card has write protection features, this command sets the write protection bit of the addressed group. The properties of write protection are coded in the cardspecific data (WP_GRP_SIZE).

If the card provides write protection features, this command clears the write protection bit of the addressed group.

If the card provides write protection features, this command asks the card to send the status of the write protection bits.

CMD31 Reserved

CMD index

Type Argument

Table 113. Erase commands

Response format

Abbreviation Description

CMD32

...

CMD34

Reserved. These command indexes cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCard.

CMD35 ac

CMD36 ac

[31:0] data address R1

ERASE_GROUP_START

ERASE_GROUP_END

Sets the address of the first erase group within a range to be selected for erase.

Sets the address of the last erase group within a continuous range to be selected for erase.

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CMD index

Type Argument

Table 113. Erase commands (continued)

Response format

Abbreviation Description

CMD37

Reserved. This command index cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCards

CMD38 ac [31:0] stuff bits R1

ERASE

Erases all previously selected write blocks.

CMD index

CMD39 ac

Type Argument

[31:16] RCA

[15:15] register write flag

[14:8] register address

[7:0] register data

CMD40 bcr [31:0] stuff bits

CMD41 Reserved

Table 114. I/O mode commands

Response format

Abbreviation

Description

FAST_IO

Used to write and read 8-bit (register) data fields. The command addresses a card and a register and provides the data for writing if the write flag is set. The R4 response contains data read from the addressed register. This command accesses application-dependent registers that are not defined in the MultiMediaCard standard.

GO_IRQ_STATE

Places the system in the interrupt mode.

CMD index

Type Argument

Table 115. Lock card

Response format

Abbreviation

CMD42 adtc [31:0] stuff bits R1b

LOCK_UNLOCK

Description

Sets/resets the password or locks/unlocks the card. The size of the data block is set by the SET_BLOCK_LEN command.

CMD43

...

CMD54

Reserved

CMD index

Type

CMD55 ac

CMD56 adtc

Argument

Table 116. Application-specific commands

Response format

Abbreviation

[31:16] RCA

[15:0] stuff bits

[31:1] stuff bits

[0]: RD/WR

APP_CMD

Description

Indicates to the card that the next command bits is an application specific command rather than a standard command

Used either to transfer a data block to the card or to get a data block from the card for general purpose/application-specific commands. The size of the data block shall be set by the

SET_BLOCK_LEN command.

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CMD index

CMD57

...

CMD59

CMD60

...

CMD63

Type

Reserved.

Table 116. Application-specific commands (continued)

Argument

Response format

Reserved for manufacturer.

Abbreviation Description

All responses are sent via the MCCMD command line SDIO_CMD. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type.

A response always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (card = 0). A value denoted by x in the tables below indicates a variable entry. All responses, except for the R3 response type, are protected by a CRC.

Every command code word is terminated by the end bit (always 1).

There are five types of responses. Their formats are defined as follows:

21.5.1 R1 (normal response command)

Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the card is coded in 32 bits.

Bit position

[45:40]

[39:8]

[7:1]

Table 117. R1 response

Width (bits Value

Description

Start bit

Transmission bit

Command index

Card status

CRC7

End bit

21.5.2 R1b

It is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception.

21.5.3 R2 (CID, CSD register)

Code length = 136 bits. The contents of the CID register are sent as a response to the

CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to

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CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. The card indicates that an erase is in progress by holding MCDAT low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card.

Bit position

135

134

[133:128]

[127:1]

127

Table 118. R2 response

Width (bits Value

‘111111’

Description

Start bit

Transmission bit

Command index

Card status

End bit

Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1.

The level coding is as follows: restricted voltage windows = low, card busy = low.

Bit position

[45:40]

[39:8]

[7:1]

Table 119. R3 response

Width (bits Value

‘111111’

‘1111111’

Description

Start bit

Transmission bit

Reserved

OCR register

Reserved

End bit

21.5.5 R4 (Fast I/O)

Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read from or written to, and its content.

[45:40]

Bit position

[39:8] Argument field

[31:16] 16

[15:8] 8

[7:0] 8

Table 120. R4 response

Width (bits Value

‘100111’

Description

Start bit

Transmission bit

CMD39

RCA register address read register contents

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Table 120. R4 response (continued)

Width (bits Value

CRC7

End bit

Description

21.5.6 R4b

For SD I/O only: an SDIO card receiving the CMD5 will respond with a unique SDIO response R4. The format is:

[45:40]

[7:1]

Bit position

[39:8] Argument field

[38:36] 3

35 1

[34:32] 3

[31:8] 24

Table 121. R4b response

Width (bits Value

0 x

Description

Start bit

Transmission bit

Reserved

Card is ready

Number of I/O functions

Present memory

Stuff bits

I/O ORC

Reserved

End bit

Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card. Note that an SD memory-only card may respond to a CMD5. The proper response for a memory-only card would be Present memory = 1 and Number of I/O functions = 0. A memory-only card built to meet the SD Memory Card specification version 1.0 would detect the CMD5 as an illegal command and not respond. The I/O aware host will send CMD5. If the card responds with response R4, the host determines the card’s configuration based on the data contained within the R4 response.

21.5.7 R5 (interrupt request)

Only for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the

RCA field in the argument will be 0x0.

[45:40]

Bit position

Table 122. R5 response

Width (bits Value

‘101000’

Description

Start bit

Transmission bit

CMD40

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[7:1]

Bit position

[39:8] Argument field

[31:16] 16

[15:0]

Table 122. R5 response (continued)

Width (bits Value

Description

RCA [31:16] of winning card or of the host

Not defined. May be used for IRQ data

CRC7

End bit

21.5.8 R6

Only for SD I/O. The normal response to CMD3 by a memory device. It is shown in

Table 123

[45:40]

Bit position

[39:8] Argument field

[7:1]

[31:16] 16

[15:0] 16

Table 123. R6 response

Width (bits) Value Description

0 Start bit

0 Transmission bit

‘101000’ CMD40

X RCA [31:16] of winning card or of the host

Not defined. May be used for IRQ data

CRC7

End bit

The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case, the 16 bits of response are the SD I/O-only values:

• Bit [15] COM_CRC_ERROR

• Bit [14] ILLEGAL_COMMAND

• Bit [13] ERROR

• Bits [12:0] Reserved

21.6 SDIO I/O card-specific operations

The following features are SD I/O-specific operations:

• SDIO read wait operation by SDIO_D2 signalling

• SDIO read wait operation by stopping the clock

• SDIO suspend/resume operation (write and read suspend)

• SDIO interrupts

The SDIO supports these operations only if the SDIO_DCTRL[11] bit is set, except for read suspend that does not need specific hardware implementation.

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21.6.1 SDIO I/O read wait operation by SDIO_D2 signaling

It is possible to start the readwait interval before the first block is received: when the data path is enabled (SDIO_DCTRL[0] bit set), the SDIO-specific operation is enabled

(SDIO_DCTRL[11] bit set), read wait starts (SDI0_DCTRL[10] =0 and SDI_DCTRL[8] =1) and data direction is from card to SDIO (SDIO_DCTRL[1] = 1), the DPSM directly moves from Idle to Readwait. In Readwait the DPSM drives SDIO_D2 to 0 after 2 SDIO_CK clock cycles. In this state, when you set the RWSTOP bit (SDIO_DCTRL[9]), the DPSM remains in Wait for two more SDIO_CK clock cycles to drive SDIO_D2 to 1 for one clock cycle (in accordance with SDIO specification). The DPSM then starts waiting again until it receives data from the card. The DPSM will not start a readwait interval while receiving a block even if read wait start is set: the readwait interval will start after the CRC is received. The

RWSTOP bit has to be cleared to start a new read wait operation. During the readwait interval, the SDIO can detect SDIO interrupts on SDIO_D1.

21.6.2 SDIO read wait operation by stopping SDIO_CK

If the SDIO card does not support the previous read wait method, the SDIO can perform a read wait by stopping SDIO_CK (SDIO_DCTRL is set just like in the method presented in

Section 21.6.1

, but SDIO_DCTRL[10] =1): DSPM stops the clock two SDIO_CK cycles after

the end bit of the current received block and starts the clock again after the read wait start bit is set.

As SDIO_CK is stopped, any command can be issued to the card. During a read/wait interval, the SDIO can detect SDIO interrupts on SDIO_D1.

21.6.3 SDIO suspend/resume operation

While sending data to the card, the SDIO can suspend the write operation. the

SDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command. The CPSM analyzes the response and when the ACK is received from the card

(suspend accepted), it acknowledges the DPSM that goes Idle after receiving the CRC token of the current block.

The hardware does not save the number of the remaining block to be sent to complete the suspended operation (resume).

The write operation can be suspended by software, just by disabling the DPSM

(SDIO_DCTRL[0] =0) when the ACK of the suspend command is received from the card.

The DPSM enters then the Idle state.

To suspend a read: the DPSM waits in the Wait_r state as the function to be suspended sends a complete packet just before stopping the data transaction. The application continues reading RxFIFO until the FIF0 is empty, and the DPSM goes Idle automatically.

SDIO interrupts are detected on the SDIO_D1 line once the SDIO_DCTRL[11] bit is set.

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21.7 CE-ATA specific operations

The following features are CE-ATA specific operations:

• sending the command completion signal disable to the CE-ATA device

• receiving the command completion signal from the CE-ATA device

• signaling the completion of the CE-ATA command to the CPU, using the status bit and/or interrupt.

The SDIO supports these operations only for the CE-ATA CMD61 command, that is, if

SDIO_CMD[14] is set.

21.7.1 Command completion signal disable

Command completion signal disable is sent 8 bit cycles after the reception of a short response if the ‘enable CMD completion’ bit, SDIO_CMD[12], is not set and the ‘not interrupt

Enable’ bit, SDIO_CMD[13], is set.

The CPSM enters the Pend state, loading the command shift register with the disable sequence “00001” and, the command counter with 43. Eight cycles after, a trigger moves the CPSM to the Send state. When the command counter reaches 48, the CPSM becomes

Idle as no response is awaited.

21.7.2 Command completion signal enable

If the ‘enable CMD completion’ bit SDIO_CMD[12] is set and the ‘not interrupt Enable’ bit

SDIO_CMD[13] is set, the CPSM waits for the command completion signal in the Waitcpl state.

When ‘0’ is received on the CMD line, the CPSM enters the Idle state. No new command can be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the CMD line is driven to

‘1’ in push-pull mode.

The command completion is signaled to the CPU by the status bit SDIO_STA[23]. This static bit can be cleared with the clear bit SDIO_ICR[23].

The SDIO_STA[23] status bit can generate an interrupt on each interrupt line, depending on the mask bit SDIO_MASKx[23].

If the command completion disable signal has not been sent and CMD61 needs to be aborted, the command state machine must be disabled. It then becomes Idle, and the

CMD12 command can be sent. No command completion disable signal is sent during the operation.

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The HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun

(RX mode) errors.

The behavior is to stop SDIO_CK and freeze SDIO state machines. The data transfer is stalled while the FIFO is unable to transmit or receive data. Only state machines clocked by

SDIOCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or emptied even if flow control is activated.

To enable HW flow control, the SDIO_CLKCR[14] register bit must be set to 1. After reset

Flow Control is disabled.

The device communicates to the system via 32-bit-wide control registers accessible via

APB2.

The peripheral registers have to be accessed by words (32 bits).

21.9.1 SDIO power control register (SDIO_POWER)

Address offset: 0x00

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

PWRC

TRL rw rw

Bits 31:2 Reserved, must be kept at reset value

Bits 1:0 PWRCTRL: Power supply control bits.

These bits are used to define the current functional state of the card clock:

00: Power-off: the clock to card is stopped.

01: Reserved

10: Reserved power-up

11: Power-on: the card is clocked.

Note: At least seven HCLK clock periods are needed between two write accesses to this register.

After a data write, data cannot be written to this register for three SDIOCLK clock periods plus two PCLK2 clock periods.

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Address offset: 0x04

Reset value: 0x0000 0000

The SDIO_CLKCR register controls the SDIO_CK output clock.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WID

BUS

CLKDIV

Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value

Bit 14 HWFC_EN: HW Flow Control enable

0b: HW Flow Control is disabled

1b: HW Flow Control is enabled

When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt signals, please see SDIO Status register definition in

Section 21.9.11

Bit 13 NEGEDGE: SDIO_CK dephasing selection bit

0b: SDIO_CK generated on the rising edge of the master clock SDIOCLK

1b: SDIO_CK generated on the falling edge of the master clock SDIOCLK

Bits 12:11 WIDBUS: Wide bus mode enable bit

00: Default bus mode: SDIO_D0 used

01: 4-wide bus mode: SDIO_D[3:0] used

10: 8-wide bus mode: SDIO_D[7:0] used

Bit 10 BYPASS: Clock divider bypass enable bit

0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the

SDIO_CK output signal.

1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal.

Bit 9 PWRSAV: Power saving configuration bit

For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting

PWRSAV:

0: SDIO_CK clock is always enabled

1: SDIO_CK is only enabled when the bus is active

Bit 8 CLKEN: Clock enable bit

0: SDIO_CK is disabled

1: SDIO_CK is enabled

Bits 7:0 CLKDIV: Clock divide factor

This field defines the divide factor between the input clock (SDIOCLK) and the output clock

(SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2].

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Note: While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK frequency must be less than 400 kHz.

The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards.

After a data write, data cannot be written to this register for three SDIOCLK clock periods plus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval for SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK.

21.9.3 SDIO argument register (SDIO_ARG)

Address offset: 0x08

Reset value: 0x0000 0000

The SDIO_ARG register contains a 32-bit command argument, which is sent to a card as part of a command message.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CMDARG rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CMDARG: Command argument

Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register.

Address offset: 0x0C

Reset value: 0x0000 0000

The SDIO_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value

Bit 14 ATACMD: CE-ATA command

If ATACMD is set, the CPSM transfers CMD61.

Bit 13 nIEN: not Interrupt Enable if this bit is 0, interrupts in the CE-ATA device are enabled.

Bit 12 ENCMDcompl: Enable CMD completion

If this bit is set, the command completion signal is enabled.

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Bit 11 SDIOSuspend: SD I/O suspend command

If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card).

Bit 10 CPSMEN: Command path state machine (CPSM) Enable bit

If this bit is set, the CPSM is enabled.

Bit 9 WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal).

If this bit is set, the CPSM waits for the end of data transfer before it starts sending a command.

Bit 8 WAITINT: CPSM waits for interrupt request

If this bit is set, the CPSM disables command timeout and waits for an interrupt request.

Bits 7:6 WAITRESP : Wait for response bits

They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response.

00: No response, expect CMDSENT flag

01: Short response, expect CMDREND or CCRCFAIL flag

10: No response, expect CMDSENT flag

11: Long response, expect CMDREND or CCRCFAIL flag

Bits 5:0 CMDINDEX: Command index

The command index is sent to the card as part of a command message.

After a data write, data cannot be written to this register for three SDIOCLK clock periods plus two PCLK2 clock periods.

MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long responses,136 bits long. SD card and SD I/O card can send only short responses, the argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. CE-ATA devices send only short responses.

Address offset: 0x10

Reset value: 0x0000 0000

The SDIO_RESPCMD register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved r r

RESPCMD r r r r

Bits 31:6 Reserved, must be kept at reset value

Bits 5:0 RESPCMD: Response command index

Read-only bit field. Contains the command index of the last command response received.

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21.9.6 SDIO response 1..4 register (SDIO_RESPx)

Address offset: (0x10 + (4 × x)); x = 1..4

Reset value: 0x0000 0000

The SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received response.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CARDSTATUSx r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r

Bits 31:0 CARDSTATUSx: see

Table 124

The Card Status size is 32 or 127 bits, depending on the response type.

Register

SDIO_RESP1

SDIO_RESP2

SDIO_RESP3

SDIO_RESP4

Table 124. Response type and SDIO_RESPx registers

Short response Long response

Card Status[31:0]

Unused

Card Status [127:96]

Card Status [95:64]

Card Status [63:32]

Card Status [31:1]0b

The most significant bit of the card status is received first. The SDIO_RESP3 register LSB is always 0b.

21.9.7 SDIO data timer register (SDIO_DTIMER)

Address offset: 0x24

Reset value: 0x0000 0000

The SDIO_DTIMER register contains the data timeout period, in card bus clock periods.

A counter loads the value from the SDIO_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATATIME rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DATATIME: Data timeout period

Data timeout period expressed in card bus clock periods.

Note: A data transfer must be written to the data timer register and the data length register before being written to the data control register.

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Address offset: 0x28

Reset value: 0x0000 0000

The SDIO_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATALENGTH

Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value

Bits 24:0 DATALENGTH: Data length value

Number of data bytes to be transferred.

Note: For a block data transfer, the value in the data length register must be a multiple of the block size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the data length register before being written to the data control register.

For an SDIO multibyte transfer the value in the data length register must be between 1 and

512.

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Address offset: 0x2C

Reset value: 0x0000 0000

The SDIO_DCTRL register control the data path state machine (DPSM).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DBLOCKSIZE

Reserved rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value

Bit 11 SDIOEN: SD I/O enable functions

If this bit is set, the DPSM performs an SD I/O-card-specific operation.

Bit 10 RWMOD: Read wait mode

0: Read Wait control stopping SDIO_D2

1: Read Wait control using SDIO_CK

Bit 9 RWSTOP: Read wait stop

0: Read wait in progress if RWSTART bit is set

1: Enable for read wait stop if RWSTART bit is set

Bit 8 RWSTART: Read wait start

If this bit is set, read wait operation starts.

Bits 7:4 DBLOCKSIZE: Data block size

Define the data block length when the block data transfer mode is selected:

0000: (0 decimal) lock length = 2 0 = 1 byte

0001: (1 decimal) lock length = 2 1 = 2 bytes

0010: (2 decimal) lock length = 2 2 = 4 bytes

0011: (3 decimal) lock length = 2 3 = 8 bytes

0100: (4 decimal) lock length = 2 4 = 16 bytes

0101: (5 decimal) lock length = 2 5 = 32 bytes

0110: (6 decimal) lock length = 2 6 = 64 bytes

0111: (7 decimal) lock length = 2 7 = 128 bytes

1000: (8 decimal) lock length = 2 8 = 256 bytes

1001: (9 decimal) lock length = 2 9 = 512 bytes

1010: (10 decimal) lock length = 2 10 = 1024 bytes

1011: (11 decimal) lock length = 2

1100: (12 decimal) lock length = 2

1101: (13 decimal) lock length = 2

= 2048 bytes

= 4096 bytes

= 8192 bytes

1110: (14 decimal) lock length = 2

= 16384 bytes

1111: (15 decimal) reserved

Bit 3 DMAEN: DMA enable bit

0: DMA disabled.

1: DMA enabled.

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Bit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

0: Block data transfer

1: Stream or SDIO multibyte data transfer

Bit 1 DTDIR: Data transfer direction selection

0: From controller to card.

1: From card to controller.

Bit 0 DTEN: Data transfer enabled bit

Data transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR, the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data transfer but the SDIO_DCTRL must be updated to enable a new data transfer

After a data write, data cannot be written to this register for three SDIOCLK clock periods plus two PCLK2 clock periods.

The meaning of the DTMODE bit changes according to the value of the SDIOEN bit. When

SDIOEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled, and when

SDIOEN=1 and DTMODE=1, the peripheral enables an SDIO multibyte transfer.

Address offset: 0x30

Reset value: 0x0000 0000

The SDIO_DCOUNT register loads the value from the data length register (see

SDIO_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and the data status end flag, DATAEND, is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved r r r r r r r r r r r

DATACOUNT r r r r r r r r r r r r r r

Bits 31:25 Reserved, must be kept at reset value

Bits 24:0 DATACOUNT: Data count value

When this bit is read, the number of remaining data bytes to be transferred is returned. Write has no effect.

Note: This register should be read only when the data transfer is complete.

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21.9.11 SDIO status register (SDIO_STA)

Address offset: 0x34

Reset value: 0x0000 0000

The SDIO_STA register is a read-only register. It contains two types of flag:

• Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the SDIO Interrupt Clear register (see SDIO_ICR)

• Dynamic flags (bits [21:11]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and deasserted as data while written to the FIFO)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r r r r r r r r r r r

Bits 31:24 Reserved, must be kept at reset value

Bit 23 CEATAEND: CE-ATA command completion signal received for CMD61

Bit 22 SDIOIT: SDIO interrupt received

Bit 21 RXDAVL: Data available in receive FIFO

Bit 20 TXDAVL: Data available in transmit FIFO

Bit 19 RXFIFOE: Receive FIFO empty

Bit 18 TXFIFOE: Transmit FIFO empty

When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words.

Bit 17 RXFIFOF: Receive FIFO full

When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the

FIFO is full.

Bit 16 TXFIFOF: Transmit FIFO full

Bit 15 RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO

Bit 14 TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into the FIFO

Bit 13 RXACT: Data receive in progress

Bit 12 TXACT: Data transmit in progress

Bit 11 CMDACT: Command transfer in progress

Bit 10 DBCKEND: Data block sent/received (CRC check passed)

Bit 9 STBITERR: Start bit not detected on all data signals in wide bus mode

Bit 8 DATAEND: Data end (data counter, SDIDCOUNT, is zero)

Bit 7 CMDSENT: Command sent (no response required)

Bit 6 CMDREND: Command response received (CRC check passed)

Bit 5 RXOVERR: Received FIFO overrun error

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Bit 4 TXUNDERR: Transmit FIFO underrun error

Bit 3 DTIMEOUT: Data timeout

Bit 2 CTIMEOUT: Command response timeout

The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.

Bit 1 DCRCFAIL: Data block sent/received (CRC check failed)

Bit 0 CCRCFAIL: Command response received (CRC check failed)

21.9.12 SDIO interrupt clear register (SDIO_ICR)

Address offset: 0x38

Reset value: 0x0000 0000

The SDIO_ICR register is a write-only register. Writing a bit with 1b clears the corresponding bit in the SDIO_STA Status register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved Reserved rw rw

Bits 31:24 Reserved, must be kept at reset value

Bit 23 CEATAENDC: CEATAEND flag clear bit

Set by software to clear the CEATAEND flag.

0: CEATAEND not cleared

1: CEATAEND cleared

Bit 22 SDIOITC: SDIOIT flag clear bit

Set by software to clear the SDIOIT flag.

0: SDIOIT not cleared

1: SDIOIT cleared

Bits 21:11 Reserved, must be kept at reset value

Bit 10 DBCKENDC: DBCKEND flag clear bit

Set by software to clear the DBCKEND flag.

0: DBCKEND not cleared

1: DBCKEND cleared

Bit 9 STBITERRC: STBITERR flag clear bit

Set by software to clear the STBITERR flag.

0: STBITERR not cleared

1: STBITERR cleared

Bit 8 DATAENDC: DATAEND flag clear bit

Set by software to clear the DATAEND flag.

0: DATAEND not cleared

1: DATAEND cleared rw rw rw rw rw rw rw rw rw rw rw

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Bit 7 CMDSENTC: CMDSENT flag clear bit

Set by software to clear the CMDSENT flag.

0: CMDSENT not cleared

1: CMDSENT cleared

Bit 6 CMDRENDC: CMDREND flag clear bit

Set by software to clear the CMDREND flag.

0: CMDREND not cleared

1: CMDREND cleared

Bit 5 RXOVERRC: RXOVERR flag clear bit

Set by software to clear the RXOVERR flag.

0: RXOVERR not cleared

1: RXOVERR cleared

Bit 4 TXUNDERRC: TXUNDERR flag clear bit

Set by software to clear TXUNDERR flag.

0: TXUNDERR not cleared

1: TXUNDERR cleared

Bit 3 DTIMEOUTC: DTIMEOUT flag clear bit

Set by software to clear the DTIMEOUT flag.

0: DTIMEOUT not cleared

1: DTIMEOUT cleared

Bit 2 CTIMEOUTC: CTIMEOUT flag clear bit

Set by software to clear the CTIMEOUT flag.

0: CTIMEOUT not cleared

1: CTIMEOUT cleared

Bit 1 DCRCFAILC: DCRCFAIL flag clear bit

Set by software to clear the DCRCFAIL flag.

0: DCRCFAIL not cleared

1: DCRCFAIL cleared

Bit 0 CCRCFAILC: CCRCFAIL flag clear bit

Set by software to clear the CCRCFAIL flag.

0: CCRCFAIL not cleared

1: CCRCFAIL cleared

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Address offset: 0x3C

Reset value: 0x0000 0000

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value

Bit 23 CEATAENDIE: CE-ATA command completion signal received interrupt enable

Set and cleared by software to enable/disable the interrupt generated when receiving the

CE-ATA command completion signal.

0: CE-ATA command completion signal received interrupt disabled

1: CE-ATA command completion signal received interrupt enabled

Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable

Set and cleared by software to enable/disable the interrupt generated when receiving the

SDIO mode interrupt.

0: SDIO Mode Interrupt Received interrupt disabled

1: SDIO Mode Interrupt Received interrupt enabled

Bit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable

Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Rx FIFO.

0: Data available in Rx FIFO interrupt disabled

1: Data available in Rx FIFO interrupt enabled

Bit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable

Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Tx FIFO.

0: Data available in Tx FIFO interrupt disabled

1: Data available in Tx FIFO interrupt enabled

Bit 19 RXFIFOEIE: Rx FIFO empty interrupt enable

Set and cleared by software to enable/disable interrupt caused by Rx FIFO empty.

0: Rx FIFO empty interrupt disabled

1: Rx FIFO empty interrupt enabled

Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable

Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.

0: Tx FIFO empty interrupt disabled

1: Tx FIFO empty interrupt enabled

Bit 17 RXFIFOFIE: Rx FIFO full interrupt enable

Set and cleared by software to enable/disable interrupt caused by Rx FIFO full.

0: Rx FIFO full interrupt disabled

1: Rx FIFO full interrupt enabled

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Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable

Set and cleared by software to enable/disable interrupt caused by Tx FIFO full.

0: Tx FIFO full interrupt disabled

1: Tx FIFO full interrupt enabled

Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable

Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.

0: Rx FIFO half full interrupt disabled

1: Rx FIFO half full interrupt enabled

Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable

Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty.

0: Tx FIFO half empty interrupt disabled

1: Tx FIFO half empty interrupt enabled

Bit 13 RXACTIE: Data receive acting interrupt enable

Set and cleared by software to enable/disable interrupt caused by data being received (data receive acting).

0: Data receive acting interrupt disabled

1: Data receive acting interrupt enabled

Bit 12 TXACTIE: Data transmit acting interrupt enable

Set and cleared by software to enable/disable interrupt caused by data being transferred

(data transmit acting).

0: Data transmit acting interrupt disabled

1: Data transmit acting interrupt enabled

Bit 11 CMDACTIE: Command acting interrupt enable

Set and cleared by software to enable/disable interrupt caused by a command being transferred (command acting).

0: Command acting interrupt disabled

1: Command acting interrupt enabled

Bit 10 DBCKENDIE: Data block end interrupt enable

Set and cleared by software to enable/disable interrupt caused by data block end.

0: Data block end interrupt disabled

1: Data block end interrupt enabled

Bit 9 STBITERRIE: Start bit error interrupt enable

Set and cleared by software to enable/disable interrupt caused by start bit error.

0: Start bit error interrupt disabled

1: Start bit error interrupt enabled

Bit 8 DATAENDIE: Data end interrupt enable

Set and cleared by software to enable/disable interrupt caused by data end.

0: Data end interrupt disabled

1: Data end interrupt enabled

Bit 7 CMDSENTIE: Command sent interrupt enable

Set and cleared by software to enable/disable interrupt caused by sending command.

0: Command sent interrupt disabled

1: Command sent interrupt enabled

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Bit 6 CMDRENDIE: Command response received interrupt enable

Set and cleared by software to enable/disable interrupt caused by receiving command response.

0: Command response received interrupt disabled

1: command Response Received interrupt enabled

Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable

Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.

0: Rx FIFO overrun error interrupt disabled

1: Rx FIFO overrun error interrupt enabled

Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable

Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error.

0: Tx FIFO underrun error interrupt disabled

1: Tx FIFO underrun error interrupt enabled

Bit 3 DTIMEOUTIE: Data timeout interrupt enable

Set and cleared by software to enable/disable interrupt caused by data timeout.

0: Data timeout interrupt disabled

1: Data timeout interrupt enabled

Bit 2 CTIMEOUTIE: Command timeout interrupt enable

Set and cleared by software to enable/disable interrupt caused by command timeout.

0: Command timeout interrupt disabled

1: Command timeout interrupt enabled

Bit 1 DCRCFAILIE: Data CRC fail interrupt enable

Set and cleared by software to enable/disable interrupt caused by data CRC failure.

0: Data CRC fail interrupt disabled

1: Data CRC fail interrupt enabled

Bit 0 CCRCFAILIE: Command CRC fail interrupt enable

Set and cleared by software to enable/disable interrupt caused by command CRC failure.

0: Command CRC fail interrupt disabled

1: Command CRC fail interrupt enabled

Address offset: 0x48

Reset value: 0x0000 0000

The SDIO_FIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The FIFO counter loads the value from the data length register (see

SDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register

(SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not wordaligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved r r r r r r r r r r r

FIFOCOUNT r r r r r r r r r r r r r

Bits 31:24 Reserved, must be kept at reset value

Bits 23:0 FIFOCOUNT: Remaining number of words to be written to or read from the FIFO.

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RM0368 Rev 5

RM0368 Secure digital input/output interface (SDIO)

Address offset: 0x80

Reset value: 0x0000 0000

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIF0Data rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 FIFOData: Receive and transmit FIFO data

The FIFO data occupies 32 entries of 32-bit words, from address:

SDIO base + 0x080 to SDIO base + 0xFC.

The following table summarizes the SDIO registers.

Table 125. SDIO register map

Offset Register

0x00 SDIO_POWER

0x04 SDIO_CLKCR

0x08 SDIO_ARG

0x0C SDIO_CMD

0x10 SDIO_RESPCMD

0x14 SDIO_RESP1

0x18

0x1C

SDIO_RESP2

SDIO_RESP3

0x20

0x24

0x28

SDIO_RESP4

SDIO_DTIMER

SDIO_DLEN

0x2C SDIO_DCTRL

0x30 SDIO_DCOUNT

Reserved

CMDARG

Reserved

CARDSTATUS1

CARDSTATUS2

CARDSTATUS3

CARDSTATUS4

DATATIME

DATALENGTH

DATACOUNT

RESPCMD

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Secure digital input/output interface (SDIO)

Table 125. SDIO register map (continued)

Offset Register

0x34 SDIO_STA

0x38 SDIO_ICR

0x3C SDIO_MASK

0x48

0x80

SDIO_FIFOCNT

SDIO_FIFO

Reserved

FIF0Data

FIFOCOUNT

RM0368

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RM0368

22

USB on-the-go full-speed (OTG_FS)

USB on-the-go full-speed (OTG_FS)

OTG

PFC

PHY

USB

UTMI

This section presents the architecture and the programming model of the OTG_FS controller.

The following acronyms are used throughout this section:

FS Full-speed

MAC

Low-speed

Media access controller

On-the-go

Packet FIFO controller

Physical layer

Universal serial bus

USB 2.0 transceiver macrocell interface (UTMI)

References are made to the following documents:

• USB On-The-Go Supplement, Revision 1.3

• Universal Serial Bus Revision 2.0 Specification

The OTG_FS is a dual-role device (DRD) controller that supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0

Specification . It can also be configured as a host-only or device-only controller, fully compliant with the USB 2.0 Specification. In host mode, the OTG_FS supports full-speed

(FS, 12 Mbits/s) and low-speed (LS, 1.5 Mbits/s) transfers whereas in device mode, it only supports full-speed (FS, 12 Mbits/s) transfers. The OTG_FS supports both HNP and SRP.

The only external device required is a charge pump for V

BUS

in host mode.

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USB on-the-go full-speed (OTG_FS) RM0368

22.2 OTG_FS main features

The main features can be divided into three categories: general, host-mode and devicemode features.

The OTG_FS interface general features are the following:

• It is USB-IF certified to the Universal Serial Bus Specification Rev 2.0

• It includes full support (PHY) for the optional On-The-Go (OTG) protocol detailed in the

On-The-Go Supplement Rev 1.3 specification

– Integrated support for A-B Device Identification (ID line)

– Integrated support for host Negotiation Protocol (HNP) and Session Request

Protocol (SRP)

– It allows host to turn V

BUS

off to conserve battery power in OTG applications

– It supports OTG monitoring of V

BUS

levels with internal comparators

– It supports dynamic host-peripheral switch of role

• It is software-configurable to operate as:

– SRP capable USB FS Peripheral (B-device)

– SRP capable USB FS/LS host (A-device)

– USB On-The-Go Full-Speed Dual Role device

• It supports FS SOF and LS Keep-alives with

– SOF pulse PAD connectivity (OTG_FS_SOF)

– SOF pulse internal connection to timer2 (TIM2)

– Configurable framing period

– Configurable end of frame interrupt

• It includes power saving features such as system stop during USB Suspend, switch-off of clock domains internal to the digital core, PHY and DFIFO power management

• It features a dedicated RAM of 1.25 Kbytes with advanced FIFO control:

– Configurable partitioning of RAM space into different FIFOs for flexible and efficient use of RAM

– Each FIFO can hold multiple packets

– Dynamic memory allocation

– Configurable FIFO sizes that are not powers of 2 to allow the use of contiguous memory locations

• It guarantees max USB bandwidth for up to one frame (1ms) without system intervention

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RM0368 USB on-the-go full-speed (OTG_FS)

The OTG_FS interface main features and requirements in host-mode are the following:

• External charge pump for V

BUS

voltage generation.

• Up to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer.

• Built-in hardware scheduler holding:

– Up to 8 interrupt plus isochronous transfer requests in the periodic hardware queue

– Up to 8 control plus bulk transfer requests in the non-periodic hardware queue

• Management of a shared RX FIFO, a periodic TX FIFO and a nonperiodic TX FIFO for efficient usage of the USB data RAM.

The OTG_FS interface main features in peripheral-mode are the following:

• 1 bidirectional control endpoint0

• 3 IN endpoints (EPs) configurable to support Bulk, Interrupt or Isochronous transfers

• 3 OUT endpoints configurable to support Bulk, Interrupt or Isochronous transfers

• Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB data RAM

• Management of up to 4 dedicated Tx-IN FIFOs (one for each active IN EP) to put less load on the application

• Support for the soft disconnect feature.

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USB on-the-go full-speed (OTG_FS)

22.3 OTG_FS functional description

Figure 242. OTG full-speed block diagram

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OTG_FS_DP

OTG_FS_DM

OTG_FS_ID

OTG_FS_VBUS

OTG_FS_SOF

Table 126. OTG_FS input/output pins

Signal type Description

Digital input/output USB OTG D+ line

Digital input/output USB OTG D- line

Digital input USB OTG ID

Analog input

Digital output

USB OTG VBUS

USB OTG Start Of Frame (visibility)

672/847

The USB OTG FS receives the 48 MHz ±0.25% clock from the reset and clock controller

(RCC), via an external quartz. The USB clock is used for driving the 48 MHz domain at fullspeed (12 Mbit/s) and must be enabled prior to configuring the OTG FS core.

The CPU reads and writes from/to the OTG FS core registers through the AHB peripheral bus. It is informed of USB events through the single USB OTG interrupt line described in

Section 22.15: OTG_FS interrupts

RM0368 Rev 5

RM0368 USB on-the-go full-speed (OTG_FS)

The CPU submits data over the USB by writing 32-bit words to dedicated OTG_FS locations

(push registers). The data are then automatically stored into Tx-data FIFOs configured within the USB data RAM. There is one Tx-FIFO push register for each in-endpoint

(peripheral mode) or out-channel (host mode).

The CPU receives the data from the USB by reading 32-bit words from dedicated OTG_FS addresses (pop registers). The data are then automatically retrieved from a shared Rx-FIFO configured within the 1.25 KB USB data RAM. There is one Rx-FIFO pop register for each out-endpoint or in-channel.

The USB protocol layer is driven by the serial interface engine (SIE) and serialized over the

USB by the full-/low-speed transceiver module within the on-chip physical layer (PHY).

22.3.3 Full-speed OTG PHY

The embedded full-speed OTG PHY is controlled by the OTG FS core and conveys USB control & data signals through the full-speed subset of the UTMI+ Bus (UTMIFS). It provides the physical support to USB connectivity.

The full-speed OTG PHY includes the following components:

• FS/LS transceiver module used by both host and device. It directly drives transmission and reception on the single-ended USB lines.

• integrated ID pull-up resistor used to sample the ID line for A/B device identification.

• DP/DM integrated pull-up and pull-down resistors controlled by the OTG_FS core depending on the current role of the device. As a peripheral, it enables the DP pull-up resistor to signal full-speed peripheral connections as soon as V

BUS

is sensed to be at a valid level (B-session valid). In host mode, pull-down resistors are enabled on both

DP/DM. Pull-up and pull-down resistors are dynamically switched when the device’s role is changed via the host negotiation protocol (HNP).

• Pull-up/pull-down resistor ECN circuit. The DP pull-up consists of 2 resistors controlled separately from the OTG_FS as per the resistor Engineering Change Notice applied to

USB Rev2.0. The dynamic trimming of the DP pull-up strength allows for better noise rejection and Tx/Rx signal quality.

• V

BUS

sensing comparators with hysteresis used to detect V

BUS

Valid, A-B Session

Valid and session-end voltage thresholds. They are used to drive the session request protocol (SRP), detect valid startup and end-of-session conditions, and constantly monitor the V

BUS

supply during USB operations.

• V

BUS

pulsing method circuit used to charge/discharge V

BUS

through resistors during the SRP (weak drive).

Caution: To guarantee a correct operation for the USB OTG FS peripheral, the AHB frequency should be higher than 14.2 MHz.

RM0368 Rev 5

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USB on-the-go full-speed (OTG_FS) RM0368

22.4 OTG dual role device (DRD)

Figure 243. OTG A-B device connection

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BUS

powered device. A basic power

22.4.1 ID line detection

The host or peripheral (the default) role is assumed depending on the ID input pin

(OTG_FS_ID). The ID line status is determined on plugging in the USB, depending on which side of the USB cable is connected to the micro-AB receptacle.

• If the B-side of the USB cable is connected with a floating ID wire, the integrated pullup resistor detects a high ID level and the default Peripheral role is confirmed. In this configuration the OTG_FS complies with the standard FSM described by section 6.8.2:

On-The-Go B-device of the On-The-Go Specification Rev1.3 supplement to the

USB2.0.

• If the A-side of the USB cable is connected with a grounded ID, the OTG_FS issues an

ID line status change interrupt (CIDSCHG bit in OTG_FS_GINTSTS) for host software initialization, and automatically switches to the host role. In this configuration the

OTG_FS complies with the standard FSM described by section 6.8.1: On-The-Go Adevice of the On-The-Go Specification Rev1.3 supplement to the USB2.0.

22.4.2 HNP dual role device

The HNP capable bit in the Global USB configuration register (HNPCAP bit in OTG_FS_

GUSBCFG) enables the OTG_FS core to dynamically change its role from A-host to Aperipheral and vice-versa, or from B-Peripheral to B-host and vice-versa according to the host negotiation protocol (HNP). The current device status can be read by the combined values of the Connector ID Status bit in the Global OTG control and status register (CIDSTS bit in OTG_FS_GOTGCTL) and the current mode of operation bit in the global interrupt and status register (CMOD bit in OTG_FS_GINTSTS).

The HNP program model is described in detail in Section 22.17

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RM0368 USB on-the-go full-speed (OTG_FS)

22.4.3 SRP dual role device

The SRP capable bit in the global USB configuration register (SRPCAP bit in

OTG_FS_GUSBCFG) enables the OTG_FS core to switch off the generation of V

BUS

for the A-device to save power. Note that the A-device is always in charge of driving V

BUS regardless of the host or peripheral role of the OTG_FS.

the SRP A/B-device program model is described in detail in Section 22.17

Note:

This section gives the functional description of the OTG_FS in the USB peripheral mode.

The OTG_FS works as an USB peripheral in the following circumstances:

• OTG B-Peripheral

– OTG B-device default state if B-side of USB cable is plugged in

• OTG A-Peripheral

– OTG A-device state after the HNP switches the OTG_FS to its peripheral role

• B-device

– If the ID line is present, functional and connected to the B-side of the USB cable, and the HNP-capable bit in the Global USB Configuration register (HNPCAP bit in

OTG_FS_GUSBCFG) is cleared (see On-The-Go Rev1.3 par. 6.8.3).

•

Peripheral only (see Figure 244 )

–

The force device mode bit in the Global USB configuration register (FDMOD in

OTG_FS_GUSBCFG) is set to 1, forcing the OTG_FS core to work as a USB peripheral-only (see On-The-Go Rev1.3 par. 6.8.3). In this case, the ID line is ignored even if present on the USB connector.

To build a bus-powered device implementation in case of the B-device or peripheral-only configuration, an external regulator has to be added that generates the V

chip-supply from V

BUS

The V

BUS

pin can be freed by disabling the V

BUS

sensing option. This is done by setting the

NOVBUSSENS bit in the OTG_FS_GCCFG register. In this case the V

BUS internally to be always at V

BUS

valid level (5 V).

is considered

RM0368 Rev 5

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USB on-the-go full-speed (OTG_FS)

Figure 244. USB peripheral-only connection

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The SRP capable bit in the Global USB configuration register (SRPCAP bit in

OTG_FS_GUSBCFG) enables the OTG_FS to support the session request protocol (SRP).

In this way, it allows the remote A-device to save power by switching off V

BUS session is suspended.

while the USB

The SRP peripheral mode program model is described in detail in the

B-device session request protocol

section.

Powered state

The V

BUS

input detects the B-Session valid voltage by which the USB peripheral is allowed to enter the powered state (see USB2.0 par9.1). The OTG_FS then automatically connects the DP pull-up resistor to signal full-speed device connection to the host and generates the session request interrupt (SRQINT bit in OTG_FS_GINTSTS) to notify the powered state.

The V

BUS

input also ensures that valid V

BUS operations. If a drop in V

BUS

levels are supplied by the host during USB

below B-session valid happens to be detected (for instance because of a power disturbance or if the host port has been switched off), the OTG_FS automatically disconnects and the session end detected (SEDET bit in

OTG_FS_GOTGINT) interrupt is generated to notify that the OTG_FS has exited the powered state.

In the powered state, the OTG_FS expects to receive some reset signaling from the host.

No other USB operation is possible. When a reset signaling is received the reset detected interrupt (USBRST in OTG_FS_GINTSTS) is generated. When the reset signaling is complete, the enumeration done interrupt (ENUMDNE bit in OTG_FS_GINTSTS) is generated and the OTG_FS enters the Default state.

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RM0368 USB on-the-go full-speed (OTG_FS)

Soft disconnect

The powered state can be exited by software with the soft disconnect feature. The DP pullup resistor is removed by setting the soft disconnect bit in the device control register (SDIS bit in OTG_FS_DCTL), causing a device disconnect detection interrupt on the host side even though the USB cable was not really removed from the host port.

Default state

In the Default state the OTG_FS expects to receive a SET_ADDRESS command from the host. No other USB operation is possible. When a valid SET_ADDRESS command is decoded on the USB, the application writes the corresponding number into the device address field in the device configuration register (DAD bit in OTG_FS_DCFG). The

OTG_FS then enters the address state and is ready to answer host transactions at the configured USB address.

Suspended state

The OTG_FS peripheral constantly monitors the USB activity. After counting 3 ms of USB idleness, the early suspend interrupt (ESUSP bit in OTG_FS_GINTSTS) is issued, and confirmed 3 ms later, if appropriate, by the suspend interrupt (USBSUSP bit in

OTG_FS_GINTSTS). The device suspend bit is then automatically set in the device status register (SUSPSTS bit in OTG_FS_DSTS) and the OTG_FS enters the suspended state.

The suspended state may optionally be exited by the device itself. In this case the application sets the remote wakeup signaling bit in the device control register (RWUSIG bit in OTG_FS_DCTL) and clears it after 1 to 15 ms.

When a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in

OTG_FS_GINTSTS) is generated and the device suspend bit is automatically cleared.

The OTG_FS core instantiates the following USB endpoints:

• Control endpoint 0:

– Bidirectional and handles control messages only

– Separate set of registers to handle in and out transactions

– Proper control (OTG_FS_DIEPCTL0/OTG_FS_DOEPCTL0), transfer configuration (OTG_FS_DIEPTSIZ0/OTG_FS_DIEPTSIZ0), and status-interrupt

(OTG_FS_DIEPINTx/)OTG_FS_DOEPINT0) registers. The available set of bits inside the control and transfer size registers slightly differs from that of other endpoints

• 3 IN endpoints

– Each of them can be configured to support the isochronous, bulk or interrupt transfer type

– Each of them has proper control (OTG_FS_DIEPCTL x ), transfer configuration

(OTG_FS_DIEPTSIZ x ), and status-interrupt (OTG_FS_DIEPINT x ) registers

– The Device IN endpoints common interrupt mask register (OTG_FS_DIEPMSK) is available to enable/disable a single kind of endpoint interrupt source on all of the

IN endpoints (EP0 included)

– Support for incomplete isochronous IN transfer interrupt (IISOIXFR bit in

OTG_FS_GINTSTS), asserted when there is at least one isochronous IN endpoint

RM0368 Rev 5

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807

USB on-the-go full-speed (OTG_FS) RM0368 on which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt

(OTG_FS_GINTSTS/EOPF).

• 3 OUT endpoints

– Each of them can be configured to support the isochronous, bulk or interrupt transfer type

– Each of them has a proper control (OTG_FS_DOEPCTL x ), transfer configuration

(OTG_FS_DOEPTSIZ x ) and status-interrupt (OTG_FS_DOEPINT x ) register

– Device Out endpoints common interrupt mask register (OTG_FS_DOEPMSK) is available to enable/disable a single kind of endpoint interrupt source on all of the

OUT endpoints (EP0 included)

– Support for incomplete isochronous OUT transfer interrupt (INCOMPISOOUT bit in OTG_FS_GINTSTS), asserted when there is at least one isochronous OUT endpoint on which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt

(OTG_FS_GINTSTS/EOPF).

Endpoint control

• The following endpoint controls are available to the application through the device endpointx IN/OUT control register (DIEPCTL x /DOEPCTL x ):

– Endpoint enable/disable

– Endpoint activate in current configuration

– Program USB transfer type (isochronous, bulk, interrupt)

– Program supported packet size

– Program Tx-FIFO number associated with the IN endpoint

– Program the expected or transmitted data0/data1 PID (bulk/interrupt only)

– Program the even/odd frame during which the transaction is received or transmitted (isochronous only)

– Optionally program the NAK bit to always negative-acknowledge the host regardless of the FIFO status

– Optionally program the STALL bit to always stall host tokens to that endpoint

– Optionally program the SNOOP mode for OUT endpoint not to check the CRC field of received data

Endpoint transfer

The device endpointx transfer size registers (DIEPTSIZ x /DOEPTSIZ x ) allow the application to program the transfer size parameters and read the transfer status. Programming must be done before setting the endpoint enable bit in the endpoint control register. Once the endpoint is enabled, these fields are read-only as the OTG FS core updates them with the current transfer status.

The following transfer parameters can be programmed:

• Transfer size in bytes

• Number of packets that constitute the overall transfer size

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RM0368 USB on-the-go full-speed (OTG_FS)

Endpoint status/interrupt

The device endpointx interrupt registers (DIEPINT x /DOPEPINT x) indicate the status of an endpoint with respect to USB- and AHB-related events. The application must read these registers when the OUT endpoint interrupt bit or the IN endpoint interrupt bit in the core interrupt register (OEPINT bit in OTG_FS_GINTSTS or IEPINT bit in OTG_FS_GINTSTS, respectively) is set. Before the application can read these registers, it must first read the device all endpoints interrupt (OTG_FS_DAINT) register to get the exact endpoint number for the device endpointx interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers

The peripheral core provides the following status checks and interrupt generation:

• Transfer completed interrupt, indicating that data transfer was completed on both the application (AHB) and USB sides

• Setup stage has been done (control-out only)

• Associated transmit FIFO is half or completely empty (in endpoints)

• NAK acknowledge has been transmitted to the host (isochronous-in only)

• IN token received when Tx-FIFO was empty (bulk-in/interrupt-in only)

• Out token received when endpoint was not yet enabled

• Babble error condition has been detected

• Endpoint disable by application is effective

• Endpoint NAK by application is effective (isochronous-in only)

• More than 3 back-to-back setup packets were received (control-out only)

• Timeout condition detected (control-in only)

• Isochronous out packet has been dropped, without generating an interrupt

Note:

This section gives the functional description of the OTG_FS in the USB host mode. The

OTG_FS works as a USB host in the following circumstances:

• OTG A-host

– OTG A-device default state when the A-side of the USB cable is plugged in

• OTG B-host

– OTG B-device after HNP switching to the host role

• A-device

– If the ID line is present, functional and connected to the A-side of the USB cable, and the HNP-capable bit is cleared in the Global USB Configuration register

(HNPCAP bit in OTG_FS_GUSBCFG). Integrated pull-down resistors are automatically set on the DP/DM lines.

•

Host only (see figure Figure 245

–

The force host mode bit in the global USB configuration register (FHMOD bit in

OTG_FS_GUSBCFG) forces the OTG_FS core to work as a USB host-only. In this case, the ID line is ignored even if present on the USB connector. Integrated pulldown resistors are automatically set on the DP/DM lines.

On-chip 5 V V

BUS

generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch must be added externally to drive

RM0368 Rev 5

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807

USB on-the-go full-speed (OTG_FS) RM0368 the 5 V V

BUS

line. The external charge pump can be driven by any GPIO output. This is required for the OTG A-host, A-device and host-only configurations.

The V

BUS

input ensures that valid V

BUS

levels are supplied by the charge pump during USB operations while the charge pump overcurrent output can be input to any GPIO pin configured to generate port interrupts. The overcurrent ISR must promptly disable the V

BUS generation.

Figure 245. USB host-only connection

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2. V

range is between 2 V and 3.6 V.

SRP support is available through the SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_FS_GUSBCFG). With the SRP feature enabled, the host can save power by switching off the V

BUS

power while the USB session is suspended.

The SRP host mode program model is described in detail in the

A-device session request protocol

section.

680/847

Host port power

On-chip 5 V V

BUS

generation is not supported. For this reason, a charge pump or, if 5 V are available on the application board, a basic power switch, must be added externally to drive the 5 V V

BUS

line. The external charge pump can be driven by any GPIO output. When the application decides to power on V

BUS

using the chosen GPIO, it must also set the port power bit in the host port control and status register (PPWR bit in OTG_FS_HPRT).

V

BUS

valid

When HNP or SRP is enabled the VBUS sensing pin (PA9) pin should be connected to

BUS

. The V

BUS

input ensures that valid V

BUS

levels are supplied by the charge pump during USB operations. Any unforeseen V

BUS

voltage drop below the V

BUS

valid threshold

(4.25 V) leads to an OTG interrupt triggered by the session end detected bit (SEDET bit in

RM0368 Rev 5

RM0368 USB on-the-go full-speed (OTG_FS)

OTG_FS_GOTGINT). The application is then required to remove the V

BUS the port power bit.

power and clear

When HNP and SRP are both disabled, the VBUS sensing pin (PA9) should not be connected to V

BUS

. This pin can be can be used as GPIO.

The charge pump overcurrent flag can also be used to prevent electrical damage. Connect the overcurrent flag output from the charge pump to any GPIO input and configure it to generate a port interrupt on the active level. The overcurrent ISR must promptly disable the

BUS

generation and clear the port power bit.

Host detection of a peripheral connection

If SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any time, the OTG_FS will not detect any bus connection . When V

BUS

is at a valid level and a remote B-device is attached, the OTG_FS core issues a host port interrupt triggered by the device connected bit in the host port control and status register (PCDET bit in

OTG_FS_HPRT).

When HNP and SRP are both disabled, USB peripherals or B-device are detected as soon as they are connected. The OTG_FS core issues a host port interrupt triggered by the device connected bit in the host port control and status (PCDET bit in OTG_FS_HPRT).

Host detection of peripheral a disconnection

The peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit in OTG_FS_GINTSTS).

Host enumeration

After detecting a peripheral connection the host must start the enumeration process by sending USB reset and configuration commands to the new peripheral.

Before starting to drive a USB reset, the application waits for the OTG interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), which indicates that the bus is stable again after the electrical debounce caused by the attachment of a pull-up resistor on

DP (FS) or DM (LS).

The application drives a USB reset signaling (single-ended zero) over the USB by keeping the port reset bit set in the host port control and status register (PRST bit in

OTG_FS_HPRT) for a minimum of 10 ms and a maximum of 20 ms. The application takes care of the timing count and then of clearing the port reset bit.

Once the USB reset sequence has completed, the host port interrupt is triggered by the port enable/disable change bit (PENCHNG bit in OTG_FS_HPRT). This informs the application that the speed of the enumerated peripheral can be read from the port speed field in the host port control and status register (PSPD bit in OTG_FS_HPRT) and that the host is starting to drive SOFs (FS) or Keep alives (LS). The host is now ready to complete the peripheral enumeration by sending peripheral configuration commands.

Host suspend

The application decides to suspend the USB activity by setting the port suspend bit in the host port control and status register (PSUSP bit in OTG_FS_HPRT). The OTG_FS core stops sending SOFs and enters the suspended state.

The suspended state can be optionally exited on the remote device’s initiative (remote wakeup). In this case the remote wakeup interrupt (WKUPINT bit in OTG_FS_GINTSTS) is

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USB on-the-go full-speed (OTG_FS) RM0368 generated upon detection of a remote wakeup signaling, the port resume bit in the host port control and status register (PRES bit in OTG_FS_HPRT) self-sets, and resume signaling is automatically driven over the USB. The application must time the resume window and then clear the port resume bit to exit the suspended state and restart the SOF.

If the suspended state is exited on the host initiative, the application must set the port resume bit to start resume signaling on the host port, time the resume window and finally clear the port resume bit.

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The OTG_FS core instantiates 8 host channels. Each host channel supports an USB host transfer (USB pipe). The host is not able to support more than 8 transfer requests at the same time. If more than 8 transfer requests are pending from the application, the host controller driver (HCD) must re-allocate channels when they become available from previous duty, that is, after receiving the transfer completed and channel halted interrupts.

Each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. Each host channel makes us of proper control (HCCHAR x ), transfer configuration (HCTSIZ x ) and status/interrupt (HCINT x ) registers with associated mask

(HCINTMSK x ) registers.

Host channel control

• The following host channel controls are available to the application through the host channelx characteristics register (HCCHAR x ):

– Channel enable/disable

– Program the FS/LS speed of target USB peripheral

– Program the address of target USB peripheral

– Program the endpoint number of target USB peripheral

– Program the transfer IN/OUT direction

– Program the USB transfer type (control, bulk, interrupt, isochronous)

– Program the maximum packet size (MPS)

– Program the periodic transfer to be executed during odd/even frames

Host channel transfer

The host channel transfer size registers (HCTSIZ x ) allow the application to program the transfer size parameters, and read the transfer status. Programming must be done before setting the channel enable bit in the host channel characteristics register. Once the endpoint is enabled the packet count field is read-only as the OTG FS core updates it according to the current transfer status.

• The following transfer parameters can be programmed:

– transfer size in bytes

– number of packets making up the overall transfer size

– initial data PID

Host channel status/interrupt

The host channelx interrupt register (HCINT x ) indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read these register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_FS_GINTSTS) is

RM0368 Rev 5

RM0368 USB on-the-go full-speed (OTG_FS) set. Before the application can read these registers, it must first read the host all channels interrupt (HCAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt source of each channel are also available in the OTG_FS_HCINTMSK-x register.

• The host core provides the following status checks and interrupt generation:

– Transfer completed interrupt, indicating that the data transfer is complete on both the application (AHB) and USB sides

– Channel has stopped due to transfer completed, USB transaction error or disable command from the application

– Associated transmit FIFO is half or completely empty (IN endpoints)

– ACK response received

– NAK response received

– STALL response received

– USB transaction error due to CRC failure, timeout, bit stuff error, false EOP

– Babble error

– fraMe overrun

– dAta toggle error

The host core features a built-in hardware scheduler which is able to autonomously re-order and manage the USB transaction requests posted by the application. At the beginning of each frame the host executes the periodic (isochronous and interrupt) transactions first, followed by the nonperiodic (control and bulk) transactions to achieve the higher level of priority granted to the isochronous and interrupt transfer types by the USB specification.

The host processes the USB transactions through request queues (one for periodic and one for nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a pending transaction request from the application, and holds the IN or OUT channel number along with other information to perform a transaction on the USB. The order in which the requests are written to the queue determines the sequence of the transactions on the USB interface.

At the beginning of each frame, the host processes the periodic request queue first, followed by the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt

(IPXFR bit in OTG_FS_GINTSTS) if an isochronous or interrupt transaction scheduled for the current frame is still pending at the end of the current frame. The OTG HS core is fully responsible for the management of the periodic and nonperiodic request queues.The periodic transmit FIFO and queue status register (HPTXSTS) and nonperiodic transmit

FIFO and queue status register (HNPTXSTS) are read-only registers which can be used by the application to read the status of each request queue. They contain:

• The number of free entries currently available in the periodic (nonperiodic) request queue (8 max)

• Free space currently available in the periodic (nonperiodic) Tx-FIFO (out-transactions)

• IN/OUT token, host channel number and other status information.

As request queues can hold a maximum of 8 entries each, the application can push to schedule host transactions in advance with respect to the moment they physically reach the

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SB for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic transactions.

To post a transaction request to the host scheduler (queue) the application must check that there is at least 1 entry available in the periodic (nonperiodic) request queue by reading the

PTXQSAV bits in the OTG_FS_HNPTXSTS register or NPTQXSAV bits in the

OTG_FS_HNPTXSTS register.

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Figure 246. SOF connectivity

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The OTG FS core provides means to monitor, track and configure SOF framing in the host and peripheral, as well as an SOF pulse output connectivity feature.

Such utilities are especially useful for adaptive audio clock generation techniques, where the audio peripheral needs to synchronize to the isochronous stream provided by the PC, or the host needs to trim its framing rate according to the requirements of the audio peripheral.

In host mode the number of PHY clocks occurring between the generation of two consecutive SOF (FS) or Keep-alive (LS) tokens is programmable in the host frame interval register (HFIR), thus providing application control over the SOF framing period. An interrupt is generated at any start of frame (SOF bit in OTH_FS_GINTSTS). The current frame number and the time remaining until the next SOF are tracked in the host frame number register (HFNUM).

An SOF pulse signal, generated at any SOF starting token and with a width of 20 HCLK cycles, can be made available externally on the OTG_FS_SOF pin using the SOFOUTEN bit in the global control and configuration register. The SOF pulse is also internally connected to the input trigger of timer 2 (TIM2), so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled register.

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In device mode, the start of frame interrupt is generated each time an SOF token is received on the USB (SOF bit in OTH_FS_GINTSTS). The corresponding frame number can be read from the device status register (FNSOF bit in OTG_FS_DSTS). An SOF pulse signal with a width of 20 HCLK cycles is also generated and can be made available externally on the

OTG_FS_SOF pin by using the SOF output enable bit in the global control and configuration register (SOFOUTEN bit in OTG_FS_GCCFG). The SOF pulse signal is also internally connected to the TIM2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled .

The end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when

80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuration register (PFIVL bit in OTG_FS_DCFG). This feature can be used to determine if all of the isochronous traffic for that frame is complete.

22.8 OTG low-power modes

Table 127

below defines the STM32 low power modes and their compatibility with the OTG.

Mode

Table 127. Compatibility of STM32 low power modes with the OTG

Description USB compatibility

Run

Sleep

Stop

Standby

MCU fully active

USB suspend exit causes the device to exit Sleep mode.

Peripheral registers content is kept.

Required when USB not in suspend state.

Available while USB is in suspend state.

USB suspend exit causes the device to exit Stop mode.

Peripheral registers content is kept

(1)

Powered-down. The peripheral must be reinitialized after exiting Standby mode.

Available while USB is in suspend state.

Not compatible with USB applications.

1. Within Stop mode there are different possible settings. Some restrictions may also exist, please refer to

Section 5: Power controller (PWR) to understand which (if any) restrictions apply when using OTG.

The power consumption of the OTG PHY is controlled by three bits in the general core configuration register:

• PHY power down (GCCFG/PWRDWN)

It switches on/off the full-speed transceiver module of the PHY. It must be preliminarily set to allow any USB operation.

• A-V

BUS

sensing enable (GCCFG/VBUSASEN)

It switches on/off the V

BUS

comparators associated with A-device operations. It must be set when in A-device (USB host) mode and during HNP.

• B-V

BUS

sensing enable (GCCFG/VBUSASEN)

It switches on/off the V

BUS

comparators associated with B-device operations. It must be set when in B-device (USB peripheral) mode and during HNP.

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Power reduction techniques are available while in the USB suspended state, when the USB session is not yet valid or the device is disconnected.

• Stop PHY clock (STPPCLK bit in OTG_FS_PCGCCTL)

When setting the stop PHY clock bit in the clock gating control register, most of the

48 MHz clock domain internal to the OTG full-speed core is switched off by clock gating. The dynamic power consumption due to the USB clock switching activity is cut even if the 48 MHz clock input is kept running by the application

Most of the transceiver is also disabled, and only the part in charge of detecting the asynchronous resume or remote wakeup event is kept alive.

• Gate HCLK (GATEHCLK bit in OTG_FS_PCGCCTL)

When setting the Gate HCLK bit in the clock gating control register, most of the system clock domain internal to the OTG_FS core is switched off by clock gating. Only the register read and write interface is kept alive. The dynamic power consumption due to the USB clock switching activity is cut even if the system clock is kept running by the application for other purposes.

• USB system stop

When the OTG_FS is in the USB suspended state, the application may decide to drastically reduce the overall power consumption by a complete shut down of all the clock sources in the system. USB System Stop is activated by first setting the Stop

PHY clock bit and then configuring the system deep sleep mode in the power control system module (PWR).

The OTG_FS core automatically reactivates both system and USB clocks by asynchronous detection of remote wakeup (as an host) or resume (as a device) signaling on the USB.

To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS core.

The USB core embeds a dynamic trimming capability of SOF framing period in host mode allowing to synchronize an external device with the SOF frames.

When the OTG_FS_HFIR register is changed within a current SOF frame, the SOF period

correction is applied in the next frame as described in Figure 247 .

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RM0368 USB on-the-go full-speed (OTG_FS)

Figure 247. Updating OTG_FS_HFIR dynamically

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22.10 USB data FIFOs

The USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control mechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space into Tx-FIFOs into which the application pushes the data to be temporarily stored before the

USB transmission, and into a single Rx FIFO where the data received from the USB are temporarily stored before retrieval (popped) by the application. The number of instructed

FIFOs and how these are organized inside the RAM depends on the device’s role. In peripheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any FIFO size is software configured to better meet the application requirements.

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Figure 248. Device-mode FIFO address mapping and AHB FIFO access mapping

Single data

FIFO

IN endpoint Tx FIFO #n

DFIFO push access from AHB

MAC pop

Dedicated Tx

FIFO #n control

(optional)

Tx FIFO #n packet

DIEPTXF2[31:16]

DIEPTXFx[15:0]

DIEPTXF2[15:0]

IN endpoint Tx FIFO #1

DFIFO push access from AHB

MAC pop

Dedicated Tx

FIFO #1 control

(optional)

Tx FIFO #1 packet

DIEPTXF1[31:16]

DIEPTXF1[15:0]

IN endpoint Tx FIFO #0

DFIFO push access from AHB

MAC pop

Dedicated Tx

FIFO #0 control

(optional)

Tx FIFO #0 packet GNPTXFSIZ[31:16]

GNPTXFSIZ[15:0]

Any OUT endpoint DFIFO pop access from AHB

MAC push

Rx FIFO control Rx packets

GRXFSIZ[31:16]

A1 = 0

(Rx start address fixed to 0) ai15611

The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT endpoints. Received packets are stacked back-to-back until free space is available in the

Rx-FIFO. The status of the received packet (which contains the OUT endpoint destination number, the byte count, the data PID and the validity of the received data) is also stored by the core on top of the data payload. When no more space is available, host transactions are

NACKed and an interrupt is received on the addressed endpoint. The size of the receive

FIFO is configured in the receive FIFO Size register (GRXFSIZ).

The single receive FIFO architecture makes it more efficient for the USB peripheral to fill in the receive RAM buffer:

• All OUT endpoints share the same RAM buffer (shared FIFO)

• The OTG FS core can fill in the receive FIFO up to the limit for any host sequence of

OUT tokens

The application keeps receiving the Rx-FIFO non-empty interrupt (RXFLVL bit in

OTG_FS_GINTSTS) as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register (GRXSTSP) and finally pops data off the receive FIFO by reading from the endpoint-related pop address.

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RM0368 USB on-the-go full-speed (OTG_FS)

22.11.2 Peripheral Tx FIFOs

The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the non periodic transmit FIFO size register (OTG_FS_TX0FSIZ) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (DIEPTXFx) for IN endpoint-x.

22.12 Host FIFO architecture

Figure 249. Host-mode FIFO address mapping and AHB FIFO access mapping

Single data

FIFO

Any periodic channel

DFIFO push access from AHB

MAC pop

Periodic Tx

FIFO control

(optional)

Periodic Tx packets HPTXFSIZ[31:16]

HPTXFSIZ[15:0]

Any non-periodic channel DFIFO push access from AHB

MAC pop

Non-periodic

Tx FIFO control

Periodic Tx packets

NPTXFSIZ[31:16]

NPTXFSIZ[15:0]

Rx packets RXFSIZ[31:16]

Any channel DFIFO pop access from AHB Rx FIFO control

MAC push

Rx start address fixed to 0

A1 = 0 ai15610

22.12.1 Host Rx FIFO

The host uses one receiver FIFO for all periodic and nonperiodic transactions. The FIFO is used as a receive buffer to hold the received data (payload of the received packet) from the

USB until it is transferred to the system memory. Packets received from any remote IN endpoint are stacked back-to-back until free space is available. The status of each received packet with the host channel destination, byte count, data PID and validity of the received data are also stored into the FIFO. The size of the receive FIFO is configured in the receive

FIFO size register (GRXFSIZ).

The single receive FIFO architecture makes it highly efficient for the USB host to fill in the receive data buffer:

• All IN configured host channels share the same RAM buffer (shared FIFO)

• The OTG FS core can fill in the receive FIFO up to the limit for any sequence of IN tokens driven by the host software

The application receives the Rx FIFO not-empty interrupt as long as there is at least one packet available for download. It reads the packet information from the receive status read and pop register and finally pops the data off the receive FIFO.

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The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB. The size of the periodic (nonperiodic) Tx FIFO is configured in the host periodic (nonperiodic) transmit FIFO size (HPTXFSIZ/HNPTXFSIZ) register.

The two Tx FIFO implementation derives from the higher priority granted to the periodic type of traffic over the USB frame. At the beginning of each frame, the built-in host scheduler processes the periodic request queue first, followed by the nonperiodic request queue.

The two transmit FIFO architecture provides the USB host with separate optimization for periodic and nonperiodic transmit data buffer management:

• All host channels configured to support periodic (nonperiodic) transactions in the OUT direction share the same RAM buffer (shared FIFOs)

• The OTG FS core can fill in the periodic (nonperiodic) transmit FIFO up to the limit for any sequence of OUT tokens driven by the host software

The OTG_FS core issues the periodic Tx FIFO empty interrupt (PTXFE bit in

OTG_FS_GINTSTS) as long as the periodic Tx-FIFO is half or completely empty, depending on the value of the periodic Tx-FIFO empty level bit in the AHB configuration register (PTXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission data in advance as long as free space is available in both the periodic Tx FIFO and the periodic request queue. The host periodic transmit FIFO and queue status register

(HPTXSTS) can be read to know how much space is available in both.

OTG_FS core issues the non periodic Tx FIFO empty interrupt (NPTXFE bit in

OTG_FS_GINTSTS) as long as the nonperiodic Tx FIFO is half or completely empty depending on the non periodic Tx FIFO empty level bit in the AHB configuration register

(TXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission data as long as free space is available in both the nonperiodic Tx FIFO and nonperiodic request queue. The host nonperiodic transmit FIFO and queue status register (HNPTXSTS) can be read to know how much space is available in both.

22.13 FIFO RAM allocation

Receive FIFO RAM allocation: the application should allocate RAM for SETUP Packets:

10 locations must be reserved in the receive FIFO to receive SETUP packets on control endpoint. The core does not use these locations, which are reserved for SETUP packets, to write any other data. One location is to be allocated for Global OUT NAK. Status information is written to the FIFO along with each received packet. Therefore, a minimum space of

(Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous endpoints are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the CPU, the USB can receive the subsequent packet.

Along with the last packet for each endpoint, transfer complete status information is also pushed to the FIFO. Typically, one location for each OUT endpoint is recommended.

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USB on-the-go full-speed (OTG_FS)

Transmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint

Transmit FIFO is the maximum packet size for that particular IN endpoint.

More space allocated in the transmit IN Endpoint FIFO results in better performance on the

USB.

Note:

Receive FIFO RAM allocation

Status information is written to the FIFO along with each received packet. Therefore, a minimum space of (Largest Packet Size / 4) + 1 must be allocated to receive packets. If multiple isochronous channels are enabled, then at least two (Largest Packet Size / 4) + 1 spaces must be allocated to receive back-to-back packets. Typically, two (Largest Packet

Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the CPU, the USB can receive the subsequent packet.

Along with the last packet in the host channel, transfer complete status information is also pushed to the FIFO. So one location must be allocated for this.

Transmit FIFO RAM allocation

The minimum amount of RAM required for the host Non-periodic Transmit FIFO is the largest maximum packet size among all supported non-periodic OUT channels.

Typically, two Largest Packet Sizes worth of space is recommended, so that when the current packet is under transfer to the USB, the CPU can get the next packet.

The minimum amount of RAM required for host periodic Transmit FIFO is the largest maximum packet size out of all the supported periodic OUT channels. If there is at least one

Isochronous OUT endpoint, then the space must be at least two times the maximum packet size of that channel.

More space allocated in the Transmit Non-periodic FIFO results in better performance on the USB.

Best USB and system performance is achieved owing to the large RAM buffers, the highly configurable FIFO sizes, the quick 32-bit FIFO access through AHB push/pop registers and, especially, the advanced FIFO control mechanism. Indeed, this mechanism allows the

OTG_FS to fill in the available RAM space at best regardless of the current USB sequence.

With these features:

• The application gains good margins to calibrate its intervention in order to optimize the

CPU bandwidth usage:

– It can accumulate large amounts of transmission data in advance compared to when they are effectively sent over the USB

– It benefits of a large time margin to download data from the single receive FIFO

• The USB Core is able to maintain its full operating rate, that is to provide maximum fullspeed bandwidth with a great margin of autonomy versus application intervention:

– It has a large reserve of transmission data at its disposal to autonomously manage the sending of data over the USB

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– It has a lot of empty space available in the receive buffer to autonomously fill it in with the data coming from the USB

As the OTG_FS core is able to fill in the 1.25 Kbyte RAM buffer very efficiently, and as

1.25 Kbyte of transmit/receive data is more than enough to cover a full speed frame, the

USB system is able to withstand the maximum full-speed data rate for up to one USB frame

(1 ms) without any CPU intervention.

When the OTG_FS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the

OTG_FS_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset.

Figure 250 shows the interrupt hierarchy.

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RM0368 Rev 5

RM0368

+&,17 +35

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USB on-the-go full-speed (OTG_FS)

Figure 250. Interrupt hierarchy

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1. OTG_FS_WKUP become active (high state) when resume condition occurs during L1 SLEEP or L2 SUSPEND states.

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22.16 OTG_FS control and status registers

By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_FS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed by words (32 bits).

CSRs are classified as follows:

• Core global registers

• Host-mode registers

• Host global registers

• Host port CSRs

• Host channel-specific registers

• Device-mode registers

• Device global registers

• Device endpoint-specific registers

• Power and clock-gating registers

• Data FIFO (DFIFO) access registers

Only the Core global, Power and clock-gating, Data FIFO access, and host port control and status registers can be accessed in both host and device modes. When the OTG_FS controller is operating in one mode, either device or host, the application must not access registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit in the OTG_FS_GINTSTS register). When the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset.

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RM0368 USB on-the-go full-speed (OTG_FS)

22.16.1 CSR memory map

The host and device mode registers occupy different addresses. All registers are implemented in the AHB clock domain.

Figure 251. CSR memory map

0000h

Core glo ba l C S R s (1 K b yte)

0400h

Ho s t mode C S R s (1 K b yte)

0 8 00h

Device mode C S R s (1.5 K b yte)

0E00h

Power a nd clock g a ting C S R s (0.5 K b yte)

1000h

Device EP 0/Ho s t ch a nnel 0 FIFO (4 K b yte)

2000h

Device EP1/Ho s t ch a nnel 1 FIFO (4 K b yte)

3 000h DFIFO p us h/pop to thi s region

Device EP (x – 1)

(1)

/Ho s t ch a nnel (x – 1)

(1)

FIFO (4 K b yte)

Device EP x

(1)

/Ho s t ch a nnel x

(1)

FIFO (4 K b yte)

Re s erved

2 0000h

Direct a cce ss to d a t a FIFO RAM for de bu gging (12 8 K b yte)

DFIFO de bu g re a d/ write to thi s region

3 FFFFh a i15615 b

1. x = 3 in device mode and x = 7 in host mode.

Global CSR map

These registers are available in both host and device modes.

Acronym

OTG_FS_GOTGCTL

OTG_FS_GOTGINT

OTG_FS_GAHBCFG

OTG_FS_GUSBCFG

OTG_FS_GRSTCTL

Table 128. Core global control and status registers (CSRs)

Address offset

Register name

0x000

OTG_FS control and status register (OTG_FS_GOTGCTL) on page 700

0x004

OTG_FS interrupt register (OTG_FS_GOTGINT) on page 701

0x008

OTG_FS AHB configuration register (OTG_FS_GAHBCFG) on page 703

0x00C

OTG_FS USB configuration register (OTG_FS_GUSBCFG) on page 704

0x010

OTG_FS reset register (OTG_FS_GRSTCTL) on page 706

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Table 128. Core global control and status registers (CSRs) (continued)

Acronym

Address offset

Register name

OTG_FS_GINTSTS

OTG_FS_GINTMSK

OTG_FS_GRXSTSR

OTG_FS_GRXSTSP

0x014

OTG_FS core interrupt register (OTG_FS_GINTSTS) on page 708

0x018

OTG_FS interrupt mask register (OTG_FS_GINTMSK) on page 712

0x01C

0x020

OTG_FS Receive status debug read/OTG status read and pop registers

(OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) on page 715

OTG_FS_GRXFSIZ

OTG_FS_HNPTXFSIZ/

OTG_FS_DIEPTXF0

(1)

OTG_FS_HNPTXSTS

0x024

OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) on page 716

0x028

OTG_FS Host non-periodic transmit FIFO size register

(OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size

(OTG_FS_DIEPTXF0)

0x02C

OTG_FS non-periodic transmit FIFO/queue status register

(OTG_FS_HNPTXSTS) on page 717

OTG_FS_GCCFG

OTG_FS_CID

0x038

OTG_FS general core configuration register (OTG_FS_GCCFG) on page 718

0x03C

OTG_FS core ID register (OTG_FS_CID) on page 719

OTG_FS_HPTXFSIZ 0x100

OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) on page 720

OTG_FS_DIEPTXFx

0x104

0x108

0x10C

OTG_FS device IN endpoint transmit FIFO size register

(OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number) on page 720

1. The general rule is to use OTG_FS_HNPTXFSIZ for host mode and OTG_FS_DIEPTXF0 for device mode.

Host-mode CSR map

These registers must be programmed every time the core changes to host mode.

Acronym

OTG_FS_HCFG

OTG_FS_HFIR

OTG_FS_HFNUM

OTG_FS_HPTXSTS

OTG_FS_HAINT

OTG_FS_HAINTMSK

Table 129. Host-mode control and status registers (CSRs)

Offset address

Register name

0x400

0x404

0x408

0x410

0x414

0x418

OTG_FS Host configuration register (OTG_FS_HCFG) on page 721

OTG_FS Host frame interval register (OTG_FS_HFIR) on page 721

OTG_FS Host frame number/frame time remaining register

(OTG_FS_HFNUM) on page 722

OTG_FS_Host periodic transmit FIFO/queue status register

(OTG_FS_HPTXSTS) on page 722

OTG_FS Host all channels interrupt register (OTG_FS_HAINT) on page 723

OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK) on page 724

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Table 129. Host-mode control and status registers (CSRs) (continued)

Acronym

Offset address

Register name

OTG_FS_HPRT 0x440

OTG_FS Host port control and status register (OTG_FS_HPRT) on page 724

OTG_FS_HCCHARx

0x500

0x520

...

0x5E0

OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx)

(x = 0..7, where x = Channel_number) on page 727

OTG_FS_HCINTx

OTG_FS_HCINTMSKx

OTG_FS_HCTSIZx

0x508

0x50C

0x510

OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where x = Channel_number) on page 728

OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx)

(x = 0..7, where x = Channel_number) on page 729

OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx)

(x = 0..7, where x = Channel_number) on page 730

Device-mode CSR map

These registers must be programmed every time the core changes to device mode.

Acronym

OTG_FS_DCFG

OTG_FS_DCTL

OTG_FS_DSTS

OTG_FS_DIEPMSK

OTG_FS_DOEPMSK

OTG_FS_DAINT

OTG_FS_DAINTMSK

OTG_FS_DVBUSDIS

OTG_FS_DVBUSPULSE

OTG_FS_DIEPEMPMSK

OTG_FS_DIEPCTL0

Table 130. Device-mode control and status registers

Offset address

Register name

0x800

OTG_FS device configuration register (OTG_FS_DCFG) on page 731

0x804

OTG_FS device control register (OTG_FS_DCTL) on page 732

0x808

OTG_FS device status register (OTG_FS_DSTS) on page 733

0x810

0x814

0x818

0x81C

0x828

0x82C

0x834

0x900

OTG_FS device IN endpoint common interrupt mask register

(OTG_FS_DIEPMSK) on page 734

OTG_FS device OUT endpoint common interrupt mask register

(OTG_FS_DOEPMSK) on page 735

OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) on page 736

OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) on page 737

OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS) on page 737

OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE) on page 737

OTG_FS device IN endpoint FIFO empty interrupt mask register:

(OTG_FS_DIEPEMPMSK) on page 738

OTG_FS device control IN endpoint 0 control register

(OTG_FS_DIEPCTL0) on page 738

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Acronym

Table 130. Device-mode control and status registers (continued)

Offset address

Register name

OTG_FS_DIEPCTLx

0x920

0x940

0x960

OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number) on page 740

OTG_FS_DIEPINTx 0x908

OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx)

(x = 0..3, where x = Endpoint_number) on page 747

OTG_FS_DIEPTSIZ0

OTG_FS_DTXFSTSx 0x918

OTG_FS_DIEPTSIZx

0x910

0x930

0x950

0x970

OTG_FS device IN endpoint 0 transfer size register

(OTG_FS_DIEPTSIZ0) on page 749

OTG_FS device IN endpoint transmit FIFO status register

(OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number) on page 753

OTG_FS device OUT endpoint-x transfer size register

(OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number) on page 753

OTG_FS_DOEPCTL0 0xB00

OTG_FS device control OUT endpoint 0 control register

(OTG_FS_DOEPCTL0) on page 743

OTG_FS_DOEPCTLx

0xB20

0xB40

0xB60

OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number) on page 740

OTG_FS_DOEPINTx

OTG_FS_DOEPTSIZ0

0xB08

0xB10

OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx)

(x = 0..3, where x = Endpoint_number) on page 748

OTG_FS device OUT endpoint 0 transfer size register

(OTG_FS_DOEPTSIZ0) on page 751

OTG_FS_DOEPTSIZx

0xB30

0xB50

0xB70

OTG_FS device OUT endpoint-x transfer size register

(OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number) on page 753

Data FIFO (DFIFO) access register map

These registers, available in both host and device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of type

IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the

FIFO can only be written on the channel.

Table 131. Data FIFO (DFIFO) access register map

FIFO access register section Address range Access

Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access

Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access

Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access

Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access

0x1000–0x1FFC

0x2000–0x2FFC r w r w

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Table 131. Data FIFO (DFIFO) access register map (continued)

FIFO access register section Address range Access

...

Device IN Endpoint x

(1)

/Host OUT Channel x

: DFIFO Write Access

Device OUT Endpoint x

/Host IN Channel x