STMicroelectronics STM32L5 Series Microcontrollers Programming manual

Section 2.1.3.1 General-purpose registers

UNKNOWN

Section 2.1.3.2 Stack Pointer

0xFFFFFFFF

Section 2.1.3.4 Link Register

Section 2.1.3.5 Program Counter

PC xPSR (includes

APSR, IPSR, and

EPSR)

Either

Either -fn

Section 2.1.3.6 Combined Program Status

APSR

IPSR

EPSR

PRIMASK

FAULTMASK

BASEPRI

CONTROL

PSPLIM

MSPLIM

Either

Privileged

UNKNOWN

00000000

Section 2.1.3.6.1 Application Program Status

00000000

Section 2.1.3.6.2 Interrupt Program Status

Section 2.1.3.6.3 Execution Program Status

Section 2.1.3.7.1 Priority Mask Register

Section 2.1.3.7.2 Fault Mask Register

Section 2.1.3.7.3 Base Priority Mask Register

Section 2.1.3.8 CONTROL register

Section 2.1.3.3 Stack limit registers

1. Describes access type during program execution in Thread mode and Handler mode. Debug access can differ.

2. An entry of Either means privileged and unprivileged software can access the register.

3. Soft reset to the value retrieved by the reset handler

4. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector. All other bits are reset to 0.

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Figure 4. Core registers with the Security Extension

Low registers

High registers

Special registers

Active Stack Pointer

Link Register

Program Counter

Combined Program Status Registers

Exception mask registers

Control Register

Stack Pointer Limit registers

R10

R11

R12

SP (R13)

LR (R14)

PC (R15) xPSR

PRIMASK

FAULTMASK

BASIPRI

CONTROL

PSPLIM

MSPLIM

General purpose registers

Banked stack pointers

PSP_S

MSP_S

PSP_NS

MSP_NS

PRIMASK_S

FAULTMASK_S

BASIPRI_S

CONTROL_S

PSPLIM_S

MSPLIM_S

PRIMASK_NS

FAULTMASK_NS

BASIPRI_NS

CONTROL_NS

PSPLIM_NS

MSPLIM_NS

Banked special registers

R0-R12

MSP_S

MSP_NS

PSP_S

PSP_NS

PC xPSR (includes APSR,

IPSR, and EPSR)

APSR

IPSR

EPSR

Name

PRIMASK_S

PRIMASK_NS

FAULTMASK_S

FAULTMASK_NS

BASEPRI_S

BASEPRI_NS

Table 3. Core register set summary with the Security Extension

Type

(1)

Required privilege

(2)

Either

Reset value

UNKNOWN

Section 2.1.3.1 General-purpose registers

Section 2.1.3.2 Stack Pointer

UNKNOWN

Description

Either

Privileged

UNKNOWN

Section 2.1.3.4 Link Register

UNKNOWN

0x00000000

Section 2.1.3.5 Program Counter

Section 2.1.3.6 Combined Program Status

Section 2.1.3.6.1 Application Program Status

Section 2.1.3.6.2 Interrupt Program Status

Section 2.1.3.6.3 Execution Program Status

0x00000000

Section 2.1.3.7.1 Priority Mask Register

Section 2.1.3.7.2 Fault Mask Register

Section 2.1.3.7.3 Base Priority Mask Register

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2.1.3.1

2.1.3.2

Name

CONTROL_S

CONTROL_NS

MSPLIM_S

MSPLIM_NS

PSPLIM_S

PSPLIM_NS

Type

(1)

Required privilege

(2)

Privileged

Reset value

0x00000000

Description

Section 2.1.3.8 CONTROL register

Section 2.1.3.3 Stack limit registers

1. Describes access type during program execution in Thread mode and Handler mode. Debug access can differ.

2. An entry of Either means privileged and unprivileged software can access the register.

3. Soft reset to the value retrieved by the reset handler.

4. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector. All other bits are reset to 0.

General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations.

Stack Pointer

The stack pointer (SP) is register R13.

The processor uses a full descending stack, meaning the Stack Pointer holds the address of the last stacked item in memory. When the processor pushes a new item onto the stack, it decrements the Stack Pointer and then writes the item to the new memory location.

When Security state is implemented, software must initialize MSP_NS.

Main

Process

Stack

Table 4. Stack pointer register without the Security Extension

Stack pointer register

MSP

PSP

In Thread mode, the CONTROL.SPSEL bit indicates the stack pointer to use.

Main stack pointer (MSP). This is the reset value.

Process stack pointer (PSP)

Secure

Non-secure

Table 5. Stack pointer register with the Security Extension

Stack stack pointer register

Main

Process

Main

Process

MSP_S

PSP_S

MSP_NS

PSP_NS

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2.1.3.3

In Non-secure Thread mode, the CONTROL_NS.SPSEL bit indicates the stack pointer to use:

Main stack pointer (MSP_NS). This is the reset value.

Process stack pointer (PSP_NS).

In Non-secure Handler mode, the MSP_NS is always used.

In Secure Thread mode, the CONTROL_S.SPSEL bit indicates the stack pointer to use:

Main stack pointer (MSP_S). This is the reset value.

Process stack pointer (PSP_S).

In Secure Handler mode, the MSP_S is always used.

The current Security state of the processor determines whether the Secure or Non-secure stacks are used.

To ensure that stacks do not overrun, the processor has stack limit check registers that can be programmed to define the bounds for each of the implemented stacks.

Stack limit registers

The stack limit registers define the lower limit for the corresponding stack. The processor raises an exception on most instructions that attempt to update the stack pointer below its defined limit.

The Cortex ® ‑ M33 processor has two stack limit registers, as the following table shows.

If the Security Extension is not implemented, the Cortex ® ‑ M33 processor has two stack limit registers, as the following table shows.

Main

Process

Stack

Table 6. Stack limit registers without the Security Extension

Stack limit register

MSPLIM

PSPLIM

The Cortex ® ‑ M33 processor has four stack limit registers, as the following table shows.

Secure

Non-secure

Security state

Table 7. Stack limit registers with the Security Extension

Stack Stack limit register

Main

Process

Main

Process

MSPLIM_S

PSPLIM_S

MSPLIM_NS

PSPLIM_NS

Note: The four stack limit registers are banked between Security states.

See

Table 2. Core register set summary without the Security Extension

table for the stack limit registers attributes.

The bit assignments for the MSPLIM and PSPLIM registers are as follows:

31 3

LIMIT

RES 0

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2.1.3.4

2.1.3.5

2.1.3.6

Table 8. MSPLIM and PSPLIM register bit assignments

Bits Name

[31:3] LIMIT

[2:0] -

Function

Main stack limit or process stack limit address for the selected Security state. Limit address for the selected stack pointer.

Reserved, res0 .

Link Register

The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor sets the LR value to 0xFFFFFFFF.

Program Counter

The Program Counter (PC) is register R15. It contains the current program address.

On reset, the processor loads the PC with the value of the reset vector defined in the vector table.

Combined Program Status Register

The Combined Program Status Register (xPSR) consists of the Application Program Status Register (APSR),

Interrupt Program Status Register (IPSR), and Execution Program Status Register (EPSR).

These registers are mutually exclusive bit fields in the 32-bit PSR. The bit assignments are as follows:

31 30 29 28 27 26 25 24 23 20 19 16 15 10 9 8 0

APSR N Z C V Q Reserved GE[3:0] Reserved

IPSR Reserved ISR_NUMBER

EPSR Reserved IT/ICI T Reserved IT/ICI Reserved

Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:

•

Read all the registers using PSR with the MRS instruction.

Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.

The PSR combinations and attributes are:

2.1.3.6.1

Table 9. xPSR register combinations

IEPSR

IAPSR

EAPSR

APSR, EPSR, and IPSR

EPSR and IPSR

APSR and IPSR

APSR and EPSR

1. The processor ignores writes to the IPSR bits.

2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.

See the MRS and MSR instruction descriptions for more information about how to access the Program Status

Registers.

Application Program Status Register

The APSR contains the current state of the condition flags from previous instruction executions.

See

Table 2. Core register set summary without the Security Extension

for the APSR attributes.

The APSR bit assignments are as follows:

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2.1.3.6.2

Bits

[31]

[30]

[29]

[28]

[27]

[26:20]

[19:16]

[15:0]

Name

GE[3:0]

Table 10. APSR bit assignments

Description

Negative flag.

Zero flag.

Carry or borrow flag.

Overflow flag.

DSP overflow and saturation flag.

Reserved.

Greater than or Equal flags. See

Section 3.4.11 SEL

for more information.

Reserved.

Interrupt Program Status Register

The IPSR contains the exception number of the current ISR.

The bit assignments are:

Bits

[31:9] -

[8:0]

Name

Exception number

Table 11. IPSR bit assignments

Function

Reserved.

This is the number of the current exception:

0 = Thread mode.

1 = Reset.

2 = NMI.

3 = HardFault.

4 = MemManage.

5 = BusFault.

6 = UsageFault

7 = SecureFault

8-10 = Reserved.

7-10 = Reserved.

11 = SVCall.

12 = DebugMonitor.

13 = Reserved.

14 = PendSV.

15 =SysTick

16 = IRQ0.

495 = IRQ479.

The active bits in the Exception number field depend on the number of interrupts implemented.

0-47 interrupts = [5:0].

48-111 interrupts = [6:0].

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2.1.3.6.3

112-239 interrupts = [7:0].

240-479 interrupts = [8:0].

Execution Program Status Register

The EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction, and

Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.

See the Table 2. Core register set summary without the Security Extension for the EPSR attributes.

The following table shows the EPSR bit assignments.

Table 12. EPSR bit assignments

Bits Name

[31:27] -

[26:25], [15:10] ICI

[26:25], [15:10] IT

[24]

[23:16]

[9:0] -

Function

Reserved

Interruptible-continuable instruction bits, see

Section 2.1.3.6.4 Interruptible-continuable instructions

Indicates the execution state bits of the IT

instruction, see Section 3.9.5 IT

Thumb state bit, see

Section 2.1.3.6.6 Thumb state

Reserved

2.1.3.6.4

Note:

2.1.3.6.5

Note:

2.1.3.6.6

Attempts to read the EPSR directly through application software using the MSR instruction always return zero.

Attempts to write the EPSR using the MSR instruction in application software are ignored.

Interruptible-continuable instructions

When an interrupt occurs during the execution of an LDM , STM , PUSH , POP , VLDM , VSTM , VPUSH , or VPOP instruction, the processor can stop the load multiple or store multiple instruction operation temporarily, storing the next register operand in the multiple operation to be transferred into EPSR[15:12].

After servicing the interrupt, the processor resumes execution of the load or store multiple, starting at the register stored in EPSR[15:12].

When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

There might be cases where the processor cannot pause and resume load or store multiple instructions in this way. When this happens, the processor restarts the instruction from the beginning on return from the interrupt.

As a result, your software should never use load or store multiple instructions to memory that is not robust to repeated accesses.

If-Then block

The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others.

Interruptible-continuable operation is not supported when the load multiple or store multiple instructions are located inside an If-Then block. In these cases, the processor can take an interrupt part-way through the load or store multiple instruction, restarting it from the beginning on return from the interrupt.

Thumb state

•

The Cortex ® ‑ M33 processor only supports execution of instructions in Thumb state.

The following can modify the T bit in the EPSR:

• Instructions BLX , BX , LDR pc, [] , and POP{PC }.

Restoration from the stacked xPSR value on an exception return.

Bit[0] of the vector value on an exception entry or reset.

Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See

Section 2.6.4 Lockup

for more information.

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2.1.3.7

2.1.3.7.1

Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. For example, you might want to disable exceptions when running timing critical tasks.

To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK.PM or FAULTMASK.FM.

Priority Mask Register

The PRIMASK register is intended to disable interrupts by preventing activation of all exceptions with configurable priority in the current Security state.

See

Table 2. Core register set summary without the Security Extension

table for the PRIMASK attributes.

The bit assignments for the PRIMASK register are as follows:

31 1 0

RES 0

2.1.3.7.2

Table 13. PRIMASK register bit assignments

Bits Name

[31:1] Reserved, res0 .

Function

Setting this bit to one boosts the current execution priority to 0, masking all exceptions with a programmable priority.

Setting PRIMASK_S to one boosts the current execution priority to 0. If AIRCR.PRIS is:

[0] PM

0 Setting PRIMASK_NS to one boosts the current execution priority to 0.

1 Setting PRIMASK_NS to one boosts the current execution priority to 80.

When the current execution priority is boosted to a particular value, all exceptions with a lower or equal priority are masked.

Fault Mask Register

The FAULTMASK register prevents activation of all exceptions with configurable priority and also some exceptions with fixed priority depending on the value of AIRCR.BFHFNMINS and AIRCR.PRIS.

See

Table 2. Core register set summary without the Security Extension

table for the FAULTMASK register attributes.

The bit assignments for the FAULTMASK register are as follows:

31 1 0

RES 0

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2.1.3.7.3

Table 14. FAULTMASK register bit assignments

Bits Name

[31:1] -

Function

Reserved, res0

When TrustZone is disabled, setting this bit to one boosts the current execution priority to -1, masking all exceptions except NMI.

When TrustZone is enabled, setting this bit to one boosts the current execution priority to -1, masking all exceptions with a lower priority. If

AIRCR.BFHFNMINS is:

[0] FM

Setting FAULTMASK_S to one boosts the current execution priority to -1.

If AIRCR.PRIS is:

0: Setting FAULTMASK_NS to one boosts the current execution priority to 0

1: Setting FAULTMASK_NS to one boosts the current execution priority to 80

Setting FAULTMASK_S to one boosts the current execution priority to -3.

Setting FAULTMASK_NS to one boosts the current execution priority to -1.

When the current execution priority is boosted to a particular value, all exceptions with a lower or equal priority are masked.

Base Priority Mask Register

Use the BASEPRI register to change the priority level that is required for exception preemption.

See

Table 2. Core register set summary without the Security Extension

table for the BASEPRI register attributes.

The bit assignments for the BASEPRI register are as follows:

31 8 7 0

RES 0 BASEPRI

Bits

[31:8] -

Name

Table 15. BASEPRI register bit assignments

Function

Reserved, res0

Software can set BASEPRI to a priority number between 1 and the maximum supported priority number.

Software can set BASEPRI_S to a priority number between 1 and the maximum supported priority number. If AIRCR.PRIS is:

Software can set BASEPRI_NS to a priority number between 1 and the maximum supported priority number.

[7:0]

BASEPRI (1)

Software can set BASEPRI_NS to a priority number between 1 and the maximum supported priority number. The value in BASEPRI_NS is then mapped to the bottom half of the priority range, so that the current execution priority is boosted to the mapped-to value in the bottom half of the priority range.

When the current execution priority is boosted to a particular value, all exceptions with a lower priority are masked. Writing 0 to BASEPRI disables base priority boosting.

1. This field is similar to the priority fields in the interrupt priority registers. If the device implements only bits[7:M] of this field,

bits[M-1:0] read as zero and ignore writes. See Section 4.2.7 Interrupt Priority Registers for more information. Remember

that higher priority field values correspond to lower exception priorities.

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2.1.3.8

CONTROL register

The CONTROL register controls the stack that is used, the privilege level for software execution when the core is in Thread mode and indicates whether the FPU state is active.

See

Table 2. Core register set summary without the Security Extension

table for the CONTROL register attributes.

This register is banked between Security states on a bit by bit basis.

The bit assignments for the CONTROL register are as follows:

31 4 3 2 1 0

RES 0

SFPA

FPCA nPRIV

SPSEL

Table 16. CONTROL register bit assignments

Bits Name

[31:4] -

Function

Reserved, res0

Indicates that the floating-point registers contain active state that belongs to the Secure state:

[3]

[2]

[1]

[0]

SFPA

0 The floating-point registers do not contain state that belongs to the Secure state.

1 The floating-point registers contain state that belongs to the Secure state.

This bit is not banked between Security states and RAZ/WI from Non-secure state.

Indicates whether floating-point context is active:

0 No floating-point context active.

FPCA

1 Floating-point context active.

This bit is used to determine whether to preserve floating-point state when processing an exception.

This bit is not banked between Security states.

Defines the currently active stack pointer:

0 MSP is the current stack pointer.

SPSEL

1 PSP is the current stack pointer.

In Handler mode, this bit reads as zero and ignores writes. The Cortex ® ‑ M33 core updates this bit automatically on exception return.

This bit is banked between Security states.

Defines the Thread mode privilege level: nPRIV

Privileged.

Unprivileged.

This bit is banked between Security states.

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Cortex® M33 configurations

Note:

2.1.4

2.1.5

2.1.6

Note:

2.2

•

Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the

CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the

CONTROL register based on the EXC_RETURN value.

In an OS environment, Arm ® recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer that is used in Thread mode to the PSP, either:

Use the MSR instruction to set the CONTROL.SPSEL bit, the current active stack pointer bit, to 1.

Perform an exception return to Thread mode with the appropriate EXC_RETURN value.

When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction.

This ensures that instructions after the ISB instruction execute using the new stack pointer.

Exceptions and interrupts

The Cortex ® ‑ M33 processor implements all the logic required to handle and prioritize interrupts and other exceptions. Software can control this prioritization using the NVIC registers. All exceptions are vectored and except for reset, handled in Handler mode. Exceptions can target either Security state.

The NVIC registers control interrupt handling.

Related reference

Section 4.2 Nested Vectored Interrupt Controller

Data types and data memory accesses

•

The Cortex ® ‑ M33 processor manages all data memory accesses as little-endian.

The processor supports the following data types:

• 32-bit words.

16-bit halfwords.

8-bit bytes.

32-bit single-precision floating-point numbers.

64-bit double-precision floating-point numbers.

•

The Cortex Microcontroller Software Interface Standard

The Cortex Microcontroller Software Interface Standard (CMSIS) simplifies software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals.

For a Cortex ® ‑ M33 microcontroller system, the CMSIS defines:

• A common way to:

– Access peripheral registers.

– Define exception vectors.

The names of:

– The registers of the core peripherals.

– The core exception vectors.

A device-independent interface for RTOS kernels, including a debug channel.

The CMSIS includes address definitions and data structures for the core peripherals in the Cortex ® ‑ M33 processor.

This document includes the register names defined by the CMSIS, and short descriptions of the CMSIS functions that address the processor core and the core peripherals.

This document uses the register short names that are defined by the CMSIS. In a few cases these short names differ from the architectural short names that might be used in other documents.

Cortex ® M33 configurations

Table 17 shows the configuration for the STM32L5 Series Cortex

® M33.

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Debug

ITM support

ETM support

1. The TrustZone ® is enabled by setting the TZEN option bit.

Memory model

Table 17. STM32L5xx Cortex ® M33 configuration

Features

Security extension (TrustZone ® )

DSP

Floating Point Unit

MPU

Interrupt priority levels

Number of IRQ

WIC

CTI

STM32L5xx

Yes (1)

Yes

Yes, single precision floating point unit

MPU secure (8 regions), MPU non-secure (8 regions)

8 regions

109

Not implemented

Yes

JTAG and serial-wire debug ports 8 breakpoints and 4 watchpoints.

Data trace (DWT), and instrumentation trace (ITM)

Instruction trace interface

The Cortex ® -M33 processor has a fixed default memory map that provides up to 4GB of addressable memory.

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2.3.1

Processor memory map

The Cortex ‑ M33 processor memory map.

Figure 5. Cortex ‑ M33 processor memory map

0xFFFFFFFF

Vendor-specific memory

511MB

Private peripheralbus

1MB

0xE0100000

0xE00FFFFF

0xE0000000

0xDFFFFFFF

External device 1.0GB

0xA0000000

0x9FFFFFFF

External RAM 1.0GB

Peripheral

SRAM

Code

0x60000000

0x5FFFFFFF

0.5GB

0x40000000

0x3FFFFFFF

0x20000000

0x1FFFFFFF

0.5GB

0x00000000

The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers.

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2.3.2

Memory regions, types, and attributes

The memory map and the programming of the Secure and Non-secure MPUs splits memory into regions. If your implementation has an MPU or has the Security Extension MPUs, programming the relevant MPUs splits memory into regions.

The memory types are:

Normal

Device

Shareable

The processor can reorder transactions for efficiency, or perform Speculative reads.

The processor preserves transaction order relative to other transactions to Device memory.

The additional memory attributes include:

For a shareable memory region, the memory system might provide data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a

DMA controller.

If multiple bus masters can access a Non-shareable memory region, software must ensure data coherency between the bus masters.

Device memory is always Shareable.

Execute Never (XN)

2.3.3

Means that the processor prevents instruction accesses. A MemManage fault exception is generated on executing an instruction fetched from an XN region of memory.

Device memory

Device memory must be used for memory regions that cover peripheral control registers. Some of the optimizations that are permitted for Normal memory, such as access merging or repeating, can be unsafe for a peripheral register.

The Device memory type has several attributes:

G or nG

R or nR

Gathering or non-Gathering. Multiple accesses to a device can be merged into a single transaction except for operations with memory ordering semantics, for example, memory barrier instructions, load acquire/store release.

Reordering or non-Reordering.

E or nE

Note:

2.3.4

Note:

Early Write Acknowledgement or no Early Write Acknowledgement.

For the Cortex ‑ M33 processor, only two combinations of these attributes are valid:

• Device-nGnRnE.

• Device-nGnRE.

•

Device-nGnRnE is equivalent to Armv7 ‑ M Strongly Ordered memory type

Device-nGnRE is equivalent to Armv7 ‑ M Device memory.

Device-nGRE and Device-GRE are new to the Armv8 ‑ M architecture.

Typically, peripheral control registers must be either Device-nGnRE or Device-nGnRnE to prevent reordering of the transactions in the programming sequences.

Device memory is shareable, and must not be cached.

Secure memory system and memory partitioning

In an implementation with the Security Extension, the Security Attribution Unit (SAU) and Implementation Defined

Attribution Unit (IDAU) partition the 4GB memory space into Secure and Non-secure memory regions.

The partitioning of the memory into Secure and Non-secure regions is independent of the Security state that the

processor executes in. See Section 2.5 Security state switches for more information on Security state.

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Secure memory partitioning

Secure addresses are used for memory and peripherals that are only accessible by Secure software or Secure masters. Transactions are deemed to be secure if they are to an address that is defined as Secure. Illegitimate accesses that are made by Non-secure software to

Secure memory are blocked and raise an exception.

Non-secure Callable (NSC) NSC is a special type of Secure location that is permitted to hold an SG instruction to enable software to transition from Non-secure to Secure state. The inclusion of NSC memory locations removes the need for Secure software creators to allow for the accidental inclusion of SG instructions, or data sharing encoding values, in normal Secure memory by restricting the functionality of the SG instruction to NSC memory only.

Non-secure (NS)

2.3.5

Non-secure addresses are used for memory and peripherals accessible by all software running on the device.

Transactions are deemed to be Non-secure if they are to an address that is defined as Non-

Secure.

Note: Transactions are deemed to be Non-secure even if secure software performs the access. Memory accesses initiated by Secure software to regions marked as

Non-secure in the SAU IDAU are marked as Non-secure on the AHB bus.

The MPU is banked between Secure and Non-secure memory. For instructions fetches, addresses that are

Secure are subject to the Secure MPU settings. Addresses that are Non-secure are subject to the Non-secure

MPU settings. For data loads and data stores, accesses depend on the Security state of the processor. For example, if the processor is in Secure state the access is subject to the Secure MPU settings. If the processor is in Non-secure state the access is subject to the Non-secure MPU settings.

Behavior of memory accesses

Summary of the behavior of accesses to each region in the memory map.

Table 18. Memory access behavior

Address range

0x00000000-0x1FFFFFFF

0x20000000-0x3FFFFFFF

Memory region Memory type Shareability XN

Code

SRAM

Normal

Non-shareable -

Description

Executable region for program code.

You can also put data here.

Executable region for data. You can also put code here.

0x40000000-0x5FFFFFFF

0x60000000-0x9FFFFFFF

0xA0000000-0xDFFFFFFF

Peripheral

RAM

External device

Device, nGnRE

Normal

Device, nGnRE

Shareable

Non-shareable -

Shareable

XN On-chip device memory.

Executable region for data.

XN External device memory.

0xE0000000-0xE003FFFF

0xE0040000-0xE0043FFF

Private Peripheral

Bus

Device

Device, nGnRnE

Shareable

This region includes the SCS, NVIC,

MPU, SAU, BPU, ITM, and DWT registers.

This region is for debug components and can include the ETM, CTI, and

TPIU configuration registers or none.

0xE0044000-0xE00FFFFFF

Private Peripheral

Bus

0xE0100000-0xFFFFFFFFF Vendor_SYS

Device, nGnRnE

Device, nGnRE

Shareable

XN This region includes the ROM tables.

XN Vendor specific.

Note:

For more information on memory types, see Section 2.3.2 Memory regions, types, and attributes

The Code, SRAM, and RAM regions can hold programs.

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DMB

DSB

ISB

2.3.5.1

The MPU can override the default memory access behavior described in this section.

Additional memory access constraints for caches and shared memory

When a system includes caches or shared memory, some memory regions have additional access constraints, and some regions are subdivided.

This behavior is shown by the following table:

Address range

0x00000000-0x1FFFFFFF

0x20000000-0x3FFFFFFF

0x40000000-0x5FFFFFFF

0x60000000-0x7FFFFFFF

0x80000000-0x9FFFFFFF

0xA0000000-0xDFFFFFFF

0xE0000000-0xE003FFFF

0xE0040000-0xE0043FFF

0xE0044000-0xE00EFFFF

0xF0000000-0xFFFFFFFF

Table 19. Memory region shareability and cache policies

Memory region

Code

SRAM

Peripheral

Memory type

Normal

Device

Shareability

Shareable

RAM

External device

Private Peripheral Bus

Device

Private Peripheral Bus

Vendor_SYS

Normal

Device

Shareable

Cache policy

WBWA

Device

Note:

2.3.6

For more information on memory types and shareability, see

Section 2.3.2 Memory regions, types, and attributes

Software ordering of memory accesses

The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions.

In the Cortex ‑ M33 processor this behavior can occur because of two reasons:

• Memory or devices in the memory map might have different wait states.

• Some memory accesses associated with instruction fetches are speculative.

Section 2.3.3 Device memory describes the cases where the memory system guarantees the order of memory

accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering.

The processor provides the following memory barrier instructions:

The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions.

The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute.

The Instruction Synchronization Barrier (ISB) ensures that the effect of any context-changing operations is recognizable by subsequent instructions.

The following are examples of using memory barrier instructions:

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Memory model

Exception vector and vector table programming

If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled, then the processor uses the new exception vector.

If the program updates the value of the VTOR, use a DMB instruction to ensure that the new vector table is used for subsequent exceptions.

Self-modifying code

Memory map switching

MPU programming

If a program contains self-modifying code, use a DSB instruction followed by an ISB instruction immediately after the code modification in the program. This ensures subsequent instruction execution uses the updated program.

If the system contains a memory map switching mechanism, use a DSB instruction followed by an ISB instruction after switching the memory map. This ensures subsequent instruction execution uses the updated memory map.

Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by subsequent instructions.

SAU programming

2.3.7

Use a DSB followed by an ISB instruction or exception return to ensure that the SAU configuration is used by subsequent instructions.

Memory endianness

The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Little-endian format in

Figure 6

describes how words of data are stored in memory.

Little-endian format

In little-endian format, the processor stores the least significant byte (lsbyte) of a word at the lowest-numbered byte, and the most significant byte (msbyte) at the highest-numbered byte.

Address A

A+1

A+2

A+3

Figure 6. Little-endian example

Memory

24 23

16 15

8 7

B3 msbyte

2.3.8

Synchronization primitives

The instruction set support for the processor includes pairs of synchronization primitives . These provide a nonblocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use them to implement semaphores or an exclusive read-modify-write memory sequence.

Instructions in synchronization primitives

A pair of synchronization primitives contains the following:

A Load-Exclusive instruction

Used to read the value of a memory location, requesting exclusive access to that location.

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A Store-Exclusive instruction

Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is:

It indicates that the thread or process gained exclusive access to the memory, and the write succeeded.

It indicates that the thread or process did not gain exclusive access to the memory, and no write was performed.

Load-Exclusive and Store-Exclusive instructions

The pairs of Load-Exclusive and Store-Exclusive instructions are:

•

The word instructions:

– LDAEX and STLEX .

– LDREX and STREX .

The halfword instructions:

– LDAEXH and STLEXH .

•

– LDREXH and STREXH .

The byte instructions:

– LDAEXB and STLEXB .

– LDREXB and STREXB .

Performing an exclusive read-modify-write

Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.

To perform an exclusive read-modify-write of a memory location, the software must:

Use a Load-Exclusive instruction to read the value of the location.

Modify the value, as required.

Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.

Test the returned status bit. If this bit is:

The read-modify-write completed successfully.

No write was performed. This indicates that the value returned at step 1 might be out of date.

The software must retry the entire read-modify-write sequence.

Implementing a semaphore

The software can use the synchronization primitives to implement a semaphore as follows:

Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.

If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address.

If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1.

Exclusive tags

The processor includes an exclusive access monitor, that tags the fact that the processor has executed a Load-

Exclusive instruction. If the processor is part of a multiprocessor system with a global monitor, and the address is in a shared region of memory, then the system also globally tags the memory locations that are addressed by exclusive accesses by each processor.

The processor clears its exclusive access tag if:

• It executes a CLREX instruction.

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2.3.9

•

It executes a STREX or STLEX instruction, regardless of whether the write succeeds.

An exception occurs. This means that the processor can resolve semaphore conflicts between different threads.

In a multiprocessor implementation:

• Executing a CLREX instruction clears only the local exclusive access tag for the processor.

•

Executing a STREX or STLEX instruction, or an exception, clears the local exclusive access tags for the processor.

Executing a STREX or STLEX instruction to a Shareable memory region can also clear the global exclusive access tags for the processor in the system.

For more information about the synchronization primitive instructions, see

Section 3.12.10 LDREX and STREX

and Section 3.12.12 CLREX

A global exclusive access can be performed:

• In a Shared region if the MPU is implemented.

• By setting ACTLR.EXTEXCLALL. In this case, exclusive information is always sent externally.

In any other case, exclusive information is not sent on the AHB bus, HEXCL is 0, and only the local monitor is used.

If HEXCL is sent externally and there is no exclusive monitor for the corresponding memory region, then STREX and STLEX fails.

Programming hints for the synchronization primitives

ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for generation of these instructions.

Instruction

LDAEX

LDAEXB

LDAEXH

LDREX

LDREXB

LDREXH

STLEX

STLEXB

STLEXH

STREX

STREXB

STREXH

CLREX

Table 20. CMSIS functions for exclusive access instructions

CMSIS function uint16_t __LDAEX (volatile uint16_t * ptr) uint8_t __LDAEXB (volatile uint8_t * ptr) uint16_t __LDAEXH (volatile uint16_t * ptr) uint32_t __LDREXW (uint32_t *addr) uint8_t __LDREXB (uint8_t *addr) uint16_t __LDREXH (uint16_t *addr) uint16_t __STLEX (uint16_t value, volatile uint16_t * ptr) uint8_t __STLEXB (uint8_t value, volatile uint8_t * ptr) uint16_t __STLEXH (uint16_t value, volatile uint16_t * ptr) uint32_t __STREXW (uint32_t value, uint32_t *addr) uint8_t __STREXB (uint8_t value, uint8_t *addr) uint16_t __STREXH (uint16_t value, uint16_t *addr) void __CLREX (void)

For example: uint16_t value; uint16_t *address = 0x20001002; value = __LDREXH (address); // load 16-bit value from memory address 0x20001002

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2.4

2.4.1

Exception model

This section contains information about different parts of the exception model such as exception types, exception priorities and exception states.

Exception states

Each exception is in one of the following states.

The exception is not active and not pending.

Inactive

Pending

Active An exception is being serviced by the processor but has not completed.

Note: An exception handler can interrupt the execution of another exception handler.

In this case, both exceptions are in the active state.

Active and pending

2.4.2

The exception is being serviced by the processor and there is a pending exception from the same source.

Exception types

This section describes the exception types for a processor with and without the Security Extension.

Reset

The exception is waiting to be serviced by the processor.

An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.

NMI

HardFault

MemManage

The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When either poweron or warm reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Secure state in Thread mode.

This exception is not banked between Security states.

A Non-Maskable Interrupt (NMI) can be signaled by a peripheral or triggered by software. It is permanently enabled and has a fixed priority of -2. NMI can only be preempted by reset and, when it is Non-secure, by a Secure HardFault.

If AIRCR.BFHFNMINS=0, then the NMI is Secure.

If AIRCR.BFHFNMINS=1, then NMI is Non-secure.

A HardFault is an exception that occurs because of an error during normal or exception processing. HardFaults have a fixed priority of at least -1, meaning they have higher priority than any exception with configurable priority.

This exception is not banked between Security states.

If AIRCR.BFHFNMINS=0, HardFault handles all faults that are unable to preempt the current execution. The HardFault handler is always Secure.

If AIRCR.BFHFNMINS=1, HardFault handles faults that target Non-secure state that are unable to preempt the current execution.

HardFaults that specifically target the Secure state when AIRCR.BFHFNMINS is set to 1 have a priority of -3 to ensure they can preempt any execution. A Secure HardFault at Priority -3 is only enabled when AIRCR.BFHFNMINS is set to 1. Secure HardFault handles Secure faults that are unable to preempt current execution.

A MemManage fault is an exception that occurs because of a memory protection violation, compared to the MPU or the fixed memory protection constraints, for both instruction and data memory transactions. This fault is always used to abort instruction accesses to Execute Never

(XN) memory regions.

This exception is banked between Security states.

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BusFault

UsageFault

SecureFault

SVCall

DebugMonitor

PendSV

SysTick

Interrupt (IRQ)

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Exception model

A BusFault is an exception that occurs because of a memory-related violation for an instruction or data memory transaction. This might be from an error that is detected on a bus in the memory system.

This exception is not banked between Security states.

If BFHFNMINS=0, BusFaults target the Secure state.

If BFHFNMINS=1, BusFaults target the Non-secure state.

•

A UsageFault is an exception that occurs because of a fault related to instruction execution.

This includes:

An undefined instruction.

An illegal unaligned access.

Invalid state on instruction execution.

An error on exception return.

The following can cause a UsageFault when the core is configured by software to report them:

• An unaligned address on word and halfword memory access.

• Division by zero.

This exception is banked between Security states.

This exception is triggered by the various security checks that are performed. It is triggered, for example, when jumping from Non-secure code to an address in Secure code that is not marked as a valid entry point. Most systems choose to treat a SecureFault as a terminal condition that either halts or restarts the system. Any other handling of the SecureFault must be checked carefully to make sure that it does not inadvertently introduce a security vulnerability.

SecureFaults always target the Secure state.

A Supervisor Call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.

This exception is banked between Security states.

A DebugMonitor exception. If Halting debug is disabled and the debug monitor is enabled, a debug event causes a DebugMonitor exception when the group priority of the DebugMonitor exception is greater than the current execution priority.

PendSV is an asynchronous request for system-level service. In an OS environment, use

PendSV for context switching when no other exception is active.

This exception is banked between Security states.

A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as a system tick.

This exception is banked between Security states.

An interrupt, or IRQ, is an exception signaled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor.

This exception is not banked between Security states. Secure code can assign each interrupt to Secure or Non-secure state. By default all interrupts are assigned to Secure state.

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8-10

Table 21. Properties of the different exception types with the Security Extension

Exception number (see notes)

IRQ number

(see notes)

Exception type Priority Vector address

16 and above

-14

-13

-12

-11

-10

-9

-5

-4

-2

-1

0 and above

Reset

NMI

Secure HardFault when

AIRCR.BFHFNMINS is 1

Secure HardFault when

AIRCR.BFHFNMINS is 0

HardFault

MemManage

BusFault

UsageFault

SecureFault

Reserved

SVCall

DebugMonitor

Reserved

PendSV

SysTick

Interrupt (IRQ)

-4, the highest 0x00000004

-2 0x00000008

-3

-1

0x0000000C

-1

Configurable 0x00000010

Configurable 0x00000014

Configurable 0x00000018

Configurable 0x0000001C

Configurable 0x0000002C

Configurable 0x00000030

Configurable 0x00000038

Configurable 0x0000003C

Configurable

0x00000040 and above. Increasing in steps of 4

Activation

Asynchronous

Synchronous

Asynchronous

Note:

Reset

NMI

HardFault

• To simplify the software layer, the CMSIS only uses IRQ numbers. It uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see

Section 2.1.3.6.2 Interrupt Program

Status Register

•

For configurable priority values, see Section 4.2.7 Interrupt Priority Registers

For an asynchronous exception, other than reset, the processor can execute extra instructions between the moment the exception is triggered and the moment the processor enters the exception handler.

Privileged software can disable the exceptions that have configurable priority, as shown in the table above.

An exception that targets Secure state cannot be disabled by Non-secure code.

The exception model treats reset as a special form of exception. When either power-on or warm reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode.

A Non-Maskable Interrupt (NMI) can be signaled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or preempted by any exception other than Reset.

A HardFault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. HardFaults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority.

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MemManage

BusFault

UsageFault

SVCall

DebugMonitor

PendSV

SysTick

Interrupt (IRQ)

(XN) memory regions.

A BusFault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction. This might be from an error that is detected on a bus in the memory system.

•

A UsageFault is an exception that occurs because of a fault related to instruction execution.

This includes:

An undefined instruction.

An illegal unaligned access.

Invalid state on instruction execution.

An error on exception return.

The following can cause a UsageFault when the core is configured by software to report them:

• An unaligned address on word and halfword memory access.

• Division by zero.

A Supervisor Call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.

PendSV is an asynchronous request for system-level service. In an OS environment, use

PendSV for context switching when no other exception is active.

7-10

Table 22. Properties of the different exception type without the Security Extensions

Exception number

(see notes)

-14

IRQ number

(see notes)

-13

-12

-11

-10

Exception type

Reset

NMI

HardFault

MemManage

BusFault

UsageFault

Reserved

Priority Vector address

-4, the highest 0x00000004

-2 0x00000008

-1 0x0000000C

Configurable 0x00000010

Configurable 0x00000014

Configurable 0x00000018

Activation

Asynchronous

Synchronous

Synchronous when precise, asynchronous when imprecise

Synchronous

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Exception number

(see notes)

-5

-4

-2

-1

IRQ number

(see notes)

16 and above 0 and above

Exception type Priority Vector address Activation

SVCall Configurable 0x0000002C

DebugMonitor Configurable 0x00000030

Reserved

PendSV

Configurable

0x00000038

SysTick

Interrupt (IRQ)

Configurable 0x0000003C

Configurable

0x00000040 and above.

Increasing in steps of 4

Synchronous

Asynchronous

Note:

2.4.3

• To simplify the software layer, the CMSIS only uses IRQ numbers. It uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see

Section 2.1.3.6.2 Interrupt Program

Status Register

For configurable priority values, see Section 4.2.7 Interrupt Priority Registers

•

For an asynchronous exception, other than reset, the processor can execute extra instructions between the moment the exception is triggered and the moment the processor enters the exception handler.

Privileged software can disable the exceptions that have configurable priority, as shown in the table above.

Exception handlers

The exception handlers are the following:

Interrupt Service Routines

(ISRs)

Interrupts IRQ0-IRQ479 are the exceptions that are handled by ISRs.

Each interrupt is configured by Secure software in Secure or Non-secure state, using

NVIC_ITNS.

Fault handler

•

The fault handler handles the following exceptions:

• HardFault.

• MemManage.

BusFault.

UsageFault.

SecureFault.

There can be separate MemManage and UsageFault handlers in Secure and Non-secure state.

The AIRCR.BFHFNMINS bit controls the target state for HardFault and BusFault. SecureFault always targets Secure State.

System handlers

2.4.4

•

The system handlers handle the following system exceptions:

• NMI.

• PendSV.

SVCall.

SysTick.

Most system handlers can be banked with separate handlers between Secure and Non-secure state. The AIRCR.BFHFNMINS bit controls the target state for NMI.

Vector table

The Vector Table Offset Register (VTOR) in the System Control Block (SCB) determines the starting address of the vector table. The VTOR is banked so there is a VTOR_S and a VTOR_NS. The initial values of VTOR_S and

VTOR_NS are system design specific. The vector table used depends on the target state of the exception. For exceptions targeting the Secure state, VTOR_S is used. For exceptions targeting the Non-secure state,

VTOR_NS is used. The Vector Table Offset Register (VTOR) in the System Control Block (SCB) determines the starting address of the vector table.

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Exception model

The following figure shows the order of the exception vectors in the vector table. The least-significant bit of each vector is 1, indicating that the exception handler is written in Thumb code.

Figure 7. Vector table

Exception number IRQ number

463

479

-1

-2

-4

-5

-11

-12

-13

-14

Vector

IRQ479

IRQ2

IRQ1

IRQ0

SysTick

PendSV

Reserved

DebugMonitor

SVCall

Reserved

UsageFault

BusFaults

MemManage

HardFault

NMI

Reset

Initial SP value

Offset

0x7BC

0x48

0x44

0x40

0x3C

0x38

0x30

0x2C

0x18

0x14

0x10

0x0C

0x08

0x04

0x00

On system reset the vector table is set to the value of the external INITNSVTOR bus. Privileged software can write to VTOR to relocate the vector table start address to a different memory location, in the range 0x00000000 to 0xFFFFFF80, assuming access is allowed by the external LOCKNSVTOR pin.

The silicon vendor must configure the required alignment, which depends on the number of interrupts implemented. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64.

The following figure shows the order of the exception vectors in the Secure and Non-secure vector tables. The least-significant bit of each vector is 1, indicating that the exception handler is written in Thumb code.

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Exception model

2.4.5

Note:

Figure 8. Vector table

Exception number IRQ number

463 479

-1

-2

-3

-5

-9

-11

-12

-13

-14

Secure Vector

IRQ479

IRQ2

IRQ1

IRQ0

SysTick_S

PendSV_S

Reserved

DebugMonitor

SVCall_S

Non-secure Vector

IRQ479

IRQ2

IRQ1

IRQ0

SysTick_NS

PendSV_NS

Reserved

DebugMonitor

SVCall_NS

Reserved

SecureFault

UsageFault_S

BusFault_S

MemManage_S

HardFault_S

NMI_S

Reset

Initial SP value

UsageFault_NS

BusFault_NS

MemManage_NS

HardFault_NS

NMI_NS

Offset

0x7BC

0x48

0x44

0x40

0x3C

0x38

0x30

0x2C

0x1C

0x18

0x14

0x10

0x0C

0x08

0x04

0x00

Because reset always targets Secure state, the Non-secure Reset and Non-secure Initial SP value are ignored by the hardware.

On system reset, the Non-secure vector table is set to the value of the external INITNSVTOR bus, and the Secure vector table is set to the value of the external INITSVTOR bus. Privileged software can write to VTOR_S and

VTOR_NS to relocate the vector table start address to a different memory location, in the range 0x00000000 to

0xFFFFFF80, assuming access is allowed by the external LOCKNSVTOR and LOCKSVTAIRCR pins respectively.

The silicon vendor must configure the required alignment of the vector tables, which depends on the number of interrupts implemented. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64.

Exception priorities

•

All exceptions have an assigned priority that is used to control both pre-emption and prioritization between pending exceptions. A lower priority value indicates a higher priority. You can configure priorities for all exceptions except Reset, HardFault, and NMI.

If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see:

Section 4.3.10 System Handler Priority Registers .

Section 4.2.7 Interrupt Priority Registers .

Configurable priorities are in the range 0-255. The Reset, HardFault, and NMI exceptions, with fixed negative priority values always have higher priority than any other exception.

<Directions for licensee: The 0-255 number is a licensee-configured value. If the device implements fewer than

8 bits of priority, the licensee must change the number 0-255 to 127, 63, 31, 15 or 7 to correspond to the number of bits implemented (7 down to 3 respectively).>

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Exception model

For configurable priority exceptions, the target Security state also affects the programmed priority. Depending on the value of AIRCR.PRIS, the priority can be extended.

In the table, the values in columns 2 and 3 must match, and increase from zero in increments of 32. The values in column 4 start from 128 and increase in increments of 16.

Table 23. Extended priority

Priority value [7:5] Secure priority

Non-secure priority when AIRCR.PRIS

= 0

128

160

192

224

128

160

192

224

192

208

224

240

Non-secure priority when AIRCR.PRIS

= 1

128

144

160

176

2.4.6

2.4.7

Preemption

Return

Assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].

If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1].

When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.

Interrupt priority grouping

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields, an upper field that defines the group priority , and a lower field that defines a subpriority within the group.

Only the group priority determines pre-emption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not pre-empt the handler.

If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first.

If a pending Secure exception and a pending Non-secure exception both have the same group priority field value, the same subpriority field value, and the same exception number, the Secure exception takes precedence.

Exception entry and return

Descriptions of exception handling use the following terms.

An exception can preempt the current execution if its priority is higher than the current execution priority.

When one exception preempts another, the exceptions are called nested exceptions.

This occurs when the exception handler is completed.

The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.

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Exception model

Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler or during the return operation, if there is a pending exception that meets the requirements for exception entry, then the stack pop is skipped and control transfers directly to the new exception handler.

Late arriving interrupts

2.4.7.1

Note:

This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving may be affected by the late arrival depending on the stacking requirements of the original exception and the late-arriving exception. On return from the exception handler of the late-arriving exception, the normal tailchaining rules apply.

Exception entry

Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in

Thread mode, or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception.

When one exception preempts another, the exceptions are nested.

Sufficient priority means that the exception has higher priority than any limits set by the mask registers. An exception with lower priority than this is pending but is not handled by the processor.

When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of the data stacked is referred as the stack frame .

If the floating-point context is active, the Cortex ‑ M33 processor can automatically stack the architected floatingpoint state on exception entry. The following figure shows the Cortex ‑ M33 processor stack frame layout when an interrupt or an exception is preserved on the stack:

• with floating-point state.

• without floating-point state.

Where stack space for floating-point state is not allocated, the stack frame is the same as that of Armv8 ‑ M implementations without an FPU.

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Exception model

Figure 9. Stack frame when an interrupt or an exception is preserved on the stack with or without floatingpoint state

SP offset

0x30

0x2C

0x28

0x24

0x20

0x1C

0x18

0x14

0x10

0x0C

0x48

0x44

0x40

0x3C

0x38

0x34

0x08

0x04

0x00

0x68

0x64

0x60

0x5C

0x58

0x54

0x50

0x4C

S0 x PSR

LR (R14)

R12

Reserved

FPSCR

S15

S14

S13

S12

S11

S10

Exception frame with floating-point storage

Original SP

FP context

†

State context

† Or at offset 0x6C if at a word-aligned but not

doubleword-aligned address.

SP offset 0x20

0x1C

0x18

0x14

0x10

0x0C

0x08

0x04

0x00 x PSR

LR (R14)

R12

Exception frame without floating-point storage

Original SP ††

State context

† † Or at offset 0x24 if at a word-aligned but not

doubleword-aligned address.

When a Non-secure exception preempts a Secure context, additional context is saved onto the stack and the stacked registers are cleared to ensure no Secure data is available to Non-secure software.

If the Security Extension is implemented, when a Non-secure exception preempts software running in a Secure state, additional context is saved onto the stack and the stacked registers are cleared to ensure no Secure data is available to Non-secure software, as the following figure shows.

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PM0264

Exception model

Note:

Figure 10. Stack frame extended to save additional context when the Security Extension is implemented

SP offset

0x30

0x2C

0x28

0x24

0x20

0x1C

0x18

0x14

0x10

0x0C

0x48

0x44

0x40

0x3C

0x38

0x34

0x08

0x04

0x00 x PSR

LR (R14)

R12

R11

R10

Reserved

Integrity signature

Original SP †

State context

Additional state context

New SP

† Or at offset 0x4C if at a word-aligned but not doubleword-aligned address.

If the floating-point context is active, the Cortex ‑ M33 processor automatically stacks floating-point state in the stack frame. There are two frame formats that contain floating-point context. If an exception is taken from Secure state and FPCCR.TS is set, the additional floating-point context is stacked. In all other cases, only the standard floating-point context is stacked, as the following figure shows.

The conditions that trigger saving additional FP context are different from those that trigger additional integer context.

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Exception model

Figure 11. Extended exception stack frame

Stack frame for Secure floating-point state when FPCCR.TS = 1

SP offset Original SP †

0x28

0x24

0x20

0x1C

0x18

0x14

0x10

0x0C

0x08

0x04

0x00

0x50

0x4C

0x48

0x44

0x40

0x3C

0x38

0x34

0x30

0x2C

0x78

0x74

0x70

0x6C

0x68

0x64

0x60

0x5C

0x58

0x54

0xAC

0xA8

0xA4

0xA0

0x9C

0x98

0x94

0x90

0x8C

0x88

0x84

0x80

0x7C

0xD0

0xCC

0xC8

0xC4

0xC0

0xBC

0xB8

0xB4

0xB0

S0 x PSR

S10

S15

S14

S13

S12

S11

S23

S22

S21

S20

S19

S18

S17

S16

Reserved

FPSCR

S31

S30

S29

S28

S27

S26

S25

S24

LR (R14)

R12

R11

R10

Reserved

Integrity signature

Additional FP context

FP context

State context

Additional state context

New SP

Stack frame for Secure floating-point state when FPCCR.TS = 0

SP offset Original SP ††

0x30

0x2C

0x28

0x24

0x20

0x1C

0x18

0x14

0x10

0x0C

0x50

0x4C

0x48

0x44

0x40

0x3C

0x38

0x34

0x08

0x04

0x00

0x78

0x74

0x70

0x6C

0x68

0x64

0x60

0x5C

0x58

0x54

0x90

0x8C

0x88

0x84

0x80

0x7C

LR (R14)

R12

R11

R10

Reserved

Integrity signature

Reserved

FPSCR

S15

S14

S13

S12

S11

S10

S0 x PSR

FP context

State context

Additional state context

New SP

† Or at offset 0xD4 if at a word-aligned but not doubleword-aligned address.

†† Or at offset 0x94 if at a word-aligned but not doubleword-aligned address.

The Stack pointer of the interrupted thread or handler is always used for stacking the state before the exception is taken. For example if an exception is taken from Secure state to a Non-secure handler the Secure stack pointer is used to save the state.

Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.

The stack frame includes the return address. This is the address of the next instruction in the interrupted program.

This value is restored to the PC at exception return so that the interrupted program resumes.

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PM0264

Exception model

2.4.7.2

In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler.

At the same time, the processor writes an EXC_RETURN value to the LR. This value is used to trigger exception return when the exception handler is complete.

If no higher priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active.

If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case.

Exception return

Exception return occurs when the processor is in Handler mode and execution of one of the following instructions attempts to set the PC to an EXC_RETURN value:

•

A POP or LDM instruction that loads the PC.

An LDR instruction that loads the PC

• A BX instruction using any register.

The processor saves an EXC_RETURN value to the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. When the processor loads a value matching this pattern to the PC it detects that the operation is not a normal branch operation and, instead, that the exception is complete. As a result, it starts the exception return sequence. Bits[6:0] of the EXC_RETURN value indicate the required return stack, processor mode, Security state, and stack frame as the following table shows.

Table 24. Exception return behavior

Bits Name Function

[31:24] PREFIX

Indicates that this is an EXC_RETURN value.

This field reads as 0b11111111.

[23:7] Reserved, RES1 .

Indicates whether registers have been pushed to a Secure or Non-secure stack.

[6]

[5]

[4]

[3]

[2]

S 0 Non-secure stack used.

1 Secure stack used.

Indicates whether the default stacking rules apply, or whether the callee registers are already on the stack.

DCRS 0 Stacking of the callee saved registers is skipped.

1 Default rules for stacking the callee registers are followed.

In a PE with the Main and Floating-point Extensions:

FType

0 The PE allocated space on the stack for FP context.

1 The PE did not allocate space on the stack for FP context.

In a PE without the Floating-point Extension, this bit is Reserved, RES1 .

Indicates the mode that was stacked from.

Mode 0 Handler mode.

1 Thread mode.

SPSEL Indicates which stack contains the exception stack frame.

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2.5

PM0264

Security state switches

Bits Name

[1] -

Function

Main stack pointer.

1 Process stack pointer.

Reserved, RES0 .

Indicates the Security state the exception was taken to.

[0] ES 0

Non-secure.

Secure.

Table 25. Exception return behavior

Bits Name Function

[31:24] PREFIX

Indicates that this is an EXC_RETURN value.

This field reads as 0b11111111.

[23:7] -

[6] -

[5] -

Reserved,

RES1

RES0

RES1 .

In a PE with the Main and Floating-point Extensions:

[4]

[3]

FType

0 The PE allocated space on the stack for FP context.

1 The PE did not allocate space on the stack for FP context.

In a PE without the Floating-point Extension, this bit is Reserved, RES1 .

Indicates the mode that was stacked from.

Mode 0 Handler mode.

1 Thread mode.

Indicates which stack contains the exception stack frame.

[2] SPSEL 0 Main stack pointer.

[1:0] -

Reserved, RES0 .

Process stack pointer.

Security state switches

The following table presents the possible security transitions, the instructions that can cause them, and any faults that may be generated.

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Security state switches

Table 26. Security state transitions

Current

Security state

Secure

Non-secure

Security attribute of the branch target address

Security state change

Non-secure

Secure and Non-secure callable

Change to Non-secure state if the branch was a BXNS or BLXNS instruction, with the lsb of its target address set to 0.

Otherwise, a SecureFault is generated.

Change to Secure state if the branch target address contains an SG instruction.

If the target address does not contain an SG a SecureFault is generated.

Secure and not Non-secure callable

A SecureFault is generated.

The following figure shows the Security state transitions:

Figure 12. Security state transitions

BLXNS-call to Non-secure function

Non-secure state

BL to SG-call to entry function

Secure state

BXNS-return from entry function

BX to FNC_RETURN-return from Non-secure function

•

Secure software can call a Non-secure function using the BLXNS instruction. When this happens, the LR is set to a special value called FNC_RETURN, and the return address and XPSR is saved onto the Secure stack. Return from Non-secure state to Secure state is triggered when one of the following instructions attempts to set the PC to an FNC_RETURN value:

A POP or LDM instruction that loads the PC.

•

An LDR instruction that loads the PC.

A BX instruction using any register.

•

When a return from Non-secure state to Secure state occurs the processor restores the program counter and

XPSR from the Secure stack.

Any scenario not listed in the table triggers a SecureFault. For example:

Sequential instructions that cross security attributes from Secure to Non-secure.

A 32-bit instruction fetch that crosses regions with different security attributes.

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PM0264

Fault handling

2.6

2.6.1

Fault handling

•

Faults can occur on instruction fetches, instruction execution, and data accesses. When a fault occurs, information about the cause of the fault is recorded in various registers, according to the type of fault. Faults are a subset of the exceptions.

Faults are generated by:

• A bus error on:

– An instruction fetch or vector table load.

– A data access.

An internally-detected error such as an undefined instruction.

Attempting to execute an instruction from a memory region marked as Execute Never (XN).

A privilege violation or an attempt to access an unmanaged region causing an MPU fault.

A security violation.

Fault types reference table

The table shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred.

Table 27. Faults

Bus error:

Fault

Bus error on a vector read

Fault escalated to a hard fault

MPU or default memory map mismatch:

On instruction access

On data access

During exception stacking

During exception unstacking

During lazy floating-point state preservation

During exception stacking

During exception unstacking

During instruction prefetch

During lazy floating-point state preservation

Precise data bus error

Imprecise data bus error

Undefined instruction

Attempt to enter an invalid instruction set state (2)

Invalid EXC_RETURN value

UsageFault

Illegal unaligned load or store

Stack overflow flag

Divide By 0

Lazy state error flag

Lazy state preservation error flag

Invalid transition flag

SecureFault

Handler

HardFault

Bit name

VECTTBL

FORCED

Fault status register

Section 4.3.13 HardFault Status Register

MemManage

BusFault

IACCVIOL

Section 4.3.12.1 MemManage Fault

DACCVIOL

MSTKERR

Status Register

MUNSKERR

MLSPERR

STKERR

UNSTKERR

IBUSERR

LSPERR

PRECISERR

IMPRECISERR

UNDEFINSTR

Section 4.3.12.2 BusFault Status Register

INVSTATE

INVPC

UNALIGNED

STKOF

DIVBYZERO

LSERR

LSPERR

INVTRAN

Section 4.3.12.3 UsageFault Status

Section 4.5.7 Secure Fault Status

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Fault handling

2.6.2

Note:

Fault

Attribution unit violation flag

Invalid exception return flag

Invalid integrity signature flag

Invalid entry point

Handler

SecureFault

Bit name

AUVIOL

INVER

INVIS

INVEP

Section 4.5.7 Secure Fault Status

Fault status register

1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.

2. Attempting to use an instruction set other than the T32 instruction set or returns to a non load/store-multiple instruction with

ICI continuation.

Fault escalation to HardFault

All fault exceptions other than HardFault have configurable exception priority. Software can disable execution of the handlers for these faults.

Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler.

In some situations, a fault with configurable priority is treated as a HardFault. This is called priority escalation , and the fault is described as escalated to HardFault . Escalation to HardFault occurs when:

• A fault handler causes the same kind of fault as the one it is servicing. This escalation to HardFault occurs because a fault handler cannot preempt itself; it must have the same priority as the current execution priority level.

•

A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler for the new fault cannot preempt the currently executing fault handler.

An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception.

A fault occurs and the handler for that fault is not enabled.

If a BusFault occurs during a stack push when entering a BusFault handler, the BusFault does not escalate to a

HardFault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted.

The faults and fixed priority exceptions are also designated as Secure or Non-secure under the control of

AIRCR.BFHFMNINS. When AIRCR.BFHFMNINS is set to:

BusFaults and fixed priority exceptions are designated as Secure. The exceptions retain the prioritization of HardFault at -1 and NMI at -2.

BusFaults and fixed priority exceptions are designated as Non-secure. In this case, Secure

HardFault is introduced at priority -3 to ensure that faults that target Secure state are recognized.

The Non-secure state cannot inhibit BusFaults and fixed priority exceptions which target Secure state. Therefore when faults and fixed priority exceptions are Secure, Non-secure FAULTMASK (FAULTMASK_NS) only inhibits programmable priority exceptions, making it equivalent to Non-secure PRIMASK (PRIMASK_NS).

Non-secure programmable priority exceptions are mapped to the regular priority range 0-255, if AIRCR.PRIS is clear. Non-secure programmable priority exceptions are mapped to the bottom half the regular priority range,

128-255, if AIRCR.PRIS is set to 1. Therefore the FAULTMASK_NS sets the execution priority to 0 or 80, according to AIRCR.PRIS, to mask the Non-secure programmable priority exception only.

When BusFaults and fixed priority exceptions are Secure, FAULTMASK_S sets execution priority to -1 to inhibit everything up to and including HardFault.

When BusFaults and fixed priority exceptions are designated as Non-secure, FAULTMASK_NS boosts priority to

-1 to inhibit everything up to Non-secure HardFault at priority -1, while FAULTMASK_S boosts priority to -3 to inhibit all faults and fixed priority exceptions including the Secure HardFault at priority -3.

Only Reset can preempt the fixed priority Secure HardFault when AIRCR.BFHFNMINS is set to 1. A Secure

HardFault when AIRCR.BFHFNMINS is set to 1 can preempt any exception other than Reset. A Secure

HardFault when AIRCR.BFHFNMINS is set to 0 can preempt any exception other than Reset, NMI, or another

HardFault.

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Power management

2.6.3

2.6.4

Note:

2.7

2.7.1

Fault status registers and fault address registers

The fault status registers indicate the cause of a fault. For BusFaults, and MemManage faults, the fault address register indicates the address that is accessed by the operation that caused the fault. The fault status registers indicate the cause of a fault. For BusFaults, SecureFaults, and MemManage faults, the fault address register indicates the address that is accessed by the operation that caused the fault.

The processor has two physical fault address registers. One shared between the MMFAR_S, SFAR, and BFAR

(only if AIRCR.BFHFNMINS is set to 0), and the other shared between the MMFAR_NS and BFAR (only if

AIRCR.BFHFNMINS is set to 1). These are targeted by Secure and Non-secure faults respectively.

The processor has one physical fault address register. It is shared between the MMFAR and BFAR.

For each physical fault address register, it is only possible to report the address of one fault at a time. Each fault address register is updated when one of the *FARVALID bits is set for their respective faults in the associated

*FSR register. Any fault that targets a fault address register with one of its *FARVALID bits already set does not update the fault address. The *FARVALID bits must be cleared before another fault address can be reported.

The following table shows the fault status and fault address registers.

Table 28. Fault status and fault address registers

Handler

HardFault

MemManage

BusFault

UsageFault

SecureFault

Status register name

HFSR

MMFSR

BFSR

UFSR

SFSR

Address register name

MMFAR

BFAR

SFAR

Section 4.3.13 HardFault Status Register

1. MMFSR, MMFAR, and UFSR are banked between Security states.

Register description

Section 4.3.12.1 MemManage Fault Status Register

Section 4.3.14 MemManage Fault Address Register

Section 4.3.12.2 BusFault Status Register

Section 4.3.15 BusFault Address Register

Section 4.3.12.3 UsageFault Status Register

Section 4.5.7 Secure Fault Status Register

Section 4.5.8 Secure Fault Address Register

•

Lockup

The processor enters a lockup state if a fault occurs when it cannot be serviced or escalated. When the processor is in lockup state, it does not execute any instructions.

The processor remains in lockup state until either:

It is reset.

Preemption by a higher priority exception occurs.

It is halted by a debugger.

If lockup state occurs from a Secure HardFault when AIRCR.BFHFNMINS is set to 1 or the NMI handler, a subsequent NMI does not cause the processor to leave lockup state.

Power management

The Cortex ‑ M33 processor supports modes for sleep and deep sleep that reduce power consumption. Sleep mode stops the processor clock. Deep sleep mode stops the system clock and switches off the PLL and flash memory.

The SCR.SLEEPDEEP bit selects which sleep mode is used. For more information about the behavior of the

sleep modes, see Section 4.3.8 System Control Register .

Entering sleep mode

The system can generate spurious wakeup events. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode.

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Power management

2.7.1.1

2.7.1.2

2.7.1.3

2.7.2

2.7.2.1

2.7.2.2

2.7.3

2.7.4

Wait for interrupt

The wait for interrupt instruction, WFI , causes immediate entry to sleep mode unless the wakeup condition is true.

When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode.

Wait for event

The wait for event instruction, WFE , causes entry to sleep mode depending on the value of a one-bit event register.

When the processor executes a WFE instruction, it checks the value of the event register:

The processor stops executing instructions and enters sleep mode.

The processor clears the register to 0 and continues executing instructions without entering sleep mode.

If the event register is 1, it indicates that the processor must not enter sleep mode on execution of a WFE instruction. Typically, this is because an external event signal is asserted, or a processor in the system has executed an SEV instruction.

Sleep-on-exit

If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of all exception handlers, it immediately enters sleep mode without restoring the Thread context from the stack. Use this mechanism in applications that only require the processor to run when an exception occurs.

Wakeup from sleep mode

The conditions for the processor to wake up depend on the mechanism that causes it to enter sleep mode.

Wakeup from WFI or sleep-on-exit

Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to zero.

•

Wakeup from WFE

Conditions which cause the processor to wakeup from WFE.

The processor wakes up if:

• It detects an exception with sufficient priority to cause exception entry.

It detects an external event signal.

In a multiprocessor system, another processor in the system executes an SEV instruction.

In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry.

The external event input

The processor provides an external event input signal. Peripherals can drive this signal, either to wake the processor from WFE, or to set the internal WFE event register to 1 to indicate that the processor must not enter sleep mode on a later WFE instruction.

Power management programming hints

ISO/IEC C cannot directly generate the WFI and WFE instructions.

The CMSIS provides the following functions for these instructions: void __WFE(void) // Wait for Event void __WFI(void) // Wait for Interrupt

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The Cortex®-M33 Instruction Set

3

3.1

Note:

BIC, BICS

BKPT

BLX

BLXNS

BXNS

CBNZ

CBZ

Mnemonic

ADC, ADCS

ADD, ADDS

ADD, ADDW

ADR

AND, ANDS

ASR, ASRS

B {cond}

BFC

BFI

The Cortex

-M33 Instruction Set

Instruction set summary

The T32 instruction set is supported by the Cortex ‑ M33 processor.

•

In the following table:

• Angle brackets, <>, enclose alternative forms of the operand.

• Braces, {}, enclose optional operands.

The Operands column is not exhaustive.

Op2 is a flexible second operand that can be either a register or a constant.

Most instructions can use an optional condition code suffix.

For more information on the instructions and operands, see the instruction descriptions.

{Rd,}

Rd, label

{Rd,}

Rd, label

Table 29. Cortex ‑ M33 instruction set summary

Operands Brief description

Rn,

Rm,

Op2

#imm12

Op2

<Rs|#n>

Add with Carry

Add

Address to Register

Logical AND

Arithmetic Shift Right

Branch {conditionally}

Bit Field Clear

Flags Page

N,Z,C,V

N,Z,C,V

Section 3.12.1 ADR

N,Z,C

Section 3.8.1 BFC and BFI

Rd, #lsb, #width

Rd, Rn, #lsb,

#width

Bit Field Insert -

Section 3.8.1 BFC and BFI

{Rd,}

#imm8 label

Rn, Op2 Bit Clear

Breakpoint

Branch with Link

Branch indirect with Link and Exchange

Branch indirect with Link and Exchange, Non-secure

N,Z,C

Section 3.11.1 BKPT

Rm Branch and Exchange -

Rn,

Rn, label label

Branch and Exchange,

Non-secure

Compare and Branch on

Non Zero

Compare and Branch on

Zero

Section 3.9.4 CBZ and CBNZ

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Instruction set summary

CMN

CMP

CPSIE

DMB

DSB

Rd, Rm

Rn, Op2

Rn, Op2 i i

{opt}

Operands

EOR, EORS {Rd,} Rn, Op2 Exclusive OR

FLDMDBX

FSTMDBX

ISB

LDA

LDAB

LDAEX

LDAEXB

LDAEXH

LDAH

LDM

LDR

, FLDMIAX Rn

FSTMIAX Rn

LDMDB, LDMEA

LDMIA, LDMFD

LDR, LDRT

{opt}

Rd, [ Rn ]

Rd,

Rd, [

[

Rd, [ Rn ]

]

Rn{!}, reglist

Rn{!},

] reglist

Rn{!}, reglist

Rt, [Rn, Rm {,

LSL #shift}]

Rt, label

FLDMX (Decrement Before,

Increment After) loads

FSTMX (Decrement Before,

Increment After) stores

Instruction Synchronization

Barrier

If Then condition block

Load-Acquire Word

Load-Acquire Byte

Load-Acquire Exclusive

Word

Load-Acquire Exclusive

Byte

Load-Acquire Exclusive

Halfword

Load-Acquire Halfword

Load Multiple

Load Multiple Decrement

Before

Load Multiple, Increment

After

Load Register Word

(register offset)

Load Register Word (literal) -

Rt, [Rn, #offset]

Load Register Word

(immediate offset, unprivileged)

N,Z,C

LDRB

Mnemonic

CLREX

CLZ

CPSID

Rt, [Rn, Rm {,

LSL #shift}]

Rt, label

Brief description

Clear Exclusive

Count Leading Zeros

Compare Negative

Compare

Change Processor State,

Disable Interrupts

Change Processor State,

Enable Interrupts

Data Memory Barrier

Data Synchronization

Barrier

Load Register Byte (register offset)

Load Register Byte (literal) -

Flags Page

Section 3.12.12 CLREX

Section 3.4.4 CLZ

N,Z,C,V

Section 3.4.5 CMP and CMN

N,Z,C,V

Section 3.4.5 CMP and CMN

Section 3.11.2 CPS

Section 3.11.4 DMB

Section 3.11.5 DSB

Section 3.10.1 FLDMDBX,

FLDMIAX

Section 3.10.2 FSTMDBX,

FSTMIAX

Section 3.11.6 ISB

Section 3.9.5 IT

page 49/245

PM0264 - Rev 1

PM0264

Instruction set summary

Mnemonic

LDRB, LDRBT

Operands

Rt, [Rn, #offset]

Brief description

Load Register Byte

(immediate offset, unprivileged)

Flags Page

LDRD

Rt, Rt2, [Rn,

#offset]

Rt, Rt2, label

Load Register Dual

(immediate offset)

Load Register Dual (PCrelative)

LDREX

LDREXB

LDREXH

LDRH

LDRH, LDRHT

LDRSB

LDRSB, LDRSBT

LDRSH

LDRSH, LDRSHT

LSL, LSLS

LSR, LSRS

MLA

MLS

MOV, MOVS

MOVT

MOVW

Rt, [Rn,

Rt, [Rn]

Rt,

#offset]

Rt, [Rn, Rm {,

LSL #shift}]

Rt, label

Rt, [Rn, #offset]

Rt, [Rn, Rm {,

LSL #shift}]

Rt, label

Rt, [Rn, #offset]

Rt, [Rn, Rm {,

LSL #shift}]

Rt, label

Rt, [Rn,

Rd,

[Rn]

Rm,

Rn,

Op2

Rd, Rm

Rd,

#offset]

<Rs|#n>

Rm, Ra

#imm16

Load Register Exclusive

Byte

Load Register Exclusive

Halfword

Load Register Halfword

(register offset)

Load Register Halfword

(literal)

Load Register Halfword

(immediate offset, unprivileged)

Load Register Signed Byte

(register offset)

Load Register Signed Byte

(PC-relative)

Load Register Signed Byte

(immediate offset, unprivileged)

Load Register Signed

Halfword (register offset)

Load Register Signed

Halfword (PC-relative)

Load Register Signed

Halfword (immediate offset, unprivileged)

Logical Shift Left

Logical Shift Right

Multiply Accumulate

Multiply and Subtract

Move

Move (register)

Move Top

Move 16-bit constant

N,Z,C

Section 3.5.1 MUL, MLA, and

MLS

Section 3.5.1 MUL, MLA, and

MLS

N,Z,C

N,Z

Section 3.4.7 MOVT

N,Z,C

Section 3.5.1 MUL, MLA, and

page 50/245

PM0264 - Rev 1

PM0264

Instruction set summary

MRS

Mnemonic

MSR

MUL, MULS

MVN, MVNS

NOP

ORN, ORNS

ORR, ORRS

QDSUB

QSAX

QSUB

QSUB16

QSUB8

RBIT

REV

REV16

PKHTB, PKHBT

PLD

POP

PUSH

QADD

QADD16

QADD8

QASX

QDADD

REVSH

ROR, RORS

RRX, RRXS

RSB, RSBS

Operands

Rd, spec_reg spec_reg, Rn

{Rd,} Rn, Rm

Rd, Op2

{Rd,} Rn, Op2

{Rd,} Rn, Rm, {,

Op2}

[Rn {, #offset}] reglist reglist

{Rd,} Rn, Rm

Rd, Rn

Rd,

Rm,

{Rd,}

<Rs|#n>

Rn, Op2

Brief description

Move from Special Register to general register

Move from general register to Special Register

Flags

Multiply

Bitwise NOT

No Operation

Logical OR NOT

Logical OR

Pack Halfword

Page

Section 3.11.7 MRS

Section 3.11.8 MSR

N,Z

MLS

N,Z,C

N,Z,C

Section 3.11.9 NOP

Section 3.12.8 PUSH and POP

Section 3.7.1 PKHBT and

PKHTB

Preload Data

Pop registers from stack

Push registers onto stack

Section 3.12.7 PLD

Saturating Add

Saturating Add 16

Saturating Add 8

Saturating Add and

Subtract with Exchange

Saturating Double and Add Q

Section 3.6.5 QDADD and

QDSUB

Section 3.6.5 QDADD and

QDSUB

Saturating Double and

Subtract

Saturating Subtract and

Add with Exchange

Saturating Subtract

Saturating Subtract 16

Saturating Subtract 8

Reverse Bits

Reverse byte order in a word

Reverse byte order in each halfword

Reverse byte order in bottom halfword and sign extend

Rotate Right

Rotate Right with Extend

Reverse Subtract

N,Z,C

N,Z,C,V

page 51/245

PM0264 - Rev 1

PM0264

Instruction set summary

SASX

Mnemonic

SADD16

SADD8

SBC, SBCS

SBFX

SDIV

SEL

SEV

SHADD16

SHADD8

SHASX

SHSAX

SHSUB16

SMLAWB, SMLAWT

{Rd,}

{Rd,} Rn, Op2

Rd, Rn, #lsb,

#width

{Rd,} Rn, Rm

{Rd,}

Rn,

SHSUB8

SMLABB,

SMLABT,

SMLATB, SMLATT

{Rd,} Rn, Rm

Rd, Rn, Rm, Ra

SMLAD , SMLADX Rd, Rn, Rm, Ra

SMLAL

RdLo, RdHi, Rn,

SMLALBB,

SMLALBT,

SMLALTB,

SMLALTT

SMLALD,

SMLALDX

RdLo, RdHi, Rn,

Operands

{Rd,} Rn, Rm

Rd, Rn, Rm, Ra

SMLSD, SMLSDX Rd, Rn, Rm, Ra

SMLSLD,

SMLSLDX

RdLo, RdHi, Rn,

SMMLA, SMMLAR Rd, Rn, Rm, Ra

Brief description

Signed Add 16

Signed Add 8

Signed Add and Subtract with Exchange

Subtract with Carry

Signed Bit Field Extract

Signed Divide

Select bytes

Send Event

Secure Gateway

Signed Halving Add 16

Signed Halving Add 8

Signed Halving Add and

Subtract with Exchange

Signed Halving Subtract and Add with Exchange

Signed Halving Subtract 16 -

Signed Halving Subtract 8 -

Signed Multiply Accumulate halfwords

Signed Multiply Accumulate

Dual

Signed Multiply Accumulate

Long (32 × 32 + 64), 64-bit result

Flags

Page

Section 3.4.9 SADD16 and

SADD8

Section 3.4.9 SADD16 and

SADD8

N,Z,C,V

Section 3.8.2 SBFX and UBFX

Section 3.4.12 SHADD16 and

Section 3.4.11 SEL

Section 3.11.10 SEV

Section 3.11.11 SG

SHADD8

Section 3.4.12 SHADD16 and

SHADD8

Section 3.4.13 SHASX and

SHSAX

Section 3.4.13 SHASX and

SHSAX

Section 3.4.14 SHSUB16 and

SHSUB8

Section 3.4.14 SHSUB16 and

SHSUB8

Section 3.5.3 SMLAWB,

SMLAWT, SMLABB, SMLABT,

SMLATB, and SMLATT

Section 3.5.4 SMLAD and

SMLADX

SMLALDX, SMLALBB, SMLALBT,

Signed Multiply Accumulate

Long, halfwords

Signed Multiply Accumulate

Long Dual

Signed Multiply

Accumulate, word by halfword

Signed Multiply Subtract

Dual

Signed Multiply Subtract

Long Dual

Signed Most Significant

Word Multiply Accumulate

Section 3.5.5 SMLALD,

SMLALTB, and SMLALTT

Section 3.5.5 SMLALD,

SMLALDX, SMLALBB, SMLALBT,

SMLALTB, and SMLALTT

Section 3.5.3 SMLAWB,

SMLAWT, SMLABB, SMLABT,

SMLATB, and SMLATT

Section 3.5.6 SMLSD and

SMLSLD

Section 3.5.6 SMLSD and

SMLSLD

Section 3.5.7 SMMLA and

SMMLS

page 52/245

PM0264 - Rev 1

PM0264

Instruction set summary

SSAT

Mnemonic

SMUSD, SMUSDX

SSAT16

STLEXH

STMDB, STMEA

{Rd,}

Operands

SMMLS, SMMLSR Rd, Rn, Rm, Ra

SMMUL, SMMULR

SMUAD, SMUADX

SMULBB,

SMULBT,

SMULTB, SMULTT

Rn,

SMULL

RdLo, RdHi, Rn,

SMULWB, SMULWT {Rd,} Rn, Rm

SSAX

SSUB16

SSUB8

STL

STLB

STLEX

STLEXB

STLH

STM

STMIA, STMFD

STR

STR, STRT

STRB

Rd, Rn,

Rn, Rm

Rd, #n, Rm

{,shift #s}

Rd, #n, Rm

{Rd,} Rn, Rm

Rt, [Rn]

Rt, Rt [Rn]

Rt, [Rn]

Rn{!}, reglist

Rt, [Rn, Rm {,

LSL #shift}]

Signed Subtract 8

Store-Release Word

Store-Release Byte

Store-Release Exclusive

Word

Store-Release Exclusive

Byte

Store-Release Exclusive

Halfword

Store-Release Halfword

Store Multiple

Store Multiple Decrement

Before

Store Multiple Increment

After

Store Register Word

(register offset)

Rt, [Rn, #offset]

Store Register Word

(immediate offset, unprivileged)

Rt, [Rn, Rm {,

LSL #shift}]

Store Register Byte

(register offset)

Brief description

Signed Most Significant

Word Multiply Subtract

Signed Most Significant

Word Multiply

Signed Dual Multiply Add

Signed Multiply (halfwords) -

Flags Page

Section 3.5.7 SMMLA and

SMMLS

Section 3.5.8 SMMUL

Section 3.5.9 SMUAD and

SMUSD

Section 3.5.10 SMUL and

SMULW

Signed Multiply Long (32 ×

32), 64-bit result

Signed Multiply word by halfword

Signed Dual Multiply

Subtract

Signed Saturate Q

Signed Saturate 16

Signed Subtract and Add with Exchange

Signed Subtract 16

Section 3.5.10 SMUL and

SMULW

Section 3.5.9 SMUAD and

SMUSD

Section 3.6.2 SSAT16 and

USAT16

Section 3.4.15 SSUB16 and

SSUB8

Section 3.4.15 SSUB16 and

SSUB8

page 53/245

PM0264 - Rev 1

PM0264

Instruction set summary

Mnemonic

STRB, STRBT

STRD

STREX

STREXB

STREXH

STRH

STRH, STRHT

SUB, SUBS

SUB, SUBW

SVC

SXTAB

SXTAB16

SXTAH

SXTB

SXTB16

SXTH

TBB

TBH

TEQ

TST

TTA

TTAT

TTT

UADD16

Operands

Rt, [Rn,

Rd,

Rd, [

[

[ Rn

Rn ]

]

#offset]

{Rd,} Rn, Rm

Brief description

Store Register Byte

(immediate offset, unprivileged)

Test Target

Test Target Alternate

Domain

Test Target Alternate

Domain Unprivileged

Test Target Unprivileged

Unsigned Add 16

Flags

Page

Rt, Rt2, [Rn,

#offset]

Rd, Rt, [Rn,

#offset]

Store Register Dual two words

Store Register Exclusive

Rd,

Rt,

[Rn]

Store Register Exclusive

Byte

Store Register Exclusive

Halfword

Rt, [Rn, Rm {,

LSL #shift}]

Store Register Halfword

(register offset)

Rt, [Rn,

{Rd,}

Rn,

#offset]

Op2

#imm12

Store Register Halfword

(immediate offset, unprivileged)

Subtract

#imm Supervisor Call

{Rd,} Rn, Rm

{,ROR #n}

{Rd,} Rn, Rm

{,ROR #n}

Sign extend 8 bits to 32 and

Add

Sign extend two 8-bit values to 16 and Add

{Rd,} Rn, Rm

{,ROR #n}

Sign extend 16 bits to 32 and Add

Rd, Rm {,ROR #n} Sign extend 8 bits to 32

N,Z,C,V

Section 3.11.12 SVC

{Rd,} Rm {,ROR

#n}

{Rd,} Rm {,ROR

#n}

Sign extend 8 bits to 16

Sign extend a Halfword to

[Rn, Rm] Table Branch Byte

[Rn, Rm, LSL #1] Table Branch Halfword

Rn, Op2

Test Equivalence

Test

Section 3.9.6 TBB and TBH

N,Z,C

Section 3.4.16 TST and TEQ

N,Z,C

Section 3.4.16 TST and TEQ

Section 3.11.13 TT, TTT, TTA, and TTAT

Section 3.4.17 UADD16 and

UADD8

page 54/245

PM0264 - Rev 1

PM0264

Instruction set summary

UMLAL

UMULL

UQADD16

UQADD8

UQASX

UQSAX

UQSUB16

UQSUB8

USAD8

USADA8

USAT

Mnemonic

UADD8

UASX

UBFX

UDF

UDIV

UHADD16

UHADD8

UHASX

UHSAX

UHSUB16

UHSUB8

UMAAL

{Rd,}

Rd,

Operands

{Rd,} Rn, Rm

Rd, Rn, #lsb,

#width

{c}{q} {#}imm

{Rd,} Rn, Rm

RdLo, RdHi, Rn,

Rn,

Rn, Rm

, Ra

Brief description

Unsigned Add 8

Flags

Page

Section 3.4.17 UADD16 and

UADD8

Unsigned Add and Subtract with Exchange

Section 3.4.18 UASX and USAX

Unsigned Bit Field Extract -

Section 3.8.2 SBFX and UBFX

Permanently Undefined.

Unsigned Divide

Unsigned Halving Add 16

Unsigned Halving Add 8

Unsigned Halving Add and

Subtract with Exchange

Unsigned Halving Subtract and Add with Exchange

Unsigned Halving Subtract

Unsigned Multiply

Accumulate Accumulate

Long (32 × 32 + 32 + 32),

64-bit result

Unsigned Multiply

Accumulate Long (32 × 32

+ 64), 64-bit result

Unsigned Multiply Long (32

× 32), 64-bit result

Unsigned Saturating Add

Unsigned Saturating Add 8 -

Unsigned Saturating Add and Subtract with Exchange

Unsigned Saturating

Subtract and Add with

Exchange

Unsigned Saturating

Subtract 16

Unsigned Saturating

Subtract 8

Unsigned Sum of Absolute

Differences

Unsigned Sum of Absolute

Differences and

Accumulate

Rd, #n, Rm{,shift

#s} , Ra

Unsigned Saturate

Section 3.11.14 UDF

Section 3.4.19 UHADD16 and

UHADD8

Section 3.4.19 UHADD16 and

UHADD8

Section 3.4.20 UHASX and

UHSAX

Section 3.4.20 UHASX and

UHSAX

Section 3.4.21 UHSUB16 and

UHSUB8

Section 3.4.21 UHSUB16 and

UHSUB8

Section 3.6.6 UQASX and

UQSAX

Section 3.6.6 UQASX and

UQSAX

Section 3.4.22 USAD8

Section 3.4.23 USADA8

Section 3.4.24 USUB16 and

page 55/245

PM0264 - Rev 1

PM0264

Instruction set summary

UXTAB16

UXTAH

UXTB

UXTB16

UXTH

VABS

VADD

VCMP

Mnemonic

USAT16

USAX

USUB16

USUB8

UXTAB

VCMPE

VCVT

VCVTA

VCVTB

VCVTM

VCVTT

Operands

Rd, #n, Rm

Brief description

Unsigned Saturate 16 Q

Flags Page

Section 3.6.2 SSAT16 and

USAT16

{Rd,} Rn, Rm

{Rd,}

Rn,

.F32.Tm <Sd>, Sm

Unsigned Subtract 16

Unsigned Subtract 8

Convert from floating-point to integer

USUB8

Section 3.4.24 USUB16 and

USUB8

{Rd,} Rn, Rm

{,ROR #n}

Rotate, unsigned extend 8 bits to 32 and Add

{Rd,} Rn, Rm

{,ROR #n}

Rotate, unsigned extend two 8-bit values to 16 and

Add

{Rd,} Rn, Rm

{,ROR #n}

Rotate, unsigned extend and Add Halfword

Rd, Rm {,ROR #n} Unsigned zero-extend Byte -

{Rd,} Rm {,ROR

#n}

Unsigned zero-extend Byte

Rd, Rm {,ROR #n}

Unsigned zero-extend

Halfword

.F32 Sd, Sm

.F32 {Sd,} Sn,

Floating-point Absolute

Floating-point Add

.F32 Sd, <<Sm|

#0.0>

.F32 Sd, <<Sm|

#0.0>

Compare two floating-point registers, or one floatingpoint register and zero

Compare two floating-point registers, or one floatingpoint register and zero with

Invalid Operation check

VCVTR between floating-point and integer

Section 3.10.3 VABS

Section 3.10.4 VADD

N,Z,C,V

Section 3.10.5 VCMP and

VCMPE

N,Z,C,V

Section 3.10.5 VCMP and

VCMPE

Section 3.10.6 VCVT and

.Td.F32 Sd, Sd,

#fbits

Convert from floating-point to fixed point

Section 3.10.7 VCVT between floating-point and fixed-point

.Tm.F32 <Sd>, Sm

.F32.F16 Sd, Sm

.F16.F32 Sd, Sm

.Tm.F32 <Sd>, Sm

Unsigned Subtract and Add with Exchange

Convert from floating-point to integer with directed rounding to nearest with

Ties Away

Convert half-precision value to single-precision or double-precision

Convert single-precision or double-precision register to half-precision

Convert from floating-point to integer with directed rounding towards Minus infinity

Section 3.4.18 UASX and USAX

Section 3.10.36 VCVTB and

VCVTT

Section 3.10.36 VCVTB and

VCVTT

page 56/245

PM0264 - Rev 1

PM0264

Instruction set summary

VCVTR

VDIV

VFMA

VFMS

VFNMA

VFNMS

VLDM

VLDR

VLLDM

VLSTM

VMAXNM

VMINNM

VMLA

VMLS

VMOV

Mnemonic

VCVTN

VCVTP

Operands

.Tm.F32 <Sd>, Sm

Brief description

Convert from floating-point to integer with directed rounding to nearest with

Ties to even

Convert from floating-point to integer with directed rounding towards Plus infinity

Convert between floatingpoint and integer with rounding.

.F32 {Sd,} Sn,

{mode}{.size}

Rn{!}, list

.F32 Sd, [<Rn>

{, #offset}]

.F32 Sd, <label>

.F32 Sd,

[PC,#-0]

<c> Rn

.F32 Sd, Sn, Sm

<Sn|Rt>, <Rt|Sn>

Floating-point Divide

Floating-point Fused

Multiply Accumulate

Floating-point Fused

Multiply Subtract

Floating-point Fused

Negate Multiply Accumulate

Floating-point Fused

Negate Multiply Subtract

Floating-point Load Multiple extension registers

Floating-point Load an extension register from memory (immediate)

Load an extension register from memory

Floating-point Lazy Load multiple

Floating-point Lazy Store multiple

Maximum of two floatingpoint numbers with

IEEE754-2008 NaN handling

Minimum of two floatingpoint numbers with

IEEE754-2008 NaN handling

Floating-point Multiply

Accumulate

Floating-point Multiply

Subtract

Copy core register to single-precision

Flags

<Sm|Rt>, <Sm1|

Rt2>, <Rt|Sm>,

<Rt2|Sm1>

Copy two core registers to two single-precision

Page

VCVTR between floating-point and integer

Section 3.10.6 VCVT and

Section 3.10.8 VDIV

Section 3.10.9 VFMA and VFMS

Section 3.10.10 VFNMA and

VFNMS

Section 3.10.10 VFNMA and

VFNMS

Section 3.10.11 VLDM

Section 3.10.12 VLDR

Section 3.10.13 VLLDM

Section 3.10.14 VLSTM

Section 3.10.37 VMAXNM and

VMINNM

Section 3.10.37 VMAXNM and

VMINNM

Section 3.10.15 VMLA and

VMLS

Section 3.10.15 VMLA and

VMLS

Section 3.10.19 VMOV core register to single-precision

Section 3.10.20 VMOV two core registers to two single-precision registers

page 57/245

PM0264 - Rev 1

PM0264

Instruction set summary

VMRS

VMSR

VMUL

VNEG

VNMLA

VNMLS

VNMUL

VPOP

VPUSH

VMOV

Mnemonic

VMOV

VRINTA

VRINTM

VRINTN

VRINTP

VRINTR

Operands

{.size} Dd[x],

{.dt} Rt, Dn[x]

.F32 Sd, #immm

.F32 Sd, Sd, Sm

<Dm|Rt>, <Rt|

Rt2>, <Rt2|Dm>

Rt, FPSCR

FPSCR, Rt

Brief description

Copy core register to scalar -

Copy scalar to core register -

Flags Page

Section 3.10.22 VMOV core register to scalar

Section 3.10.18 VMOV scalar to core register

Section 3.10.16 VMOV

Immediate

Floating-point Move immediate

Copies the contents of one register to another

Floating-point Move transfers two words between two core registers and a doubleword register

Move to core register from floating-point Special

Move to floating-point

Special Register from core register

Section 3.10.17 VMOV Register

Section 3.10.21 VMOV two core registers and a double-precision register

N,Z,C,V

Section 3.10.23 VMRS

Section 3.10.24 VMSR

.F32 {Sd,} Sn,

.F32 Sd, Sm

Floating-point Multiply -

Section 3.10.25 VMUL

.F32 Sd, Sn, Sm

.F32 {Sd,} Sn,

{.size} list

.F32 Sd, Sm

Floating-point Negate

Floating-point Multiply

Accumulate and Negate

Floating-point Multiply,

Subtract and Negate

Floating-point Multiply and

Negate

Load multiple consecutive floating-point registers from the stack

Store multiple consecutive floating-point registers to the stack

Float to integer in floatingpoint format conversion with directed rounding to

Nearest with Ties Away

Float to integer in floatingpoint format conversion with directed rounding to Minus infinity

Float to integer in floatingpoint format conversion with directed rounding to

Nearest with Ties to even

Float to integer in floatingpoint format conversion with directed rounding to Plus infinity

Float to integer in floatingpoint format conversion with rounding towards value specified in FPSCR

Section 3.10.26 VNEG

Section 3.10.27 VNMLA, VNMLS and VNMUL

Section 3.10.28 VPOP

Section 3.10.29 VPUSH

Section 3.10.38 VRINTR and

VRINTX

page 58/245

PM0264

CMSIS functions

3.1.1

3.2

3.2.1

VRINTX

VRINTZ

VSEL

VSTM

VSTR

Mnemonic

VSQRT

Operands

.F32 Sd, Sm

.F32 Sd, Sn, Sm

.F32 Sd, Sm

Brief description

Float to integer in floatingpoint format conversion with rounding specified in

FPSCR

Float to integer in floatingpoint format conversion with rounding towards Zero

Flags

Select register, alternative to a pair of conditional

VMOV

Calculates floating-point

Square Root

{mode}{.size}

Rn{!}, list

Floating-point Store Multiple -

.F32 Sd, [Rn{,

#offset}]

Floating-point Store

F32 {Sd,} Sn, Sm Floating-point Subtract

Wait For Event -

Wait For Interrupt

Suspend task -

Page

Section 3.10.38 VRINTR and

VRINTX

Section 3.3.2 Restrictions when using PC or SP

Section 3.10.34 VSEL

Section 3.10.30 VSQRT

Section 3.11.17 YIELD

VSUB

WFE

WFI

YIELD

•

Binary compatibility with other Cortex processors

The processor implements the T32 instruction set and features provided by the Armv8 ‑ M architecture profile.

There are restrictions on moving code designed for processors that are implementations of the Armv6 ‑ M or

Armv7 ‑ M architectures.

If code designed for other Cortex ‑ M processors relies on memory protection, it cannot be moved to the

Cortex ‑ M33 processor. In this case, the memory protection scheme and driver code must be updated from

PMSAv7 to PMSAv8.

If code for the Armv7 ‑ M processor relies on double-precision-floating point, it cannot be moved to the Cortex ‑ M33 processor. Any Armv7 ‑ M code that uses double-precision arithmetic must be recompiled to use a software library, or DP emulation if supported by the tools.

To ensure a smooth transition, Arm recommends that code designed to operate on other Cortex ‑ M profile processor architectures obey the following rules and that you configure the Configuration and Control Register

(CCR) appropriately:

Use word transfers only to access registers in the NVIC and System Control Space (SCS).

Treat all unused SCS registers and register fields on the processor as Do-Not-Modify.

Configure the following fields in the CCR:

– STKALIGN bit to 1.

– UNALIGN_TRP bit to 1.

– Leave all other bits in the CCR register at their original value.

CMSIS functions

ISO/IEC C code cannot directly access some Cortex-M33 processor instructions. Instead, intrinsic functions that are provided by the CMSIS or a C compiler are used to generate them. If a C compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access some instructions.

List of CMSIS functions to generate some processor instructions

The CMSIS provides the following intrinsic functions that are provided to generate instructions that ISO/IEC C code cannot directly access.

PM0264 - Rev 1 page 59/245

PM0264 - Rev 1

LDRT

NOP

RBIT

REV

REV16

REVSH

ROR

LDA

LDAB

LDAEX

LDAEXB

LDAEXH

LDAH

Instruction

BKPT

CLREX

CLZ

CPSID F

CPSID I

CPSIE F

CPSIE I

DMB

DSB

ISB

RRX

SEV

STL

STLEX

STLEXB

STLEXH

STLH

STREX

STREXB

STREXH

WFE

WFI

Table 30. CMSIS functions to generate some Cortex-M33 processor instructions

CMSIS function void __BKPT void __CLREX uint8_t __CLZ (uint32_t value) void __disable_fault_irq(void) void __disable_irq(void) void __enable_fault_irq(void) void __enable_irq(void) void __DMB(void) void __DSB(void) void __ISB(void) uint32_t __LDA (volatile uint32_t * ptr) uint8_t __LDAB (volatile uint8_t * ptr) uint32_t __LDAEX (volatile uint32_t * ptr) uint8_t __LDAEXB (volatile uint32_t * ptr) uint16_t __LDAEXH (volatile uint32_t * ptr) uint32_t __LDAH (volatile uint32_t * addr) uint32_t __LDRT (uint32_t ptr) void __NOP (void) uint32_t __RBIT(uint32_t int value) uint32_t __REV(uint32_t int value) uint32_t __REV16(uint32_t int value) uint32_t __REVSH(uint32_t int value) uint32_t __ROR (uint32_t value, uint32_t shift) uint32_t __RRX (uint32_t value) void __SEV (void) void __STL (uint32_t value, volatile uint32_t * ptr) uint32_t __STLEX (uint16_t value, volatile uint32_t * ptr) uint32_t __STLEXB (uint16_t value, volatile uint8_t * ptr) uint32_t __STLEXH (uint16_t value, volatile uint16_t * ptr) void __STLH (uint16_t value, volatile uint16_t * ptr) uint32_t __STREXW (uint32_t value, uint32_t *addr) uint32_t __STREXB (uint8_t value, uint8_t *addr) uint32_t __STREXH (uint16_t value, uint16_t *addr) void __WFE(void) void __WFI(void)

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CMSIS functions

3.2.2

3.2.3

3.2.4

CMSE

CMSE is the compiler support for the Security Extension (architecture intrinsics and options) and is part of the

Arm C Language (ACLE) specification.

CMSE features are required when developing software running in Secure state. This provides mechanisms to define Secure entry points and enable the tool chain to generate correct instructions or support functions in the program image.

The CMSE features are accessed using various attributes and intrinsics. Additional macros are also defined as part of the CMSE.

CMSIS functions to access the special registers

List of functions that are provided by the CMSIS for accessing the special registers using MRS and MSR instructions.

Special register

PRIMASK

FAULTMASK

BASEPRI

CONTROL

MSP

PSP

APSR

IPSR xPSR

BASEPRI_MAX

FPSCR

MSPLIM

PSPLIM

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Access

Read

Write

Read

Write

Table 31. CMSIS functions to access the special registers

CMSIS function uint32_t __get_PRIMASK (void) void __set_PRIMASK (uint32_t value) uint32_t __get_FAULTMASK (void) void __set_FAULTMASK (uint32_t value) uint32_t __get_BASEPRI (void) void __set_BASEPRI (uint32_t value) uint32_t __get_CONTROL (void) void __set_CONTROL (uint32_t value) uint32_t __get_MSP (void) void __set_MSP (uint32_t TopOfMainStack) uint32_t __get_PSP (void) void __set_PSP (uint32_t TopOfProcStack) uint32_t __get_APSR (void) uint32_t __get_IPSR (void) uint32_t __get_xPSR (void) void __set_BASEPRI_MAX (uint32_t basePri) uint32_t __get_FPSCR (void) void __set_FPSCR (uint32_t fpscr) uint32_t __get_MSPLIM (void) void __set_MSPLIM (uint32_t MainStackPtrLimit) uint32_t __get_PSPLIM (void) void __set_PSPLIM (uint32_t ProcStackPtrLimit)

CMSIS functions to access the Non-secure special registers

The CMSIS also provides several functions for accessing the Non-secure special registers in Secure state using

MRS and MSR instructions:

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About the instruction descriptions

3.3

3.3.1

3.3.2

Note:

Special register

PRIMASK_NS

CONTROL_NS

MSP_NS

PSP_NS

MSPLIM_NS

PSPLIM_NS

Table 32. CMSIS intrinsic functions to access the Non-secure special registers

FAULTMASK_NS

Read

Write

Read

Write

Read

Write

Read

Write

Access

Read

Write

Read

Write

Read

Write

CMSIS function uint32_t __TZ_get_PRIMASK_NS (void) void __TZ_set_PRIMASK_NS (uint32_t value) uint32_t __TZ_get_FAULTMASK_NS (void) void __TZ_set_FAULTMASK_NS (uint32_t value) uint32_t __TZ_get_CONTROL_NS (void) void __TZ_set_CONTROL_NS (uint32_t value) uint32_t __TZ_get_MSP_NS (void) void __TZ_set_MSP_NS (uint32_t TopOfMainStack) uint32_t __TZ_get_PSP_NS (void) void __TZ_set_PSP_NS (uint32_t TopOfProcStack) uint32_t __TZ_get_MSPLIM_NS (void) void __TZ_set_MSPLIM_NS (uint32_t MainStackPtrLimit) uint32_t __TZ_get_PSPLIM_NS (void) void __TZ_set_PSPLIM_NS (uint32_t ProcStackPtrLimit)

About the instruction descriptions

•

The following sections give more information about using the instructions:

•

Section 3.3.1 Operands

•

Section 3.3.3 Flexible second operand

Section 3.3.4 Shift Operations

Section 3.3.5 Address alignment

Section 3.3.6 PC ‑ relative expressions

Section 3.3.7 Conditional execution

Section 3.3.8 Instruction width selection

Operands

An instruction operand can be an Arm register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands.

Operands in some instructions are flexible in that they can either be a register or a constant.

•

Restrictions when using PC or SP

Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register. See instruction descriptions for more information.

For correct operation of B{L}XNS, Rm[0] must be 0 for correct Secure to Non-secure transition.

Bit[0] of any address you write to the PC with a BX , BLX , LDM , LDR , or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex ‑ M33 processor only supports T32 instructions.

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About the instruction descriptions

3.3.3

3.3.3.1

Note:

3.3.3.1.1

3.3.3.2

Flexible second operand

Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction.

Operand2 can be:

• A constant.

• A register with optional shift.

Constant

Instruction form when specifying an Operand2 constant.

# constant where constant can be:

•

Any constant that can be produced by shifting an 8 ‑ bit value left by any number of bits within a 32 ‑ bit word.

Any constant of the form 0x00XY00XY .

•

Any constant of the form 0xXY00XY00

Any constant of the form 0xXYXYXYXY .

In these constants, X and Y are hexadecimal digits.

In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions.

When an Operand2 constant is used with the instructions MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or

TST , the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant.

Instruction substitution

Your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted.

For example, an assembler might assemble the instruction CMP Rd , #0xFFFFFFFE as the equivalent instruction

CMN Rd , #0x2 .

Register with optional shift

Instruction form when specifying an Operand2 register.

Rm {, shift }

Where:

Is the register holding the data for the second operand.

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About the instruction descriptions shift

ASR #n

LSL #n

LSR #n

ROR #n

RRX

3.3.4

3.3.4.1

Note:

Is an optional shift to be applied to Rm . It can be one of:

Arithmetic shift right n bits, 1 ≤ n ≤ 32.

Logical shift left n bits, 1 ≤ n ≤ 31.

Logical shift right n bits, 1 ≤ n ≤ 32.

Rotate right n bits, 1 ≤ n ≤ 31.

Shift right one bit and insert the carry flag into the most significant bit of the result.

If omitted, no shift occurs, equivalent to LSL #0 .

If you omit the shift, or specify LSL #0 , the instruction uses the value in Rm .

If you specify a shift, the shift is applied to the value in Rm , and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remain unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions.

Shift Operations

• Directly by the instructions ASR , LSR , LSL , ROR , and RRX , and the result is written to a destination register.

• During the calculation of Operand2 by the instructions that specify the second operand as a register with shift. The result is used by the instruction.

The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or the Flexible second operand. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length.

ASR

•

Arithmetic shift right by n bits moves the left-hand 32 n bits of the register Rm , to the right by n places, into the right-hand 32 n bits of the result. And it copies the original bit[31] of the register into the left ‑ hand n bits of the result.

You can use the ASR # n operation to divide the value in the register Rm by 2 n , with the result being rounded towards negative-infinity.

When the instruction is ASRS or when ASR # n is used in Operand2 with the instructions MOVS , MVNS , ANDS ,

ORRS , ORNS , EORS , BICS , TEQ or TST , the carry flag is updated to the last bit shifted out, bit[ n -1], of the register

Rm .

If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.

If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.

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About the instruction descriptions

Figure 13. ASR #3

5 4 3 2 1 0

Carry

Flag

3.3.4.2

Note:

LSR

•

Logical shift right by n bits moves the left-hand 32 n bits of the register Rm , to the right by n places, into the righthand 32 n bits of the result. And it sets the left ‑ hand n bits of the result to 0.

You can use the LSR # n operation to divide the value in the register Rm by 2 n , if the value is regarded as an unsigned integer.

When the instruction is LSRS or when LSR # n is used in Operand2 with the instructions MOVS , MVNS , ANDS , ORRS ,

ORNS , EORS , BICS , TEQ or TST , the carry flag is updated to the last bit shifted out, bit[ n -1], of the register Rm .

If n is 32 or more, then all the bits in the result are cleared to 0.

If n is 33 or more and the carry flag is updated, it is updated to 0.

Figure 14. LSR #3

Carry

Flag 0 0 0

31 5 4 3 2 1 0

3.3.4.3

Note:

3.3.4.4

LSL

•

Logical shift left by n bits moves the right-hand 32 n bits of the register Rm , to the left by n places, into the lefthand 32 n bits of the result. And it sets the right ‑ hand n bits of the result to 0.

You can use the LSL # n operation to multiply the value in the register Rm by 2 n , if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning.

When the instruction is LSLS or when LSL # n , with non-zero n , is used in Operand2 with the instructions MOVS ,

MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST , the carry flag is updated to the last bit shifted out, bit[ 32 n ], of the register Rm . These instructions do not affect the carry flag when used with LSL #0 .

If n is 32 or more, then all the bits in the result are cleared to 0.

If n is 33 or more and the carry flag is updated, it is updated to 0.

Figure 15. LSL #3

0 0 0

5 4 3 2 1 0

Carry

Flag

ROR

Rotate right by n bits moves the left-hand 32 n bits of the register Rm , to the right by n places, into the right-hand

32 n bits of the result. And it moves the right ‑ hand n bits of the register into the left ‑ hand n bits of the result.

When the instruction is RORS or when ROR # n is used in Operand2 with the instructions MOVS , MVNS , ANDS ,

ORRS , ORNS , EORS , BICS , TEQ or TST , the carry flag is updated to the last bit rotation, bit[ n -1], of the register Rm .

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Note: •

•

If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.

ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.

Figure 16. ROR #3

Carry

Flag

31 5 4 3 2 1 0

3.3.4.5

RRX

Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result.

When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS , MVNS , ANDS , ORRS ,

ORNS , EORS , BICS , TEQ or TST , the carry flag is updated to bit[0] of the register Rm .

Figure 17. RRX

Carry

Flag

31 30 1 0

3.3.5

3.3.6

Note:

Address alignment

•

An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.

The Cortex ‑ M33 processor supports unaligned access only for the following instructions:

• LDR , LDRT .

• LDRH , LDRHT .

•

LDRSH , LDRSHT .

STR , STRT .

STRH , STRHT .

All other load and store instructions generate a UsageFault exception if they perform an unaligned access, and therefore their accesses must be address aligned.

Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, Arm recommends that programmers ensure that accesses are aligned.

To trap accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control

•

PC

‑

relative expressions

A PC ‑‑ relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error.

For B , BL , CBNZ , and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.

For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.

Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number] .

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About the instruction descriptions

3.3.7

3.3.7.1

Note:

Conditional execution

•

Most data processing instructions can optionally update the condition flags in the Application Program Status

Register (APSR) according to the result of the operation. Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect.

You can execute an instruction conditionally, based on the condition flags set in another instruction, either:

Immediately after the instruction that updated the flags.

After any number of intervening instructions that have not updated the flags.

•

Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction:

• Does not execute.

Does not write any value to its destination register.

Does not affect any of the flags.

Does not generate any exception.

Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. Depending on the vendor, the assembler might automatically insert an IT instruction if you have conditional instructions outside the IT block.

Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result.

The condition flags

The APSR contains the N, Z, C, and V condition flags.

Set to 1 when the result of the operation was negative, cleared to 0 otherwise.

Set to 1 when the result of the operation was zero, cleared to 0 otherwise.

Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.

Set to 1 when the operation caused overflow, cleared to 0 otherwise.

For more information about APSR, see Section 2.1.3.6.1 Application Program Status Register

The C condition flag is set in one of four ways:

• For an addition, including the comparison instruction CMN , C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise.

•

For a subtraction, including the comparison instruction CMP , C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise.

For non-addition or subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter.

• For other non-addition or subtractions, C is normally left unchanged. See the individual instruction descriptions for any special cases.

•

Overflow occurs when the sign of the result, in bit[31], does not match the sign of the result had the operation been performed at infinite precision. For example, the V condition flag can be set in one of four ways:

If adding two negative values results in a positive value.

If adding two positive values results in a negative value.

If subtracting a positive value from a negative value generates a positive value.

If subtracting a negative value from a positive value generates a negative value.

The Compare operations are identical to subtracting, for CMP , or adding, for CMN , except that the result is discarded. See the instruction descriptions for more information.

Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more information.

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About the instruction descriptions

3.3.7.2

Suffix

CS or HS

CC or LO

Condition code suffixes

The instructions that can be conditional have an optional condition code, shown in syntax descriptions as { cond }.

Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition.

You can use conditional execution with the IT instruction to reduce the number of branch instructions in code.

The following table also shows the relationship between condition code suffixes and the N, Z, C, and V flags.

Flags

Z = 1

Z = 0

C = 1

C = 0

N = 1

N = 0

V = 1

V = 0

C = 1 and Z = 0

C = 0 or Z = 1

N = V

N != V

Z = 0 and N = V

Z = 1 and N != V

Can have any value

Table 33. Condition code suffixes

Meaning

Equal.

Not equal.

Higher or same, unsigned.

Lower, unsigned.

Negative.

Positive or zero.

Overflow.

No overflow.

Higher, unsigned.

Lower or same, unsigned.

Greater than or equal, signed.

Less than, signed.

Greater than, signed.

Less than or equal, signed.

Always. This is the default when no suffix is specified.

The following example shows the use of a conditional instruction to find the absolute value of a number. R0 = abs ( R1 ).

Absolute value

MOVS R0, R1 ; R0 = R1, setting flags.

IT MI ; Skipping next instruction if value 0 or positive.

RSBMI R0, R0, #0 ; If negative, R0 = -R0.

The following example shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3 .

Compare and update value

CMP R0, R1 ; Compare R0 and R1, setting flags.

ITT GT ; Skip next two instructions unless GT condition holds.

CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags.

MOVGT R4, R5 ; If still 'greater than', do R4 = R5.

3.3.8

Instruction width selection

There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, you can force a specific instruction size by using an instruction width suffix. The .W

suffix forces a 32-bit instruction encoding. The .N

suffix forces a

16-bit instruction encoding.

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General data processing instructions

Note:

If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error.

In some cases it might be necessary to specify the .W

suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding.

To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any.

The following example shows instructions with the instruction width suffix.

Instruction width selection

BCS.W label ; Creates a 32-bit instruction even for a short branch.

ADDS.W R0, R0, R1 ; Creates a 32-bit instruction even though the same

; operation can be done by a 16-bit instruction.

3.4

General data processing instructions

Table 34 shows the data processing instructions:

Table 34. Data processing instructions

MOVW

MVN

ORN

ORR

RBIT

REV

REV16

CMN

CMP

EOR

LSL

LSR

MOV

MOVT

Mnemonic

ADC

ADD

ADDW

AND

ASR

BIC

CLZ

REVSH

ROR

RRX

RSB

Add with Carry

Add

Logical AND

Arithmetic Shift Right

Bit Clear

Count leading zeros

Compare Negative

Compare

Exclusive OR

Logical Shift Left

Logical Shift Right

Move

Move Top

Move 16-bit constant

Move NOT

Logical OR NOT

Logical OR

Reverse Bits

Reverse byte order in a word

Reverse byte order in each halfword

Reverse byte order in bottom halfword and sign extend

Rotate Right

Rotate Right with Extend

Reverse Subtract

Brief description See

Section 3.4.3 ASR, LSL, LSR, ROR, and RRX

Section 3.4.5 CMP and CMN

Section 3.4.4 CLZ

Section 3.4.3 ASR, LSL, LSR, ROR, and RRX

Section 3.4.7 MOVT

Section 3.4.8 REV, REV16, REVSH, and RBIT

Section 3.4.3 ASR, LSL, LSR, ROR, and RRX

Section 3.4.9 SADD16 and SADD8

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General data processing instructions

3.4.1

Mnemonic

SADD16 Signed Add 16

SADD8 Signed Add 8

Brief description

SASX

SEL

SSAX

Signed Add and Subtract with Exchange

Select bytes

Signed Subtract and Add with Exchange

SBC Subtract with Carry

SHADD16 Signed Halving Add 16

SHADD8 Signed Halving Add 8

SHASX Signed Halving Add and Subtract with Exchange

SHSAX Signed Halving Subtract and Add with Exchange

SHSUB16 Signed Halving Subtract 16

SHSUB8 Signed Halving Subtract 8

SSUB16 Signed Subtract 16

SSUB8 Signed Subtract 8

SUB Subtract

SUBW

TEQ

Subtract

Test Equivalence

TST Test

UADD16 Unsigned Add 16

UADD8

UASX

USAX

Unsigned Add 8

Unsigned Add and Subtract with Exchange

Unsigned Subtract and Add with Exchange

UHADD16 Unsigned Halving Add 16

UHADD8 Unsigned Halving Add 8

UHASX Unsigned Halving Add and Subtract with Exchange

UHSAX Unsigned Halving Subtract and Add with Exchange

UHSUB16 Unsigned Halving Subtract 16

UHSUB8 Unsigned Halving Subtract 8

USAD8 Unsigned Sum of Absolute Differences

USADA8 Unsigned Sum of Absolute Differences and Accumulate

USUB16 Unsigned Subtract 16

USUB8 Unsigned Subtract 8

ADD, ADC, SUB, SBC, and RSB

Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.

op {S}{ cond } { Rd ,} Rn , Operand2 ; ADD; ADC; SBC; RSB op {S|W}{ cond } { Rd ,} Rn , # imm12 ; ADD; SUB

Where:

See

Section 3.4.11 SEL

Section 3.4.12 SHADD16 and SHADD8

Section 3.4.13 SHASX and SHSAX

Section 3.4.14 SHSUB16 and SHSUB8

Section 3.4.15 SSUB16 and SSUB8

Section 3.4.16 TST and TEQ

Section 3.4.17 UADD16 and UADD8

Section 3.4.18 UASX and USAX

Section 3.4.19 UHADD16 and UHADD8

Section 3.4.20 UHASX and UHSAX

Section 3.4.21 UHSUB16 and UHSUB8

Section 3.4.22 USAD8

Section 3.4.23 USADA8

Section 3.4.24 USUB16 and USUB8

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General data processing instructions op

ADD

Add.

ADC

Add with Carry.

Is one of:

SUB

Subtract.

SBC

Subtract with Carry.

RSB

Reverse Subtract.

Is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the register holding the first operand.

Operand2

Is a flexible second operand.

imm12

Is any value in the range 0-4095.

Note:

Operation

The ADD instruction adds the value of Operand2 or imm12 to the value in Rn .

The ADC instruction adds the values in Rn and Operand2 , together with the carry flag.

The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn .

The SBC instruction subtracts the value of Operand2 from the value in Rn . If the carry flag is clear, the result is reduced by one.

The RSB instruction subtracts the value in Rn from the value of Operand2 . This is useful because of the wide range of options for Operand2 .

Use ADC and SBC to synthesize multiword arithmetic.

ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses the imm12 operand.

Restrictions

In these instructions:

• Operand2 must not be SP and must not be PC.

• Rd can be SP only in ADD

– Rn must also be SP.

and SUB , and only with the additional restrictions:

•

– Any shift in Operand2 must be limited to a maximum of 3 bits using LSL .

Rn can be SP only in ADD and SUB .

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General data processing instructions

Note:

•

Rd can be PC only in the ADD{ cond } PC, PC, Rm instruction where:

– You must not specify the S suffix.

– Rm must not be PC and must not be SP.

– If the instruction is conditional, it must be the last instruction in the IT block.

with the exception of the ADD{ cond } PC, PC, Rm instruction, Rn can be PC only in ADD and SUB , and only with the additional restrictions:

– You must not specify the S suffix.

– The second operand must be a constant in the range 0-4095.

– When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 00 before performing the calculation, making the base address for the calculation word-aligned.

– If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. Arm recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because your assembler automatically calculates the correct constant for the ADR instruction.

When Rd is PC in the ADD{ cond } PC, PC, Rm instruction:

• Bit[0] of the value written to the PC is ignored.

• A branch occurs to the address created by forcing bit[0] of that value to 0.

Condition flags

If S is specified, these instructions update the N, Z, C and V flags according to the result.

ADD R2, R1, R3

SUBS R8, R6, #240 ; Sets the flags on the result.

RSB R4, R4, #1280 ; Subtracts contents of R4 from 1280.

ADCHI R11, R0, R3 ; Only executed if C flag set and Z.

; flag clear.

Multiword arithmetic examples

The following example shows two instructions that add a 64 ‑ bit integer contained in R2 and R3 to another 64 ‑ bit integer contained in R0 and R1 , and place the result in R4 and R5 .

64-bit addition

ADDS R4, R0, R2 ; Add the least significant words.

ADC R5, R1, R3 ; Add the most significant words with carry.

Multiword values do not have to use consecutive registers. The following example shows instructions that subtract a 96 ‑ bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2.

96-bit subtraction

3.4.2

SUBS R6, R6, R9 ; Subtract the least significant words.

SBCS R9, R2, R1 ; Subtract the middle words with carry.

SBC R2, R8, R11 ; Subtract the most significant words with carry.

AND, ORR, EOR, BIC, and ORN

Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.

op {S}{ cond } { Rd ,} Rn , Operand2

Where:

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General data processing instructions op

Is one of:

AND

Logical AND.

ORR

Logical OR, or bit set.

EOR

Logical Exclusive OR.

BIC

Logical AND NOT, or bit clear.

ORN

Logical OR NOT.

Is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the register holding the first operand.

Operand2

Is a flexible second operand.

Operation

The AND , EOR , and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2 .

The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2 .

The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2 .

Restrictions

Do not use SP and do not use PC.

Condition flags

If S is specified, these instructions:

•

Update the N and Z flags according to the result.

Can update the C flag during the calculation of

Do not affect the V flag.

Operand2 .

AND R9, R2, #0xFF00

ORREQ R2, R0, R5

ANDS R9, R8, #0x19

EORS R7, R11, #0x18181818

BIC R0, R1, #0xab

ORN R7, R11, R14, ROR #4

ORNS R7, R11, R14, ASR #32

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General data processing instructions

3.4.3

ASR, LSL, LSR, ROR, and RRX

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.

op {S}{ cond } Rd , Rm , Rs op {S}{ cond } Rd , Rm , # n

RRX{S}{ cond } Rd , Rm

Where: op

Is one of:

ASR

Arithmetic Shift Right.

LSL

Logical Shift Left.

LSR

Logical Shift Right.

ROR

Rotate Right.

Is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

Is the destination register.

Is the register holding the value to be shifted.

Is the register holding the shift length to apply to the value in Rm . Only the least significant byte is used and can be in the range 0-255.

Is the shift length. The range of shift length depends on the instruction:

ASR

Shift length from 1 to 32

LSL

Shift length from 0 to 31

LSR

Shift length from 1 to 32

ROR

Shift length from 1 to 31.

Note: MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0 .

Operation

ASR , LSL , LSR , and ROR move the bits in the register Rm to the left or right by the number of places specified by constant n or register Rs .

RRX moves the bits in register Rm to the right by 1.

In all these instructions, the result is written to Rd , but the value in register Rm remains unchanged. For details on what result is generated by the different instructions.

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General data processing instructions

3.4.4

cond

3.4.5

cond

Restrictions

Do not use SP and do not use PC.

Condition flags

If S is specified:

• These instructions update the N, Z and C flags according to the result.

• The C flag is updated to the last bit shifted out, except when the shift length is 0.

ASR R7, R8, #9 ; Arithmetic shift right by 9 bits.

LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update.

LSR R4, R5, #6 ; Logical shift right by 6 bits.

ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6.

RRX R4, R5 ; Rotate right with extend.

CLZ

Count Leading Zeros.

CLZ { cond } Rd , Rm

Where:

Is an optional condition code.

Is the destination register.

Is the operand register.

Operation

The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd . The result value is 32 if no bits are set and zero if bit[31] is set.

Restrictions

Do not use SP and do not use PC.

Condition flags

This instruction does not change the flags.

CLZ R4,R9

CLZNE R2,R3

CMP and CMN

Compare and Compare Negative.

CMP { cond } Rn , Operand2

CMN { cond } Rn , Operand2

Where:

Is an optional condition code.

Is the register holding the first operand.

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General data processing instructions

Operand2

3.4.6

Is a flexible second operand.

Operation

These instructions compare the value in a register with Operand2 . They update the condition flags on the result, but do not write the result to a register.

The CMP instruction subtracts the value of Operand2 from the value in Rn . This is the same as a SUBS instruction, except that the result is discarded.

The CMN instruction adds the value of Operand2 to the value in Rn . This is the same as an ADDS instruction, except that the result is discarded.

Restrictions

In these instructions:

• Do not use PC.

• Operand2 must not be SP.

Condition flags

These instructions update the N, Z, C and V flags according to the result.

CMP R2, R9

CMN R0, #6400

CMPGT SP, R7, LSL #2

MOV and MVN

Move and Move NOT.

MOV{S} { cond } Rd , Operand2

MOV{S} { cond } Rd , Rm

MOV{W} { cond } Rd , # imm16

MVN{S} { cond } Rd , Operand2

Where:

S cond

Operand2

Rm imm16

Is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

Is an optional condition code.

Is the destination register.

Is a flexible second operand.

The source register.

Is any value in the range 0-65535.

Operation

The MOV instruction copies the value of Operand2 into Rd .

When Operand2 in a MOV instruction is a register with a shift other than LSL #0 , the preferred syntax is the corresponding shift instruction:Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:

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General data processing instructions

Note:

3.4.7

cond

Rd imm16

•

ASR{S}{ cond } Rd , Rm , #n is the preferred syntax for MOV{S}{ cond } Rd , Rm , ASR #n .

LSL{S}{ cond } Rd , Rm , #n is the preferred syntax for MOV{S}{ cond } Rd , Rm , LSL #n if n != 0.

LSR{S}{ cond } Rd , Rm , #n is the preferred syntax for MOV{S}{ cond } Rd , Rm , LSR #n .

ROR{S}{ cond } Rd , Rm , #n is the preferred syntax for MOV{S}{ cond } Rd , Rm , ROR #n .

RRX{S}{ cond } Rd , Rm is the preferred syntax for MOV{S}{ cond } Rd , Rm , RRX .

MOV{S}{ cond } Rd , Rm , ASR Rs is a synonym for ASR{S}{ cond } Rd , Rm , Rs .

MOV{S}{ cond } Rd , Rm , LSL Rs is a synonym for LSL{S}{ cond } Rd , Rm , Rs .

MOV{S}{ cond } Rd , Rm , LSR Rs is a synonym for LSR{S}{ cond } Rd , Rm , Rs .

MOV{S}{ cond } Rd , Rm , ROR Rs is a synonym for ROR{S}{ cond } Rd , Rm , Rs .

The MVN instruction takes the value of Operand2 , performs a bitwise logical NOT operation on the value, and places the result into Rd .

The MOVW instruction provides the same function as MOV , but is restricted to using the imm16 operand.

Restrictions

You can use SP and PC only in the MOV instruction, with the following restrictions:

• The second operand must be a register without shift.

• You must not specify the S suffix.

When Rd is PC in a MOV instruction:

•

Bit[0] of the value written to the PC is ignored.

A branch occurs to the address created by forcing bit[0] of that value to 0.

Though it is possible to use MOV as a branch instruction, Arm strongly recommends the use of a BX or BLX instruction to branch for software portability to the Arm instruction set.

Condition flags

If S is specified, these instructions:

•

Update the N and Z flags according to the result.

Can update the C flag during the calculation of

Do not affect the V flag.

Operand2 .

MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated.

MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated.

MOVS R10, R12 ; Write value in R12 to R10, flags get updated.

MOV R3, #23 ; Write value of 23 to R3.

MOV R8, SP ; Write value of stack pointer to R8.

MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF).

; to the R2 and update flags.

MOVT

Move Top.

MOVT{ cond } Rd , # imm16

Where:

Is an optional condition code.

Is the destination register.

Is a 16 ‑ bit immediate constant and must be in the range 0-65535.

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General data processing instructions

Operation

MOVT writes a 16 ‑ bit immediate value, imm16 , to the top halfword, Rd [31:16], of its destination register. The write does not affect Rd [15:0].

The MOV , MOVT instruction pair enables you to generate any 32 ‑ bit constant.

Restrictions

Rd must not be SP and must not be PC.

Condition flags

This instruction does not change the flags.

MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword

; and APSR are unchanged.

3.4.8

REV, REV16, REVSH, and RBIT

Reverse bytes and Reverse bits.

op { cond } Rd , Rn

Where: op

Is one of:

REV

Reverse byte order in a word.

REV16

Reverse byte order in each halfword independently.

REVSH

Reverse byte order in the bottom halfword, and sign extend to 32 bits.

RBIT

Reverse the bit order in a 32 ‑ bit word.

cond

Is an optional condition code.

Is the destination register.

Is the register holding the operand.

Operation

Use these instructions to change endianness of data:

REV

REV16 converts either:

•

32 ‑ bit big ‑ endian data into little ‑ endian data.

32 ‑ bit little ‑ endian data into big ‑ endian data.

converts either:

•

16 ‑ bit big ‑ endian data into little ‑ endian data.

16 ‑ bit little ‑ endian data into big ‑ endian data.

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General data processing instructions

REVSH converts either:

•

16 ‑ bit signed big ‑ endian data into 32 ‑ bit signed little ‑ endian data.

16 ‑ bit signed little ‑ endian data into 32 ‑ bit signed big ‑ endian data.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

3.4.9

REV R3, R7 ; Reverse byte order of value in R7 and write it to R3.

REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0.

REVSH R0, R5 ; Reverse Signed Halfword.

REVHS R3, R7 ; Reverse with Higher or Same condition.

RBIT R7, R8 ; Reverse bit order of value in R8 and write the result to R7.

SADD16 and SADD8

Signed Add 16 and Signed Add 8.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

SADD16

Performs two 16-bit signed integer additions.

SADD8

Performs four 8-bit signed integer additions.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

Use these instructions to perform a halfword or byte add in parallel.

The SADD16 instruction:The SADD8 instruction:

Adds each halfword from the first operand to the corresponding halfword of the second operand.

Writes the result in the corresponding halfwords of the destination register.

Adds each byte of the first operand to the corresponding byte of the second operand.

Writes the result in the corresponding bytes of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions set the APSR.GE bits according to the results of the additions.

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General data processing instructions

For SADD16 : if ConditionPassed() then

EncodingSpecificOperations();

sum1 = SInt(R[n]<15:0>) + SInt(R[m]<15:0>);

sum2 = SInt(R[n]<31:16>) + SInt(R[m]<31:16>);

R[d]<15:0> = sum1<15:0>;

R[d]<31:16> = sum2<15:0>;

APSR.GE<1:0> = if sum1 >= 0 then '11' else '00';

APSR.GE<3:2> = if sum2 >= 0 then '11' else '00';

For SADD8 : if ConditionPassed() then

EncodingSpecificOperations();

sum1 = SInt(R[n]<7:0>) + SInt(R[m]<7:0>);

sum2 = SInt(R[n]<15:8>) + SInt(R[m]<15:8>);

sum3 = SInt(R[n]<23:16>) + SInt(R[m]<23:16>);

sum4 = SInt(R[n]<31:24>) + SInt(R[m]<31:24>);

R[d]<7:0> = sum1<7:0>;

R[d]<15:8> = sum2<7:0>;

R[d]<23:16> = sum3<7:0>;

R[d]<31:24> = sum4<7:0>;

APSR.GE<0> = if sum1 >= 0 then '1' else '0';

APSR.GE<1> = if sum2 >= 0 then '1' else '0';

APSR.GE<2> = if sum3 >= 0 then '1' else '0';

APSR.GE<3> = if sum4 >= 0 then '1' else '0';

3.4.10

SADD16 R1, R0 ; Adds the halfwords in R0 to the corresponding halfwords of

; R1 and writes to corresponding halfword of R1.SADD8 R4, R0, R5

; Adds bytes of R0 to the corresponding byte in R5 and writes

; to the corresponding byte in R4.

SASX and SSAX

Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

SASX

Signed Add and Subtract with Exchange.

SSAX

Signed Subtract and Add with Exchange.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

The SASX instruction:

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General data processing instructions

3.4.11

cond

Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.

Writes the signed result of the addition to the top halfword of the destination register.

Subtracts the signed bottom halfword of the second operand from the top signed halfword of the first operand.

Writes the signed result of the subtraction to the bottom halfword of the destination register.

The SSAX instruction:

Subtracts the signed bottom halfword of the second operand from the top signed halfword of the first operand.

Writes the signed result of the addition to the bottom halfword of the destination register.

Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.

Writes the signed result of the subtraction to the top halfword of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions set the APSR.GE bits according to the results.

For SASX : if ConditionPassed() then

EncodingSpecificOperations();

diff = SInt(R[n]<15:0>) - SInt(R[m]<31:16>);

sum = SInt(R[n]<31:16>) + SInt(R[m]<15:0>);

R[d]<15:0> = diff<15:0>;

R[d]<31:16> = sum<15:0>;

APSR.GE<1:0> = if diff >= 0 then '11' else '00';

APSR.GE<3:2> = if sum >= 0 then '11' else '00';

For SSAX : if ConditionPassed() then

EncodingSpecificOperations();

sum = SInt(R[n]<15:0>) + SInt(R[m]<31:16>);

diff = SInt(R[n]<31:16>) - SInt(R[m]<15:0>);

R[d]<15:0> = sum<15:0>;

R[d]<31:16> = diff<15:0>;

APSR.GE<1:0> = if sum >= 0 then '11' else '00';

APSR.GE<3:2> = if diff >= 0 then '11' else '00';

SASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and

; writes to top halfword of R0.

; Subtracts bottom halfword of R5 from top halfword of R4

; and writes to bottom halfword of R0.

SSAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3

; and writes to bottom halfword of R7.

; Adds top halfword of R3 with bottom halfword of R2 and

; writes to top halfword of R7.

SEL

Select bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags.

SEL{ cond } { Rd ,} Rn , Rm

Where:

Is an optional condition code.

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General data processing instructions

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

The SEL instruction:

Reads the value of each bit of APSR.GE.

Depending on the value of APSR.GE, assigns the destination register the value of either the first or second operand register.

The behavior is: if ConditionPassed() then

EncodingSpecificOperations();

R[d]<7:0> = if APSR.GE<0> == '1' then R[n]<7:0> else R[m]<7:0>;

R[d]<15:8> = if APSR.GE<1> == '1' then R[n]<15:8> else R[m]<15:8>;

R[d]<23:16> = if APSR.GE<2> == '1' then R[n]<23:16> else R[m]<23:16>;

R[d]<31:24> = if APSR.GE<3> == '1' then R[n]<31:24> else R[m]<31:24>;

Restrictions

None.

Condition flags

These instructions do not change the flags.

3.4.12

SADD16 R0, R1, R2 ; Set GE bits based on result.

SEL R0, R0, R3 ; Select bytes from R0 or R3, based on GE.

SHADD16 and SHADD8

Signed Halving Add 16 and Signed Halving Add 8.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

SHADD16

Signed Halving Add 16.

SHADD8

Signed Halving Add 8.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

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General data processing instructions

Operation

Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register.

The SHADD16 instruction:The SHADD8 instruction:

Adds each halfword from the first operand to the corresponding halfword of the second operand.

Shuffles the result by one bit to the right, halving the data.

Writes the halfword results in the destination register.

Adds each byte of the first operand to the corresponding byte of the second operand.

Shuffles the result by one bit to the right, halving the data.

Writes the byte results in the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

3.4.13

SHADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1 and

; writes halved result to corresponding halfword in R1.

SHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and

; writes halved result to corresponding byte in R4.

SHASX and SHSAX

Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange.

op { cond } { Rd, } Rn , Rm

Where: op

Is one of:

SHASX

Add and Subtract with Exchange and Halving.

SHSAX

Subtract and Add with Exchange and Halving.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

The SHASX instruction:

Adds the top halfword of the first operand with the bottom halfword of the second operand.

Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving.

Subtracts the top halfword of the second operand from the bottom highword of the first operand.

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General data processing instructions

Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving.

The SHSAX instruction:

Subtracts the bottom halfword of the second operand from the top highword of the first operand.

Writes the halfword result of the addition to the bottom halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving.

Adds the bottom halfword of the first operand with the top halfword of the second operand.

Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

3.4.14

SHASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2

; and writes halved result to top halfword of R7.

; Subtracts top halfword of R2 from bottom halfword of

; R4 and writes halved result to bottom halfword of R7.

SHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword

; of R3 and writes halved result to top halfword of R0.

; Adds top halfword of R5 to bottom halfword of R3 and

; writes halved result to bottom halfword of R0.

SHSUB16 and SHSUB8

Signed Halving Subtract 16 and Signed Halving Subtract 8.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

SHSUB16

Signed Halving Subtract 16.

SHSUB8

Signed Halving Subtract 8.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register.

The SHSUB16 instruction: The SHSUBB8 instruction:

Subtracts each halfword of the second operand from the corresponding halfwords of the first operand.

Shuffles the result by one bit to the right, halving the data.

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General data processing instructions

Writes the halved halfword results in the destination register.

Subtracts each byte of the second operand from the corresponding byte of the first operand.

Shuffles the result by one bit to the right, halving the data.

Writes the corresponding signed byte results in the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

3.4.15

SHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword

; of R1 and writes to corresponding halfword of R1.

SHSUB8 R4, R0, R5 ; Subtracts bytes of R0 from corresponding byte in R5,

; and writes to corresponding byte in R4.

SSUB16 and SSUB8

Signed Subtract 16 and Signed Subtract 8.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

SSUB16

Performs two 16-bit signed integer subtractions.

SSUB8

Performs four 8-bit signed integer subtractions.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

Use these instructions to change endianness of data.

The SSUB16 instruction:The SSUB8 instruction:

Subtracts each halfword from the second operand from the corresponding halfword of the first operand.

Writes the difference result of two signed halfwords in the corresponding halfword of the destination register.

Subtracts each byte of the second operand from the corresponding byte of the first operand.

Writes the difference result of four signed bytes in the corresponding byte of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions set the APSR.GE bits according to the results of the subtractions.

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General data processing instructions

3.4.16

For SSUB16 : if ConditionPassed() then

EncodingSpecificOperations();

diff1 = SInt(R[n]<15:0>) - SInt(R[m]<15:0>);

diff2 = SInt(R[n]<31:16>) - SInt(R[m]<31:16>);

R[d]<15:0> = diff1<15:0>;

R[d]<31:16> = diff2<15:0>;

APSR.GE<1:0> = if diff1 >= 0 then '11' else '00';

APSR.GE<3:2> = if diff2 >= 0 then '11' else '00';

For SSUB8 : if ConditionPassed() then

EncodingSpecificOperations();

diff1 = SInt(R[n]<7:0>) - SInt(R[m]<7:0>);

diff2 = SInt(R[n]<15:8>) - SInt(R[m]<15:8>);

diff3 = SInt(R[n]<23:16>) - SInt(R[m]<23:16>);

diff4 = SInt(R[n]<31:24>) - SInt(R[m]<31:24>);

R[d]<7:0> = diff1<7:0>;

R[d]<15:8> = diff2<7:0>;

R[d]<23:16> = diff3<7:0>;

R[d]<31:24> = diff4<7:0>;

APSR.GE<0> = if diff1 >= 0 then '1' else '0';

APSR.GE<1> = if diff2 >= 0 then '1' else '0';

APSR.GE<2> = if diff3 >= 0 then '1' else '0';

APSR.GE<3> = if diff4 >= 0 then '1' else '0';

SSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of R1

; and writes to corresponding halfword of R1.

SSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in

; R0, and writes to corresponding byte of R4.

TST and TEQ

Test bits and Test Equivalence.

TST { cond } Rn , Operand2

TEQ { cond } Rn , Operand2

Where: cond

Operand2

Is an optional condition code.

Is the first operand register.

Is a flexible second operand.

Operation

These instructions test the value in a register against Operand2 . They update the condition flags based on the result, but do not write the result to a register.

The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2 . This is the same as the ANDS instruction, except that it discards the result.

To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0.

The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2 .

This is the same as the EORS instruction, except that it discards the result.

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General data processing instructions

Use the TEQ instruction to test if two values are equal without affecting the V or C flags.

TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands.

Restrictions

Do not use SP and do not use PC.

Condition flags

•

These instructions:

• Update the N and Z flags according to the result.

Can update the C flag during the calculation of

Do not affect the V flag.

Operand2 ,

3.4.17

TST R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,

; APSR is updated but result is discarded

TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to

; value in R9, APSR is updated but result is discarded.

UADD16 and UADD8

Unsigned Add 16 and Unsigned Add 8.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

UADD16

Performs two 16-bit unsigned integer additions.

UADD8

Performs four 8-bit unsigned integer additions.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

Use these instructions to add 16- and 8-bit unsigned data.

The UADD16 instruction:

Adds each halfword from the first operand to the corresponding halfword of the second operand.

Writes the unsigned result in the corresponding halfwords of the destination register.

The UADD8 instruction:

Adds each byte of the first operand to the corresponding byte of the second operand.

Writes the unsigned result in the corresponding byte of the destination register.

Restrictions

Do not use SP and do not use PC.

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General data processing instructions

Condition flags

These instructions set the APSR.GE bits according to the results of the additions.

For UADD16 : if ConditionPassed() then

EncodingSpecificOperations();

sum1 = UInt(R[n]<15:0>) + UInt(R[m]<15:0>);

sum2 = UInt(R[n]<31:16>) + UInt(R[m]<31:16>);

R[d]<15:0> = sum1<15:0>;

R[d]<31:16> = sum2<15:0>;

APSR.GE<1:0> = if sum1 >= 0x10000 then '11' else '00';

APSR.GE<3:2> = if sum2 >= 0x10000 then '11' else '00';

For UADD8 : if ConditionPassed() then

EncodingSpecificOperations();

sum1 = UInt(R[n]<7:0>) + UInt(R[m]<7:0>);

sum2 = UInt(R[n]<15:8>) + UInt(R[m]<15:8>);

sum3 = UInt(R[n]<23:16>) + UInt(R[m]<23:16>);

sum4 = UInt(R[n]<31:24>) + UInt(R[m]<31:24>);

R[d]<7:0> = sum1<7:0>;

R[d]<15:8> = sum2<7:0>;

R[d]<23:16> = sum3<7:0>;

R[d]<31:24> = sum4<7:0>;

APSR.GE<0> = if sum1 >= 0x100 then '1' else '0';

APSR.GE<1> = if sum2 >= 0x100 then '1' else '0';

APSR.GE<2> = if sum3 >= 0x100 then '1' else '0';

APSR.GE<3> = if sum4 >= 0x100 then '1' else '0';

UADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1,

; writes to corresponding halfword of R1.

UADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and writes

; to corresponding byte in R4.

3.4.18

UASX and USAX

Unsigned Add and Subtract with Exchange and Unsigned Subtract and Add with Exchange.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

UASX

Add and Subtract with Exchange.

USAX

Subtract and Add with Exchange.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

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General data processing instructions

3.4.19

Operation

The UASX instruction:

Subtracts the top halfword of the second operand from the bottom halfword of the first operand.

Writes the unsigned result from the subtraction to the bottom halfword of the destination register.

Adds the top halfword of the first operand with the bottom halfword of the second operand.

Writes the unsigned result of the addition to the top halfword of the destination register.

The USAX instruction:

Adds the bottom halfword of the first operand with the top halfword of the second operand.

Writes the unsigned result of the addition to the bottom halfword of the destination register.

Subtracts the bottom halfword of the second operand from the top halfword of the first operand.

Writes the unsigned result from the subtraction to the top halfword of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions set the APSR.GE bits according to the results.

For UASX : if ConditionPassed() then

EncodingSpecificOperations();

diff = UInt(R[n]<15:0>) - UInt(R[m]<31:16>);

sum = UInt(R[n]<31:16>) + UInt(R[m]<15:0>);

R[d]<15:0> = diff<15:0>;

R[d]<31:16> = sum<15:0>;

APSR.GE<1:0> = if diff >= 0 then '11' else '00';

APSR.GE<3:2> = if sum >= 0x10000 then '11' else '00';

For USAX : if ConditionPassed() then

EncodingSpecificOperations();

sum = UInt(R[n]<15:0>) + UInt(R[m]<31:16>);

diff = UInt(R[n]<31:16>) - UInt(R[m]<15:0>);

R[d]<15:0> = sum<15:0>;

R[d]<31:16> = diff<15:0>;

APSR.GE<1:0> = if sum >= 0x10000 then '11' else '00';

APSR.GE<3:2> = if diff >= 0 then '11' else '00';

UASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and

; writes to top halfword of R0.

; Subtracts bottom halfword of R5 from top halfword of R0

; and writes to bottom halfword of R0.

USAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3

; and writes to bottom halfword of R7.

; Adds top halfword of R3 to bottom halfword of R2 and

; writes to top halfword of R7.

UHADD16 and UHADD8

Unsigned Halving Add 16 and Unsigned Halving Add 8.

op { cond } { Rd ,} Rn , Rm

Where:

PM0264 - Rev 1 page 89/245

PM0264

General data processing instructions op

Is one of:

UHADD16

Unsigned Halving Add 16.

UHADD8

Unsigned Halving Add 8.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the register holding the first operand.

Is the register holding the second operand.

Operation

Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the destination register.

The UHADD16 instruction:

Adds each halfword from the first operand to the corresponding halfword of the second operand.

Shuffles the halfword result by one bit to the right, halving the data.

Writes the unsigned results to the corresponding halfword in the destination register.

The UHADD8 instruction:

Adds each byte of the first operand to the corresponding byte of the second operand.

Shuffles the byte result by one bit to the right, halving the data.

Writes the unsigned results in the corresponding byte in the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

3.4.20

UHADD16 R7, R3 ; Adds halfwords in R7 to corresponding halfword of R3

; and writes halved result to corresponding halfword in R7.

UHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and writes

; halved result to corresponding byte in R4.

UHASX and UHSAX

Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange.

op { cond } { Rd ,} Rn , Rm

Where:

PM0264 - Rev 1 page 90/245

PM0264

General data processing instructions op

Is one of:

UHASX

Unsigned Halving Add and Subtract with Exchange.

UHSAX

Unsigned Halving Subtract and Add with Exchange.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

The UHASX instruction:

Adds the top halfword of the first operand with the bottom halfword of the second operand.

Shifts the result by one bit to the right causing a divide by two, or halving.

Writes the halfword result of the addition to the top halfword of the destination register.

Subtracts the top halfword of the second operand from the bottom halfword of the first operand.

Shifts the result by one bit to the right causing a divide by two, or halving.

Writes the halfword result of the subtraction in the bottom halfword of the destination register.

The UHSAX instruction:

Subtracts the bottom halfword of the second operand from the top halfword of the first operand.

Shifts the result by one bit to the right causing a divide by two, or halving.

Writes the halfword result of the subtraction in the top halfword of the destination register.

Adds the bottom halfword of the first operand with the top halfword of the second operand.

Shifts the result by one bit to the right causing a divide by two, or halving.

Writes the halfword result of the addition to the bottom halfword of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

3.4.21

UHASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2

; and writes halved result to top halfword of R7.

; Subtracts top halfword of R2 from bottom halfword of

; R7 and writes halved result to bottom halfword of R7.

UHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of

; R3 and writes halved result to top halfword of R0.

; Adds top halfword of R5 to bottom halfword of R3 and

; writes halved result to bottom halfword of R0.

UHSUB16 and UHSUB8

Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8.

op { cond } { Rd ,} Rn , Rm

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PM0264

General data processing instructions

Where: op

Is one of:

UHSUB16

Performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register.

UHSUB8

Performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register.

The UHSUB16 instruction:

Subtracts each halfword of the second operand from the corresponding halfword of the first operand.

Shuffles each halfword result to the right by one bit, halving the data.

Writes each unsigned halfword result to the corresponding halfwords in the destination register.

The UHSUB8 instruction:

Subtracts each byte of second operand from the corresponding byte of the first operand.

Shuffles each byte result by one bit to the right, halving the data.

Writes the unsigned byte results to the corresponding byte of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

3.4.22

UHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of

; R1 and writes halved result to corresponding halfword in

; R1.

UHSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0 and

; writes halved result to corresponding byte in R4.

USAD8

Unsigned Sum of Absolute Differences.

USAD8{ cond } { Rd ,} Rn , Rm

Where: cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

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General data processing instructions cond

3.4.23

Is the first operand register.

Is the second operand register.

Operation

The USAD8 instruction:

Subtracts each byte of the second operand register from the corresponding byte of the first operand register.

Adds the absolute values of the differences together.

Writes the result to the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

USAD8 R1, R4, R0 ; Subtracts each byte in R0 from corresponding byte of R4

; adds the differences and writes to R1.

USAD8 R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0,

; adds the differences and writes to R0.

USADA8

Unsigned Sum of Absolute Differences and Accumulate.

USADA8{ cond } Rd , Rn , Rm , Ra

Where:

Is an optional condition code.

Is the destination register.

Is the first operand register.

Is the second operand register.

Is the register that contains the accumulation value.

Operation

The USADA8 instruction:

Subtracts each byte of the second operand register from the corresponding byte of the first operand register.

Adds the unsigned absolute differences together.

Adds the accumulation value to the sum of the absolute differences.

Writes the result to the destination register.

Restrictions

Do not use SP and do not use PC.

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PM0264

General data processing instructions

Condition flags

These instructions do not change the flags.

3.4.24

USADA8 R1, R0, R6 ; Subtracts bytes in R0 from corresponding halfword of R1

; adds differences, adds value of R6, writes to R1.

USADA8 R4, R0, R5, R2 ; Subtracts bytes of R5 from corresponding byte in R0

; adds differences, adds value of R2 writes to R4.

USUB16 and USUB8

Unsigned Subtract 16 and Unsigned Subtract 8.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

USUB16

Unsigned Subtract 16.

USUB8

Unsigned Subtract 8.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register.

Operation

Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register.

The USUB16 instruction:

Subtracts each halfword from the second operand register from the corresponding halfword of the first operand register.

Writes the unsigned result in the corresponding halfwords of the destination register.

The USUB8 instruction:

Subtracts each byte of the second operand register from the corresponding byte of the first operand register.

Writes the unsigned byte result in the corresponding byte of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions set the APSR.GE bits according to the results of the subtractions.

For USUB16 :

PM0264 - Rev 1 page 94/245

3.5

PM0264

Multiply and divide instructions if ConditionPassed() then

EncodingSpecificOperations();

diff1 = UInt(R[n]<15:0>) - UInt(R[m]<15:0>);

diff2 = UInt(R[n]<31:16>) - UInt(R[m]<31:16>);

R[d]<15:0> = diff1<15:0>;

R[d]<31:16> = diff2<15:0>;

APSR.GE<1:0> = if diff1 >= 0 then '11' else '00';

APSR.GE<3:2> = if diff2 >= 0 then '11' else '00';

For USUB8 : if ConditionPassed() then

EncodingSpecificOperations();

diff1 = UInt(R[n]<7:0>) - UInt(R[m]<7:0>);

diff2 = UInt(R[n]<15:8>) - UInt(R[m]<15:8>);

diff3 = UInt(R[n]<23:16>) - UInt(R[m]<23:16>);

diff4 = UInt(R[n]<31:24>) - UInt(R[m]<31:24>);

R[d]<7:0> = diff1<7:0>;

R[d]<15:8> = diff2<7:0>;

R[d]<23:16> = diff3<7:0>;

R[d]<31:24> = diff4<7:0>;

APSR.GE<0> = if diff1 >= 0 then '1' else '0';

APSR.GE<1> = if diff2 >= 0 then '1' else '0';

APSR.GE<2> = if diff3 >= 0 then '1' else '0';

APSR.GE<3> = if diff4 >= 0 then '1' else '0';

USUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of R1

; and writes to corresponding halfword in R1.

USUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0 and

; writes to the corresponding byte in R4.

Multiply and divide instructions

Table 35 shows the multiply and divide instructions:

Mnemonic

MLA

MLS

MUL

SDIV

SMLA[B,T]

SMLAD

SMLAL

SMLSD

, SMLADX

SMLAL[B,T]

SMLALD , SMLALDX

SMLAW[B|T]

SMLSLD

Table 35. Multiply and divide instructions

Brief description

Multiply with Accumulate, 32-bit result

Multiply and Subtract, 32-bit result

Multiply, 32-bit result

Signed Divide

Signed Multiply Accumulate (halfwords)

Signed Multiply Accumulate Dual

Signed Multiply with Accumulate (32 × 32 + 64),

64-bit result

Signed Multiply Accumulate Long (halfwords)

Signed Multiply Accumulate Long Dual

Signed Multiply Accumulate (word by halfword)

Signed Multiply Subtract Dual

Signed Multiply Subtract Long Dual

See

Section 3.5.1 MUL, MLA, and MLS

Section 3.5.3 SMLAWB, SMLAWT, SMLABB,

SMLABT, SMLATB, and SMLATT

Section 3.5.4 SMLAD and SMLADX

Section 3.5.11 UMULL, UMAAL, UMLAL, SMULL, and SMLAL

Section 3.5.5 SMLALD, SMLALDX, SMLALBB,

SMLALBT, SMLALTB, and SMLALTT

Section 3.5.5 SMLALD, SMLALDX, SMLALBB,

SMLALBT, SMLALTB, and SMLALTT

Section 3.5.3 SMLAWB, SMLAWT, SMLABB,

SMLABT, SMLATB, and SMLATT

Section 3.5.6 SMLSD and SMLSLD

PM0264 - Rev 1 page 95/245

PM0264

Multiply and divide instructions

3.5.1

cond

Rn, Rm

Mnemonic

SMMLA

SMMLS , SMMLSR

SMMUL , SMMULR

SMUAD , SMUADX

SMUL[B,T]

Brief description

Signed Most Significant Word Multiply Accumulate

Section 3.5.7 SMMLA and SMMLS

Signed Most Significant Word Multiply Subtract

Signed Most Significant Word Multiply

Signed Dual Multiply Add

Signed Multiply (word by halfword)

Section 3.5.8 SMMUL

See

Section 3.5.7 SMMLA and SMMLS

Section 3.5.9 SMUAD and SMUSD

Section 3.5.10 SMUL and SMULW

SMULL Signed Multiply (32 × 32), 64-bit result

Section 3.5.11 UMULL, UMAAL, UMLAL, SMULL, and SMLAL

SMULWB , SMULWT Signed Multiply (word by halfword)

SMUSDX , SMUSD Signed Dual Multiply Subtract

UDIV Unsigned Divide

UMAAL

UMLAL

UMULL

Section 3.5.10 SMUL and SMULW

Section 3.5.9 SMUAD and SMUSD

Section 3.5.11 UMULL, UMAAL, UMLAL, SMULL, and SMLAL

Unsigned Multiply Accumulate Accumulate Long

(32 × 32 + 32 + 32), 64-bit result

Unsigned Multiply with Accumulate (32 × 32 + 64),

64-bit result

Unsigned Multiply (32 × 32), 64-bit result

MUL, MLA, and MLS

Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32 ‑ bit operands, and producing a 32-bit result.

MUL{S} { cond } { Rd ,} Rn , Rm ; Multiply

MLA { cond } Rd , Rn , Rm , Ra ; Multiply with accumulate

MLS { cond } Rd , Rn , Rm , Ra ; Multiply with subtract

Where:

Is an optional condition code.

Is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

Is the destination register. If Rd is omitted, the destination register is Rn .

Are registers holding the values to be multiplied.

Is a register holding the value to be added or subtracted from.

Operation

The MUL instruction multiplies the values from Rn and Rm , and places the least significant 32 bits of the result in

Rd .

The MLA instruction multiplies the values from Rn and Rm , adds the value from Ra , and places the least significant 32 bits of the result in Rd .

The MLS instruction multiplies the values from Rn and Rm , subtracts the product from the value from Ra , and places the least significant 32 bits of the result in Rd .

The results of these instructions do not depend on whether the operands are signed or unsigned.

Restrictions

In these instructions, do not use SP and do not use PC.

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PM0264

Multiply and divide instructions cond

3.5.2

3.5.3

If you use the S suffix with the MUL instruction:

• Rd , Rn , and Rm must all be in the range R0 R7 .

• Rd must be the same as Rm .

• You must not use the cond suffix.

Condition flags

The MLA instruction and MULS instructions:

• Only MULS instruction updates the N and Z flags according to the result.

• No other MUL, MLA, or MLS instruction affects the condition flags.

MUL R10, R2, R5 ; Multiply, R10 = R2 × R5

MLA R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 × R1) + R5

MULS R0, R2, R2 ; Multiply with flag update, R0 = R2 × R2

MULLT R2, R3, R2 ; Conditionally multiply, R2 = R3 × R2

MLS R4, R5, R6, R7 ; Multiply with subtract, R4 = R7 - (R5 × R6)

SDIV and UDIV

Signed Divide and Unsigned Divide.

SDIV { cond } { Rd ,} Rn , Rm

UDIV { cond } { Rd ,} Rn, Rm

Where:

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the register holding the value to be divided.

Is a register holding the divisor.

Operation

The SDIV instruction performs a signed integer division of the value in Rn by the value in Rm .

The UDIV instruction performs an unsigned integer division of the value in Rn by the value in Rm .

For both instructions, if the value in Rn is not divisible by the value in Rm , the result is rounded towards zero.

For the Cortex ‑ M33 processor, the integer divide operation latency is in the range of 2-11 cycles.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4

UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1

SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT

Signed Multiply Accumulate (halfwords).

op { cond } Rd , Rn , Rm , Ra

Where:

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PM0264

Multiply and divide instructions op

Is one of:

SMLAWB

Signed Multiply Accumulate (word by halfword)

The bottom halfword, bits [15:0], of Rm is used.

SMLAWT

Signed Multiply Accumulate (word by halfword)

The top halfword, bits [31:16] of Rm is used.

SMLABB , SMLABT

Signed Multiply Accumulate Long (halfwords)

The bottom halfword, bits [15:0], of Rm is used.

SMLATB , SMLATT

Signed Multiply Accumulate Long (halfwords)

The top halfword, bits [31:16] of Rm is used.

cond

Is an optional condition code.

Is the destination register.

Rn, Rm

Are registers holding the values to be multiplied.

Is a register holding the value to be added or subtracted from.

Operation

•

The SMLABB , SMLABT , SMLATB , SMLATT instructions:

• Multiply the specified signed halfword, top or bottom, values from Rn and Rm .

Add the value in Ra to the resulting 32-bit product.

Write the result of the multiplication and addition in Rd .

The non-specified halfwords of the source registers are ignored.

•

The SMLAWB and SMLAWT instructions:

• Multiply the 32-bit signed values in Rn with:

– The top signed halfword of Rm , T instruction suffix.

– The bottom signed halfword of Rm , B instruction suffix.

Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product

Write the result of the multiplication and addition in Rd .

The bottom 16 bits of the 48-bit product are ignored.

If overflow occurs during the addition of the accumulate value, the SMLAWB , SMLAWT , instruction sets the Q flag in the APSR. No overflow can occur during the multiplication.

Restrictions

In these instructions, do not use SP and do not use PC.

Condition flags

If an overflow is detected, the Q flag is set.

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Multiply and divide instructions

3.5.4

SMLABB R5, R6, R4, R1 ; Multiplies bottom halfwords of R6 and R4, adds

; R1 and writes to R5.

SMLATB R5, R6, R4, R1 ; Multiplies top halfword of R6 with bottom halfword

; of R4, adds R1 and writes to R5.

SMLATT R5, R6, R4, R1 ; Multiplies top halfwords of R6 and R4, adds

; R1 and writes the sum to R5.

SMLABT R5, R6, R4, R1 ; Multiplies bottom halfword of R6 with top halfword

; of R4, adds R1 and writes to R5.

SMLABT R4, R3, R2 ; Multiplies bottom halfword of R4 with top halfword of

; R3, adds R2 and writes to R4.

SMLAWB R10, R2, R5, R3 ; Multiplies R2 with bottom halfword of R5, adds

; R3 to the result and writes top 32-bits to R10.

SMLAWT R10, R2, R1, R5 ; Multiplies R2 with top halfword of R1, adds R5

; and writes top 32-bits to R10.

SMLAD and SMLADX

Signed Multiply Accumulate Long Dual, Signed Multiply Accumulate Long Dual exchange.

op {X}{ cond } Rd , Rn , Rm , Ra

Where: op

Is one of:

SMLAD

Signed Multiply Accumulate Long Dual.

SMLADX

Signed Multiply Accumulate Long Dual exchange.

X specifies which halfword of the source register Rn is used as the multiply operand.

If X is omitted, the multiplications are bottom × bottom and top × top.

If X is present, the multiplications are bottom × top and top × bottom.

cond

Is an optional condition code.

Is the destination register.

Is the first operand register holding the values to be multiplied.

Is the second operand register.

Is the accumulate value.

Operation

The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values.

The SMLAD instruction:

Multiplies the top signed halfword value in Rn with the top signed halfword of Rm and the bottom signed halfword value in Rn with the bottom signed halfword of Rm .

Adds both multiplication results to the signed 32-bit value in Ra .

Writes the 32-bit signed result of the multiplication and addition to Rd .

The SMLADX instruction:

Multiplies the top signed halfword value in Rn with the bottom signed halfword of Rm and the bottom signed halfword value in Rn with the top signed halfword of Rm .

Adds both multiplication results to the signed 32-bit value in Ra .

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Multiply and divide instructions

Writes the 32-bit signed result of the multiplication and addition to Rd .

Restrictions

Do not use SP and do not use PC.

Condition flags

Sets the Q flag if the accumulate operation overflows.

3.5.5

SMLAD R10, R2, R1, R5 ; Multiplies two halfword values in R2 with

; corresponding halfwords in R1, adds R5 and writes to

; R10.

SMLALDX R0, R2, R4, R6 ; Multiplies top halfword of R2 with bottom halfword

; of R4, multiplies bottom halfword of R2 with top

; halfword of R4, adds R6 and writes to R0.

SMLALD, SMLALDX, SMLALBB, SMLALBT, SMLALTB, and SMLALTT

Signed Multiply Accumulate Long Dual and Signed Multiply Accumulate Long (halfwords).

op { cond } RdLo , RdHi , Rn , Rm

Where: op

Is one of:

SMLALBB , SMLALBT

Signed Multiply Accumulate Long (halfwords, B and T ).

B and T specify which halfword of the source registers Rn and Rm are used as the first and second multiply operand:

The bottom halfword, bits [15:0], of Rn is used.

SMLALBB : the bottom halfword, bits [15:0], of Rm is used. SMLALBT : the top halfword, bits [31:16], of Rm is used.

SMLALTB , SMLALTT

Signed Multiply Accumulate Long (halfwords, B and T ).

The top halfword, bits [31:16], of Rn is used.

SMLALTB : the bottom halfword, bits [15:0], of Rm is used. SMLALTT : the top halfword, bits [31:16], of Rm is used.

SMLALD

Signed Multiply Accumulate Long Dual.

The multiplications are bottom × bottom and top × top.

SMLALDX

Signed Multiply Accumulate Long Dual reversed.

The multiplications are bottom × top and top × bottom.

cond

Is an optional condition code.

RdHi, RdLo

Are the destination registers. RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer. The accumulating value for the lower and upper 32 bits are held in the RdLo and RdHi registers respectively.

Rn, Rm

Are registers holding the first and second operands.

•

Operation

Multiplies the two’s complement signed word values from Rn and Rm .

Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product.

Writes the 64-bit result of the multiplication and addition in RdLo and RdHi .

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Multiply and divide instructions

3.5.6

The SMLALBB , SMLALBT , SMLALTB and SMLALTT instructions:

• Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm .

• Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi .

• Writes the 64-bit result of the multiplication and addition in RdLo and RdHi .

The non-specified halfwords of the source registers are ignored.

The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement signed 16-bit integers. These instructions:

• SMLALD multiplies the top signed halfword value of Rn with the top signed halfword of signed halfword values of Rn with the bottom signed halfword of Rm .

Rm and the bottom

•

SMLALDX multiplies the top signed halfword value of Rn with the bottom signed halfword of Rm and the bottom signed halfword values of Rn with the top signed halfword of Rm .

Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit product.

Write the 64-bit product in RdLo and RdHi .

Restrictions

In these instructions:

• Do not use SP and do not use PC.

• RdHi and RdLo must be different registers.

Condition flags

These instructions do not affect the condition code flags.

SMLALBT R2, R1, R6, R7 ; Multiplies bottom halfword of R6 with top

; halfword of R7, sign extends to 32-bit, adds

; R1:R2 and writes to R1:R2.

SMLALTB R2, R1, R6, R7 ; Multiplies top halfword of R6 with bottom

; halfword of R7,sign extends to 32-bit, adds R1:R2

; and writes to R1:R2.

SMLALD R6, R8, R5, R1 ; Multiplies top halfwords in R5 and R1 and bottom

; halfwords of R5 and R1, adds R8:R6 and writes to

; R8:R6.

SMLALDX R6, R8, R5, R1 ; Multiplies top halfword in R5 with bottom

; halfword of R1, and bottom halfword of R5 with

; top halfword of R1, adds R8:R6 and writes to

; R8:R6.

SMLSD and SMLSLD

Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual.

op {X}{ cond } Rd , Rn , Rm , Ra ; SMLSD op {X}{ cond } RdLo , RdHi , Rn , Rm ; SMLSLD

Where:

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Multiply and divide instructions cond

Rn, Rm

RdLo op

Is one of:

SMLSD

Signed Multiply Subtract Dual.

SMLSDX

Signed Multiply Subtract Dual reversed.

SMLSLD

Signed Multiply Subtract Long Dual.

SMLSLDX

Signed Multiply Subtract Long Dual reversed.

RdHi

If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top.

Is an optional condition code.

Is the destination register.

Are registers holding the first and second operands.

Is the register holding the accumulate value.

Supplies the lower 32 bits of the accumulate value, and is the destination register for the lower 32 bits of the result.

Supplies the upper 32 bits of the accumulate value, and is the destination register for the upper 32 bits of the result.

Operation

•

The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This instruction:

Optionally rotates the halfwords of the second operand.

Performs two signed 16 × 16-bit halfword multiplications.

Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.

Adds the signed accumulate value to the result of the subtraction.

Writes the result of the addition to the destination register.

•

The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords. This instruction:

• Optionally rotates the halfwords of the second operand.

•

Performs two signed 16 × 16-bit halfword multiplications.

Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.

Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.

Writes the 64-bit result of the addition to the RdHi and RdLo .

Restrictions

In these instructions:

• Do not use SP and do not use PC.

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Multiply and divide instructions

Condition flags

The SMLSD{X} instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction.

For the T32 instruction set, these instructions do not affect the condition code flags.

3.5.7

SMLSD R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom

; halfword of R5, multiplies top halfword of R4

; with top halfword of R5, subtracts second from

; first, adds R6, writes to R0.

SMLSDX R1, R3, R2, R0 ; Multiplies bottom halfword of R3 with top

; halfword of R2, multiplies top halfword of R3

; with bottom halfword of R2, subtracts second from

; first, adds R0, writes to R1.

SMLSLD R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with bottom

; halfword of R2, multiplies top halfword of R6

; with top halfword of R2, subtracts second from

; first, adds R6:R3, writes to R6:R3.

SMLSLDX R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with top

; halfword of R2, multiplies top halfword of R6

; with bottom halfword of R2, subtracts second from

; first, adds R6:R3, writes to R6:R3.

SMMLA and SMMLS

Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract.

op {R}{ cond } Rd , Rn , Rm , Ra

Where: op

Is one of:

SMMLA

Signed Most Significant Word Multiply Accumulate.

SMMLS

Signed Most Significant Word Multiply Subtract.

If R is present, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the top halfword is extracted.

cond

Is an optional condition code.

Is the destination register.

Rn, Rm

Are registers holding the first and second multiply operands.

Is the register holding the accumulate value.

Operation

The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words.

The SMMLA instruction:

•

Multiplies the values in Rn and Rm .

Optionally rounds the result by adding 0x80000000.

• Extracts the most significant 32 bits of the result.

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Multiply and divide instructions

•

Adds the value of Ra to the signed extracted value.

Writes the result of the addition in Rd .

The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words.

•

The SMMLS instruction:

• Multiplies the values in Rn and Rm .

•

Optionally rounds the result by adding 0x80000000.

Extracts the most significant 32 bits of the result.

Subtracts the extracted value of the result from the value in Ra .

• Writes the result of the subtraction in Rd .

Restrictions

In these instructions:

• Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

SMMLA R0, R4, R5, R6 ; Multiplies R4 and R5, extracts top 32 bits, adds

; R6, truncates and writes to R0.

SMMLAR R6, R2, R1, R4 ; Multiplies R2 and R1, extracts top 32 bits, adds

; R4, rounds and writes to R6.

SMMLSR R3, R6, R2, R7 ; Multiplies R6 and R2, extracts top 32 bits,

; subtracts R7, rounds and writes to R3.

SMMLS R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits,

; subtracts R8, truncates and writes to R4.

3.5.8

SMMUL

Signed Most Significant Word Multiply.

op {R}{ cond } Rd , Rn , Rm

Where: op

Is one of:

SMMUL

Signed Most Significant Word Multiply.

If R is present, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the top halfword is extracted.

cond

Is an optional condition code.

Is the destination register.

Rn, Rm

Are registers holding the first and second operands.

Operation

•

The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The

SMMUL instruction:

• Multiplies the values from Rn and Rm .

Optionally rounds the result, otherwise truncates the result.

Writes the most significant signed 32 bits of the result in Rd .

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Multiply and divide instructions

Restrictions

In this instruction:

• Do not use SP and do not use PC.

Condition flags

This instruction does not affect the condition code flags.

3.5.9

SMMUL R0, R4, R5 ; Multiplies R4 and R5, truncates top 32 bits

; and writes to R0.

SMMULR R6, R2 ; Multiplies R6 and R2, rounds the top 32 bits

; and writes to R6.

SMUAD and SMUSD

Signed Dual Multiply Add and Signed Dual Multiply Subtract.

op {X}{ cond } Rd , Rn , Rm

Where: op

Is one of:

SMUAD

Signed Dual Multiply Add.

SMUADX

Signed Dual Multiply Add reversed.

SMUSD

Signed Dual Multiply Subtract.

SMUSDX

Signed Dual Multiply Subtract reversed.

If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top.

cond

Is an optional condition code.

Is the destination register.

Rn, Rm

Are registers holding the first and the second operands.

Operation

•

The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each operand. This instruction:

Optionally rotates the halfwords of the second operand.

Performs two signed 16 × 16-bit multiplications.

Adds the two multiplication results together.

Writes the result of the addition to the destination register.

•

The SMUSD instruction interprets the values from the first and second operands as two’s complement signed integers. This instruction:

Optionally rotates the halfwords of the second operand.

Performs two signed 16 × 16-bit multiplications.

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Multiply and divide instructions

3.5.10

op cond

Rn, Rm

•

Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.

Writes the result of the subtraction to the destination register.

Restrictions

In these instructions:

• Do not use SP and do not use PC.

Condition flags

SMUAD , SMUADX set the Q flag if the addition overflows. The multiplications cannot overflow.

SMUAD R0, R4, R5 ; Multiplies bottom halfword of R4 with the bottom

; halfword of R5, adds multiplication of top halfword

; of R4 with top halfword of R5, writes to R0.

SMUADX R3, R7, R4 ; Multiplies bottom halfword of R7 with top halfword

; of R4, adds multiplication of top halfword of R7

; with bottom halfword of R4, writes to R3.

SMUSD R3, R6, R2 ; Multiplies bottom halfword of R4 with bottom halfword

; of R6, subtracts multiplication of top halfword of R6

; with top halfword of R3, writes to R3.

SMUSDX R4, R5, R3 ; Multiplies bottom halfword of R5 with top halfword of

; R3, subtracts multiplication of top halfword of R5

; with bottom halfword of R3, writes to R4.

SMUL and SMULW

Signed Multiply (halfwords) and Signed Multiply (word by halfword).

op { XY }{ cond } Rd , Rn , Rm ; SMUL op { Y }{ cond } Rd . Rn , Rm ; SMULW

For SMUL{ XY } only:

Is one of SMULBB , SMULBT , SMULTB , SMULTT :

SMUL{ XY } Signed Multiply (halfwords)

X and Y specify which halfword of the source registers Rn and Rm is used as the first and second multiply operand. If X is B , then the bottom halfword, bits [15:0] of Rn is used. If X is T , then the top halfword, bits [31:16] of Rn is used. If Y is B , then the bottom halfword, bits [15:0], of Rm is used. If Y is T , then the top halfword, bits

[31:16], of Rm is used.

SMULW{ Y } Signed Multiply (word by halfword)

Y specifies which halfword of the source register Rm is used as the second multiply operand. If Y is B , then the bottom halfword (bits [15:0]) of Rm is used. If Y is T , then the top halfword (bits [31:16]) of Rm is used.

Is an optional condition code.

Is the destination register.

Are registers holding the first and second operands.

Operation

The SMULBB , SMULTB , SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed 16bit integers.

These instructions:

• Multiply the specified signed halfword, Top or Bottom, values from Rn and Rm .

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Multiply and divide instructions

• Write the 32-bit result of the multiplication in Rd.

•

The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two halfword 16-bit signed integers. These instructions:

Multiply the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.

Write the signed most significant 32 bits of the 48-bit result in the destination register.

Restrictions

In these instructions:

• Do not use SP and do not use PC.

• RdHi and RdLo must be different registers.

3.5.11

SMULBT R0, R4, R5 ; Multiplies the bottom halfword of R4 with the

; top halfword of R5, multiplies results and

; writes to R0.

SMULBB R0, R4, R5 ; Multiplies the bottom halfword of R4 with the

; bottom halfword of R5, multiplies results and

; writes to R0.

SMULTT R0, R4, R5 ; Multiplies the top halfword of R4 with the top

; halfword of R5, multiplies results and writes

; to R0.

SMULTB R0, R4, R5 ; Multiplies the top halfword of R4 with the

; bottom halfword of R5, multiplies results and

; and writes to R0.

SMULWT R4, R5, R3 ; Multiplies R5 with the top halfword of R3,

; extracts top 32 bits and writes to R4.

SMULWB R4, R5, R3 ; Multiplies R5 with the bottom halfword of R3,

; extracts top 32 bits and writes to R4.

UMULL, UMAAL, UMLAL, SMULL, and SMLAL

Signed and Unsigned Multiply Long, with optional Accumulate, using 32 ‑ bit operands and producing a 64 ‑ bit result.

op { cond } RdLo , RdHi , Rn , Rm

Where: op

Is one of:

UMULL

Unsigned Multiply Long.

UMLAL

Unsigned Multiply, with Accumulate Long.

UMAAL

Unsigned Long Multiply with Accumulate Accumulate.

SMULL

Signed Multiply Long.

SMLAL

Signed Multiply, with Accumulate Long.

cond

Is an optional condition code.

RdHi, RdLo

Are the destination registers. For UMLAL and SMLAL they also hold the accumulating value of the lower and upper words respectively.

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Saturating instructions

Rn, Rm

3.6

Are registers holding the operands.

Operation

The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo , and the most significant 32 bits of the result in RdHi .

The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64 ‑ bit result to the 64 ‑ bit unsigned integer contained in RdHi and RdLo , and writes the result back to

RdHi and RdLo .

The UMAAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication, adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition, writes the top 32-bits of the result to RdHi and writes the lower 32-bits of the result to RdLo .

The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo , and the most significant 32 bits of the result in RdHi .

The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64 ‑ bit result to the 64 ‑ bit signed integer contained in RdHi and RdLo , and writes the result back to RdHi and RdLo .

Restrictions

In these instructions:

• Do not use SP and do not use PC.

• RdHi and RdLo must be different registers.

Condition flags

These instructions do not affect the condition code flags.

UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 × R6

SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 × R8

Saturating instructions

Table 36 shows the saturating instructions:

Mnemonic

QADD

QASX

QDADD

QDSUB

QSAX

QSUB

QSUB16

SSAT

SSAT16

UQADD16

UQADD8

Table 36. Saturating instructions

Brief description

Saturating Add

Saturating Add and Subtract with Exchange

Saturating Double and Add

Saturating Double and Subtract

Saturating Subtract and Add with Exchange

Saturating Subtract

Saturating Subtract 16

Signed Saturate

Signed Saturate Halfword

Unsigned Saturating Add 16

Unsigned Saturating Add 8

See

Section 3.6.5 QDADD and QDSUB

Section 3.6.2 SSAT16 and USAT16

Section 3.6.7 UQADD and UQSUB

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Saturating instructions

Mnemonic

UQASX

UQSAX

UQSUB16

UQSUB8

USAT

USAT16

Brief description

Unsigned Saturating Add and Subtract with Exchange

Unsigned Saturating Subtract and Add with Exchange

Unsigned Saturating Subtract 16

Unsigned Saturating Subtract 8

Unsigned Saturate

Unsigned Saturate Halfword

See

Section 3.6.6 UQASX and UQSAX

Section 3.6.7 UQADD and UQSUB

Section 3.6.2 SSAT16 and USAT16

3.6.1

For signed n -bit saturation, this means that:

• If the value to be saturated is less than −2 n−1 , the result returned is −2 n-1

• If the value to be saturated is greater than 2 n−1 −1, the result returned is 2 n-1 −1

• Otherwise, the result returned is the same as the value to be saturated.

•

For unsigned n -bit saturation, this means that:

• If the value to be saturated is less than 0, the result returned is 0

If the value to be saturated is greater than 2 n −1, the result returned is 2 n −1

Otherwise, the result returned is the same as the value to be saturated.

If the returned result is different from the value to be saturated, it is called saturation . If saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, you must use the MSR instruction.

To read the state of the Q flag, use the MRS instruction.

SSAT and USAT

Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.

op { cond } Rd , # n , Rm {, shift #s}

Where: op

Is one of:

SSAT

Saturates a signed value to a signed range.

USAT

Saturates a signed value to an unsigned range.

cond

Is an optional condition code.

Is the destination register.

Specifies the bit position to saturate to:

• n ranges from 1 to 32 for SSAT .

• n ranges from 0 to 31 for USAT .

Is the register containing the value to saturate.

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Saturating instructions shift #s

Is an optional shift applied to Rm before saturating. It must be one of the following:

ASR #s where s is in the range 1-31.

LSL #s where s is in the range 0-31.

Operation

These instructions saturate to a signed or unsigned n -bit value.

The SSAT instruction applies the specified shift, then saturates to the signed range −2 n –1 ≤ x ≤ 2 n –1 −1.

The USAT instruction applies the specified shift, then saturates to the unsigned range 0 ≤ x ≤ 2 n −1.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

If saturation occurs, these instructions set the Q flag to 1.

3.6.2

SSAT R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then

; saturate it as a signed 16-bit value and

; write it back to R7.

USATNE R0, #7, R5 ; Conditionally saturate value in R5 as an

; unsigned 7 bit value and write it to R0.

SSAT16 and USAT16

Signed Saturate and Unsigned Saturate to any bit position for two halfwords.

op { cond } Rd , # n , Rm

Where: op

Is one of:

SSAT16

Saturates a signed halfword value to a signed range.

USAT16

Saturates a signed halfword value to an unsigned range.

cond

Is an optional condition code.

Is the destination register.

Specifies the bit position to saturate to:

•

• n ranges from 1 to 16 for SSAT n ranges from 0 to 15 for USAT .

Is the register containing the values to saturate.

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Saturating instructions

Operation

The SSAT16 instruction:

Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit position in n .

Writes the results as two signed 16-bit halfwords to the destination register.

The USAT16 instruction:

Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit position in n .

Writes the results as two unsigned halfwords in the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

If saturation occurs, these instructions set the Q flag to 1.

3.6.3

SSAT16 R7, #9, R2 ; Saturates the top and bottom highwords of R2

; as 9-bit values, writes to corresponding halfword

; of R7.

USAT16NE R0, #13, R5 ; Conditionally saturates the top and bottom

; halfwords of R5 as 13-bit values, writes to

; corresponding halfword of R0.

QADD and QSUB

Saturating Add and Saturating Subtract, signed.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

QADD

Saturating 32-bit add.

QADD8

Saturating four 8-bit integer additions.

QADD16

Saturating two 16-bit integer additions.

QSUB

Saturating 32-bit subtraction.

QSUB8

Saturating four 8-bit integer subtraction.

QSUB16

Saturating two 16-bit integer subtraction.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

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Saturating instructions

Rn, Rm

Are registers holding the first and second operands.

Operation

These instructions add or subtract two, four or eight values from the first and second operands and then writes a signed saturated value in the destination register.

The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed range −2 n –1

≤ x ≤ 2 n –1

−1, where x is given by the number of bits applied in the instruction, 32, 16 or 8.

If the returned result is different from the value to be saturated, it is called saturation . If saturation occurs, the

QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit and 16-bit QADD and QSUB instructions always leave the Q flag unchanged.

To clear the Q flag to 0, you must use the MSR instruction.

To read the state of the Q flag, use the MRS instruction.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

If saturation occurs, the QADD and QSUB instructions set the Q flag to 1.

3.6.4

QADD16 R7, R4, R2 ; Adds halfwords of R4 with corresponding halfword of

; R2, saturates to 16 bits and writes to corresponding

; halfword of R7.

QADD8 R3, R1, R6 ; Adds bytes of R1 to the corresponding bytes of R6,

; saturates to 8 bits and writes to corresponding byte of

; R3.

QSUB16 R4, R2, R3 ; Subtracts halfwords of R3 from corresponding halfword

; of R2, saturates to 16 bits, writes to corresponding

; halfword of R4.

QSUB8 R4, R2, R5 ; Subtracts bytes of R5 from the corresponding byte in

; R2, saturates to 8 bits, writes to corresponding byte of

; R4.

QASX and QSAX

Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

QASX

Add and Subtract with Exchange and Saturate.

QSAX

Subtract and Add with Exchange and Saturate.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

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Saturating instructions

Rn, Rm

Are registers holding the first and second operands.

Operation

The QASX instruction:

Adds the top halfword of the source operand with the bottom halfword of the second operand.

Subtracts the top halfword of the second operand from the bottom highword of the first operand.

Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register.

Saturates the results of the sum and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.

The QSAX instruction:

Subtracts the bottom halfword of the second operand from the top highword of the first operand.

Adds the bottom halfword of the source operand with the top halfword of the second operand.

Saturates the results of the sum and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register.

Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

3.6.5

QASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2,

; saturates to 16 bits, writes to top halfword of R7

; Subtracts top highword of R2 from bottom halfword of

; R4, saturates to 16 bits and writes to bottom halfword

; of R7

QSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of

; R3, saturates to 16 bits, writes to top halfword of R0

; Adds bottom halfword of R3 to top halfword of R5,

; saturates to 16 bits, writes to bottom halfword of R0.

QDADD and QDSUB

Saturating Double and Add and Saturating Double and Subtract, signed.

op { cond } { Rd }, Rm , Rn

Where: op

Is one of:

QDADD

Saturating Double and Add.

QDSUB

Saturating Double and Subtract.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

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Saturating instructions

Rm, Rn

Are registers holding the first and second operands.

Operation

•

The QDADD instruction:

• Doubles the second operand value.

Adds the result of the doubling to the signed saturated value in the first operand.

Writes the result to the destination register.

•

The QDSUB instruction:

• Doubles the second operand value.

Subtracts the doubled value from the signed saturated value in the first operand.

Writes the result to the destination register.

Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range –

231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR.

Restrictions

Do not use SP and do not use PC.

Condition flags

If saturation occurs, these instructions set the Q flag to 1.

3.6.6

QDADD R7, R4, R2 ; Doubles and saturates R4 to 32 bits, adds R2,

; saturates to 32 bits, writes to R7

QDSUB R0, R3, R5 ; Subtracts R3 doubled and saturated to 32 bits

; from R5, saturates to 32 bits, writes to R0.

UQASX and UQSAX

Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned.

op { cond } { Rd ,} Rn , Rm

Where: type

Is one of:

UQASX

Add and Subtract with Exchange and Saturate.

UQSAX

Subtract and Add with Exchange and Saturate.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Rn, Rm

Are registers holding the first and second operands.

Operation

The UQASX instruction:

Adds the bottom halfword of the source operand with the top halfword of the second operand.

Subtracts the bottom halfword of the second operand from the top highword of the first operand.

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Saturating instructions

Saturates the results of the sum and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.

Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register.

The UQSAX instruction:

Subtracts the bottom halfword of the second operand from the top highword of the first operand.

Adds the bottom halfword of the first operand with the top halfword of the second operand.

Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.

Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

3.6.7

UQASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2,

; saturates to 16 bits, writes to top halfword of R7

; Subtracts top halfword of R2 from bottom halfword of

; R4, saturates to 16 bits, writes to bottom halfword of R7

UQSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of R3,

; saturates to 16 bits, writes to top halfword of R0

; Adds bottom halfword of R4 to top halfword of R5

; saturates to 16 bits, writes to bottom halfword of R0.

UQADD and UQSUB

Saturating Add and Saturating Subtract Unsigned.

op { cond } { Rd ,} Rn , Rm

Where: op

Is one of:

UQADD8

Saturating four unsigned 8-bit integer additions.

UQADD16

Saturating two unsigned 16-bit integer additions.

UQSUB8

Saturating four unsigned 8-bit integer subtractions.

UQSUB16

Saturating two unsigned 16-bit integer subtractions.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Rn, Rm

Are registers holding the first and second operands.

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Packing and unpacking instructions

3.7

Operation

•

These instructions add or subtract two or four values and then writes an unsigned saturated value in the destination register.

The UQADD16 instruction:

Adds the respective top and bottom halfwords of the first and second operands.

Saturates the result of the additions for each halfword in the destination register to the unsigned range 0 ≤ x

≤ 2 16 −1, where x is 16.

The UQADD8 instruction:

• Adds each respective byte of the first and second operands.

• Saturates the result of the addition for each byte in the destination register to the unsigned range 0 ≤ x ≤

2 8 −1, where x is 8.

The UQSUB16 instruction:

• Subtracts both halfwords of the second operand from the respective halfwords of the first operand.

• Saturates the result of the differences in the destination register to the unsigned range 0 ≤ x ≤ 2

−1, where x is 16.

The UQSUB8 instructions:

• Subtracts the respective bytes of the second operand from the respective bytes of the first operand.

• Saturates the results of the differences for each byte in the destination register to the unsigned range 0 ≤ x ≤

2 8 −1, where x is 8.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the condition code flags.

UQADD16 R7, R4, R2 ; Adds halfwords in R4 to corresponding halfword in R2,

; saturates to 16 bits, writes to corresponding halfword

; of R7

UQADD8 R4, R2, R5 ; Adds bytes of R2 to corresponding byte of R5, saturates

; to 8 bits, writes to corresponding bytes of R4

UQSUB16 R6, R3, R0 ; Subtracts halfwords in R0 from corresponding halfword

; in R3, saturates to 16 bits, writes to corresponding

; halfword in R6

UQSUB8 R1, R5, R6 ; Subtracts bytes in R6 from corresponding byte of R5,

; saturates to 8 bits, writes to corresponding byte of R1.

Packing and unpacking instructions

Table 37 shows the instructions that operate on packing and unpacking data:

Mnemonic

PKH

SXTAB

SXTAB16

SXTAH

SXTB

Table 37. Packing and unpacking instructions

Brief description

Pack Halfword

Extend 8 bits to 32 and add

Dual extend 8 bits to 16 and add

Extend 16 bits to 32 and add

Sign extend a byte

See

Section 3.7.1 PKHBT and PKHTB

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Packing and unpacking instructions

Mnemonic

SXTB16

SXTH

UXTAB

UXTAB16

UXTAH

UXTB

UXTB16

UXTH

Brief description

Dual extend 8 bits to 16 and add

Sign extend a halfword

Extend 8 bits to 32 and add

Dual extend 8 bits to 16 and add

Extend 16 bits to 32 and add

Zero extend a byte

Dual zero extend 8 bits to 16 and add

Zero extend a halfword

See

Table 38 shows the instructions that operate on adjacent sets of bits in registers or bit fields:

3.7.1

PKHBT and PKHTB

Pack Halfword.

op { cond } { Rd }, Rn , Rm {, LSL # imm } ;PKHBT op { cond } { Rd }, Rn , Rm {, ASR # imm } ;PKHTB

Where: op

Is one of:

PKHBT

Pack Halfword, bottom and top with shift.

PKHTB

Pack Halfword, top and bottom with shift.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the second operand register holding the value to be optionally shifted.

imm

Is the shift length. The type of shift length depends on the instruction:For PKHBT :

For PKHTB :

LSL

A left shift with a shift length from 1 to 31, 0 means no shift.

ASR

An arithmetic shift right with a shift length from 1 to 32, a shift of 32-bits is encoded as 0b00000.

Operation

The PKHBT instruction:

Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register.

If shifted, the shifted value of the second operand is written to the top halfword of the destination register.

The PKHTB instruction:

Writes the value of the top halfword of the first operand to the top halfword of the destination register.

If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register.

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Packing and unpacking instructions

Restrictions

Rd must not be SP and must not be PC.

Condition flags

This instruction does not change the flags.

PKHBT R3, R4, R5 LSL #0 ; Writes bottom halfword of R4 to bottom halfword of

; R3, writes top halfword of R5, unshifted, to top

; halfword of R3

PKHTB R4, R0, R2 ASR #1 ; Writes R2 shifted right by 1 bit to bottom halfword

; of R4, and writes top halfword of R0 to top

; halfword of R4.

3.7.2

SXTA and UXTA

Signed and Unsigned Extend and Add.

op { cond } { Rd ,} Rn , Rm {, ROR # n }

Where: op

Is one of:

SXTAB

Sign extends an 8 ‑ bit value to a 32 ‑ bit value and add.

SXTAH

Sign extends a 16 ‑ bit value to a 32 ‑ bit value and add.

SXTAB16

Sign extends two 8-bit values to two 16-bit values and add.

UXTAB

Zero extends an 8 ‑ bit value to a 32 ‑ bit value and add.

UXTAH

Zero extends a 16 ‑ bit value to a 32 ‑ bit value and add.

UXTAB16

Zero extends two 8-bit values to two 16-bit values and add.

cond

Is an optional condition code.

Is the destination register. If Rd is omitted, the destination register is Rn .

Is the first operand register.

Is the register holding the value to rotate and extend.

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Packing and unpacking instructions

ROR #n

Is one of:

ROR #8

Value from Rm is rotated right 8 bits.

ROR #16

Value from Rm is rotated right 16 bits.

ROR #24

Value from Rm is rotated right 24 bits.

If ROR # n is omitted, no rotation is performed.

Operation

These instructions do the following:

Rotate the value from Rm right by 0, 8, 16 or 24 bits.

Extract bits from the resulting value:

– SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits.

– UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits.

– SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits.

– UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits.

– SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits, and extracts bits [23:16] from Rm and sign extends to 16 bits.

– UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits, and extracts bits [23:16] from Rm and zero extends to 16 bits.

Adds the signed or zero extended value to the word or corresponding halfword of Rn and writes the result in

Rd .

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the flags.

3.7.3

SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom

; halfword, sign extends to 32 bits, adds R8,and

; writes to R4

UXTAB R3, R4, R10 ; Extracts bottom byte of R10 and zero extends to 32

; bits, adds R4, and writes to R3.

SXT and UXT

Sign extend and Zero extend.

SXT op { cond } Rd , Rn {, ROR # n }

UXT op { cond } Rd , Rn {, ROR # n }

Where:

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Packing and unpacking instructions op

Is one of:

SXTB

Sign extends an 8 ‑ bit value to a 32 ‑ bit value.

SXTH

Sign extends a 16 ‑ bit value to a 32 ‑ bit value.

SXTB16

Sign extends two 8-bit values to two 16-bit values.

UXTB

Zero extends an 8 ‑ bit value to a 32 ‑ bit value.

UXTH

Zero extends a 16 ‑ bit value to a 32 ‑ bit value.

UXTB16

Zero extends two 8-bit values to two 16-bit values.

cond

Is an optional condition code.

Is the destination register.

Is the register holding the value to extend.

ROR #n

Is one of:

ROR #8

Value from Rn is rotated right 8 bits.

ROR #16

Value from Rn is rotated right 16 bits.

ROR #24

Value from Rn is rotated right 24 bits.

If ROR # n is omitted, no rotation is performed.

Operation

These instructions do the following:

Rotate the value from Rn right by 0, 8, 16 or 24 bits.

Extract bits from the resulting value:

– SXTB extracts bits[7:0] and sign extends to 32 bits.

– UXTB extracts bits[7:0] and zero extends to 32 bits.

– SXTH extracts bits[15:0] and sign extends to 32 bits.

– UXTH extracts bits[15:0] and zero extends to 32 bits.

– SXTB16 extracts bits[7:0] and sign extends to 16 bits, and extracts bits [23:16] and sign extends to 16 bits.

– UXTB16 extracts bits[7:0] and zero extends to 16 bits, and extracts bits [23:16] and zero extends to 16 bits.

Restrictions

Do not use SP and do not use PC.

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Bit field instructions

3.8

3.8.1

cond

Rn lsb width

Condition flags

These instructions do not affect the flags.

SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower

; halfword of the result and then sign extend to

; 32 bits and write the result to R4.

UXTB R3, R10 ; Extract lowest byte of the value in R10 and zero

; extend it, and write the result to R3.

Bit field instructions

BFC

BFI

Mnemonic

SBFX

UBFX

Table 38. Bit field instructions

Bit Field Clear

Brief description

Bit Field Insert

Signed Bit Field Extract

Unsigned Bit Field Extract

See

Section 3.8.1 BFC and BFI

Section 3.8.2 SBFX and UBFX

BFC and BFI

Bit Field Clear and Bit Field Insert.

BFC { cond } Rd , # lsb , # width

BFI { cond } Rd , Rn , # lsb , # width

Where:

Is an optional condition code.

Is the destination register.

Is the source register.

Is the position of the least significant bit of the bit field. lsb must be in the range 0-31.

Is the width of the bit field and must be in the range 1-32− lsb .

Operation

BFC clears a bit field in a register. It clears width bits in Rd , starting at the low bit position lsb . Other bits in Rd are unchanged.

BFI copies a bit field into one register from another register. It replaces width bits in Rd starting at the low bit position lsb , with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the flags.

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Branch and control instructions

3.8.2

cond

Rn lsb width

3.9

3.9.1

BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0

BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with

; bit 0 to bit 11 from R2.

SBFX and UBFX

Signed Bit Field Extract and Unsigned Bit Field Extract.

SBFX { cond } Rd , Rn , # lsb , # width

UBFX { cond } Rd , Rn , # lsb , # width

Where:

Is an optional condition code.

Is the destination register.

Is the source register.

Is the position of the least significant bit of the bit field. lsb must be in the range 0-31.

Is the width of the bit field and must be in the range 1-32− lsb .

Operation

SBFX extracts a bit field from one register, sign extends it to 32 bits, and writes the result to the destination register.

UBFX extracts a bit field from one register, zero extends it to 32 bits, and writes the result to the destination register.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not affect the flags.

SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign

; extend to 32 bits and then write the result to R0.

UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero

; extend to 32 bits and then write the result to R8.

Branch and control instructions

Reference material for the Cortex ‑ M33 processor branch and control instruction set.

List of branch and control instructions

An alphabetically ordered list of the branch and control instructions, with a brief description and link to the syntax definition, operations, restrictions, and example usage for each instruction.

Mnemonic

Branch

Branch with Link

Table 39. Branch and control instructions

Brief description See

Section 3.9.2 B, BL, BX, and BLX

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Branch and control instructions

3.9.2

cond label

Mnemonic

BLX

BLXNS

BXNS

CBNZ

CBZ

TBB

TBH

B, BL, BX, and BLX

Branch instructions.

B{ cond } label

BL label

BX Rm

BLX Rm

Where:

Brief description

Branch indirect with Link

Branch indirect with Link, Non-secure

Branch indirect

Branch indirect, Non-secure

Compare and Branch if Non Zero

Compare and Branch if Zero

If ‑ Then

Table Branch Byte

Table Branch Halfword

See

Section 3.9.2 B, BL, BX, and BLX

Section 3.9.2 B, BL, BX, and BLX

Section 3.9.4 CBZ and CBNZ

Section 3.9.5 IT

Section 3.9.6 TBB and TBH

Is an optional condition code.

Is a PC-relative expression.

Is a register providing the address to branch to.

Operation

All these instructions cause a branch to the address indicated by label or contained in the register specified by Rm .

In addition:

•

The BL and BLX instructions write the address of the next instruction to LR, the link register R14.

The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0.

BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is suitable for use by a subsequent POP {PC} or BX instruction to perform a successful return branch.

The following table shows the ranges for the various branch instructions.

B label

B cond label

BL label

BX Rm

BLX Rm

Instruction

Table 40. Branch ranges

Branch range

−2KB to +2KB.

−256 bytes to +254 bytes.

−16MB to +16MB.

Any value in register.

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Branch and control instructions

Note:

3.9.3

Restrictions

In these instructions:

• Do not use SP or PC in the BX or BLX instruction.

• For BX and BLX , bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update the EPSR T-bit and is discarded from the target address.

Bcond is the only conditional instruction on the processor.

BX can be used an Exception or Function return.

Condition flags

These instructions do not change the flags.

Examples

B loopA ; Branch to loopA

BL funC ; Branch with link (Call) to function funC, return address

; stored in LR

BX LR ; Return from function call if LR contains a FUNC_RETURN value.

BLX R0 ; Branch with link and exchange (Call) to a address stored

; in R0

BEQ labelD ; Conditionally branch to labelD if last flag setting

; instruction set the Z flag, else do not branch.

BXNS and BLXNS

Branch and Exchange Non-secure and Branch with Link and Exchange Non-secure.

BXNS <Rm>

BLXNS <Rm>

Where:

Is a register containing an address to branch to.

Operation

The BLXNS instruction calls a subroutine at an address contained in Rm and conditionally causes a transition from the Secure to the Non-secure state.

For both BXNS and BLXNS , Rm[0] indicates a transition to Non-secure state if value is 0, otherwise the target state remains Secure. If transitioning to Non-secure, BLXNS pushes the return address and partial PSR to the Secure stack and assigns R14 to a FNC_RETURN value.

These instructions are available for Secure state only. When the processor is in Non-secure state, these instructions are UNDEFINED and triggers a UsageFault if executed.

Restrictions

PC and SP cannot be used for Rm .

Condition flags

These instructions do not change the flags.

Examples

LDR r0, =non_secure_function

MOVS r1, #1

BICS r0, r1 # Clear bit 0 of address in r0

BLXNS r0 ; Call Non-secure function. This sets r14 to FUNC_RETURN value

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Branch and control instructions cond

Note:

Specifies the condition for the first instruction in the IT block.

The condition switch for the second, third and fourth instruction in the IT block can be either:

Then. Applies the condition cond to the instruction.

Else. Applies the inverse condition of cond to the instruction.

It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E .

Operation

The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT block .

The instructions in the IT block, including any branches, must specify the condition in the { cond } part of their syntax.

Your assembler might be able to generate the required IT instructions for conditional instructions automatically, so that you do not have to write them yourself. See your assembler documentation for details.

A BKPT instruction in an IT block is always executed, even if its condition fails.

Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked

PSR.

Instructions designed for use for exception returns can be used as normal to return from the exception, and execution of the IT block resumes correctly. This is the only way that a PC ‑ modifying instruction is permitted to branch to an instruction in an IT block.

Restrictions

The following instructions are not permitted in an IT block:

• IT .

•

CBZ and CBNZ .

CPSID and CPSIE.

•

Other restrictions when using an IT block are:

• A branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are:

– ADD PC, PC, Rm .

– MOV PC, Rm .

•

– B , BL , BX , BLX .

– Any LDM , LDR , or POP instruction that writes to the PC.

– TBB and TBH.

Do not branch to any instruction inside an IT block, except when returning from an exception handler.

All conditional instructions except B cond must be inside an IT block. B cond can be either outside or inside an IT block but has a larger branch range if it is inside one.

Each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block.

Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them.

Condition flags

This instruction does not change the flags.

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Branch and control instructions

3.9.6

ITTE NE ; Next 3 instructions are conditional

ANDNE R0, R0, R1 ; ANDNE does not update condition flags

ADDSNE R2, R2, #1 ; ADDSNE updates condition flags

MOVEQ R2, R3 ; Conditional move

CMP R0, #9 ; Convert R0 hex value (0 to 15) into ASCII

; ('0'-'9', 'A'-'F')

ITE GT ; Next 2 instructions are conditional

ADDGT R1, R0, #55 ; Convert 0xA -> 'A'

ADDLE R1, R0, #48 ; Convert 0x0 -> '0'

IT GT ; IT block with only one conditional instruction

ADDGT R1, R1, #1 ; Increment R1 conditionally ITTEE EQ

; Next 4 instructions are conditional

MOVEQ R0, R1 ; Conditional move

ADDEQ R2, R2, #10 ; Conditional add

ANDNE R3, R3, #1 ; Conditional AND

BNE.W dloop ; Branch instruction can only be used in the last

; instruction of an IT block

IT NE ; Next instruction is conditional

ADD R0, R0, R1 ; Syntax error: no condition code used in IT block

TBB and TBH

Table Branch Byte and Table Branch Halfword.

TBB [ Rn , Rm ]

TBH [ Rn , Rm , LSL #1]

Where:

Is the register containing the address of the table of branch lengths.

If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction.

Is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table.

Operation

These instructions cause a PC ‑ relative forward branch using a table of single byte offsets for TBB , or halfword offsets for TBH . Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch offset is the unsigned value of the byte returned from the table, and for TBH the branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the address of the byte immediately after the TBB or TBH instruction.

Restrictions

The restrictions are:

•

Rn must not be SP.

Rm must not be SP and must not be PC.

When any of these instructions is used inside an IT block, it must be the last instruction of the IT block.

Condition flags

These instructions do not change the flags.

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Floating-point instructions

3.10

ADR.W R0, BranchTable_Byte

TBB [R0, R1] ; R1 is the index, R0 is the base address of the

; branch table

Case1

; an instruction sequence follows

Case2

; an instruction sequence follows

Case3

; an instruction sequence follows

BranchTable_Byte

DCB 0 ; Case1 offset calculation

DCB ((Case2-Case1)/2) ; Case2 offset calculation

DCB ((Case3-Case1)/2) ; Case3 offset calculation

TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the

; branch table

BranchTable_H

DCW ((CaseA - BranchTable_H)/2) ; CaseA offset calculation

DCW ((CaseB - BranchTable_H)/2) ; CaseB offset calculation

DCW ((CaseC - BranchTable_H)/2) ; CaseC offset calculation

CaseA

; an instruction sequence follows

CaseB

; an instruction sequence follows

CaseC

; an instruction sequence follows

Floating-point instructions

This section provides the instruction set that the FPU uses.

Table 41 shows the floating-point instructions.

These instructions are only available if the FPU is included, and enabled, in the system. See

Section 4.6.5 Code sequence for enabling the FPU for information about enabling the floating-point unit.

Mnemonic

FLDMDBX

FLDMIAX

FSTMDBX

FSTMIAX

VABS

VADD

VCMP

VCMPE

VCVT

VCVTA , VCVTN ,

VCVTP , VCVTM

Table 41. Floating-point instructions

Brief description

FLDMX (Decrement Before) loads multiple extension registers from consecutive memory locations

FLDMX (Increment After) loads multiple extension registers from consecutive memory locations

FSTMX (Decrement Before) stores multiple extension registers to consecutive memory locations

FSTMX (Increment After) stores multiple extension registers to consecutive memory locations

Floating-point Absolute

See

Section 3.10.1 FLDMDBX, FLDMIAX

Section 3.10.2 FSTMDBX, FSTMIAX

Section 3.10.3 VABS

Floating-point Add

Compare two floating-point registers, or one floating-point register and zero

Section 3.10.4 VADD

Section 3.10.5 VCMP and VCMPE

Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check

Section 3.10.5 VCMP and VCMPE

Convert between floating-point and integer

Convert between floating-point and fixed point

Section 3.10.6 VCVT and VCVTR between floating-point and integer

Section 3.10.7 VCVT between floating-point and fixed-point

Float to integer conversion with directed rounding

Section 3.10.35 VCVTA, VCVTM VCVTN, and VCVTP

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PM0264

Floating-point instructions

Mnemonic

VCVTB

Brief description

Converts half-precision value to single-precision

See

Section 3.10.36 VCVTB and VCVTT

VCVTR Convert between floating-point and integer with rounding

Section 3.10.6 VCVT and VCVTR between floating-point and integer

Section 3.10.36 VCVTB and VCVTT

VCVTT

VDIV

VFMA

VFMS

VFNMA

VFNMS

VLDM

Converts single-precision register to half-precision

Floating-point Divide

Floating-point Fused Multiply Accumulate

Floating-point Fused Multiply Subtract

Floating-point Fused Negate Multiply Accumulate

Floating-point Fused Negate Multiply Subtract

Load Multiple extension registers

VLDR Loads an extension register from memory

VMAXNM , VMINNM Maximum, Minimum with IEEE754-2008 NaN handling

VMLA Floating-point Multiply Accumulate

VMLS

VMOV

Floating-point Multiply Subtract

Floating-point Move Immediate

Floating-point Move Register

Section 3.10.8 VDIV

Section 3.10.9 VFMA and VFMS

Section 3.10.10 VFNMA and VFNMS

Section 3.10.11 VLDM

Section 3.10.12 VLDR

Section 3.10.37 VMAXNM and VMINNM

Section 3.10.15 VMLA and VMLS

Section 3.10.16 VMOV Immediate

Section 3.10.17 VMOV Register

VMOV

Copy Arm core register to single-precision

Copy 2 Arm core registers to 2 single-precision

Copies between Arm core register to scalar

Copies between Scalar to Arm core register

Section 3.10.19 VMOV core register to single-precision

Section 3.10.20 VMOV two core registers to two single-precision registers

Section 3.10.22 VMOV core register to scalar

Section 3.10.18 VMOV scalar to core register

VMRS

VMSR

Move to Arm core register from floating-point System

Move to floating-point System Register from Arm Core register

Section 3.10.23 VMRS

Section 3.10.24 VMSR

VMUL

VNEG

Multiply floating-point

Floating-point negate

Section 3.10.25 VMUL

Section 3.10.26 VNEG

VNMLA

VNMLS

VNMUL

Floating-point multiply and add

Floating-point multiply and subtract

Floating-point multiply

Section 3.10.27 VNMLA, VNMLS and

VNMUL

Section 3.10.27 VNMLA, VNMLS and

VNMUL

Section 3.10.27 VNMLA, VNMLS and

VNMUL

VPOP

VPUSH

Pop extension registers

Push extension registers

VRINTA ,

VRINTN ,

VRINTP , VRINTM

Float to integer (in floating-point format) conversion with directed rounding

Section 3.10.28 VPOP

Section 3.10.29 VPUSH

Section 3.10.39 VRINTA, VRINTN, VRINTP,

VRINTM, and VRINTZ

VRINTR , VRINTX Float to integer (in floating-point format) conversion

VSEL Select register, alternative to a pair of conditional

Section 3.10.38 VRINTR and VRINTX

VMOV

Section 3.10.34 VSEL

VSQRT Floating-point square root

Section 3.10.30 VSQRT

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Floating-point instructions

3.10.1

cond

Rn dreglist

3.10.2

cond

dreglist

Mnemonic

VSTM

VSTR

VSUB

Brief description

Store Multiple extension registers

Stores an extension register to memory

Floating-point Subtract

See

Section 3.10.31 VSTM

Section 3.10.32 VSTR

Section 3.10.33 VSUB

FLDMDBX, FLDMIAX

FLDMX (Decrement Before, Increment After) loads multiple extension registers from consecutive memory locations using an address from a general-purpose register.

FLDMDBX{ cond } Rn !, dreglist

FLDMIAX{ cond } Rn {!}, dreglist

Where:

Is an optional condition code.

Is the base register. If write-back is not specified, the PC can be used.

Specifies base register write-back.

Is the list of consecutively numbered 64-bit SIMD and FP registers to be transferred. The list must contain at least one register, all registers must be in the range D0-D15, and must not contain more than 16 registers.

Operation

FLDMX loads multiple SIMD and FP registers from consecutive locations in the Advanced SIMD and floating-point register file using an address from a general-purpose register.

Arm deprecates use of FLDMDBX and FLDMIAX , except for disassembly purposes, and reassembly of disassembled code.

Depending on settings in the CPACR and NSACR and the Security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined .

FSTMDBX, FSTMIAX

FSTMX (Decrement Before, Increment After) stores multiple extension registers to consecutive memory locations using an address from a general-purpose register.

FSTMDBX{ c }{ q } Rn !, dreglist

FSTMIAX{ c }{ q } Rn {!}, dreglist

Where:

Is an optional condition code.

Is the base register. If write-back is not specified, the PC can be used. However, Arm deprecates use of the PC.

Specifies base register write-back.

Is the list FP registers to be transferred. The list must contain at least one register, all registers must be in the range D0-D15, and must not contain more than 16 registers.

Operation

FSTMX stores multiple SIMD and FP registers from the Advanced SIMD and floating-point register file to consecutive locations using an address from a general-purpose register.

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Floating-point instructions

3.10.3

cond

Sd, Sm

3.10.4

cond

Sn, Sm

Arm deprecates use of FLDMDBX and FLDMIAX , except for disassembly purposes, and reassembly of disassembled code.

Depending on settings in the CPACR , NSACR , and FPEXC Registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined .

VABS

Floating-point Absolute.

VABS{ cond }.F32 Sd , Sm

Where:

Is an optional condition code.

Are the destination floating-point value and the operand floating-point value.

Operation

This instruction:

Takes the absolute value of the operand floating-point register.

Places the results in the destination floating-point register.

Restrictions

There are no restrictions.

Condition flags

This instruction does not change the flags.

VABS.F32 S4, S6

VADD

Floating-point Add.

VADD{ cond }.F32 { Sd ,} Sn , Sm

Where:

Is an optional condition code.

Is the destination floating-point value.

Are the operand floating-point values.

Operation

This instruction:

Adds the values in the two floating-point operand registers.

Places the results in the destination floating-point register.

the results in the destination floating-point register.

Restrictions

There are no restrictions.

Condition flags

This instruction does not change the flags.

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Floating-point instructions

3.10.5

cond

Sm|Dm

3.10.6

R cond

VADD.F32 S4, S6, S7

VCMP and VCMPE

Compares two floating-point registers, or one floating-point register and zero.

VCMP{ E }{ cond }.F32 Sd , Sm|#0.0

VCMP{ E }{ cond }.F32 Sd , #0.0

Where:

Is an optional condition code.

If present, any NaN operand causes an Invalid Operation exception. Otherwise, only a signaling NaN causes the exception.

Is the floating-point operand to compare.

Is the floating-point operand that is compared with.

Operation

This instruction:

Compares either:

– Two floating-point registers.

– Or one floating-point register and zero.

Writes the result to the FPSCR flags.

Restrictions

This instruction can optionally raise an Invalid Operation exception if either operand is any type of NaN . It always raises an Invalid Operation exception if either operand is a signaling NaN .

Condition flags

When this instruction writes the result to the FPSCR flags, the values are normally transferred to the Arm flags by a subsequent VMRS instruction.

VCMP.F32 S4, #0.0VCMP.F32 S4, S2

VCVT and VCVTR between floating-point and integer

Converts a value in a register from floating-point to and from a 32-bit integer.

VCVT{R}{ cond }.

Tm .F32 Sd , Sm

VCVT{ cond }.F32.

Tm Sd , Sm

Where:

If R is specified, the operation uses the rounding mode specified by the FPSCR . If R is omitted. the operation uses the Round towards Zero rounding mode.

Is an optional condition code.

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Floating-point instructions

Sd, Sm

3.10.7

cond

Sd fbits

Is the data type for the operand. It must be one of:

• S32 signed 32-bit value.

• U32 unsigned 32-bit value.

Are the destination register and the operand register.

Operation

These instructions:

Either:

– Convert a value in a register from floating-point value to a 32-bit integer.

– Convert from a 32-bit integer to floating-point value.

Place the result in a second register.

The floating-point to integer operation normally uses the Round towards Zero rounding mode, but can optionally use the rounding mode specified by the FPSCR .

The integer to floating-point operation uses the rounding mode specified by the FPSCR .

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VCVT between floating-point and fixed-point

Converts a value in a register from floating-point to and from a 32-bit integer.

VCVT{ cond }.

Td .F32 Sd , Sd , # fbits

VCVT{ cond }.F32.

Td Sd , Sd , # fbits

Where:

Is an optional condition code.

•

Is the data type for the fixed-point number. It must be one of:

• S16 signed 16-bit value.

•

U16 unsigned 16-bit value.

S32 signed 32-bit value.

U32 unsigned 32-bit value.

Is the destination register and the operand register.

Is the number of fraction bits in the fixed-point number:

• If Td is S16 or U16 , fbits must be in the range 0-16.

• If Td is S32 or U32 , fbits must be in the range 1-32.

Operation

This instruction:

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Floating-point instructions

3.10.8

cond

Sn, Sm

3.10.9

cond

Either

– Converts a value in a register from floating-point to fixed-point.

– Converts a value in a register from fixed-point to floating-point.

Places the result in a second register.

The floating-point values are single-precision or double-precision.

The fixed-point value can be 16-bit or 32-bit. Conversions from fixed-point values take their operand from the loworder bits of the source register and ignore any remaining bits.

Signed conversions to fixed-point values sign-extend the result value to the destination register width.

Unsigned conversions to fixed-point values zero-extend the result value to the destination register width.

The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VDIV

Divides floating-point values.

VDIV{ cond }.F32 { Sd ,} Sn , Sm

Where:

Is an optional condition code.

Is the destination register.

Are the operand registers.

Operation

This instruction:

Divides one floating-point value by another floating-point value.

Writes the result to the floating-point destination register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VFMA and VFMS

Floating-point Fused Multiply Accumulate and Subtract.

VFMA{ cond }.F32 { Sd, } Sn , Sm

VFMS{ cond }.F32 { Sd, } Sn , Sm

Where:

Is an optional condition code.

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Floating-point instructions

Sn, Sm

3.10.10

cond

Sn, Sm

Is the destination register.

Are the operand registers.

Operation

The VFMA instruction:

Multiplies the floating-point values in the operand registers.

Accumulates the results into the destination register.

The result of the multiply is not rounded before the accumulation.

The VFMS instruction:

Negates the first operand register.

Multiplies the floating-point values of the first and second operand registers.

Adds the products to the destination register.

Places the results in the destination register.

The result of the multiply is not rounded before the addition.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VFNMA and VFNMS

Floating-point Fused Negate Multiply Accumulate and Subtract.

VFNMA{ cond }.F32 { Sd, } Sn , Sm

VFNMS{ cond }.F32 { Sd, } Sn , Sm

Where:

Is an optional condition code.

Is the destination register.

Are the operand registers.

Operation

The VFNMA instruction:

Negates the first floating-point operand register.

Multiplies the first floating-point operand with second floating-point operand.

Adds the negation of the floating -point destination register to the product

Places the result into the destination register.

The result of the multiply is not rounded before the addition.

The VFNMS instruction:

Multiplies the first floating-point operand with second floating-point operand.

Adds the negation of the floating-point value in the destination register to the product.

Places the result in the destination register.

The result of the multiply is not rounded before the addition.

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Floating-point instructions

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

3.10.11

VLDM

Floating-point Load Multiple.

VLDM{ mode }{ cond }{.

size } Rn {!}, list

Where: mode

Is the addressing mode:

Increment after. The consecutive addresses start at the address specified in Rn .

Decrement before. The consecutive addresses end before the address specified in Rn .

cond

Is an optional condition code.

size

Is an optional data size specifier.

Is the base register. The SP can be used.

Is the command to the instruction to write a modified value back to Rn . This is required if mode == DB , and is optional if mode == IA .

list

Is the list of extension registers to be loaded, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets.

Operation

This instruction loads multiple extension registers from consecutive memory locations using an address from an

Arm core register as the base address.

Restrictions

The restrictions are:

• If size is present, it must be equal to the size in bits, 32 or 64 , of the registers in list .

•

For the base address, the SP can be used. In the Arm instruction set, if !

is not specified the PC can be used.

list must contain at least one register. If it contains doubleword registers, it must not contain more than 16 registers.

If using the Decrement before addressing mode, the write back flag, !

, must be appended to the base register specification.

Condition flags

These instructions do not change the flags.

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Floating-point instructions cond

32, 64

Rn imm

3.10.12

label

3.10.13

cond

VLDMIA.F64 r1, {d3,d4,d5}

VLDR

Loads a single extension register from memory.

VLDR{ cond }{.

F<32 |64>} <Sd|Dd >, [ Rn {, # imm }]

VLDR{ cond }{.

F<32 |64>} <Sd|Dd >, label

VLDR{ cond }{.

F<32 |64>} <Sd|Dd >, [PC, # imm ]

Where:

Is an optional condition code.

Are the optional data size specifiers.

Is the destination register for a doubleword load.

Is the destination register for a singleword load.

Is the base register. The SP can be used.

Is the + or - immediate offset used to form the address. Permitted address values are multiples of 4 in the range

0-1020.

Is the label of the literal data item to be loaded.

Operation

This instruction loads a single extension register from memory, using a base address from an Arm core register, with an optional offset.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VLLDM

Floating-point Lazy Load Multiple restores the contents of the Secure floating-point registers that were protected by a VLSTM instruction, and marks the floating-point context as active.

VLLDM { cond } < Rn >

Where:

Is an optional condition code.

Is the base register.

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Floating-point instructions

3.10.14

cond

3.10.15

cond

Operation

If the lazy state preservation set up by a previous VLSTM instruction is active (FPCCR.LSPACT == 1), this instruction deactivates lazy state preservation and enables access to the Secure floating-point registers. If lazy state preservation is inactive (FPCCR.LSPACT == 0), either because lazy state preservation was not enabled

(FPCCR.LSPEN == 0) or because a floating-point instruction caused the Secure floating-point register contents to be stored to memory, this instruction loads the stored Secure floating-point register contents back into the floatingpoint registers. If Secure floating-point is not in use (CONTROL_S.SFPA == 0), this instruction behaves as a NOP .

This instruction is only available in Secure state, and is UNDEFINED in Non-secure state. If the Floating-point

Extension is not implemented, this instruction is available in Secure state, but behaves as a NOP .

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VLSTM

Floating-point Lazy Store Multiple stores the contents of Secure floating-point registers to a prepared stack frame, and clears the Secure floating-point registers.

VLSTM { cond } < Rn >

Where:

Is an optional condition code.

Is the base register.

Operation

•

If floating-point lazy preservation is enabled (FPCCR.LSPEN == 1), then the next time a floating-point instruction other than VLSTM or VLLDM is executed:

The contents of Secure floating-point registers are stored to memory.

The Secure floating-point registers are cleared.

If Secure floating-point is not in use (CONTROL_S.SFPA == 0), this instruction behaves as a NOP .

This instruction is only available in Secure state, and is UNDEFINED in Non-secure state.

If the Floating-point Extension is not implemented, this instruction is available in Secure state, but behaves as a

NOP .

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VMLA and VMLS

Multiplies two floating-point values, and accumulates or subtracts the result.

VMLA{ cond }.F32 Sd , Sn , Sm

VMLS{ cond }.F32 Sd , Sn , Sm

Where:

Is an optional condition code.

PM0264 - Rev 1 page 138/245

Sn, Sm

3.10.16

cond

Sd imm

3.10.17

cond

Is the destination floating-point value.

Are the operand floating-point values.

Operation

The floating-point Multiply Accumulate instruction:

Multiplies two floating-point values.

Adds the results to the destination floating-point value.

The floating-point Multiply Subtract instruction:

Multiplies two floating-point values.

Subtracts the products from the destination floating-point value.

Places the results in the destination register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VMOV Immediate

Move floating-point Immediate.

VMOV{ cond }.F32

Sd , # imm

Where:

Is an optional condition code.

Is the destination register.

Is a floating-point constant.

Operation

This instruction copies a constant value to a floating-point register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VMOV Register

Copies the contents of one register to another.

VMOV{ cond }.F<32> Sd , Sm Dm

Where:

Is an optional condition code.

Is the destination register, for a doubleword operation.

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Floating-point instructions page 139/245

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Floating-point instructions

Sm cond

Dn x

3.10.18

3.10.19

cond

Is the source register, for a doubleword operation.

Is the destination register, for a singleword operation.

Is the source register, for a singleword operation.

Operation

This instruction copies the contents of one floating-point register to another.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VMOV scalar to core register

Transfers one word of a doubleword floating-point register to an Arm core register.

VMOV{ cond } Rt , Dn [ x ]

Where:

Is an optional condition code.

Is the destination Arm core register.

Is the 64-bit doubleword register.

Specifies which half of the doubleword register to use:

• If x is 0, use lower half of doubleword register.

• If x is 1, use upper half of doubleword register.

Operation

This instruction transfers one word from the upper or lower half of a doubleword floating-point register to an Arm core register.

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions do not change the flags.

VMOV core register to single-precision

Transfers a single-precision register to and from an Arm core register.

VMOV{ cond } Sn , Rt

VMOV{ cond } Rt , Sn

Where:

Is an optional condition code.

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Floating-point instructions cond

Sm1

Rt2

<Sn>

3.10.20

Is the single-precision floating-point register.

Is the Arm core register.

Operation

This instruction transfers:

• The contents of a single-precision register to an Arm core register.

• The contents of an Arm core register to a single-precision register.

Restrictions

Rt cannot be PC or SP.

Condition flags

These instructions do not change the flags.

VMOV two core registers to two single-precision registers

Transfers two consecutively numbered single-precision registers to and from two Arm core registers.

VMOV{ cond } Sm , Sm1 , Rt , Rt2

VMOV{ cond } Rt , Rt2 , Sm , Sm1

Where:

Is an optional condition code.

Is the first single-precision register.

Is the second single-precision register. This is the next single-precision register after Sm .

Is the Arm core register that Sm is transferred to or from.

Is the Arm core register that Sm1 is transferred to or from.

Operation

This instruction transfers:

• The contents of two consecutively numbered single-precision registers to two Arm core registers.

• The contents of two Arm core registers to a pair of single-precision registers.

Restrictions

•

The restrictions are:

• The floating-point registers must be contiguous, one after the other.

The Arm core registers do not have to be contiguous.

Rt cannot be PC or SP.

Condition flags

These instructions do not change the flags.

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PM0264

Floating-point instructions

3.10.21

cond

Rt, Rt2

3.10.22

cond

Dd[x]

VMOV two core registers and a double-precision register

Transfers two words from two Arm core registers to a doubleword register, or from a doubleword register to two

Arm core registers.

VMOV{ cond } Dm , Rt , Rt2

VMOV{ cond } Rt , Rt2 , Dm

Where:

Is an optional condition code.

Is the double-precision register.

Are the two Arm core registers.

Operation

This instruction:

• Transfers two words from two Arm core registers to a doubleword register.

• Transfers a doubleword register to two Arm core registers.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VMOV core register to scalar

Transfers one word to a floating-point register from an Arm core register.

VMOV{ cond }{.

32 } Dd [ x ], Rt

Where:

Is an optional condition code.

Is an optional data size specifier.

Is the destination, where [ x ] defines which half of the doubleword is transferred, as follows:

• If x is 0, the lower half is extracted.

• If x is 1, the upper half is extracted.

Is the source Arm core register.

Operation

This instruction transfers one word to the upper or lower half of a doubleword floating-point register from an Arm core register.

Restrictions

Rt cannot be PC or SP.

PM0264 - Rev 1 page 142/245

3.10.23

Condition flags

These instructions do not change the flags.

VMRS

Move to Arm Core register from floating-point System Register.

VMRS{ cond } Rt , FPSCR

VMRS{ cond } APSR_nzcv , FPSCR

Where: cond

Is an optional condition code.

Is the destination Arm core register. This register can be R0-R14.

APSR_nzcv

Transfer floating-point flags to the APSR flags.

Operation

This instruction performs one of the following actions:

• Copies the value of the FPSCR to a general-purpose register.

• Copies the value of the FPSCR flag bits to the APSR N, Z, C, and V flags.

Restrictions

Rt cannot be PC or SP.

3.10.24

Condition flags

These instructions optionally change the N, Z, C, and V flags.

VMSR

Move to floating-point System Register from Arm Core register.

VMSR{ cond } FPSCR, Rt

Where: cond

Is an optional condition code.

3.10.25

Is the general-purpose register to be transferred to the FPSCR.

Operation

This instruction moves the value of a general-purpose register to the FPSCR.

Restrictions

Rt cannot be PC or SP.

Condition flags

This instruction updates the FPSCR.

VMUL

Floating-point Multiply.

VMUL{ cond }.F32 { Sd ,} Sn , Sm

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cond

Sn, Sm

3.10.26

cond

3.10.27

Where:

Is an optional condition code.

Is the destination floating-point value.

Are the operand floating-point values.

Operation

This instruction:

Multiplies two floating-point values.

Places the results in the destination register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VNEG

Floating-point Negate.

VNEG{ cond }.F32

Sd , Sm

Where:

Is an optional condition code.

Is the destination floating-point value.

Is the operand floating-point value.

Operation

This instruction:

Negates a floating-point value.

Places the results in a second floating-point register.

The floating-point instruction inverts the sign bit.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VNMLA, VNMLS and VNMUL

Floating-point multiply with negation followed by add or subtract.

VNMLA{ cond }.F32 Sd , Sn , Sm

VNMLS{ cond }.F32 Sd , Sn , Sm

VNMUL{ cond }.F32 { Sd ,} Sn , Sm

Where:

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Floating-point instructions cond

Sn, Sm

3.10.28

cond size list

Is an optional condition code.

Is the destination floating-point register.

Are the operand floating-point registers.

Operation

The VNMLA instruction:

Multiplies two floating-point register values.

Adds the negation of the floating-point value in the destination register to the negation of the product.

Writes the result back to the destination register.

The VNMLS instruction:

Multiplies two floating-point register values.

Adds the negation of the floating-point value in the destination register to the product.

Writes the result back to the destination register.

The VNMUL instruction:

Multiplies together two floating-point register values.

Writes the negation of the result to the destination register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VPOP

Floating-point extension register Pop.

VPOP{ cond }{.

size } list

Where:

Is an optional condition code.

Is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list .

Is a list of extension registers to be loaded, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets.

Operation

This instruction loads multiple consecutive extension registers from the stack.

Restrictions list must contain at least one register, and not more than sixteen registers.

Condition flags

These instructions do not change the flags.

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Floating-point instructions

3.10.29

cond size list

3.10.30

cond

3.10.31

VPUSH

Floating-point extension register Push.

VPUSH{ cond }{.

size } list

Where:

Is an optional condition code.

Is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list .

Is a list of the extension registers to be stored, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets.

Operation

This instruction stores multiple consecutive extension registers to the stack.

Restrictions list must contain at least one register, and not more than sixteen.

Condition flags

These instructions do not change the flags.

VSQRT

Floating-point Square Root.

VSQRT{ cond }.F32 Sd , Sm

Where:

Is an optional condition code.

Is the destination floating-point value.

Is the operand floating-point value.

Operation

This instruction:

• Calculates the square root of the value in a floating-point register.

• Writes the result to another floating-point register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VSTM

Floating-point Store Multiple.

VSTM{ mode }{ cond }{.

size } Rn {!}, list

Where:

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Floating-point instructions mode cond size

Rn list cond

32, 64

3.10.32

Is the addressing mode:

• IA Increment After can be omitted.

. The consecutive addresses start at the address specified in Rn . This is the default and

• DB Decrement Before . The consecutive addresses end just before the address specified in Rn .

Is an optional condition code.

Is an optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers in list .

Is the base register. The SP can be used.

Is the function that causes the instruction to write a modified value back to Rn . Required if mode == DB .

Is a list of the extension registers to be stored, as a list of consecutively numbered doubleword or singleword registers, separated by commas and surrounded by brackets.

Operation

This instruction stores multiple extension registers to consecutive memory locations using a base address from an

Arm core register.

Restrictions

The restrictions are:

•

• list must contain at least one register. If it contains doubleword registers it must not contain more than 16 registers.

Use of the PC as Rn is deprecated.

Condition flags

These instructions do not change the flags.

VSTR

Floating-point Store.

VSTR{ cond }{.

32 } Sd , [ Rn {, # imm }]

VSTR{ cond }{.

64 } Dd , [ Rn {, # imm }]

Where:

Is an optional condition code.

Are the optional data size specifiers.

Is the source register for a singleword store.

Is the source register for a doubleword store.

Is the base register. The SP can be used.

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Floating-point instructions imm

3.10.33

cond

Sn, Sm

3.10.34

cond

Sn, Sm

Is the + or - immediate offset used to form the address. Values are multiples of 4 in the range 0-1020. imm can be omitted, meaning an offset of +0 .

Operation

This instruction stores a single extension register to memory, using an address from an Arm core register, with an optional offset, defined in imm :

Restrictions

The use of PC for Rn is deprecated.

Condition flags

These instructions do not change the flags.

VSUB

Floating-point Subtract.

VSUB{ cond }.F32 { Sd ,} Sn , Sm

Where:

Is an optional condition code.

Is the destination floating-point value.

Are the operand floating-point values.

Operation

This instruction:

Subtracts one floating-point value from another floating-point value.

Places the results in the destination floating-point register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VSEL

Floating-point Conditional Select allows the destination register to take the value from either one or the other of two source registers according to the condition codes in the APSR.

VSEL{ cond }.F32 Sd , Sn , Sm

Where:

Is an optional condition code. VSEL has a subset of the condition codes. The condition codes for VSEL are limited to GE , GT , EQ and VS , with the effect that LT , LE , NE and VC is achievable by exchanging the source operands.

Is the destination single-precision floating-point value.

Are the operand single-precision floating-point values.

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Operation

Depending on the result of the condition code, this instruction moves either:

• Sn source register to the destination register.

• Sm source register to the destination register.

The behavior is:

EncodingSpecificOperations();

ExecuteFPCheck(); if dp_operation then

S[d] = if ConditionHolds(cond) then S[n] else S[m];

Restrictions

The VSEL instruction must not occur inside an IT block.

Condition flags

This instruction does not change the flags.

3.10.35

VCVTA, VCVTM VCVTN, and VCVTP

Floating-point to integer conversion with directed rounding.

VCVT <rmode> .S32.F32 Sd , Sm

VCVT <rmode> .U32.F32 Sd , Sm

Where:

Is the destination single-precision or double-precision floating-point value.

Sm,

Are the operand single-precision or double-precision floating-point values.

<rmode>

Is one of:

Round to nearest ties away.

Round to nearest even.

Round towards plus infinity.

Round towards minus infinity.

Operation

These instructions:

Read the source register.

Convert to integer with directed rounding.

Write to the destination register.

Restrictions

There are no restrictions.

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Floating-point instructions

3.10.36

y cond

3.10.37

Sn, Sm

Condition flags

These instructions do not change the flags.

VCVTB and VCVTT

Converts between half-precision and single-precision without intermediate rounding.

VCVT{ y }{ cond }.F32.F16 Sd , Sm

VCVT{ y }{ cond }.F16.F32 Sd , Sm

Where:

Specifies which half of the operand register Sm or destination register Sd is used for the operand or destination:

• If y is B , then the bottom half, bits [15:0], of Sm or Sd is used.

• If y is T , then the top half, bits [31:16], of Sm or Sd is used.

Is an optional condition code.

Is the destination register.

Is the operand register.

Operation

This instruction with the .F16.F32

suffix:

Converts the half-precision value in the top or bottom half of a single-precision register to single-precision value.

Writes the result to a single-precision register.

This instruction with the .F32.F16

suffix:

Converts the value in a single-precision register to half-precision value.

Writes the result into the top or bottom half of a single-precision register, preserving the other half of the target register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VMAXNM and VMINNM

Return the minimum or the maximum of two floating-point numbers with NaN handling as specified by

IEEE754-2008.

VMAXNM.F32 Sd , Sn , Sm

VMINNM.F32 Sd , Sn , Sm

Where:

Is the destination single-precision floating-point value.

Are the operand single-precision floating-point values.

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Floating-point instructions

3.10.38

cond

3.10.39

Operation

The VMAXNM instruction compares two source registers, and moves the largest to the destination register.

The VMINNM instruction compares two source registers, and moves the smallest to the destination register.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VRINTR and VRINTX

Round a floating-point value to an integer in floating-point format.

VRINT{R,X}{ cond }.F32 Sd , Sm

Where:

Is an optional condition code.

Is the destination floating-point value.

Are the operand floating-point values.

Operation

These instructions:

Read the source register.

Round to the nearest integer value in floating-point format using the rounding mode specified by the FPSCR.

A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

Write the result to the destination register.

For the VRINTX instruction only. Generate a floating-point exception if the result is not numerically equal to the input value.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ

Round a floating-point value to an integer in floating-point format using directed rounding.

VRINT <rmode> .F32 Sd , Sm

Where:

Is the destination single-precision floating-point value.

Are the operand single-precision floating-point values.

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Miscellaneous instructions

<rmode>

Is one of:

Round to nearest ties away.

Round to Nearest Even.

Round towards Plus Infinity.

Round towards Minus Infinity.

Round towards Zero.

Operation

These instructions:

Read the source register.

Round to the nearest integer value with a directed rounding mode specified by the instruction.

A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

Write the result to the destination register.

Restrictions

VRINTA , VRINTN , VRINTP and VRINTM cannot be conditional. VRINTZ can be conditional.

3.11

Condition flags

These instructions do not change the flags.

Miscellaneous instructions

Table 42 shows the remaining Cortex®-M33 instructions: .

DMB

DSB

ISB

MRS

MSR

NOP

SEV

Mnemonic

BKPT

CPSID

CPSIE

Table 42. Miscellaneous instructions

Brief description

Breakpoint

Change Processor State, Disable Interrupts

Change Processor State, Enable Interrupts

Data Memory Barrier

Data Synchronization Barrier

Instruction Synchronization Barrier

Move from special register to register

Move from register to special register

No Operation

Send Event

Secure Gateway

See

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Miscellaneous instructions

3.11.1

Mnemonic

SVC

TTT

TTA

TTAT

WFE

WFI

YIELD

Brief description

Supervisor Call

Test Target

Test Target Unprivileged

Test Target Alternate Domain

Test Target Alternate Domain Unprivileged

Wait For Event

Wait For Interrupt

Yield

BKPT

Breakpoint.

BKPT # imm

Where:

See

Section 3.11.12 SVC

Section 3.11.13 TT, TTT, TTA, and TTAT

Section 3.11.15 WFE

Section 3.11.16 WFI

Section 3.11.17 YIELD

imm

Is an expression evaluating to an integer in the range 0-255 (8-bit value).

Operation

The BKPT instruction causes the processor to enter Debug state if invasive debug is enabled. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.

The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition specified by the IT instruction.

Condition flags

This instruction does not change the flags.

Note:

BKPT #0x3 ; Breakpoint with immediate value set to 0x3 (debugger can

; extract the immediate value by locating it using the PC)

Arm does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other than Semi-hosting.

3.11.2

CPS

Change Processor State.

CPS effect iflags

Where: effect

Is one of:

Clears the special purpose register.

Sets the special purpose register.

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Miscellaneous instructions iflags

Is a sequence of one or more flags: i

Set or clear PRIMASK.

Set or clear FAULTMASK.

Operation

CPS changes the PRIMASK and FAULTMASK special register values.

Restrictions

The restrictions are:

• Use CPS only from privileged software. It has no effect if used in unprivileged software.

• CPS cannot be conditional and so must not be used inside an IT block.

Condition flags

This instruction does not change the condition flags.

3.11.3

3.11.4

CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK)

CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK)

CPSIE i ; Enable interrupts and configurable fault handlers (clear PRIMASK)

CPSIE f ; Enable interrupts and fault handlers (clear FAULTMASK)

CPY

Copy is a pre-Unified Assembler Language (UAL) synonym for MOV (register).

CPY Rd , Rn

This is equivalent to:

MOV Rd , Rn

DMB

Data Memory Barrier.

DMB{ cond } { opt }

Where: cond

Is an optional condition code.

opt

Specifies an optional limitation on the DMB operation. Values are:

DMB operation ensures ordering of all accesses, encoded as opt == '1111'. Can be omitted.

All other encodings of opt are reserved . The corresponding instructions execute as system ( SY ) DMB operations, but software must not rely on this behavior.

Operation

DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory.

Condition flags

This instruction does not change the flags.

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Miscellaneous instructions cond opt

SY cond opt

3.11.5

3.11.6

DMB ; Data Memory Barrier

DSB

Data Synchronization Barrier.

DSB{ cond } { opt }

Where:

Is an optional condition code.

Specifies an optional limitation on the DSB operation. Values are:

DSB operation ensures completion of all accesses, encoded as opt == '1111'. Can be omitted.

All other encodings of opt are reserved . The corresponding instructions execute as system ( SY ) DSB operations, but software must not rely on this behavior.

Operation

DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB , in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete.

Condition flags

This instruction does not change the flags.

DSB ; Data Synchronisation Barrier

ISB

Instruction Synchronization Barrier.

ISB{ cond } { opt }

Where:

Is an optional condition code.

Specifies an optional limitation on the ISB operation. Values are:

Fully system ISB operation, encoded as opt == '1111'. Can be omitted.

All other encodings of opt are reserved . The corresponding instructions execute as full system ISB operations, but software must not rely on this behavior.

Operation

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.

Condition flags

This instruction does not change the flags.

ISB ; Instruction Synchronisation Barrier

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Miscellaneous instructions

3.11.7

MRS

Move the contents of a special register to a general-purpose register.

MRS { cond } Rd , spec_reg

Where:

Is an optional condition code.

cond

Is the destination register.

spec_reg

Note:

3.11.8

Can be any of: APSR , IPSR , EPSR , IEPSR , IAPSR , EAPSR , PSR , MSP , PSP , PRIMASK , BASEPRI , BASEPRI_MAX ,

FAULTMASK , CONTROL , MSP_NS , PSP_NS , MSPLIM , PSPLIM , MSPLIM_NS , PSPLIM_NS , PRIMASK_NS ,

FAULTMASK_NS , and CONTROL_NS .

All the EPSR and IPSR fields are zero when read by the MRS instruction.

An access to a register not ending in _NS returns the register associated with the current Security state. Access to a register ending in _NS in Secure state returns the Non-secure register. Access to a register ending in _NS in Non-secure state is RAZ/WI.

Operation

Use MRS in combination with MSR as part of a read ‑ modify ‑ write sequence for updating a PSR, for example to clear the Q flag.

In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence.

BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.

Restrictions

Rd must not be SP and must not be PC.

Condition flags

This instruction does not change the flags.

MRS R0, PRIMASK ; Read PRIMASK value and write it to R0

MSR

Move the contents of a general ‑ purpose register into the specified special register.

MSR { cond } spec_reg , Rn

Where:

Is an optional condition code.

cond

Rn spec_reg

Note:

Is the source register.

Can be any of: APSR_nzcvq , APSR_g , APSR_nzcvqg , MSP , PSP , PRIMASK , BASEPRI , BASEPRI_MAX ,

FAULTMASK , CONTROL , MSP_NS , PSP_NS MSPLIM , PSPLIM , MSPLIM_NS , PSPLIM_NS , PRIMASK_NS ,

FAULTMASK_NS , and CONTROL_NS .

You can use APSR to refer to APSR_nzcvq .

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Miscellaneous instructions

Note:

3.11.9

cond

3.11.10

cond

Operation

The register access operation in MSR depends on the privilege level. Unprivileged software can only access the

APSR , see the APSR bit assignments. Privileged software can access all special registers.

In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.

When you write to BASEPRI_MAX , the instruction writes to BASEPRI only if either:

• Rn is non-zero and the current BASEPRI value is 0.

• Rn is non-zero and less than the current BASEPRI value.

An access to a register not ending in _NS writes the register associated with the current Security state. Access to a register ending in _NS in Secure state writes the Non-secure register. Access to a register ending in _NS in

Non-secure state is RAZ/WI.

Restrictions

Rn must not be SP and must not be PC.

Condition flags

This instruction updates the flags explicitly based on the value in Rn .

MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register.

NOP

No Operation.

NOP{ cond }

Where:

Is an optional condition code.

Operation

NOP does nothing. NOP is not necessarily a time ‑ consuming NOP . The processor might remove it from the pipeline before it reaches the execution stage.

Use NOP for padding, for example to place the following instruction on a 64 ‑ bit boundary.

Condition flags

This instruction does not change the flags.

NOP ; No operation

SEV

Send Event.

SEV{ cond }

Where:

Is an optional condition code.

Operation

SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1.

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Miscellaneous instructions

3.11.11

Note:

3.11.12

cond imm

3.11.13

Condition flags

This instruction does not change the flags.

SEV ; Send Event

SG

Secure Gateway.

Operation

Secure Gateway marks a valid branch target for branches from Non-secure code that wants to call Secure code.

A linker is expected to generate a Secure Gateway operation as a part of the branch table for the Non-secure

Callable (NSC) region.

There is no C intrinsic function for SG . Secure Gateways are expected to be generated by linker or by assembly programming. Arm does not expect software developers to insert a Secure Gateway instruction inside C or C++ program code.

For information about how to build a Secure image that uses a previously generated import library, see the Arm ®

Compiler Software Development Guide.

SVC

Supervisor Call.

SVC { cond } # imm

Where:

Is an optional condition code.

Is an expression evaluating to an integer in the range 0 ‑ 255 (8 ‑ bit value).

Operation

The SVC instruction causes the SVC exception.

imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested.

Condition flags

This instruction does not change the flags.

SVC #0x32 ; Supervisor Call (SVCall handler can extract the immediate value

; by locating it through the stacked PC)

TT, TTT, TTA, and TTAT

Test Target (Alternate Domain, Unprivileged).

{ op } { cond } Rd , Rn

Where:

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Miscellaneous instructions op

Is one of:

Test Target (TT) queries the Security state and access permissions of a memory location.

TTT

Test Target Unprivileged (TTT) queries the Security state and access permissions of a memory location for an unprivileged access to that location.

TTA

Test Target Alternate Domain (TTA) queries the Security state and access permissions of a memory location for a Non-secure access to that location. These instructions are only valid when executing in Secure state, and are undefined if used from Nonsecure state.

TTAT

Test Target Alternate Domain Unprivileged (TTAT) queries the Security state and access permissions of a memory location for a

Non-secure and unprivileged access to that location. These instructions are only valid when executing in Secure state, and are undefined if used from Non-secure state.

cond

Is an optional condition code.

Is the destination general-purpose register into which the status result of the target test is written.

Is the base register.

Operation

The instruction returns the Security state and access permissions in the destination register, the contents of which are as follows:

Table 43. Security state and access permissions in the destination register

Bits Name Description

[7:0]

[16]

[17]

MREGION The MPU region that the address maps to. This field is 0 if MRVALID is 0.

[15:8] -SREGION

. RAZ/WI The SAU region that the address maps to. This field is only valid if the instruction is executed from Secure state. This field is 0 if SRVALID is 0.

MRVALID Set to 1 if the MREGION content is valid. Set to 0 if the MREGION content is invalid.

[18]

[19]

-SRVALID . RAZ/WI Set to 1 if the SREGION content is valid. Set to 0 if the SREGION content is invalid.

Read accessibility. Set to 1 if the memory location can be read according to the permissions of the selected MPU when operating in the current mode. For TTT and TTAT , this bit returns the permissions for unprivileged access, regardless of whether the current mode is privileged or unprivileged.

Read/write accessibility. Set to 1 if the memory location can be read and written according to the permissions of the selected MPU when operating in the current mode.

[31:20] -

[20]

[21]

[22]

NSR

NSRW

RAZ/WI

Equal to R AND NOT S. Can be used with the LSLS (immediate) instruction to check both the MPU and

SAU or IDAU permissions. This bit is only valid if the instruction is executed from Secure state and the R field is valid.

Equal to RW AND NOT S. Can be used with the LSLS (immediate) instruction to check both the MPU and SAU or IDAU permissions. This bit is only valid if the instruction is executed from Secure state and the RW field is valid.

Security. A value of 1 indicates that the memory location is Secure, and a value of 0 indicates that the memory location is Non-secure. This bit is only valid if the instruction is executed from Secure state.

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Miscellaneous instructions

Bits

[23]

Name

IRVALID

[31:24] IREGION

Description

IREGION valid flag. For a Secure request, indicates the validity of the IREGION field. Set to 1 if the

IREGION content is valid. Set to 0 if the IREGION content is invalid.

This bit is always 0 if the IDAU cannot provide a region number, the address is exempt from security attribution, or if the requesting TT instruction is executed from the Non-secure state.

IDAU region number. Indicates the IDAU region number containing the target address. This field is 0 if

IRVALID is 0.

3.11.14

imm cond

3.11.15

cond

•

Invalid fields are 0.

The MREGION field is invalid and 0 if any of the following conditions are true:

•

The MPU is not present or MPU_CTRL.ENABLE is 0.

The address did not match any enabled MPU regions.

The address matched multiple MPU regions.

• TT was executed from an unprivileged mode, or TTA is executed and Non-secure state is unprivileged.

The R, RW, NSR, and NSRW bits are invalid and 0 if any of the following conditions are true:

• The address matched multiple MPU regions.

• TT is executed from an unprivileged mode, or TTA is executed and Non-secure state is unprivileged.

UDF

Permanently Undefined.

UDF{ cond }.W {#} imm

Where:

Is a:

•

8-bit unsigned immediate, in the range 0 to 255. The PE ignores the value of this constant.

16-bit unsigned immediate, in the range 0 to 65535. The PE ignores the value of this constant.

Arm deprecates using any c value other than AL .

Operation

Permanently Undefined generates an Undefined Instruction UsageFault exception.

WFE

Wait For Event.

WFE{ cond }

Where:

Is an optional condition code.

Operation

WFE is a hint instruction.

•

If the event register is 0, WFE suspends execution until one of the following events occurs:

• An exception, unless masked by the exception mask registers or the current priority level.

• An exception enters the Pending state, if SEVONPEND

A Debug Entry request, if Debug is enabled.

in the System Control Register is set.

An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.

If the event register is 1, WFE clears it to 0 and returns immediately.

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Memory access instructions

3.11.16

cond

3.11.17

cond

3.12

Condition flags

This instruction does not change the flags.

WFE ; Wait for event

WFI

Wait for Interrupt.

WFI{ cond }

Where:

Is an optional condition code.

Operation

WFI is a hint instruction that suspends execution until one of the following events occurs:

•

A non-masked interrupt occurs and is taken.

An interrupt masked by PRIMASK becomes pending.

A Debug Entry request, if Debug is enabled.

Condition flags

This instruction does not change the flags.

WFI ; Wait for interrupt

YIELD

Yield

YIELD{ cond }

Where:

Is an optional condition code.

Operation

YIELD is a hint instruction that enables software with a multithreading capability to indicate to the hardware that a task is being performed, which could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple code threads if it supports the capability.

Condition flags

This instruction does not change the flags.

YIELD; Suspend task

Memory access instructions

Table 44 shows the memory access instructions:

ADR

Mnemonic

Table 44. Memory access instructions

Brief description

Generate PC-relative address

Section 3.12.1 ADR

See

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Memory access instructions

3.12.1

cond

Rd label

Note:

Mnemonic

CLREX

LDM{mode}

LDA{type}

LDAEX

LDR{type}

LDR{type}T

LDR

LDRD

Load-Acquire

Brief description

Clear Exclusive

Load Multiple registers

Load-Acquire Exclusive

Load Register using immediate offset

Load Register using register offset

Load Register with unprivileged access

Load Register using PC-relative address

Load Register Dual

LDREX{type} Load Register Exclusive

PLD Preload Data.

POP Pop registers from stack

PUSH

STL{mode}

STLEX

Push registers onto stack

Store-Release

Store Release Exclusive

STM{mode}

STR{type}

STR{type}T

Store Multiple registers

Store Register using immediate offset

Store Register using register offset

Store Register with unprivileged access

STREX{type} Store Register Exclusive

ADR

Generate PC-relative address.

ADR { cond } Rd , label

Where:

See

Section 3.12.12 CLREX

Section 3.12.11 LDAEX and STLEX

Section 3.12.4 LDR and STR, unprivileged

Section 3.12.10 LDREX and STREX

Section 3.12.7 PLD

Section 3.12.8 PUSH and POP

Section 3.12.11 LDAEX and STLEX

Section 3.12.4 LDR and STR, unprivileged

Section 3.12.10 LDREX and STREX

Is an optional condition code.

Is the destination register.

Is a PC ‑ relative expression.

Operation

ADR generates an address by adding an immediate value to the PC, and writes the result to the destination register.

ADR provides the means by which position ‑ independent code can be generated, because the address is

PC ‑ relative.

If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the address you generate is set to1 for correct execution.

Values of label must be within the range of −4095 to +4095 from the address in the PC.

You might have to use the .W

suffix to get the maximum offset range or to generate addresses that are not word-aligned.

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Memory access instructions op

LDR

‑ cond

Rn offset

STR type

3.12.2

Restrictions

Rd must not be SP and must not be PC.

Condition flags

This instruction does not change the flags.

ADR R1, TextMessage ; Write address value of a location labelled as

; TextMessage to R1.

LDR and STR, immediate offset

Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

op { type }{ cond } Rt , [ Rn {, # offset }] ; immediate offset op { type }{ cond } Rt , [ Rn , # offset ]! ; pre-indexed op { type }{ cond } Rt , [ Rn ], # offset ; post-indexed op D{ cond } Rt , Rt2 , [ Rn {, # offset }] ; immediate offset, two words op D{ cond } Rt , Rt2 , [ Rn , # offset ]! ; pre-indexed, two words op D{ cond } Rt , Rt2 , [ Rn ], # offset ; post-indexed, two words

Where:

Is one of:

Load Register.

Store Register.

Is one of:

Unsigned byte, zero extend to 32 bits on loads.

Signed byte, sign extend to 32 bits ( LDR only).

Unsigned halfword, zero extend to 32 bits on loads.

Signed halfword, sign extend to 32 bits ( LDR only).

Omit, for word.

Is an optional condition code.

Is the register to load or store.

Is the register on which the memory address is based.

Is an offset from Rn . If offset is omitted, the address is the contents of Rn .

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Memory access instructions

Rt2

Is the additional register to load or store for two-word operations.

Operation

LDR instructions load one or two registers with a value from memory.

STR instructions store one or two register values to memory.

Load and store instructions with immediate offset can use the following addressing modes:

Offset addressing The offset value is added to or subtracted from the address obtained from the register Rn . The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is:

[ Rn , # offset ]

Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn . The result is used as the address for the memory access and written back into the register Rn . The assembly language syntax for this mode is:

[ Rn , # offset ]!

Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn .

The assembly language syntax for this mode is:

[ Rn ], # offset

The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned.

The following table shows the ranges of offset for immediate, pre-indexed and post-indexed forms.

Table 45. Offset ranges

Instruction type

Two words

Immediate offset

Word, halfword, signed halfword, byte, or signed byte

−255 to 4095 multiple of 4 in the range −1020 to 1020

Pre-indexed

−255 to 255 multiple of 4 in the range

−1020 to 1020

Post-indexed

−255 to 255 multiple of 4 in the range

−1020 to 1020

Restrictions

•

For load instructions:

• Rt can be SP or PC for word loads only.

Rt must be different from Rt2 for two-word loads.

Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

When Rt is PC in a word load instruction:

• Bit[0] of the loaded value must be 1 for correct execution.

• A branch occurs to the address created by changing bit[0] of the loaded value to 0.

• If the instruction is conditional, it must be the last instruction in the IT block.

For store instructions:

• Rt can be SP for word stores only.

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Memory access instructions op

LDR

‑ cond

STR type

3.12.3

•

Rt must not be PC.

Rn must not be PC.

Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

Condition flags

These instructions do not change the flags.

LDR R8, [R10] ; Loads R8 from the address in R10.

LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word

; 960 bytes above the address in R5, and

; increments R5 by 960.

STR R2, [R9,#const ‑ struc] ; const ‑ struc is an expression evaluating

; to a constant in the range 0 ‑ 4095.

STRH R3, [R4], #4 ; Store R3 as halfword data into address in

; R4, then increment R4 by 4.

LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the

; address in R3, and load R9 from a word 36

; bytes above the address in R3.

STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to

; a word 4 bytes above the address in R8,

; and then decrement R8 by 16.

LDR and STR, register offset

Load and Store with register offset.

op { type }{ cond } Rt , [ Rn , Rm {, LSL # n }]

Where:

Is one of:

Load Register.

Store Register.

Is one of:

Unsigned byte, zero extend to 32 bits on loads.

Signed byte, sign extend to 32 bits ( LDR only).

Unsigned halfword, zero extend to 32 bits on loads.

Signed halfword, sign extend to 32 bits ( LDR only).

omit, for word.

Is an optional condition code.

Is the register to load or store.

Is the register on which the memory address is based.

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Memory access instructions op

LDR

STR

LSL #n

3.12.4

Is a register containing a value to be used as the offset.

Is an optional shift, with n in the range 0-3.

Operation

LDR instructions load a register with a value from memory.

STR instructions store a register value into memory.

The memory address to load from or store to is at an offset from the register Rn . The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL .

The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned.

Restrictions

•

In these instructions:

• Rn must not be PC.

• Rm must not be SP and must not be PC.

Rt can be SP only for word loads and word stores.

Rt can be PC only for word loads.

When Rt is PC in a word load instruction:

• Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address.

• If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

STR R0, [R5, R1] ; Store value of R0 into an address equal to

; sum of R5 and R1.

LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to

; sum of R5 and two times R1, sign extended it

; to a word value and put it in R0.

STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1

; and four times R2.

LDR and STR, unprivileged

Load and Store with unprivileged access.

op { type }T{ cond } Rt , [ Rn {, # offset }]

Where:

Is one of:

Load Register.

Store Register.

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Memory access instructions type

‑ cond

Rn offset

3.12.5

Is one of:

Unsigned byte, zero extend to 32 bits on loads.

Signed byte, sign extend to 32 bits ( LDR only).

Unsigned halfword, zero extend to 32 bits on loads.

Signed halfword, sign extend to 32 bits ( LDR only).

Omit, for word.

Is an optional condition code.

Is the register to load or store.

Is the register on which the memory address is based.

Is an immediate offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn .

Operation

These load and store instructions perform the same function as the memory access instructions with immediate offset. The difference is that these instructions have only unprivileged access even when used in privileged software.

When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset.

Restrictions

In these instructions:

• Rn must not be PC.

• Rt must not be SP and must not be PC.

Condition flags

These instructions do not change the flags.

STRBTEQ R4, [R7] ; Conditionally store least significant byte in

; R4 to an address in R7, with unprivileged access.

LDRHT R2, [R2, #8] ; Load halfword value from an address equal to

; sum of R2 and 8 into R2, with unprivileged access.

LDR, PC

‑

relative

Load register from memory.

LDR{ type }{ cond } Rt , label

LDRD{ cond } Rt , Rt2 , label ; Load two words

Where:

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Memory access instructions

H type

‑ cond

Rt2 label

Note:

Is one of:

Unsigned byte, zero extend to 32 bits.

Signed byte, sign extend to 32 bits.

Unsigned halfword, zero extend to 32 bits.

Signed halfword, sign extend to 32 bits.

Omit, for word.

Is an optional condition code.

Is the register to load or store.

Is the second register to load or store.

Is a PC ‑ relative expression.

Operation

LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC.

The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned.

label must be within a limited range of the current instruction. The following table shows the possible offsets between label and the PC.

Table 46. Offset ranges

Instruction type

Word, halfword, signed halfword, byte, signed byte

Two words

Offset range

−4095 to 4095

−1020 to 1020

You might have to use the .W

suffix to get the maximum offset range.

Restrictions

•

In these instructions:

• Rt can be SP or PC only for word loads.

Rt2 must not be SP and must not be PC.

Rt must be different from Rt2 .

When Rt is PC in a word load instruction:

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Memory access instructions

3.12.6

•

Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address.

If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

LDR R0, LookUpTable ; Load R0 with a word of data from an address

; labelled as LookUpTable.

LDRSB R7, localdata ; Load a byte value from an address labelled

; as localdata, sign extend it to a word

; value, and put it in R7.

LDM and STM

Load and Store Multiple registers.

op { addr_mode }{ cond } Rn {!}, reglist

Where: op

Is one of:

LDM

Load Multiple registers.

STM

Store Multiple registers.

addr_mode

Is any one of the following:

Increment address After each access. This is the default.

Decrement address Before each access.

cond

Is an optional condition code.

Is the register on which the memory addresses are based.

Is an optional write-back suffix. If !

is present the final address, that is loaded from or stored to, is written back into Rn .

reglist

Is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.

LDMIA and LDMFD are synonyms for LDM . LDMFD refers to its use for popping data from Full Descending stacks.

LDMEA is a synonym for LDMDB , and refers to its use for popping data from Empty Ascending stacks.

STMIA and STMEA are synonyms for STM . STMEA refers to its use for pushing data onto Empty Ascending stacks.

STMFD is a synonym for STMDB , and refers to its use for pushing data onto Full Descending stacks.

Operation

LDM instructions load the registers in reglist with word values from memory addresses based on Rn .

STM instructions store the word values in the registers in reglist to memory addresses based on Rn .

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Memory access instructions cond

Rn imm

3.12.7

For LDM , LDMIA , LDMFD , STM , STMIA , and STMEA the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn + 4 * ( n -1), where n is the number of registers in reglist . The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the write-back suffix is specified, the value of Rn +

4 * ( n -1) is written back to Rn .

For LDMDB , LDMEA , STMDB , and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * ( n -1), where n is the number of registers in reglist . The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the write-back suffix is specified, the value of Rn - 4 *

( n -1) is written back to Rn .

The PUSH and POP instructions can be expressed in this form.

Restrictions

•

In these instructions:

• Rn must not be PC.

reglist must not contain SP.

In any STM instruction, reglist must not contain PC.

In any LDM instruction, reglist must not contain PC if it contains LR.

reglist must not contain Rn if you specify the write-back suffix.

When PC is in reglist in an LDM instruction:

•

Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address

If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM.

STMDB R1!,{R3 ‑ R6,R11,R12}

Incorrect examples

STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable.

LDM R2, {} ; There must be at least one register in the list.

PLD

Preload Data.

PLD{ cond } [ Rn {, #imm }] ; Immediate

PLD{ cond } [ Rn , Rm {, LSL #shift }] ; Register

PLD{ cond } label ; Literal

Where:

Is an optional condition code.

Is the base register.

Is the + or - immediate offset used to form the address. This offset can be omitted, meaning an offset of 0.

Is the optionally shifted offset register.

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Memory access instructions shift label

3.12.8

cond reglist

Specifies the shift to apply to the value read from <Rm> , in the range 0-3. If this option is omitted, a shift by 0 is assumed.

The label of the literal item that is likely to be accessed in the near future.

Operation

PLD signals the memory system that data memory accesses from a specified address are likely in the near future.

If the address is cacheable then the memory system responds by pre-loading the cache line containing the specified address into the data cache. If the address is not cacheable, or the data cache is disabled, this instruction behaves as no operation.

Restrictions

There are no restrictions.

Condition flags

These instructions do not change the flags.

PUSH and POP

Push registers onto, and pop registers off a full-descending stack.

PUSH { cond } reglist

POP { cond } reglist

Where:

Is an optional condition code.

Is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.

PUSH and POP are synonyms for STMDB and LDM (or LDMIA ) with the memory addresses for the access based on

SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred mnemonics in these cases.

Operation

PUSH stores registers on the stack, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address.

POP loads registers from the stack, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address.

PUSH uses the value in the SP register minus four as the highest memory address, POP uses the value in the SP register as the lowest memory address, implementing a full-descending stack. On completion, PUSH updates the

SP register to point to the location of the lowest store value, POP updates the SP register to point to the location above the highest location loaded.

If a POP instruction includes PC in its reglist, a branch to this location is performed when the POP instruction has completed. Bit[0] of the value read for the PC is used to update the APSR T-bit. This bit must be 1 to ensure correct operation.

Restrictions

In these instructions:

• reglist must not contain SP.

• For the PUSH instruction, reglist must not contain PC.

• For the POP instruction, reglist must not contain PC if it contains LR.

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Memory access instructions op

LDA

STL type cond

3.12.9

When PC is in reglist in a POP instruction:

• Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address.

• If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack

PUSH {R2,LR} ; Push R2 and the link-register onto the stack

POP {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to the new PC.

LDA and STL

Load-Acquire and Store-Release.

op { type }{ cond } Rt , [ Rn ]

Where:

Is one of:

Load-Acquire Register.

Store-Release Register.

Is one of:

Unsigned byte, zero extend to 32 bits on loads.

Unsigned halfword, zero extend to 32 bits on loads..

Is an optional condition code.

Is the register to load or store.

Is the register on which the memory address is based.

Operation

LDA , LDAB , and LDAH loads word, byte, and halfword data respectively from a memory address. If any loads or stores appear after a load-acquire in program order, then all observers are guaranteed to observe the loadacquire before observing the loads and stores. Loads and stores appearing before a load-acquire are unaffected.

STL , STLB , and STLH stores word, byte, and halfword data respectively to a memory address. If any loads or stores appear before a store-release in program order, then all observers are guaranteed to observe the loads and stores before observing the store-release. Loads and stores appearing after a store-release are unaffected.

In addition, if a store-release is followed by a load-acquire, each observer is guaranteed to observe them in program order.

There is no requirement that a load-acquire and store-release be paired.

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Memory access instructions cond

Rn offset

3.12.10

Note:

All store-release operations are multi-copy atomic, meaning that in a multiprocessing system, if one observer observes a write to memory because of a store-release operation, then all observers observe it. Also, all observers observe all such writes to the same location in the same order.

Restrictions

The address specified must be naturally aligned, or an alignment fault is generated.

The PC must not use SP for Rt .

Condition flags

These instructions do not change the flags.

LDREX and STREX

Load and Store Register Exclusive.

LDREX{ cond } Rt , [ Rn {, # offset }]

STREX{ cond } Rd , Rt , [ Rn {, # offset }]

LDREXB{ cond } Rt , [ Rn ]

STREXB{ cond } Rd , Rt , [ Rn ]

LDREXH{ cond } Rt , [ Rn ]

STREXH{ cond } Rd , Rt , [ Rn ]

Where:

Is an optional condition code.

Is the destination register for the returned status.

Is the register to load or store.

Is the register on which the memory address is based.

Is an optional offset applied to the value in Rn . If offset is omitted, the address is the value in Rn .

Operation

LDREX , LDREXB , and LDREXH load a word, byte, and halfword respectively from a memory address.

STREX , STREXB , and STREXH attempt to store a word, byte, and halfword respectively to a memory address. The address used in any Store-Exclusive instruction must be the same as the address in the most recently executed

Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a Loadexclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation.

If a Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is guaranteed that no other process in the system has accessed the memory location between the Load-exclusive and Store-Exclusive instructions.

For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and Store-

Exclusive instruction to a minimum.

The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding Load-Exclusive instruction is unpredictable.

Restrictions

In these instructions:

• Do not use PC.

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Memory access instructions cond

STLEX type

3.12.11

•

Do not use SP for Rd and Rt .

For STREX , Rd must be different from both Rt and Rn .

The value of offset must be a multiple of four in the range 0-1020.

Condition flags

These instructions do not change the flags.

MOV R1, #0x1 ; Initialize the ‘lock taken’ value try

LDREX R0, [LockAddr] ; Load the lock value

CMP R0, #0 ; Is the lock free?

ITT EQ ; IT instruction for STREXEQ and CMPEQ

STREXEQ R0, R1, [LockAddr] ; Try and claim the lock

CMPEQ R0, #0 ; Did this succeed?

BNE try ; No – try again

.... ; Yes – we have the lock.

LDAEX and STLEX

Load-Acquire and Store Release Exclusive.

op { type } Rt , [ Rn ]

Where:

Is one of:

LDAEX

Load Register.

Store Register.

Is one of:

Unsigned byte, zero extend to 32 bits on loads.

Unsigned halfword, zero extend to 32 bits on loads..

is an optional condition code.

is the destination register for the returned status.

is the register to load or store.

is the register on which the memory address is based.

Operation

Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and:

• If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing core in a global monitor.

• Causes the core that executes to indicate an active exclusive access in the local monitor.

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Memory access instructions

Note:

3.12.12

cond

• If any loads or stores appear after LDAEX in program order, then all observers are guaranteed to observe the

LDAEX before observing the loads and stores. Loads and stores appearing before LDAEX are unaffected.

Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory If the executing core has exclusive access to the memory addressed:

• Rd is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the Rd field. The value returned is:

If the operation updates memory.

•

If the operation fails to update memory.

If any loads or stores appear before STLEX in program order, then all observers are guaranteed to observe the loads and stores before observing the store-release. Loads and stores appearing after STLEX are unaffected.

All store-release operations are multi-copy atomic.

Restrictions

In these instructions:

• Do not use PC.

• Do not use SP for Rd and Rt .

• For STLEX , Rd must be different from both Rt and Rn .

Condition flags

These instructions do not change the flags.

lock

MOV R1, #0x1 ; Initialize the ‘lock taken’ value try

LDAEX R0, [LockAddr] ; Load the lock value

CMP R0, #0 ; Is the lock free?

BNE try ; No – try again

STREX R0, R1, [LockAddr] ; Try and claim the lock

CMP R0, #0 ; Did this succeed?

BNE try ; No – try again

; Yes – we have the lock.

unlock

MOV r1, #0

STL r1, [r0]

CLREX

Clear Exclusive.

CLREX{ cond }

Where:

Is an optional condition code.

Operation

Use CLREX to make the next STREX , STREXB , or STREXH instruction write 1 to its destination register and fail to perform the store. CLREX enables compatibility with other Arm Cortex processors that have to force the failure of the store exclusive if the exception occurs between a load-exclusive instruction and the matching store-exclusive instruction in a synchronization operation. In Cortex-M processors, the local exclusive access monitor clears automatically on an exception boundary, so exception handlers using CLREX are optional.

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Condition flags

This instruction does not change the flags.

CLREX

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Memory access instructions

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Cortex®-M33 peripherals

4

4.1

Cortex

-M33 peripherals

About the Cortex®-M33 peripherals

The address map of the Private peripheral bus (PPB) is:

RAZ

Privileged

Table 47. Core peripheral register regions

Address

0xE000E000-0xE000E00F

Core peripheral

0xE000ED00-0xE000ED8F

System control and ID registers

0xE000EDF0-0xE000EEFF

0xE000EF00-0xE000EF8F

0xE000E010-0xE000E0FF System timer

0xE000E100-0xE000ECFF

Nested Vectored Interrupt Controller registers

Description

Includes the Interrupt Controller Type and Auxiliary

Control registers

Section 4.3 System Control Block

Debug registers in the SCS

Includes the SW Trigger Interrupt Register

Section 4.4 System timer, SysTick

Section 4.2 Nested Vectored Interrupt Controller

0xE000ED00-0xE000EDEF Security Attribution Unit

0xE000ED90-0xE000EDB8 Memory Protection Unit

0xE000EF30-0xE000EF44 Floating-Point Unit

Section 4.5.1 Security Attribution Unit

Section 4.5.9 Memory Protection Unit

Section 4.6 Floating-Point Unit

1. Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a Memory Protection Unit (MPU).

• The register type is described as follows:

Read and write.

•

Read-only.

Write-only.

Read As Zero.

Write Ignored.

The required privilege gives the privilege level that is required to access the register, as follows:

Only privileged software can access the register.

Unprivileged

•

Note:

Both unprivileged and privileged software can access the register.

The peripheral registers are banked in Secure and Non-secure state. The Non-secure registers can be accessed in Secure state by using an aliased address at offset 00020000 from the normal register address.

The alias locations are always RAZ/WI if accessed from Non-secure state.

Attempting to access a privileged register from unprivileged software results in a BusFault.

4.2

Nested Vectored Interrupt Controller

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.

The NVIC supports:

• 1-480 interrupts.

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4.2.1

•

A programmable priority level of 0-255. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. In Non-secure state, the priority also depends on the value of AIRCR.PRIS.A

programmable priority level of 0-255. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.

Level and pulse detection of interrupt signals.

Interrupt tail-chaining.

An external Non-Maskable Interrupt

Late arriving interrupts.

(NMI).

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling.

The following table shows the hardware implementation of NVIC registers. In an implementation with the Security

Extension, register fields that are associated with interrupts designated as Secure in the ITNS register are always

RAZ/WI if accessed from Non-secure state.

Table 48. NVIC registers summary

Address Name Type

Required privilege

Reset value Description

0xE000E100 0xE000E13C

NVIC_ISER0-

NVIC_ISER15

0XE000E180 - 0xE000E1BC

NVIC_ICER0-

NVIC_ICER15

0XE000E200 - 0xE000E23C

NVIC_ISPR0-

NVIC_ISPR15

0XE000E280 - 0xE000E2BC

NVIC_ICPR0-

NVIC_ICPR15

0xE000E300 0xE000E33C

NVIC_IABR0-

NVIC_IABR15

0xE000E380 0xE000E3BC

NVIC_ITNS0-

NVIC_ITNS15

0xE000E400 0xE000E5DC

NVIC_IPR0-

NVIC_IPR119

0xE000EF00 STIR

RW Privileged

Section 4.2.2 Interrupt Set

Privileged

RW Privileged

Configurable (2)

0x00000000

Enable Registers

0x00000000

Section 4.2.3 Interrupt

Clear Enable Registers

0x00000000

Section 4.2.4 Interrupt Set

Pending Registers - Cortex-

M33

0x00000000

Section 4.2.8 Interrupt

Clear Pending Registers

0x00000000

Section 4.2.5 Interrupt

Active Bit Registers

0x00000000

Section 4.2.6 Interrupt

Target Non-secure

Registers .

0x00000000

Section 4.2.7 Interrupt

Priority Registers

0x00000000

Section 4.2.9 Software

Trigger Interrupt Register

1. ITNS is RAZ/WI from the Non-Secure state.

2. See the register description for more information.

Accessing the NVIC registers using CMSIS

CMSIS functions enable software portability between different Cortex ‑ M profile processors.

To access the NVIC registers when using CMSIS, use the following functions:

Table 49. CMSIS access NVIC functions

CMSIS function void NVIC_SetPriorityGrouping (uint32_t

PriorityGroup) uint32_t NVIC_GetPriorityGrouping (void) void NVIC_EnableIRQ (IRQn_Type IRQn) uint32_t NVIC_GetEnableIRQ (IRQn_Type IRQn)

Description

Set priority grouping

Read the priority grouping

Enable a device-specific interrupt

Get a device-specific interrupt enable status.

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Note:

4.2.2

CMSIS function void NVIC_DisableIRQ (IRQn_Type IRQn) uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn) void NVIC_SetPendingIRQ (IRQn_Type IRQn) void NVIC_ClearPendingIRQ (IRQn_Type IRQn) uint32_t NVIC_GetActive (IRQn_Type IRQn) void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority) uint32_t NVIC_GetPriority (IRQn_Type IRQn) uint32_t NVIC_EncodePriority (uint32_t

PriorityGroup, uint32_t PreemptPriority, uint32_t

SubPriority) void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) uint32_t NVIC_GetVector (IRQn_Type IRQn) void NVIC_SetVector (IRQn_Type IRQn, uint32_t vector) void NVIC_SystemReset (void) uint32_t NVIC_GetTargetState (IRQn_Type IRQn) uint32_t NVIC_SetTargetState (IRQn_Type IRQn uint32_t NVIC_ClearTargetState (IRQn_Type IRQn)

Description

Disable a device-specific interrupt

Get the pending device-specific interrupt

Set a device-specific interrupt to pending

Clear a device-specific interrupt from pending

Get the device-specific interrupt active

Set the priority for an interrupt

Get the priority of an interrupt

Encodes priority

Decode the interrupt priority

Read interrupt vector

Modify interrupt vector

Reset the system

Get interrupt target state

Set interrupt target state

Clear interrupt target state

The input parameter IRQn is the IRQ number. For more information on CMSIS NVIC functions, see http://armsoftware.github.io/CMSIS_5/Core/html/group__NVIC__gr.html

Interrupt Set Enable Registers

The NVIC_ISER0-NVIC_ISER15 registers enable interrupts, and show which interrupts are enabled.

See the register summary in Section 4.2 Nested Vectored Interrupt Controller

for the register attributes.

These registers are not banked between Security states. The register bits can be RAZ/WI depending on the value of NVIC_ITNS.

The bit assignments are:

31 0

SETENA

Table 50. NVIC_ISERn bit assignments

Bits Name

[31:0] SETENA.

Function

Interrupt set-enable bits. For SETENA[m] in NVIC_ISERn, allows interrupt 32n + m to be accessed.

Write:

No effect.

1 Enable interrupt 32n+m.

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Bits Name

Read:

Function

Interrupt 32n+m disabled.

Interrupt 32n+m enabled.

If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.

The register bits can be RAZ/WI depending on the value of NVIC_ITNS

Interrupt Clear Enable Registers

The NVIC_ICER0-NVIC_ICER15 registers disable interrupts, and show which interrupts are enabled.

See the register summary in Section 4.2 Nested Vectored Interrupt Controller

for the register attributes.

The register bits can be RAZ/WI from Non-secure state depending on the value of NVIC_ITNS.

These registers are not banked between Security states.

The bit assignments are:

31 0

CLRENA

4.2.4

Bits Name

Table 51. NVIC_ICERn bit assignments

Function

Interrupt clear-enable bits. For SETENA[m] in NVIC_ICERn, allows interrupt 32n + m to be accessed.

Write:

0 No effect.

Disable interrupt 32n+m.

[31:0] CLRENA

Read:

0 Interrupt 32n+m disabled.

1 Interrupt 32n+m enabled.

Interrupt Set Pending Registers - Cortex-M33

The NVIC_ISPR0-NVIC_ISPR15 registers force interrupts into the pending state, and shows which interrupts are pending.

See the register summary in Section 4.2 Nested Vectored Interrupt Controller

for the register attributes.

The register bits can be RAZ/WI from Non-secure state depending on the value of NVIC_ITNS.

These registers are not banked between Security states.

The bit assignments are:

31 0

SETPEND

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4.2.5

Bits Name

Table 52. NVIC_ISPRn bit assignments

Function

Interrupt set-pending bits. For SETPEND[m] in NVIC_ISPRn, allows interrupt 32n + m to be accessed.

Write:

[31:0] SETPEND

Read:

No effect.

Pend interrupt 32n + m.

Interrupt 32n + m is not pending.

Interrupt 32n + m pending.

Writing 1 to the NVIC_ISPR bit corresponding to:

• An interrupt that is pending has no effect.

• A disabled interrupt sets the state of that interrupt to pending.

Interrupt Active Bit Registers

The NVIC_IABR0-NVIC_IABR15 registers indicate the active state of each interrupt.

See the register summary in Section 4.2 Nested Vectored Interrupt Controller

for the register attributes.

The register bits can be RAZ/WI depending on the value of NVIC_ITNS.

These registers are not banked between Security states.

The bit assignments are:

31 0

ACTIVE

4.2.6

Bits Name

Table 53. NVIC_IABRn bit assignments

Function

Active state bits. For ACTIVE[m] in NVIC_IABRn, indicates the active state for interrupt 32n+m.

[31:0] ACTIVE 0 The interrupt is not active.

1 The interrupt is active.

Interrupt Target Non-secure Registers

The NVIC_ITNS0-NVIC_ITNS15 determine, for each group of 32 interrupts, whether each interrupt targets Nonsecure or Secure state. Otherwise, This register is RAZ/WI

See the register summary in Section 4.2 Nested Vectored Interrupt Controller

for the register attributes.

This register is accessible from Secure state only.

The bit assignments are:

31 0

ITNS

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Table 54. NVIC_ITNSn bit assignments

Bits Name Function

Interrupt Targets Non-secure bits. For ITNS[m] in NVIC_ITNSn, this field indicates and allows modification of the target Security state for interrupt 32n+m.

[31:0] ITNS

0 The interrupt targets Secure state.

1 The interrupt targets Non-secure state.

Interrupt Priority Registers

The NVIC_IPR0-NVIC_IPR119 registers provide an 8-bit priority field for each interrupt. These registers are word, halfword, and byte accessible.

See the register summary in Section 4.2 Nested Vectored Interrupt Controller

for their attributes.

Each register holds four priority fields as shown:

31 24 23 16 15 8 7 0

NVIC_IPR 119 PRI_ 479 PRI_ 478 PRI_ 477 PRI_ 476

NVIC_IPR n PRI_( 4n+3 ) PRI_( 4n+2 ) PRI_( 4n+1 ) PRI_( 4n )

NVIC_IPR0 PRI_3 PRI_2 PRI_1 PRI_0

Bits Name

[31:24]

Priority, byte offset

[23:16]

Priority, byte offset

[15:8]

[7:0]

Priority, byte offset

Table 55. NVIC_IPRn bit assignments

Function

Each priority field holds a priority value. The priority depends on the value of PRIS for exceptions targeting the Non-secure state. If the processor implements fewer than 8 bits of priority, then the least significant bits of this field are res0 . Each priority field holds a priority value. The lower the value, the greater the priority of the corresponding interrupt. If the processor implements fewer than 8 bits of priority, then the least significant bits of this field are res0 .

See

Section 4.2.1 Accessing the NVIC registers using CMSIS for more information about the access to the

interrupt priority array, which provides the software view of the interrupt priorities.

Find the NVIC_IPR number and byte offset for interrupt M as follows:

• The corresponding NVIC_IPR number, N , is given by N = N DIV 4.

• The byte offset of the required Priority field in this register is M MOD 4, where:

– Byte offset 0 refers to register bits[7:0].

– Byte offset 1 refers to register bits[15:8].

– Byte offset 2 refers to register bits[23:16].

– Byte offset 3 refers to register bits[31:24].

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Priority values depend on the value of PRIS.

The register bits can be RAZ/WI depending on the value of NVIC_ITNS.

These registers are not banked between Security states.

Interrupt Clear Pending Registers

The NVIC_ICPR0-NVIC_ICPR15 registers remove the pending state from interrupts, and shows which interrupts are pending.

See the register summary in Section 4.2 Nested Vectored Interrupt Controller

for the register attributes.

The register bits can be RAZ/WI depending on the value of NVIC_ITNS.

These registers are not banked between Security states.

The bit assignments are:

31 0

CLRPEND

Note:

4.2.9

Note:

Bits Name

Table 56. NVIC_ICPRn bit assignments

Function

Interrupt clear-pending bits.

Write:

[31:0] CLRPEND

Read:

No effect.

Clear pending state of interrupt 32n + m.

Interrupt 32n + m is not pending.

Interrupt 32n + m is pending.

Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.

Software Trigger Interrupt Register

Write to the STIR to generate an interrupt from software.

When the USERSETMPEND bit in the CCR is set to 1, unprivileged software can access the STIR.

Only privileged software can enable unprivileged access to the STIR.

See

Section 4.2 Nested Vectored Interrupt Controller for the register attributes.

This register is not banked between Security states.

The bit assignments are:

31 9 8 0

RES 0 INTID

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4.2.10

4.2.10.1

4.2.11

Table 57. STIR bit assignments

Bits Field

[31:9] Reserved, res0 .

Function

[8:0] INTID

Interrupt ID of the interrupt to trigger, in the range 0-479. For example, a value of 0x03 specifies interrupt

IRQ3.

Level-sensitive and pulse interrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edgetriggered interrupts.

A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure that the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.

When the processor enters the ISR, it automatically removes the pending state from the interrupt.

For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.

See <reference required> for details of which interrupts are level-sensitive and which are pulsed.

•

Hardware and software control of interrupts

The processor latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:

The NVIC detects that the interrupt signal is active and the corresponding interrupt is not active.

The NVIC detects a rising edge on the interrupt signal.

• Software writes to the corresponding Interrupt Set Enable Register bit.

A pending interrupt remains pending until one of the following occurs:

• The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active.

Then:

– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately reenter the ISR. Otherwise, the state of the interrupt changes to inactive.

– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately reenter the

ISR.

•

If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive.

Software writes to the corresponding Interrupt Clear Pending Register bit.

For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive.

For a pulse interrupt, state of the interrupt changes to:

– Inactive, if the state was pending.

– Active, if the state was active and pending.

NVIC usage hints and tips

Ensure that software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers.

An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.

Before programming VTOR to relocate the vector table, ensure that the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions like interrupts.

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4.3

4.3.1

NVIC programming hints

Software uses the CPSIE i and CPSID i instructions to enable and disable interrupts.

The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts

In addition, the CMSIS provides functions for NVIC control, listed in Section 4.2.1 Accessing the NVIC registers using CMSIS .

The input parameter IRQn

is the IRQ number, see Section 2.4.2 Exception types

for more information. For more information about these functions, see the CMSIS documentation.

System Control Block

The System Control Block (SCB) provides system implementation information and system control that includes configuration, control, and reporting of system exceptions.

The system control block registers are:

Table 58. Summary of the system control block registers

Address Name

E000E008 ACTLR

E000ED00 CPUID

Type

Required privilege

Reset value

Description

Privileged 00000000

Section 4.3.3 Auxiliary Control Register

Privileged 0x410FD214

Section 4.3.4 CPUID Base Register

E000ED04 ICSR

E000ED08 VTOR

E000ED0C AIRCR

E000ED10 SCR

E000ED14 CCR

E000ED18 SHPR1

E000ED1C SHPR2

Section 4.3.5 Interrupt Control and State Register

Privileged 00000000

RW Privileged UNKNOWN

Section 4.3.6 Vector Table Offset Register

Section 4.3.7 Application Interrupt and Reset Control Register

Privileged FA050000

Privileged 00000000

Privileged 0x00000201

Section 4.3.8 System Control Register

Section 4.3.9 Configuration and Control Register

Privileged 00000000

Privileged

Section 4.3.10.1 System Handler Priority Register 1

00000000

Section 4.3.10.2 System Handler Priority Register 2

E000ED20 SHPR3 RW

E000ED24 SHCSR RW

E000ED28 CFSR RW

Privileged 00000000

Section 4.3.10.3 System Handler Priority Register 3

Section 4.3.11 System Handler Control and State Register

Section 4.3.12 Configurable Fault Status Register

E000ED28 MMFSR (2)

E000ED29 BFSR (2)

E000ED2A UFSR

(2)

E000ED2C HFSR

Privileged 00

Privileged 0000

Privileged 00000000

Section 4.3.12.1 MemManage Fault Status Register

Section 4.3.12.2 BusFault Status Register

Section 4.3.12.3 UsageFault Status Register

Section 4.3.13 HardFault Status Register

E000ED34 MMFAR RW

E000ED38 BFAR

E000ED3C AFSR

RAZ/WI Privileged -

E000ED8C NSACR RW

Privileged UNKNOWN

Section 4.3.15 BusFault Address Register

Privileged UNKNOWN

Section 4.3.14 MemManage Fault Address Register

Auxiliary Fault Status Register not implemented

Section 4.3.2 Non-secure Access Control Register

1. See the register description for more information.

2. A subregister of the CFSR.

Coprocessor Access Control Register

The CPACR register specifies the access privileges for the FPU.

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See System control block registers summaryReference information for the SCB registers. for the CPACR attributes.

In an implementation with the Security Extension, this field is banked between Security states.

The CPACR bit assignments are:

RES 0

24 23 22 21 20 19

CP11 CP10 RES0

4.3.2

Table 59. CPACR bit assignments

Bits Name

[31:24] -

[23:22] CP11

Function

Reserved, res0

CP11 Privilege. The value in this field is ignored.

If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN.

CP10 Privilege. Defines the access rights for the floating-point functionality.

The possible values of this bit are:

00 All accesses to the FP Extension result in NOCP UsageFault.

[21:20] CP10 01 Unprivileged accesses to the FP Extension result in NOCP UsageFault.

[19:0] -

11 Full access to the FP Extension.

All other values are reserved.

The features controlled by this field are the execution of any floating-point instruction and access to any floating-point registers D0-D16.

Reserved, res0

Non-secure Access Control Register

The NSACR register defines the Non-secure access permissions for the FPU.

See the System control block registers summaryReference information for the SCB registers. for the NSACR attributes.

This field is not banked between Security states.

The NSACR bit assignments are:

31 12 11 10 9 8 7 0

RES 0 RES 0

CP10

CP11

[31:12]

[11]

Bits

Table 60. NSACR bit assignments

Name

CP11

Function

Reserved, res0 .

CP11 access. Enables Non-secure access to the Floating-point Extension.

Programming with a different value other than that used for CP10 is

UNPREDICTABLE .

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[10]

Bits

CP10

Name Function

CP10 access. Enables Non-secure access to the Floating-point Extension.

Non-secure accesses to the

Floating-point Extension generate a NOCP

UsageFault.

Non-secure access to the

Floating-point Extension permitted.

Reserved, res0 [9:0] -

Auxiliary Control Register

The ACTLR provides disable bits for the FPU exception outputs, dual-issue functionality, flushing of the trace output from the ITM and DWT, Exclusive instruction control, out-of-order floating point instructions, and handling interruptible instructions.

By default, this register is set to provide optimum performance from the Cortex ‑ M33 processor and does not normally require modification.

See System control block registers summaryReference information for the SCB registers. for the ACTLR attributes.

This register is banked between Security states.

The ACTLR bit assignments are:

31 30 29 28

UNK/SBZP

13 12 11 10 9 8

UNK/SBZP

3 2 1 0

EXTEXCLALL

UNK/SBZP

DISITMATBFLUSH

UNK/SBZP

FPEXCODIS

DISOOFP

DISFOLD

UNK/SBZP

DISMCYCINT

Bits

[31:30] -

Name

Table 61. ACTLR bit assignments

Function

Reserved, UNK/SBZP

Normal operation. Memory requests on Code region AHB (C-AHB) or

System AHB (S-AHB) interfaces associated with LDREX and STREX instructions only assert HEXCL and respond to HEXOKAY if the address is shareable.

[29] EXTEXCLALL

All memory requests on C-AHB or S-AHB interfaces associated with

LDREX and STREX instructions assert HEXCL and respond to

HEXOKAY irrespective of the shareable attribute associated with the address.

[28:13] -

[12]

Setting EXTEXCLALL allows external exclusive operations to be used in a configuration with no

MPU. This is because the default memory map does not include any shareable Normal memory.

Reserved. UNK/SBZP

DISITMATBFLUSH Disables ITM and DWT ATB flush:

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Bits

[11]

[10]

[9]

[8:3] -

[2]

[1] -

Name

FPEXCODIS

DISOOFP

DISFOLD

Normal operation.

Function

ITM and DWT ATB flush disabled. AFVALID is ignored and AFREADY is held HIGH.

Reserved. UNK/SBZP

Disables FPU exception outputs:

0 Normal operation.

1 FPU exception outputs are disabled.

Disables floating-point instructions completing out of order with respect to the non-floating point instructions:

0 Normal operation.

Reserved. UNK/SBZP

Floating-point instructions completing out of order are disabled.

Disables dual-issue functionality:

0 Normal operation.

Dual-issue functionality is disabled. Setting this bit reduces performance.

Reserved. UNK/SBZP

Disables interruption of multi-cycle instructions:

0 Normal operation.

[0] DISMCYCINT

Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor because load, store, multiply, and divide operations complete before interrupt stacking occurs.

CPUID Base Register

The CPUID Base Register contains the processor part number, version, and implementation information.

See System control block registers summaryReference information for the SCB registers. for the CPUID attributes.

This register is not banked between Security states.

The bit assignments are:

31 24 23 20 19 16 15 4 3 0

Implementer Variant Constant PartNo Revision

Table 62. CPUID bit assignments

Bits Name Function

[31:24] Implementer

Implementer code:

[23:20] Variant

0x41 Arm

Variant number, the n value in the r n p m product revision identifier:

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4.3.5

Bits Name Function

[19:16] Constant

Reads as 0xF

Revision 0

Part number of the processor:

[15:4] PartNo

D21 Cortex ‑ M33

Revision number, the m value in the r n p m product revision identifier:

[3:0] Revision

2 Patch 2.

Interrupt Control and State Register

•

The ICSR provides a set-pending bit for the non-maskable interrupt exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions.

The ICSR indicates:

• The exception number of the exception being processed.

Whether there are pre-empted active exceptions.

The exception number of the highest priority pending exception

• Whether any interrupts are pending.

See System control block registers summaryReference information for the SCB registers. for the ICSR attributes.

This register is banked between Security states on a bit by bit basis.

The ICSR bit assignments are:

PENDNMISET

PENDNMICLR

RES 0

PENDSVSET

PENDSVCLR

PENDSTSET

31 30 29 28 27 26 25 24 23 22 21 20

VECTPENDING

RES 0

ISRPENDING

Reserved for Debug use

STTNS

PENDSTCLR

12 11 10 9 8

VECTACTIVE

RES 0

RETTOBASE

[31]

Bits

Table 63. ICSR bit assignments with the Security Extension

Name type Function

NMI set-pending bit.

Write:

PENDNMISET

Read:

No effect.

Changes NMI exception state to pending.

0 NMI exception is not pending.

1 NMI exception is pending.

A read of this bit by the NMI exception handler returns

1 only if the NMI signal is reasserted while the processor is executing that handler.

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[30]

[29]

[28]

[27]

[26]

Bits

Name

PENDNMICLR

PENDSVSET

PENDSVCLR

PENDSTSET

PM0264

System Control Block type Function

If AIRCR.BFHFNMINS is zero this bit is RAZ/WI from

Non-secure state.

This bit is not banked between Security states.

Pend NMI clear bit.

Write:

0 No effect.

WO 1 Clear pending status.

This bit is write-one-to-clear. Writes of zero are ignored.

If AIRCR.BFHFNMINS is zero this bit is RAZ/WI from

Non-secure state.

This bit is not banked between Security states.

Reserved, RES0

PendSV set-pending bit.

Write:

RW Read:

No effect.

Changes PendSV exception state to pending.

0 PendSV exception is not pending.

1 PendSV exception is pending.

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

This bit is banked between Security states.

PendSV clear-pending bit.

Write:

0 No effect.

Removes the pending state from the

PendSV exception.

This bit is banked between Security states.

SysTick exception set-pending bit.

Write:

No effect.

Read:

Changes SysTick exception state to pending.

0 SysTick exception is not pending.

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Bits

PM0264

System Control Block

Name

PENDSTCLR

STTNS

Reserved for Debug use

ISRPENDING

VECTPENDING

RETTOBASE

VECTACTIVE (1)

type

Function

SysTick exception is pending.

This bit is banked between Security states.

SysTick exception clear-pending bit.

Write:

0 No effect.

Removes the pending state from the

SysTick exception.

This bit is WO. On a register read, its value is

UNKNOWN.

This bit is not banked between Security states.

RO RES0

This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.

Interrupt pending flag, excluding NMI and Faults:

0 Interrupt not pending.

1 Interrupt not pending.

This bit is not banked between Security states.

Reserved, RES0

Indicates the exception number of the highest priority pending enabled exception:

0 No pending exceptions.

Nonzero

The exception number of the highest priority pending enabled exception.

The value that this field indicates includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.

This field is not banked between Security states.

Indicates whether there are pre-empted active exceptions:

There are pre-empted active exceptions to execute.

There are no active exceptions, or the currently executing exception is the only active exception.

This bit is not banked between Security states.

Reserved, RES0

Contains the active exception number:

Thread mode.

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PM0264

System Control Block

4.3.6

Note:

4.3.7

Bits Name type

Function

The exception number