ST EVAL6470H, EVAL6470PD, EVAL6472H and EVAL6472PD: fully integrated microstepping motor drivers User Manual

PDF

Document

UM1688

User manual

EVAL6470H, EVAL6470PD, EVAL6472H and EVAL6472PD: fully integrated microstepping motor drivers

Introduction

The EVAL6470H, EVAL6470PD, EVAL6472H and EVAL6472PD are four demonstration boards based on the L6470 and L6472 devices implementing a complete stepper motor driver solution. They are designed for operate with a supply voltage ranging from 8 V to 45 V and can drive up to 3 A r.m.s.

for each phase.

In combination with the STEVAL-PCC009V2 demonstration board and the SPINFamily evaluation tool, the boards provide a complete and easy to use evaluation environment allowing the user to investigate all the features of the L6470 and L6472 devices. Both the boards support the daisy chain configuration making them suitable for the evaluation of the devices in multi motor applications.

April 2015 DocID025471 Rev 2 1/41 www.st.com

Contents

UM1688

Boards description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

EVAL6470H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

EVAL6470H - thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2

EVAL6470PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

EVAL6470PD - thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.3

EVAL6472H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

EVAL6472H - thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.4

EVAL6472PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

EVAL6472PD - thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Evaluation environment setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.1

Voltage mode driving (EVAL6470H/PD) . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2

Advanced current control (EVAL6472H/PD) . . . . . . . . . . . . . . . . . . . . . . 37

3.3

Overcurrent and stall detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . 37

3.4

Speed profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

How to change the supply configuration of the board . . . . . . . . . . . . 39

Daisy chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2/41 DocID025471 Rev 2

UM1688

List of tables

List of tables

EVAL6470H - specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

EVAL6470H - jumpers and connectors description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

EVAL6470H - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

EVAL6470H - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

EVAL6470H - bill of material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

EVAL6470PD - specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

EVAL6470PD - jumper and connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

EVAL6470PD - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9.

EVAL6470PD - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 10.

EVAL6470PD - bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11.

EVAL6472H - specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12.

EVAL6472H - jumpers and connectors description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13.

EVAL6472H - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14.

EVAL6472H - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15.

EVAL6472H - bill of material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 16.

EVAL6472PD - specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17.

EVAL6472PD - jumper and connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18.

EVAL6472PD - master SPI connector pinout (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19.

EVAL6472PD - slave SPI connector pinout (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20.

EVAL6472PD - bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 21.

Device supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 22.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DocID025471 Rev 2 3/41

List of figures

List of figures

UM1688

Figure 1.

EVAL6470H - jumpers and connectors location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

EVAL6470H - schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.

EVAL6470H - layout (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.

EVAL6470H - layout (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5.

EVAL6470H - layout (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

EVAL6470H - layout (bottom layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7.

EVAL6470H - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8.

EVAL6470PD - jumper and connector location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9.

EVAL6470PD - schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10.

EVAL6470PD - layout (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11.

EVAL6470PD - layout (inner layer 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.

EVAL6470PD - layout (inner layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13.

EVAL6470PD - layout (bottom layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.

EVAL6470PD - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15.

EVAL6472H - jumpers and connectors location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16.

EVAL6472H - schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17.

EVAL6472H - layout (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18.

EVAL6472H - layout (inner layer2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 19.

EVAL6472H - layout (inner layer3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 20.

EVAL6472H - layout (bottom layer3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21.

EVAL6472H - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 22.

EVAL6472PD - jumper and connector location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 23.

EVAL6472PD - schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 24.

EVAL6472PD - layout (inner layer2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 25.

EVAL6472PD - layout (inner layer3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 26.

EVAL6472PD - layout (bottom layer3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 27.

EVAL6472PD - thermal impedance graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4/41 DocID025471 Rev 2

UM1688 Boards description

1.1 EVAL6470H

Parameter

Table 1. EVAL6470H - specifications

Value

Supply voltage (VS)

Maximum output current (each phase)

Logic supply voltage (VREG)

Logic interface voltage (VDD)

Low level logic inputs voltage

High level logic input voltage

Operating temperature

L6470H thermal resistance junction to ambient

1. All logic inputs are 5 V tolerant.

8 to 45 V

3 A r.m.s.

Externally supplied: 3.3 V, internally supplied: 3 V

(typ.)

Externally supplied: 3.3 V or 5 V, internally supplied: VREG

0 V

VDD

(1)

-25 to +125 °C

21 °C/W (typ.)

Figure 1. EVAL6470H - jumpers and connectors location

#64:-&%

"NCFS

'-"(-&%

.BTUFS41*

DPOOFDUPS

3FE

&YUFSOBMTXJUDIDPOOFDUPS

48JOQVU

.PUPSTVQQMZWPMUFHF

DPNQFOTBUJPO

QBSUJUJPOJOHSFHVMBUJPO

"%$*/JOQVU

1IBTF"DPOOFDUPS

"QQMJDBUJPOSFGFSFODF

BSFB

1PXFSTVQQMZDPOOFDUPS

+17%%TVQQMZGSPN

NBTUFS41*DPOOFDUPS

+1%BJTZDIBJO

UFSNJOBUJPO

4MBWF41*

DPOOFDUPS

+17%%UP73&(

DPOOFDUJPO

1IBTF#DPOOFDUPS

04$*/04$065

DPOOFDUPS

$0Y

DocID025471 Rev 2 5/41

Boards description UM1688

Name

TP1 (VS)

TP4 (VDD)

TP5 (VREG)

TP6 (GND)

TP2 (STCK)

TP3 (STBY/RES)

TP7 (FLAG)

TP8 (BUSY/SYNC)

Table 2. EVAL6470H - jumpers and connectors description

Type Function

Power supply

Power output

SPI connector

NM connector

Test point

Motor supply voltage

Bridge A outputs

Bridge B outputs

Master SPI

Slave SPI

OSCIN and OSCOUT pins

External switch input

Motor supply voltage test point

Logic interface supply voltage test point

Logic supply voltage/L6470 internal regulator test point

Ground test point

Step-clock input test point

Standby/reset input test point

FLAG output test point

BUSY/SYNC output test point

Pin number

Table 3. EVAL6470H - master SPI connector pinout (J10)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6470 BUSY/SYNC output

L6470 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to L6470 SDO output through daisy-chain termination jumper JP2)

SPI serial clock signal (connected to L6470 CK input)

SPI master OUT slave IN signal (connected to L6470 SDI input)

SPI slave select signal (connected to L6470 CS input)

L6470 step-clock input

L6470 STBY/RST input

6/41 DocID025471 Rev 2

UM1688

Pin number

Boards description

Table 4. EVAL6470H - slave SPI connector pinout (J11)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6470 BUSY/SYNC output

L6470 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to pin 5 of J10)

SPI serial clock signal (connected to L6470 CK input)

SPI master OUT slave IN signal (connected to L6470 SDO output)

SPI slave select signal (connected to L6470 CS input)

L6470 step-clock input

L6470 STBY/RST input

DocID025471 Rev 2 7/41

Boards description

& X)9

Figure 2. EVAL6470H - schematic

$ $ % %

& X)9

&$ X)9

& Q)9

96%

96$

9%227

95(*

9''

3*1'

$*1'

(3$'

'*1'

& Q)9

& S)9

& Q)9

UM1688

$0Y

8/41 DocID025471 Rev 2

Item

UM1688 Boards description

Quantity

Table 5. EVAL6470H - bill of material

Reference Value

C2,C4

C7, C8, C15, C16

C9A

C10, C11, C12

C13

C14

DL1

DL2

JP1

JP2, JP3

J1, J5, J6

J2,J3

J4,J7

220 nF/16 V

100 nF/6.3 V

10 µF/6.3 V

47 µF/6.3 V

10 nF/50 V

100 nF/50 V

100 µF/63 V

100 pF/6.3 V

3.3 nF/6.3 V

10 nF/6.3 V

LED diode (red)

LED diode (amber)

BAV99

BZX585-B3V6(1)

Jumper - OPEN

Jumper - CLOSED

Screw connector 2 poles

Pol. IDC male header vertical 10 poles

N.M.

31.6 k 

CON-FLAT-5X2-180M

R4, R5, R6

R7, R9

TP1, TP2, TP3, TP4, TP5,

TP6, TP7, TP8

Test point

200 k 

8.2 k 

39 k 

470 

100 

L6470

Package

CAPC-0603

CAPC-3216

CAPC-0603

CAPE-R8H12-P35

CAPES-R10HXX

CAPC-0603

LEDC-0805

SOT23

SOD523

JP2SO

MORSV-508-2P

STRIP254P-M-2

RESC-0603

TRIMM-100X50X110-

64W

RESC-0603

HTSSOP28

DocID025471 Rev 2 9/41

Boards description

Figure 3. EVAL6470H - layout (top layer)

UM1688

Figure 4. EVAL6470H - layout (inner layer 2)

$0Y

10/41 DocID025471 Rev 2

$0Y

UM1688

Figure 5. EVAL6470H - layout (inner layer 3)

Boards description

Figure 6. EVAL6470H - layout (bottom layer)

$0Y

DocID025471 Rev 2

$0Y

11/41

Boards description

EVAL6470H - thermal data

Figure 7. EVAL6470H - thermal impedance graph

Zth

1 10

Time(seconds)

100 1000

AM11339v1

UM1688

1.2 EVAL6470PD

Parameter

Table 6. EVAL6470PD - specifications

Supply voltage (VS)

Maximum output current (each phase)

Logic supply voltage (VREG)

Logic interface voltage (VDD)

Low level logic input voltage

High level logic input voltage

Operating temperature

L6470PD thermal resistance junction to ambient

1. All logic inputs are 5 V tolerant.

Value

8 to 45 V

3 A r.m.s.

Externally supplied: 3.3 V internally supplied: 3 V typical

Externally supplied: 3.3 V or 5 V internally supplied: VREG

0 V

VDD

(1)

-25 to +125 °C

12 °C/W typical

12/41 DocID025471 Rev 2

UM1688

Figure 8. EVAL6470PD - jumper and connector location

Boards description

AM11330v1

DocID025471 Rev 2 13/41

Boards description UM1688

Name

CN1

CN2

CN3

CN4

TP1 (VS)

TP2 (VDD)

TP3 (VREG)

TP5 (GND)

TP6 (GND)

TP8 (STCK)

TP9 (STBY/RES)

TP10 (FLAG)

TP11 (BUSY/SYNC)

Table 7. EVAL6470PD - jumper and connector description

Type Function

Power supply

Power output

SPI connector

NM connector

Test point

Motor supply voltage

Bridge A outputs

Bridge B outputs

Master SPI

Slave SPI

OSCIN and OSCOUT pins

External switch input

Motor supply voltage test point

Logic interface supply voltage test point

Logic supply voltage/L6470 internal regulator test point

Ground test point

Step-clock input test point

Standby/reset input test point

FLAG output test point

BUSY/SYNC output test point

Pin number

Table 8. EVAL6470PD - master SPI connector pinout (J10)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6470 BUSY/SYNC output

L6470 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to the L6470 SDO output through the daisy chain termination jumper JP2)

SPI serial clock signal (connected to L6470 CK input)

SPI master OUT slave IN signal (connected to L6470 SDI input)

SPI slave select signal (connected to L6470 CS input)

L6470 step-clock input

L6470 STBY/RST input

14/41 DocID025471 Rev 2

UM1688

Pin number

Boards description

Table 9. EVAL6470PD - slave SPI connector pinout (J11)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6470 BUSY/SYNC output

L6470 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to pin 5 of J10)

SPI serial clock signal (connected to L6470 CK input)

SPI master OUT slave IN signal (connected to L6470 SDO output)

SPI slave select signal (connected to L6470 CS input)

L6470 step-clock input

L6470 STBY/RST input

DocID025471 Rev 2 15/41

Boards description

Figure 9. EVAL6470PD - schematic

1A 2A 1B 2B

UM1688

VSB

VSA

VBOOT

VREG

VDD

PGND

AGND

DGND

E_PAD

16/41

3 1

DocID025471 Rev 2

AM12921v1

UM1688 Boards description

Index Quantity

Table 10. EVAL6470PD - bill of material

Reference Value Package

CN1

CN2

CN3, CN4

C1A

C2, C14, C15, C1

C4, C6

C9, C10

C11

C12

C13

DL1

DL2

JP1

JP2, JP3

M1, M2, M3

R3, R4, R5

R6, R7

TP1, TP2, TP3, TP5, TP6,

TP8, TP9, TP10, TP11

TR1

Pol. IDC male header vertical 10 poles

(black)

Pol. IDC male header vertical 10 poles

(gray)

N. M.

100 µF/63 V (option)

100 µF/63 V

100 nF/50 V

10 nF/50 V

100 nF/6.3 V

47 µF/6.3 V

10 µF/6.3 V

220 nF/16 V

100 pF/6.3 V

CON-FLAT-5X2-180M

STRIP254P-M-2

CAPE-R10HXX-P5

CAPES-R10HXX

CAPC-0603

CAPC-1206

CAPC-0805

CAPC-0603

1 nF/6.3 V

3.3 nF/6.3 V

10 nF/6.3 V

LED red

LED amber

BAV99

BZX585-B3V6

Jumper OPEN

CAPC-0603

LEDC-0805

SOT23

SOD523

JP2SO

Jumper CLOSED JP2SO

Screw connector 2 poles MORSV-508-2P

31.6 k  RESC-0603

8.2 k  RESC-0603

39 k 

470 k 

10 k 

RESC-0603

TPTH-RING-1MM

200 k 

L6470

TRIMM-100x50x110-64W

PowerSO36

DocID025471 Rev 2 17/41

Boards description

Figure 10. EVAL6470PD - layout (top layer)

UM1688

Figure 11. EVAL6470PD - layout (inner layer 2)

AM12923v1

18/41 DocID025471 Rev 2

AM12924v1

UM1688

Figure 12. EVAL6470PD - layout (inner layer 3)

Boards description

Figure 13. EVAL6470PD - layout (bottom layer

AM12925v1

DocID025471 Rev 2

AM12926v1

19/41

Boards description

EVAL6470PD - thermal data

Figure 14. EVAL6470PD - thermal impedance graph

Zth

1 10 100

Time (seconds)

1000

10000

AM11337v1

UM1688

20/41 DocID025471 Rev 2

UM1688 Boards description

1.3 EVAL6472H

Table 11. EVAL6472H - specifications

Parameter Value

Supply voltage (VS)

Maximum output current (each phase)

Logic supply voltage (VREG)

Logic interface voltage (VDD)

Low level logic input voltage

High level logic input voltage

Operating temperature

L6472H thermal resistance junction to ambient

1. All logic inputs are 5 V tolerant.

8 to 45 V

3 A r.m.s.

Externally supplied: 3.3 V

Internally supplied: 3 V typical

Externally supplied: 3.3 V or 5 V

Internally supplied: VREG

0 V

VDD

(1)

-25 to +125 °C

21 °C/W typical

Figure 15. EVAL6472H - jumpers and connectors location

FLAG LED

(Red) Application reference area

Power supply connector

(8 V - 45 V)

BUSY LED

(Amber)

Master SPI connector

JP1: VDD supply from master SPI connector

JP3: Daisy chain termination

Slave SPI connector

External switch connector

(SW input)

Motor supply voltage compensation partitioning regulation

(ADCIN input)

Phase A connector Phase B connector

JP2: VDD to VREG connection

OSCIN/OSCOUT connector

AM10289V1

DocID025471 Rev 2 21/41

Boards description UM1688

Name

CN1

CN2

CN3

CN4

TP1 (VS)

TP2 (VDD)

TP3 (VREG)

TP5 (GND)

TP6 (GND)

TP8 (STCK)

TP9 (STBY/RES)

TP10 (FLAG)

TP11 (BUSY/SYNC)

Table 12. EVAL6472H - jumpers and connectors description

Type Function

Power supply

Power output

SPI connector

NM connector

Test point

Motor supply voltage

Bridge A outputs

Bridge B outputs

Master SPI

Slave SPI

OSCIN and OSCOUT pins

External switch input

Motor supply voltage test point

Logic interface supply voltage test point

Logic supply voltage/L6470 internal regulator test point

Ground test point

Step-clock input test point

Standby/reset input test point

FLAG output test point

BUSY/SYNC output test point

Pin number

Table 13. EVAL6472H - master SPI connector pinout (J10)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6472 BUSY output

L6472 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to L6472 SDO output through daisy chain termination jumper JP2)

SPI serial clock signal (connected to L6472 CK input)

SPI master OUT slave IN signal (connected to L6472 SDI input)

SPI slave select signal (connected to L6472 CS input)

L6472 step-clock input

L6472 standby/reset input

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Pin number

Boards description

Table 14. EVAL6472H - slave SPI connector pinout (J11)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6472 BUSY output

L6472 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to pin 5 of J10)

SPI serial clock signal (connected to L6472 CK input)

SPI master OUT slave IN signal (connected to L6472 SDO output)

SPI slave select signal (connected to L6472 CS input)

L6472 step-clock input

L6472 standby/reset input

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Boards description

C5 47uF/6V3

Figure 16. EVAL6472H - schematic

1B 2B 1A 2A

1 2

C3 10uF/6V3

UM1688

24/41

1 2

CK nCS

MISO SDO

CK nCS

MISO SDI

C9A 100uF/63V

C6 10nF/50V

VSB

VSA

VBOOT

VREG

VDD

R6 39k

R4 39k

R5 39k

C10 100pF/6V3

PGND

AGND

EPAD

DGND

R8 100

1 2

C14 10nF/6V3

C13 3.3nF/6V3

C12 100pF/6V3

R1 31k6

3 1

R3 8k2

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AM10295V1

UM1688 Boards description

Index Quantity

19 2

Table 15. EVAL6472H - bill of material

Reference Value

C2, C4

C7, C8, C15, C16

C9A

C10, C11, C12

C13

C14

DL1

DL2

JP1

JP2, JP3

J1, J5, J6

J2,J3

J4, J7

R4, R5, R6

R7, R9

TP1, TP2, TP3, TP4,

TP5, TP7, TP8

TP6

220 nF/16 V

100 nF/6.3 V

10 µF/6.3 V

47 µF/6.3 V

10 nF/50 V

100 nF/50 V

100 µF/6.3 V (option)

100 µF/6.3 V

100 pF/6.3 V

3.3 nF/6.3 V

10 nF/6.3 V

LED diode (red)

LED diode (amber)

BAV99

BZX585-B3V6

Jumper - open

Jumper - closed

Screw connector 2 poles

Pol. IDC male header vertical 10 poles

31.6 k 

200 k 

8.2 k 

39 k 

470 

100 

TPTH-ring-1 mm red

TPTH-ring-1 mm black

L6472

Package

CAPC-0603

CAPC-3216

CAPC-0603

CAPE-R10HXX-P5

CAPES-R10HXX

CAPC-0603

LEDC-0805

SOT23

SOD323

JP2SO

MORSV-508-2P

CON-FLAT-5X2-180M

STRIP254P-M-2

RESC-0603

TRIMM-100X50X110-64W

RESC-0603

HTSSOP28

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Boards description

Figure 17. EVAL6472H - layout (top layer)

UM1688

Figure 18. EVAL6472H - layout (inner layer2)

AM10290V1

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AM10291V1

UM1688

Figure 19. EVAL6472H - layout (inner layer3)

Boards description

Figure 20. EVAL6472H - layout (bottom layer3)

AM10292V1

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AM10293V1

27/41

Boards description

EVAL6472H - thermal data

Figure 21. EVAL6472H - thermal impedance graph

1 10

100

Time (sec)

UM1688

1000

AM10294V1

1.4 EVAL6472PD

Table 16. EVAL6472PD - specifications

Parameter Value

Supply voltage (VS)

Maximum output current (each phase)

Logic supply voltage (VREG)

Logic interface voltage (VDD)

Low level logic input voltage

High level logic input voltage

Operating temperature

L6472PD thermal resistance junction to ambient

1. All logic inputs are 5 V tolerant.

8 to 45 V

3 A r.m.s.

Externally supplied: 3.3 V

Internally supplied: 3 V typical

Externally supplied: 3.3 V or 5 V

Internally supplied: VREG

0 V

VDD

(1)

-25 to +125 °C

12 °C/W typical

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UM1688 Boards description

Figure 22. EVAL6472PD - jumper and connector location

FLAG LED

(Red)

BUSY LED

(Amber)

Application reference area

Power supply connector

(8 V - 45 V)

Master SPI connector

JP1: VDD supply from master SPI connector

JP3: Daisy chain termination

Slave SPI connector

JP2: VDD to VREG connection

ADCIN input OSCIN/OSCOUT connector

External switch connector

(SW input)

Phase A connector Phase B connector

AM14850v1

Name

Table 17. EVAL6472PD - jumper and connector description

Type Function

CN1

CN2

CN3

CN4

TP1 (VS)

TP2 (VDD)

TP3 (VREG)

TP5 (GND)

TP6 (GND)

TP8 (STCK)

TP9 (STBY/RES)

TP10 (FLAG)

TP11 (BUSY/SYNC)

Power supply

Power output

SPI connector

NM connector

Test point

Motor supply voltage

Bridge A outputs

Bridge B outputs

Master SPI

Slave SPI

OSCIN and OSCOUT pins

External switch input

Motor supply voltage test point

Logic interface supply voltage test point

Logic supply voltage/L6472 internal regulator test point

Ground test point

Step-clock input test point

Standby/reset input test point

FLAG output test point

BUSY/SYNC output test point

DocID025471 Rev 2 29/41

Boards description

Pin number

UM1688

Table 18. EVAL6472PD - master SPI connector pinout (J10)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6472 BUSY output

L6472 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to L6472 SDO output through daisy chain termination jumper JP2)

SPI serial clock signal (connected to L6472 CK input)

SPI master OUT slave IN signal (connected to L6472 SDI input)

SPI slave select signal (connected to L6472 CS input)

L6472 step-clock input

L6472 standby/reset input

Pin number

Table 19. EVAL6472PD - slave SPI connector pinout (J11)

Type Description

Open drain output

Ground

Supply

Digital output

Digital input

L6472 BUSY output

L6472 FLAG output

Ground

EXT_VDD (can be used as external logic power supply)

SPI master IN slave OUT signal (connected to pin 5 of J10)

SPI serial clock signal (connected to L6472 CK input)

SPI master OUT slave IN signal (connected to L6472 SDO output)

SPI slave select signal (connected to L6472 CS input)

L6472 step-clock input

L6472 standby/reset input

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UM1688

Figure 23. EVAL6472PD - schematic

1A 2A 1B 2B

Boards description

VSB

VSA

VBOOT

VREG

VDD

PGND

AGND

DGND

E_PAD

3 1

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AM14851v1

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Boards description UM1688

Index Quantity

CN3, CN4

C1A

C2, C14, C15, C16

C4, C6

C9, C10

C11

C12

C13

JP1

DL2

JP1

JP2,JP3

M1, M2, M3

R3, R4, R5

R6, R7

TP1, TP2, TP3, TP8,

TP9, TP10, TP11

TP5, TP6

TR1

Table 20. EVAL6472PD - bill of material

Reference Value

CN1

CN2

Pol. IDC male header vertical 10 poles (black)

Pol. IDC male header vertical 10 poles (gray)

N.M

100 µF/63 V

100 nF/50 V

10 nF/50 V

100 nF/6.3 V

47  F/6.3 V

10  F/6.3 V

220 nF/16 V

100 pF/6.3 V

1 nF/6.3 V

3.3 nF/6.3 V

10 nF/6.3 V

LED red

LED amber

BAV99

BZX585-B3V6

Jumper OPEN

Jumper CLOSED

Screw connector 2 poles

31.6 k 

8.2 k 

39 k 

470 

10 k 

TPTH-ring-1 mm (red)

TPTH-ring-1 mm (black)

200 k 

L6472

Package

CON-FLAT-5X2-180M

STRIP254P-M-2

CAPE-R10HXX-P5

CAPES-R10HXX

CAPC-0603

CAPC-1206

CAPC-0805

CAPC-0603

LEDC-0805

SOT23

SOD523

JP2SO

MORSV-508-2P

RESC-0603

TRIMM-100x50x110-64W

PowerSO36

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Figure 24. EVAL6472PD - layout (inner layer2)

Boards description

Figure 25. EVAL6472PD - layout (inner layer3)

AM14854v1

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AM14855v1

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Boards description

Figure 26. EVAL6472PD - layout (bottom layer3)

UM1688

AM14856v1

EVAL6472PD - thermal data

Figure 27. EVAL6472PD - thermal impedance graph

Zth

Zth 6

1 10

100

Time (seconds)

1000 10000

AM14857v1

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UM1688

2 Evaluation environment setup

Evaluation environment setup

The evaluation environment is composed by:

 One or more EVAL6470H\PD or EVAL6472H\PD.

 One STEVAL-PCC009V2 demonstration board.

 A USB cable.

 A stepper motor with a small mechanical load (unloaded stepper motors suffer of strong resonance issues).

 A power supply with an output voltage within the operative range of the evaluation board.

 A Windows ® 7 or Windows XP PC with a free USB port.

 The SPINFamily evaluation tool (the last version can be downloaded from the

STMicroelectronics

website).

In order to start using the evaluation environment the following steps are required:

Install the SPINFamily evaluation tool

2. Start the SPINFamily evaluation tool (by default it is in Start menu > All programs >

STMicroelectronics > SPINFamily Evaluation Tool).

3. Select the proper device when requested by the application.

4. Plug the STEVAL-PCC009V2 demonstration board to a free USB port.

5. Wait a few seconds for board initialization.

6. Connect the SPI_IN connector (black) of the demonstration board to the 10-pin connector of the STEVAL-PCC009V2 board using the provided cable.

For connecting more devices to the same board, please consult the daisy chain connection paragraph (

Section 5: Daisy chaining on page 40 ).

7. Power-up the demonstration boards. The FLAG LED should turn on.

8. Click on the button with the USB symbol to connect the STEVAL-PCC009V2 board to the PC and initialize the evaluation environment.

The application automatically identifies the number of demonstration boards connected.

9. The evaluation environment is ready.

Before start working with the demonstration board, the device must be configured according

to the indications in Section 3: Device configuration .

Warning: Important - the device configuration is mandatory. The default configuration is not operative.

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Device configuration UM1688

This section offers an overview of the basic configuration steps which are required for make the demonstration board operative.

Warning: Important - the device configuration is mandatory. The default configuration is not operative.

Important - before changing the device configuration verify that the device is in high impedance status (power stage is disabled).

3.1 Voltage mode driving (EVAL6470H/PD)

The configuration parameters of the voltage mode driving can be obtained through the

BEMF compensation tool embedded into the SPINFamily software.

A wrong setup of these parameters could cause several issues, in particular:

 The phase current decreases with the speed and the motor will stall.

 The wrong voltage is applied to the motor and the system is very noisy.

 The phase current reaches the overcurrent limit.

The BEMF compensation form uses the application parameters as inputs in order to evaluate the proper device setup.

The required inputs are:

 Supply voltage.

 Target phase current (r.m.s. value) at different motion conditions (acceleration, deceleration, constant speed and holding).

 Target operating speed (maximum speed).

 Motor characteristics.

The motor characteristics are: electrical constant (Ke), phase inductance and resistance.

The inductance and the resistance of the phase are given in the motor datasheet. The Ke is rarely given in the specification and must be measured.

In the help section of the SPINFamily software a step by step procedure is explained. The same procedure can also be found in the application note “AN4144: Voltage mode control operation and parameter optimization” on www.st.com.

Click on the “evaluate” button to get the suggested setup for the voltage mode driving. Then click on “write” button to copy the data in the registers of the device.

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UM1688 Device configuration

3.3

The following configuration gives good results with most of motors:

 Minimum ON time = 4 µs.

 Minimum OFF time = 21 µs.

 Max. fast decay = 10 µs.

 Max. fast decay at step change = 16 µs.

 Target switching time = 48 µs.

 Predictive current control enabled.

The impact of the timing parameters are explained in the application note “AN4158: Peak current control with automatic decay adjustment and predictive current control: basics and setup”.

The target phase current is set through the TVAL registers. The TVAL determinates the current corresponding to the peak of the sine wave (microstepping operation).

Overcurrent and stall detection thresholds

The overcurrent protection and the stall detection (EVAL6470H\PD only) are implemented measuring the current flowing into each integrated MOSFET.

The overcurrent protection threshold should be set just above the current rating of the motor:

OCDth

> I max,r.m.s.

√

For example: if the maximum phase current of the motor is 2 A r.m.s.

protection should be set to about 3 A.

, the overcurrent

Warning: Important - it is strongly discouraged to disable the overcurrent shutdown. It may result in critical failures.

The stall detection threshold should be just above the operating peak current of the application. During the preliminary stages of evaluation, it can be set to the maximum value.

The max. speed parameter is the maximum speed the motor will run. By default, it is about

1000 step/s. That means, if you send a command to run at 2000 step/s, the motor speed is limited at 1000 step/s.

This is an important safety feature in the final application, but not necessarily useful to evaluate the device performances. Setting the parameter to high values (e.g. 6000 step/s) allows evaluating the maximum speed which can be achieved by the application under test through the speed tracking command (Run), but it probably limits the possibility to use positioning commands (Move, GoTo, etc.).

DocID025471 Rev 2 37/41

Device configuration UM1688

The Full-step speed parameter indicates the speed at which the system switches from microstepping to full step operation.

In voltage mode driving devices (EVAL6470H\PD), it is always recommended to operate in microstepping and not to switch to full step. Hence, this parameter should be greater than the maximum speed.

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4

How to change the supply configuration of the board

How to change the supply configuration of the board

The configuration of the supply voltages can be changed through the jumpers from J1 to J6 as listed in

Table 21 .

Table 21. Device supply configurations

Configuration

Logic supplied by the integrated voltage regulator and VDD shorted to VREG.

Logic supplied by the integrated voltage regulator and VDD floating.

Logic supplied by the integrated voltage regulator and VDD supplied through the

SPI connector.

Logic and VDD supplied through the SPI connector.

JP1 JP2

Open Closed

Open Open

Closed Open

Closed Closed

Logic levels

3.3 V logic compliant.

According to

VDD voltage.

According to

VDD voltage.

3.3 V logic compliant.

Notes

Default.

The VDD must be supplied through the respective test point.

The VDD must be supplied through the SPI connector.

The supply voltage from the SPI connector must be 3.3 V.

When VREG pin is supplied through an external voltage source, particular care must be taken in order to avoid that VS voltage falls below the VREG one (e.g. VS is floating and

VREG is supplied). In this case the internal ESD diode is turned on and the device could be damaged.

Adding a low drop diode between VREG and VS protects the internal ESD diode from this event.

DocID025471 Rev 2 39/41

Daisy chaining UM1688

Note:

More demonstration boards can be connected in daisy chain mode.

To drive two or more boards in daisy chain configuration:

Connect the STEVAL-PCC009V2 board 10-pin connector to the SPI_IN connector of the first demonstration board through the 10-pole flat cable.

2. Open the termination jumper (see Section 1.1: EVAL6470H on page 5 ,

Section 1.2:

EVAL6470PD on page 12

Section 1.3: EVAL6472H on page 21 and

Section 1.4:

EVAL6472PD on page 28

3. Connect the SPI_OUT connector of the first demonstration board to the SPI_IN of the next one through the 10-pole flat cable.

4. Repeat point 2 and 3 for all the others board of the chain but the last one.

5. Check the termination jumpers of the demonstration boards: all the jumpers but the last one should be opened.

Increasing the number of devices connected in chain could degrade SPI communication performances. If communication issues occur, try reducing the SPI clock speed.

Date

15-Nov-2013

16-Apr-2015

Table 22. Document revision history

Revision Changes

Initial release.

Updated Section : Introduction on page 1

(replaced

“dSPIN TM family devices” and “dSPIN TM” by “L6470 and

L6472 devices”).

Updated Section : Introduction on page 1

and Section 2:

Evaluation environment setup on page 35

(replaced

“SPIN family evaluation tool” by “SPINFamily evaluation tool”).

Removed Figure 3. EVAL6470H - layout (silk screen ) from page 10, Figure 11. EVAL6470PD - layout (silk screen) from page 18, Figure 19. EVAL6472H - silkscreen from page 26 , and Figure 27. EVAL6472PD - silkscreen from page 34.

Updated value in Table 5: EVAL6470H - bill of material on page 9

, and packages in Table 10: EVAL6470PD - bill of material on page 17

and Table 20: EVAL6472PD - bill of material on page 32 .

Minor modifications throughout document.

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UM1688

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DocID025471 Rev 2 41/41