BM63SPKA1MGA

BM63SPKA1MGA

Bluetooth 3.0 Digital Audio Output Module

5F, No.5, Industry E. Rd. VII, Hsinchu Science Park, Hsinchu city 30077, Taiwan, R.O.C

Phone: 886-3-577-8385

Version:1.2

10/15/2014

Fax: 886-3-577-850 1

BM63SPKA1MGA

Product Description

The ISSC BM63SPKA1MGA is a highly integrated Bluetooth 3.0 digital audio output module, designed for high data rate, short-range wireless communication in the 2.4 GHz ISM band. With the built-in ISSC Bluetooth stack, profiles and digital audio interface, the ISSC BM63SPKA1MGA can combine the external DSP and codec to provide high performance Bluetooth audio.

Features

 Main Chip: ISSC IS2063GM(Flash version)

 Bluetooth 3.0 compliant

 Max. +4dBm Class 2 output power

 Receiver Sensitivity: GFSK typical -89 dBm, π/4 PSK typical -90dBm,

8DPSK typical -83dBm

 Piconet and Scatter net support

 CVSD, A-law,



-law, mSBC CODEC algorithms for voice applications

 Support SONY new feature

 SBC/AAC decode for Bluetooth audio streaming

 Microphone input and audio line-in support

 Built-in four language voice prompt (Chinese/English/Spanish/French)

 Support PCM and I2S digital audio interface

 Built-in 350mAH Li-ion battery charger

 HSP 1.2, HFP 1.6, A2DP 1.2, AVRCP 1.5,SPP 1.0 profiles supported

 Support USB 1.1 DFU and BC1.2/Apple charger detection

USB BC1.2 charger detection for DCP/CDP/SDP

Apple Charger: 2.5W, 5W, 10W, 12.5W

 3.3V operating voltage

 Built-in program ROM and 64Kb EEPROM

 51 pins for SMT module Size: 15mmx32mm

 Built-in PCB Antenna

 RoHS compliant

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BM63SPKA1MGA

Module Pin Out Diagram

BM63SPKA1MGA

49

50

51

ANT1

ANT2

ANT3

10

11

12

8

9

6

7

1

2

3

4

5

13

14

15

16

17

18

19

DR0

RFS0

SCLK0

DT0

AOHPR

AOHPM

AOHPL

MICN1

MICP1

MICBIAS

AIR

AIL

P12

P13

RST_N

P01

P24

P04

P15

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

GND

P05

P30

P27

P20

P02

P31

P33

P36

DP

DM

EAN

P03

P00

P35

P37

GND

LED1

LED2

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4

5

6

7

1

2

3

8

9

10

11

12

BM63SPKA1MGA

Pin Definition for Flash module

Pin No. Pin type Name Description

13

14

15

16

17

18

19

20

21

22

23

I

O

O

DR0 I2S interface: Digital Left/Right Data from ADC

RFS0 I2S interface: DAC Left/Right Clock

SCLK0 I2S interface: Bit Clock

DT0 I2S interface: Digital Left/Right Data to DAC O

O

O

O

I

I

AOHPR R-channel analog headphone output

AOHPM Headphone common mode output/sense input.

AOHPL L-channel analog headphone output

MICN1

MICP1

MIC 1 mono differential analog negative input

MIC 1 mono differential analog positive input

P

I

I

I/O

I/O

I

I/O

I/O

MICBIAS Electric microphone biasing voltage

AIR R-channel single-ended analog input

AIL

P12

P13

RST_N

P01

P24

P04

L-channel single-ended analog input

GPIO, default pull-high input

1. KEY PIN for FT Test

2. EEPROM clock SCL

GPIO, default pull-high input

1. KEY PIN for FT Test

2. EEPROM data SDA

KEY PIN for FT Test

System Reset Pin (Low active)

GPIO, default pull-high input

BAT_CHK_EN

GPIO, default pull-high input

1. KEY PIN for FT Test

2. System Configuration:

H: Boot Mode

L: Boot Mode with P2_0 low combination

GPIO, default pull-high input. I/O

I/O

I

O

P15

HCI_RXD

HCI_TXD

GPIO, default pull-high input

KEY PIN for FT Test

1-bit serial data received from MCU through UART

KEY PIN for FT Test

1-bit serial data transmitted to MCU through UART

P CODEC_VO 3.1V LDO output for CODEC power

P VDD_IO I/O power supply input

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Pin No. Pin type Name

24 P ADAP_IN Power adaptor input

BM63SPKA1MGA

Description

31

32

33

25

26

27

28

29

30

34

35

36

37

38

39

40

41

42

43

44

45

46

I

P

I/O

P

P

P

I

I

I

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

BAT_IN Battery input

AMB_DET ADC analog input 1

SYS_PWR System Power Output

PWR(MFB) Multi-Function Push Button key

LED3 LED Driver 3

LED2 LED Driver 2

LED1 LED Driver 1

GND Ground Pin

P37

P35

P00

P03

EAN

DM

DP

P36

P33

P31

P02

P20

P27

P30

GPIO, default pull-high input

GPIO, default pull-high input (LF/ES samples)

Default pull-low input (CS/MP samples)

Charger Enable

GPIO, default pull-high input

UART TX_IND signal to wake up MCU

GPIO, default pull-high input

UART RX_IND signal to wake up BT

(Note: HCI_RXD can also be used to wake up BT)

Embedded ROM/External Flash enable

H: Embedded; L: External Flash

USB Differential data bus

Data -

USB Differential data bus

Data +

GPIO, default pull-high input

GPIO, default pull-high input

ICHG1

GPIO, default pull-high input

ICHG0

GPIO, default pull-high input

GPIO, default pull-high input

1. KEY PIN for FT Test

2. System Configuration,

H: Application

L: Baseband(IBDK Mode)

GPIO, default pull-high input

GPIO, default pull-high input

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BM63SPKA1MGA

Description Pin No. Pin type Name

47

48

I/O

P

P05

Line-in Detector

GPIO, default pull-high input

Charger Status

GND Ground Pin

49 P ANT1 Antenna modification point

50

51

P

P

ANT2 Antenna modification point

ANT3 Antenna modification point

Block Diagram

BT 3.0

Transceiver

Synthesizer

RF Transmitter

RF Receiver

XTAL + POR

I2S/PCM

Module

Audio Codec

Audio Digital Core

Stereo DAC

Stereo ADC

Anti-Pop

BUS

BT 3.0 Digital Core

Interrupts

Modem + MAC

ROM

MCU Core

DSP Core

DSP ROM/RAM

Common RAM

DMA Controller

Memory Controller

RAM

Flash

PMU

Power Switch

Battery Charger

BUCK

LDO

LED Driver * 2

SAR_ADC

Misc. PMU logic

HCI/UART

SPI

ULPC 32KHz

GPIOs (Buttons)

I2C (GPIOs or H/W)

External

MCU

Buttons

EEPROM

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BM63SPKA1MGA

Digital Audio Interface

 Support I2S and PCM interface

 Sampling Rate : 8K, 16K, 44.1K, 48K, 88.2K, 96K

 Word Length: 16 bits, 24 bits

 4 application modes

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BM63SPKA1MGA

Mode 1: I2S Master

External CODEC/DSP

DAC

ADC

BCLK

ADCLRC

DACLRC

ADCDAT

DACDAT

Slave

BM63

SCLK0

RFS0

TFS0

DR0

DT0

A2DP/SCO

LineIn

Master

SCO

ADC

1/fs

SCLK0

RFS0

Left Channel Right Channel

DR0/DT0

B n-1

B n-2

B

1

B

0

B n-1

B n-2

Word Length or

 Solutions with mic and line-in analog input with I2S audio output



Mic for Bluetooth SCO link

 Line-in for external audio playback(for high SNR requirement)

B

1

B

0

External CODEC/DSP

DAC

BCLK

ADCLRC

DACLRC

ADCDAT

DACDAT

LineIn

Slave

BM63

SCLK0

RFS0

TFS0

DR0

DT0

Master

A2DP/SCO

SCO

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BM63SPKA1MGA

Mode 2: I2S Slave

External CODEC/DSP

DAC

ADC

BCLK

ADCLRC

DACLRC

ADCDAT

DACDAT

Master

BM63

SCLK0

RFS0

TFS0

DR0

DT0

LineIn

Slave

A2DP/SCO

SCO

ADC

1/fs

SCLK0

RFS0

Left Channel Right Channel

DR0/DT0

B n-1

B n-2

B

1

B

0

B n-1

B n-2

Word Length or

 Solutions with mic and line-in analog input with I2S audio output



Mic for Bluetooth SCO link

 Line-in for external audio playback(for high SNR requirement)

External CODEC/DSP BM63

B

1

B

0

DAC

BCLK

ADCLRC

DACLRC

ADCDAT

DACDAT

SCLK0

RFS0

TFS0

DR0

DT0

A2DP/SCO

SCO

LineIn

Master Slave

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BM63SPKA1MGA

Mode 3: PCM master

External CODEC/DSP

DAC

ADC

BCLK

ADCLRC

DACLRC

ADCDAT

DACDAT

Slave

BM63

SCLK0

RFS0

TFS0

DR0

DT0

A2DP/SCO

LineIn

Master

SCO

ADC

1/fs

SCLK0

RFS0

DR0/DT0

B n-1

B n-2

Left Channel

B

1

B

0

B n-1

B

Right Channel n-2

B

1

B

0

Word Length

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BM63SPKA1MGA

Mode 4: PCM slave

External CODEC/DSP

DAC

ADC

BCLK

ADCLRC

DACLRC

ADCDAT

DACDAT

Master

BM63

SCLK0

RFS0

TFS0

DR0

DT0

LineIn

Slave

A2DP/SCO

SCO

ADC

1/fs

SCLK0

RFS0

DR0/DT0

B n-1

B n-2

Left Channel

B

1

B

0

B n-1

B

Right Channel n-2

B

1

B

0

Word Length

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BM63SPKA1MGA

Outline Dimension (Module Foot print)

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BM63SPKA1MGA

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BM63SPKA1MGA

Electrical Characteristics

Table 1: Absolute Maximum Voltages

Storage Temperature

ESD: Human Body Mode

ESD: Machine Mode

ESD: Charge Device Mode

Core supply voltage

RF supply voltage

Min Max

-40ºC +85ºC

± 2KV

± 200V

± 200V

VDD_CORE, AVDD_PLL 1.14V 1.26V

VCC_RF 1.22V 1.34V

SAR supply voltage AVDD_SAR

Codec supply voltage VDD_AUDIO

I/O voltage VDD_IO

1.62V 1.98V

2.7V 3.0V

3.6V

BK_VDD 4.5V

3V1_VIN 4.5V

Supply voltage

BAT_IN

ADAP_IN

LED

Power switch

Table 2: Recommended Operating Conditions

Storage Temperature

Core supply voltage

RF supply voltage

3.0

4.5

4.5V

7.0V

5.1V

7.0V

Min Typ Max

-10ºC +25ºC +60ºC

VDD_CORE, AVDD_PLL 1.14V 1.2V 1.26V

VCC_RF 1.22V 1.28V 1.34V

SAR supply voltage AVDD_SAR 1.62V 1.8V 1.98V

Codec supply voltage VDD_AUDIO

I/O voltage VDD_IO

BK_VDD

3V1_VIN

Supply voltage

BAT_IN

ADAP_IN

LED

Power switch

2.7V

2.7V

3V

3V

3V

4.5V

1.8V

3.0V

3.0V

3.3V

4.3V

4.3V

4.3V

6.0V

4.3V 5.0V

6.0V

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BM63SPKA1MGA

Table 3: BUCK switching regulator

Normal Operation

Operation Temperature

Input Voltage (V

IN

)

Output Voltage (V

OUT

)

(I

LOAD

=70mA, V

IN

=4V)

Output Voltage Accuracy

Output Voltage Adjustable Step

Output Adjustment Range

Output Ripple

Average Load Current (I

LOAD

)

Settling Time

EN or V

IN

to V

OUT

(start-up time)

Conversion efficiency

@BAT=3.8V

I

LOAD

= 50mA

I

LOAD

≥ 10mA (PWM)

I

LOAD

≥ 10mA (PFM)

I

LOAD

≥ 250 μ A (PFM)

Switching Frequency

Min

-40

3.0

1.7

-0.1

120

Typ

3.8

1.80

± 5

50

10

1.2

Max

85

4.5

2.05

+0.25

15

% mV/Step

V mV

RMS mA

2

88

70

80

65 70

800

Unit

℃

V

V ms

%

KHz

PWM/PFM Switching Point by F/W mA

Start-up Current Limit

Start-up Inrush

Current

I

LOAD

= 10mA

PWM

Quiescent Current

Output Current (Peak)

PFM

0

200

50

30

210

400

1000

40 mA mA

μ A mA

Load Regulation (I

LOAD

= 10 ~ 100mA) 1 mV/mA

Line Regulation (3.2V < V

IN

< 4.2V)

Logic Low Voltage (V

IL

)

EN threshold

EN current

Shutdown Current

Logic High Voltage (V

IH

) 1.62

0.03

(30)

0.4

10

<1

%/V

(mV/V)

V

V nA

μ A

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BM63SPKA1MGA

Table 4: Low Drop Regulation

Operation Temperature

Input Voltage (V

IN

)

V

OUT

= 2.9V

Output Voltage (V

OUT

)

(2.4~3.4V)

(1) V

OUT_CODEC

V

OUT

= 1.8V

(2) V

OUT_IO

(1.3~2.3V)

Accuracy (V

IN

=3.7V, I

LOAD

=100mA, 27 ’C)

Output Voltage Adjustable Step

Output Adjustment Range

Start-up Inrush Current I

LOAD

=10mA

Settling Time (start-up time) EN or V

IN

to V

OUT

Min Typ Max

-40 85

3.0 4.5

67

2.9

1.8

± 5

100

± 0.5

200

250

400

500

Unit

℃

V

V

% mV/Step

V mA

μ s

100 mA Output Current (Average) V

OUT

Output Current (Peak)

EN current

Shutdown Current (*1)

V

OUT

Drop-Out Voltage

(I

LOAD

= maximum output current)

Quiescent Current

(excluding load, I

LOAD

< 1mA)

Quiescent Current

(excluding load, I

LOAD

< 100 μ A)

Load Regulation (I load

= 0mA to 100mA), Δ V

OUT

Note: 0.4(mV/mA) * (100mA-0mA)=40mV

Line Regulation (V

OUT

+0.3V<V

IN

<4.5V

Logic Low Voltage (V

IL

)

EN threshold

Logic High Voltage (V

IH

) 1.62

45

7

150

300

N/A

40

(0.4)

10

0.4

10

<1 mA mV

μ A

μ A mV

(mV/mA) mV/V

V

V nA

μ A

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BM63SPKA1MGA

Table 5: Battery Charger

Charging Mode (BAT_IN rising to 4.2V)

Operation Temperature

Min

-40

Typ Max

85

Unit

℃

Input Voltage (V

IN

)

Note: It needs more time to get battery fully charged when 4.5 5.0 7.0 V

V

IN

=4.5V

3 4.5 mA Supply current to charger only

Battery trickle charge current

(BAT_IN < trickle charge voltage threshold)

Maximum Battery

Fast Charge Current

(ADAP_IN=5V)

Headroom = 0.3V

Note: ENX2=0

Headroom > 0.7V

(ADAP_IN=4.5V)

Maximum Battery

Fast Charge Current

(ADAP_IN=5V)

Headroom = 0.3V

Note: ENX2=1

Headroom > 0.7V

(ADAP_IN=4.5V)

170

160

330

180

0.1C

200

180

370

220

240

240

420

270 mA mA mA mA mA

Minimum Step 1 mA

Trickle Charge Voltage Threshold 3 V

Float Voltage

Battery Charge Termination Current,

% of Fast Charge Current

Standby Mode (BAT_IN falling from 4.2V)

Supply current to charger only

4.158 4.2

10

2

4.242

4

V

% mA

Battery Current

Battery Recharge Current

Note: C



Battery Capacity (*1)

-1

0.25C

μ A mA

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BM63SPKA1MGA

Table 6: Audio codec ADC

Temperature

Resolution

Conditions

Input sample rate, F sample

8KHz for MIC

44.1/48KHz for Line-in f in

=1KHz

B/W=20~20KHz

8KHz

Signal to Noise Ratio

(SNR @MIC or Line-in mode)

(A-weighted)

THD+N < 1%

44.1/

48KHz

2.26Vpp input

Digital Gain

Digital Gain Resolution

MIC Boost Gain

PGA Analog Gain

Analog Gain step

Input full-scale at maximum gain (differential)

Input full-scale at minimum gain (differential)

3dB bandwidth

Note:

Input V

PP

=0.8*AVDD

Input impedance Microphone mode input impedance

THD+N (microphone input)

@30mV

RMS

input

Input capacitance

THD+N (line input)

Min

-40

8

90

90

Typ

25

Max

85

16

48

92

92

Unit

℃

Bits

KHz dB

-54

-6

2~6

20

1

4

(AVDD=2.8V)

800

(AVDD=2.8V)

20

6

4.85 dB dB

26 dB dB

10

20 mV mV

RMS

RMS

KHz

K Ω pF

0.02

0.04

%

%

ADC channels

Analog supply voltage

Digital supply voltage

Crosstalk @line-in mode

2.6

1.08

42

2

2.8

1.2

45

3.0 V

1.32 V

48 dB

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BM63SPKA1MGA

MIC Boost Gain and PGA Gain are controlled by DSP F/W

AIL

MICP1

MICN1 -

+

MIC AMP

+

LINE AMP

-

1-bit

SD ADC

Digital

Codec

DSP

Core

MIC Boost Gain

0dB or 20dB

PGA Analog Gain

-6 ~ 26dB in 1dB step

ADC Digital Gain

-54 ~ 4.85dB

Fixed in 0dB now

DSP Digital Gain

-96 ~ 0dB in 6dB step

Fixed in 0dB now

System Gain = MIC Boost Gain + PGA Analog Gain + ADC Digital Gain + DSP Digital Gain

(1) MIC mode:

(a) There are 16 gain levels: 46/43/40/37/34/31/28/25/22/19/16/13/10/7/4/0 dB

(b) 46/43/40/37 dB gain levels are normally used for MIC mode

(2) Line-in mode:

(a) MIC boost gain = 0 dB

(b) PGA analog gain = 0 dB

(c) ADC digital gain = 0 dB

(d) DSP digital gain = 0 dB

(e) Gain control for line-in mode is recommended to be done by DAC side

Note: For I 2 S digital audio output, no gain control in BM63 so far and it is controlled by external DAC

AIL

MICP1

MICN1

Line-in mode

+

-

MIC AMP

MIC Boost Gain

0dB or 20dB

SCO up link

+

LINE AMP

-

PGA Analog Gain

-6 ~ 26dB in 1dB step

1-bit

SD ADC

Digital

Codec

BT

RF/MAC

UART

DSP

Core I 2 S

External

MCU

I 2 C

External

DSP/DAC

(YDA174)

A2DP down link

&

SCO down link

ADC Digital Gain

-54 ~ 4.85dB

Fixed in 0dB now

DSP Digital Gain

-96 ~ 0dB in 6dB step

Fixed in 0dB now

Digital/Analog

Gain Control

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BM63SPKA1MGA

Table 7: Transmitter section for BDR (25 ℃ )

Min Typ Max

2.0* 5.0

Bluetooth specification

-6 to 4 Maximum RF transmit power

RF power variation over temperature range with compensation disabled

RF power control range

RF power range control resolution

20dB bandwidth for modulated carrier

ACP

Note:

F = F

0

± 2MHz

F = F

0

± 3MHz

F

0

=2441MHz F = F

0

± >3MHz

∆f

1avg

maximum modulation

∆f

2max

maximum modulation

∆f

2avg

/∆f

1avg

ICFT

±

±

2.0

18

0.5

925

≥16

≤1000

-42

-49

-40

-48

≤-20

≤-40

≤-40 -57 -53

145

120 135

175 140<∆f

1avg

<175

140

≥115

0.9 0.95 ≥0.80

4.5 8 10.5 ± 75

Drift rate

Drift (single slot packet)

2 nd

harmonic content

3 rd

harmonic content

3.3

* The transmit power is calibrated in MP.

5

12

-42

-45

7.0

≤20

≤40

≤-30

≤-30

Unit dBm dB dB dB

KHz dBm dBm dBm

KHz

KHz

KHz

KHz/50 us

KHz dBm dBm

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BM63SPKA1MGA

Table 8 Transmitter section for EDR (25 ℃ )

Min Typ Max

Bluetooth specification

Unit

Relative transmit power

π /4 DQPSK max carrier frequency stability

|ω o

| freq. error

|ω

|ω i o

| initial freq. error

+ω i

|

8DPSK max carrier frequency stability block freq. error

|ω o

| freq. error

|ω i

| initial freq. error

|ω o

+ω i

| block freq. error

π /4 DQPSK modulation accuracy

RMS DEVM

99% DEVM

Peak DEVM

RMS DEVM 8DQPSK modulation accuracy

99% DEVM

Peak DEVM

In-band spurious emissions

Note:

F

0

=2441MHz

F > F

0

+3MHz

F < F

0

-3MHz

F = F

F = F

F = F

0

-3MHz

0

-2MHz

0

-1MHz

F = F

0

+1MHz

F = F

0

+2MHz

F = F

0

+3MHz

EDR differential phase encoding

-1.2

2.5

2.5

5

2.5

2.5

5

-4 to 1 dB

5

≤10 for all blocks KHz

5 ≤75 for all blocks KHz

10 ≤75 for all blocks KHz

5 ≤10 for all blocks KHz

5

≤75 for all blocks KHz

10

≤75 for all blocks KHz

7 12.2

PASS

7

25

PASS

20

<-52

<-53

-46

-34

-34

-37

-34

-46

100

≤-40

≤-40

≤-20

≤-26

≤-26

≤-20

≤-40

≥99

≤20

≤30

≤35

≤13

≤20

≤25

≤-40 dBm dBm dBm dBm dBm dBm

%

%

%

%

%

%

% dBm dBm

ISSC Confidential

(Version: 1.2) - 21 - 10/15/2014

Table 9 Receiver section for BDR (25 ℃ )

BM63SPKA1MGA

Bluetooth specification

Unit

Sensitivity at 0.1%

BER for all basic rate packet types

Frequency

(GHz)

2.402

2.441

Min

2.480

Maximum received signal at 0.1% BER

Continuous power 0.030

–2.000 required to block

Bluetooth reception

2.000-2.400

2.500-3.000

(for input power of

-67dBm with 0.1%

BER) measured at the unbalanced port of the balun

3.000-12.75

Typ

-89

-89

-89

0

-7

-10

-11

-7

Max

C/I co-channel

Adjacent channel selectivity C/I

Note: F

0

=2441MHz

F = F

0

+1MHz

F = F

0

-1MHz

F = F

F = F

0

0

+2MHz

-2MHz

F = F

0

-3MHz

F = F

0

+5MHz

F = F image

Maximum level of inter-modulation interferers

Spurious output level

6

-6

-6.5

-36

-28

-31

-48

-28

-37

N/A

≤-70

≥-20

-10

-27

-27

-10

≤11

≤0

≤0

≤-30

≤-9

≤-20

≤-40

≤-9

≥-39 dBm dBm dBm dB dB dB dB dB dB dB dB dBm dBm/Hz

ISSC Confidential

(Version: 1.2) - 22 - 10/15/2014

BM63SPKA1MGA

Table 10: Receiver section for EDR (25 ℃ )

Bluetooth specification

Unit

Sensitivity at

0.01% BER

Frequency

(GHz)

2.402

2.441

2.480

2.402

2.441

Modulation

π /4 DQPSK

π /4 DQPSK

π /4 DQPSK

8DPSK

8DPSK

Maximum received signal at

0.1% BER

Adjacent channel selectivity C/I

Note:

F

0

=2441MHz

2.480

π

π

/4 DQPSK

8DPSK

π /4 DQPSK

C/I co-channel at 0.1% BER

F= F

0

+1MHz

8DPSK

π /4 DQPSK

8DPSK

π /4 DQPSK

F= F

0

-1MHz

F= F

0

+2MHz

F= F

F= F

0

0

-2MHz

-3MHz

8DPSK

8DPSK

π /4 DQPSK

8DPSK

/4 DQPSK

8DPSK

π /4 DQPSK

8DPSK

π /4 DQPSK

F= F

0

+5MHz

8DPSK

π /4 DQPSK

F= F image

8DPSK

Min Typ

-90

-90

-90

-83

-83

-82

-10

-10

10

16

-11

-5

-8

-4

-38.5

-33.5

-29

-25

-32.5

-27

-49.5

-43.5

-29

-25

Max

≤-70

≤-70 dBm dBm dBm

≥-20

≥-20

≤13

≤21

≤0

≤5

≤0

≤5

≤-30

≤-25

≤-7

≤0

≤-20

≤-13

≤-40

≤-33

≤-7

≤0 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB

ISSC Confidential

(Version: 1.2) - 23 - 10/15/2014

Reflow profile

BM63SPKA1MGA

ISSC Confidential

(Version: 1.2) - 24 - 10/15/2014

QR code label information

Label Size:15

±

1.5 *6

±

1.5 mm

Device Name: BM63SPKA1MGA

MAC ID: xxxxxxxxxx

Customer ID Name: Cxxxxx

Date Code: 13xx

Module Weight

(Test condition: module with QR label)

TBD

BM63SPKA1MGA

ISSC Confidential

(Version: 1.2) - 25 - 10/15/2014

BM63SPKA1MGA

Storage standard

1. Calculated shelf life in sealed bag: 12 months at < 40 ℃ and <90% relative humidity (RH)

2. After bag is opened, devices that will be subjected to reflow solder or other high temperature process must be Mounted within 168 hours of factory conditions <30 ℃ /60% RH

ISSC Confidential

(Version: 1.2) - 26 - 10/15/2014

BM63SPKA1MGA

Ordering Information

Device

Size

BM63SPKA1MGA

Bluetooth 3.0 digital audio Module

Note:

32*15 mm

2

Minimum Order Quantity is 630pcs Tray.

Module

Shipment

Method

Tray

Order Number

ISSC Confidential

(Version: 1.2) - 27 - 10/15/2014

BM63SPKA1MGA

Packing Information

Tray Dimensions

Packing Method

ISSC Confidential

(Version: 1.2) - 28 - 10/15/2014

BM63SPKA1MGA

Inner box: Q ’ty (630 Pcs)

Dimensions: 36*16*9.5 cm

Bar Code Label

P/N: Device name

C/N: Customer name

Lot No: Lot ID

Q ’ty: Box or Carton Module’s Q’ty

Carton: Q’ty (3780 Pcs)

Dimensions: 38*35*30 cm

ISSC Confidential

(Version: 1.2) - 29 - 10/15/2014

 

1.

BM63   module   contain   PCB   antenna  

2.

The   gain   of   PCB   antenna   is   2.4dBi

 

 

 

 

 

1.

Every   module   has   48   pin  

2.

Fix   BT   module   on   main   board   by   its   8   pin  

3.

Every   pin   is   fixed   on   the   main   board   by   tin  

 

 

 

Main   board  

 

 

 

 

SRS ‐ X55  

 

＋

 

＋

1.Main

  board   plug   in   the   plastic   enclose   inside.

 

 

=

 

FCC statement

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) this device may not cause harmful interference, and (2)this device must accept any interference received, including interference that may cause undesired operation.

IC statement

This device complies with Industry

Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions:

(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device

Le pr é sent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence.

L'exploitation est autoris é e aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radio é lectrique subi, m ê me si le brouillage est susceptible d'en compromettre le fonctionnement.