X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

W M

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/ n

P a

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D m e e m n t t o

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B y s o t t a e r d e m

Rev. 2.0.0 January 2014

GENERAL DESCRIPTION

The XRP7720/7724/7725EVB-DEMO-1 board is a complete, four channel, power system. It provides 3.3V, 2.5V 1.5V and 1V at a maximum of 3A, 3A, 5A and 10A loads respectively. The 1.5V and 1V supplies can be adjusted in 2.5mV increments, the 2.5V supply in 5mV increments, and the 3.3V supply is adjustable in 10mV increments. The order and ramp rates for each supply can be programmed to accommodate any sequencing requirement. All power supply operations can be controlled over an I 2 C interface. Faults, output voltages and currents can also be monitored. Two GPIO and three PSIO signals are available and can be programmed to provide a variety of functions. Unused

GPIO/PSIO pins can be programmed as I/O expansion for a microcontroller. The board is supported by PowerArchitect TM 5.1 and plugs directly onto the Exar Communications Module

(XRP77xxEVB-XCM).

E V A L U A T I I O N B O A R D M A N U A L

XRP7724EVB-DEMO-1

FEATURES

• XRP7720/XRP7724/XRP7725

Programmable Controller

• 4 Channel Power System

• Wide Input Voltage Range: 5.5V-18V

• I 2 C Interface

− Programming

− Monitoring

− Control

Exar Corporation

48720 Kato Road, Fremont CA 94538, USA www.exar.com

Tel. +1 510 668-7000 – Fax. +1 510 668-7001

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

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D l l e i i g

P i i t t o a l l w

P e r

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B y s o t t a e r d e m

Rev. 2.0.0 January 2014

EVALUATION BOARD SCHEMATICS

P11 1

3

2

P10

1

2

1888687

T14

VIN

GND

T15

C45

35V

10UF

AVDD

CH1_OUT

GND

C39

16V

4.7UF

GND

C40

50V

0.01UF

GND

C29

50V

0.01UF

R1 DNS

0603

T16

V5EXT

GND

C28

50V

0.01UF

LDO5

GND

C37

16V

4.7UF

GND

R35 DNS

0603

C34

50V

0.01UF

VCCD

LDO3V3

C38

16V

2.2UF

C35

50V

0.01UF

GND GND

VCCD

GND

C17

50V

0.01UF

GND

C23

50V

0.01UF

GND

VIN

P8

4

5

6

GND

GND

VIN

SDA

SCL

10

11

12

A3

A4

A5

IO2

IO3

IO4

15

16

17

D2

D3

D4

IO2

IO3

IO4

R45

R43

R44

DNS

0603

DNS

0603

DNS

0603

GPIO1

GPIO2

ENABLE

VIN

U1

C33

50V

0.1UF

GND GND

CPLL

LDO5

LDO3V3

V5EXT

AVDD

GPIO1

GPIO2

SDA

SCL

PS1

PS2

PS3

3

42

44

1

43

4

16

CPLL

BFB

LDO5

LDO3.3

V5EXT

AVDD

DVDD

9

10

11

12

13

14

15

GPIO1

GPIO2

SDA

SCL

PS1

PS2

PS3

ENABLE R13 DNS

0603

ENABLE_IC 40

ENABLE

GND

BST1

VIN

GL1

R9 DNS

0603

C21

50V

0603

0.1UF

C13

35V

10UF

GH1

R10 DNS

0603

FDMC8200

1 2 3 4 Q1

R28

DNS

C46

DNS

LX1

L1

4.9uH

744314490

C5

6.3V

47uF

T1

3.3V- 5.0V 3A

CH1_OUT

C1

6.3V

47uF

C8

50V

1UF

R21

DNS

VOUT1

R20

DNS

P1

1

2

1888687

C32

35V

10UF

C26

50V

2200pF

BST1

GH1

LX1

GL1

PGND1

VOUT1

VCCD1-2

BST2

GH2

LX2

GL2

PGND2

VOUT2

BST3

GH3

LX3

GL3

PGND3

VOUT3

VCCD3-4

BST4

GH4

LX4

GL4

PGND4

VOUT4

C27

50V

0.01UF

BST2

18

19

20

21

22

8

24

25

26

27

28

7

29

30

31

32

33

6

35

36

37

38

39

5

GND

34 VCCD

BST1

GH1

GL1

CH1_OUT

R38 DNS

LX1

0603

C41

0603

0.1UF

50V

C24

0805

16V

4.7UF

BST2

GH2

GL2

CH2_OUT

BST3

GH3

GL3

C42

CH3_OUT

R36 DNS

0603

0603

0.1UF

50V

R39

LX2

GND

DNS

0603

GND

LX3

GND

23 VCCD

0603

C44

0.1UF

50V C18

GND

0805

16V

4.7UF

BST4

GH4

GL4

VOUT4_VPP

0603

C43

0.1UF

50V

R41

DNS

0603

GND

LX4

C20

35V

10UF

BST3

GL2

R11 DNS

0603

VIN

C19

50V

GH2

R12

0603

DNS

FDMC8200

Q2

1 2 3 4

C14

10UF

GH3

C22

GL3

R8

50V

0603

0603

0.1UF

R7

0603

FDMC7660

VIN

DNS

DNS

4

Q4

G

Q3

4

G

LX2

R29

DNS

C47

DNS

L2

3.3uH

744314330

D

S

D

S

VIN

FDMC8882

LX3

L3

744314200

2.0uH

R31

DNS

C48

DNS

C6

6.3V

47uF

C2

6.3V

47uF

T3

2.5V 3A

C7

6.3V

100uF

C9

50V

1UF

C3

6.3V

100uF

CH2_OUT

R23

DNS

VOUT2

R22

DNS

1.5V 5A

C10

50V

1UF

GND

T2

P2

1

2

1888687

CH3_OUT

R25

DNS

VOUT3

R24

DNS

D

SIR474DP

C31

35V

10UF

C30

35V

10UF

BST4 C25

GH4

R15 DNS

0603

50V

0603

0.1UF

4

G

GL4

R14 DNS

4

G

0603

FDMS7560S

S

Q6

LX4

D

S

Q5

R37

DNS

C49

DNS

L4

1.3uH

7443551130

C15

6.3V

100uF

C12

6.3V

100uF

C4

6.3V

100uF

C11

6.3V

100uF

T4

C16

50V

1UF

1.0V 10A

CH4_OUT

R27

DNS

VOUT4

R26

DNS

P3

1

2

1888687

P4

1

2

1888687

GND

GND

LDO5

LDO3V3

AVDD

GPIO1

GPIO2

SDA

SCL

PS1

PS2

PS3

ENABLE_IC

P9

9

10

11

12

13

14

15

7

8

5

6

3

4

1

2

Header 15

26

27

28

D13

GND

AREF

DNS

T8

T13

GND

T7

SCL

SDA

LDO5

ENABLE

LDO5

LDO3V3

PS2

J3

5

7

1

3

9 10

6

8

2

4

Header 5X2

J2

1

3

2

4

Header 2X2

J1

1

3

5

2

4

6

Header 3X2

GND

GPIO1

GPIO2

VIN

PS3

PS1

VPP

GND

GPIO1

GPIO2

PS1

PS2

PS3

R42

R40

R32

R33

R34

1206

DNS

1206

DNS

1206

DNS

1206

DNS

1206

DNS

EX1

EX2

EX3

EX4

EX5

R30

DNS

GND

T5

T9

EX5

SCL

SDA

ENABLE

P7

5

7

1

3

9 10

6

8

2

4

Header 5X2

P6

1

3

2

4

Header 2X2

P5

1

3

5

2

4

6

Header 3X2

EX4

EX3

VPP

EX1

EX2

T12

GND

GND

PS1

PS2

PS3

R4

DNS

R3

DNS

R2

DNS

R6

DNS

GND

R5

DNS

GND

LDO5

T10

LDO5

R18

DNS

R19

DNS

GND

C36

DNS

R17

4.7K

R16

4.7K

SDA

SCL

GND

Figure 1: XRP7720 /7724/7725 Evaluation Board Schematics

T6 T11

GND GND

CH4_OUT

VOUT4_VPP

VPP

JP1

1 2 3

Exar Corporation

48720 Kato Road, Fremont CA 94538, USA www.exar.com

Tel. +1 510 668-7000 – Fax. +1 510 668-7001

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u a d C h a n n e l l D i i g

XRP7720-DEV PIN ASSIGNMENT

P r o g r a m m a b l l e g

P i i t t o a l l w

P e r

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P a

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D m e e m n t t o

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B y s o t t a e r d e m

NC

AGND

NC

AVDD

VOUT1

VOUT2

VOUT3

VOUT4

GPIO0

GPIO1

SDA 11

8

9

10

5

6

7

3

4

1

2

XRP7720-DEV

TQFN

7mm X 7mm

Exposed Pad: AGND

33 GL_RTN2

32 GL2

31 LX2

30 GH2

29 BST2

28

27

GL_RTN3

GL3

26 LX3

25 GH3

24 BST3

23 VCCD3-4

Figure 2: XRP7720-DEV Pin Assignment

XRP7720-DEV PIN DESCRIPTION

Name

VCC

DVDD

VCCD1-2

VCCD3-4

AGND

Pin Number

41

16

23,34

2

Description

Input voltage. Place a decoupling capacitor close to the pin. This input is used in UVLO fault generation.

1.8V supply for digital circuitry. Connect pin to AVDD. Place a decoupling capacitor close to the pin.

Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be connected to the LDO5 pin to enable two power rails initially. It is recommended that the other VCCD pin be connected to the output of a 5V switching rail(for improved efficiency or for driving larger external FETs), if available, otherwise this pin may also be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for each VCCD pin with the pin(s) connected to LDO5 with shortest possible etch.

Analog ground pin. This is the small signal ground connection.

© 2014 Exar Corporation 3/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

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D m e e m n t t o

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B y s o t t a e r d e m

Name

GL_RTN1-4

GL1-GL4

GH1-GH4

Pin Number Description

LX1-LX4

BST1-BST4

GPI0-GPIO1

PSIO0-PSIO2

SDA, SCL

VOUT1-VOUT4

LDO5

ENABLE

DGND

NC

37,31, 26,20

35,29, 24,18

9,10

13,14,15

11,12

5,6,7,8

44

40

17

1,3,42

Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFETs and the inductor. These pins are also used to measure voltage drop across bottom MOSFETs in order to provide output current information to the control engine.

High side driver supply pin(s). Connect BST to the external capacitor as shown in the

Typical Application Circuit on page 5. The high side driver is connected between the

BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each cycle.

These pins can be configured as inputs or outputs to implement custom flags, power good signals, enable/disable controls and synchronization to an external clock.

Open drain, these pins can be used to control external power MOSFETs to switch loads on and off, shedding the load for fine grained power management. They can also be configures as standard logic outputs or inputs just as any of the GPIOs can be configured, but as open drains require an external pull-up when configured as outputs.

SMBus/I 2 C serial interface communication pins. These pins can be configured open drain or pseudo-TTL requiring a pull-up resistor.

Connect to the output of the corresponding power stage. The output is sampled at least once every switching cycle

Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of the IC is in the stand-by mode. This LDO is also used to power the internal Analog

Blocks.

If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset, registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be placed into shutdown. Active channels will automatically be ramped down, if desired, prior to the disabling of the chip.

Digital ground pin. This is the logic ground connection, and should be connected to the ground plane close to the PAD.

No Connect

© 2014 Exar Corporation 4/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o

XRP7724/XRP7725 PIN ASSIGNMENT

g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

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M a

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P a

F g

M e

D m e e m n t t o

S

B y s o t t a e r d e m

LDO3_3

AGND

CPLL

AVDD

VOUT1

VOUT2

VOUT3

VOUT4

GPIO0

GPIO1

SDA 11

8

9

10

3

4

5

1

2

6

7

XRP7724/XRP7725

TQFN

7mm X 7mm

Exposed Pad: AGND

33 GL_RTN2

32 GL2

31 LX2

30

29

GH2

BST2

28 GL_RTN3

27 GL3

26 LX3

25 GH3

24 BST3

23 VCCD3-4

Figure 3: XRP7724/XRP7725 Pin Assignment

XRP7724/XRP7725 PIN DESCRIPTION

Name

VCC

DVDD

VCCD1-2

VCCD3-4

AGND

GL_RTN1-4

Pin Number

41

16

23,34

2

Description

Input voltage. Place a decoupling capacitor close to the pin. This input is used in UVLO fault generation.

1.8V supply for digital circuitry. Connect pin to AVDD. Place a decoupling capacitor close to the pin.

Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be connected to the LDO5 pin to enable two power rails initially. It is recommended that the other VCCD pin be connected to the output of a 5V switching rail(for improved efficiency or for driving larger external FETs), if available, otherwise this pin may also be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for each VCCD pin with the pin(s) connected to LDO5 with shortest possible etch.

Analog ground pin. This is the small signal ground connection.

© 2014 Exar Corporation 5/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

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D m e e m n t t o

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B y s o t t a e r d e m

Name

GL1-GL4

GH1-GH4

Pin Number Description

LX1-LX4

BST1-BST4

GPI0-GPIO1

PSIO0-PSIO2

SDA, SCL

VOUT1-VOUT4

LDO5

LDO3_3

ENABLE

BFB

DGND

CPLL

37,31, 26,20

35,29, 24,18

9,10

13,14,15

11,12

5,6,7,8

44

1

40

42

17

3

Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFETs and the inductor. These pins are also used to measure voltage drop across bottom MOSFETs in order to provide output current information to the control engine.

High side driver supply pin(s). Connect BST to the external capacitor as shown in the

Typical Application Circuit on page 5. The high side driver is connected between the

BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each cycle.

These pins can be configured as inputs or outputs to implement custom flags, power good signals, enable/disable controls and synchronization to an external clock.

Open drain, these pins can be used to control external power MOSFETs to switch loads on and off, shedding the load for fine grained power management. They can also be configures as standard logic outputs or inputs just as any of the GPIOs can be configured, but as open drains require an external pull-up when configured as outputs.

SMBus/I 2 C serial interface communication pins. These pins can be configured open drain or pseudo-TTL requiring a pull-up resistor.

Connect to the output of the corresponding power stage. The output is sampled at least once every switching cycle

Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of the IC is in the stand-by mode. This LDO is also used to power the internal Analog

Blocks.

Output of the 3.3V standby LDO. This is a micro power LDO that can remain active while the rest of the IC is in shutdown.

If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset, registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be placed into shutdown. Active channels will automatically be ramped down, if desired, prior to the disabling of the chip.

Input from the 15V output created by the external boost supply. When this pin goes below a pre-defined threshold, a pulse is created on the low side drive to charge this output back to the original level. If not used, this pin should be connected to GND.

Digital ground pin. This is the logic ground connection, and should be connected to the ground plane close to the PAD.

PLL compensation capacitor

ORDERING INFORMATION

Refer to XRP7720/XRP7724/XRP7725 datasheets and/or www.exar.com

for exact and up to date ordering information.

© 2014 Exar Corporation 6/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

USING THE EVALUATION BOARD

Q u a d C h a n n e l l D i i g

P r o g r a m m a b l l e P o w

Load the PowerArchitect TM run it.

5.1 software and

I

NPUT

V

OLTAGE

R

ANGE g i i t t a l l w

P e r

W M

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B y s o t t a e r d e m

The input voltage range of these boards is from 5.5V to 18V. The power components have been optimized for a 12V input rail.

When running the board at an input voltage other than 12V, use PowerArchitect TM evaluate the system performance.

5.1 to

After selecting the proper family (Chips) and the device (XRP7720, XRP7724, or XRP7725), select the “Get Started with the EVB-DEMO-1” option when prompted as shown below.

I

2

C I

NTERFACE

The controller employs a standard I 2 interface. Pull-ups for the I 2 included on the demo board.

C

C signals are

O

PERATING THE

E

VALUATION

B

OARD

The demo board is designed to be powered from either an AC/DC wall wart (the output voltage must be in the range of the controller

VCC specification – 5.5V to 18V) connected to the barrel connector, or a test bench DC power supply (the voltage must be in the range of the controller VCC specification –

5.5V to 18V) connected to the Vin phoenix connector (the positive side is indicated with

VIN text in silkscreen. The proper connection is indicated in the evaluation board connections section below).

B

RING UP

P

ROCEDURE

Plug the demo board to the XCM as shown below.

When done, click “Create”. PowerArchitect TM

5.1 will load the default configuration automatically.

Apply Power to the board. Please refer to the sections above on how to properly supply power to the board and what voltage range to use.

Turn on the Power supply.

Insert the USB cable into the computer and the XCM board.

Go to the Tools tab in PowerArchitect TM 5.1 and select Boards. The software will identify communication ports where it found the XCM board. Select the port.

© 2014 Exar Corporation 7/16

PowerArchitect corner.

TM 5.1 is now communicating with XCM which is indicated in the lower left

Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

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Programming the Configuration onto

XRP7720-DEV/XRP7724/XRP7725

To program a configuration go to the Tools tab in PowerArchitect

Flash.

TM 5.1 and select Program

PowerArchitect TM 5.1 will go through the process of loading configuration in the flash.

Once it has successfully completed the task, it will report the outcome as seen above and reset the device if “Automatically Reset After

Flashing” box checked (default option).

Close the window.

Note that the boards will be pre-loaded with the default configuration.

Regulation

To enable channel regulation go to the Tools tab in PowerArchitect TM

Dashboard.

5.1 and select

The program Flash window will appear.

Click the Flash button.

© 2014 Exar Corporation

In Dashboard turn Group 1 and Group 2 on.

The configuration groups channel 1, channel 2, and LDO3.3

* into Group 1, and channels 3 and 4 into Group 2. The channels are now in regulation as indicated by Vout readings as well as the in-regulation indicators.

Note* : Not available in XRP7720EVB-DEMO-1

8/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

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B y s o t t a e r d e m

E

VALUATION

B

OARD

C

ONNECTIONS

The following picture illustrates how Vin supplied from a test bench DC power supply and instruments attached to the outputs would be connected to the demo board.

GND1 OUT1 GND2 OUT2 GND3 OUT3 GND4 OUT4

Channels can be turned on/off individually if desired.

Note : Make sure there is a jumper shorting

JP1 pins 1 and 2 installed on your board.

Channel 4 will not regulate without it.

JP1 JUMPER

© 2014 Exar Corporation 9/16

VIN GND

VIN BARREL

CONNECTOR

Rev. 2.0.0

2 3 4 5

A

P11

1

T14

P10

1

2

P0P1001

P0P1002

1888687

GND

T15

C45

35V

10UF

AVDD

C39

16V

4.7UF

C40

50V

0.01UF

C29

50V

0.01UF

GND GND GND

CH1_OUT

R1

P0R101

0603

DNS

P0R102

T16

V5EXT

GND

C28

50V

0.01UF

GND

C37

16V

4.7UF

R35 DNS

P0R3501

0603

P0R3502

C34

50V

0.01UF

GND

B

C

VCCD

C38

16V

2.2UF

C35

50V

0.01UF

GND GND

GND

C17

50V

0.01UF

C23

50V

0.01UF

GND

GND

10

11

12

IO2

IO3

IO4

15

16

17

4

5

6

P8

R45

P0R4501

0603

DNS

P0R4502

R43

P0R4301

0603

DNS

P0R4302

R44

P0R4401

0603

DNS

P0R4402

ENABLE

Evaluation Board Schematic

CPLL

C33

50V

0.1UF

GND GND

LDO5

R13

P0R1301

0603

DNS

P0R1302

U1

3

P0U103

CPLL

42

P0U1042

BFB

44

1

P0U101

LDO3.3

43

P0U1043

V5EXT

4

16

P0U1016

DVDD

9

10

P0U1010

GPIO2

11

12

13

14

P0U1013

PS1

15

40

GND

C21

50V

0603

P0C2102

0.1UF

C13

35V

10UF

R10

P0R1001

0603

DNS

P0R1002

P0Q102

FDMC8200

Q1

P0Q10MB2

P0Q10MB1

R9

P0R901

0603

DNS

P0R902

R28

DNS

C46

DNS

T1

3.3V- 5.0V 3A

L1

P0L101

4.9uH

744314490

P0L102

C5

6.3V

47uF

C1

6.3V

47uF

C8

50V

1UF

R21

DNS

VOUT1

R20

DNS

P1

1888687

C32

35V

10UF

C26

50V

2200pF

C27

50V

0.01UF

C19

50V

0603

P0C1902

0.1UF

BST1

35

GH1

36

LX1

GL1

P0U1039

39

PGND1

P0U105

5

VOUT1

GND

P0U1034

VCCD1-2

BST2

GH2

LX2

34

29

30

GL2

P0U1033

33

PGND2

P0U106

VOUT2

BST3

GH3

LX3

6

24

25

GL3

P0U1028

28

PGND3

P0U107

VOUT3

7

BST1

GH1

GL1

R38 DNS

P0R3801

0603

P0R3802

LX1

C41

0603

0.1UF

50V

C24

0805

16V

4.7UF

BST2

GH2

GL2

R36 DNS

P0R3601

0603

P0R3602

LX2

GND

GND

CH2_OUT

C42

0603

0.1UF

50V

GND

BST3

GH3

GL3

R39

P0R3901

0603

DNS

P0R3902

LX3

CH3_OUT

P0U1023

VCCD3-4

23

0603 C44

P0C4401 P0C4402

0.1UF

50V C18

GND

0805

16V

4.7UF

BST4

18

GH4

19

LX4

GL4

P0U1022

PGND4

22

P0U108

VOUT4

8

BST4

GH4

GL4

R41

P0R4101

DNS

0603

P0R4102

GND

LX4

VOUT4_VPP

0603

C43

0.1UF

50V

C20

35V

10UF

GND

C31

35V

10UF

C30

35V

10UF

C14

35V

10UF

R12 DNS

P0R1201

0603

P0R1202

FDMC8200

Q2

R11 DNS

P0R1101

0603

P0R1102

P0Q202

P0Q20MB2

P0Q20MB1

R29

DNS

L2

P0L201

3.3uH

744314330

P0L202

C47

DNS

C6

6.3V

47uF

2.5V 3A

C2

6.3V

47uF

C9

50V

1UF

C22

R8

P0R801

DNS

P0R802

4

0603

Q4

D

50V

0603

P0C2202

0.1UF

R7 DNS

P0R701

0603

FDMC7660

4

Q3

P0R702

G

S

FDMC8882

D

S

L3

744314200

P0L301

2.0uH

P0L302

T3

R31

DNS

C7

6.3V

100uF

C48

DNS

R23

DNS

VOUT2

R22

DNS

1.5V 5A

C3

6.3V

100uF

C10

50V

1UF

T2

P2

1888687

R25

DNS

VOUT3

R24

DNS

R15

P0R1501

DNS

4

P0R1502

G

0603

50V

C25

0603

P0C2501 P0C2502

0.1UF

D

SIR474DP

S

Q6

R14 DNS

P0R1401

0603

4

P0R1402

G

FDMS7560S

D

S

Q5

R37

DNS

L4

P0L401

1.3uH

7443551130

P0L402

C15

6.3V

100uF

C49

DNS

C12

6.3V

100uF

C4

6.3V

100uF

T4

1.0V 10A

CH4_OUT

C11

6.3V

100uF

C16

50V

1UF

R27

DNS

VOUT4

R26

DNS

P3

1888687

P4

1888687

D

LDO3V3

P9

P0P901

1

P0P902

2

P0P903

3

P0P904

4

P0P905

5

P0P906

6

P0P907

7

P0P908

8

P0P909

9

GND

GND

ENABLE_IC

Header 15

26

27

28

DNS

T8

T13

P0T800

GND

PS2

T7

P0T700

SCL

SDA

J3

P0J301

P0J303

1

3

P0J305

5

P0J307

7

P0J309

9 10

6

8

2

4

P0J302

GPIO1

P0J304

P0J306

GPIO2

P0J308

VIN

P0J3010

Header 5X2

J2

P0J201

1

P0J203

3

2

4

P0J202

P0J204

Header 2X2

J1

P0J101

P0J103

P0J105

1

3

5

2

4

6

Header 3X2

P0J102

P0J104

PS3

PS1

VPP

P0J106

GND

GND

1 2

R42 1206

P0R4202

DNS

P0R4201

R40

1206

P0R4002

DNS

P0R4001

R32 1206

P0R3202

DNS

P0R3201

R33 1206

P0R3302

DNS

P0R3301

R34 1206

P0R3402

DNS

P0R3401

EX1

EX2

EX3

EX4

EX5

R30

DNS

GND

P7

P0P701

1

P0P703

3

P0P705

P0P707

5

7

6

8

P0P709

9 10

2

4

Header 5X2

P0P702

P0P704

P0P706

P0P708

P6

P0P601

P0P603

1

3

2

4

Header 2X2

P0P602

P0P604

T5

T9

GND

P0T900

P5

P0P501

1

P0P503

3

P0P505

5

2

4

6

Header 3X2

P0P502

P0P504

P0P506

T12

GND

3

R4

DNS

R3

DNS

R2

DNS

R6

DNS

GND

R5

DNS

GND

T10

GND

R18

DNS

R19

DNS

R17

4.7K

R16

4.7K

GND

C36

DNS

10/16

4

T6 T11

GND GND

JP1

5

Title

XRP7724EVB-DEMO-1

Size:

Date:

File:

C Name:

XRP7724.SchDoc

Rev: 1.0

1/17/2013 Time: 3:02:06 PM Sheet 1 of 1

C:\XRP7724EVB-DEMO-1\Board\XRP7724.SchDoc

EXAR

48720 Kato Road

Fremont, CA 94538 www.exar.com

6

6

A

B

C

D

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

W M

M a

/ n

P a

F g

M e

D m e e m n t t o

S

B y s o t t a e r d e m

BILL OF MATERIAL

Ref.

U1

Q1,Q2

Q3

Q4

Q5

Q6

L1

L2

L3

L4

C1,C2,C5,C6

C3,C4,C7,C11,C12,C15

C8,C9,C10,C16

C13,C14,C20,C30,C31,C32,C45

C17,C23,C27-C29,C34,C35

C18,C24,C37,C39

** ,C40 8 MURATA CORP. GRM188R71H103KA01D

C19,C21,C22,C25,C33,C41-C44

C26

Qty Manufacturer

1

2

1

1

Exar Corp.

FAIRCHILD

FAIRCHILD

FAIRCHILD

Part Number

XRP7720-DEV

/XRP7724/XRP7725

FDMC8200

FDMC7660

FDMC8882

Size

TQFN44

Power 33

Power 33

MLP 3.3X3.3

Component

2nd Generation 4Ch.

Sw. Controller

Dual N-Channel Power

Trench MOSFET

N-Channel Power

Trench MOSFET

N-Channel Power

Trench MOSFET

1 FAIRCHILD FDMS7560S Power 56

N-Channel Power

Trench SyncFET

1 Vishay Siliconix

1

1

1

1

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

SIR474DP

744314490

744314330

744314200

7443551130

4 MURATA CORP. GRM32ER70J476KE20L

PowerPAK SO-

8

7.0x6.9mm

7.0x6.9mm

7.0x6.9mm

N-Ch. 30-V (D-S)

MOSFET

Inductor 4.9uH,

14.5mΩ, 6.5A

Inductor 3.3uH,

9.0mΩ, 9.0A

Inductor 2.0uH,

5.85mΩ, 11.5A

13.2X12.8mm

1210

Inductor 1.3uH,

1.8mΩ, 25A

CAP CER 47uF, 6.3V,

X7R, 10%

6 MURATA CORP. GRM32ER60J107M20L

4 MURATA CORP. GRM21BR71H105KA12L

1210

0805

CAP CER 100uF, 6.3V,

X5R, 20%

CAP CER 1.0uF, 50V,

X7R, 10%

7 MURATA CORP. GRM32ER7YA106KA12L

4 MURATA CORP. GRM21BR71C475KA73

9 MURATA CORP. GRM188R71H104KA93D

1 MURATA CORP. GRM188R71H222KA01D

1210

0603

0805

0603

0603

CAP CER 10uF,

35V,X7R, 10%

CAP CER

0.01uF,50V,X7R,10%

CAP CER 4.7uF,

16V,X7R,10%

CAP CER 0.1uF,

50V,X7R,10%

CAP CER

2200pF,50V,X7R,10%

© 2014 Exar Corporation 11/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

W M

M a

/ n

P a

F g

M e

D m e e m n t t o

S

B y s o t t a e r d e m

Ref.

C38 **

R16,R17

J1

J3

Qty Manufacturer

1 MURATA CORP. GRM21BR71C225KA12L

2

1

1

PANASONIC

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

Part Number

ERJ-3EKF4701V

61300624321

613 010 243 121

61300311121

Size

0805

0603

2.54mm

Angled Dual

Socket

2.54mm

Angled Dual

Socket

2.54mm Pin

Header

Component

CAP CER 2.2uF,

16V,X7R,10%

RES 4.7K OHM,

1/10W, 1%, SMD

2.54mm dual Pin

Socket Header WR-

PHD

2.54mm dual Pin

Socket Header WR-

PHD

2.54mm Pin Header

WR-PHD, 3 Pins

JP1

JP1(jumper)

1

1

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

P1, P2,P3,P4,P10

P5

P7

P9

P11

T6,T8,T10,T11

5

1

1

1

1

4

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

WURTH

ELEKTRONIK

Switchceaft

Corp.

WURTH

ELEKTRONIK

Note** : Not loaded on XRP7720EVB-DEMO-1

609 002 115 121

691 216 510 002

61300621021

61301021021

61301511121

RAPC722X

61304011121

2.54mm Pin

Jumper

2.54mm Pin Jumper w/Test Point

2.54mm Dual

Pin Header

2.54mm Dual

Pin Header

2.54mm Dual Pin

Header Wr-PHD

2.54mm Dual Pin

Header Wr-PHD

2.54mm Pin

Header

2.54mm Pin Header

WR-PHD, 15 Pins

2.1mmID,

5.5mmOD

Conn. Powerjack Mini

R/A, T/H

2.54mm Pin

Header

2.54mm Pin Header

WR-PHD, 40 Pins

© 2014 Exar Corporation 12/16 Rev. 2.0.0

EVALUATION BOARD LAYOUT

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

W M

M a

/ n

P a

F g

M e

D m e e m n t t o

S

B y s o t t a e r d e m

Figure 4: Component Placement – Top Side

© 2014 Exar Corporation

Figure 5: Layout – Top Side

13/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

W M

M a

/ n

P a

F g

M e

D m e e m n t t o

S

B y s o t t a e r d e m

Figure 6: Layout - Bottom

© 2014 Exar Corporation

Figure 7: Layout – Middle Layer 1

14/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g

P i i t t o a l l w

P e r

W M

M a

/ n

P a

F g

M e

D m e e m n t t o

S

B y s o t t a e r d e m

Figure 8: Layout – Internal Plane

© 2014 Exar Corporation 15/16 Rev. 2.0.0

X R P 7 7 2 0 / 7 7 2 4 / 7 7 2 5 E V B D E M O 1

DOCUMENT REVISION HISTORY

Q u

P a r d o g

C r h a a n m n m e a l l b

D l l e i i g g

P i i t t o a l l w

P e r

W M

M a

/ n

P a

F g

M e

D m e e m n t t o

S

B y s o t t a e r d e m

Revision

1.0.0

1.1.0

1.1.1

2.0.0

Date Description

09/28/12 Initial release of document

06/18/2013 BOM- Change of Manufacturer P1,P2,P3,P4,P10.

10/14/2013 Deleted C36 from the bill of materials

01/31/2014 Added XRP7720-DEV and XRP7725 information

BOARD REVISION HISTORY

Board Revision

XRP7724EVB-

DEMO-1-01

Date

10/01/12 Initial release of evaluation board

Description

FOR FURTHER ASSISTANCE

Email:

Exar Technical Documentation: [email protected] http://www.exar.com/TechDoc/default.aspx?

E

XAR

C

ORPORATION

H

EADQUARTERS AND

S

ALES

O

FFICES

48720 Kato Road

Fremont, CA 94538 – USA

Tel.: +1 (510) 668-7000

Fax: +1 (510) 668-7030 www.exar.com

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

© 2014 Exar Corporation 16/16 Rev. 2.0.0