= 0 V, TA = TL to TH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 31.

16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 32.

ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 33.

Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 34.

Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 35.

Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 36.

Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 37.

RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 38.

JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 39.

Nexus debug port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 40.

External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 41.

DSPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 42.

LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 43.

LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 44.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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List of figures

List of figures

Figure 1.

SPC56xP54x/SPC56xP60x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2.

LQFP176 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 3.

LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4.

LQFP100 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 5.

Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 6.

Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 7.

Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 8.

Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 9.

Voltage regulator configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 10.

Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 11.

Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 12.

Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 13.

I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 14.

I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 15.

ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 16.

Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 17.

Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 18.

Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 19.

Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 20.

Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 21.

Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 22.

JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 23.

JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 24.

JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 25.

Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 26.

Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 27.

Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 28.

External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 29.

DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 30.

DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 31.

DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 32.

DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 33.

DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 34.

DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 35.

DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 36.

DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 37.

DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 38.

LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 39.

LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 40.

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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Introduction

1 Introduction

SPC56xP54x, SPC56xP60x

This document provides electrical specifications, pin assignments, and package diagrams for the SPC56xP54x/SPC56xP60x series of microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical characteristics. For functional characteristics, refer to the device reference manual.

1.2 Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis applications specifically the airbag application.

This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology.

The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category. It operates up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.

Table 2 provides a summary of different members of the SPC56xP54x/SPC56xP60x family

and their features—relative to Full-featured version—to enable a comparison among the family members and an understanding of the range of functionality offered within this family.

Feature

Table 2. SPC56xP54x/SPC56xP60x device comparison

SPC560P54 SPC560P60 SPC56AP54

768 KB 1 MB 768 KB Code Flash memory (with ECC)

Data Flash / EE (with ECC)

SRAM (with ECC)

Processor core

Instruction set

CPU performance

FMPLL (frequency-modulated phaselocked loop) modules

INTC (interrupt controller) channels

PIT (periodic interrupt timer)

64 KB 80 KB

32-bit e200z0h

64 KB

VLE

0-64 MHz

SPC56AP60

1 MB

64 KB 80 KB

32-bit Dual e200z0h

148

1 (includes four 32-bit timers)

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Table 2. SPC56xP54x/SPC56xP60x device comparison (continued)

Feature SPC560P54 SPC560P60 SPC56AP54 SPC56AP60

Enhanced DMA (direct memory access) channels

FlexRay

FlexCAN (controller area network)

Safety port

FCCU (fault collection and control unit)

CTU (cross triggering unit) eTimer channels

FlexPWM (pulse-width modulation) channels

Yes (64 message buffer)

(1),(2)

Yes (via third FlexCAN module)

Yes

(3)

Yes

2 × 6

Analog-to-digital converters (ADC)

LINFlex modules

DSPI (deserial serial peripheral interface) modules

CRC (cyclic redundancy check) units

JTAG interface

Nexus port controller (NPC)

Digital power supply

(9)

Supply

Analog power supply

Internal RC oscillator

External crystal oscillator

One (10-bit, 27-channel)

(6)

(4)

2 (1 × Master/Slave, 1 × Master only)

(5)

(7)

Yes

Yes (Level 2+)

(8)

3.3 V or 5 V single supply with external transistor

3.3 V or 5 V

16 MHz

4–40 MHz

Packages

LQFP100

LQFP144

LQFP100

LQFP144

LQFP176 (10)

Temperature

Standard ambient temperature

–40 to 125 °C

1. Each FlexCAN module has 32 message buffers.

2. One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.

3. Enhanced FCCU version.

4. Same amount of ADC channels as on SPC560P44/50 not considering the internally connected ones. 26 channels on

LQFP144 and 16 channels on LQFP100.

5. LinFlex_1 is Master Only.

6. Increased number of CS for DSPI_1.

7. Upgraded specification with addition of 8-bits polynomial (CRC-8 VDA CAN) support and 3rd context.

8. Improved debugging capability with data trace capability and increased Nexus throughput available on emulation package.

9. 3.3 V range and 5 V range correspond to different orderable parts.

10. Software development package only. Not available for production.

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SPC56xP54x/SPC56xP60x is present on the market in two different options enabling different features: Full-featured, and Airbag configuration.

Table 3

shows the main differences between the two versions.

Table 3. SPC56xP54x/SPC56xP60x device configuration difference

Feature

Enhanced

Full-featured

FlexCAN (controller area network)

CTU (cross triggering unit)

FlexRay

DSPI (deserial serial peripheral interface) modules

CRC (cyclic redundancy check) unit

3 2

Yes

Yes (64 message buffer)

Airbag

Figure 1

shows a top-level block diagram of the SPC56xP54x/SPC56xP60x MCU. Table 4

summarizes the functions of the blocks.

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Figure 1. SPC56xP54x/SPC56xP60x block diagram

Introduction

PMU

INTC_0

SWT_0

STM_0

ECSM_0

SEMA4_0 e200z0 Core

32-bit general purpose registers

Variable length encoded instructions

Exception handler

Special purpose registers

Instruction unit

Integer execution unit

Load/Store unit

Branch prediction unit

JTAG

Nexus 2+

Nexus port controller e200z0 Core

32-bit general purpose registers

Variable length encoded instructions

Exception handler

Special purpose registers

Instruction unit

Integer execution unit

Load/Store unit

Branch prediction unit

JTAG

Nexus 2+

INTC_1

SWT_1

STM_1

ECSM_1

SEMA4_1

DMAMUX_0

DMA_0

INSTR DATA INSTR DATA

PBRIDGE_0

M3 M0 M1 M5

Cross Bar Switch (XBAR, AMBA 2.0 v6 AHB) XBAR_0

Memory protection unit MPU_0

S2 S0 S1

Memory protection unit MPU_1

NASPS_0 NASPS_1

PFLASHC_0

PBRIDGE_1

SRAMC_0

SRAMC_1

48KB

SRAM with ECC

1024KB code flash with ECC

4x16KB data flash with ECC

32KB

SRAM with ECC

Peripheral Bus (IPS) Peripheral Bus (IPS)

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Block

Table 4. SPC56xP54x/SPC56xP60x series block summary

Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

Block of read-only memory containing VLE code which is executed according to the boot mode of the device

Clock generation module

(MC_CGM)

Controller area network

(FlexCAN)

Provides logic and control required for the generation of system and peripheral clocks

Supports the standard CAN communications protocol

Cross triggering unit (CTU)

Crossbar switch (XBAR)

Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT

Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width.

Cyclic redundancy checker

(CRC) unit

Deserial serial peripheral interface (DSPI)

Enhanced direct memory access

(eDMA)

Enhanced timer (eTimer)

Error correction status module

(ECSM)

External oscillator (XOSC)

Is dedicated to the computation of CRC off-loading the CPU. Each context has a separate CRC computation engine in order to allow the concurrent computation of the CRC of multiple data streams.

Provides a synchronous serial interface for communication with external devices

Performs complex data transfers with minimal intervention from a host processor via “ n ” programmable channels

Provides enhanced programmable up/down modulo counting

Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes

Provides an output clock used as input reference for FMPLL_0 or as reference clock for specific modules depending on system needs

Fault collection and control unit

(FCCU)

Flash memory

Frequency-modulated phaselocked loop (FMPLL)

Interrupt controller (INTC)

JTAG controller

Provides functional safety to the device

Provides non-volatile storage for program code, constants and variables

FlexRay (FlexRay communication controller)

Provides high-speed distributed control for advanced automotive applications

Generates high-speed system clocks and supports programmable frequency modulation

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode

LINFlex controller

Mode entry module (MC_ME)

Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load

Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications

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Table 4. SPC56xP54x/SPC56xP60x series block summary (continued)

Block Function

Peripheral bridge (PBRIDGE)

Periodic interrupt timer (PIT)

Power control unit (MC_PCU)

Reset generation module

(MC_RGM)

Semaphore unit (SEMA4)

Is the interface between the system bus and on-chip peripherals

Produces periodic interrupts and triggers

Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU

Centralizes reset sources and manages the device reset sequence of the device

Provides the hardware support needed in multi-core systems for implementing semaphores and provide a simple mechanism to achieve lock/unlock operations via a single write access

Static random-access memory

(SRAM)

System status and configuration module (SSCM)

System timer module (STM)

Provides storage for program code, constants, and variables

System integration unit lite (SIUL)

Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration

Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable

Provides a set of output compare events to support AUTOSAR

(1) system tasks

and operating

System watchdog timer (SWT)

Wakeup unit (WKPU)

Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events.

1. AUTOSAR: AUTomotive Open System ARchitecture (see autosar.org web site).

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1.5.1

1.5.2 High performance e200z0h core processor

The e200z0h Power Architecture core provides the following features:

 High performance e200z0 core processor for managing peripherals and interrupts

 Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

 Harvard architecture

 Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions

– Results in smaller code size footprint

– Minimizes impact on performance

 Branch processing acceleration using lookahead instruction buffer

 Load/store unit

– 1-cycle load latency

– Misaligned access support

– No load-to-use pipeline bubbles

 Thirty-two 32-bit general purpose registers (GPRs)

 Separate instruction bus and load/store bus Harvard architecture

 Hardware vectored interrupt support

 Reservation instructions for implementing read-modify-write constructs

 Long cycle time instructions, except for guarded loads, do not increase interrupt latency

 Extensive system development support through Nexus debug port

 Non maskable Interrupt support

Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between six master ports and six slave ports. The crossbar supports a 32-bit address bus width and a

32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grant it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and will be granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access.

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The crossbar provides the following features:

 6 master ports:

– 2 e200z0 core complex Instruction ports

– 2 e200z0 core complex Load/Store Data ports

– eDMA

– FlexRay

 6 slave ports:

– 2 Flash memory (code flash and data flash)

– 2 SRAM (48 KB + 32 KB)

– 2 PBRIDGE

 32-bit internal address, 32-bit internal data paths

 Fixed Priority Arbitration based on Port Master

 Temporary dynamic priority elevation of masters

Introduction

1.5.4

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a

DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size.

The eDMA module provides the following features:

 16 channels support independent 8, 16 or 32-bit single value or block transfers

 Supports variable sized queues and circular queues

 Source and destination address registers are independently configured to postincrement or remain constant

 Each transfer is initiated by a peripheral, CPU, or eDMA channel request

 Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer

 DMA transfers possible between system memories, DSPIs, ADC, eTimer and CTU

 Programmable DMA Channel Multiplexer for assignment of any DMA source to any available DMA channel with up to 30 potential request sources

 eDMA abort operation through software

On-chip flash memory with ECC

The SPC56xP54x/SPC56xP60x provides up to 1024 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash memory module interfaces the system bus to a dedicated flash memory array controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains a four-entry, 4x128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses are registered and are forwarded to the system bus on the following cycle, incurring 2 wait states.

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1.5.5

SPC56xP54x, SPC56xP60x

The flash memory module provides the following features:

 Up to 1024 KB flash memory

– 14 blocks (2×16 KB + 2×32 KB + 2×16 KB + 2×64 KB + 6×128 KB) code flash

– 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash

– Full Read While Write (RWW) capability between code and data flash

 Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to prefetch code or data or both)

 Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page buffer miss at 64 MHz

 Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

 Hardware and software configurable read and write access protections on a per-master basis.

 Configurable access timing allowing use in a wide range of system frequencies.

 Multiple-mapping support and mapping-based block access timing (0–31 additional cycles) allowing use for emulation of other memory types.

 Software programmable block program/erase restriction control.

 Erase of selected block(s)

 Read page size of 128 bits (4 words)

 64-bit ECC with single-bit correction, double-bit detection for data integrity

 Embedded hardware program and erase algorithm

 Erase suspend, program suspend and erase-suspended program

 Censorship protection scheme to prevent flash memory content visibility

 Hardware support for EEPROM emulation

On-chip SRAM with ECC

The SPC56xP54x/SPC56xP60x SRAM module provides a general-purpose memory of up to 80 KB.

The SRAM module provides the following features:

 Supports read/write accesses mapped to the SRAM memory from any master

 Up to 80 KB general purpose RAM

– 2 blocks (48 KB + 32 KB)

 Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory

 Typical SRAM access time: 0 wait state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back with a read to same memory block

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The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems.

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To

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1.5.7

Introduction allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other.

The INTC provides the following features:

 Unique 9-bit vector for each separate interrupt source

 8 software triggerable interrupt sources

 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

 Ability to modify the ISR or task priority.

– Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources.

 2 external high priority interrupts directly accessing the main core and IOP critical interrupt mechanism

The INTC module is replicated for each processor.

System clocks and clock generation

The following list summarizes the system clock and clock generation on the

SPC56xP54x/SPC56xP60x:

 Lock detect circuitry continuously monitors lock status

 Loss of clock (LOC) detection for PLL outputs

 Programmable output clock divider (  1,  2,  4,  8)

 Programmable output clock divider (  1,  2,  3 to  256)

 eTimer module running at the same frequency as the e200z0h core

 On-chip oscillator with automatic level control

 Internal 16 MHz RC oscillator for rapid start-up and safe mode

– Supports frequency trimming by user application

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio are all software configurable.

The FMPLL has the following major features:

 Input clock frequency from 4 MHz to 40 MHz

 Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

 Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

 Modulation enabled/disabled through software

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 Triangle wave modulation

 Programmable modulation depth (±0.25% to ±4% deviation from center frequency)

– Programmable modulation frequency dependent on reference frequency

 Self-clocked mode (SCM) operation

The main oscillator provides these features:

 Input frequency range 4 MHz to 40 MHz

 Crystal input mode or Oscillator input mode

 PLL reference

This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap reference voltage.

The RC Oscillator provides these features:

 Nominal frequency 16 MHz

 ±6% variation over voltage and temperature after process trim

 Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the PLL

 RC oscillator is used as the default system clock during startup

The PIT module implements these features:

 Up to four general purpose interrupt timers

 32-bit counter resolution

 Clocked by system clock frequency

 Each channel can be used as trigger for a DMA request

1.5.12 System timer module (STM)

The STM module implements these features:

 32-bit up counter with 8-bit prescaler

 Four 32-bit compare channels

 Independent interrupt source for each channel

 Counter can be stopped in debug mode

The STM module is replicated for each processor.

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The SWT has the following features:

 Fault tolerant output

 Safe internal RC oscillator as reference clock

 Windowed watchdog

 Program flow control monitor with 16-bit pseudorandom key generation

The SWT module is replicated for each processor.

The FCCU provides an independent fault reporting mechanism even if the CPU is exhibiting unstable behaviors. The FCCU module has the following features:

 Redundant collection of hardware checker results

 Redundant collection of error information and latch of faults from critical modules on the device

 Collection of self-test results

 Configurable and graded fault control

– Internal reactions (no internal reaction, IRQ)

– External reaction (failure is reported to the external/surrounding system via configurable output pins)

The SPC56xP54x/SPC56xP60x SIUL controls MCU pad configuration, external interrupts, general purpose I/O (GPIO) pin configuration, and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The SIUL provides the following features:

 Centralized general purpose input output (GPIO) control of input/output pins and analog input-only pads (package dependent)

 All GPIO pins can be independently configured to support pull-up, pull down, or no pull

 Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

 All peripheral pins (except ADC channels) can be alternatively configured as both general purpose input or output pins

 ADC channels support alternative configuration as general purpose inputs

 Direct readback of the pin value is supported on all pins through the SIU

 Configurable digital input filter that can be applied to some general purpose input pins for noise elimination

– Up to 4 internal functions can be multiplexed onto one pin

Different booting modes are available in the SPC56xP54x/SPC56xP60x:

 From internal flash memory

 Via a serial link

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The default booting scheme is the one which uses the internal flash memory (an internal pull-down is used to select this mode). The alternate option allows the user to boot via

FlexCAN or LINFlex (using the boot assist module software).

A censorship scheme is provided to protect the contents of the flash memory and offer increased security for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile memory.

1.5.16.1 Boot assist module (BAM)

The BAM is a block of read-only one-time programmed memory and is identical for all

SPC56xP54x/SPC56xP60x devices that are based on the e200z0h core. The BAM program is executed every time the device is powered on if the alternate boot mode has been selected by the user.

The BAM provides the following features:

 Serial bootloading via FlexCAN or LINFlex.

 BAM can accept a password via the used serial communication channel to grant the legitimate user access to the non-volatile memory.

The ECSM on this device features the following:

 Platform configuration and revision

 ECC error reporting for flash memory and SRAM

 ECC error injection for SRAM

The ECSM module is replicated for each processor.

1.5.18 FlexCAN

The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: realtime processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN module contains 32 message buffers.

The FlexCAN module provides the following features:

 Full implementation of the CAN protocol specification, Version 2.0B

– Standard data and remote frames

– Extended data and remote frames

– 0 to 8 bytes data length

– Programmable bit rate as fast as 1 Mbit/s

 32 message buffers of 0 to 8 bytes data length

 Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

 Programmable loop-back mode supporting self-test operation

 3 programmable mask registers

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 Programmable transmit-first scheme: lowest ID or lowest buffer number

 Time stamp based on 16-bit free-running timer

 Global network time, synchronized by a specific message

 Maskable interrupts

 Independent of the transmission medium (an external transceiver is assumed)

 High immunity to EMI

 Short latency time due to an arbitration scheme for high-priority messages

 Transmit features

– Supports configuration of multiple mailboxes to form message queues of scalable depth

– Arbitration scheme according to message ID or message buffer number

– Internal arbitration to guarantee no inner or outer priority inversion

– Transmit abort procedure and notification

 Receive features

– Individual programmable filters for each mailbox

– 8 mailboxes configurable as a six-entry receive FIFO

– 8 programmable acceptance filters for receive FIFO

 Programmable clock source

– System clock

– Direct oscillator clock to avoid PLL jitter

1.5.19 Safety port (FlexCAN)

The SPC56xP54x/SPC56xP60x MCU has a second CAN controller synthesized to run at high bit rates to be used as a safety port. The CAN module of the safety port provides the following features:

 Identical to the FlexCAN module

 Bit rate as fast as 7.5 Mb at 60 MHz CPU clock using direct connection between CAN modules (no physical transceiver required)

 32 Message buffers of 0 to 8 bytes data length

 Can be used as a third independent CAN module

1.5.20 FlexRay

The FlexRay module provides the following features:

 Full implementation of FlexRay Protocol Specification 2.1

 64 configurable message buffers can be handled

 Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate

 Message buffers configurable as Tx, Rx or RxFIFO

 Message buffer size configurable

 Message filtering for all message buffers based on FrameID, cycle count and message

 Programmable acceptance filters for RxFIFO message buffers

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The LINFlex on the SPC56xP54x/SPC56xP60x features the following:

 Supports LIN Master mode (on both modules), LIN Slave mode (on one module) and

UART mode

 LIN state machine compliant to LIN1.3, 2.0, and 2.1 Specifications

 Handles LIN frame transmission and reception without CPU intervention

 LIN features

– Autonomous LIN frame handling

– Message buffer to store Identifier and up to 8 data bytes

– Supports message length as long as 64 bytes

– Detection and flagging of LIN errors: Sync field; Delimiter; ID parity; Bit; Framing;

Checksum and Time-out errors

– Classic or extended checksum calculation

– Configurable Break duration as long as 36-bit times

– Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)

– Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

– Interrupt-driven operation with 16 interrupt sources

 LIN slave mode features

– Autonomous LIN header handling

– Autonomous LIN response handling

 UART mode

– Full-duplex operation

– Standard non return-to-zero (NRZ) mark/space format

– Data buffers with 4-byte receive, 4-byte transmit

– Configurable word length (8-bit or 9-bit words)

– Error detection and flagging

– Parity, Noise and Framing errors

– Interrupt-driven operation with four interrupt sources

– Separate transmitter and receiver CPU interrupt sources

– 16-bit programmable baud-rate modulus counter and 16-bit fractional

– 2 receiver wake-up methods

The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for communication between the SPC56xP54x/SPC56xP60x MCU and external devices.

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The DSPI modules provide these features:

 Full duplex, synchronous transfers

 Master or slave operation

 Programmable master bit rates

 Programmable clock polarity and phase

 End-of-transmission interrupt flag

 Programmable transfer baud rate

 Programmable data frames from 4 to 16 bits

 Up to 28 chip select lines available

– 8 each on DSPI_0 and DSPI_1

– 4 each on DSPI_2, DSPI_3, and DSPI_4

 8 clock and transfer attributes registers

 Chip select strobe available as alternate function on one of the chip select pins for deglitching

 FIFOs for buffering up to 5 transfers on the transmit and receive side

 Queueing operation possible through use of the eDMA

 General purpose I/O functionality on pins when not used for SPI

1.5.23 eTimer

Two eTimer modules are provided, each with six 16-bit general purpose up/down timer/counter per module. The following features are implemented:

 Individual channel capability

– Input capture trigger

– Output compare

– Double buffer (to capture rising edge and falling edge)

– Separate prescaler for each counter

– Selectable clock source

– 0 % to 100% pulse measurement

– Rotation direction flag (Quad decoder mode)

 Maximum count rate

– Equals peripheral clock/2 — for external event counting

– Equals peripheral clock — for internal clock counting

 Cascadeable counters

 Programmable count modulo

 Quadrature decode capabilities

 Counters can share available input pins

 Count once or repeatedly

 Preloadable counters

 Pins available as GPIO when timer functionality not in use

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The ADC module provides the following features:

Analog part:

 1 on-chip analog-to-digital converter

 10-bit AD resolution

 1 sample and hold unit per ADC

 Conversion time, including sampling time, less than 1  s (at full precision)

 Typical sampling time is 150 ns min. (at full precision)

 Differential non-linearity error (DNL) ±1 LSB

 Integral non-linearity error (INL) ±1.5 LSB

 Total unadjusted error (TUE) <3 LSB

 Single-ended input signal range from 0 to 3.3 V / 5.0 V

 ADC and its reference can be supplied with a voltage independent from V

DDIO

 ADC supply can be equal or higher than V

DDIO

 ADC supply and the ADC reference are not independent from each other (they are internally bonded to the same pad)

 Sample times of 2 (default), 8, 64, or 128 ADC clock cycles

Digital part:

 27 input channels (26 + 1 internally connected)

 4 analog watchdogs to compare ADC results against predefined levels (low, high, range) before results are stored

 2 operating modes: Normal mode and CTU control mode

 Normal mode features

– Register-based interface with the CPU: control register, status register, 1 result register per channel

– ADC state machine managing 3 request flows: regular command, hardware injected command, and software injected command

– Selectable priority between software and hardware injected commands

– DMA compatible interface

 CTU control mode features

– Triggered mode only

– 4 independent result queues (2 × 16 entries, 2 × 4 entries)

– Result alignment circuitry (left justified; right justified)

– 32-bit read mode allows to have channel ID on one of the 16-bit part

– DMA compatible interfaces

The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests on user selected conditions with minimized CPU load for dynamic configuration.

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It implements the following features:

 Double buffered trigger generation unit with up to eight independent triggers generated from external triggers

 Trigger generation unit configurable in sequential mode or in triggered mode

 Each Trigger can be appropriately delayed to compensate the delay of external low pass filter

 Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

 Double buffered ADC command list pointers to minimize ADC-trigger unit update

 Double buffered ADC conversion command list with up to 24 ADC commands

 Each trigger has the capability to generate consecutive commands

 ADC conversion command allows to control ADC channel from each ADC, single or synchronous sampling, independent result queue selection

 3 contexts for the concurrent CRC computation

 Separate CRC engine for each context

 Zero-wait states during the CRC computation (pipeline scheme)

 3 hard-wired polynomials (CRC-8 VDA CAN, CRC-32 Ethernet and CRC-16-CCITT)

 Support for byte/half-word/word width of the input data stream

 Support for expected and actual CRC comparison

1.5.27 Nexus development interface (NDI)

The NDI block provides real-time development support capabilities for the

SPC56xP54x/SPC56xP60x Power Architecture based MCU in compliance with the IEEE-

ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several individual Nexus blocks that are selected to provide the development support interface for this device. The NDI block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard. The development support provided includes access to the MCU’s internal memory map and access to the processor’s internal registers during run time.

The Nexus Interface provides the following features:

 Configured via the IEEE 1149.1

 All Nexus port pins operate at V

DDIO

(no dedicated power supply)

 Nexus 2+ features supported

– Static debug

– Watchpoint messaging

– Ownership trace messaging

– Program trace messaging

– Real time read/write of any internally memory mapped resources through JTAG pins

– Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of information

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– Watchpoint triggering, watchpoint triggers program tracing

– DDR

 Auxiliary Output Port

– 4 MDO (Message Data Out) pins

– MCKO (Message Clock Out) pin

– 2 MSEO (Message Start/End Out) pins

– EVTO (Event Out) pin

 Auxiliary Input Port

– EVTI (Event In) pin (a)

1.5.28 IEEE 1149.1 (JTAG) controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

 IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO)

 Selectable modes of operation include JTAGC/debug or normal system operation.

 A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

– BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD

 A 5-bit instruction register that supports the additional following public instructions:

– ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_CORE0,

ACCESS_AUX_TAP_CORE1, ACCESS_AUX_TAP_NASPS_0,

ACCESS_AUX_TAP_NASPS_1

 Three test data registers: a bypass register, a boundary scan register, and a device identification register.

 A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry.

1.5.29 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

 Uses external NPN transistor

 Regulates external 3.3 V to 5.0 V down to 1.2 V for the core logic

 Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

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a. At least one TCK clock is necessary for the EVTI signal to be recognized by the MCU.

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Package pinouts and signal descriptions

Package pinouts and signal descriptions

The LQFP pinouts are shown in the following figures.

Figure 2. LQFP176 pinout (top view)

(b)

NC NC NC PB

SS_LV_COR0

PF[7]

PF[8]

DD_HV_IO1

PF[9]

PF[10]

PF[11]

PD[9]

DD_HV_OSC

SS_HV_OSC

XTAL

EXTAL

RESET

PD[8]

PD[5]

PD[6]

SS_LV_COR3

DD_LV_COR3

NMI

PA[6]

PD[1]

PF[4]

DD_HV_IO5

MDO4

MDO5

MDO6

PF[5]

DD_HV_IO0

PF[6]

MDO0

PA[7]

PC[4]

PA[8]

PC[5]

PA[5]

PC[7]

PC[3]

176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133

LQFP176

108

107

106

105

104

103

102

101

116

115

114

113

112

111

110

109

124

123

122

121

120

119

118

117

132

131

130

129

128

127

126

125

100

TDO

TCK

TMS

TDI

PG[5]

PA[2]

PG[7]

PC[12]

PG[8]

PC[11]

PG[9]

PD[11]

PG[10]

PD[10]

PG[11]

PA[1]

PA[0]

PA[4]

PF[12]

PD[14]

PG[3]

PC[14]

PG[2]

PC[13]

PG[4]

PD[12]

PG[6]

DD_HV_FL

PD[13]

SS_LV_COR1

DD_LV_COR1

PA[3]

DD_HV_IO2

SS_HV_IO2

MDO9

MDO8

MDO7

SS_HV_IO6

DD_HV_IO6

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

[15] NC NC NC NC NC NC NC NC b. Software development package only. Not available for production.

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Figure 3. LQFP144 pinout (top view) (c)

PC[3]

SS_LV_COR0

DD_LV_COR0

PF[7]

PF[8]

DD_HV_IO1

SS_HV_IO1

PF[9]

PF[10]

PF[11]

PD[9]

DD_HV_OSC

SS_HV_OSC

XTAL

EXTAL

RESET

PD[8]

PD[5]

PD[6]

SS_LV_COR3

DD_LV_COR3

NMI

PA[6]

PD[1]

PF[4]

PF[5]

DD_HV_IO0

SS_HV_IO0

PF[6]

MDO

PA[7]

PC[4]

PA[8]

PC[5]

PA[5]

PC[7]

LQFP144

PA[2]

PG[7]

PC[12]

PG[8]

PC[11]

PG[9]

PD[11]

PG[10]

PD[10]

PG[11]

PA[1]

PA[0]

PA[4]

PP_TEST

PF[12]

PD[14]

PG[3]

PC[14]

PG[2]

PC[13]

PG[4]

PD[12]

PG[6]

DD_HV_FL

SS_HV_FL

PD[13]

SS_LV_COR1

DD_LV_COR1

PA[3]

DD_HV_IO2

SS_HV_IO2

TDO

TCK

TMS

TDI

PG[5]

108

107

106

105

104

103

102

101

100

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c. Availability of port pin alternate functions depends on product selection.

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Figure 4. LQFP100 pinout (top view) (d)

NMI

PA[6]

PD[1]

PA[7]

PC[4]

PA[8]

PC[5]

PA[5]

PC[7]

PC[3]

SS_LV_COR0

DD_LV_COR0

DD_HV_IO1

SS_HV_IO1

PD[9]

DD_HV_OSC

SS_HV_OSC

XTAL

EXTAL

RESET

PD[8]

PD[5]

PD[6]

SS_LV_COR3

DD_LV_COR3

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

LQFP100 63

PA[4]

PP TEST

PD[14]

PC[14]

PC[13]

PD[12]

DD_HV_FL

SS_HV_FL

PD[13]

SS_LV_COR1

DD_LV_COR1

PA[3]

DD_HV_IO2

SS_HV_IO2

TDO

TCK

TMS

TDI

PA[2]

PC[12]

PC[11]

PD[11]

PD[10]

PA[1]

PA[0]

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

The following sections provide signal descriptions and related information about the functionality and configuration of the SPC56xP54x/SPC56xP60x devices.

2.2.1 Power supply and reference voltage pins

Table 5 lists the power supply and reference voltage for the SPC56xP54x/SPC56xP60x

devices.

Table 5. Supply pins

Supply

Symbol Description

Pin

LQFP

100

LQFP

144

LQFP

176

(1)

BCTRL

VREG control and power supply pins

Voltage regulator external NPN Ballast base control pin 47 69 81 d. Availability of port pin alternate functions depends on product selection.

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Symbol

Table 5. Supply pins (continued)

Supply

Description

DD_HV_REG

(3.3 V or

5.0 V)

Voltage regulator supply voltage

DD_LV_REGCOR

SS_LV_REGCOR

1.2 V decoupling

(2)

pins for core logic supply and voltage regulator feedback. Decoupling capacitor must be connected between this pins and V

SS_LV_REGCOR.

1.2 V decoupling

(2)

pins for core logic GND and voltage regulator

feedback. Decoupling capacitor must be connected between this pins and V

DD_LV_REGCOR.

ADC0 reference and supply voltage

DD_HV_AD

SS_HV_AD

ADC supply and high reference voltage

ADC ground and low reference voltage

Power supply pins (3.3 V or 5.0 V)

Input/Output supply voltage V

DD_HV_IO0

SS_HV_IO0

DD_HV_IO1

SS_HV_IO1

DD_HV_IO2

SS_HV_IO2

DD_HV_IO3

SS_HV_IO3

DD_HV_IO4

SS_HV_IO4

DD_HV_IO5

SS_HV_IO5

DD_HV_IO6

SS_HV_IO6

DD_HV_FL

SS_HV_FL

DD_HV_OSC

SS_HV_OSC

Input/Output ground

Input/Output supply voltage

Input/Output ground

Input/Output supply voltage

Input/Output ground

Input/Output supply voltage

Input/Output ground

Input/Output supply voltage

Input/Output ground

Input/Output supply voltage

Input/Output ground

Input/Output supply voltage

Input/Output ground

Code and data flash supply voltage

Code and data flash supply ground

Crystal oscillator amplifier supply voltage

Crystal oscillator amplifier ground

Power supply pins (1.2 V)

DD_LV_COR0

1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest

SS_LV_COR0

pin.

LQFP

100

—

126

127

169

170

108

109

121

120

115

114

150

151

—

Pin

LQFP

144

LQFP

176

(1)

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Table 5. Supply pins (continued)

Supply

Symbol Description

SS_LV_COR0

DD_LV_COR1

SS_LV_COR1

DD_LV_COR2

SS_LV_COR2

DD_LV_COR3

SS_LV_COR3

1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest

DD_LV_COR0

1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest

SS_LV_COR1

pin.

1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest

DD_LV_COR1 pin.

1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest

SS_LV_COR2

pin.

1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest

DD_LV_COR 2

pin.

1.2 V Decoupling pins for core logic supply. Decoupling capacitor must be connected between these pins and the nearest

SS_LV_COR3

pin.

1.2 V Decoupling pins for core logic GND. Decoupling capacitor must be connected between these pins and the nearest

DD_LV_COR 3

pin.

1. LQFP176 available only as development package.

2. See datasheet Voltage Regulator Electrical Characteristics section for more details.

Pin

LQFP

100

LQFP

144

LQFP

176

(1)

131

132

117

118

155

156

Table 6 and

Table 7

contain information on pin functions for the SPC56xP54x/SPC56xP60x devices. The pins listed in

Table 6

are single-function pins. The pins shown in Table 7 are

multi-function pins, programmable via their respective Pad Configuration Register (PCR) values.

Symbol

MDO0

MDO4

Description

Table 6. System pins

Pad Speed (1) Pin

Direction

SRC=0 SRC=1

LQFP

100

LQFP

144

LQFP

176

(2)

Dedicated pins

Nexus Message Data Output—line 0

Output

Only

Nexus Message Data Output—line 4

Output

Only

Fast

—

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Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Symbol

Table 6. System pins (continued)

Pad Speed (1)

Description Direction

SRC=0 SRC=1

Pin

LQFP

100

LQFP

144

LQFP

176

(2)

MDO5

MDO6

MDO7

MDO8

MDO9

MDO10

MDO11

Nexus Message Data Output—line 5

Nexus Message Data Output—line 6

Nexus Message Data Output—line 7

Nexus Message Data Output—line 8

Nexus Message Data Output—line 9

Nexus Message Data Output—line 10

Nexus Message Data Output—line 11

Output

Only

Output

Only

Output

Only

Output

Only

Output

Only

Output

Only

Output

Only

Fast

RDY

NMI

XTAL

EXTAL

TMS

(3)

TDO

RESET

(4)

Nexus ready output

Non-Maskable Interrupt

Analog output of the oscillator amplifier circuit. Needs to be grounded if oscillator is used in bypass mode.

Output

Only

Input Only

—

Analog input of the oscillator amplifier circuit, when the oscillator is not in bypass mode. 

Analog input for the clock generator when the oscillator is in bypass mode.

JTAG state machine control

JTAG clock

JTAG data input

—

Input Only

—

JTAG data output

Output

Only

—

Reset pin

Bidirectional reset with Schmitt trigger characteristics and noise filter

Bidirection al

Medium

PP TEST

Test pin

Pin for testing purpose only. To be tied to ground in normal operating mode.

REG_BYPASS

Pin for testing purpose only. To be tied to ground in normal operating mode.

—

1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

—

107

110

111

112

166

171

172

105

106

104

107

131

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SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

2. LQFP176 available only as development package.

3. In this pin there is an internal pull; refer to JTAGC chapter in the device reference manual for pull direction.

4. Its configuration can be set up by the PCR[108] register inside the SIU module. See SIUL chapter in the device reference manual.

Port pin

Table 7 defines the pin list and muxing for the SPC56xP54x/SPC56xP60x devices relative

to Full-featured version.

Each row of Table 7 shows all the possible ways of configuring each pin, via “alternate

functions”. The default function assigned to each pin after reset is the ALT0 function.

Pins marked as external interrupt capable can also be used to resume from STOP and

HALT mode.

SPC56xP54x/SPC56xP60x devices provide four main I/O pad types depending on the associated functions:

 Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission.

 Medium pads provide fast enough transition for serial communication channels with controlled current to reduce electromagnetic emission.

 Fast pads provide maximum speed. They are used for improved NEXUS debugging capability.

 Symmetric pads are designed to meet FlexRay requirements.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.

PCR

No.

Alternate function

(3)

(2),

Functions

Table 7. Pin muxing (1)

Peripheral

(4)

Pad speed (6)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

A[0] PCR[0]

A[1] PCR[1]

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[0]

ETC[0]

SCK_2

F[0]

EIRQ[0]

GPIO[1]

ETC[1]

SOUT_2

F[1]

EIRQ[1]

SIUL eTimer_0

DSPI_2

FCCU

SIUL

Port A

I/O

SIUL eTimer_0

DSPI_2

FCCU

SIUL

I/O

Slow

Medium

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Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Port pin

A[2]

(8)

A[3]

(8)

A[4]

(8)

PCR

No.

PCR[2]

PCR[3]

PCR[4]

A[5] PCR[5]

A[6] PCR[6]

A[7] PCR[7]

A[8] PCR[8]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[5]

CS0_1

ETC[5]

CS7_0

EIRQ[5]

GPIO[6]

SCK_1

CS2_4

—

EIRQ[6]

GPIO[7]

SOUT_1

CS1_4

—

EIRQ[7]

GPIO[2]

ETC[2]

CS3_4

—

SIN_2

ABS[0]

EIRQ[2]

GPIO[3]

ETC[3]

CS0_2

—

ABS[1]

EIRQ[3]

GPIO[4]

ETC[0]

CS1_2

ETC[4]

FAB

EIRQ[4]

GPIO[8]

—

CS0_4

—

SIN_1

EIRQ[8]

SIUL

DSPI_1 eTimer_1

DSPI_0

SIUL

DSPI_1

DSPI_4

—

SIUL

DSPI_1

DSPI_4

—

SIUL

SIUL eTimer_0

DSPI_4

—

DSPI_2

MC_RGM

SIUL

SIUL eTimer_0

DSPI_2

—

MC_RGM

SIUL

SIUL eTimer_1

DSPI_2 eTimer_0

MC_RGM

SIUL

—

DSPI_4

—

DSPI_1

SIUL

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

Slow

Medium

108

102

116

132

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DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

Port pin

PCR

No.

A[9] PCR[9]

A[10] PCR[10]

A[11] PCR[11]

A[12] PCR[12]

A[13] PCR[13]

A[14] PCR[14]

A[15] PCR[15]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[11]

SCK_2

—

EIRQ[10]

GPIO[12]

SOUT_2

—

EIRQ[11]

GPIO[13]

CS4_1

—

SIN_2

EIRQ[12]

GPIO[9]

CS1_2

—

SIN_4

GPIO[10]

CS0_2

—

EIRQ[9]

GPIO[14]

TXD

ETC[4]

CS5_1

EIRQ[13]

GPIO[15]

CS6_1

ETC[5]

—

RXD

EIRQ[14]

SIUL

DSPI_2

—

SIUL

DSPI_2

—

SIUL

DSPI_1

—

DSPI_2

SIUL

DSPI_2

—

DSPI_4

SIUL

DSPI_2

—

SIUL

Safety Port eTimer_1

DSPI_1

SIUL

DSPI_1 eTimer_1

—

Safety Port

SIUL

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

Slow

Medium

100

134

118

120

122

136

143

144

158

142

144

146

160

175

176

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Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Port pin

PCR

No.

B[0] PCR[16]

B[1] PCR[17]

B[2] PCR[18]

B[3] PCR[19]

B[6] PCR[22]

B[7] PCR[23]

B[8] PCR[24]

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

GPIO[16]

TXD

ETC[2]

DEBUG[0]

EIRQ[15]

GPIO[23]

—

AN[0]

RXD

GPIO[24]

—

AN[1]

ETC[5]

Port B

SIUL

FlexCAN_0 eTimer_1

SSCM

SIUL

I/O

—

GPIO[17]

CS7_1

ETC[3]

DEBUG[1]

RXD

EIRQ[16]

GPIO[18]

TXD

SOUT_4

DEBUG[2]

EIRQ[17]

GPIO[19]

—

SCK_4

DEBUG[3]

RXD

GPIO[22] clk_out

CS2_2 clk_out_div2

EIRQ[18]

SIUL

DSPI_1 eTimer_1

SSCM

FlexCAN_0

SIUL

LINFlex_0

DSPI_4

SSCM

SIUL

—

DSPI_4

SSCM

LINFlex_0

SIUL

MC_CGL

DSPI_2

MC_CGL

SIUL

—

ADC_0

LINFlex_0

SIUL

—

ADC_0 eTimer_0

Input Only

I/O

—

I/O

—

I/O

—

I/O

—

Slow

—

Medium

—

109

110

114

116

138

133

134

138

140

162

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SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

Port pin

PCR

No.

B[9] PCR[25]

B[10] PCR[26]

B[11] PCR[27]

B[12] PCR[28]

B[13] PCR[29]

B[14] PCR[30]

B[15] PCR[31]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[27]

—

AN[13]

GPIO[28]

—

AN[14]

GPIO[29]

—

AN[16]

RXD

GPIO[25]

—

AN[11]

GPIO[26]

—

AN[12]

GPIO[30]

—

AN[17]

ETC[4]

EIRQ[19]

GPIO[31]

—

AN[18]

EIRQ[20]

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

LINFlex_1

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0 eTimer_0

SIUL

—

ADC_0

SIUL

Input Only

—

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Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Port pin

PCR

No.

C[0] PCR[32]

C[1] PCR[33]

C[2] PCR[34]

C[3] PCR[35]

C[4] PCR[36]

C[5] PCR[37]

C[6] PCR[38]

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

GPIO[35]

CS1_0

ETC[4]

TXD

EIRQ[21]

GPIO[36]

CS0_0

—

DEBUG[4]

EIRQ[22]

GPIO[37]

SCK_0

SCK_4

DEBUG[5]

EIRQ[23]

GPIO[38]

SOUT_0

—

DEBUG[6]

EIRQ[24]

GPIO[32]

—

AN[19]

GPIO[33]

—

AN[2]

GPIO[34]

—

AN[3]

Port C

SIUL

DSPI_0

DSPI_4

SSCM

SIUL

DSPI_0

—

SSCM

SIUL

DSPI_0 eTimer_1

LINFlex_1

SIUL

DSPI_0

—

SSCM

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

Input Only

I/O

—

I/O

—

I/O

—

I/O

—

Slow

—

Medium

142

174

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SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

Port pin

PCR

No.

C[7] PCR[39]

C[8] PCR[40]

C[9] PCR[41]

C[10] PCR[42]

C[11] PCR[43]

C[12] PCR[44]

C[13] PCR[45]

C[14] PCR[46]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

I/O

—

I/O

—

I/O

—

I/O

—

I/O

SIUL

—

SSCM

DSPI_0

DSPI_4

SIUL

DSPI_1

DSPI_4

DSPI_0

SIUL

DSPI_2

DSPI_4

—

SIUL

DSPI_2

DSPI_4

—

SIUL eTimer_0

DSPI_2

DSPI_3

SIUL eTimer_0

DSPI_2

DSPI_3

SIUL eTimer_1

—

CTU_0

FlexCAN_1

SIUL eTimer_1

CTU_0

FlexCAN_1

GPIO[39]

—

DEBUG[7]

SIN_0

SIN_4

GPIO[40]

CS1_1

CS1_4

CS6_0

GPIO[41]

CS3_2

CS0_4

—

GPIO[42]

CS2_2

CS2_4

—

GPIO[43]

ETC[4]

CS2_2

CS0_3

GPIO[44]

ETC[5]

CS3_2

CS1_3

GPIO[45]

ETC[1]

—

EXT_IN

RXD

GPIO[46]

ETC[2]

EXT_TGR

TXD

Slow

Medium

130

123

111

101

103

154

147

135

100

125

127

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104

Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Port pin

PCR

No.

C[15] PCR[47]

D[0] PCR[48]

D[1] PCR[49]

D[2] PCR[50]

D[3] PCR[51]

D[4] PCR[52]

D[5] PCR[53]

D[6] PCR[54]

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

—

GPIO[47]

CA_TR_EN

ETC[0]

—

EXT_IN

GPIO[51]

CB_TX

ETC[4]

—

GPIO[52]

CB_TR_EN

ETC[5]

—

GPIO[53]

CS3_0

—

SOUT_3

GPIO[54]

CS2_0

SCK_3

SOUT_4

GPIO[48]

CA_TX

ETC[1]

—

GPIO[49]

CS4_1

ETC[2]

EXT_TRG

CA_RX

GPIO[50]

CS5_1

ETC[3]

—

CB_RX

SIUL

FlexRay_0 eTimer_1

—

SIUL

FlexRay_0 eTimer_1

—

SIUL

DSPI_0

—

DSPI_3

SIUL

DSPI_0

DSPI_3

DSPI_4

SIUL

FlexRay_0 eTimer_1

—

CTU_0

Port D

I/O

—

SIUL

FlexRay_0 eTimer_1

—

SIUL

DSPI_1 eTimer_1

CTU_0

FlexRay_0

SIUL

DSPI_1 eTimer_1

—

FlexRay_0

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

Slow Symmetric 85

Slow Symmetric 86

Slow

Medium

Slow Symmetric 89

Slow Symmetric 90

124

125

140

128

129

148

149

168

152

153

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SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

Port pin

PCR

No.

D[7] PCR[55]

D[8] PCR[56]

D[9] PCR[57]

D[10] PCR[58]

D[11] PCR[59]

D[12] PCR[60]

D[13] PCR[61]

D[14] PCR[62]

D[15] PCR[63]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[58]

—

CS0_3

—

GPIO[59]

—

CS1_3

SCK_3

GPIO[60]

—

CS7_1

RXD

GPIO[55]

CS3_1

—

CS4_0

SIN_3

GPIO[56]

CS2_1

RDY

CS5_0

GPIO[57]

—

TXD

CS6_1

GPIO[61]

—

CS2_3

SOUT_3

GPIO[62]

—

CS3_3

—

SIN_3

GPIO[63]

—

AN[20]

SIUL

—

DSPI_3

—

SIUL

—

DSPI_3

SIUL

—

DSPI_1

LINFlex_1

SIUL

DSPI_1

—

DSPI_0

DSPI_3

SIUL

DSPI_1 nexus_0

DSPI_0

SIUL

—

LINFlex_1

DSPI_1

SIUL

—

DSPI_3

SIUL

—

DSPI_3

—

DSPI_3

SIUL

—

ADC_0

Input Only

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

Slow

—

Medium

—

105

123

119

129

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104

Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Port pin

PCR

No.

E[0] PCR[64]

E[1] PCR[65]

E[2] PCR[66]

E[3] PCR[67]

E[4] PCR[68]

E[5] PCR[69]

E[6] PCR[70]

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[69]

—

AN[8]

GPIO[70]

—

AN[9]

GPIO[67]

—

AN[6]

GPIO[68]

—

AN[7]

GPIO[64]

—

AN[21]

GPIO[65]

—

AN[4]

GPIO[66]

—

AN[5]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

Port E

Input Only

—

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SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

Port pin

PCR

No.

E[7] PCR[71]

E[8] PCR[72]

E[9] PCR[73]

E[10] PCR[74]

E[11] PCR[75]

E[12] PCR[76]

E[13] PCR[77]

E[14] PCR[78]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[76]

—

AN[26]

GPIO[77]

SCK_3

—

EIRQ[25]

GPIO[73]

—

AN[23]

GPIO[74]

—

AN[24]

GPIO[75]

—

AN[25]

GPIO[78]

SOUT_3

—

EIRQ[26]

GPIO[71]

—

AN[10]

GPIO[72]

—

AN[22]

SIUL

—

ADC_0

SIUL

DSPI_3

—

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

—

ADC_0

SIUL

DSPI_3

—

SIUL

—

ADC_0

SIUL

—

ADC_0

Input Only

I/O

—

I/O

—

Slow

—

Medium

—

117

119

141

143

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104

Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Port pin

PCR

No.

E[15] PCR[79]

F[0] PCR[80]

F[1] PCR[81]

F[2] PCR[82]

F[3] PCR[83]

F[4] PCR[84]

F[5] PCR[85]

F[6] PCR[86]

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

MDO[3]

—

MDO[2]

—

GPIO[86]

—

MDO[1]

—

GPIO[80]

DBG_0

CS3_3

—

EIRQ[28]

GPIO[81]

DBG_1

CS2_3

—

EIRQ[29]

GPIO[82]

DBG_2

CS1_3

—

GPIO[83]

DBG_3

CS0_3

—

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

—

GPIO[79]

—

SIN_3

EIRQ[27]

SIUL

—

DSPI_3

SIUL

—

— nexus_0

—

— nexus_0

—

SIUL

— nexus_0

—

Port F

SIUL

FlexRay_0

DSPI_3

—

SIUL

I/O

—

SIUL

FlexRay_0

DSPI_3

—

SIUL

FlexRay_0

DSPI_3

—

SIUL

FlexRay_0

DSPI_3

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

Slow

Medium

Fast

—

121

133

135

137

139

145

157

159

161

167

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DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

Port pin

PCR

No.

F[7] PCR[87]

F[8] PCR[88]

F[9] PCR[89]

F[10] PCR[90]

F[11] PCR[91]

F[12] PCR[92]

F[13] PCR[93]

F[14] PCR[94]

F[15] PCR[95]

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

GPIO[87]

—

MCKO

—

GPIO[88]

—

MSEO1

—

GPIO[89]

—

MSEO0

—

GPIO[90]

—

EVTO

—

GPIO[91]

EVTI

—

GPIO[92]

ETC[3]

—

GPIO[93]

ETC[4]

—

GPIO[94]

TXD

—

GPIO[95]

—

RXD

SIUL

— nexus_0

—

SIUL

— nexus_0

—

SIUL

— nexus_0

—

SIUL

— nexus_0

—

SIUL nexus_0

—

SIUL eTimer_1

—

SIUL eTimer_1

—

SIUL

LINFlex_1

—

SIUL

—

LINFlex_1

Slow

Fast

Medium

—

106

112

115

113

130

136

139

137

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104

Package pinouts and signal descriptions SPC56xP54x, SPC56xP60x

Port pin

PCR

No.

G[0] PCR[96]

G[1] PCR[97]

G[2] PCR[98]

G[3] PCR[99]

G[4] PCR[100]

G[5] PCR[101]

G[6] PCR[102]

G[7] PCR[103]

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

GPIO[100]

—

SCK_4

—

GPIO[101]

—

CS0_4

—

GPIO[102]

—

CS1_4

—

GPIO[103]

—

CS2_4

—

GPIO[96]

F[0]

—

EIRQ[30]

GPIO[97]

F[1]

—

EIRQ[31]

GPIO[98]

—

SIN_4

GPIO[99]

—

SOUT_4

—

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

SIUL

—

DSPI_4

—

SIUL

—

DSPI_4

—

SIUL

—

DSPI_4

—

SIUL

—

DSPI_4

—

SIUL

FCCU

—

SIUL

Port G

I/O

—

SIUL

FCCU

—

SIUL

—

DSPI_4

SIUL

—

DSPI_4

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

Slow

Medium

—

141

102

104

100

173

126

128

124

103

122

101

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SPC56xP54x, SPC56xP60x Package pinouts and signal descriptions

Port pin

PCR

No.

Alternate function

(3)

(2),

Table 7. Pin muxing (1) (continued)

Pad speed (6)

Functions

Peripheral

(4)

I/O direction

(5) SRC = 0 SRC = 1

Pin

LQFP

100

LQFP

144

LQFP

176

(7)

G[8] PCR[104]

G[9] PCR[105]

G[10] PCR[106]

G[11] PCR[107]

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

ALT0

ALT1

ALT2

ALT3

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[104]

—

CS3_4

—

GPIO[105]

—

RXD

GPIO[106]

—

TXD

—

GPIO[107]

—

SIUL

—

DSPI_4

—

SIUL

—

FlexCAN_1

SIUL

—

FlexCAN_1

—

SIUL

—

I/O

—

I/O

—

I/O

—

I/O

—

Slow

Medium

—

1. This table concerns Enhanced Full-featured version. Please refer to “SPC56xP54x/SPC56xP60x device configuration difference” table for difference between Enhanced Full-featured, Full-featured, and Airbag configuration.

2. ALT0 is the primary (default) function for each port after reset.

3. Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.

PCR[PA] = 00  ALT0; PCR[PA] = 01  ALT1; PCR[PA] = 10  ALT2; PCR[PA] = 11  ALT3. This is intended to select the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

4. Module included on the MCU.

5. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMI[PADSEL x ] bitfields inside the SIUL module.

6. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

7. LQFP176 available only as development package.

8. Weak pull down during reset.

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Electrical characteristics SPC56xP54x, SPC56xP60x

3.1 Introduction

This section contains electrical characteristics of the device as well as temperature and power considerations.

This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V

DD or V

). This can be done by the internal pull-up or pull-down, which is provided by the product for most general purpose pins.

The parameters listed in the following tables represent the characteristics of the device and its demands on the system.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the

Symbol column.

Caution: All of the following parameter values can vary depending on the application and must be confirmed during silicon validation, silicon characterization or silicon reliability trial.

The electrical parameters shown in this supplement are guaranteed by various methods. To

give the customer a better understanding, the classifications listed in Table 8 are used and

the parameters are tagged accordingly in the tables where appropriate.

Classification tag

Table 8. Parameter classifications

Tag description

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.

Those parameters are derived mainly from simulations.

Note: The classification is shown in the column labeled “C” in the parameter tables where appropriate.

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SPC56xP54x, SPC56xP60x Electrical characteristics

3.3 Absolute maximum ratings

Symbol

SS_HV

DD_HV_IOx

(3)

SS_HV_IOx

DD_HV_FL

SS_HV_FL

DD_HV_OSC

SS_HV_OSC

DD_HV_REG

DD_HV_AD

SS_HV_AD

INAN

INJPAD

Table 9. Absolute maximum ratings (1)

Parameter Conditions

SR Digital ground

—

3.3 V / 5.0 V input/output supply voltage with respect to ground

SS_HV

)

Input/output ground voltage with respect to ground (V

SS_HV

)

—

3.3 V / 5.0 V code and data flash memory supply voltage with respect to ground (V

SS_HV

)

—

Relative to

DD_HV_IOx

Code and data flash memory ground with respect to ground (V

SS_HV

)

—

3.3 V / 5.0 V crystal oscillator amplifier supply voltage with respect to ground (V

SS_HV

)

—

Relative to

DD_HV_IOx

3.3 V / 5.0 V crystal oscillator amplifier reference voltage with respect to ground (V

SS_HV

)

—

3.3 V / 5.0 V voltage regulator supply voltage with respect to ground

SS_HV

)

3.3 V / 5.0 V ADC supply and high reference voltage with respect to ground (V

SS_HV

)

Relative to

DD_HV_IOx

DD_HV_REG

< 2.7 V

—

DD_HV_REG

> 2.7 V

ADC ground and low reference voltage with respect to ground

SS_HV

)

Slope characteristics on all V

DD during power up

(4)

with respect to ground (V

SS_HV

)

—

Voltage on any pin with respect to ground (V

SS_HV_IOx ground (V

SS_HV

)

) with respect to

SR Analog input voltage

—

Relative to

DD_HV_IOx

DD_HV_REG

< 2.7 V

DD_HV_REG

> 2.7 V

Injected input current on any pin during overload condition

—

Min

–0.3

–0.1

–0.3

–0.1

–0.3

–0.1

– 0.3

–0.1

3.0

(5)

Max

(2)

6.0

0.1

6.0

DD_HV_IOx

0.3

0.1

6.0

DD_HV_IOx

0.3

0.1

6.0

DD_HV_IOx

0.3

DD_HV_REG

+ 0.3

6.0

0.1

500 x 10

(0.5 [V/µs])

–0.3

SS_HV_AD

0.3



6.0

DD_HV_IOx

0.3

DD_HV_AD

0.3

SS_HV_AD

–10

DD_HV_AD

Unit

V/s

V mA

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Electrical characteristics SPC56xP54x, SPC56xP60x

Symbol

Table 9. Absolute maximum ratings (1) (continued)

Parameter Conditions Min Max (2) Unit

INJSUM

Absolute sum of all injected input currents during overload condition

— –50 50 mA

VDD_LV

Low voltage static current sink through V

DD_LV

SR Storage temperature

— — 155 mA

STG

SR Junction temperature under bias

—

–55

–40

150

°C

1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device.

2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined.

3. The difference between each couple of voltage supplies must be less than 300 mV, |V

DD_HV_IOy

– V

DD_HV_IOx

| < 300 mV.

4. Guaranteed by device validation.

5. Minimum value of TV

must be guaranteed until V

DD_HV_REG

reaches 2.6 V (maximum value of V

PORH

Figure 5 shows the constraints of the different power supplies.

Figure 5. Power supplies constraints

6.0V

VDD_HV_xxx

50/105

-0.3V

6.0V

VDD_HV_IOx

The SPC56xP54x/SPC56xP60x supply architecture provides an ADC supply that is managed independently of standard V

DD_HV

ADC power supply.

supply.

Figure 6 shows the constraints of the

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x

Figure 6. Independent ADC supply (e)

Electrical characteristics

VDD_HV_AD

6.0V

-0.3V

2.7V

6.0V

VDD_HV_REG

3.4 Recommended operating conditions

Symbol

SS_HV

DD_HV_IOx

(2)

SS_HV_IOx

DD_HV_FL

SS_HV_FL

DD_HV_OSC

SS_HV_OSC

Table 10. Recommended operating conditions (5.0 V)

Parameter Conditions Min

SR Digital ground

5.0 V input/output supply voltage

—

SR Input/output ground voltage

5.0 V code and data flash memory supply voltage

—

Relative to

DD_HV_IOx

Code and data flash memory ground

—

5.0 V crystal oscillator amplifier supply voltage

—

Relative to

DD_HV_IOx

5.0 V crystal oscillator amplifier reference voltage

—

4.5

Max

(1)

5.5

DD_HV_IOx

– 0.1 V

DD_HV_IOx

+ 0.1

DD_HV_IOx

– 0.1 V

DD_HV_IOx

+ 0.1

5.5

Unit

V e. Device design targets the removal of this conditions. To be confirmed by design during device validation.

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Electrical characteristics SPC56xP54x, SPC56xP60x

Symbol

Table 10. Recommended operating conditions (5.0 V) (continued)

Parameter Conditions Min Max (1) Unit

DD_HV_REG

DD_HV_AD

SS_HV_AD

—

5.0 V voltage regulator supply voltage

Relative to

DD_HV_IOx

—

5.0 V ADC supply and high reference voltage

Relative to

DD_HV_REG

ADC ground and low reference voltage

—

DD_LV_REGCOR

(3),(4)

SS_LV_REGCOR

SS_LV_CORx

SR Internal supply voltage

SR Internal reference voltage

SR Internal supply voltage

SR Internal reference voltage

Ambient temperature under bias

—

4.5

DD_HV_IOx

4.5

– 0.1 V

DD_HV_IOx

DD_HV_REG

– 0.1

—

–40

5.5

—

125

+ 0.1

1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.

In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV, |V

DD_HV_IOy

– V

DD_HV_IOx

| < 100 mV.

3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (V

SS_LV_xxx

) must be shorted to high voltage grounds (V emitter.

SS_HV_xxx

) and the low voltage supply pins (V

DD_LV_xxx

) must be connected to the external ballast

4. The low voltage supplies (V

DD_LV_COR1

and V

DD_LV_xxx

DD_LV_COR2

) are not all independent. 

are shorted internally via double bonding connections with lines that provide the low

DD_LV_REGCOR

and V

DD_LV_REGCORx

SS_LV_COR1

and V

are physically shorted internally, as are V

are internally shorted.

SS_LV_REGCOR

and V

SS_LV_CORx



°C

Symbol

SS_HV

DD_HV_IOx

(2)

SS_HV_IOx

DD_HV_FL

SS_HV_FL

DD_HV_OSC

SS_HV_OSC

Table 11. Recommended operating conditions (3.3 V)

Parameter Conditions Min

0 SR Digital ground

3.3 V input/output supply voltage

SR Input/output ground voltage

3.3 V code and data flash memory supply voltage

—

Relative to

DD_HV_IOx

Code and data flash memory ground

—

3.3 V crystal oscillator amplifier supply voltage

—

Relative to

DD_HV_IOx

3.3 V crystal oscillator amplifier reference voltage

—

3.0

Max (1)

3.6

DD_HV_IOx

– 0.1 V

DD_HV_IOx

+ 0.1

DD_HV_IOx

– 0.1 V

DD_HV_IOx

+ 0.1

3.6

Unit

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SPC56xP54x, SPC56xP60x Electrical characteristics

Symbol

Table 11. Recommended operating conditions (3.3 V) (continued)

Parameter Conditions Min Max (1) Unit

DD_HV_REG

DD_HV_AD

3.3 V voltage regulator supply voltage

3.3 V ADC supply and high reference voltage

—

Relative to

DD_HV_IOx

—

3.0

DD_HV_IOx

– 0.1 V

3.0

Relative to

DD_HV_REG

– 0.1

3.6

DD_HV_IOx

5.5

+ 0.1

SS_HV_AD

ADC ground and low reference voltage

DD_LV_REGCOR

(3),(4)

DD_LV_CORx

SR Internal supply voltage

SR Internal reference voltage

SR Internal supply voltage

SR Internal reference voltage

Ambient temperature under bias

—

–40

—

125

1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.

In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

2. The difference between each couple of voltage supplies must be less than 100 mV, |V

DD_HV_IOy

– V

DD_HV_IOx

| < 100 mV.

SS_LV_xxx

) must be shorted to high voltage grounds (V emitter.

SS_HV_xxx

) and the low voltage supply pins (V

DD_LV_xxx

) must be connected to the external ballast

4. The low voltage supplies (V

DD_LV_COR1

and V

DD_LV_xxx

DD_LV_COR2

) are not all independent. 

are shorted internally via double bonding connections with lines that provide the low

DD_LV_REGCOR

and V

DD_LV_REGCORx

SS_LV_COR1

and V

are physically shorted internally, as are V

are internally shorted.

SS_LV_REGCOR

and V

SS_LV_CORx



°C

Figure 7 shows the constraints of the different power supplies.

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Electrical characteristics SPC56xP54x, SPC56xP60x

Figure 7. Power supplies constraints (f)

5.5V

VDD_HV_xxx

3.3V

3.2V

5.5V

VDD_HV_IOx

3.2V

3.3V

The SPC56xP54x/SPC56xP60x supply architecture provides an ADC supply that is managed independently of standard V

DD_HV

ADC power supply.

supply.

Figure 8 shows the constraints of the

54/105

IO AC and DC characteristics are guaranteed only in the range 3.0 V–3.6 V when PAD3V5V is low, and in the range 4.5 V–5.5 V when PAD3V5V is high.

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x

VDD_HV_AD

Figure 8. Independent ADC supply

Electrical characteristics

5.5V

3.0V

5.5V

VDD_HV_REG

Symbol

Table 12. Thermal characteristics for 144-pin LQFP

Parameter Conditions Typical value Unit

 JA

 JB

 JCtop



D Thermal resistance junction-to-ambient,

D natural convection

(1)

D Thermal resistance junction-to-board

(2)

D Thermal resistance junction-to-case (top)

D Junction-to-board, natural convection

D Junction-to-case, natural convection

(4)

(5)

(3)

Single layer board—1s

Four layer board—2s2p

Single layer board—1s

Operating conditions

53.4

43.9

29.6

9.3

29.8

1.3

°C/W

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification for this package.

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.

3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.

5. Thermal characterization parameter indicating the temperature difference between the case and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.

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Electrical characteristics SPC56xP54x, SPC56xP60x

Symbol

Table 13. Thermal characteristics for 100-pin LQFP

Parameter Conditions Typical value Unit

 JA

 JB

 JCtop



Thermal resistance junction-to-ambient, natural convection

(1)

D Thermal resistance junction-to-board

(2)

D Thermal resistance junction-to-case (top)

D Junction-to-board, natural convection

(4)

D Junction-to-case, natural convection

(5)

(3)

Single layer board—1s

Four layer board—2s2p

Single layer board—1s

Operating conditions

47.3

35.6

19.1

9.1

19.1

1.1

°C/W

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification for this package.

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.

3.5.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T

, can be obtained from

Equation 1

Equation 1 T

= T

+ (R

 JA

× P

) where:

= ambient temperature for the package ( o C)

 JA

= junction to ambient thermal resistance ( o

C/W)

= power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a

junction to case thermal resistance and a case to ambient thermal resistance:

Equation 2 R

 JA

= R

 JC

+ R

 CA where:

 JA

= junction to ambient thermal resistance (°C/W)

 JC

= junction to case thermal resistance (°C/W)

 CA

= case to ambient thermal resistance (°C/W)

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 JC

is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, R

 CA

. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter ( 

) can be used to determine the junction temperature with a measurement of the temperature at the top center of the

package case using Equation 3

Equation 3 T

= T

+ ( 

× P

) where:

= thermocouple temperature on top of the package (°C)



= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package.

A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

3.5.1.1 References

Semiconductor Equipment and Materials International 

3081 Zanker Road 

San Jose, CA 95134 U.S.A.



(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering

Documents at 800-854-7179 or 303-397-7956.

JEDEC specifications are available on the WEB at jedec.org web site.

1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module , Proceedings of SemiTherm, San Diego, 1998, pp.

47-54.

2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled

Applications , Electronic Packaging and Production, pp. 53-58, March 1998.

3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling , Proceedings of SemiTherm, San

Diego, 1999, pp. 212-220.

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Electrical characteristics SPC56xP54x, SPC56xP60x

Parameter Symbol

RE_TEM

Radiated emissions, electric field

Table 14. EMI testing specifications

Conditions

= 5 V;

= 25 °C

150 kHz–30 MHz

RBW 9 kHz, Step

Size 5 kHz

30 MHz–1 GHz

RBW 120 kHz,

Step Size 80 kHz f

OSC

BUS

Frequency

8 MHz crystal

64 MHz bus

No PLL frequency modulation

150 kHz–150 MHz

150–1000 MHz

IEC Level

8 MHz crystal

64 MHz bus

±2% PLL frequency modulation

150 kHz–150 MHz

150–1000 MHz

IEC Level

Level

(Max)

Unit dB  V

— dB  V

—

Symbol

Table 15. ESD ratings

(1)(2)

Parameter Conditions Value Unit

ESD(HBM)

ESD(CDM)

SR Electrostatic discharge (Human Body Model)

SR Electrostatic discharge (Charged Device Model)

—

2000

750 (corners)

500 (other)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.

3.8.1

Note:

Voltage regulator electrical characteristics

The internal voltage regulator requires an external NPN ballast to be connected as shown in

Figure 9 . Table 16

contains all approved NPN ballast components. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the V

DD_HV_REG

, BCTRL and V

DD_LV_CORx

Reg

see Table 17

pins to less than

The voltage regulator output cannot be used to drive external circuits. Output pins are used only for decoupling capacitances.

DD_LV_COR

must be generated using internal regulator and external NPN transistor. It is not possible to provide V

DD_LV_COR

through external regulator.

For the SPC56xP54x/SPC56xP60x microcontroller, capacitors, with total values not below

DEC1

, should be placed between V microcontroller pins between each V

DD_LV_CORx

SS_LV_CORx

close to external ballast transistor emitter. 4 capacitors, with total values not below C

DD_LV_CORx

DEC2

, should be placed close to

SS_LV_CORx

supply pairs and the

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DD_LV_REGCOR

SS_LV_REGCOR

pair. Additionally, capacitors with total values not below

DEC3

, should be placed between the V

DD_HV_REG

SS_HV_REG

pins close to ballast collector. Capacitors values have to take into account capacitor accuracy, aging and variation versus temperature.

All reported information are valid for voltage and temperature ranges described in recommended operating condition,

Table 10

and Table 11

Figure 9. Voltage regulator configuration

VDD_HV_REG

SPC56xP54x/SPC5 C

DEC3

BCTRL BJT

(1)

VDD_LV_COR

DEC2

DEC1

1. Refer to Table 16

Part

Table 16. Approved NPN ballast components

Manufacturer Approved derivatives

(1)

BCP68

BCX68

BC868

BC817

BCP56

ON Semi

NXP

Infineon

NXP

Infineon

NXP

Infineon

ON Semi

NXP

BCP68

BCP68-25

BCX68-10;BCX68-16;BCX68-25

BC868

BC817-16;BC817-25;BC817SU;

BC817-16;BC817-25

BCP56-16

BCP56-10;BCP56-16

BCP56-10

BCP56-10;BCP56-16

1. For automotive applications please check with the appropriate transistor vendor for automotive grade certification.

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Electrical characteristics SPC56xP54x, SPC56xP60x

Table 17. Voltage regulator electrical characteristics

Symbol C Parameter Conditions

Value

Min Typ Max

Unit

DD_LV_REGCOR

CC P

Output voltage under maximum load run supply current configuration

DEC1

REG

DEC2

DEC3

Reg

Post-trimming 1.15

— 1.32

SR —

External decoupling/stability ceramic capacitor

Resulting ESR of all three capacitors of C capacitor C

External decoupling/stability ceramic capacitor on

DD_HV_REG

DEC1

Resulting ESR of the unique

DEC1

External decoupling/stability ceramic capacitor

SR —

Resulting ESL of V

DD_HV_REG

BCTRL and V

DD_LV_CORx

pins

BJT from Table 16

. 3 capacitances (i.e. X7R or

X8R capacitors) with nominal value of 10 µF

19.5

30 — µF

BJT BC817, one capacitance of 22 µF

14.3

22 µF

BJT from Table 16

. 3x10 µF.

Absolute maximum value between 100 kHz and

10 MHz

BJT BC817, 1x 22 µF.

Absolute maximum value between 100 kHz and

10 MHz

—

40 m m



4 capacitances (i.e. X7R or

X8R capacitors) with nominal value of 440 nF

1200 1760 — nF

3 capacitances (i.e. X7R or

X8R capacitors) with nominal value of 10 µF; C

DEC3

has to be equal or greater than

DEC1

19.5

30 — µF

— — — 15 nH

3.8.2 Voltage monitor electrical characteristics

The device implements a Power On Reset module to ensure correct power-up initialization, as well as three low voltage detectors to monitor the V device is supplied:

and the V

DD_LV

voltage while

 POR monitors V

DD reset state

during the power-up phase to ensure device is maintained in a safe

 LVDHV3 monitors V

to ensure device reset below minimum functional supply

 LVDHV5 monitors V

when application uses device in the 5.0V ± 10% range

 LVDLVCOR monitors low voltage digital power domain

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Table 18. Low voltage monitor electrical characteristics

Symbol Parameter

PORH

PORUP

REGLVDMOK_H

REGLVDMOK_L

FLLVDMOK_H

FLLVDMOK_L

IOLVDMOK_H

IOLVDMOK_L

IOLVDM5OK_H

IOLVDM5OK_L

MLVDDOK_H

MLVDDOK_L

T Power-on reset threshold

P Supply for functional POR module

P Regulator low voltage detector high threshold

P Regulator low voltage detector low threshold

P Flash memory low voltage detector high threshold

P Flash memory low voltage detector low threshold

P I/O low voltage detector high threshold

P I/O low voltage detector low threshold

P I/O 5V low voltage detector high threshold

P I/O 5V low voltage detector low threshold

P Digital supply low voltage detector high

P Digital supply low voltage detector low

1. V

= 3.3V ± 10% / 5.0V ± 10%, T

= –40 °C to T

A MAX

, unless otherwise specified.

—

= 25°C

—

Conditions

(1)

Value

Min Max

2.6

—

2.6

—

1.5

1.0

—

2.6

—

3.8

—

1.08

2.7

—

2.95

—

2.95

—

2.95

—

4.4

—

1.15

—

Unit

To prevent an overstress event or a malfunction within and outside the device, the

SPC56xP54x/SPC56xP60x implements the following sequence to ensure each module is started only when all conditions for switching it ON are available:

A POWER_ON module working on voltage regulator supply controls the correct startup of the regulator. This is a key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5V. Associated POWER_ON (or POR) signal is active low.

– Several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage regulator, I/Os, flash memory and low voltage domain). LVDs are gated low when POWER_ON is active.

– A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active high and released to all modules including I/Os, flash memory and RC16 oscillator needed during power-up phase and reset phase. When POWER_OK is low the associated modules are set into a safe state.

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Electrical characteristics SPC56xP54x, SPC56xP60x

Figure 10. Power-up typical sequence

VDD_HV_REG

POR_UP

POWER_ON

LVDM (HV)

VDD_LV_REGCOR

PORH

LVDD (LV)

POWER_OK

RC16MHz Oscillator

Internal Reset Generation Module

FSM

LVDHV3H

MLVDOK_H

~1us

P0 P1

1.2V

3.3V

1.2V

3.3V

Figure 11. Power-down typical sequence

VDD_HV_REG

LVDHV3L V

PORH

LVDM (HV)

POWER_ON

VDD_LV_REGCOR

LVDD (LV)

POWER_OK

RC16MHz Oscillator

Internal Reset Generation Module

FSM IDLE P0

1.2V

3.3V

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Figure 12. Brown-out typical sequence

LVDHV3L

LVDHV3H

VDD_HV_REG

LVDM (HV)

POWER_ON

VDD_LV_REGCOR

LVDD (LV)

POWER_OK

RC16MHz Oscillator

Internal Reset Generation Module

FSM

IDLE P0

~1us

1.2V

3.3V

Portions of the device configuration, such as high voltage supply, and watchdog enable/disable after reset are controlled via bit values in the non-volatile user options register (NVUSRO) register.

For a detailed description of the NVUSRO register, please refer to the device reference manual.

3.10.1 NVUSRO[PAD3V5V] field description

Table 19 shows how NVUSRO[PAD3V5V] controls the device configuration.

Value

(2)

Table 19. PAD3V5V field description (1)

Description

High voltage supply is 5.0 V

High voltage supply is 3.3 V

1. See the device reference manual for more information on the NVUSRO register.

2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.

The DC electrical characteristics are dependent on the PAD3V5V bit value.

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Electrical characteristics

3.11 DC electrical characteristics

SPC56xP54x, SPC56xP60x

Table 20 gives the DC electrical characteristics at 5 V (4.5 V < V

DD_HV_IOx

NVUSRO[PAD3V5V]=0) as described in Figure 13

< 5.5 V,

Figure 13. I/O input DC electrical characteristics definition

HYS

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

Symbol

Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)

Parameter

D Minimum low level input voltage

Conditions

—

Min

–0.1

(1)

Max

—

OL_S

OH_S

OL_M

OH_M

OL_F

OH_F

HYS

OL_SYM

P Maximum level input voltage

P Minimum high level input voltage

D Maximum high level input voltage

—

T Schmitt trigger hysteresis —

P Slow, low level output voltage

P Slow, high level output voltage

P Fast, high level output voltage

= 3 mA

= –3 mA

P Medium, low level output voltage I

= 3 mA

P Medium, high level output voltage I

= –3 mA

P Fast, low level output voltage I

= 3 mA

= –3 mA

Symmetric, low level output voltage

= 3 mA

—

0.65 V

DD_HV_IOx

—

0.1 V

DD_HV_IOx

—

0.8V

DD_HV_IOx

—

0.8 V

DD_HV_IOx

—

0.8 V

DD_HV_IOx

—

0.35 V

DD_HV_IOx

—

DD_HV_IOx

+ 0.1

(1)

—

0.1 V

DD_HV_IOx

—

0.1 V

DD_HV_IOx

—

0.1 V

DD_HV_IOx

—

0.1 V

DD_HV_IOx

OH_SYM

Symmetric, high level output voltage

= –3 mA 0.8 V

DD_HV_IOx

—

Unit

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Table 20. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) (continued)

Symbol Parameter Conditions Min Max

P Equivalent pull-up current

P Equivalent pull-down current

= V

–130

—

Input leakage current

(all bidirectional ports)

Input leakage current

(all ADC input-only ports)

= –40 to 125 °C

–1

–0.5

D Input capacitance — —

D RESET, equivalent pull-up current

RESET, equivalent pull-down current

= V

–130

—

1. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9

—

–10

—

130

—

–10

—

130

0.5

Unit

µA

µA pF

µA

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Electrical characteristics SPC56xP54x, SPC56xP60x

Table 21. Supply current (5.0 V, NVUSRO[PAD3V5V]=0)

Value

Symbol Parameter Conditions Unit

Typ Max

RUN — Maximum Mode

(1)

DD_LV_CORE externally forced at 1.3 V 

ADC Freq = 32 MHz

PLL Freq = 64 MHz

64 MHz 90 120

DD_LV_CORE

RUN - Platform consumption, single core

(2)

RUN - Platform consumption, dual core

(3)

VDD_LV_CORE externally forced to 1.3V

16 MHz 21

40 MHz 35

64 MHz 48

16 MHz 24

40 MHz 42

64 MHz 58

DD_FLASH

Supply current

RUN — Maximum Mode

HALT Mode

STOP Mode

(5)

(6)

(4)

DD_LV_CORE externally forced at 1.3 V

Flash memory supply current during read

DD_HV_FL

at 5.0 V

Flash memory supply current during erase operation on 1 flash memory module

DD_HV_FL

at 5.0 V

64 MHz

—

5.5

4.5

—

113

42 mA

DD_ADC

ADC supply current —

Maximum Mode

DD_HV_AD

at 5.0 V

ADC Freq = 16 MHz

— 3 4

DD_OSC

T OSC supply current V

DD_OSC

at 5.0 V 8 MHz 2.6

3.2

1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM enabled. I/O supply current excluded.

2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz on, PLL64MHz OFF (except for code running at 64 MHz).



Code is performing continuous data transfer from Flash to RAM.

3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,

PLL64MHz OFF (except for code running at 64 MHz).



Code is performing continuous data transfer from Flash to RAM.

4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM enabled. I/O supply current excluded.

5. HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

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Table 22 gives the DC electrical characteristics at 3.3 V (3.0 V < V

DD_HV_IOx

NVUSRO[PAD3V5V]=1) as described in Figure 14

< 3.6 V,

Figure 14. I/O input DC electrical characteristics definition

HYS

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

Symbol

Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)

(1)

Parameter

D Minimum low level input voltage

Conditions

—

Min

–0.1

(2)

Max

—

OL_S

OH_S

OL_M

OH_M

OL_F

OH_F

HYS

OL_SYM

P Maximum low level input voltage

P Minimum high level input voltage

D Maximum high level input voltage

—

T Schmitt trigger hysteresis —

P Slow, low level output voltage

P Slow, high level output voltage

P Fast, high level output voltage

= 1.5 mA

= –1.5 mA

P Medium, low level output voltage I

= 2 mA

P Medium, high level output voltage I

= –2 mA

P Fast, high level output voltage I

= 11 mA

= –11 mA

Symmetric, high level output voltage

= 1.5 mA

—

0.65 V

DD_HV_IOx

—

0.1 V

DD_HV_IOx

—

DD_HV_IOx

– 0.8

—

DD_HV_IOx

– 0.8

—

0.35 V

DD_HV_IOx

—

DD_HV_IOx

+ 0.1

(2)

—

0.5

—

0.5

—

0.5

DD_HV_IOx

– 0.8

—

0.5

OH_SYM

Symmetric, high level output voltage

= –1.5 mA V

DD_HV_IOx

– 0.8

—

Unit

P Equivalent pull-up current

= V

–130

—

–10

µA

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Electrical characteristics SPC56xP54x, SPC56xP60x

Table 22. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) (1) (continued)

Symbol Parameter Conditions Min Max

P Equivalent pull-down current

= V

—

Input leakage current 

(all bidirectional ports)

Input leakage current 

(all ADC input-only ports)

= –40 to 125 °C

—

D Input capacitance — —

D RESET, equivalent pull-up current

RESET, equivalent pull-down current

= V

–130

—

1. These specifications are design targets and subject to change per device characterization.

2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9

—

130

0.5

—

–10

—

130

Unit

µA

µA pF

µA

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Table 23. Supply current (3.3 V, NVUSRO[PAD3V5V]=1)

Value

Symbol Parameter Conditions Unit

Typ Max

DD_LV_CORE

RUN — Maximum Mode

RUN - Platform consumption, single core

RUN - Platform consumption, dual core

(3)

(2)

(1)

DD_LV_CORE externally forced at

1.3 V 

ADC Freq = 32 MHz

PLL Freq = 64 MHz

64 MHz 90

16 MHz 21

40 MHz 35

VDD_LV_CORE externally forced to 1.3V

64 MHz 48

16 MHz 24

40 MHz 42

64 MHz 58

120

Supply current

RUN — Maximum Mode

HALT Mode

STOP Mode

(5)

(6)

(4)

DD_LV_CORE externally forced at

1.3 V

DD_LV_CORE externally forced at

1.3 V

DD_LV_CORE externally forced at

1.3 V

64 MHz

—

5.5

4.5

113

13 mA

DD_FLASH

Flash memory supply current during read

Flash memory supply current during erase operation on 1 flash memory module

DD_HV_FL

at 3.3 V

—

DD_ADC

ADC supply current —

Maximum Mode

DD_HV_AD

at 3.3 V

ADC Freq = 16 MHz

— 3 4

DD_OSC

T OSC supply current V

DD_OSC

at 3.3 V 8 MHz 2.4

1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM enabled. I/O supply current excluded.

2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz on, PLL64MHz OFF (except for code running at 64 MHz).



Code is performing continuous data transfer from Flash to RAM.

3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,

PLL64MHz OFF (except for code running at 64 MHz).



Code is performing continuous data transfer from Flash to RAM.

4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,

LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM enabled. I/O supply current excluded.

6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.

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Table 24. Peripherals supply current (5 V and 3.3 V) (1)

Value

Symbol Parameter Conditions Unit

Typ Max

DD_HV(CAN)

DD_HV(SCI)

CAN (FlexCAN) supply current on

VDD_HV_REG

SCI (LINFlex) supply current on

VDD_HV_REG

500 Kbyte/s

Total (static + dynamic) consumption:

– FlexCAN in loop-back mode

– XTAL@ 8 MHz used as CAN engine clock source

– Message sending period is 580

µs

Total (static + dynamic) consumption:

– LIN mode

– Baudrate: 115.2 Kbyte/s

DD_HV(SPI)

DD_HV(ADC)

DD_HV_ADC(ADC)

DD_HV(eTimer)

DD_HV(FlexRay)

SPI (DSPI) supply current on

VDD_HV_REG

ADC supply current on VDD_HV_REG

ADC supply current on VDD_HV_ADC

T eTimer supply current on VDD_HV_REG

FlexRay supply current on

VDD_HV_REG

Ballast dynamic consumption (continuous communication):

– Baudrate: 2 Mbit/s

– Transmission every 8 µs

– Frame: 16 bits

VDD = 5.5 V

PWM signals generation on all 1 channel @10kHz

Static consumption

Ballast dynamic consumption

(continuous conversion)

Analog dynamic consumption

(continuous conversion)

Dynamic consumption does not change varying the frequency

1. Operating conditions: f periph

= 8 MHz to 64 MHz

21.6 * f

10.8 * f

4.8 * f

120 * f

4.2 * f periph periph periph periph periph

28.1* f

14.1 * f

6.3 * f

156 * f periph periph periph periph

0.005 * f periph

+ 2.8 0.007 * f periph

+ 3.4 mA

1.8

2.4

µA mA

SPC56xP54x, SPC56xP60x Electrical characteristics

Package

LQFP100

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V

supply pair as described in

Table 25

Table 25. I/O supply segment

Supply segment

LQFP144 pin8 – pin20 pin15 – pin26

2 pin23 – pin38 pin27 – pin38

3 pin39 – pin55 pin41 – pin46

4 pin58 – pin68 pin51 – pin61

5 pin73 – pin89 pin64 – pin86

6 pin92 – pin125 pin89 – pin10

7 pin128 – pin5

—

Table 26. I/O consumption

Symbol C Parameter Conditions

(1)

Value

Min Typ Max

Unit

SWTMED

(2)

SWTSLW

(2)

SWTFST

(2)

RMSSLW

RMSMED

CC D

Dynamic I/O current for SLOW configuration

Dynamic I/O current for MEDIUM configuration

Dynamic I/O current for FAST configuration

= 25 pF

= 5.0 V ± 10%, 

PAD3V5V = 0

= 3.3 V ± 10%, 

PAD3V5V = 1

= 5.0 V ± 10%, 

PAD3V5V = 0

= 3.3 V ± 10%, 

PAD3V5V = 1

= 5.0 V ± 10%, 

PAD3V5V = 0

= 3.3 V ± 10%, 

PAD3V5V = 1

CC D

= 25 pF, 2 MHz

= 25 pF, 4 MHz

Root medium square

I/O current for SLOW configuration

= 100 pF, 2 MHz

= 25 pF, 2 MHz

= 25 pF, 4 MHz

= 100 pF, 2 MHz

CC D

= 25 pF, 13 MHz

Root medium square

I/O current for

MEDIUM configuration

= 25 pF, 40 MHz

= 100 pF, 13 MHz

= 25 pF, 13 MHz

= 25 pF, 40 MHz

= 100 pF, 13 MHz

= 5.0 V ± 10%, 

PAD3V5V = 0

= 3.3 V ± 10%, 

PAD3V5V = 1

= 5.0 V ± 10%, 

PAD3V5V = 0

= 3.3 V ± 10%, 

PAD3V5V = 1

—

17 mA mA

— 110 mA

— 50

—

2.3

4.7

— 6.6

— 13.4

2.3

3.2

6.6

1.6

— 18.3

— 5

—

8.5

11 mA mA

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Electrical characteristics SPC56xP54x, SPC56xP60x

Table 26. I/O consumption (continued)

Symbol C Parameter Conditions

(1)

Value

Min Typ Max

Unit

RMSFST

AVGSEG

CC D

SR D

= 25 pF, 40 MHz

= 25 pF, 64 MHz

Root medium square

I/O current for FAST configuration

= 100 pF, 40 MHz

= 25 pF, 40 MHz

= 25 pF, 64 MHz

= 100 pF, 40 MHz

Sum of all the static

I/O current within a supply segment

= 5.0 V ± 10%, PAD3V5V = 0

= 5.0 V ± 10%,

PAD3V5V = 0

= 3.3 V ± 10%,

PAD3V5V = 1

= 3.3 V ± 10%, PAD3V5V = 1



1. V

= 3.3 V ± 10% / 5.0 V ± 10%, T

= –40 to 125 °C, unless otherwise specified.

2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

—

— mA mA

3.12 Main oscillator electrical characteristics

The SPC56xP54x/SPC56xP60x provides an oscillator/resonator driver.

Table 27. Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)

Symbol Parameter Min Max Unit f

OSC g m

OSC t

OSCSU

SR Oscillator frequency

Transconductance

Oscillation amplitude on EXTAL pin

T Start-up time

(1),(2)

6.5

—

MHz mA/V

V ms

1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive loads can cause long start-up time.

2. Value captured when amplitude reaches 90% of EXTAL.

Table 28. Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)

Symbol Parameter Min Max Unit f

OSC g m

OSC t

OSCSU

SR Oscillator frequency

Transconductance

Oscillation amplitude on EXTAL pin

T Start-up time

(1),(2)

—

MHz mA/V

V ms

1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive loads can cause long start-up time.

2. Value captured when amplitude reaches 90% of EXTAL.

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SPC56xP54x, SPC56xP60x Electrical characteristics

Symbol f

OSC f

CLK t rCLK t

Table 29. Input clock characteristics

Parameter

SR Oscillator frequency

SR Frequency in bypass

SR Rise/fall time in bypass

SR Duty cycle

Min

—

47.5

Typ

—

Max Unit

52.5

MHz

MHz ns

3.13 FMPLL electrical characteristics

Table 30. PLLMRFM electrical specifications (V

= T

DDPLL

= 1.08 V to 1.32 V, V

to T

)

= V

SSPLL

= 0 V,

Value

Symbol Parameter Conditions Unit min max f ref_crystal f ref_ext

D PLL reference frequency range

(1)

Crystal reference f pll_in f

FMPLLOUT f

FREE f sys t

CYC f

LORL f

LORH f

SCM

JITTER

Phase detector input frequency range

(after pre-divider)

D Clock frequency range in normal mode

Free running frequency

On-chip PLL frequency

D System clock period

—

Measured using clock division — typically /16

—

D Loss of reference frequency window

(2)

—

Lower limit

Upper limit

D Self-clocked mode frequency

(3),(4)

Short-term jitter

(9)

CLKOUT period jitter

(5),(6),(7),(8)

Long-term jitter (avg. over 2 ms interval)

— f

SYS

maximum f

PLLIN

= 16 MHz

(resonator) , f

PLLCLK

at 64 MHz,

4000 cycles t lpll t dc f

LCK f

D PLL lock time

(10), (11)

D Duty cycle of reference

Frequency LOCK range

Frequency un-LOCK range f

CS f

D Modulation Depth f

MOD

D Modulation frequency

(13)

1. Considering operation with PLL not bypassed.

—

Center spread

Down Spread

—

–6

–18

±0.25

–0.5

—

1.6

–4

120

150

200

±4.0

(12)

–8.0

1 / f sys

3.7

150

MHz

MHz ns

MHz

% f

CLKOUT ns

µs

% f sys

%f sys kHz

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Electrical characteristics SPC56xP54x, SPC56xP60x

2. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.

3. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f window.

LOR

4. f self clock range is 20–150 MHz. f mode.

SCM

represents f

SYS

after PLL output divider (ERFD) of 2 through 16 in enhanced

5. This value is determined by the crystal manufacturer and board design.

6. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f injected into the PLL circuitry via V percentage for a given interval.

DDPLL

and V

SSPLL

and variation in crystal oscillator frequency increase the C

SYS

JITTER

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

7. Proper PC board layout procedures must be followed to achieve specifications.

8. Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C either f

or f

(depending on whether center spread or down spread modulation is enabled).

JITTER

and

9. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

PLL, load capacitors should not exceed these limits.

11. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR).

12. This value is true when operating at frequencies above 60 MHz, otherwise f

is 2% (above 64 MHz).

13. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

3.14 16 MHz RC oscillator electrical characteristics

Symbol

Table 31. 16 MHz RC oscillator electrical characteristics

Parameter Conditions Min Typ Max Unit



 f

RCMVAR

RCMTRIM

RCMSTEP

P RC oscillator frequency

Fast internal RC oscillator variation over temperature and supply with respect to f

RC at T A = 25 °C in high-frequency configuration

Post Trim Accuracy: The variation of the PTF

(1)

from the 16 MHz

Fast internal RC oscillator trimming step

= 25 °C

—

= 25 °C

—

–6

–1

—

1.6

1. PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and temperature

— MHz

—

The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital

Converter.

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Figure 15. ADC characteristics and error definitions

Offset Error OSE Gain Error GE

1020

1019

1018

1023

1022

1021

1 LSB ideal = V

DD_ADC

/ 1024

(2) code out

(4)

1 LSB (ideal)

(3)

1 2 3 4 5 6 7

Offset Error OSE

(5)

(1)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error

(DNL)

(4) Integral non-linearity error

(INL)

1017 1018 1019 1020 1021 1022 1023

V in(A)

(LSB ideal

)

3.15.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high-frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuate the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a highimpedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be measured.

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Electrical characteristics SPC56xP54x, SPC56xP60x

The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being C

and C

P2 substantially two switched capacitances, with a frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.

For instance, assuming a conversion rate of 1 MHz, with C

S resistance of 330 k  is obtained (R

+ C

equal to 3 pF, a

= 1 / (fc ×  (C

+ C

)), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on C

+ C

) and the sum of R

the external circuit must be designed to respect the Equation 4 :

+ R

Equation 4



+ R

---------------------



LSB

Equation 4 generates a constraint for external network design, in particular on resistive path.

Internal switch resistances (R

SW resistances.

and R

) can be neglected with respect to external

Figure 16. Input equivalent circuit (precise channels)

Source

EXTERNAL CIRCUIT

Filter

Current Limiter

INTERNAL CIRCUIT SCHEME

Channel

Selection

Sampling

SW1

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

SW1

Channel Selection Switch Impedance

Sampling Switch Impedance

Pin Capacitance (two contributions, C

)

and

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SPC56xP54x, SPC56xP60x Electrical characteristics

Figure 17. Input equivalent circuit (extended channels)

Source

EXTERNAL CIRCUIT

Filter

Current Limiter

INTERNAL CIRCUIT SCHEME

Channel

Selection

Extended

Switch

Sampling

SW1

SW2

: Source impedance

: Filter resistance

: Filter capacitance

: Current limiter resistance

SW1

: Channel selection switch impedance (two contributions, R

SW1

and R

SW2

)

: Sampling switch impedance

: Pin capacitance (two contributions, C

, C

and C

)

: Sampling capacitance

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C

, C

and C

P2 are initially charged at the source voltage V

(refer to the equivalent circuit reported in

Figure 16 ): A charge sharing phenomenon is installed when

the sampling phase is started (A/D switch close).

Figure 18. Transient behavior during sampling phase

Voltage Transient on C

 V <  0.5 LSB 



< (R

+ R

) C

<< T



= R

+ C

)

S t

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Electrical characteristics SPC56xP54x, SPC56xP60x

In particular two different transient periods can be distinguished:

 A first and quick charge transfer from the internal capacitance C

P1 sampling capacitance C

occurs (C

and C

to the

is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which

is reported in parallel to C

(call C

are in series, and the time constant is

= C

+ C

), the two capacitances C

and

Equation 5



=  R

+ R

 



Equation 5 can again be simplified considering only C

as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T

S longer than the internal time constant:

is always much

Equation 6



  R

+ R

  C

« T

The charge of C

P1 voltage V

and C

is redistributed also on C

, determining a new value of the on the capacitance according to

Equation 7

Equation 7

  C

+ C

 = V

  C

+ C



 A second charge transfer involves also C

F capacitance) through the resistance R

L and C

were in parallel to C time constant is:

(that is typically bigger than the on-chip

: again considering the worst case in which C

(since the time constant in reality would be faster), the

Equation 8



 R

  C

+ C



In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time T

sizing is obtained:

, a constraint on

Equation 9

8.5

 

= 

  C

+ C

  T

Of course, R

shall be sized also according to the current limitation constraints, in combination with R

(source impedance) and R

F definitively bigger than C

, C

and C charge transfer transient) will be much higher than V

(charge balance assuming now C

(filter resistance). Being C

, then the final voltage V

(at the end of the

. Equation 10

must be respected

already charged at V

Equation 10

  C

+ C

 = V

 C

+ V

  C

+ C



The two transients above are not influenced by the voltage source that, due to the presence of the R

filter, is not able to provide the extra charge to compensate the voltage drop on

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SPC56xP54x, SPC56xP60x Electrical characteristics

with respect to the ideal source V

A respect to the sampling time (T

; the time constant R

of the filter is very high with

). The filter is typically designed to act as anti-aliasing.

Figure 19. Spectral representation of input signal

Analog Source Bandwidth (V

)

Noise

 2 R

(Conversion Rate vs. Filter Pole) f

 f

(Anti-aliasing Filtering Condition)

2 f

 f

(Nyquist) f

0 f

Anti-Aliasing Filter (f

= RC Filter pole) Sampled Signal Spectrum (f

= conversion Rate) f

F f f

0 f

C f

Calling f

the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f

F at least 2f

; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (T

C sampling time T

), according to the Nyquist theorem the conversion rate f

). Again the conversion period T

must be

is longer than the

, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter R sampling time T

, so the charge level on C

is definitively much higher than the

cannot be modified by the analog signal source during the time in which the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on C

; from the two charge balance equations above, it is simple to derive

Equation 11 between the ideal and real sampled voltage on C

Equation 11

----------

From this formula, in the worst case (when V

is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on C

value:

Equation 12

 

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Electrical characteristics SPC56xP54x, SPC56xP60x

3.15.2 ADC conversion characteristics

Table 32. ADC conversion characteristics

Symbol

INAN

Parameter

SR Analog input voltage

(2)

Conditions

(1)

—

Min

SS_HV_AD

 0.3



Value

Typ

—

Max

SS_HV_AD

+ 0.3

Unit

V f

CK f s t

ADC_S t

ADC_C

(8)

SW1

(8)

SW2

(8)

INJ

INL

DNL

OFS

GNE

TUE

ADC Clock frequency

(depends on ADC configuration)

(The duty cycle depends on

AD_clk

(3)

frequency)

SR Sampling frequency

D Sample time

(5)

P Conversion time

(6)

—

— f

ADC

= 20 MHz, 

INPSAMP = 3 f

ADC

= 9 MHz, 

INPSAMP = 255 f

ADC

= 20 MHz

(7)

, 

INPCMP = 1

ADC input sampling capacitance

D ADC input pin capacitance 1

D ADC input pin capacitance 2

P Differential Non Linearity

T Offset error

No overload

—

D ADC input pin capacitance 3

—

Internal resistance of analog source

DD_HV_AD

= 5 V ±10%

DD_HV_AD

= 3.3 V ±10%

DD_HV_AD

= 5 V ±10%

DD_HV_AD

= 3.3 V ±10%

Internal resistance of analog source

—

T Input current injection

P Integral Non Linearity

Current injection on one ADC input, different from the converted one. Remains within TUE spec.

No overload

—

— T Gain error

Total unadjusted error without current injection

16 precision channels

(4)

—

125

—

0.650

—

–5

—

–1.0

—

–2.5

—

±1.5

—

±1

—

1.53

—

28.2

—

2.5

0.6

2.15

3.6

—

1.0

—

2.5

MHz

MHz ns

µs

µs pF

LSB

LSB pF pF pF k  k  k  k  k  mA

LSB

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SPC56xP54x, SPC56xP60x Electrical characteristics

Symbol

Table 32. ADC conversion characteristics (continued)

Value

Parameter Conditions

(1)

Min Typ

Unit

Max

TUE

Total unadjusted error with current injection

16 precision channels

10 standard channels

–3

–4

—

LSB

1. V

= 3.3 V to 3.6 V / 4.5 V to 5.5 V, T

SS_HV_AD

to V

DD_HV_AD

= –40 °C to T

A MAX

, unless otherwise specified and analog input voltage from

2. V

INAN

may exceed V

SS_ADC

and V

DD_ADC

limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF.

3. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

4. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.

5. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t

ADC_S

. After the end of the sample time t clock t

ADC_S

, changes of the analog input voltage have no effect on the conversion result. Values for the sample

ADC_S

depend on programming.

6. This parameter includes the sample time t

ADC_S

7. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

8. See

Figure 16 .

3.16 Flash memory electrical characteristics

Symbol

T wprogram

T dwprogram

BKPRG

MDPRG

16kpperase

32kpperase

64kpperase

128kpperase t

ESRT

Table 33. Program and erase specifications

Parameter Conditions

Min Typ

(1)

Value

Initial max (2)

P Word Program (32 bits) Time

(4)

P Double Word (64 bits) Program Time (4)

P Bank Program (64 KB)

(4),

(5)

P Bank Program (1056 KB)

(4), (5)

P Module Program (512 KB)

(4)

P 16 KB Block Pre-program and Erase Time

P 32 KB Block Pre-program and Erase Time

P 64 KB Block Pre-program and Erase Time

P 128 KB Block Pre-program and Erase Time

P Erase Suspend Request Rate

(6)

Max

(3)

Unit

Data Flash —

Code Flash —

Data Flash — 0.49

Code Flash —

2.6

1.3

1.2

6.6

1.65

500

4.1

Code Flash

Data Flash

—

200

700

Code Flash — 300

500

800

600

5000 ms

Code Flash — 400 900

5000 ms

Code Flash — 600 1300 5000 ms

Code Flash 20

— — — ms

Data Flash 10

µs

µs s s s

1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization.

2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

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Electrical characteristics SPC56xP54x, SPC56xP60x

3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed.

4. Actual hardware programming times. This does not include software overhead.

5. Typical bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).

6. Time between erase suspend resume and next erase suspend.

Table 34. Flash memory module life

Value

Symbol Parameter Conditions Unit

Min Typ

P/E

Number of program/erase cycles per block for 16 KB blocks over the operating temperature range (T

)

Number of program/erase cycles per block for 32 KB blocks over the operating temperature range (T

)

Number of program/erase cycles per block for 64 KB blocks over the operating temperature range (T

)

Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (T

)

—

100000

10000

1000

100000 cycles

Retention C

Minimum data retention at 85 °C average ambient temperature

(1)

Blocks with 0 – 1000

P/E cycles

Blocks with 10000 P/E cycles

Blocks with 100000 P/E cycles

—

— years years years

1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range.

Symbol C

Table 35. Flash read access timing

Parameter Conditions

(1)

Fmax C

Maximum working frequency for Code Flash at given number of WS in worst conditions

2 wait states

0 wait states

Fmax C

Maximum working frequency for Data Flash at given number of WS in worst conditions

8 wait states

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.

Max Unit

MHz

66 MHz

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Table 36. Output pin transition times

Symbol C Parameter Conditions

(1)

T tr tr tr sim

(3)

Output transition time output pin

(2)



SLOW configuration

Output transition time output pin

(2)



MEDIUM configuration

CC D

Output transition time output pin

(2)



FAST configuration

CC T

Symmetric, same drive strength between N and P transistor

= 25 pF

= 50 pF

= 100 pF

= 5.0 V ± 10%, 

PAD3V5V = 0

= 25 pF

= 50 pF

= 3.3 V ± 10%,

PAD3V5V = 1

= 100 pF

= 25 pF V

= 50 pF

= 5.0 V ± 10%,

PAD3V5V = 0

= 100 pF

SIUL.PCRx.SRC = 1

= 25 pF V

= 50 pF

= 3.3 V ± 10%,

PAD3V5V = 1

= 100 pF

SIUL.PCRx.SRC = 1

= 25 pF V

= 50 pF

= 5.0 V ± 10%,

PAD3V5V = 0

= 100 pF

SIUL.PCRx.SRC = 1

= 25 pF V

= 50 pF

= 3.3 V ± 10%,

PAD3V5V = 1

= 100 pF

SIUL.PCRx.SRC = 1

= 5.0 V ± 10%, PAD3V5V = 0

= 3.3 V ± 10%, PAD3V5V = 1

1. V

= 3.3 V ± 10% / 5.0 V ± 10%, T

= –40 °C to T

A MAX

, unless otherwise specified.

2. C

includes device and package capacitances (C

PKG

< 5 pF).

3. Transition timing of both positive and negative slopes will differ maximum 50 %.

Value

Min Typ Max

Unit

— — 50

— — 100

— — 125

— — 40

— — 50

— — 75

— — 10

— — 20

— — 40

— — 12

— — 25

— — 40

— — 4

— — 6

— — 12

— — 4

— — 7

— — 12

— — 4

— — 5 ns ns ns ns

3.18.1 RESET pin characteristics

The SPC56xP54x/SPC56xP60x implements a dedicated bidirectional RESET pin.

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Electrical characteristics SPC56xP54x, SPC56xP60x

Figure 20. Start-up reset requirements (g)

DDMIN

RESET

IL device reset forced by V

RESET

POR device start-up phase

Figure 21. Noise filtering on reset signal

RESET

DD hw_rst

‘1’ filtered by

hysteresis filtered by

lowpass filter

FRST filtered by

lowpass filter

FRST unknown reset state

NFRST device under hardware reset

‘0’

84/105

g. The output drive provided is open drain and hence must be terminated by an external resistor of value 1 k 

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Electrical characteristics

Table 37. RESET electrical characteristics

Value

Symbol C Parameter Conditions

(1)

Unit

Min Typ Max

SR P

Input High Level CMOS

(Schmitt Trigger)

SR P

Input low Level CMOS

(Schmitt Trigger)

—

HYS

CC C

Input hysteresis CMOS

(Schmitt Trigger)

—

Push Pull, I

= 5.0 V ±

= 2mA,

(recommended)



10%, PAD3V5V = 0 

OL tr

CC P Output low level

CC D

Output transition time output pin

(3) 

MEDIUM configuration

SR P RESET input filtered pulse

Push Pull, I

= 1mA, 

= 5.0 V ± 10%, PAD3V5V = 1

(2)

Push Pull, I

= 3.3 V ±

= 1mA,

(recommended)



10%, PAD3V5V = 1 

= 25pF, 

= 5.0 V ± 10%, PAD3V5V = 0

= 50pF, 

= 5.0 V ± 10%, PAD3V5V = 0

= 100pF, 

= 5.0 V ± 10%, PAD3V5V = 0

= 25pF, 

= 3.3 V ± 10%, PAD3V5V = 1

= 50pF, 

= 3.3 V ± 10%, PAD3V5V = 1

= 100pF, 

= 3.3 V ± 10%, PAD3V5V = 1

— W

FRST

NFRST

SR P

RESET input not filtered pulse

—

0.65V

 0.4

0.1V

—

500

— V

—

+0.4

0.35V

—

0.1V

0.5

—

V ns ns ns

POR

CC D maximum delay before internal reset is released after all VDD_HV reach nominal supply

Monotonic VDD_HV supply ramp — — 1 ms

WPU

| CC P

Weak pull-up current absolute value

= 3.3 V ± 10%, PAD3V5V = 1

= 5.0 V ± 10%, PAD3V5V = 0

= 5.0 V ± 10%, PAD3V5V = 1

(4)

—

150

250

1. V

= 3.3 V ± 10% / 5.0 V ± 10%, T

= –40 °C to T

A MAX

, unless otherwise specified.

2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device reference manual).

3. C

includes device and package capacitance (C

PKG

< 5 pF).

4. The configuration PAD3V5 = 1 when V

= 5 V is only transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

µA

DocID18340 Rev 6

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104

Electrical characteristics SPC56xP54x, SPC56xP60x

3.18.2 IEEE 1149.1 interface timing

No.

Symbol C

Table 38. JTAG pin AC electrical characteristics

Parameter

2 t

JCYC t

JDC

3 t

TCKRISE

4 t

TMSS, t

TDIS

5 t

TMSH, t

TDIH

6 t

TDOV

10 t

TDOI t

TDOHZ t

BSDV t

BSDVZ

13 t

BSDHZ t

BSDST t

BSDHT

CC D TCK cycle time

CC D TCK clock pulse width (measured at V

DD_HV_IOx

/2)

CC D TCK rise and fall times (40% – 70%)

CC D TMS, TDI data setup time

CC D TMS, TDI data hold time

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

CC D TCK low to TDO high impedance

CC D TCK falling edge to output valid

CC D TCK falling edge to output valid out of high impedance

CC D TCK falling edge to output high impedance

CC D Boundary scan input valid to TCK rising edge

CC D TCK rising edge to boundary scan input invalid

Conditions Min Max Unit

—

100 — ns

40 60 ns

— 3 ns

5 — ns

25 — ns

— 40 ns

0 — ns

40 — ns

— 50 ns

50 — ns

Figure 22. JTAG test clock input timing

TCK

86/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Electrical characteristics

Figure 23. JTAG test access port timing

TCK

TMS, TDI

7 8

TDO

DocID18340 Rev 6

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104

Electrical characteristics SPC56xP54x, SPC56xP60x

Figure 24. JTAG boundary scan timing

TCK

Output

Signals

Output

Signals

Input

Signals

No.

Symbol t

MCYC t

MDOV t

MSEOV t

EVTOV t

TCYC

Table 39. Nexus debug port timing (1)

CC D TCK cycle time

Parameter

CC D MCKO cycle time

CC D MCKO edge to MDO data valid

CC D MCKO edge to MSEO data valid

CC D MCKO edge to EVTO data valid

Value

Min

–

0.1 × t

MCYC

–

0.1 × t

MCYC

–

0.1 × t

MCYC

(2)

Typ

—

Max

—

0.25 × t

—

MCYC

Unit ns ns ns ns ns

88/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Electrical characteristics

No.

Symbol C

Table 39. Nexus debug port timing (1) (continued)

Value

Parameter

Min Typ

9 t

NTDIS t

NTMSS t

NTDIH t

NTMSH t

TDOV t

TDOI

CC D TDI data setup time

CC D TMS data setup time

CC D TDI data hold time

CC D TMS data hold time

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

1. All values need to be confirmed during device validation.

2. Lower frequency is required to be fully compliant to standard.

—

Max

—

Unit ns ns ns ns ns ns

Figure 25. Nexus output timing

MCKO

MDO

MSEO

EVTO

Output Data Valid

Figure 26. Nexus event trigger and test clock timings

TCK

EVTI

EVTO

DocID18340 Rev 6

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104

Electrical characteristics SPC56xP54x, SPC56xP60x

Figure 27. Nexus TDI, TMS, TDO timing

TCK

TMS, TDI

TDO

No.

Symbol C

Table 40. External interrupt timing (1)

Parameter Conditions Min Max Unit

3 t

IPWL t

IPWH t

ICYC

D IRQ pulse width low

D IRQ pulse width high

CC D IRQ edge to edge time

(2)

—

4 + N

(3)

—

1. IRQ timing specified at f

SYS

= 64 MHz and V

DD_HV_IOx

= 3.0 V to 5.5 V, T

= T

to T

, and CL = 200pF with SRC = 0b00.

2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

3. N= ISR time to clear the flag.

CYC t

CYC

90/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x

Figure 28. External interrupt timing

Electrical characteristics

IRQ

No.

Symbol C Parameter

Table 41. DSPI timing (1)

Conditions

2 t

3 t

4 t

11 t t t t

SCK

CSC

ASC

SDC t t

DIS

7 t

PCSC

8 t

PASC

SUI

SUO

CC D DSPI cycle time

CC D PCS to SCK delay

CC D After SCK delay

CC D SCK duty cycle

CC D Slave access time

CC D Slave SOUT disable time

CC D PCSx to PCSS time

CC D PCSS to PCSx time

CC D Data setup time for inputs

Master (MTFE = 0)

Slave (MTFE = 0)

—

SS active to SOUT valid

SS inactive to SOUT High-Z or invalid

—

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

CC D Data hold time for inputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

Slave

CC D Data valid (after SCK edge)

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

–5

—

–5

Min Max

—

0.4 × t

SCK

—

0.6 × t

SCK

Unit ns ns ns ns ns

— 16 ns

—

— ns ns ns ns ns

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104

Electrical characteristics

No.

Symbol C

Table 41. DSPI timing (1) (continued)

Parameter Conditions

12 t

CC D Data hold time for outputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

1. All timing are provided with 50pF capacitance on output, 1ns transition time on input signal

SPC56xP54x, SPC56xP60x

Min

–2

Max

—

Unit ns

Figure 29. DSPI classic SPI timing — master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data

Last Data

92/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Electrical characteristics

Figure 30. DSPI classic SPI timing — master, CPHA = 1

CSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data

Last Data

Figure 31. DSPI classic SPI timing — slave, CPHA = 0

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Data

Last Data

DocID18340 Rev 6

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104

Electrical characteristics SPC56xP54x, SPC56xP60x

Figure 32. DSPI classic SPI timing — slave, CPHA = 1

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Data

Last Data

Figure 33. DSPI modified transfer format timing — master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data

Last Data

94/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Electrical characteristics

Figure 34. DSPI modified transfer format timing — master, CPHA = 1

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data

Last Data

Figure 35. DSPI modified transfer format timing — slave, CPHA = 0

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Data

11 12

Last Data

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104

Electrical characteristics SPC56xP54x, SPC56xP60x

Figure 36. DSPI modified transfer format timing — slave, CPHA = 1

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Data

Last Data

PCSS

PCSx

Figure 37. DSPI PCS strobe (PCSS) timing

96/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Package characteristics

4.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

4.2 Package mechanical data

Figure 38. LQFP144 package mechanical drawing

Seating plane

A A2 A1 ccc C b c

109

108 73

0.25 mm gage plane k

E3 E1 E

Pin 1 identification

144

1 e

ME_1A

DocID18340 Rev 6

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104

Package characteristics SPC56xP54x, SPC56xP60x

Table 42. LQFP144 mechanical data mm

Symbol

Min Typ Max Min e

L1 k ccc

(2)

E3 b c

—

0.050

1.350

0.170

0.090

21.800

19.800

—

21.800

19.800

—

0.450

—

0.0 °

17.500

22.000

20.000

17.500

0.500

0.600

1.000

3.5 °

0.080

—

1.400

0.220

—

22.000

20.000

1.600

0.150

1.450

0.270

0.200

22.200

20.200

—

22.200

20.200

—

0.750

—

7.0°

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Tolerance.

—

0.8583

0.7795

—

0.0177

—

3.5 °

—

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

inches

(1)

Typ

0.6890

0.8661

0.7874

0.6890

0.0197

0.0236

0.0394

0.0 °

0.0031

—

0.0551

0.0087

—

0.8661

0.7874

Max

—

0.8740

0.7953

—

0.0295

—

7.0 °

0.0630

0.0059

0.0571

0.0106

0.0079

0.8740

0.7953

98/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x

Package characteristics

Figure 39. LQFP100 package mechanical drawing

0.25 mm

0.10 inch

GAGE PLANE k

50 b

E3 E1 E

100

Pin 1 identification

Symbol

26 ccc C e

SEATING PLANE

1L_ME

Min

—

0.050

1.350

Table 43. LQFP100 mechanical data mm

Typ

—

1.400

Max

1.600

0.150

1.450

Min

—

0.0020

0.0531

inches

(1)

Typ

—

0.0551

Max

0.0630

0.0059

0.0571

DocID18340 Rev 6

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104

Package characteristics SPC56xP54x, SPC56xP60x

Table 43. LQFP100 mechanical data (continued) mm inches (1)

Symbol

Min Typ Max Min

E1 b c

0.170

0.090

15.800

13.800

—

15.800

13.800

0.220

—

16.000

14.000

12.000

16.000

14.000

0.270

0.200

16.200

14.200

—

16.200

14.200

E3 e

—

0.450

—

12.000

0.500

0.600

1.000

—

0.750

—

0.0177

— k ccc

(2)

0.0 ° 3.5 °

0.080

7.0 ° 0.0 °

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Tolerance.

0.0067

0.0035

0.6220

0.5433

—

0.6220

0.5433

Typ

0.4724

0.0197

0.0236

0.0394

3.5 °

0.0031

0.0087

—

0.6299

0.5512

0.4724

0.6299

0.5512

Max

0.0106

0.0079

0.6378

0.5591

—

0.6378

0.5591

—

0.0295

—

7.0 °

100/105

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Ordering information

Figure 40. Ordering information scheme (h)

Example code:

Product identifier

SPC56

Core Family

A P

Memory

Package

Temperature

Custom vers.

EFA

Conditioning

Y = Tray 

R = Tape and Reel 



X = Tape and Reel 90° 

A = 5 V, 64 MHz 

B = 3,3 V, 64 MHz 



A = “Airbag” feature set 



F = “Full feature” set 



E = Data flash memory 

B = –40 to 105 °C 

C = –40 to 125 °C 



L5 = LQFP144 



L3 = LQFP100 

60 = 1 MB 

54 = 768 KB 



P = SPC56xP54x/SPC56xP60x family 



A = Dual core e200z0h 



0 = Single core e200z0h 

SPC56 = Power Architecture in 90nm h. Not all configurations are available on the market. Please contact your ST sales representative to get the list of orderable commercial part number.

DocID18340 Rev 6

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104

Revision history

102/105

SPC56xP54x, SPC56xP60x

Table 44 summarizes revisions to this document.

Date

21-Dec-2010

18-Oct-2011

Revision

Table 44. Document revision history

Substantive changes

Initial release

In the Feature list: 

Revised the first bullet.



Changed “Up to 82 GPIO” to “Up to 80 GPIO” 

Changed “and 82 GPIO” to “and 49 GPIO” 

Changed “FlexRay module“ to “1 FlexRay™ module”.

Added

Section 1.5: Feature details

Table 4: SPC56xP54x/SPC56xP60x series block summary

, added

FlexRay entry.

In the “LQFP176 pinout (top view)” figure:

– Pin 104 now is TDI, was PB[5]

– Pin 107 now is TDO, was PB[4]

– Pin 71 now is NC, was OKOUT

– Pin 72 now is NC, was OKOUT_B

– Pin 87 now is NC, was NBYPASS_HV

– Pin 88 now is NC, was IPP_LIVI_B_VDDIO

Table 7: Pin muxing :



PB[6] was clk_out_div5, is now clk_out_div256 

Removed PB[4] and PB[5] rows 

In the A[3] row, changed ABS[2] to ABS[1]

Section 3.11: DC electrical characteristics , added “Peripherals supply

current (5 V and 3.3 V)” table

Table 14: EMI testing specifications , removed all references to SAE

Replaced both

Table 12: Thermal characteristics for 144-pin LQFP

and

Table 13: Thermal characteristics for 100-pin LQFP

Table 30: PLLMRFM electrical specifications (V

DDPLL

1.32 V, V

of f

SYS

= V

SSPLL

from 120 to 64

Table 33: Program and erase specifications :



Removed all TBC 

= 1.08 V to

= 0 V, TA = TL to TH)

, changed the max value changed the initial max value of T

BKPRG

6.6 s 

(Code Flash) from 3.3 to changed the max value of T changed the max value of T

Added t

ESRT row

BKPRG

(Data Flash) from 1.9 to 4.1 s  wprogram

(Data Flash) from 300 to 500 µs 

Table 17: Voltage regulator electrical characteristics

, updated

DD_LV_REGCOR

values

Updated

Table 18: Low voltage monitor electrical characteristics

Updated

Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0)

and

Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1)

Removed “NVUSRO[OSCILLATOR_MARGIN] field description” section.

Removed orderable parts tables.

DocID18340 Rev 6

SPC56xP54x, SPC56xP60x Revision history

Date

15-May-2012

Table 44. Document revision history (continued)

Revision Substantive changes

Removed “Enhanced Full-featured” version.

In the cover page, added “(1 × Master/Slave, 1 × Master Only)“ at the end of the bullet “2 LINFlex modules (LIN 2.1)”

Table 2: SPC56xP54x/SPC56xP60x device comparison

, updated the value of “LINFLEX module” to “2 (1 × Master/Slave, 1 × Master only)”

Section 1.5.4: On-chip flash memory with ECC 

replaced two occurrences of “3 wait states” to “2 wait states”  replaced 60 MHz to 64 MHz

Section 1.5.21: Serial communication interface module (LINFlex)

, updated first bullet to “Supports LIN Master mode (on both modules),

LIN Slave mode (on one module) and UART mode”

Section 1.5.24: Analog-to-digital converter (ADC) , removed bullet

concerning the analog watchdogs from Normal mode features.

Table 5: Supply pins , removed V

REG_BYPASS

row.

Table 6: System pins :

 added V

REG_BYPASS

row  added a footnote about RESET

Table 9: Absolute maximum ratings

:  changed typical value of TV

DD added V

INAN

entry

to 0.25 and added a footnote 

Updated

Section 3.8.1: Voltage regulator electrical characteristics

Updated

Table 14: EMI testing specifications

Table 18: Low voltage monitor electrical characteristics , changed

maximum value of V

MLVDDOK_H to 1.15

Table 20: DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)

, added IPU and IPD rows for RESET pin.

Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0) :

 added maximum values of I

DD_LV_CORE

for: RUN, HALT, and STOP mode  updated values and parameter classification of I

DD_FLASH

Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)

, added IPU and IPD rows for RESET pin.

Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1) :

 added maximum values of I

DD_LV_CORE

for: RUN, HALT, and STOP mode  updated values and parameter classification of I

DD_FLASH

Added

Table 26: I/O consumption

Table 31: 16 MHz RC oscillator electrical characteristics

, changed minimum and maximum values of



RCMVAR

respectively to -6 and 6.

Renamed Figure 16: Input equivalent circuit (precise channels) (was

“Input equivalent circuit”)

Added

Figure 17: Input equivalent circuit (extended channels)

Section 3.15.1: Input impedance and ADC accuracy

, updated Equation

and Equation 10

Table 32: ADC conversion characteristics

, added V

INAN rows

, C

and R

SW2

DocID18340 Rev 6

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104

Revision history SPC56xP54x, SPC56xP60x

Date

21-Nov-2012

18-Sep-2013

15-Jun-2016

Table 44. Document revision history (continued)

Revision Substantive changes

In the cover page, replaced “64 MHz, dual issue, 32-bit CPU core complex” with “64 MHz, single issue, 32-bit CPU core complex”

Table 9: Absolute maximum ratings

, updated TV

entry

Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) :



Updated conditions value of V

OL_F

OH_F

to 11 mA 

to – 11 mA

Table 24: Peripherals supply current (5 V and 3.3 V) :



Replaced all occurrences of I

DD_BV

in this table with I

DD_HV 

Replaced all occurrences of VDD_BV in this table with

VDD_HV_REG.

Figure 40: Ordering information scheme

, fixed typo in the footnote.

Updated Disclaimer.

Added “AEC-Q10x qualified” in

Features

section.

Table 2: SPC56xP54x/SPC56xP60x device comparison

added footnote “LinFlex_1 is Master Only.” related to row “LINFlex modules”

Updated

Table 3: SPC56xP54x/SPC56xP60x device configuration difference

Figure 2: LQFP176 pinout (top view)

– Changed PB[4] to TDO

– Changed PB[5] to TDI

– Changed pins 71,72 to NC

– Changed pins 87,88 to NC

Section 1.5.27: Nexus development interface (NDI)

, added note “At least one TCK clock is necessary for the EVTI signal to be recognized by the MCU.” for EVTI pin.

Table 7: Pin muxing :

– Replaced “PCR register” with “PCR No.”

– Updated “CS3” with “CS3_4” function related to A[2] port pin

– In column “I/O direction”, added “O” for “DSPI_1” peripheral

– In “Functions” column related to D[12] port pin, changed DS7_1 to

CS7_1

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SPC56xP54x, SPC56xP60x

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DocID18340 Rev 6

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105

32-bit Power Architecture

®

based MCU with 1088KB Flash memory and 80KB RAM for automotive chassis and safety applications

-

Features

Contents

List of tables

List of figures

1 Introduction

1.2 Description

1.5.1

1.5.2

High performance e200z0h core processor

Crossbar switch (XBAR)

1.5.4

On-chip flash memory with ECC

1.5.5

On-chip SRAM with ECC

1.5.7

System clocks and clock generation

1.5.12 System timer module (STM)

1.5.18 FlexCAN

1.5.19 Safety port (FlexCAN)

1.5.20 FlexRay

1.5.23 eTimer

1.5.27 Nexus development interface (NDI)

1.5.28 IEEE 1149.1 (JTAG) controller

1.5.29 On-chip voltage regulator (VREG)

2

Package pinouts and signal descriptions

2.2.1 Power supply and reference voltage pins

3.1 Introduction

3.3 Absolute maximum ratings

3.4 Recommended operating conditions

3.5.1 General notes for specifications at maximum junction temperature

3.8.1

Voltage regulator electrical characteristics

3.8.2 Voltage monitor electrical characteristics

3.10.1 NVUSRO[PAD3V5V] field description

3.11 DC electrical characteristics

3.12 Main oscillator electrical characteristics

3.13 FMPLL electrical characteristics

3.14 16 MHz RC oscillator electrical characteristics

3.15.1 Input impedance and ADC accuracy

3.15.2 ADC conversion characteristics

3.16 Flash memory electrical characteristics

3.18.1 RESET pin characteristics

3.18.2 IEEE 1149.1 interface timing

4.1 ECOPACK

4.2 Package mechanical data

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