STMicroelectronics BlueNRG-1 Datasheet

1. Not available on WCSP34.

If they have been programmed as wake-up source in the system controller registers.

Sleep state

In this state:

• Only the digital power supplies necessary to keep the RAM in retention are used.

DS11481 - Rev 10 page 9/167

BlueNRG-1

Power management

3.4.2

3.4.2.1

3.4.2.2

3.4.3

• The low frequency oscillator is switched on.

•

The wake-up from this low power state is driven by the following sources:

• IO9

•

IO10

IO11

IO12

• IO13

Figure 7. Reset and wake-up generation shows the general principle of reset. Releasing the reset pin puts

1. Not available on WCSP34.

If they have been programmed as wake-up source in the system controller registers and from the internal timers of the BLE radio.

GPIO management during low power modes

IO wake-up sources

The IOs programmed to be wake-up sources need an external drive according to the selected level sensitivity.

If the wake-up level is high level, a pull-down drive should be used. If the wake-up level is low level, a pull-up drive should be used.

IO9, IO10 and IO11 are only sensitive to low level as they have an internal pull-up (activated by default). IO12 and

IO13 do not have an internal pull and therefore require an external drive.

Wake-up time

The wake-up time is typically 200 µs at 3.0 V and a temperature of 25 °C.

Power saving strategy

The application power saving strategy is based on clock stopping, dynamic clock gating, digital power supply switch off and analog current consumption minimization.

A summary of functional blocks versus the BlueNRG-1 states is provided below.

3.4.4

Functional blocks

Table 2. Relationship between the BlueNRG-1 states and functional blocks

RESET STANDBY SLEEP Preactive Active

LOCK RX/

LOCK TX

LDO_SOFT_1V2 or

LDO_SOFT_0V9

LDO_STRONG_1V2

LDO_DIG_1V8

SMPS

LDO_DIG_1V2

BOR

16 MHz RO

16 MHz XO

32 kHz RO or XO

OFF

System controller registers

SYSTEM_CTRL peripheral base address (SYSTEM_CTRL_BASE_ADDR) 0x40200000.

OFF

DS11481 - Rev 10 page 10/167

BlueNRG-1

Power management

Address offset

0x00

0x04

0x08

Name

WKP_IO_IS

WKP_IO_IE

CTRL

Table 3. SYSTEM_CTRL registers

Reset

0x00000000

0x00000007

0x00000000

Description

Level selection for wake-up IO (1 bit for IO).

0: The system wakes up when IO is low.

1: The system wakes up when IO is high.

Enables the IO that wakes up the device (1 bit for

IO).

0: The wake-up feature on the IO is disabled.

1: The wake-up feature on the IO is enabled.

XO frequency indication is provided by the application. Refer to the detailed description below.

Table 4. SYSTEM_CTRL - WKP_IO_IS register description: address offset SYSTEM_CTRL_BASE_ADDR+0x00

Bit

4:0

31:5

Field name

LEVEL_SEL

RESERVED

Reset

0x00

Description

Selects the active wake-up level for the five IOs.

0: The system wakes up when IO is low.

1: The system wakes up when IO is high.

One bit by IO:

Bit0: IO9

Bit1: IO10

Bit2: IO11

Bit3: IO12

Bit4: IO13

RW RESERVED

Table 5. SYSTEM_CTRL - WKP_IO_IE register description: address offset SYSTEM_CTRL_BASE_ADDR+0x04

Bit

4:0

31:5

Field name

IO_WAKEUP_EN

RESERVED

Reset

0x07

0x00

Description

Enables the IOs to be wake-up source.

0: Wake-up on the IO disabled.

1: Wake-up on the IO enabled.

One bit by IO:

Bit0: IO9

Bit1: IO10

Bit2: IO11

Bit3: IO12

Bit4: IO13

RW RESERVED

Table 6. SYSTEM_CTRL - CTRL register description: address offset SYSTEM_CTRL_BASE_ADDR+0x08

Bit

Field name

MHZ32_SEL

Reset

0x0

Description

Indicates the crystal frequency used in the application.

0: The 16 MHz is selected.

DS11481 - Rev 10 page 11/167

BlueNRG-1

Clocks and reset management

Bit

31:1

Field name Reset RW Description

1: The 32 MHz is selected.

RW RESERVED RESERVED 0x0

AHBUPCONV peripheral base address (AHBUPCONV_BASE_ADDR) 0x40C00000.

Address offset

0x00

0x04

Name

COMMAND

STATUS

Table 7. AHBUPCONV registers

Reset

0x00000000

Description

AHB up/down converter command register

AHB up/down converter status register

BLUE_CTRL peripheral base address (BLUE_CTRL_BASE_ADDR) 0x48000000.

Note:

Address offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x18

0x1C

0x20

0x24

0x28

0x2C

Name

INTERRUPT

TIMEOUT

TIMER_CAPTURE

RADIO_CONFIG

CURRENT_TIME

STATUS

AES_KEY0

AES_KEY1

AES_KEY2

AES_KEY3

CLEAR_TEXT0

CLEAR_TEXT1

CLEAR_TEXT2

CLEAR_TEXT3

AES_CYPHERTEXT0

AES_CYPHERTEXT1

AES_CYPHERTEXT2

AES_CYPHERTEXT3

HOST_WKUP_TIMER

Table 8. BLUE_CTRL registers

RWC

Reset

0x00000000

Description

Interrupt status and clear register

Timeout programming register

Capture time value register

Radio configuration register

24-bit timer current value register

Status register

Bits[127:96] of AES key

Bits[95:64] of AES key

Bits[63:32] of AES key

Bits[31:0] of AES key

Bits[127:96] of AES clear text

Bits[95:64] of AES clear text

Bits[63:32] of AES clear text

Bits[31:0] of AES clear text

Bits[127:96] of AES cypher text

Bits[95:64] of AES cypher text

Bits[63:32] of AES cypher text

Bits[31:0] of AES cypher text

Second wake-up timer (CPU wake-up timer) register

All RESERVED fields inside registers must always be written with their default value.

3.5

Clocks and reset management

The BlueNRG-1 embeds an RC low-speed frequency oscillator at 32 kHz and an RO high-speed frequency oscillator at 16 MHz.

The low-frequency clock is used in low power mode and can be supplied either by a 32.7 kHz oscillator that uses an external crystal and guarantees up to ±50 ppm frequency tolerance, or by a ring oscillator, which does not require any external components.

DS11481 - Rev 10 page 12/167

BlueNRG-1

Clocks and reset management

Note:

RO16M

The primary high-speed frequency clock is a 16 MHz or 32 MHz crystal oscillator. A fast-starting 16 MHz ring oscillator provides the clock while the crystal oscillator is starting up. Frequency tolerance of high-speed crystal oscillator is ±50 ppm.

The usage of the 16 MHz (for constraints related to the 16 MHz high-speed crystal usage, refer to the BlueNRG-1

DK SW release notes) (or 32 MHz) crystal is strictly necessary for RF communications.

The clock tree for the peripherals is as follows:

Figure 6. Clock tree

CLK_16M_NVM

CLK_16M_I2Cx

CLOCK_EN->NVM

CLOCK_EN->I2Cx

CLK_16M_UART

CLK_16M_RNG

CLOCK_EN->UART

16M_CLK

CLOCK_EN >RNG

CLOCK_EN->ADC

CLK_16M_ADC

CLOCK_EN->SPI

CLK_16M_SPI

CLK_APB_BLUE

CLK_BLUE

XO16/32M

DIV2

SYS_CLK

CLK_APB_GPIO

CLOCK_EN->NVM

CLK_APB_NVM

CLOCK_EN->GPIO

CLK_APB_UART

CLOCK_EN

->SYSCTRL

CLK_APB_SYSCTRL

CLOCK_EN->UART

CLK_MFTx

CLK_APB_SPI

CLOCK_EN->MFTx

CLOCK_EN->SPI

CLK_32K_RTC

CLK_APB_MFTx

CLK_APB_ADC CLOCK_EN->MFTx

CLOCK_EN->RTC

XO32K

CLK_32K_WDG

CLOCK_EN->ADC

CLOCK_EN->I2Cx

CLK_APB_I2Cx

CLOCK_EN->PKA

CLK_AHB_PKA

RC32K

CLOCK_EN->WDG

CLK_APB_WDG

CLOCK_EN->DMA

CLK_APB_RTC

CLOCK_EN->RNG

CLK_AHB_DMA

CLK_AHB_RNG

CLOCK_EN->RTC

•

When 32 MHz XO is used, the Cortex-M0, the DMA and the APB tree (except for BLE radio access) run at 32

MHz. The rest of the clock tree is divided by two and is at 16 MHz.

•

The following clocks can be enabled/disabled by software to implement optimal power consumption:

• DMA

BLE controller

BLE clock generator

RNG

Flash controller

GPIO

System controller

UART

SPI

I2C1 (1)

I2C2

ADC

MFT1

MFT2

DS11481 - Rev 10 page 13/167

Note:

3.5.1

BlueNRG-1

Clocks and reset management

•

RTC

WDG

PKA

1. The I 2 C1 is not available with WLCSP34 package.

By default, all the peripheral APB and AHB clocks are enabled, except for the PKA peripheral. The following clocks are enabled/disabled automatically:

• Processor clock (disabled in sleep mode)

• RAM clock (disabled if processor clock, SPI clock and BLE clock are all disabled)

It is possible to provide an external 32 kHz signal to the BlueNRG-1 device through the SXTAL0 pin by sourcing a periodic waveform from 0 to 1.2 V.

•

Reset management

•

the chip out of shutdown state. The wake-up logic is powered and receives the POR. Each time the wake-up controller decides to exit sleep or standby modes, it will generate a reset for the core logic. The core logic can also be reset by:

Watchdog

Reset request from the processor (system reset)

LOCKUP state of the Cortex-M0

The SWD logic is reset by the POR. It is important to highlight that reset pin actually power down chip, so it is not possible to perform debug access with system under reset.

Figure 7. Reset and wake-up generation

DS11481 - Rev 10

If, for any reason, the users would like to power off the device there are two options:

Force RESETN pin to ground, keeping VBAT level

To put VBAT pins to ground (e.g. via a transistor)

In the second option, care must be taken to ensure that no voltage is applied to any of the other pins since device can be powered and having an anomalous power consumption. ST recommendation is to use RESETN whenever it is possible.

page 14/167

BlueNRG-1

Clocks and reset management

3.5.1.1

3.5.1.2

Power-on-Reset

The Power-on-Reset (POR) signal is the combination of the POR signal and the BOR signal generated by the analog circuitry contained in the BlueNRG-1 device. The combination of these signals is used to generate the input to the Cortex-M0, which is used to reset the debug access port (DAP) of the processor. It is also used to generate the signal, which resets the debug logic of the Cortex-M0. The POR signal also resets the TAP controller of the BlueNRG-1 and a part of the Flash controller (managing the Flash memory boot, which does not need to be impacted by system resets).

The BOR reset is enabled by default. At software level, it can be decided to change the default values after reset.

Power-on sequence

The starting sequence of the BlueNRG-1 supply and reset signal is shown below.

Figure 8. BlueNRG-1 power-on sequence

VBATx

X=1,2,3

30 µs

RESETN

1.82 ms max.

Internal POR

System clock

Note:

CPU activity CPU under reset

CPU is running on

RCO 16 MHz

CPU can switch on

XO 32 MHz by SW

•

The VBATx power must only be raised when RESETN pin is low.

The different VBATx (x=1,2,3) power can be raised separately or together.

Once the VBATx (x=1, 2, 3) reaches the nominal value, the RESETN pin could be driven high after a 30 us.

The internal POR is released once internal LDOs are established and RCO clock is ready.

The system starts on RCO 16 MHz clock system. The software is responsible for configuring the XO 16/32

MHz when necessary.

The minimum negative pulse to reset the system must be at least 30 µs.

DS11481 - Rev 10 page 15/167

BlueNRG-1

Clocks and reset management

The POR circuit is powered by a 1.2 V regulator, which must also be powered up with the correct startup sequence. Before VBAT has reached the nominal value, RESETN line must be kept low. An external RC circuit on RESETN pin adds a delay that can prevent RESETN signal from going high before VBAT has reached the nominal value.

Figure 9. Reset circuit

3.5.1.3

3.5.1.4

3.5.1.5

3.5.1.6

If the above conditions are not satisfied, ST cannot guarantee the correct operation of the device.

Watchdog reset

The BlueNRG-1 contains a watchdog timer, which may be used to recover from software crashes. The watchdog contains a 32-bit down counter, which generates an interrupt, if the interrupt is not serviced, the watchdog generates a reset. The watchdog reset resets the Flash controller, the Cortex-M0 and all its peripherals but it does not reset the debug circuitry of the Cortex-M0.

System reset request

The system reset request is generated by the debug circuitry of the Cortex-M0. The debugger writes to the

SYSRESETREQ bit of the “application interrupt and reset control register” (AIRCR). This system reset request through AIRCR register can also be done by embedded software. The system reset request does not affect the debugger, thus allowing the debugger to remain connected during the reset sequence.

LOCKUP reset

The Cortex-M0 generates an output LOCKUP that indicates that the core is in a deliberate lock-up state resulting from an unrecoverable exception. The LOCKUP signal is used to generate a reset in the BlueNRG-1, which affects the Cortex-M0, the Flash controller and all the peripherals.

The LOCKUP signal does not reset the Cortex-M0 debug circuitry and it is not generated if a debugger is connected.

Reset and wake-up reason decoding

The BlueNRG-1 provides a set of registers to identify the reason behind a reset and wake-up generation. Two registers are used: CKGEN_SOC->REASON_RST and CKGEN_BLE->REASON_RST. The possible reasons are listed below:

DS11481 - Rev 10 page 16/167

BlueNRG-1

Clocks and reset management

3.5.1.7

If the register CKGEN_SOC->REASON_RST = 0, according to the CKGEN_BLE->REASON_RST the possible reasons are: a.

Wake-up from IO9, IO10, IO11, IO12, IO13 b.

Wake-up from internal timer: BLE timer 1 or BLE timer 2 c.

POR or BOR

If the register CKGEN_SOC->REASON_RST is not 0, according to its value the possible reasons are: a.

System reset b.

Watchdog reset c.

Lockup reset

Clock and reset registers

CKGEN_SOC peripheral base address (CKGEN_SOC_BASE_ADDR) 0x40900000.

Address offset

0x08

0x1C

Name

REASON_RST

DIE_ID

Several channels are available for the conversion, the CHSEL selects the channel according to Table 20. ADC channels .

0x20 CLOCK_EN

0x24 DMA_CONFIG

1. It depends on the cut version.

Table 9. CKGEN_SOC registers

RW Reset

0x00000111

0x0003FFFF

0x00000000

Description

Indicates the reset reason from Cortex-M0. Refer to the detailed description below.

Identification information of the device. Refer to the detailed description below.

Enable or gates the APB clock of the peripherals.

Refer to the detailed description below.

DMA config. Refer to the detailed description below.

Table 10. CKGEN_SOC - REASON_RST register description: address offset CKGEN_SOC_BASE_ADDR+0x08

Bit

31:4

Field name

RESERVED

SYSREQ

WDG

LOCKUP

RESERVED

Reset

0x0

Description

RESERVED

Reset caused by Cortex-M0 debug asserting

SYSRESETREQ

Reset caused by assertion of watchdog reset

Reset caused by Cortex-M0 asserting LOCKUP signal

RESERVED

Table 11. CKGEN_SOC - DIE_ID register description: address offset CKGEN_SOC_BASE_ADDR+0x1C

Bit

3:0

7:4

11:8

31:12

Field name

REV

VERSION

PRODUCT

RESERVED

Reset

0x1

0x0

Cut revision

Cut version

Product

RESERVED

Description

Table 12. CKGEN_SOC - CLOCK_EN register description: address offset CKGEN_SOC_BASE_ADDR+0x20

Bit

Field name

GPIO

NVM

Reset

0x1

RW GPIO clock

RW Flash controller clock

Description

DS11481 - Rev 10 page 17/167

BlueNRG-1

Clocks and reset management

Bit

15:14

31:20

6:5

Field name

SYSCTRL

UART

SPI

RESERVED

WDOG

ADC

I2C1

I2C2

MFT1

MFT2

RTC

RESERVED

DMA

RNG

PKA

PKA RAM

RESERVED

Reset

0x1

0x3

0x1

0x0

0x1

0x3

RW Description

RW System controller clock

RW UART clock

RW SPI clock

RW RESERVED

RW Watchdog clock

RW ADC clock

RW I2C1 clock

RW I2C2 clock

RW MFT1 clock

RW MFT2 clock

RW RTC clock

RW RESERVED

RW DMA AHB clock

RW RNG AHB clock

RW PKA AHB clock

RW PKA RAM clock

RW RESERVED

Note:

Table 13. CKGEN_SOC - DMA_CONFIG register description: address offset CKGEN_SOC_BASE_ADDR+0x24

31:8

Bit

Field name

ADC_CH0

ADC_CH1

ADC_CH2

ADC_CH3

ADC_CH4

ADC_CH5

ADC_CH6

ADC_CH7

RESERVED

0x0

Reset

0x0

RW Description

RW Select ADC on DMA channel 0 instead of peripheral

RW Select ADC on DMA channel 1 instead of peripheral

RW Select ADC on DMA channel 2 instead of peripheral

RW Select ADC on DMA channel 3 instead of peripheral

RW Select ADC on DMA channel 4 instead of peripheral

RW Select ADC on DMA channel 5 instead of peripheral

RW Select ADC on DMA channel 6 instead of peripheral

RW Select ADC on DMA channel 7 instead of peripheral.

RW RESERVED

Only one DMA channel for the ADC should be selected at time. Hardware does not prevent selecting more than one DMA channel for ADC.

CKGEN_BLE peripheral base address (CKGEN_BLE_BASE_ADDR) 0x48100000.

Address offset

0x08

0x0C

0x10

Name

REASON_RST

CLK32K_COUNT

CLK32K_PERIOD

Table 14. CKGEN_BLE registers

RW Reset

0x00000005

0x0000000F

0x00000000

Description

Indicates the Reset reason from BLE. Refer to the detailed description below.

Counter of 32 kHz clock. Refer to the detailed description below.

Period of 32 kHz clock. Refer to the detailed description below.

DS11481 - Rev 10 page 18/167

BlueNRG-1

Clocks and reset management

Address offset

0x14

0x18

Name

CLK32K_FREQ

CLK32K_IT

Reset

0x00000000

Description

Measurement of frequency of 32 kHz clock. Refer to the detailed description below.

Interrupt event for 32 kHz clock measurement. Refer to the detailed description below.

Table 15. CKGEN_BLE - REASON_RST register description: address offset CKGEN_BLE_BASE_ADDR+0x08

Bit

31:11

Field name

RESERVED

BOR

POR

WKP_IO9

WKP_IO10

WKP_IO11

WKP_IO12

WKP_IO13

WKP_BLUE

WKP2_BLUE

RESERVED

0x0

Reset

0x1

0x0

0x1

0x0

Description

RESERVED

Reset from BOR

Reset from POR

Wake-up from external IO9

Wake-up from external IO10

Wake-up from external IO11

Wake-up from external IO12

Wake-up from external IO13

Wake-up comes from the timer 1 expiration in the wake-up control block of the BLE radio

Wake-up comes from the timer 2 expiration in the wake-up control block of the BLE radio

RESERVED

Table 16. CKGEN_BLE - CLK32K_COUNT register description: address offset CKGEN_BLE_BASE_ADDR+0x0C

Bit

8:0

31:9

Field name

SLOW_COUNT

RESERVED

Reset

0xF

0x0

RW Description

Program the window length (in slow clock period unit) for slow clock measurement

RW RESERVED

Table 17. CKGEN_BLE - CLK32K_PERIOD register description: address offset CKGEN_BLE_BASE_ADDR+0x10

Bit

18:0

31:19

Field name

SLOW_PERIOD

RESERVED

Reset

0x0

Description

Indicates slow clock period information. The result provided in this field corresponds to the length of SLOW_COUNT periods of the slow clock (32 kHz) measured in 16 MHz half-period unit. The measurement is done automatically each time the device enters in active2 mode using SLOW_COUNT

= 16. A new calculation can be launched by writing zero in CLK32K_PERIOD register. In this case, the time window uses the value programmed in

SLOW_COUNT field.

RESERVED

Table 18. CKGEN_BLE - CLK32K_FREQ register description: address offset CKGEN_BLE_BASE_ADDR+0x14

Bit

26:0

31:27

Field name

SLOW_FREQ

RESERVED

Reset

0x0

Description

Value equal to 2 39 / SLOW_PERIOD

RESERVED

DS11481 - Rev 10 page 19/167

BlueNRG-1

ADC

Note:

Table 19. CKGEN_BLE - CLK32K_IT register description: address offset CKGEN_BLE_BASE_ADDR+0x18

Bit

31:1

Field name

CLK32K_MEAS_IRQ

RESERVED

Reset

0x0

Description

When read, provides the status of the interrupt indicating slow clock measurement is finished:

0: No pending interrupt.

1: Pending interrupt.

When written, clears the interrupt:

0: No effect.

1: Clear the interrupt.

RW RESERVED

All RESERVED fields inside registers must always be written with their default value.

3.6

3.6.1

3.6.2

ADC

•

Introduction

•

The BlueNRG-1 integrates a 10-bit analog-to-digital converter (ADC) for sampling an external signal.

Main features are:

Sampling frequency 1 MHz

One channel in single ended or differential input through the pins ADC1 and ADC2

Temperature and battery voltage sensors

The conversion are either continuous or single step acquisition

An integrated digital filter is used to process a PDM data stream from a MEMS microphone

Functional overview

The figure below shows a top diagram of the ADC.

Figure 10. ADC block diagram

ADC1 pin

PGA

Vbias

ADC2 pin

PGA

VBATSENS

TEMP

InP

InN

ADC_DATA

ADC

ADC_CLK

CLK

MIC_SEL

DOWNSAMPLE and

FILTERS

CONV_DATA

CHSEL PDM_CLK PDM_DATA

CLK to external microphone

(1.6 MHz or 800 kHz)

PDM signal from external microphone

DS11481 - Rev 10 page 20/167

DS11481 - Rev 10

BlueNRG-1

ADC

CHSEL

Table 20. ADC channels

Channel description

All switch open. No input

Single ended through ADC2 pin. InP = Vbias (internal), InN = ADC2 pin

Single ended through ADC1 pin. InP = ADC1 pin, InN = Vbias (internal)

Differential ADC1 pin – ADC2 pin. InP = ADC1 pin, InN = ADC2 pin

Temperature sensor. InN=TEMP, InP = 0.6 V (internal)

Battery voltage sensor. InN = VBATSENS, InP = 0.6 V (internal)

Short. InP = InN = 0.6 V (internal)

•

The conversion can be single (CONT = 0) or continuous (CONT = 1). In continuous mode, the conversion runs with a pre-programmed sampling rate, the user must discard the first samples that are not valid because generated during the establishment of the internal filter. In particular, it must discards a number of samples as follows:

10 samples if the bitfield SKIP is 0 (COMP filter not bypassed)

3 samples if the bitfield SKIP is 1 (COMP filter bypassed)

In single step mode the ADC performs a conversion and then stops.

The output data rate depends on the setting of OSR according to the following table.

Table 21. ADC data rate

OSR

0 (200)

1 (100)

2 (64)

3 (32)

Output data rate [Ksample/s]

15.625

31.25

The setting of the oversampling ratio (OSR) must be done according to the frequency of the input signal (AC), while for DC signals, the best performance is with OSR = 200. In order to achieve the best performance within the selected input voltage range, the attenuation value must be set through the corresponding register PGASEL value, as in the following table.

Vin range [V]

[0, 1.2]

[0, 2.4]

[0, 3.6]

Vbias [V]

0.6

Table 22. ADC parameter settings

Attenuation [dB]

6.02

9.54

REFSEL value

PGASEL value

The impedance of the ADC input pins is programmable through the register PGASEL as shown in the following table:

PGASEL value

Table 23. Impedance of the ADC pin

Attenuation [dB]

6.02

9.54

Input impedance [kΩ]

HiZ

520

585 page 21/167

BlueNRG-1

ADC

Note:

3.6.2.1

Note:

3.6.2.2

Note:

In order to reduce leakage from ADC pins, the PGASEL register must be set to 0 if the ADC is not used, regardless the ADC is enabled or disabled.

ADC microphone mode

The system can work in conjunction with an external MEMS microphone. In this mode the user must configure:

•

• an IO as PDM_CLK (GPIO Serial2 mode) in order to provide the clock signal to an external MEMS microphone (output signal) an IO as PDM_DATA (GPIO Serial2 mode) in order to receive and process the PDM data stream from the external MEMS microphone (input signal). See for more details about how these pins can be used for this mode.

set the MIC_SEL bitfield of the CONF register, in order to provide a clock to the MEMS microphone. The

PDM_CLK signal provides a clock that can be 1.6 MHz (DIG_FILT_CLK = 0) or 0.8 MHz (DIG_FILT_CLK

=1)

• set the MIC_ON bitfield of the CTRL register, in order to make the ADC start the conversion from the MEMS microphone

MIC_ON and ON bitfields must be exclusive and must not be set together.

The output data rate changes with the OSR and according to the clock frequency provided as explained in

Table 24. Output data rate with microphone .

Table 24. Output data rate with microphone

DIG_FILT_CLK

1 (clock = 0.8 MHz)

0 (clock = 1.6 MHz)

OSR

0 (200)

1 (100)

2 (64)

3 (32)

0 (200)

1 (100)

2 (64)

3 (32)

Output data rate

[Ksample/s]

12.5

ADC start conversion

The ADC both analog and digital sub-system are switched on by setting ADCON and SWSTART.

The conversion operation consists of four phases.

The wake-up phase lasts 6 µs, is present at the beginning of a single acquisition, with the goal to let the analog system settle before starting the acquisition.

When CALEN bit and AUTO_OFFSET are set in ADC_CTRL register, a calibration starts. It permits compensating the offset in the analog part. The conversion status is tracked by SR status register. At the beginning of the conversion the BUSY bit is set and masks any attempt to change CONF, up to the end of the conversion. At end of this conversion, the ENDCAL flag is generated and the OFFSET register is written with the converted offset voltage.

The acquisition phase is regulated by a timeout depending on the resolution. In this phase, digital filter chain processes the data coming from ADC.

The elaboration phase is at the end of the timeout, the data obtained at the output of the digital filter is written in the DATA register. The content of the OFFSET register is automatically used to compensate the final result. Furthermore, the ADCEOC flag is generated to warn about the end of conversion. If

ENAB_COMP bit is set, the WDOG flag is generated to warn that the result of the conversion is between a high THRESHOLD_HI and low threshold THRESHOLD_LO.

It is always advisable to set the register fields CALEN and AUTO_OFFSET in order to perform automatic calibration for each measurement.

DS11481 - Rev 10 page 22/167

BlueNRG-1

ADC

3.6.2.3

3.6.2.4

ADC offset

The ADC automatically corrects a potential offset error by taking into account the content of the register OFFSET.

To enable the automatic offset correction the CALEN and the AUTO_OFFSET must be both set. The result of the calibration is stored in the OFFSET register.

The correction of the offset can be also done manually, for example by performing firstly an automatic offset calibration by making an ADC conversion with both AUTO_OFFSET and CALEN bitfields set. In this way, the

OFFSET register is updated with the current offset error. Then, the automatic offset calibration can be disabled by set to 0b the AUTO_OFFSET and the CALEN bitfields. And so, the offset value is applied to all the next ADC conversions.

The calibration value is a 16-bit value in the register OFFSET. It must be placed in the bitfield OFFSET_MSB if the bitfield SKIP is 0 (filter not bypassed). While, if the bitfield SKIP is 1 (filter bypassed), the calibration value must be placed in the bitfield OFFSET_LSB.

ADC conversion

The relationship between differential input voltage and ADC

RAW

code (first 16-bit MSB of DATA_CONV register) depends on a limited set of parameters: the digital reference voltage VREF, the PGA value, and a scaling factor.

Differential mode

This mode enables the ADC differential conversion from the pins ADC1 and ADC2.

VADC12 Volt = VADC1 − VADC2 = 1 + PGASEL *

ADCRAW

FS_16 OSR *VREF

Single-ended mode

This mode enables the ADC conversion from the pin ADC1 or from the pin ADC2.

VADC1 Volt = 1 + PGASEL * Vbias +

ADCRAW

FS_16 OSR * VREF

(1)

(2)

VADC2 Volt = 1 + PGASEL * Vbias −

ADCRAW

FS_16 OSR * VREF

Battery voltage sensor

This mode enables the monitoring of the battery voltage V

BATT

, through an internal resistive bridge.

VBATT Volt = KBATT* Vbias −

ADCRAW

FS_16 OSR * VREF

(3)

(4)

Temperature sensor

This mode enables the monitoring of the temperature by means of an internal sensor, with the following voltage to temperature conversion:

VTEMP °C = KTC* Vbias −

ADCRAW

FS_16 OSR * VREF + OFFSETTC

To ensure an accurate temperature reading, average the value over several readings.

Below the values for the symbols used in the ADC conversion formulas:

• PGASEL is the input attenuation register, values: 0, 1, or 2

• FS_16(OSR) is the full scale factor for ADC

RAW

and it depends on the oversampling ratio (OSR) as shown below:

• If SKIP is 0 (filter not bypassed), then:

– ADC

RAW

is DATA_CONV_MSB

– FS_16(32) = FS_16(64) = 16708

(5)

•

– FS_16(100) = FS_16(200) = 19450

If SKIP is 1 (filter bypassed), then:

– ADC

RAW

is DATA_CONV_LSB

– FS_16(32) = FS_16(64) = 32768

– FS_16(100) = FS_16(200) = 38147

REF

represents the digital core power supply, typical V

REF

value is 2.4 V

V bias

is given by the register REFSEL, with a typical value of 0.6 V

BATT

is 4.36

is 401

DS11481 - Rev 10 page 23/167

3.6.3

BlueNRG-1

ADC

• OFFSET

is 267 °C

ADC registers

ADC peripheral base address (ADC_BASE_ADDR) 0x40800000.

Address offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x20

0x24

0x28

Name

CTRL

CONF

IRQSTAT

IRQMASK

IRQRAW

DATA_CONV

OFFSET

SR_REG

THRESHOLD_HI

THRESHOLD_LO

Table 25. ADC registers

Reset

0x00000000

0x0000000C

0x00000000

0x0000000F

0x00000000

0xFFFFFFFF

0x00000000

Description

ADC control register. Refer to the detailed description below.

ADC configuration register. Refer to the detailed description below.

IRQ masked status register. Refer to the detailed description below.

It sets the mask for ADC interrupt. Refer to the detailed description below.

IRQ status register. Refer to the detailed description below.

Result of the conversion in two complement format.

Offset for correction of converted data

ADC status register. Refer to the detailed description below.

High threshold for window comparator.

Low threshold for window comparator.

Bit

Table 26. ADC - CTRL register description: address offset ADC_BASE_ADDR+0x00

Field name

CALEN

SWSTART

RESET

Reset

0x0

Description

Starts ADC analog subsystem. This bit must be set before starting a conversion.

0: ADC is OFF.

1: ADC is ON.

This bit works for all the mode except the microphone mode.

The automatic calibration routine is enabled if both AUTO_OFFSET and

CALEN bitfields are set. The result of the calibration is placed in the OFFSET register according to the SKIP bitfield value.

0: disable the automatic calibration

1: enable the automatic calibration

This bitfield can be set to 0 only by setting to 1 the bitfield RSTCALEN

Starts the ADC conversion phase when set.

This bit works for all the mode except the microphone mode.

Reset all the ADC APB registers when set (CTRL, CONF,

DATA_CONV,THRESHOLD_HI).

DS11481 - Rev 10 page 24/167

DS11481 - Rev 10

BlueNRG-1

ADC

Bit

3:1

Bit

31:10

Field name

STOP

ENAB_COMP

RSTCALEN

AUTO_OFFSET

MIC_ON

DMA_EN

RESERVED

Reset

0x0

Description

This bit is auto-cleared by the hardware so it is always read 0

Permits the continuous conversion to be stopped.

1: stop the continuous conversion and switch off the ADC.

The bitfields SWSTART, ON, DMA_EN and MIC_ON are auto-cleared if set.

This bit is auto-cleared by the hardware so it is always read at 0.

Enables the window comparator when set to 1. WDOG flag is ADC_SR register is set if the converted value is between

THRESHOLD_HI and THRESHOLD_LO value.

Disable the calibration phase when set to 1. This bit has to be set to disable the calibration each time calibration is enabled. This bit is auto-cleared by the hardware so it is always read at 0.

The automatic calibration routine is enabled if both AUTO_OFFSET and

CALEN bitfields are set. The result of the calibration is placed in the OFFSET register according to the SKIP bitfield value.

0: disable the automatic calibration.

1: enable the automatic calibration.

Starts ADC analog subsystem for microphone mode only.

0: ADC is OFF

1: ADC is ON

Enables the DMA.

0: DMA is disabled.

1: DMA is enabled.

RESERVED

Table 27. ADC - CONF register description: address offset ADC_BASE_ADDR+0x04

Field name

RESERVED

CHSEL

Reset

0x0

0x6

RW RESERVED

Description

Select the input channel:

000b: All switches open.

001b: Single-ended through ADC2 pin. InP = Vbias

(internal), InN = ADC2 pin.

010b: Single-ended through ADC1 pin. InP = ADC1 pin,

InN = Vbias (internal).

011b: Differential ADC1 pin - ADC2 pin, InP = ADC1 pin,

InN = ADC2 pin.

100b: Temperature sensor. InP = 0.6 V (internal), InN =

TEMP.

101b: Battery voltage sensor. InP = 0.6 V (internal), InN =

VBATSENS.

page 25/167

DS11481 - Rev 10

BlueNRG-1

ADC

Bit

5:4

7:6

9:8

17:12

Field name

REFSEL

OSR

PGASEL

RESERVED

CONT

RESERVED

SKIP

RESERVED

DIG_FILT_CLK

0x0

RESERVED

MIC_SEL

0x0

31:23 RESERVED

1. Best value for sampling DC signals.

0x000

0x0

0x00

Reset

0x0

Description

110b: Short InN = InP = 0.6 V (internal).

Set the Vbias for single ended conversion:

00b: 0.0 V (default value not recommended)

10b: 0.6 V (suggested value)

Set the oversampling ratio.

00b: Set the oversampling ratio to 200

Table 36. Programmable data width and endian behavior (when bits PINC = MINC = 1) : Programmable data

01b: Set the oversampling ratio to 100

10b: Set the oversampling ratio to 64

11b: Set the oversampling ratio to 32

Set the input attenuator value:

00b: Input attenuator at 0 dB

01b: Input attenuator at 6.02 dB

10b: Input attenuator at 9.54 dB

RW RESERVED

Enable the continuous conversion mode:

0: Single conversion

1: Continuous conversion

RW RESERVED

It permits the filter COMP to be bypassed to speed up the conversion for signal at low frequency:

0: Filter not bypassed

1: Filter bypassed

According to the value of this bitfield, the behavior of the

ADC changes as follows:

- If SKIP is 0: the first 10 converted samples in ADC mode continuous should be discarded by the user. The converted date is in the bitfield DATA_CONV_MSB. The calibration result is in the bitfield OFFSET_MSB.

- If SKIP is 1: the first 3 converted samples in ADC mode continuous should be discarded by the user. The converted date is in the bitfield DATA_CONV_LSB. The calibration result is in the bitfield OFFSET_LSB.

So, a calibration must be redone if the SKIP bitfield value changes.

RW RESERVED

Frequency clock selection value on PDM_CLK when

MIC_SEL=1:

0: 1.6 MHz

1: 0.8 MHz

RW RESERVED

Provides the clock on GPIO:

0: Do not provided any external clock source

1: Provide clock source from GPIO

RW RESERVED page 26/167

DS11481 - Rev 10

BlueNRG-1

ADC

Bit

31:4

Table 28. ADC - IRQSTAT register description: address offset ADC_BASE_ADDR+0x08

Field name

ENDCAL

RESERVED

EOC

WDOG

RESERVED

Reset

0x0

Description

1: When the calibration is completed. Clear on register read.

R RESERVED

1: When the conversion is completed. Clear on register read.

If ENAB_COMP = 1, this bit indicates the result of the conversion is between high and low threshold:

0: DATA_CONV is NOT between THRESHOLD_HI and

THRESHOLD_LO values.

1: DATA_CONV is between THRESHOLD_HI and

THRESHOLD_LO values.

This field is updated on each new end of conversion event related to the converted data value.

Clear on register read.

R RESERVED

Bit

31:4

Table 29. ADC - IRQMASK register description: address offset ADC_BASE_ADDR+0x0C

Field name

ENDCAL

RESERVED

EOC

WDOG

RESERVED

Reset

0x1

0x0

Description

Interrupt mask for the end of calibration event:

0: Interrupt is enabled.

1: Interrupt is disabled.

RW RESERVED

Interrupt mask for the end of conversion event:

0: Interrupt is enabled.

1: Interrupt is disabled.

Interrupt mask for the within the threshold event:

0: Interrupt is enabled.

1: Interrupt is disabled.

RW RESERVED

Bit

Table 30. ADC - IRQRAW register description: address offset ADC_BASE_ADDR+0x10

Field name

ENDCAL

RESERVED

EOC

WDOG

Reset

0x0

RW Description

1: When the calibration is completed. Clear on register read.

R RESERVED

1: When the conversion is completed. Clear on register read.

If ENAB_COMP = 1, this bit indicates the result of the conversion is between high and low threshold:

0: DATA_CONV is NOT between THRESHOLD_HI and

THRESHOLD_LO values.

1: DATA_CONV is between THRESHOLD_HI and

THRESHOLD_LO values.

This field is updated on each new end of conversion event related to the converted data value.

page 27/167

Note:

BlueNRG-1

ADC

Bit

31:4

Field name

RESERVED

Reset

0x0

Clear on register read.

R RESERVED

Description

Table 31. ADC - DATA_CONV register description: address offset ADC_BASE_ADDR+0x14

Bit

31:16

15:0

Field name

DATA_CONV_MS

DATA_CONV_LSB

Reset

0x0000

Description

Result of the conversion in two complement format. If the filter is not bypassed, the bitfield SKIP is

0, the DATA_CONV_LSB is negligible and the ADC converted data is the

DATA_CONV_MSB.

Result of the conversion in two complement format. If the filter is bypassed, the bitfield SKIP is 1, the

DATA_CONV_MSB is negligible and the

ADC converted data is the value of

DATA_CONV_LSB * 1.08 (corrective factor).

Bit

15:0

Table 32. ADC - OFFSET register description: address offset ADC_BASE_ADDR+0x18

31:16

Field name

OFFSET_MSB

OFFSET_LSB

Reset

0x0000

Description

Offset for correction of converted data. If the bitfield SKIP is 0, the 16-bit offset is in the MSB part of the register.

Offset for correction of converted data. if the bitfield SKIP is 1, the 16-bit offset is in the LSB part of the register.

Bit

31:2

Table 33. ADC - SR_REG register description: address offset ADC_BASE_ADDR+0x20

Field name

RESERVED

BUSY

RESERVED

Reset

0x0

RW RESERVED

RW 1: during conversion

RW RESERVED

Description

Table 34. ADC - THRESHOLD_HI register description: address offset ADC_BASE_ADDR+0x24

Bit

31:0

Field name

THRESHOLD_HI

Reset

0xFFFFFFFF

Description

High threshold for window comparator.

Table 35. ADC - THRESHOLD_LO register description: address offset ADC_BASE_ADDR+0x28

Bit

31:0

Field name

THRESHOLD_LO

Reset

0x00000000

Description

Low threshold for window comparator.

All RESERVED fields inside registers must always be written with their default value.

DS11481 - Rev 10 page 28/167

3.7

3.7.1

3.7.2

3.7.2.1

3.7.2.2

BlueNRG-1

DMA

•

Introduction

•

The BlueNRG-1 device embeds a DMA allowing various combination of data transfer between the memory and the peripherals without CPU intervention.

Main features are:

• Eight independently configurable channels connected to dedicated hardware DMA requests; software trigger is also supported.

• Priorities between requests from channels of the DMA are software programmable (four levels consisting of very high, high, medium, low). When two channels with same software priority need attention, channel with lower hardware index takes the priority.

Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking.

Support for circular buffer management.

Event flags (DMA half transfer, DMA transfer complete), logically ORed together in a single interrupt request for each channel.

Memory-to-memory transfer (RAM only), peripheral-to-memory and memory-to-peripheral, and peripheral-toperipheral transfers.

Programmable number of data to be transferred up to 65536 bytes.

Functional overview

The DMA controller performs direct memory transfer by sharing the system bus with the other masters of the device. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU.

DMA transactions

After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA controller accesses the peripheral, the DMA controller sends an acknowledge to the peripheral. The peripheral releases its request as soon as it gets the acknowledge from the DMA controller. Once the request is deasserted by the peripheral, the DMA controller releases the acknowledge. If there are more requests, the peripheral can initiate the next transaction.

In summary, each DMA transfer consists of three operations:

•

The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register.

The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register.

The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed.

Arbiter

The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences.

The priorities are managed in two stages:

•

Software: each channel priority can be configured in the DMA_CCRx register. There are four levels:

– Very high priority

– High priority

– Medium priority

– Low priority

Hardware: if two requests have the same software priority level, the channel with the lowest number has the priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4.

DS11481 - Rev 10 page 29/167

BlueNRG-1

DMA

3.7.2.3

3.7.2.4

DMA channels

Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register, which contains the amount of data items to be transferred, is decremented after each transaction.

Programmable data sizes

Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the DMA_CCRx register.

Pointer increments

Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the

DMA_CNDTRx register, the DMA channel must be disabled.

If a DMA channel is disabled, the DMA registers are not Reset. The DMA channel registers (DMA_CCRx,

DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase.

In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the

DMA_CPARx/DMA_CMARx registers.

Channel configuration procedure

The following sequence should be followed to configure a DMA channelx (where x is the channel number).

Set the peripheral register address in the DMA_CPARx register. The data are moved from/ to this address to/ from the memory after the peripheral event.

Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event.

Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral event, this value is decremented.

Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register.

Configure data transfer direction, circular mode, peripheral and memory incremented mode, peripheral and memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register.

Activate the channel by setting the ENABLE bit in the DMA_CCRx register.

As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel.

Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is generated if the transfer complete interrupt enable bit (TCIE) is set.

Circular mode

Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served.

Memory-to-memory mode

The DMA channels can also work without being triggered by a request from a peripheral. This mode is called memory-to-memory mode. If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory-to-memory mode may not be used at the same time as circular mode.

Programmable data width, data alignment and endianness

When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in

width and endian behavior (when bits PINC = MINC = 1).

DS11481 - Rev 10 page 30/167

DS11481 - Rev 10

BlueNRG-1

DMA

Source port width

Table 36. Programmable data width and endian behavior (when bits PINC = MINC = 1)

Destination port width

Number of data items to transfer

(NDT)

Source content: address/data

Transfer operations

Destination content: address/data

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / B1B0

@0x1 / B3B2

@0x2 / B5B4

@0x3 / B7B6

@0x0 / B1B0

@0x1 / B3B2

@0x2 / B5B4

@0x3 / B7B6

@0x0 / B1B0

@0x1 / B3B2

@0x2 / B5B4

1: READ B0[7:0] @0x0 then WRITE

B0[7:0] @0x0

2: READ B1[7:0] @0x1 then WRITE

B0[7:0] @0x1

3: READ B2[7:0] @0x2 then WRITE

B0[7:0] @0x2

4: READ B3[7:0] @0x3 then WRITE

B0[7:0] @0x3

1: READ B0[7:0] @0x0 then WRITE

00B0[15:0] @0x0

2: READ B1[7:0] @0x1 then WRITE

00B0[15:0] @0x2

3: READ B2[7:0] @0x2 then WRITE

00B0[15:0] @0x4

4: READ B3[7:0] @0x3 then WRITE

00B0[15:0] @0x6

1: READ B0[7:0] @0x0 then WRITE

000000B0[31:0] @0x0

2: READ B1[7:0] @0x1 then WRITE

000000B0[31:0] @0x4

3: READ B2[7:0] @0x2 then WRITE

000000B0[31:0] @0x8

4: READ B3[7:0] @0x3 then WRITE

000000B0[31:0] @0xC

1: READ B1B0[15:0] @0x0 then WRITE

B0[7:0] @0x0

2: READ B3B2[15:0] @0x2 then WRITE

B0[7:0] @0x1

3: READ B5B4[15:0] @0x4 then WRITE

B0[7:0] @0x2

4: READ B7B6[15:0] @0x6 then WRITE

B0[7:0] @0x3

1: READ B1B0[15:0] @0x0 then WRITE

B1B0[15:0] @0x0

2: READ B3B2[15:0] @0x2 then WRITE

B3B2[15:0] @0x2

3: READ B5B4[15:0] @0x4 then WRITE

B5B4[15:0] @0x4

4: READ B7B6[15:0] @0x6 then WRITE

B7B6[15:0] @0x6

1: READ B1B0[15:0] @0x0 then WRITE

0000B1B0[31:0] @0x0

2: READ B3B2[15:0] @0x2 then WRITE

0000B3B2[31:0] @0x4

3: READ B5B4[15:0] @0x4 then WRITE

0000B5B4[31:0] @0x8

@0x0 / B0

@0x1 / B1

@0x2 / B2

@0x3 / B3

@0x0 / 00B0

@0x2 / 00B1

@0x4 / 00B2

@0x6 / 00B3

@0x0 / 000000B0

@0x4 / 000000B1

@0x8 / 000000B2

@0xC / 000000B3

@0x0 / B0

@0x1 / B2

@0x2 / B4

@0x3 / B6

@0x0 / B1B0

@0x2 / B3B2

@0x4 / B5B4

@0x6 / B7B6

@0x0 / 0000B1B0

@0x4 / 0000B3B2

@0x8 / 0000B5B4 page 31/167

BlueNRG-1

DMA

3.7.2.5

Source port width

Destination port width

Number of data items to transfer

(NDT)

Source content: address/data

4 @0x3 / B7B6

@0x0 /

B3B2B1B0

@0x4 /

B7B6B5B4

@0x8 /

BBBAB9B8

@0xC /

BFBEBDBC

@0x0 /

B3B2B1B0

@0x4 /

B7B6B5B4

@0x8 /

BBBAB9B8

@0xC /

BFBEBDBC

@0x0 /

B3B2B1B0

@0x4 /

B7B6B5B4

@0x8 /

BBBAB9B8

@0xC /

BFBEBDBC

Transfer operations

4: READ B7B6[15:0] @0x6 then WRITE

0000B7B6[31:0] @0xC

1: READ B3B2B1B0[31:0] @0x0 then

WRITE B0[7:0] @0x0

2: READ B7B6B5B4[31:0] @0x4 then

WRITE B0[7:0] @0x1

3: READ BBBAB9B8[31:0] @0x8 then

WRITE B0[7:0] @0x2

4: READ BFBEBDBC[31:0] @0xC then

WRITE B0[7:0] @0x3

1: READ B3B2B1B0[31:0] @0x0 then

WRITE B1B0[15:0] @0x0

2: READ B7B6B5B4[31:0] @0x4 then

WRITE B3B2[15:0] @0x2

3: READ BBBAB9B8[31:0] @0x8 then

WRITE B5B4[15:0] @0x4

4: READ BFBEBDBC[31:0] @0xC then

WRITE B7B6[15:0] @0x6

1: READ B3B2B1B0[31:0] @0x0 then

WRITE 0000B1B0[31:0] @0x0

2: READ B7B6B5B4[31:0] @0x4 then

WRITE 0000B3B2[31:0] @0x4

3: READ BBBAB9B8[31:0] @0x8 then

WRITE 0000B5B4[31:0] @0x8

4: READ BFBEBDBC[31:0] @0xC then

WRITE 0000B7B6[31:0] @0xC

Destination content: address/data

@0xC /

0000B7B6

@0x0 / B0

@0x1 / B4

@0x2 / B8

@0x3 / BC

@0x0 / B1B0

@0x2 / B5B4

@0x4 / B9B8

@0x6 / BDBC

@0x0 /

B3B2B1B0

@0x4 /

B7B6B5B4

@0x8 /

BBBAB9B8

@0xC /

BFBEBDBC

•

The DMA is addressed through AHB and can be accessed only with 32-bit access. Any 8-bit or 16-bit access generates a hard fault.

When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32

HWDATA bits as shown in the two examples below:

To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord

To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = byte

Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it transforms any AHB byte or halfword operation into a 32-bit APB operation in the following manner:

• an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) is converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0

• an AHB half-word write operation of the data “0xB1B0” to 0x0 (or to 0x2) is converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0

Error management

A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the ISR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set.

DS11481 - Rev 10 page 32/167

BlueNRG-1

DMA

3.7.2.6

3.7.2.7

Interrupts

An interrupt can be produced on a half-transfer, transfer complete or transfer error for each DMA channel.

Separate interrupt enable bits are available for flexibility.

Interrupt event

Half-transfer

Transfer complete

Transfer error

Table 37. DMA interrupt requests

Event flag

HTIF

TCIF

TEIF

Enable control bit

HTIE

TCIE

TEIE

DMA request mapping

The eight requests from the peripherals (SPI, I2Cx[1,2] and UART) are multiplexed before entering DMA with the ADC request. For each channel, the choice between the peripheral and the ADC is done through the

DMA_CONFIG register.

Figure 11. DMA request mapping in the BlueNRG-1

3.7.3

DMA registers

DMA peripheral base address (DMA_BASE_ADDR) 0xA0000000.

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BlueNRG-1

DMA

Address offset Name RW

0x00 ISR R

0x04 IFCR W

Reset

0x00000000

Table 38. DMA registers

Description

DMA interrupt status register. Refer to the detailed description below.

DMA interrupt flag clear register. Refer to the detailed description below.

Bit

Table 39. DMA - ISR register description: address offset DMA_BASE_ADDR+0x00

Field name

GIF0

TCIF0

HTIF0

TEIF0

GIF1

TCIF1

HTIF1

TEIF1

GIF2

Reset

0x0

Description

Channel 0 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 0.

1: A TE, HT or TC event occurred on channel 0.

Channel 0 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 0.

1: A transfer complete (TC) occurred on channel 0.

Channel 0 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 0.

1: A half transfer (HT) event occurred on channel 0.

Channel 0 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 0.

1: A transfer error (TE) occurred on channel 0.

Channel 1 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 1.

1: A TE, HT or TC event occurred on channel 1.

Channel 1 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 1.

1: A transfer complete (TC) occurred on channel 1.

Channel 1 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 1.

1: A half transfer (HT) event occurred on channel 1.

Channel 1 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 1.

1: A transfer error (TE) occurred on channel 1.

Channel 2 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

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DS11481 - Rev 10

Bit Field name

9 TCIF2

10 HTIF2

11 TEIF2

12 GIF3

13 TCIF3

14 HTIF3

15 TEIF3

16 GIF4

17 TCIF4

18 HTIF4

Reset

0x0

BlueNRG-1

DMA

Description

0: No TE, HT or TC event on channel 2.

1: A TE, HT or TC event occurred on channel 2.

Channel 2 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 2.

1: A transfer complete (TC) occurred on channel 2.

Channel 2 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 2.

1: A half transfer (HT) event occurred on channel 2.

Channel 2 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 2.

1: A transfer error (TE) occurred on channel 2.

Channel 3 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 3.

1: A TE, HT or TC event occurred on channel 3.

Channel 3 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 3.

1: A transfer complete (TC) occurred on channel 3.

Channel 3 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 3.

1: A half transfer (HT) event occurred on channel 3.

Channel 3 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 3.

1: A transfer error (TE) occurred on channel 3.

Channel 4 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 4.

1: A TE, HT or TC event occurred on channel 4.

Channel 4 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 4.

1: A transfer complete (TC) occurred on channel 4.

Channel 4 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 4.

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DS11481 - Rev 10

Bit Field name

19 TEIF4

20 GIF5

21 TCIF5

22 HTIF5

23 TEIF5

24 GIF6

25 TCIF6

26 HTIF6

27 TEIF6

28 GIF7

Reset

0x0

BlueNRG-1

DMA

Description

1: A half transfer (HT) event occurred on channel 4.

Channel 4 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 4.

1: A transfer error (TE) occurred on channel 4.

Channel 5 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 5.

1: A TE, HT or TC event occurred on channel 5.

Channel 5 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 5.

1: A transfer complete (TC) occurred on channel 5.

Channel 5 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 5.

1: A half transfer (HT) event occurred on channel 5.

Channel 5 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 5.

1: A transfer error (TE) occurred on channel 5.

Channel 6 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 6.

1: A TE, HT or TC event occurred on channel 6.

Channel 6 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 6.

1: A transfer complete (TC) occurred on channel 6.

Channel 6 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 6.

1: A half transfer (HT) event occurred on channel 6.

Channel 6 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 6.

1: A transfer error (TE) occurred on channel 6.

Channel 7 global interrupt flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 7.

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BlueNRG-1

DMA

Bit

Field name

TCIF7

HTIF7

TEIF7

Reset

0x0

Description

1: A TE, HT or TC event occurred on channel 7.

Channel 7 transfer complete flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 7.

1: A transfer complete (TC) occurred on channel 7.

Channel 7 half transfer flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 7.

1: A half transfer (HT) event occurred on channel 7.

Channel 7 transfer error flag. This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 7.

1: A transfer error (TE) occurred on channel 7.

Table 40. DMA - IFCR register description: address offset DMA_BASE_ADDR+0x04

Field name

CGIF0

CTCIF0

CHTIF0

CTEIF0

CGIF1

CTCIF1

CHTIF1

CTEIF1

CGIF2

Reset

0x0

Description

Channel 0 global interrupt flag. This bit is set by software.

0: No effect.

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 0 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 0 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

Channel 0 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

Channel 1 global interrupt flag. This bit is set by software.

0: No effect.

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 1 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 1 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

Channel 1 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

Channel 2 global interrupt flag. This bit is set by software.

0: No effect.

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DS11481 - Rev 10

Bit Field name

9 CTCIF2

10 CHTIF2

11 CTEIF2

12 CGIF3

13 CTCIF3

14 CHTIF3

15 CTEIF3

16 CGIF4

17 CTCIF4

18 CHTIF4

19 CTEIF4

20 CGIF5

21 CTCIF5

22 CHTIF5

Reset

0x0

BlueNRG-1

DMA

Description

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 2 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 2 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

Channel 2 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

Channel 3 global interrupt flag. This bit is set by software.

0: No effect.

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 3 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 3 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

Channel 3 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

Channel 4 global interrupt flag. This bit is set by software.

0: No effect.

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 4 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 4 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

Channel 4 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

Channel 5 global interrupt flag. This bit is set by software.

0: No effect.

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 5 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 5 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

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DS11481 - Rev 10

BlueNRG-1

DMA

•

Bit

Field name

CTEIF5

CGIF6

CTCIF6

CHTIF6

CTEIF6

CGIF7

CTCIF7

CHTIF7

CTEIF7

Reset

0x0

Description

Channel 5 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

Channel 6 global interrupt flag. This bit is set by software.

0: No effect.

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 6 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 6 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

Channel 6 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

Channel 7 global interrupt flag. This bit is set by software.

0: No effect.

1: Clears the GIF, TEIF, HTIF and TCIF flags in the ISR register.

Channel 7 transfer complete flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TCIF flag in the ISR register.

Channel 7 half transfer flag. This bit is set by software.

0: No effect.

1: Clears the corresponding HTIF flag in the ISR register.

Channel 7 transfer error flag. This bit is set by software.

0: No effect.

1: Clears the corresponding TEIF flag in the ISR register.

DMA_CH0 peripheral base address (DMA_CH0_BASE_ADDR) 0xA0000008

DMA_CH1 peripheral base address (DMA_CH1_BASE_ADDR) 0xA000001C

DMA_CH2 peripheral base address (DMA_CH2_BASE_ADDR) 0xA0000030

DMA_CH3 peripheral base address (DMA_CH3_BASE_ADDR) 0xA0000044

DMA_CH4 peripheral base address (DMA_CH4_BASE_ADDR) 0xA0000058

DMA_CH5 peripheral base address (DMA_CH5_BASE_ADDR) 0xA000006C

DMA_CH6 peripheral base address (DMA_CH6_BASE_ADDR) 0xA0000080

DMA_CH7 peripheral base address (DMA_CH7_BASE_ADDR) 0xA0000094

Address offset Name RW

0x00 CCR RW

0x04

0x08

CNDTR

CPAR

Table 41. DMA_CHx registers

Reset

0x00000000

Description

DMA channel configuration register. Refer to the detailed description below.

DMA channel number of data register. Refer to the detailed description below.

DMA channel peripheral address register. Refer to the detailed description below.

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BlueNRG-1

DMA

Address offset Name RW

0x0C CMAR RW

Reset

0x00000000

Description

DMA channel memory address register. Refer to the detailed description below.

Bit

9:8

11:10

13:12

Table 42. DMA_CHx - CCR register description: address offset DMA_CHX_BASE_ADDR+0x00

Field name

TCIE

HTIE

TEIE

DIR

CIRC

PINC

MINC

PSIZE

MSIZE

MEM2MEM

Reset

0x0

Description

DMA channel enable.

0: DMA channel disabled.

1: DMA channel enabled.

Transfer complete interrupt enable.

0: TC interrupt disabled.

1: TC interrupt enabled.

Half transfer interrupt enable.

0: HT interrupt disabled.

1: HT interrupt enabled.

Transfer error interrupt enable.

0: TE interrupt disabled.

1: TE interrupt enabled.

Data transfer direction.

0: Read from peripheral.

1: Read from memory.

Circular mode.

0: Circular mode disabled.

1: Circular mode enabled.

Peripheral increment mode.

0: Peripheral increment disabled.

1: Peripheral increment enabled.

Memory increment mode.

0: Memory increment disabled.

1: Memory increment enabled.

Peripheral size.

00b: Size 8 bits.

01b: Size 16 bits.

10b: Size 32 bits.

Memory size.

00b: Size 8 bits.

01b: Size 16 bits.

10b: Size 32 bits.

Channel priority level.

00b: Low priority.

01b: Medium priority.

10b: High priority.

11b: Very high priority.

Memory-to-memory mode.

page 40/167

Note:

3.8

3.8.1

BlueNRG-1

SPI

Bit Field name

31:15 RESERVED

Reset RW

Description

0: Memory-to-memory mode disabled.

0: Memory-to-memory mode enabled.

RESERVED 0x0

Bit

Table 43. DMA_CHx - CNDTR register description: address offset DMA_CHX_BASE_ADDR+0x04

15:0

31:16

Field name

NDT

RESERVED

Reset

0x0

RW Description

Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer.

Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not.

RW RESERVED

Bit

31:0

Table 44. DMA_CHx - CPAR register description: address offset DMA_CHX_BASE_ADDR+0x08

Field name

Reset

0x0

Description

Base address of the peripheral data register from/to which the data are read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored.

Access is automatically aligned to a halfword address. When

PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.

Bit

31:0

Table 45. DMA_CHx - CMAR register description: address offset DMA_CHX_BASE_ADDR+0x0C

Field name

Reset

0x0

Description

Base address of the memory area from/to which the data are read/ written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10

(32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.

All RESERVED fields inside registers must always be written with their default values.

SPI

•

Introduction

The BlueNRG-1 integrates a serial peripheral interface compatible with the Motorola and National Semiconductor

Microwire standards.

Main features are:

Maximal supported baud rate is 1 MHz in slave mode and 8 MHz in master mode

Parallel-to-serial conversion on data written to an internal 32-bit wide, 16-location deep transmitter FIFO

Serial-to-parallel conversion on received data, buffering in a 32-bit wide 16-location deep receive FIFO

Programmable data frame size from 4-bit to 32-bit

Programmable clock bit rate and prescaler

Programmable clock phase and polarity in SPI mode

Support for direct memory access (DMA)

DS11481 - Rev 10 page 41/167

BlueNRG-1

SPI

3.8.2

3.8.2.1

3.8.2.2

Note:

Functional overview

The SPI performs serial-to-parallel conversion on data received from a peripheral device on the SPI_IN pin, and parallel-to-serial conversion on data written by CPU for transmission on the SPI_OUT pin.

The role of the SPI pins are defined by the SPI master or SPI slave role.

SPI role

Master

Slave

Table 46. SPI pin assignments

SPI_IN pin

MISO

MOSI

SPI_OUT pin

MOSI

MISO

The transmit and receive paths are buffered with internal FIFO memories allowing up to 16 x 32-bit values to be stored independently in both transmit and receive modes. FIFOs may be burst-loaded or emptied by the system processor or by the DMA, from one to eight words per transfer. Each 32-bit word from the system fills one entry in

FIFO.

The SPI includes a programmable bitrate clock divider and prescaler to generate the serial output clock signal from the SPI_CLK pin.

SPI clock phase and clock polarity

The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.

The SPO bit selects the clock polarity (low or high) of the clock signal. SPH in conjunction with the SPO bit allow four possible timing variations listed in the following table.

Table 47. SPI clock phase and clock polarity

SPH SPO

0b 0b

Timing description

The clock signal is stopped to low inactive level between transfers. The first rising edge occurs in the middle of the first data bit (with delay). The SPI transmits data one-half cycle ahead of the rising edge of clock signal and receives data on the rising edge of clock signal. In case of multi byte transmission, the CS line must be pulsed

HIGH between each data word transfer.

The clock signal is stopped to high inactive level between transfers. The first falling edge occurs in the middle of the first data bit (with delay). The SPI transmits data one-half cycle ahead of the falling edge of clock signal and receives data on the falling edge of clock signal. In case of multi byte transmission, the CS line must be pulsed

HIGH between each data word transfer.

The clock signal is stopped to low inactive level between transfers. The first rising edge occurs at the start of the first data bit (no delay). The SPI transmits data on the rising edge of clock signal and receives data on the failing edge of clock signal.

The clock signal is stopped to high inactive level between transfers. The first falling edge occurs at the start of the first data bit (no delay). The SPI transmits data on the falling edge of clock signal and receives data on the rising edge of clock signal.

Procedure for enabling SPI

The SPI initialization procedure is the following (assuming clocks already enabled):

Clear the SSE bit in the CR1 register. This step is not required after a hardware or software reset of the

BlueNRG-1.

Empty the receive FIFO. This step is not required after a hardware or software reset of the device

BlueNRG-1.

Program IO_MODE to route SPI port signals on those GPIOs. See section GPIO operating modes.

Program the SPI clock prescaler register (CPSR), then program the configuration registers CR0 and CR1.

The transmit FIFO can optionally be filled before enabling the SPI.

Set the SSE bit to enable SPI operation.

The transmit FIFO and the receive FIFO are not cleared when the SSE bit is cleared.

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BlueNRG-1

SPI

3.8.2.3

3.8.2.4

3.8.2.5

3.8.2.6

3.8.2.7

SPI bit rate generation

The SPI bit rate is derived by dividing down the peripheral clock (CLK) by an even prescaler value CPSDVSR from 2 to 254, the clock is further divided by a value from 1 to 256, which is 1+SCR. The SPI frequency clock duty cycle is always 0.5.

SPI data endianness

All transfers can be sent and received with configurable endianness according the setting of the (T/R)ENDN bit in the CR1 registers

The cases "00b" and "11b" of TENDN and RENDN are implemented for data frame size from 4- to 32-bit. The cases "01b" and "10b" of TENDN and RENDN are implemented only for the following data frame sizes: 16-bit,

24-bit and 32-bit. Transmit data endianness: TENDN in CR1:

TENDN

00b

01b

10b

11b

Table 48. SPI_OUT endianness

Endianness

The element is transmitted MSByte-first and MSbit-first

The element is transmitted LSByte-first and MSbit-first

The element is transmitted MSByte-first and LSbit-first

The element is transmitted LSByte-first and LSbit-first

RENDN

00b

01b

10b

11b

Table 49. SPI_IN endianness

Endianness

The element is received MSByte-first and MSbit-first

The element is received LSByte-first and MSbit-first

The element is received MSByte-first and LSbit-first

The element is received LSByte-first and LSbit-first

•

SPI interrupts

There are six individual maskable interrupt sources generated by the SPI (single interrupt signal that drives the

NVIC):

Receive interrupt

Transmit interrupt

Timeout interrupt

Receive overrun interrupt

Transmit underrun interrupt

Transmit empty interrupt

The user can enable or disable the individual interrupt sources by changing the mask bits in the IMSC register.

Setting the appropriate mask bit to 1b enables the interrupt. The status of the individual interrupt sources can be read from the RIS register (raw interrupt status) or from the MIS register (masked interrupt status).

Receive interrupt

The receive interrupt is asserted when the number of data in receive FIFO reaches the programmed trigger watermark level. The receive interrupt is cleared by reading data from the receive FIFO until there are less data than the programmed watermark level.

Transmit interrupt

The transmit interrupt is asserted when the number of data in the transmit FIFO is less than or equal to the programmed watermark level. It is cleared by performing writes to the transmit FIFO until it holds more elements than the programmed watermark level. The transmitter interrupt is not qualified with the SPI enable bit, which allows operation in one of two ways:

• Data can be written to the transmit FIFO prior to enabling the SPI and the interrupts.

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SPI

3.8.2.8

3.8.2.9

3.8.2.10

3.8.2.11

3.8.2.12

Note:

• Or the SPI and the interrupts can be enabled so that data can be written to the transmit FIFO by an interrupt service routine.

Timeout interrupt

The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period of the serial clock. This mechanism ensures that the user is aware that data is still present in the receive FIFO and requires servicing.

The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data, or if new data is received, or when a 1b is written to the corresponding bit of the ICR register.

Receive overrun interrupt

The receive overrun interrupt is asserted when the receive FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the receive shift register, but not in the FIFO. The interrupt is cleared when a 1b is written to the corresponding bit of the ICR register.

Transmit underrun interrupt

The transmit underrun interrupt is asserted when the transmit FIFO is already empty and an additional frame is transmitted, causing an underrun of the FIFO. Data is over-read in the transmit shift register. This interrupt is cleared when a 1b is written to the corresponding bit of the ICR register.

Transmit empty interrupt

The transmit interrupt is asserted when the transmit FIFO is empty. It is cleared by performing writes to the transmit FIFO.

SPI master communication mode for Motorola standard

The SPIM register field selects the SPI transmission mode, these modes are applicable only for SPI master mode:

• Full duplex mode (SPIM = 00b): the master transmits the data available in the TXFIFO and receives the data from the slave.

• Transmit mode (SPIM = 01b): when the data is available in TX FIFO, the SPI_OUT line is run, and no data is written in RX FIFO

• Receive mode (SPIM = 10b): the sequence of receive mode is:

The software sets the mode to receive (SPIM = 10) and writes the dummy character value to the CHN register.

The software writes the value “number of frames to receive from the slave” in the RXFRM register.

When the receive mode is selected we have two cases:

If the TXFIFO is empty, the master receives data from the slave, transmitting the character from the CHN register in each frame received. The RXFRM register is decremented by one at each transmission/reception. The interface runs until the RXFRM value is dummy AND the written number of frames in RXFRM is received.

If the TXFIFO is not empty, the master first transmits the data available in the TXFIFO and receives the data from the slave (like the full duplex mode). The RXFRM register is not decremented. When all the data available in TXFIFO are transmitted, the TXFIFO becomes empty (case a), then the dummy character from the CHN register are transmitted for each frame received. The RXFRM register is decremented for each transaction. When the value in this register is zero and the written number of frames in RXFRM is received, the interface does not run anymore. The user has to write the RXFRM

(with value greater than zero) by software to reactivate the interface.

In all cases, the RXFRM is decremented by one only if the TXFIFO is empty. The RFRM is decremented before the data is sent.

If the software fills the TXFIFO while the SPI is transmitting the dummy character, then the words of TXFIFO should be ignored and we should not send them in this mode, only the dummy -character are transmitted.

• Combined mode (SPIM = 11b): the sequence of combined mode is:

The software sets the mode to combined mode: (SPIM=11).

The software writes to the WDTXF register the "number of frames to be received by the slave (a value greater than zero) from TXFIFO master".

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SPI

3.8.2.13

If the number of words written in the WDTXF register are sent (WDTXF is equal to zero) but the RXFRM register is not equal to zero, the master transmits the dummy character (defined in CHM register) and receives the slave data, decrementing the RXFRM register by one. Once the RXFRM register is equal to zero and all the data written in RXFRM are sent, the interface is stopped.

When the RXFRM register is zero and WDTXF is not equal to zero and the TXFIFO of the master and of slave are not empty, the master transmits the data from TXFIFO and receives the data from the slave. Before the data is sent from TXFIFO, the WDTXF is decremented by one. When the WDTXF register is zero and all the numbers written in this register are sent, the interface is stopped.

The interface is stopped when:

• WDTXF and RXFRM registers are equal to zero.

• WDTXF register is not equal to zero and TXFIFO is empty.

• RXFRM register is not equal to zero, the WDTXF register is zero and TXFIFO is not empty.

For each data transmission (TXFIFO data or CHN register data), the data slave is received.

WDTXF is decremented by one only at each data transmission from TXFIFO. The decrementing is done before the words are sent out.

RXFRM is decremented by one only at each dummy character transmission from the CHN register. The decrementing is done before the words are sent out.

When we start decrementing one of the registers (RXFRM or WDTXF), we must decrement until we reach zero and we send the last words before starting the decrement of other registers (RXFRM or WDTXF).

Switching between these different modes when SPI is enabled is possible. If the transmission mode is deselected for another mode during a frame transmission, the new mode becomes active at the start of the next word.

SPI master communication mode for National Semiconductor Microwire standard

The FRF register field selects the SPI mode interface: the default value 0 indicates the Motorola standard interface, while FRF = 2 selects the Microwire standard interface for the 3-wire SPI mode.

The hardware connection considers the SPI_IN and SPI_OUT pins connected together as shown in the figure below. The two pins are handled internally to send and receive data.

Figure 12. MicroWire master and slave communication

DS11481 - Rev 10

The CSS register field specifies the length of the data to send and the DSS register field specifies the length of the data to receive.

In reception mode, the quantity of data to read is specified in the DSS register field. The set of the SSE register field, enables SPI for the communication. The user should wait for data reception to end before attempting any reads. The SSE register field must be reset at the end of the communication.

In transmission mode, the send data are written inside the TX FIFO and the quantity of data to send is specified in the CSS register field. The SSE register field setting enables SPI for the communication. When the busy flag is

RESET, SPI communication is terminated. The SSE register field must be reset at the end of the communication.

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3.8.3

BlueNRG-1

SPI

SPI registers

SPI peripheral base address (SPI_BASE_ADDR) 0x40400000.

Table 50. SPI registers

Address offset Name RW

0x00 CR0 RW

Reset Description

0x1C000000 Control register 0. Refer to the detailed description below

0x04

0x08

CR1

0x00000000 Control register 1. Refer to the detailed description below

0x00000000 Data register. Refer to the detailed description below.

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

CPSR RW 0x00000000 Clock prescale register. Refer to the detailed description below.

IMSC

RIS

MIS

0x00000003 Status register. Refer to the detailed description below

0x00000000 Interrupt mask set or clear register. Refer to the detailed description below

R 0x00000000 Raw interrupt status register. Refer to the detailed description below.

R 0x00000000 Masked interrupt status register. Refer to the detailed description below.

0x28

0x2C

0x30

0x80

0x8C

ICR W 0x00000000 Interrupt clear register. Refer to the detailed description below

DMACR RW 0x00000000 SPI DMA control register. Refer to the detailed description below

RXFRM RW 0x00000000

SPI receive frame register. Indicates the number of frames to receive from the slave.

CHN RW 0x00000000 Dummy character register

WDTXF RW 0x00000000

SPI transmit FIFO receive frame number. Indicates the number of frames to receive from the transmit FIFO

ITCR

TDR

RW 0x00000000 Integration test control register. Refer to the detailed description below

RW 0x00000000 Test data register

Bit Field name

4:0

5 RESERVED

15:8

DSS

SPO

SPH

SCR

Table 51. SPI - CR0 register description: address offset SPI_BASE_ADDR+0x00

Reset

0x0

RW Description

Data size select. (DSS+1) defines the number of bits:

0x00: Reserved.

0x01: Reserved.

0x02: Reserved.

0x03: 4-bit data.

0x04: 5-bit data.

...

0x1F: 32-bit data.

RW RESERVED

Clock polarity (Motorola SPI format only):

0: Steady-state of clock polarity is low.

1: Steady-state of clock polarity is high

Clock phase (Motorola SPI format only):

0: Steady-state of clock phase is low.

1: Steady-state of clock phase is high.

Serial clock rate.

The SRC value is used to generate the transmit and receive bit rate of the

SPI. The bit rate is: f_SPICLK / (CPSDVR * (1 + SCR)), where CPSDVR is an even value from 2 to 254 and SCR is a value from 0 to 255.

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SPI

Bit Field name

20:16 CSS

21:22 FRF

24:23 SPIM

25 RESERVED

26 CS1

31:27 RESERVED

Reset

0X00

0x00

0x0

0x1

0x3

RW Description

Command size select (CSS+1) defines the number of bits for the command in MicroWire mode only:

0x00: Reserved

0x01: Reserved

0x02: Reserved

0x03: 4-bit data

0x04: 5-bit data

...

0x1F: 32-bit data

Frame format:

0: Motorola SPI frame format

2: National MicroWire frame format

SPI master transmission mode (in Motorola SPI master mode only):

00b: Full duplex mode.

01b: Transmit mode.

10b: Receive mode.

11b: Combined mode.

RW RESERVED

Chip selection for slave one

0: the slave 1 is selected.

1: the slave 1 is not selected.

RW RESERVED

5:4

SSE

SOD

Table 52. SPI - CR1 register description: address offset SPI_BASE_ADDR+0x04

Bit Field name

0 RESERVED

RENDN

Reset

0x0

RW RESERVED

Description

SPI enable.

0: SPI disable.

1: SPI enable.

Master or slave mode select.

0: Master mode.

1: Slave mode.

Slave mode output disable (slave mode only).

0: SPI can drive the MISO signal in slave mode.

1: SPI must not drive the MISO signal in slave mode.

In multiple slave system, it is possible for a SPI master to broadcast a message to all slaves in the system while ensuring only one slave drives data onto the serial output line MISO.

Receive endian format.

00b: The element is received MSByte-first and MSbit-first.

01b: The element is received LSByte-first and MSbit-first.

10b: The element is received MSByte-first and LSbit-first.

11b: The element is received LSByte-first and LSbit-first.

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BlueNRG-1

SPI

Bit Field name

6 MWAIT

9:7 RXIFLSEL

12:10 TXIFLSEL

13 RESERVED

17:14 MSPIWAIT

19:18 TENDN

20 RESERVED

21 DATAINDEL

31:22 RESERVED

Reset

0x0

Description

The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits.

MicroWire wait state bit enable:

0: No wait state

1: One wait state

Receive interrupt FIFO level select. This bit field selects the trigger points to receive FIFO interrupt:

000b: RX FIFO contains 1 element or more.

001b: RX FIFO contains 4 elements or more.

010b: RX FIFO contains 8 elements or more.

Others: Reserved.

Transmit interrupt FIFO level select. This bit field selects the trigger points to transmit FIFO interrupt:

000b: TX FIFO contains 1 element or more.

001b: TX FIFO contains 4 elements or more.

010b: TX FIFO contains 8 elements or more.

Others: Reserved.

RW RESERVED

Motorola SPI wait mode. This value is used to insert a wait state between frames.

Transmit endian format.

00b: The element is transmitted MSByte-first and MSbit-first.

01b: The element is transmitted LSByte-first and MSbit-first.

10b: The element is transmitted MSByte-first and LSbit-first.

11b: The element is transmitted LSByte-first and LSbit-first.

The cases 00b and 11b are set for data frame size from 4 to 32 bits. The cases 01b and 10b are set only for data frame size 16, 24 and 32 bits.

RW RESERVED

Data input delay.

0: No delay is inserted in data input.

1: A delay of 2-clock cycles is inserted in the data input path.

RW RESERVED

Bit

Field name

31:0 DATA

Table 53. SPI - DR register description: address offset SPI_BASE_ADDR+0x08

Reset

0x0

RW Description

Transmit/receive data:

Read: RX FIFO is read.

Write: TX FIFO is written.

Data must be right-justified when a data size of less than 32-bit is programmed.

Unused bits are ignored by the transmit logic. The receive logic automatically right-justifies data.

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BlueNRG-1

SPI

TFE

TNF

RNE

RFF

BSY

Table 54. SPI - SR register description: address offset SPI_BASE_ADDR+0x0C

Bit Field name

31:5 RESERVED

Reset

0x1

0x0

RW Description

Transmit FIFO empty:

0: TX FIFO is not empty.

1: TX FIFO is empty.

Transmit FIFO not full:

0: TX FIFO is full.

1: TX FIFO is not full.

Receive FIFO not empty:

0: RX FIFO is empty.

1: RX FIFO is not empty.

Receive FIFO full:

0: RX FIFO is not full.

1: RX FIFO is full.

SPI busy flag:

0: SPI is idle.

1: SPI is currently transmitting and/or receiving a frame or the TX FIFO is not empty.

R RESERVED

Table 55. SPI - CPSR register description: address offset SPI_BASE_ADDR+0x10

Bit Field name

7:0 CPSDVSR

31:8 RESERVED

Reset

0x0

RW Description

Clock prescaler divisor. It must be an even number from 2 to 254. The value is used to generate the transmit and receive bit rate of the SPI. The bit rate is:

FSSPCLK / [CPSDVR x (1+SCR)] where SCR is a value from 0 to 255, programmed through the SSP_CR0 register.

RW RESERVED

Table 56. SPI - IMSC register description. Address offset SPI_BASE_ADDR+0x14.

Bit Field name

RORIM

RTIM

RXIM

TXIM

Reset

0x0

Description

Receive overrun interrupt mask:

0: RX FIFO written to while full condition interrupt is masked (irq disabled).

1: RX FIFO written to while full condition interrupt is not masked (irq enabled).

Receive timeout interrupt mask:

0: RX FIFO not empty or no read prior to the timeout period interrupt is masked (irq disabled).

1: RX FIFO not empty or no read prior to the timeout period interrupt is not masked (irq enabled).

Receive FIFO interrupt mask:

0: Receive interrupt is masked (irq disabled).

1: Receive interrupt is not masked (irq enabled).

Transmit FIFO interrupt mask:

0: Transmit interrupt is masked (irq disabled).

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BlueNRG-1

SPI

Bit Field name

4 TURIM

5 TEIM

31:6 RESERVED

Reset

0x0

Description

1: Transmit interrupt is not masked (irq enabled).

Transmit underrun interrupt mask:

0: Transmit underrun interrupt is masked (irq disabled).

1: Transmit underrun interrupt is not masked (irq enabled).

Transmit FIFO empty interrupt mask:

0: TX FIFO empty interrupt is masked (irq disabled).

1: TX FIFO empty interrupt is not masked (irq enabled).

RW RESERVED

Bit

31:6

Table 57. SPI - RIS register description: address offset SPI_BASE_ADDR+0x18

Field name

RORRIS

RTRIS

RXRIS

TXRIS

TURRIS

TERIS

RESERVED

Reset

0x0

RW Description

R Receive overrun raw interrupt status

R Receive time out raw interrupt status

R Receive raw interrupt status

R Transmit raw interrupt status

R Transmit underrun raw interrupt Status

R Transmit FIFO empty raw interrupt status

R RESERVED

RTMIS

RXMIS

TXMIS

TEMIS

Table 58. SPI - MIS register description: address offset SPI_BASE_ADDR+0x1C

Bit Field name

RORMIS

TURMIS

31:6 RESERVED

Reset

0x0

RW Description

Receive overrun masked interrupt status: gives the interrupt status after masking of the receive overrun interrupt.

Receive time out masked interrupt status: gives the interrupt status after masking of receive timeout interrupt.

Receive masked interrupt status: gives the interrupt status after masking of the receive interrupt.

Transmit masked interrupt status: gives the interrupt status after masking of the transmit interrupt.

Transmit underrun masked interrupt status: gives the interrupt status after masking of the transmit underrun interrupt.

Transmit FIFO empty masked interrupt status: gives the interrupt status after masking of the transmit FIFO empty interrupt.

R RESERVED

2 TURIC

Table 59. SPI - ICR register description: address offset SPI_BASE_ADDR+0x20

Bit Field name

RORIC

RTIC

31:3 RESERVED

Reset

0x0

RW Description

W Receive overrun clear interrupt: writing 1 clears the receive overrun interrupt.

W Receive time out clear interrupt: writing 1 clears the receive timeout interrupt.

Transmit underrun clear interrupt: writing 1 clears the transmit overrun interrupt.

W RESERVED page 50/167

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BlueNRG-1

SPI

Bit

31:3

Table 60. SPI - DMACR register description: address offset SPI_BASE_ADDR+0x24

Field name

RXDMASE

RESERVED

TXDMASE

RESERVED

Reset

0x0

Description

Single receive DMA request.

0: Single transfer DMA in receive disable.

1: Single transfer DMA in receive enable.

RW RESERVED

Single transmit DMA request.

0: Single transfer DMA in transmit disable.

1: Single transfer DMA in transmit enable.

RW RESERVED

Table 61. SPI – RXFRM register description: address offset SPI_BASE_ADDR+0x28

Bit Field name Reset RW

15:0 RXFRM

Description

0x0000 RW SPI receive frame register. Indicates the number of frames to receive from the slave.

31:16 RESERVED 0x0000 RW RESERVED

Bit

31:0

Table 62. SPI – CHN register description: address offset SPI_BASE_ADDR+0x2C

Field name

CHN

Reset

0x00000000

RW Description

RW Dummy character register.

Table 63. SPI – WDTXF register description: address offset SPI_BASE_ADDR + 0x30

Bit Field name Reset RW Description

15:0 WDTXF 0x0000 0x0000

SPI transmit FIFO receive frame number. Indicates the number of frames to receive from the TX FIFO.

31:16 RESERVED 0x0000 0x0000 RESERVED

Table 64. SPI - ITCR register description: address offset SPI_BASE_ADDR+0x80

Bit Field name

0 RESERVED

1 SWAPFIFO

31:2 RESERVED

Reset

0x0

RW Description

RW RESERVED

FIFO control mode:

0: FIFO normal mode. Write in TDR register puts data in TX FIFO and read from TDR register read data from RX FIFO.

1: FIFO swapped mode. Write in TDR register puts data in RX FIFO and read from TDR register read data from TX FIFO.

The registers SWAPFIFO and TDR allow the TX FIFO to be cleared from unwanted data.

RW RESERVED

Table 65. SPI – TDR register description: address offset SPI_BASE_ADDR+0x8C

Bit Field name

31:0 TDR

Reset RW Description

0x00000000 RW Allows reading out data from TX FIFO if the SWAPFIFO bitfield is set.

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UART

Note:

3.9

3.9.1

3.9.2

3.9.2.1

Bit Field name Reset RW Description

The registers SWAPFIFO and TDR allow the TX FIFO to be cleared from unwanted data.

All RESERVED fields inside registers must always be written with their default values.

UART

Introduction

The BlueNRG-1 integrates a universal asynchronous receiver/transmitter that support much of the functionality of the industry-standard 16C650 UART.

•

Main features are:

• Programmable baud rates up to 2 Mbps

Programmable data frame of 5, 6, 7 or 8 bits of data

Even, odd, stick or no-parity bit generation and detection

Programmable 1 or 2 stop bit

Support of hardware flow control using CTS and RTS pins

•

Support of software flow control using programmable Xon/Xoff characters

False start bit detection.

Line break generation and detection

Programmable 8-bit wide, 64-deep transmit FIFO and 12-bit wide (8-bit data and 4-bit status) , 64-deep receive FIFO

Support for direct memory access (DMA)

Functional description

The UART performs serial-to-parallel conversion on data asynchronously received from a peripheral device on the UART_RX pin, and parallel-to-serial conversion on data written by CPU for transmission on the UART_TX pin. The transmit and receive paths are buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64 data byte with 4-bit status (break, frame, parity, and overrun) for receive. FIFOs may be burst-loaded or emptied by the system processor from 1 to 16 words per transfer.

Data transmission or reception

Data received or transmitted is stored in two 64-byte FIFOs. The receive FIFO has an extra four bits per character for the status information:

• Error bits 8 to 10 are associated with a particular character: break error, parity error and framing error.

• Overrun indicator bit 11 is set when the FIFO is full, and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location is available in the receive FIFO, and another character is received, the state of the overrun bit is copied into the received FIFO along with the received character. The overrun state is then cleared.

FIFO bit

7:0

Table 66. RX FIFO errors

Function

Overrun indicator

Break error

Parity error

Framing error

Received data

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UART

For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in LCRH_TX. Data continue to be transmitted until there is no data left in the transmit FIFO. The BUSY flag in the UARTFR register is set as soon as data is written to the transmit

FIFO (that is, the FIFO is non-empty) and remains asserted while data is being transmitted. BUSY is cleared only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be set even though the UART might no longer be enabled. For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined, and one sample is taken either side of it. When the receiver detect a start bit, the receive counter runs and data is sampled on the 8th cycle of that counter in normal UART mode. The start bit is valid if UART_RX signal is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. If the start bit is valid, successive data bits are sampled on every 16th cycle of Baud16 (that is 1-bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Lastly, a valid stop bit is confirmed if UART_RX signal is high, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that. The UART character frame is shown in

Figure 13. UART character frame below.

Figure 13. UART character frame

3.9.2.2

FIFOs can be disabled. In this case, the transmit and receive sides of the UART have 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received, and the previous one was not yet read. In this implementation, the FIFOs are not physically disabled, but the flags are manipulated to give the illusion of a 1-byte register.

Baud rate divisor

The baud rate divisor is a 22-bit number consisting of a 16-bit integer (BRDI) and a 6-bit fractional part (BRDF).

The fractional baud rate divider enables the use of any clock to act as UART_CLK, while it is still possible to generate all the standard baud rates.

The 16-bit integer is loaded through the UART_IBRD register and the 6-bit fractional part is loaded into the

UART_FBRD register. The baud rate divisor has the following relationship:

When bit OVSFACT = 0b: divisor = UARTCLK/(16 x baud rate) = BRDI + BRDF.

When bit OVSFACT = 1b: divisor = UARTCLK/(8 x baud rate) = BRDI + BRDF.

Calculation of the fractional 6-bit number (DIVFRAC) is done by taking the fractional part of the required baud rate divisor and multiplying it by 64 (that is, 2n, where n is the width of the UART_FBRD register) and adding 0.5 to account for rounding errors:

DIVFRAC = integer(BRDF * 64 + 0.5)

The maximum deviation error using a 6-bit UART_FBRD register is 1/64 * 100 = 1.56%.

This occurs when DIVFRAC = 1, and the error is cumulative over 64 clock ticks.

Example 1 : Calculating the divisor value (with OVSFACT = 0b).

If the required baud rate is 460 800 and the UART clock frequency is 16 MHz then:

Baud rate divisor = (16 x 10 6 ) / (16 x 460 800) = 2.170

BRDI = 2 and BRDF = 0.170

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UART

Therefore fractional part DIVFRAC = integer(BRDF * 64 + 0.5) = 11

Generated baud rate divider = 2 + (11 / 64) = 2.171875

Generated baud rate = (16 x 10 6 ) / (16 x 2.171875) = 460 431

Error = (460 800 - 460 431) / 460 800 x 100 = 0.08%

An internal clock enable signal, Baudl6, is generated, and is a stream of one UARTCLK wide pulses with an average frequency of 16 (OVSFACT = 0b) or 8 (OVSFACT = 1b) times the desired baud rate. This signal is then divided by 16 or 8 to give the transmit clock. A low number in the baud rate divisor gives a short bit period, and a high number in the baud rate divisor gives a long bit period.

Table 67. Typical baud rates with OVSFACT = 0

shows some typical bit rates and their corresponding divisors when OVSFACT = 0b, given the UART clock frequency of 16 MHz.

Required bit rate (bps)

921 600

460 800

230 400

115 200

57 600

38 400

28 800

19 200

9 600

2 400

1 200

300

110

Table 67. Typical baud rates with OVSFACT = 0

Programmed divisor

Integer (DIVINT) Fraction (DIVFRAC)

1 (16’h0001)

2 (16’h0002)

4 (16’h0004)

8 (16’h0008)

17 (16’h0011)

26 (16’h001A)

34 (16’h0022)

52 (16’h0034)

104 (16’h0068)

416 (16’h01A0)

833 (16’h04B0)

3333 (16’h0D05)

9090 (16’h2382)

5 (6’h05)

11 (6’h0B)

22 (6’h16)

44 (6’h2C)

23 (6’h17)

3 (6’h03)

46 (6’h2E)

5 (6’h05)

11 (6’h0B)

43 (6’h2B)

21 (6’h15)

58 (6’h3A)

Generated bit rate (bps)

927 557

460 447

230 218

115 107

57 606

38 392

28 802

19 201

9 599

2 399

1 200

300

110

Error (%)

0.646

- 0.077

- 0.079

- 0.081

0.010

- 0.021

0.007

0.005

- 0.010

- 0.042

Required bit rate (bps)

1 843 200

921 600

460 800

230 400

115 200

57 600

38 400

28800

19 200

9 600

2 400

1 200

Table 68. Typical baud rates with OVSFACT = 1

Programmed divisor

Integer (DIVINT) Fraction (DIVFRAC)

1 (16’h0001)

2 (16’h0002)

5 (6’h05)

11 (6’h0B)

4 (16’h0004)

8 (16’h0008)

17 (16’h0011)

34 (16’h0022)

22 (6’h16)

44 (6’h2C)

23 (6’h17)

46 (6’h2E)

52 (16’h0034)

69 (16’h0045)

104 (16’h0068)

208 (16’h00D0)

833 (16’h0341)

1666 (16’h0682)

5 (6’h05)

28 (6’h1C)

11 (6’h0B)

21 (6’h15)

43 (6’h2B)

Generated bit rate (bps)

1 855 115

920 895

461 436

230 215

115 212

57 605

38 403

28 802

19 199

9 600

2 400

1 199

Error (%)

0.008

0.007

- 0.005

-0.083

0.646

- 0.076

- 0.079

- 0.080

0.010

0.009

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BlueNRG-1

UART

3.9.2.3

Required bit rate (bps)

300

110

Programmed divisor

Integer (DIVINT)

6666 (16’h1A0A)

18181 (16’h4705)

Fraction (DIVFRAC)

43 (6’h2B)

52 (6’h34)

Generated bit rate (bps)

299

110

Error (%)

-0.333

Hardware flow control

The hardware flow controls feature is fully selectable through RTSEN and CTSEN in UARTCR register, and allows to control the serial data flow by using the UART_RTS output and UART_CTS input signals.

Figure 14. Hardware flow control between two similar devices

DS11481 - Rev 10

When the RTS flow control is enabled, the UART_RTS signal is asserted until the receive FIFO is filled up to the programmed watermark level. When the CTS flow control is enabled, the transmitter can only transmit data when the UART_CTS signal is asserted.

CTSEN

Table 69. Control bits to enable and disable hardware flow control

RTSEN

Function

Both RTS and CTS flow control disabled.

Only RTS flow control enabled.

Only CTS flow control enabled.

Both RTS and CTS flow control enabled.

The RTS flow control logic is linked to the programmable receive FIFO watermark levels. When RTS flow control is enabled, the UART_RTS is asserted until the receive FIFO is filled up to the watermark level. When the receive

FIFO watermark level is reached, the UART_RTS signal is de-asserted, indicating that there is no more room to receive any more data. The transmission of data is expected to cease after the current character has been transmitted. The UART_RTS signal is reasserted when data has been read out of the receive FIFO so that it is filled to less than the watermark level. If RTS flow control is disabled and the UART is still enabled, then data is received until the receive FIFO is full, or no more data is transmitted to it.

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3.9.2.4

Note:

If CTS flow control is enabled, then the transmitter checks the UART_CTS signal before transmitting the next byte. If the UART_CTS signal is asserted, it transmits the byte otherwise, transmission does not occur. The data continues to be transmitted while UART_CTS is asserted, and the transmit FIFO is not empty. If the transmit FIFO is empty and the UART_CTS signal is asserted no data is transmitted. If the UART_CTS signal is de-asserted and CTS flow control is enabled, then the current character transmission is completed before stopping. If CTS flow control is disabled and the UART is enabled, then the data continues to be transmitted until the transmit FIFO is empty.

Software flow control

Software flow control is enabled through register UART_XFCR bit SFEN.

Software receive flow control

Once the software receive flow control is enabled, the receiver compares the incoming data with the programmed

Xoff values. Different combinations of software receive flow control, which can be selected through SFRMOD, where only 1 character match is needed or in which 2 Xoff characters must be received sequentially.

SFSEN

Table 70. Control bits to enable and program receive software flow control

SFRMOD xxb

00b

01b

10b

11b

Function

Software flow control disabled.

Software receive flow control disabled.

Use Xon1, Xoff1 for matching.

Use Xon2, Xoff2 for matching.

Use Xon1 & Xon2, Xoff1 & Xoff2 for matching.

If received characters match the programmed Xoff values, the transmission stops as soon as the current character is completely transferred. The interrupt bit XOFFRIS in the raw interrupt register UART_RIS is set.

If the corresponding interrupt mask bit is set, the corresponding bit in the UART_MIS register is set and the UART interrupt pin is asserted. Following such a transmission suspension, the receiver will monitor incoming characters for a match with the programmed Xon values. The matching strategy is programmable through SWRFCPROG in register UART_XFCR. Once a match is found, the receiver clears the interrupt bit XOFFRIS in the raw interrupt register UART_RIS and the Xoff interrupt is disabled. The transmission can then resume normally. When the

XONANY bit in register UART_XFCR is set, any incoming character is accepted as a valid Xon condition and the transmission can then resume. The received character is written into the received FIFO.

If the software flow control is enabled, the received Xon/Xoff characters are never written into the received FIFO.

Exceptions to this occur when the special character detection feature is enabled (Xoff2 is then written into FIFO upon a special character match) and when the Xon-any bit is set.

The received status (parity, framing and break error) of Xon/Xoff characters does not have to be valid for these characters to be accepted as valid matches.

When the software transmit flow control is enabled through the SFTMOD bit field in the UART_XFCR register, the transmitter will automatically insert an Xoff character if the received FIFO has passed the received trigger level

(bit field RXIFLSEL in the UART_IFLS register). The RTXDIS (remote transmitter disabled) bit in the UART_FR register is set to signal the remote transfer was stopped. When the receive FIFO falls below the trigger level, an

Xon character is automatically inserted in the transmission stream and the RTXDIS bit in the UART_FR register is cleared.

SFSEN

Table 71. Control bits to enable and program transmit software flow control

SFTMOD xxb

00b

01b

10b

11b

Function

Software flow control disabled.

Software transmit flow control disabled.

Use Xon1, Xoff1 for matching.

Use Xon2, Xoff2 for matching.

Use Xon1 and Xon2, Xoff1 and Xoff2 for matching.

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Note:

3.9.2.5

3.9.2.6

3.9.2.7

3.9.2.8

After an Xoff character has been transmitted, if the software flow controlled is turned off, a Xon character is automatically be inserted in the transmission stream and the bit RTXDIS bit in the UART_FR register is cleared.

Transmission of an Xon/Xoff character follows the standard transmission protocol as programmed in the transmitter registers (word length, parity and so on).

When using the software transmit flow control, there are some cautions to take to manage the interrupt handler.

The software must react on RX interrupt (the flag is raised once the RX FIFO contains the RXIFSEL trigger level. Then the interrupt handler must first poll the UART_FR.RTXDIS bit until it is set to indicate the Xoff byte transmission is over and only then read the RX FIFO content. Note that hardware and software flow control cannot be enabled simultaneously.

Software transmit flow control

When the special character detection feature is enabled through the SPECHAR bit in the UART_XFCR register, the software flow control is turned off and the receiver compares received characters with the Xoff2 value. When a match is found, the interrupt bit XOFFRIS in the raw interrupt register UART_RIS is set. If the corresponding interrupt mask bit is set, the UART interrupt pin is asserted. The transmission is not halted. The special character is written into the received FIFO. The interrupt bit XOFFIS will be cleared when the corresponding bit in interrupt clear register is written as 1b.

It is assumed that software flow control is turned off when this feature is used. The received status (i.e. parity, framing and break error) of special characters does not have to be valid for these characters to be accepted as valid matches.

•

UART interrupts

There are six individual maskable interrupt sources generated by the UART (single interrupt signal that drives the

NVIC):

TX FIFO empty interrupt

Xoff/ special character interrupt

Receive interrupt

Transmit interrupt

Timeout interrupt

Error interrupt

The user can enable or disable the individual interrupt sources by changing the mask bits in the UART_IMSC register. Setting the appropriate mask bit to 1b enables the interrupt. The status of the individual interrupt sources can be read from the UART_RIS register (raw interrupt status) or from the UART_MIS register (masked interrupt status).

TX FIFO empty interrupt

The TX FIFO empty interrupt is asserted whenever the BUSY status bit goes low to indicate that all DATA has been transmitted. This BUSY bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. So, the new TX FIFO empty interrupt is asserted when the transmit FIFO and the transmit shift register are empty.

Xoff/ special character interrupt

The Xoff/special character interrupt is asserted whenever an Xoff condition is detected by the receiver (incoming data matches with the programmable Xoff values), or when a special character detection was performed

(incoming data matches with the Xoff2 and SPECHAR bit set).

Receive interrupt

The receive interrupt is asserted HIGH when one of the following conditions occurs:

•

If FIFOs are enabled and the number of characters received reaches the programmed trigger watermark level. The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the programmed watermark level, or by clearing the interrupt by writing a 1b to the corresponding bit in the

UART_ICR register.

If FIFOs are disabled (have a depth of one location) and there is a data present in the receiver single location. It is cleared by performing a single read.

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3.9.2.9

Note:

3.9.2.10

3.9.2.11

3.9.3

Transmit interrupt

The transmit interrupt is asserted HIGH when one of the following conditions occurs:

• If the FIFOs are enabled and the number of characters in the transmit FIFO is less than the programmed watermark level. It is cleared by performing writes to the transmit FIFO until it holds more characters than the programmed watermark level, or by clearing the interrupt by software.

• If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitter single location. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt by software.

The transmit FIFO service interrupt is based on a transition through a level, rather than on the level itself. When the interrupt and the UART are enabled before any data is written to the transmit FIFO, the interrupt is not set.

The interrupt is only set once written data leaves the single location of the transmit FIFO and it becomes empty.

When the TX FIFO is disabled, the DATA can be written on the bottom of the FIFO during the transmission of a previous DATA, or in another words, when the holding register is busy.

The interrupt is de-asserted when we write the next DATA on the bottom of the TX FIFO. If we write DATA only on the holding register and the bottom of the TX FIFO is empty, the only way to clear the interrupt is by the software.

Timeout interrupt

The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received (or no correct start bit of a frame is detected in the RX line) over a programmable timeout period. This mechanism ensures that the user is aware that data is still present in the receive FIFO and requires servicing. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1b is written to the corresponding bit of the UART_ICR register.

Error interrupt

•

The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be caused by the following error conditions:

•

Framing

Parity

Break

• Overrun

The cause of the interrupt is available by reading the UART_RIS or UART_MIS registers. The interrupt can be cleared by writing to the relevant bits of the UART_ICR register.

UART registers

UART peripheral base address (UART_BASE_ADDR) 0x40300000.

Address offset

0x00

0x04

0x0C

0x18

0x1C

0x24

0x28

0x2C

Name RW

RSR

ECR

TIMEOUT RW

FR R

LCRH_RX RW

IBRD RW

FBRD RW

LCRH_TX RW

Reset

0x00000000

0x000001FF

0x00001E90

0x00000000

Table 72. UART registers

Description

Data register. Refer to the detailed description below.

Receive status register. Refer to the detailed description below.

Error clear register. A write to this register clears the framing (FE), parity (PE), break (BE), and overrun (OE) errors.

Timeout register. Refer to the detailed description below.

Flag register. Refer to the detailed description below.

Receive line control register. Refer to the detailed description below.

Integer baud rate register. Refer to the detailed description below.

Fractional baud rate register. Refer to the detailed description below.

Transmit line control register. Refer to the detailed description below.

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Address offset

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

0x50

0x54

0x58

0x5C

0x60

Name

IFLS

IMSC

RIS

MIS R

ICR W

DMACR RW

XFCR RW

XON1 RW

XON2

XOFF1

XOFF2 RW

Reset

0x00040300

0x00000012

0x00000000

Description

Control register. Refer to the detailed description below.

Interrupt FIFO level select register. Refer to the detailed description below.

Interrupt mask set/clear register. Refer to the detailed description below.

Raw interrupt status register. Refer to the detailed description below.

Masked interrupt status register. Refer to the detailed description below.

Interrupt clear register. Refer to the detailed description below.

DMA control register. Refer to the detailed description below.

XON/XOFF control register. Refer to the detailed description below.

Bit Field name

7:0

Table 73. UART - DR register description: address offset UART_BASE_ADDR+0x00

DATA

31:12 RESERVED

Reset

0x0

Description

UART data register:

Receive: read data character.

Transmit: write data character.

Frame error. This bit is set to 1 if the received character did not have a valid stop bit. In FIFO mode, this error is associated with the character at the top of the FIFO.

Parity error. This bit is set to 1 if the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the

LCRH_RX register. In FIFO mode, this error is associated with the character at the top of the FIFO.

When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to HIGH

(marking state), and the next valid start bit is received

Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0b once there is an empty space in the FIFO and a new character can be written to it. The FIFO content remains valid since no further data is written when the FIFO is full, only the content of the shift register is overwritten.

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Bit Field name

Table 74. UART - RSR register description: address offset UART_BASE_ADDR+0x04

31:4 RESERVED

Reset

0x0

Description

Frame error. This bit is set to 1 if the received character did not have a valid stop bit (a valid stop bit is 1).This bit is cleared to 0b after a write to ECR.

In FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error. This bit is set to 1 if the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the

LCRH_RX register. This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO.

Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity and stop bits). This bit is cleared to 0b after a write to ECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to HIGH (marking state), and the next valid start bit is received.

Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 by a write to ECR (data value is not important). The FIFO contents remain valid since no further data is written when the FIFO is full, only the content of the shift register are overwritten.

The CPU or DMA must now read the data in order to empty the FIFO.

R RESERVED

Bit Field name

21:0

Table 75. UART - TIMEOUT register description: address offset UART_BASE_ADDR+0x0C

PERIOD

31:22 RESERVED

Reset

0x1FF

0x0

Description

Timeout period configuration. This bit field contains the timeout period for the UART timeout interrupt assertion. The receive timeout interrupt is asserted when the receive FIFO is not empty and no further data is received over a programmed timeout period. The duration before the timeout interrupt assert is calculated by the following formula: timeout = PERIOD / (OverSamplingFactor * BaudRate) Where

OverSamplingFactor is:

16 if OVSFACT is 0

8 if OVSFACT is 1.

RW RESERVED

Table 76. UART - FR register description: address offset UART_BASE_ADDR+0x18

Bit Field name

0 CTS

2:1 RESERVED

BUSY

RXFE

Reset

0x0

0x1

R Clear to send.

Description

R RESERVED

UART Busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. However, if the transmit section of the UART is disabled in the middle of a transmission, the BUSY bit gets cleared.

This bit is set again once the transmit section is re-enabled to complete the remaining transmission. This bit is set as soon as the transmit FIFO becomes nonempty (regardless of whether the UART is enabled or not).

Receive FIFO empty. If the FIFO is disabled (bit FEN = 0b), this bit is set when the receive holding register is empty. If the FIFO is enabled (FEN =

1b), the RXFE bit is set when the receive FIFO is empty.

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Bit Field name

5 TXFF

6 RXFF

7 TXFE

8 RESERVED

9 DCTS

12:10 RESERVED

13 RTXDIS

31:14 RESERVED

Reset

0x0

0x1

0x0

0x1

0x7

0x0

RW Description

Transmit FIFO full. If the FIFO is disabled (bit FEN = 0b), this bit is set when the transmit holding register is full. If the FIFO is enabled (FEN = 1b), the

TXFF bit is set when the transmit FIFO is full.

Receive FIFO full. If the FIFO is disabled (bit FEN = 0b), this bit is set when the receive holding register is full. If the FIFO is enabled (FEN = 1b), the

RXFF bit is set when the receive FIFO is full.

Transmit FIFO empty. If the FIFO is disabled (bit FEN = 0b), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN =

1b), the TXFE bit is set when the transmit FIFO is empty.

R RESERVED

Delta clear to send. This bit is set CTS changes since the last read of the

FR register.

R RESERVED

Remote transmitter disabled (software flow control). This bit indicates an

Xoff character was sent to the remote transmitter to stop it after the received

FIFO has passed over its trigger limit. This bit is cleared when a Xon character is sent to the remote transmitter.

R RESERVED

Table 77. UART - LCRH_RX register description: address offset UART_BASE_ADDR+0x1C

Bit Field name

0 RESERVED

PEN_RX

EPS_RX

STP2_RX

FEN_RX

6:5 WLEN_RX

SPS_RX

Reset

0x0

RW RESERVED

Description

RX parity enable:

0: Parity disabled.

1: Parity enabled.

RX even parity selection, when the parity is enabled.

0: Odd parity generation and checking is performed during reception, which check for an odd number of 1s in data and parity bits.

1: Even parity generation and checking is performed during reception, which check for an even number of 1s in data and parity bits.

RX two stop bits select. This bit enables the check for two stop bits being received:

0: 1 stop bit received.

1: 2 stop bits received.

RX enable FIFOs. This bit enables/disables the receive RX FIFO buffer:

0: RX FIFO is disabled (character mode).

1: RX FIFO is enabled.

RX word length. This bit field indicates the number of data bits received in a frame as follows:

00b: 5 bits.

01b: 6 bits.

10b: 7 bits.

11b: 8 bits.

RX stick parity select:

0: stick parity is disabled.

1: when PEN_RX = 1b (parity enabled) and EPS_RX = 1b (even parity), the parity is checked as a 0. When PEN_RX = 1b and EPS_RX = 0b (odd parity), the parity bit is checked as a 1.

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Bit Field name

31:8 RESERVED

Reset

0x0

RW RESERVED

Description

Bit Field name

15:0

Table 78. UART - IBRD register description: address offset UART_BASE_ADDR+0x24

DIVINT

31:16 RESERVED

Reset

0x0

RW Description

Baud rate integer. The baud rate divisor is calculated as follows:

When OVSFACT = 0b in the CR register: Baud rate divisor = (frequency

(UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: Baud rate divisor = (frequency

(UARTCLK)/(8*Baud rate)) where frequency (UARTCLK) is the UART reference clock frequency. The baud rate divisor comprises the integer value (DIVINT) and the fractional value (DIVFRAC). The contents of the IBRD and FBRD registers are not updated until transmission or reception of the current character has completed.

RW RESERVED

Bit Field name

5:0

Table 79. UART - FBRD register description: address offset UART_BASE_ADDR+0x28

DIVFRAC

31:6 RESERVED

Reset

0x0

RW Description

Baud rate fraction. Baud rate integer. The baud rate divisor is calculated as follows:

When OVSFACT = 0b in the CR register: baud rate divisor = (frequency

(UARTCLK)/(16*Baud rate))

When OVSFACT = 1b in CR register: baud rate divisor = (frequency

RW RESERVED

Table 80. UART - LCRH_TX register description: address offset UART_BASE_ADDR+0x2C

Bit Field name

BRK

PEN_TX

EPS_TX

Reset

0x0

Description

Send break. This bit allows a continuous low-level to be forced on TX output, after completion of the current character. This bit must be asserted for at least one complete frame transmission time in order to generate a break condition. The transmit FIFO contents remain unaffected during a break condition.

0: Normal transmission.

1: Break condition transmission.

TX parity enable:

0: Parity disabled.

1: Parity enable.

TX even parity select. This bit selects the parity generation, when the parity is enabled (PEN_TX =1b). This bit has no effect when parity is disabled

(PEN_TX = 0b).

0: Odd parity generation and checking is performed during transmission, which check for an odd number of 1s in data and parity bits.

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Bit Field name

3 STP2_TX

4 FEN_TX

6:5 WLEN_TX

7 SPS_TX

31:8 RESERVED

Reset

0x0

Description

1: Even parity generation and checking is performed during transmission, which check for an even number of 1s in data and parity bits.

TX two-stop bits select. This bit enables the check for two stop bits being received:

0: 1 stop bit received.

1: 2 stop bits received.

TX Enable FIFO. This bit enables/disables the transmit TX FIFO buffer:

0: TX FIFO is disabled (character mode), i.e. the TX FIFO becomes a

1-byte deep holding register.

1: TX FIFO is enabled.

TX word length. This bit field indicates the number of data bits transmitted in a frame as follows:

00b: 5 bits.

01b: 6 bits.

10b: 7 bits.

11b: 8 bits.

TX stick parity check:

0: stick parity disable.

1: when PEN_TX = 1b (parity enabled) and EPS_TX = 1b (even parity), the parity is transmitted as a 0. When PEN_TX = 1b and EPS_TX = 0b (odd parity), the parity bit is transmitted as a 1.

RW RESERVED

7:4

Bit

2:1

Table 81. UART - CR register description: address offset UART_BASE_ADDR+0x30

Field name

RESERVED

OVSFACT

RESERVED

TXE

RXE

RESERVED

RTS

Reset

0x0

0x1

0x0

RW Description

UART enable. This bit enables the UART.

0: UART is disabled.

1: UART is enabled. Data transmission and reception can occur.

When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

RW RESERVED

UART oversampling factor. This bit enables the UART oversampling factor. If UARTCLK is 16 MHz thus max. baud-rate is 1 Mbaud when

OVSFACT = 0b, and 2 Mbaud when OVSFACT = 1b.

0: UART it is 16 UARTCLK clock cycles.

1: UART it is 8 UARTCLK clock cycles.

RW RESERVED

Transmit enable.

0b: UART TX disabled.

1b: UART TX enabled.

Receive enable.

0b: UART RX disabled.

1b: UART RX enabled.

RW RESERVED

Request to send.

0: RTS is high.

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Bit

13:12

Field name

RESERVED

RTSEN

CTSEN

19:16 STA_B_DURATION

31:20 RESERVED

Reset

0x0

0x4

0x0

1: RTS is low.

RW RESERVED

Description

RTS hardware flow control enable.

0b: RTS disabled.

1b: RTS enabled. Data is only requested when there is space in the receive FIFO for it to be received.

CTS hardware flow control enable.

0b: CTS disabled.

1b: CTS enabled. Data is only transmitted when the CTS is asserted.

START bit duration receiver state. These bits can be used to configure the START bit duration (in clock cycles) to get the bit sampled in the middle of the UART receiver. These bits can be used only when using high baud rates (IBRD = 1, FBRD ≥ 0 and

OVSFACT = 1). Below the formula to calculate the START bit duration receiver state:

STA_B_DURATION = Integer(Fuartclk/(2* BAUD RATE)) - 1

Example: when UARTCLK = 16 MHz and BAUD RATE = 2.0 Mbps then STA_B_DURATION = 4 - 1 = 3. STA_B_DURATION field should be configured with 4'b0011.

RW RESERVED

Table 82. UART - IFLS register description: address offset UART_BASE_ADDR+0x34

Bit Field name

2:0 TXIFLSEL

5:3 RXIFLSEL

31:6 RESERVED

Reset

0x2

0x0

Description

Transmit interrupt FIFO level select. This bit field selects the trigger points for TX FIFO interrupt:

000b: Interrupt when FIFO ≥ 1/64 empty.

001b: Interrupt when FIFO ≥ 1/32 empty.

010b: Interrupt when FIFO ≥ 1/16 empty.

011b: Interrupt when FIFO ≥ 1/8 empty.

100b: Interrupt when FIFO ≥ 1/4 empty.

101b: Interrupt when FIFO ≥ 1/2 empty.

110b: Interrupt when FIFO ≥ 3/4 empty.

Receive interrupt FIFO level select. This bit field selects the trigger points for RX FIFO interrupt:

000b: Interrupt when FIFO ≥ 1/64 full.

001b: Interrupt when FIFO ≥ 1/32 full.

010b: Interrupt when FIFO ≥ 1/16 full.

011b: Interrupt when FIFO ≥ 1/8 full.

100b: Interrupt when FIFO ≥ 1/4 full.

101b: Interrupt when FIFO ≥ 1/2 full.

110b: Interrupt when FIFO ≥ 3/4 full.

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Bit Field name

0 RESERVED

3:2 RESERVED

Table 83. UART - IMSC register description: address offset UART_BASE_ADDR+0x38

CTSMIM

RXIM

TXIM

RTIM

FEIM

PEIM

BEIM

OEIM

XOFFIM

TXFEIM

31:13 RESERVED

Reset

0x0

RW RESERVED

Description

Clear to send modem interrupt mask. On a read, the current mask for the

CTSMIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

RW RESERVED

Receive interrupt mask. On a read, the current mask for the RXIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

Transmit interrupt mask. On a read, the current mask for the TXIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

Receive timeout interrupt mask. On a read, the current mask for the RTIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

Framing error interrupt mask. On a read, the current mask for the FEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

Parity error interrupt mask. On a read, the current mask for the PEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

Break error interrupt mask. On a read, the current mask for the BEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

Overrun error interrupt mask. On a read, the current mask for the OEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

XOFF interrupt mask. On a read, the current mask for the XOFFIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

TX FIFO empty interrupt mask. On a read, the current mask for the TXFEIM interrupt is returned.

0: Clears the mask (interrupt is disabled).

1: Sets the mask (interrupt is enabled).

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Bit

3:2

Bit

3:2

31:13

Table 84. UART - RIS register description: address offset UART_BASE_ADDR+0x3C

Field name

RESERVED

CTSMIS

RESERVED

RXIS

TXIM

RTIS

FEIS

PEIS

BEIS

OEIS

XOFFIS

TXFEIS

RESERVED

Reset

0x0

R RESERVED

Description

Clear to send interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

R RESERVED

Receive interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Transmit interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Receive timeout interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Framing error interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Parity error interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Break error interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Overrun error interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

XOFF interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

TX FIFO empty interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

R RESERVED

Table 85. UART - MIS register description: address offset UART_BASE_ADDR+0x40

Field name

RESERVED

CTSMMIS

RESERVED

Reset

0x0

RW Description

R RESERVED

Clear to send masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

R RESERVED page 66/167

DS11481 - Rev 10

BlueNRG-1

UART

Bit

3:2

Bit

Field name

RXMIS

TXMIS

RTMIS

FEMIS

PEMIS

BEMIS

OEMIS

XOFFMIS

31:13

TXFEMIS

RESERVED

Reset

0x0

RW Description

Receive masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Transmit masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Receive timeout masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Framing error masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Parity error masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Break error masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

Overrun error masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

XOFF interrupt masked status.

0: The interrupt is not pending.

1: The interrupt is pending.

TX FIFO empty masked interrupt status.

0: The interrupt is not pending.

1: The interrupt is pending.

R RESERVED

Table 86. UART - ICR register description: address offset UART_BASE_ADDR+0x44

Field name

RESERVED

CTSMIC

RESERVED

RXIC

TXIC

Reset

0x0

RW Description

RW RESERVED

Clear to send modem interrupt clear.

0: No effect.

1: Clears the interrupt.

RW RESERVED

Receive interrupt clear.

0: No effect.

1: Clears the interrupt.

Transmit interrupt clear.

0: No effect.

1: Clears the interrupt.

page 67/167

DS11481 - Rev 10

BlueNRG-1

UART

Bit

31:13

Field name

RTIC

FEIC

PEIC

BEIC

OEIC

XOFFIC

TXFEIC

RESERVED

Reset

0x0

RW Description

Receive timeout interrupt clear.

0: No effect.

1: Clears the interrupt.

Framing error interrupt clear.

0: No effect.

1: Clears the interrupt.

Parity error interrupt clear.

0: No effect.

1: Clears the interrupt.

Break error interrupt clear.

0: No effect.

1: Clears the interrupt.

Overrun error interrupt clear.

0: No effect.

1: Clears the interrupt.

XOFF interrupt clear.

0: No effect.

1: Clears the interrupt.

TX FIFO empty interrupt clear.

0: No effect.

1: Clears the interrupt.

RW RESERVED

Table 87. UART - DMACR register description: address offset UART_BASE_ADDR+0x48

Bit Field name

RXDMAE

TXDMAE

RESERVED

3 DMAONERR

31:4 RESERVED

Reset

0x0

RW Description

Receive DMA enable bit.

0: DMA mode is disabled for reception.

1: DMA mode is enabled for reception.

Transmit DMA enable bit.

0: DMA mode is disabled for transmit.

1: DMA mode is enabled for transmit.

RW RESERVED

DMA on error.

0: UART error interrupt status has no impact in receive DMA mode.

1: DMA receive requests are disabled when the UART error interrupt is asserted.

RW RW RESERVED

Table 88. UART - XFCR register description: address offset UART_BASE_ADDR+0x50

Bit Field name

SFEN

Reset

0x0

Software flow control enable.

0: Software flow control disable.

Description page 68/167

DS11481 - Rev 10

BlueNRG-1

UART

Bit Field name

2:1 SFRMOD

4:3 SFTMOD

5 XONANY

6 SPECHAR

31:7 RESERVED

Reset

0x0

1: software flow control enable.

Description

Software receive flow control mode:

00b: Receive flow control is disabled.

01b: Xon1, Xoff1 characters are used in receiving software flow control.

10b: Xon2, Xoff2 characters are used in receiving software flow control.

11b: Xon1 and Xon2, Xoff1 and Xoff2 characters are used in receiving software flow control.

Software transmit flow control mode:

00b: Transmit flow control is disabled.

01b: Xon1, Xoff1 characters are used in transmitting software flow control.

10b: Xon2, Xoff2 characters are used in transmitting software flow control.

11b: Xon1 and Xon2, Xoff1 and Xoff2 characters are used in transmitting software flow control.

Xon-any bit:

0: Incoming character must match Xon programmed value(s) to be a valid

Xon.

1: Any incoming character is considered as a valid Xon.

Special character detection bit.

0: Special character detection disabled.

1: Special character detection enabled.

RW RESERVED

Bit

7:0

31:8

Table 89. UART - XON1 register description: address offset UART_BASE_ADDR+0x54

Field name

XON1

RESERVED

Reset

0x0

RW Description

RW Value of Xon1 character used in the software flow control

RW RW RESERVED

Bit

7:0

31:8

Table 90. UART - XON2 register description. Address offset UART_BASE_ADDR+0x58.

Field name

XON2

RESERVED

Reset

0x0

RW Description

RW Value of Xon2 character used in the software flow control.

RW RESERVED

Bit

7:0

31:8

Table 91. UART - XOFF1 register description. Address offset UART_BASE_ADDR+0x5C.

Field name

XOFF1

RESERVED

Reset

0x0

RW Description

RW Value of Xoff1 character used in the software flow control.

RW RESERVED

Bit

7:0

31:8

Table 92. UART - XOFF2 register description. Address offset UART_BASE_ADDR+0x60.

Field name

XOFF2

RESERVED

Reset

0x0

RW Description

RW Value of Xoff2 character used in the software flow control.

RW RESERVED page 69/167

BlueNRG-1

I²C

Note:

3.10

3.10.1

3.10.2

3.10.2.1

3.10.2.2

All RESERVED fields inside registers must always be written with their default values.

I²C

Introduction

The BlueNRG-1 integrates two I²C controllers in the QFN32 package (I 2 C2 and I 2 C1), and one in the WCSP34 package (I2C2). The I²C controller interface is designed to support the physical and data link layer according to

I²C standard revision 3.0 and provides a low-cost interconnection between ICs.

•

Main features are:

• Up to 400 Kb/s in fast mode and up to 100 Kb/s in standard mode.

•

Operating modes supported are master mode, slave mode, master/slave mode for multi-master system with bus arbitration.

Programmable 7-bit or 10-bit addressing (also with combined formats).

Programmable start byte procedure.

16-byte depth RX FIFO and 16-byte depth TX FIFO.

Spike digital filtering on the SDA and SCL lines.

Control timing constraint defined by the I²C standard.

Support for direct memory access (DMA).

Functional description

Two wires, serial data (SDA) and serial clock (SCL) carry information between the devices connected to the bus.

Each device has a unique address and can operate as either a transmitter or receiver, depending on the function of the device. A master is the device that initiates a data transfer on the bus and generates the clock signal. Any device addressed is considered at that time a slave. The I²C bus is a multi-master bus where more than one device is capable of controlling the bus. This means that more than one master could try to initiate a data transfer at the same time. The arbitration procedure relies on the wired-AND connection of all I²C interfaces to the I²C bus.

If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line. Generation of clock signals on the I²C bus is always the responsibility of master devices; each master generates its own clock signals when transferring data to the bus. Bus clock signals from a master can only be altered when they are stretched by a slow slave device holding down the clock line, or by another master when arbitration occurs.

Two modes:

• Standard mode with bit rate up to 100 Kb/s

• Fast mode with bit rate up to 400 Kb/s

I²C FIFO management

The transmit and receive paths are buffered with internal FIFO memory enabling up to 16 bytes to be stored independently in both transmit and receive modes. The FIFOs status can be checked using the I²C interrupts.

There is a programmable threshold value for each FIFO. When the number of entries is greater for the receive

FIFO or less for the transmit FIFO, an interrupt is set.

I²C clock rate calculation

To define the I²C clock rate generation there is one register to configure: BRCR. The clock rate can be calculated using this formula:

DS11481 - Rev 10

Where:

• f

I2C

is the I²C peripheral clock, clocked on the system clock divided by 3.

page 70/167

BlueNRG-1

I²C

3.10.2.3

Note:

3.10.2.4

3.10.3

•

BRCNT2 is a field of the BRCR register.

Foncycle depends on a programmable field of the CR register:

– CR: FON = “00” → Filter the clock spike wide = 0 → Foncycle = 1

– CR: FON = “01” → Filter the clock spike wide = 1 → Foncycle = 3

– CR: FON = “10” → Filter the clock spike wide = 2 → Foncycle = 4

– CR: FON = “11” → Filter the clock spike wide = 4 → Foncycle = 6

The minimum input clock frequency for the I²C is:

• 1.4 MHz if the I²C is in standard mode at 100 kHz.

• 7.2 MHz if the I²C is in fast mode at 400 kHz.

•

I²C configuration

Following a reset, the I²C logic is disabled and must be configured when in this state.

The control register (CR) and baud rate register (BRCR) need to be programmed to configure the following parameters of the peripheral:

Master or slave.

7- or 10-bit addressing mode.

Speed mode.

Clock rate.

If in slave mode, the SCR register has to be programmed with the selected slave address.

•

Then, if in master mode, the MCR register is used to define the transaction:

• Read or write.

•

Slave addresses (7- or 10-bit) to communicate with.

Addressing a 7- or 10-bit slave address.

Stop condition, to generate a stop or restart condition at the end of the transaction (for consecutive transactions).

• Transaction length.

For a master write, the data to transmit have to be written to the transmit FIFO in the I2C_TFR register. For a master read, when the master transaction is done, data are available in the receive FIFO in I2C_RFR.

DMA interface

The I²C controller includes a specific DMA interface. The following section describes the signals interface, data flow and programming model for the RX and the TX paths.

The DMA interfaces are separated for each path and two DMA request channels shall be used for a device.

In RX mode, a DMA transfer based on a single descriptor shall be used and the DMA RX channel must be programmed for a peripheral-to-memory transfer where the flow controller is the DMA. Each descriptor is related to a single I²C transaction (master read or write-to-slave operation) and no linked list item should be used. The transfer length is programmed on the DMA and the termination of the frame transfer is notified by the assertion of the related interrupt I2C_RISR:STD or I2C_RISR:MTD bits. In case of read-from-slave operation, on the DMA

(master device) the transfer length shall be programmed according to the I2C_MCR:LENGTH register field. In case of write-to-slave operation, on the DMA (slave device) the maximum length (not the real length because it is unknown) shall be programmed.

In TX mode, a DMA transfer based on a single descriptor shall be used and the DMA TX channel must be programmed for a memory-to-peripheral transfer where the flow controller is the DMA. Each descriptor is related to a single I²C transaction (master write or read-from-slave operation) and no linked list item should be used. The transfer length is programmed on the DMA and the termination of the frame transfer is notified by the assertion of the related interrupt I2C_RISR:STD or I2C_RISR:MTD bits. In case of write-to-slave operation, on the DMA

(master device) the transfer length shall be programmed according to the I2C_MCR:LENGTH register field. In case of read-from-slave operation, on the DMA (slave device) the maximum length (not the real length because it is unknown) shall be programmed.

I²C registers

I 2 C2 peripheral base address (I 2 C2_BASE_ADDR) 0x40A00000

I 2 C1 peripheral base address (I 2 C1_BASE_ADDR) 0x40B00000

DS11481 - Rev 10 page 71/167

DS11481 - Rev 10

BlueNRG-1

I²C

0x38

0x4C

0x50

0x54

0x58

0x20

0x24

0x28

0x2C

0x30

0x34

Address offset

0x00

0x04

0x0C

0x10

0x14

0x18

0x1C

Table 93. I 2 Cx registers

Name RW Reset Description

SCR

MCR

TFR

RFR

TFTR

RFTR

DMAR

BRCR

IMSCR

RISR

RW 0x00000000 I²C control register. Refer to the detailed description below.

RW 0x000F0055 I²C slave control register. Refer to the detailed description below.

RW 0x00000000

I²C master control register. Refer to the detailed description below.

RW 0x00000000

I²C transmit FIFO register. Refer to the detailed description below.

0x00000000 I²C status register. Refer to the detailed description below.

0x00000000 I²C receive FIFO register. Refer to the detailed description below.

0x00000000

I²C transmit FIFO threshold register. Refer to the detailed description below.

RW 0x00000000

I²C receive FIFO threshold register. Refer to the detailed description below.

RW 0x00000000 I²C DMA register. Refer to the detailed description below.

RW 0x00000008

I²C baud-rate counter register. Refer to the detailed description below.

RW 0x00000000

I²C interrupt mask set/clear register. Refer to the detailed description below.

R 0x00000013

I²C raw interrupt status register. Refer to the detailed description below.

MISR

ICR

R 0x00000000

RW 0x00000000

I²C masked interrupt status register. Refer to the detailed description below.

I²C interrupt clear register. Refer to the detailed description below.

THDDAT RW 0x00000014 I²C hold time data. Refer to the detailed description below.

THDSTA_FST_STD RW 0x003F00E2

I²C hold time start condition F/S. Refer to the detailed description below.

RESERVED RW 0x00000019 RESERVED

TSUSTA_FST_STD RW 0x001D00E2

I²C setup time start condition F/S. Refer to the detailed description below.

Bit

2:1

Table 94. I2C - CR register description: address offset I2CX_BASE_ADDR+0x00

Field name

Reset

0x0

Description

I²C enable disable:

0: I²C disable.

1: I²C enable.

This bit when deasserted works as software reset for I²C peripheral.

Select the operating mode:

00b: Slave mode. The peripheral can only respond (transmit/receive) when addressed by a master device

01b: Master mode. The peripheral works in a multi-master system where itself cannot be addressed by another master device. It can only initiate a new transfer as master device.

10b: Master/slave mode. The peripheral works in a multi-master system where itself can be addressed by another master device, besides to initiate a transfer as master device.

page 72/167

DS11481 - Rev 10

BlueNRG-1

I²C

Bit Field name Reset

3 SAM

5:4

12:11

14:13

SGCM

FTX

FRX

DMA_TX_EN

DMA_RX_EN

RESERVED

FON

0x0

RW Description

Slave addressing mode. SAM defines the slave addressing mode when the peripheral works in slave or master/slave mode. The received address is compared with the content of the register SCR.

0: 7-bit addressing mode.

1: 10-bit addressing mode.

Speed mode. SM defines the speed mode related to the serial bit rate:

0: Standard mode (up to 100 k/s).

1: Fast mode (up to 400 k/s).

Slave general call mode defines the operating mode of the slave controller when a general call is received. This setting does not affect the hardware general call that is always managed in transparent mode.

0: transparent mode, the slave receiver recognizes the general call but any action is taken by the hardware after the decoding of the message included in the Rx FIFO.

1: direct mode, the slave receiver recognizes the general call and executes directly (without software intervention) the related actions. Only the status code word is stored in the I2C_SR register for notification to the application.

FTX flushes the transmit circuitry (FIFO, fsm). The configuration of the

I²C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I²C clocks) and needs several system clock cycles before being completed. Upon completion, the I²C node (internal logic) clears this bit. The application must not access the Tx FIFO during the flushing operation and should poll on this bit waiting for completion.

0: Flush operation is completed (I 2 C controller clears the bit).

1: Flush operation is started and in progress (set by application).

FRX flushes the receive circuitry (FIFO, fsm).The configuration of the

I²C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I²C clocks) and needs several system clock cycles before to be completed. Upon completion, the I²C node (internal logic) clears this bit. The application must not access the Rx FIFO during the flushing operation and should poll on this bit waiting for the completion.

0: Flush operation is completed (I 2 C controller clears the bit).

1: Flush operation is started and in progress (set by application).

Enables the DMA TX interface.

0: Idle state, the DMA TX interface is disabled.

1: Run state, the DMA TX interface is enabled.

On the completion of the DMA transfer, the DMA TX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time.

Enables the DMA RX interface.

0: Idle state, the DMA RX interface is disabled.

1: Run state, the DMA RX interface is enabled.

On the completion of the DMA transfer, the DMA RX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time.

RW RESERVED

Filtering on sets the digital filters on the SDA, SCL line, according to the

I²C bus requirements, when standard open-drain pads are used: page 73/167

DS11481 - Rev 10

BlueNRG-1

I²C

Bit Field name

15 FS_1

31:16 RESERVED

Reset

0x0

RW Description

00b: No digital filters are inserted.

01b: Digital filters (filter 1 ck wide spikes) are inserted.

10b: Digital filters (filter 2 ck wide spikes) are inserted.

11b: Digital filters (filter 4 ck wide spikes) are inserted.

Force stop enable bit. When set to 1b, the STOP condition is generated.

0: Force stop disabled.

1: Enable force stop.

RW RESERVED

6:0

9:7

31:16

Table 95. I2C - SCR register description: address offset I2CX_BASE_ADDR+0x04

Bit Field name

SA7

ESA10

15:10 RESERVED

SLSU

Reset

0x55

0x0

0xF

Description

Slave address 7-bit. SA7 includes the slave address 7-bit or the LSB bits of the slave address 10-bit

Extended slave address 10-bit. ESA10 includes the extension (MSB bits) to the SA7 register field in case of slave addressing mode set to 10-bit

RW RESERVED

Slave data setup time. SLSU defines the data setup time after SCL clock stretching in terms of i2c_clk cycles. Data setup time is actually equal to

SLSU-1 clock cycles. The typical values for i2c_clk of 16 MHz are SLSU = 5 in standard mode and SLSU = 3 in fast modes.

7:1

10:8

13:12

Table 96. I2C2 - MCR register description: address offset I2CX_BASE_ADDR+0x0C

Bit Field name

EA10

Reset

0x0

Description

Operation

0: Indicates a master write operation.

1: Indicates a master read operation.

Address. Includes the 7-bit address or the LSB bits of the10-bit address used to initiate the current transaction

Extended address. Includes the extension (MSB bits) of the field A7 used to initiate the current transaction

Start byte:

0: The start byte procedure is not applied to the current transaction.

1: The start byte procedure is prefixed to the current transaction.

Address type:

00b: The transaction is initiated by a general call command. In this case the fields OP, A7, EA10 are "don't care".

01b: The transaction is initiated by the 7-bit address included in the A7 field.

10b: The transaction is initiated by the 10-bit address included in the EA10 and A7 fields.

Stop condition:

0: The current transaction is not terminated by a STOP condition. A repeated START condition is generated on the next operation which is required to avoid to stall the I²C line.

1: The current transaction is terminated by a STOP condition.

page 74/167

DS11481 - Rev 10

BlueNRG-1

I²C

Bit Field name

25:15 LENGTH

31:26 RESERVED

Reset

0x0

RW Description

Transaction length. Defines the length, in terms of the number of bytes to be transmitted (MW) or received (MR). In case of write operation, the payload is stored in the Tx FIFO. A transaction can be larger than the Tx FIFO size.

In case of read operation the length refers to the number of bytes to be received before generating a not-acknowledge response. A transaction can be larger than the Rx FIFO size. The I²C clock line is stretched low until the data in Rx FIFO are consumed.

RW RESERVED

Bit Field name

7:0

Table 97. I2C - TFR register description: address offset I2CX_BASE_ADDR+0x10

TDATA

31:8 RESERVED

Reset

0x0

RW Description

Transmission data. TDATA contains the payload related to a master write or read-from-slave operation to be written in the Tx FIFO. TDATA(0) is the first

LSB bit transmitted over the I²C line.

In case of master write operation, the Tx FIFO shall be preloaded otherwise the I²C controller cannot start the operation until data are available.

In case of read-from-slave operation, when the slave is addressed, the interrupt RISR:RFSR bit is asserted and the CPU shall download the data in the FIFO. If the FIFO is empty and the I²C master is still requiring data, a new request (RISR:RFSE interrupt bit) is asserted to require additional data to the CPU. The slave controller stretches the I²C clock line when no data are available for transmission. Since the Tx FIFO could contain some pending data related to the previous transfer (the transfer length may be unknown to the slave controller), the Tx FIFO is self-flushed before asserting the I2C_RISR:RFSR bit. Upon completion of the read-from-slave operation the interrupt bit I2C_RISR:STD is asserted and the related status of the operation is stored in the I2C_SR register. In CPU mode, the FIFO management is based on the assertion of the interrupt bit RISR:TXFNE, related to the nearly-empty threshold.

In DMA mode, the single/burst requests are automatically executed based on the number of entries available in the TX FIFO and the related destination burst size programmed in the I2C_DMAR:DBSIZE_TX register field. The DMA requests are terminated at the end of the I²C read operation

(notacknowledge received by the master) by a dummy last single/burst request.

RW RESERVED

1:0

3:2

6:4

Table 98. I2C - SR register description: address offset I2CX_BASE_ADDR+0x14

Bit Field name

STATUS

CAUSE

Reset

0x0

Description

Operation:

00b: MW: master write operation.

01b: MR: master read operation.

10b: WTS: write-to-slave operation.

11b: RFS: read-from-slave operation.

Controller status. Valid for the operations MW, MR, WTS RFS:

00b: NOP: No operation is in progress.

01b: ON_GOING: An operation is ongoing.

10b: OK: The operation (OP field) has been completed successfully.

11b: ABORT: The operation (OP field) has been aborted due to the occurrence of the event described in the CAUSE field.

Abort cause. This field is valid only when the STATUS field contains the

ABORT tag. Others: RESERVED.

page 75/167

DS11481 - Rev 10

BlueNRG-1

I²C

Bit Field name

8:7 TYPE

19:9 LENGTH

28:

RESERVED

29 DUALF

Reset

0x0

Description

000b: NACK_ADDR: The master receives a not-acknowledge after the transmission of the address. Valid for the operation MW, MR.

001b: NACK_DATA: The master receives a not-acknowledge during the data phase of a MW operation. Valid for the operation MW.

011b: ARB_LOST: The master loses the arbitration during a MW or MR operation. Valid for the operation MW, MR.

100b: BERR_START: Slave restarts, a START Condition occurs while the byte transfer is not terminated.

101b: BERR_STOP: Slave Reset, a STOP Condition while the byte transfer is not terminated.

110b: OVFL: The slave receives a frame related to the WTS operation longer than the maximum size = 2047 bytes. In this case the slave device returns a NACK to complete the data transfer. Valid for WTS operation

Receive type. Valid only for the operation WTS:

00b: FRAME: The slave has received a normal frame.

01b: GCALL: The slave has received a general call. If the it I2C_CR:SGCM is set to 1, the general call is directly executed without software intervention and only the control code word is reported in FIFO (LENGTH =0).

10b: HW_GCALL: The slave has received a hardware general call.

Transfer length. For an MR, WTS operation the LENGTH field defines the actual size of the subsequent payload, in terms of number of bytes. For an

MW, RFS operation the LENGTH field defines the actual number of bytes transferred by the master/slave device. For a WTS operation if the transfer length exceeds 2047 bytes, the operation is stopped by the slave returning a NACK handshake and the flag OVFL is set. For an RFS operation if the transfer length exceeds 2047 bytes, the operation continues normally but the LENGTH field is reset to 0.

R RESERVED

Dual flag (slave mode):

0: Received address matched with slave address (SA7).

1: Received address matched with dual slave address (DSA7).

Cleared by hardware after a stop condition or repeated Start condition, bus error or when PE=0.

R RESERVED 31:30 RESERVED 0x0

Bit Field name

7:0

Table 99. I2C - RFR register description: address offset I2CX_BASE_ADDR+0x18

RDATA

31:8 RESERVED

Reset

0x0

Description

Receive data. RDATA contains the received payload, related to a master read or write-to-slave operation, to be read from the Rx FIFO. The

RDATA(0) is the first LSB bit received over the I2C line. In case the FIFO is full, the I2C controller stretches automatically the I2C clock line until a new entry is available.

For a write-to-slave operation, when the slave is addressed, the interrupt

I2C_RISR:WTSR bit is asserted for notification to the CPU. In CPU mode the FIFO management shall be based on the assertion of the interrupt bit

I2C_RISR:RXFNF, related to the nearly-full threshold.

In DMA mode, the single requests are automatically executed based on the number of entries contained in the Rx FIFO.

R RESERVED page 76/167

DS11481 - Rev 10

BlueNRG-1

I²C

Table 100. I2C - TFTR register description: address offset I2CX_BASE_ADDR+0x1C

Bit Field name

9:0 THRESH_TX

31:10 RESERVED

Reset

0x0

Description

Threshold TX, contains the threshold value, in terms of number of bytes, of the Tx FIFO.

When the number of entries of the Tx FIFO is less or equal than the threshold value, the interrupt bit I2C_RISR:TXFNE is set in order to request the loading of data to the application.

RW RESERVED

Bit

Table 101. I2C - RFTR register description: address offset I2CX_BASE_ADDR+0x20

Field name

9:0 THRESH_RX

31:10 RESERVED

Reset

0x0

RW Description

Threshold RX, contains the threshold value, in terms of number of bytes, of the Rx FIFO.

When the number of entries of the RX FIFO is greater than or equal to the threshold value, the interrupt bit RISR:RXFNF is set in order to request the download of received data to the application. The application shall download the received data based on the threshold. (RISR:RXFNF).

RW RESERVED

Table 102. I2C - DMAR register description: address offset I2CX_BASE_ADDR+0x24

Bit Field name

7:0 RESERVED

10:8 DBSIZE_TX

11 BURST_TX

31:12 RESERVED

Reset

0x0

RW RESERVED

Description

Destination burst size. This register field is valid only if the BURST_TX bit is set to '1'. If burst size is smaller than the transaction length, only single request are generated.

Defines the type of DMA request generated by the DMA TX interface.

0: Single request mode. Transfers a single data (one byte) in the TX FIFO.

1: Burst request mode. Transfers a programmed burst of data according to

DBSIZE_TX field.

When the burst mode is programmed, the DMA transfer can be completed by one or more single requests as required.

RW RESERVED

Bit Field name

15:0

Table 103. I2C - BRCR register description: address offset I2CX_BASE_ADDR+0x28

BRCNT

31:16 RESERVED

Reset

0x8

0x0

RW Description

Baud rate counter. BRCNT defines the counter value used to set up the I2C baud rate in standard and fast mode, when the peripheral is operating in master mode.

RW RESERVED

Table 104. I2C - IMSCR register description: address offset I2CX_BASE_ADDR+0x2C

Bit Field name

TXFEM

TXFNEM

Reset

0x0

Description

TX FIFO empty mask. TXFEM enables the interrupt bit TXFE:

0: TXFE interrupt is disabled.

1: TXFE interrupt is enabled.

RW TX FIFO nearly empty mask. TXFNEM enables the interrupt bit TXFNE: page 77/167

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Bit Field name Reset

15:7

TXFFM

TXFOVRM

RXFEM

RXFNFM

RXFFM

RESERVED

RFSRM

RFSEM

WTSRM

MTDM

STDM

23:21 RESERVED

MALM

BERRM

27:26 RESERVED

MTDWSM

0x0

Description

0: TXFNE interrupt is disabled.

1: TXFNE interrupt is enabled.

TX FIFO full mask. TXFFM enables the interrupt bit TXFF:

0: TXFF interrupt is disabled.

1: TXFF interrupt is enabled.

TX FIFO overrun mask. TXOVRM enables the interrupt bit TXOVR:

0: TXOVR interrupt is disabled.

1: TXOVR interrupt is enabled.

RX FIFO empty mask. RXFEM enables the interrupt bit RXFE:

0: RXFE interrupt is disabled.

1: RXFE interrupt is enabled.

RX FIFO nearly full mask. RXNFM enables the interrupt bit RXNF:

0: RXNF interrupt is disabled.

1: RXNF interrupt is enabled

RX FIFO full mask. RXFFM enables the interrupt bit RXFF:

0: RXFF interrupt is disabled.

1: RXFF interrupt is enabled.

RW RESERVED

Read-from-slave request mask. RFSRM enables the interrupt bit RFSR:

0: RFSR interrupt is disabled.

1: RFSR interrupt is enabled.

Read-from-slave empty mask. RFSEM enables the interrupt bit RFSE:

0: RFSE interrupt is disabled.

1: RFSE interrupt is enabled.

Write-to-slave request mask. WTSRM enables the interrupt bit WTSR:

0: WTSR interrupt is disabled.

1: WTSR interrupt is enabled.

Master transaction done mask. MTDM enables the interrupt bit MTD:

0: MTD interrupt is disabled.

1: MTD interrupt is enabled.

Slave transaction done mask. STDM enables the interrupt bit STD:

0: STDM interrupt is disabled.

1: STDM interrupt is enabled.

RW RESERVED

Master arbitration lost mask. MALM enables the interrupt bit MAL:

0: MAL interrupt is disabled.

1: MAL interrupt is enabled.

Bus error mask. BERRM enables the interrupt bit BERR:

0: BERR interrupt is disabled.

1: BERR interrupt is enabled.

RW RESERVED

Master transaction done without stop mask. MTDWSM enables the interrupt bit MTDWS:

0: MTDWS interrupt is disabled.

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Bit Field name

31:29 RESERVED

Reset

0x0

1: MTDWS interrupt is enabled.

Description

RW RESERVED

Bit Field name

Table 105. I2C - RISR register description: address offset I2CX_BASE_ADDR+0x30

TXFE

TXFNE

TXFF

TXFOVR

RXFE

RXFNF

RXFF

15:7 RESERVED

Reset

0x1

0x0

0x1

0x0

Description

TX FIFO empty. TXFE is set when TX FIFO is empty. This bit is self-cleared by writing in TX FIFO.

0: TX FIFO is not empty.

1: TX FIFO is empty.

TX FIFO nearly empty. TXFNE is set when the number of entries in TX

FIFO is less than or equal to the threshold value programmed in the

I2C_TFTR:THRESHOLD_TX register. It is self-cleared when the threshold level is over the programmed threshold.

0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.

1: Number of entries in TX FIFO less than or equal to the

TFTR:THRESHOLD_TX register.

TX FIFO full. TXFF is set when a full condition occurs in TX FIFO. This bit is self-cleared when the TX FIFO is not full:

0: TX FIFO is not full.

1: TX FIFO is full.

TX FIFO overrun. TXFOVR is set when a write operation in TX FIFO is performed and TX FIFO is full. The application must avoid an overflow condition by a proper data flow control. Anyway in case of overrun, the application shall flush the transmitter (CR:FTX bit to set) because the TX

FIFO content is corrupted (at least one word has been lost in FIFO). This interrupt is cleared by setting the related bit of the ICR register:

0: No overrun condition occurred in TX FIFO.

1: Overrun condition occurred in TX FIFO.

RX FIFO empty. RXFE is set when the RX FIFO is empty. This bit is self-cleared when the slave RX FIFO is not empty:

0: RX FIFO is not empty.

1: RX FIFO is empty.

RX FIFO nearly full. RXFNF is set when the number of entries in RX

FIFO is greater than or equal to the threshold value programmed in the

RFTR:THRESHOLD_RX register. Its self-cleared when the threshold level is under the programmed threshold:

0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.

1: Number of entries in the RX FIFO greater than or equal to the

RFTR:THRESHOLD_RX register.

RX FIFO full. RXFF is set when a full condition occurs in RX FIFO. This bit is self-cleared when the data are read from the RX FIFO.

0: RX FIFO is not full.

1: RX FIFO is full.

R RESERVED page 79/167

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Bit Field name Reset

RFSR

RFSE

WTSR

MTD

STD

23:21 RESERVED

24 MAL

0x0

RW Description

Read-from-slave request. RFSR is set when a read-from-slave

"Slavetransmitter" request is received (I²C slave is addressed) from the

I²C line. On the assertion of this interrupt the TX FIFO is flushed (pending data are cleared) and the CPU shall put the data in TX FIFO. This bit is self-cleared by writing data in FIFO. In case the FIFO is empty before the completion of the read operation, the RISR:RFSE interrupt bit is set.This

interrupt is cleared by setting the related bit of the ICR register.

0: Read-from-slave request has been served.

1: Read-from-slave request is pending.

Read-from-slave empty. RFSE is set when a read-from-slave operation is in progress and TX FIFO is empty. On the assertion of this interrupt, the CPU shall download in TX FIFO the data required for the slave operation. This bit is self-cleared by writing in TX FIFO. At the end of the read-from-slave operation this bit is cleared although the TX FIFO is empty.

0: TX FIFO is not empty.

1: TX FIFO is empty with the read-from-slave operation in progress.

Write-to-slave request. WTSR is set when a write-to-slave operation is received (I2C slave is addressed) from the I2C line. This notification can be used by the application to program the DMA descriptor when required.

This interrupt is cleared by setting the related bit of the ICR register:

0: No write-to-slave request pending.

1: Write-to-slave request is pending.

Master transaction done. MTD is set when a master operation (master write or master read) has been executed after a stop condition. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a master read operation) and clear this interrupt

(transaction acknowledgment). A subsequent master operation can be issued (writing the MCR register) after the clearing of this interrupt. A subsequent slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I²C clock line is stretched low. This interrupt is cleared by setting the related bit of the

ICR register.

0: Master transaction acknowledged.

1: Master transaction done (ready for acknowledgment).

Slave transaction done. STD is set when a slave operation (write-toslave or read-from-slave) has been executed. The application shall read the related transaction status (SR register), the pending data in the

RX FIFO (only for a write-to-slave operation) and clear this interrupt

(transaction acknowledgment). A subsequent slave operation will be notified

(RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I2C clock line will be stretched low. A subsequent master operation can be issued (by writing the MCR register) after clearing this interrupt. This interrupt is cleared by setting the related bit of the ICR register:

0: Slave transaction acknowledged.

1: Slave transaction done (ready for acknowledgment).

R RESERVED

Master arbitration lost. MAL is set when the master loses the arbitration.

The status code word in the SR contains a specific error tag (CAUSE field) for this error condition. A collision occurs when 2 stations transmit simultaneously 2 opposite values on the serial line. The station that is pulling up the line, identifies the collision reading a 0 value on the sda_in signal, stops the transmission, leaves the bus and waits for the idle state (STOP condition received) on the bus line before retrying the same transaction. The station which transmits the first unique zero wins the bus arbitration. This interrupt is cleared by setting the related bit of the ICR register.

0: No master arbitration lost.

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Bit Field name

25 BERR

27:26 RESERVED

28 MTDWS

31:29 RESERVED

Reset

0x0

RW Description

1: Master arbitration lost.

Bus Error. BERR is set when an unexpected Start/Stop condition occurs during a transaction. The related actions are different, depending on the type of operation in progress.The status code word in the SR contains a specific error tag (CAUSE field) for this error condition. This interrupt is cleared by setting the related bit of the ICR register.

0: No bus error detection.

1: Bus error detection.

R RESERVED

Master transaction done without stop. MTDWS is set when a master operation (write or read) has been executed and a stop (MCR:P field) is not programmed. The application shall read the related transaction status (SR register), the pending data in the RX FIFO (only for a master read operation) and clear this interrupt (transaction acknowledgment). A subsequent master operation can be issued (by writing the MCR register) after clearing this interrupt. A subsequent slave operation will be notified

(RISR:WTSR and RISR:RFSR interrupt bits assertion) after clearing this interrupt, meanwhile the I²C clock line will be stretched low. This interrupt is cleared by setting the related bit of the ICR register:

0: Master transaction acknowledged.

1: Master transaction done (ready for acknowledgment) and stop is not applied into the I²C bus.

R RESERVED

Table 106. I2C - MISR register description: address offset I2CX_BASE_ADDR+0x34

Bit Field name

TXFEMIS

TXFNEMIS

TXFFMIS

3 TXFOVRMIS

RXFEMIS

RXFNFMIS

RXFFMIS

Reset

0x0

RW Description

TX FIFO empty masked interrupt status.

0: TX FIFO is not empty.

1: TX FIFO is empty.

TX FIFO nearly empty masked interrupt status.

0: Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX register.

1: Number of entries in TX FIFO less than or equal to the

TFTR:THRESHOLD_TX register.

Tx FIFO full masked interrupt status.

0: TX FIFO is not full.

1: TX FIFO is full.

Tx FIFO overrun masked interrupt status.

0: No overrun condition occurred in TX FIFO.

1: Overrun condition occurred in TX FIFO.

RX FIFO empty masked interrupt status.

0: RX FIFO is not empty.

1: RX FIFO is empty.

RX FIFO nearly full masked interrupt status.

0: Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX register.

1: Number of entries in the RX FIFO greater than or equal to the

RFTR:THRESHOLD_RX register.

R RX FIFO full masked interrupt status.

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Bit Field name

15:7 RESERVED

16 RFSRMIS

17 RFSEMIS

18 WTSRMIS

19 MTDMIS

20 STDMIS

23:21 RESERVED

24 MALMIS

25 BERRMIS

27:26 RESERVED

28 MTDWSMIS

31:29 RESERVED

Reset

0x0

0: RX FIFO is not full.

1: RX FIFO is full.

R RESERVED

Description

Read-from-slave request masked interrupt status.

0: Read-from-slave request has been served.

1: Read-from-slave request is pending.

Read-from-slave empty masked interrupt status.

0: TX FIFO is not empty.

1: TX FIFO is empty with the read-from-slave operation in progress.

Write-to-slave request masked interrupt status.

0: No write-to-slave request pending.

1: Write-to-slave request is pending.

Master transaction done masked interrupt status.

0: Master transaction acknowledged.

1: Master transaction done (ready for acknowledgment).

Slave transaction done masked interrupt status.

0: Slave transaction acknowledged.

1: Slave transaction done (ready for acknowledgment).

R RESERVED

Master arbitration lost masked interrupt status.

0: No master arbitration lost.

1: Master arbitration lost.

Bus error masked interrupt status.

0: No bus error detection.

1: Bus error detection.

R RESERVED

Master transaction done without stop masked interrupt status.

0: Master transaction acknowledged.

1: Master transaction done (ready for acknowledgment) and stop is not applied into the I²C bus.

R RESERVED

Bit

2:0

15:4

Table 107. I2C - ICR register description: address offset I2CX_BASE_ADDR+0x38

Field name

RESERVED

TXFOVRIC

RESERVED

RFSRIC

RFSEIC

Reset

0x0

RW Description

RW RESERVED

Tx FIFO overrun interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

RW RESERVED

Read-from-Slave request interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

RW Read-from-slave empty interrupt clear.

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Bit Field name

WTSRIC

MTDIC

20 STDIC

23:21 RESERVED

24 MALIC

25 BERRIC

27:26 RESERVED

28 MTDWSIC

31:29 RESERVED

Reset

0x0

Description

0: Has no effect.

1: Clears interrupt pending.

Write-to-slave request interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

Master transaction done interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

Slave transaction done interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

RW RESERVED

Master arbitration lost interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

Bus error interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

RW RESERVED

Master transaction done without stop interrupt clear.

0: Has no effect.

1: Clears interrupt pending.

RW RESERVED

Bit Field name

8:0

Table 108. I2C - THDDAT register description: address offset I2CX_BASE_ADDR+0x4C

THDDAT

31:9 RESERVED

Reset

0x14

0x0

Description

Hold time data value. In master or slave mode, when the I2C controller detects a falling edge in the SCL line, the counter, which is loaded by the

THDDAT, is launched. Once the THDDAT value is reached, the data is transferred.

RW RESERVED

Bit

Table 109. I2C - THDSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x50

Field name

8:0 THDSTA_STD

15:9 RESERVED

24:16 THDSTA_FST

31:25 RESERVED

Reset

0xE2

0x0

0x3F

0x0

RW Description

Hold time start condition value for standard mode. When the start condition is asserted, the decimeter loads the value of THDSTA_STD for standard mode, once the THDSTA_STD value is reached, the SCL line asserts low.

RW RESERVED

Hold time start condition value for fast mode. When the start condition is asserted, the decimeter loads the value of THDSTA_FST for fast mode, once the THDSTA_FST value is reached, the SCL line assert slow.

RW RESERVED page 83/167

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Note:

3.11

3.11.1

3.11.2

Note:

3.11.2.1

3.11.2.2

Bit

Table 110. I2C - TSUSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x58

Field name

8:0 TSUSTA_STD

15:9 RESERVED

24:16 TSUSTA_FST

31:25 RESERVED

Reset

0xE2

0x0

0x1D

0x0

RW Description

Setup time start condition value for standard mode. After a non-stop on the SCL line the decimeter loads the value of TSUSTA_STD according to standard mode. Once the counter is expired, the start condition is generated.

RW RESERVED

Set-up time start condition value for fast mode. After a non-stop on the

SCL line the decimeter loads the value of TSUSTA_FST according to fast mode. Once the counter is expired the start condition is generated.

RW RESERVED

All RESERVED fields inside registers must always be written with their default value.

Flash controller

•

Flash controller introduction

The BlueNRG-1 integrates a Flash controller to interface the embedded Flash memory.

Main features are:

• Sector erase and mass erase

160 kbyte Flash memory: 80 pages of 8 rows with 64 words each

Flash programming

Mass read

Enable readout protection

32-bit read access

32-bit write access in single write and 4x32-bit in burst write (reduce programming time by 2)

Flash controller functional description

The BlueNRG-1 embeds up to 160 kB (40960 x 32-bit) of internal Flash memory. A Flash interface implements instruction access and data access based on the AHB protocol. It implements the logic necessary to carry out the

Flash memory operations (Program/Erase) controlled through the Flash registers.

Writing to Flash only allows clearing bits from ‘1’ to ‘0’. This means any write from ‘0’ to ‘1’ implies erasing before performing a write.

Flash memory is composed of 80 pages containing 8 rows of 64 words (80 x 8 x 64 = 40960 words). Each word is

32-bit = 4 bytes long which means 160 kB of Flash.

The address inside the ADDRESS register is built as follows:

•

ADDRESS[15:0] = XADR[9:0] & YADR[5:0] with:

• XADR[9:3] = page address

XADR[2:0] = row address

YADR[5:0] = word address (one word = four bytes)

One specific address can be written only twice between two erase actions even if each writing only clears bits.

The Flash data retention is greater than 10 years at 85 °C. The Flash is rated to have a Flash cycling of 10.000

write/erase cycles.

Reading Flash memory

To read one single word of the flash, just read it as if RAM memory: read the desired flash address and get read data on the bus.

Erasing Flash

The Flash controller allows erasing one page or the full main Flash.

ERASE sequence (erase one page):

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3.11.2.3

3.11.2.4

Write the page address to be erased by writing in the ADDRESS register the following value: a.

ADDRESS[15:9] = XADR[9:3] = page address to erase b.

ADDRESS[8:0] = 9’b0 (row and word addresses at zero).

Write the ERASE command (0x11) in the COMMAND register.

Wait for the CMDSTART flag in the IRQSTAT register (polling mode or interrupt mode) indicating command is taken into account and under execution.

Clear the CMDSTART flag by writing CMDSTART to ‘1’ in the IRQSTAT register.

Wait for the CMDDONE flag in the IRQSTAT register (polling mode or interrupt mode) indicating that the command is completed.

Clear the CMDDONE flag by writing CMDDONE to ‘1’ in the IRQSTAT register.

After this command, the erased page contains only bits set to ‘1’.

MASSERASE sequence (erase completely main flash):

Write the MASSERASE command (0x22) in the COMMAND register.

Wait for the CMDSTART flag in the IRQSTAT register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution.

Clear the CMDSTART flag by writing CMDSTART to ‘1’ in the IRQSTAT register.

Wait for the CMDDONE flag in the IRQSTAT register (polling mode or interrupt mode) indicating that the command is completed.

Clear the CMDDONE flag by writing CMDDONE to ‘1’ in the IRQSTAT register.

After this command, the full main Flash contains only bits set to ‘1’.

Write function examples

The Flash controller allows writing one word (WRITE), up to 4 words (BURSTWRITE) or the full main Flash memory (with a single fixed word).

Note: As a write can only program to ‘0’ on bits already set to ‘1’, it is necessary to erase the page and request that the bits be set to ‘1’ (instead of ‘0’) in order to re-write to ‘0’.

WRITE sequence:

Indicate the location to write by filling the ADDRESS register with the targeted address (page, row and word number)

Write the value to program in the DATA0 register.

Write the WRITE command (0x33) in the COMMAND register.

Wait for the CMDSTART flag in the IRQSTAT register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution.

Clear the CMDSTART flag by writing CMDSTART to ‘1’ in the IRQSTAT register.

Wait for the CMDDONE flag in the IRQSTAT register (polling mode or interrupt mode) indicating that the command is completed.

Clear the CMDDONE flag by writing CMDDONE to ‘1’ in the IRQSTAT register.

BURSTWRITE sequence:

Indicate the location to write by filling the ADDRESS register with the targeted address of the first data to write (page, row and word number). DATA0 will be written and ADDRESS, DATA1 at ADDRESS+1 and so on. (Write the values to program in the DATA0-3 registers. To write less than four words, write 0xFFFFFFFF in the unused DATA1-3 registers.)

Write the BURSTWRITE command (0xCC) in the COMMAND register.

Wait for the CMDSTART flag in the IRQSTAT register (polling mode or interrupt mode) indicating that the command has been taken into account and is under execution.

Clear the CMDSTART flag by writing CMDSTART to ‘1’ in the IRQSTAT register.

Wait for the CMDDONE flag in the IRQSTAT register (polling mode or interrupt mode) indicating that the command is completed.

Clear the CMDDONE flag by writing CMDDONE to ‘1’ in the IRQSTAT register.

Flash readout protection

It is possible to protect flash memory from unwanted access while in debug mode, this is normally used to avoid copy or reverse engineering of a deployed application in the market.

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Flash controller

3.11.2.5

3.11.2.6

3.11.3

If the readout protection mechanism is activated, as soon as Cortex-M0 is halted, any access to Flash memory returns a fixed 0x0 value and generate an AHB error if a debugger tries to read it.

Note that RAM memory debug accesses are also disabled by this lock protection.

Enabling readout protection:

Program a secret 64 bit sequence in the last two word address of the user flash. The secret 64-bit sequence can be anything different from 0xFFFFFFFF, 0xFFFFFFFF.

Disable readout protection:

Perform a mass erase of the user flash.

Flash command list

The valid command values list for the COMMAND register is reported in the table below.

Command name

ERASE

MASSERASE

WRITE

BURSTWRITE

Flash interface timing characteristics

Table 111. Flash commands

Description

Erase page defined by register ADDRESS

Mass erase (Flash is completely erased)

Program one location (defined by registers DATA and ADDRESS)

Burst write operation

Value

0x11

0x22

0x33

0xCC

Table 112. Flash interface timing

Description

Page erase time

Mass erase time

Program time WRITE

Program time BURSTWRITE 1 word (1)

Program time BURSTWRITE 2 words

Program time BURSTWRITE 3 words

Program time BURSTWRITE 4 words

Table 205. Digital I/O specifications

1. Burst write procedure skips the 0xFFFF_FFFF word

Flash controller registers

Flash controller peripheral base address (FLASH_BASE_ADDR) 0x40100000.

Max.

21.5

107

Address offset

0x00

Name RW

COMMAND RW

0x04 CONFIG RW

0x08

0x0C

IRQSTAT

IRQMASK

0x10

0x14

IRQRAW

SIZE

Table 113. FLASH controller registers

Reset

0x00000000

0x0000003F

0x00000000

0x00009FFF

Description

Commands for the module

Configure the wrapper

Flash status interrupt (masked). Refer to the detailed description below.

Mask for interrupts. Refer to the detailed description below.

Status interrupts (unmasked). Refer to the detailed description below.

Indicates the size of the Flash

Unit ms ms

µs

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Address offset

0x18

0x24

0x28

0x2C

0x30

0x40

0x44

0x48

0x4C

Name RW

ADDRESS RW

RESERVED R

RESERVED RW

DATA0

DATA1

DATA2

DATA3

Reset

0x00000000

0xFFFFFFFF

0x0B061515

0x0B156506

0x00000011

0xFFFFFFFF

Description

Address for programming Flash, will auto-increment

RESERVED

Program cycle data

Table 114. FLASH – COMMAND register description: address offset FLASH_BASE_ADDR+0x00

Bit

31:0

Field name

COMMAND

Reset

0x00000000

Description

Command for the module.

Bit

31:4

Table 115. FLASH – CONFIG register description: address offset FLASH_BASE_ADDR+0x04

Field name

RESERVED

REMAP

RESERVED

PREMAP

RESERVED

Reset

RW Description

RW RESERVED

RW Remaps the interrupt vector table in RAM

RW RESERVED

RW Remaps the interrupt vector table in FLASH

RW RESERVED

Table 116. FLASH - IRQSTAT register description: address offset FLASH_BASE_ADDR+0x08

Bit Field name

CMDDONE

CMDSTART

CMDERR

ILLCMD

4 READOK

5 FLNREADY

31:6 RESERVED

Reset

0x0

RW Description

RW Command is done. 1: clear the interrupt pending bit.

RW Command is started.1: clear the interrupt pending bit.

RW Command written while BUSY. 1: clear the interrupt pending bit.

RW Illegal command written. 1: clear the interrupt pending bit.

RW Mass read was OK. 1: clear the interrupt pending bit.

RW Flash not ready (sleep). 1: clear the interrupt pending bit.

RW RESERVED

Bit

Table 117. FLASH - IRQMASK register description: address offset FLASH_BASE_ADDR+0x0C

Field name

CMDDONE

CMDSTART

CMDERR

ILLCMD

READOK

Reset

0x1

RW Command is done.

Description

RW Command is started.

RW Command written while BUSY

RW Illegal command written

RW Mass read was OK.

page 87/167

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Flash controller

Bit

31:6

Field name

FLNREADY

RESERVED

Reset

0x1

0x0

RW Flash not ready (sleep).

RW RESERVED

Description

Bit

31:6

Table 118. FLASH - IRQRAW register description: address offset FLASH_BASE_ADDR+0x10

Field name

CMDDONE

CMDSTART

CMDERR

ILLCMD

READOK

FLNREADY

RESERVED

Reset

0x0

RW Command is done.

Description

RW Command is started.

RW Command written while BUSY

RW Illegal command written

RW Mass read was OK.

RW Flash not ready (sleep).

RW RESERVED

Bit

15:0

31:16

Table 119. FLASH – SIZE register description: address offset FLASH_BASE_ADDR+0x14

Field name

SIZE

RESERVED

Reset

0x9FFF

0x0000

Description

Indicates the size of the flash. 0x9FFF: 160 kB of flash

RESERVED

Bit

31:0

Table 120. FLASH – ADDRESS register description: address offset FLASH_BASE_ADDR+0x18

Field name

ADDRESS

Reset

0x00000000

Description

Address for programming flash, auto-increment.

Bit

31:0

Table 121. FLASH – DATA0 register description: address offset FLASH_BASE_ADDR+0x40

Field name

DATA0

Reset

0xFFFFFFFF

Description

Program cycle data.

Bit

31:0

Table 122. FLASH – DATA1 register description: address offset FLASH_BASE_ADDR+0x44

Field name

DATA1

Reset

0xFFFFFFFF

Description

Program cycle data.

Bit

31:0

Table 123. FLASH – DATA2 register description: address offset FLASH_BASE_ADDR+0x48

Field name

DATA2

Reset

0xFFFFFFFF

Description

Program cycle data.

Bit

31:0

Table 124. FLASH – DATA3 register description: address offset FLASH_BASE_ADDR+0x4C

Field name

DATA3

Reset

0xFFFFFFFF

Description

Program cycle data.

All RESERVED fields inside registers must always be written with their default value.

DS11481 - Rev 10 page 88/167

BlueNRG-1

GPIO

3.12

3.12.1

3.12.2

3.12.2.1

GPIO

Introduction

The BlueNRG-1 offers 14 GPIOs (WCSP34 package) or 15 GPIOs (QFN32 package).

•

The programmable I/O pin can be configured for operating as:

• Programmable GPIOs

•

Peripheral input or output line of standard communication interfaces

PDM processor data/clock

2 PWM sources (PWM0 and PWM1 independently configurable) and 4 PWM output pins (IO2, IO3, IO4 and

IO5)

5 wake-up sources from standby and sleep mode

Each I/O can generate an interrupt independently to the selected mode. Interrupts are generated depending on a level or edge

Functional description

In the table below is reported the GPIO configuration table where at each IO pin is associated the related functions.

Table 125. IO functional map

Pin name

IO7

IO8

IO9

IO10

IO11

IO12

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO13

IO14

(1)

GPIO mode "000"

I/O

Type

I/O

Signal

GPIO 0

GPIO 1

GPIO 2

GPIO 3

GPIO 4

GPIO 5

GPIO 6

GPIO 7

GPIO 8

GPIO 9

GPIO 10

GPIO 11

GPI 12 (2)

GPI 13

(2)

GPIO 14

Mode serial1 '001"

Type

I/O

Signal

UART_CTS

UART_RTS

PWM0

PWM1

UART_RXD

UART_TXD

UART_RTS

UART_CTS

UART_TXD

SWCLK

SWDIO

UART_RXD

UART_CTS

I2C1_CLK

1. All the I2C pins require external pull-up

2. IO12 and IO13 can only be general purpose input pins (not output).

Mode serial0 ‘100’

I/O

Type

I/O

Signal

SPI_CLK

SPI_CS1

SPI_OUT

SPI_IN

I2C2_CLK

I2C2_DAT

I2C2_CLK

I2C2_DAT

SPI_CLK

SPI_IN

SPI_OUT

SPI_CS1

I2C1_CLK

I/O

I2C1_DAT

SPI_CLK

Mode serial2 '101'

Type

Signal

PWM0

PWM1

PDM_DATA

PDM_CLK

PDM_DATA

PDM_CLK

GPIO interrupts

Each IO in GPIO mode can be used as interrupt source from external signal. The trigger event is both edge and level sensitive according to configuration. All the configuration are reported in table below.

DS11481 - Rev 10 page 89/167

BlueNRG-1

GPIO

3.12.2.2

Configuration

IOIS

IOIBE

IOIEV

Falling edge

Table 126. GPIO interrupt modes

Rising edge

Interrupt mode

Both edges

Low level

High level

The interrupt is enabled by writing 1 in the MIS register, in the position with same number of the IO desired. Once the interrupt occurs, it can be cleared by writing 1 in the IC register. All the interrupts drive a single interrupt signal of the NVIC.

Each time the status of an IO matches its interrupt setting expressed by the registers IS, IBE and IEV, then the correspondent bit in the RIS register is set. Before enabling the correspondent interrupt mask (register IE), it is recommended to clear the RIS register by writing the correspondent bit of the register IC.

GPIO characteristics

By default all the GPIO pins are configured as input with related pull-up or pull-down enabled in order to have a specific reference voltage level.

Name

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

IO8

IO9

IO10

IO11

IO12

IO13

IO14

Type

I/O

1. See

Table 127. Pin characteristics

Buffer strength (1)

Low / high drive

10 mA (2)

Low / high drive

Pull-up / pulldown availability

Pull-down

Pull- up

Pull-up

No pull

Pull-down

Default state after reset

GPIO input mode, pull-down

Serial1 mode

(SWCLK), pull-up

High impedance state

GPIO input mode with internal pull-up

Serial1 mode

(SWDIO), pull-up

GPIO input mode, pull-up

GPIO input mode with internal pull-up

GPIO input mode GPIO input mode

State during low power modes

High impedance state

GPIO input mode GPIO input mode

GPIO input mode, pull-down

High impedance state

DS11481 - Rev 10 page 90/167

BlueNRG-1

GPIO

Note:

3.12.3

2. Drive strength for I 2 C bus.

•

If the user needs pull-up or pull-down capability to drive the GPIO line, this must be done through an external resistor.

All the IOs are in high impedance under reset. In low power modes (sleep and standby) the IOs are configured as follows:

IO0 to IO8 and IO14 are in high impedance state

IO9, IO10, IO11 are in input state with internal pull

IO12 , IO13 are in input state no pull

When the device is in low power mode, in order to avoid leakage, IO12 and IO13 need to be driven to logic level high or low. If these pins are no used, it is recommended to pull them down through a pull-down resistor of 10 kΩ.

As DIO14 is internally bound with the ANATEST0 signal, a short positive pulse of about 75 μs is generated at the device reset.

GPIO registers

GPIO peripheral base address (GPIO_BASE_ADDR) 0x40000000.

Address offset

Name RW

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x24

0x28

DATA RW

OEN RW

PE RW

DS RW

IBE RW

IEV RW

MIS

Reset

0x00000000

0x03FFFFFF

0x00000000

Table 128. GPIO registers

Description

IO0 to IO14 data value.

Writing to a bit drives the written value on the corresponding IO when it is configured in GPIO mode and the output direction. Reading a bit indicates the pin value

GPIO output enable register (1 bit per GPIO)

0: input mode

1: output mode

Pull enable (1 bit per IO)

0: pull disabled

1: pull enabled

IO driver strength (1 bit per IO)

0: low drive

1: high drive

Interrupt sense register (1 bit per IO)

0: edge detection

1: level detection

Interrupt edge register (1 bit per IO)

0: single edge

1: both edges

Interrupt event register (1 bit per IO)

0: falling edge or low level

1: rising edge or high level

Interrupt mask register (1 bit per IO)

0: Interrupt disabled

1: Interrupt enabled

Masked interrupt status register (1 bit per IO)

Interrupt clear register (1 bit per IO)

DS11481 - Rev 10 page 91/167

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BlueNRG-1

GPIO

Address offset

Name RW

0x2C

0x30

0x3C

0x40

0x44

MODE0

MODE1

DATS RW

DATC RW

MFTX RW

Reset

0x00000000

0x00000110

0x00000000

Description

0: no effect

1: clear interrupt

Select mode for IO0 to IO7.

000b: GPIO mode

001b: Serial1 mode

100b: Serial0 mode

101b: Serial2 mode

Refer to the detailed description below.

Select mode for IO8 to IO14

000b: GPIO mode

001b: Serial1 mode

100b: Serial0 mode

101b: Serial2 mode

Refer to the detailed description below.

Set some bits of DATA when in GPIO mode without affecting the others (1 bit per IO).

0: no effect.

1: set at 1 the bit

Clear some bits of DATA when in GPIO mode without affecting the others

(1 bit per IO)

0: no effect.

1: clear at 0 the bit

Select the IO to be used as capture input for the MFTX timers. Refer to the detailed description below.

Table 129. GPIO – DATA register description: address offset GPIO_BASE_ADDR+0x00

Bit Field name

31:0 DATA

Reset RW Description

0x00000000 RW

IO0 to IO14 data value.

Writing to a bit drives the written value on the corresponding IO when it is configured in

GPIO mode and the output direction. Reading a bit indicates the pin value.

Bit

31:0

Table 130. GPIO – OEN register description: address offset GPIO_BASE_ADDR+0x04

Field name

OEN

Reset

0x00000000

Description

•

GPIO output enable register (1 bit per GPIO).

0: Input mode

1: Output mode

Bit

31:0

Table 131. GPIO – PE register description: address offset GPIO_BASE_ADDR+0x08

Field name

Reset

0x03FFFFFF

Description

•

Pull enable (1 bit per IO).

0: Pull disabled.

1: Pull enabled.

page 92/167

DS11481 - Rev 10

BlueNRG-1

GPIO

Bit

31:0

Table 132. GPIO – DS register description: address offset GPIO_BASE_ADDR+0x0C

Field name

Reset

0x00000000

Description

•

IO driver strength (1 bit per IO).

0: Low drive

1: High drive

Bit

31:0

Table 133. GPIO – IS register description: address offset GPIO_BASE_ADDR+0x10

Field name

Reset

0x00000000

Description

•

Interrupt sense register (1 bit per IO).

0: Edge detection.

1: Level detection.

Bit

31:0

Table 134. GPIO – IBE register description: address offset GPIO_BASE_ADDR+0x14

Field name

IBE

Reset

0x00000000

Description

•

Interrupt edge register (1 bit per IO).

0: Single edge

1: Both edges

Bit

31:0

Table 135. GPIO – IEV register description: address offset GPIO_BASE_ADDR+0x18

Field name

IEV

Reset

0x00000000

Description

•

Interrupt event register (1 bit per IO).

0: Falling edge or low level.

1: Rising edge or high level.

Bit

31:0

Table 136. GPIO – IE register description: address offset GPIO_BASE_ADDR+0x1C

Field name

Reset

0x00000000

Description

•

Interrupt mask register (1 bit per IO).

0: Interrupt disabled

1: Interrupt enabled

Bit

31:0

Table 137. GPIO – MIS register description: address offset GPIO_BASE_ADDR+0x24

Field name

MIS

Reset

0x00000000

RW Description

R Masked interrupt status register (1 bit per IO).

Bit

31:0

Table 138. GPIO – IC register description: address offset GPIO_BASE_ADDR+0x28

Field name

Reset

0x00000000

Description

•

Interrupt clear register (1 bit per IO).

0: No effect

1: Clear interrupt page 93/167

DS11481 - Rev 10

BlueNRG-1

GPIO

18:16

22:20

26:24

30:28

10:8

14:12

Bit

2:0

6:4

Table 139. GPIO - MODE0 register description: address offset GPIO_BASE_ADDR+0x2C

Field name

IO0

RESERVED

IO1

RESERVED

IO2

RESERVED

IO3

RESERVED

IO4

RESERVED

IO5

RESERVED

IO6

RESERVED

IO7

RESERVED

0x0

Reset

0x0

RW IO0 mode

RW RESERVED

RW IO1 mode

RW RESERVED

RW IO2 mode

RW RESERVED

RW IO3 mode

RW RESERVED

RW IO4 mode

RW RESERVED

RW IO5 mode

RW RESERVED

RW IO6 mode

RW RESERVED

RW IO7 mode

RW RESERVED

Description

14:12

18:16

Bit

2:0

6:4

10:8

22:20

26:24

31:27

Table 140. GPIO – MODE1 register description: address offset GPIO_BASE_ADDR+0x30

Field name

IO8

RESERVED

IO9

RESERVED

IO10

RESERVED

IO11

RESERVED

IO12

RESERVED

IO13

RESERVED

IO14

RESERVED

0x0

Reset

0x0

0x1

0x0

0x1

0x0

RW IO8 mode

RW RESERVED

RW IO9 mode

RW RESERVED

RW IO10 mode

RW RESERVED

RW IO11 mode

RW RESERVED

RW IO12 mode

RW RESERVED

RW IO13 mode

RW RESERVED

RW IO14 mode

RW RESERVED

Description

Table 141. GPIO – DATS register description: address offset GPIO_BASE_ADDR+0x3C

Bit Field name

31:0 DATS

Reset RW Description

0x00000000 RW

•

Set some bits of DATA when in GPIO mode without affecting the others (1 bit per IO).

0: No effect

1: Set at 1 the bit page 94/167

BlueNRG-1

MFT

Note:

3.13

3.13.1

Table 142. GPIO – DATC register description: address offset GPIO_BASE_ADDR+0x40

Bit Field name

31:0 DATC

Reset RW Description

0x00000000 RW

•

Clear some bits of DATA when in GPIO mode without affecting the others (1 bit per

IO).

0: No effect

1: Clear at 0 the bit

Bit

Table 143. GPIO - MFTX register description: address offset GPIO_BASE_ADDR+0x44

Field name

7:0 MFT1_TIMER_A

15:8 MFT1_TIMER_B

23:16 MFT2_TIMER_A

31:24 MFT2_TIMER_B

Reset

0x0

Description

•

Selects which IO must be used as input pin TnA for the MFT1 peripheral. Mode 2 and mode 4 only.

0x00: IO0

0x01: IO1

0x02: IO2

...

0x0E: IO14

•

Selects which IO must be used as input pin TnB for the MFT1 peripheral. Mode 2 and mode 4 only.

0x00: IO0

0x01: IO1

0x02: IO2

...

0x0E: IO14

•

Selects which IO must be used as input pin TnA for the MFT2 peripheral. Mode 2 and mode 4 only.

0x00: IO0

0x01: IO1

0x02: IO2

...

0x0E: IO14

•

Selects which IO must be used as input pin TnB for the MFT2 peripheral. Mode 2 and mode 4 only.

0x00: IO0

0x01: IO1

0x02: IO2

...

0x0E: IO14

All RESERVED fields inside registers must always be written with their default value.

MFT

•

MFT introduction

The BlueNRG-1 integrates two multi functions timers (MFT).

Main features are:

• Two 16-bit programmable timer/counters.

Two 16-bit reload/capture registers that function either as reload registers or as capture registers, depending on the mode of operation.

An 8-bit fully programmable clock prescaler.

DS11481 - Rev 10 page 95/167

BlueNRG-1

MFT

3.13.2

•

Clock source selectors that allow each counter to operate in:

– Pulse-accumulate mode

– External-event mode

– System clock with configurable prescaler

Two I/O pins (TnA and TnB) with programmable edge detection that operate as:

– Capture and preset inputs

– External event (clock) inputs

– PWM outputs

Two interrupts, one for each counter, that can be triggered by a:

– Timer underflow

– Timer reload

– Input capture

– Pulse train for generation of single or multiple PWM pulses.

MFT functional description

The MFT can be configured in five different modes. At each mode is associated a particular function for the two timers both for counter and reload registers as reported in

Table 144. MFT modes

Mode

Description

PWM and system timer or external event counter

PWM pulse train

Dual-input capture and system timer

Dual independent timer

Single-input capture and single timer

Timer Counter 1

(TnCNT1)

Counter for PWM

Capture A and B time base

Time base for first timer

Table 144. MFT modes

Reload / capture A

(TnCRA)

Auto reload A = PWM time

Capture Timer/Counter 1 value upon TnA event

Reload register for Timer/

Counter 1

Reload register for Timer/

Counter 1

Reload / Capture B

(TnCRB)

Auto reload B = PWM time 2

Auto reload B= PWM time 2

Capture Timer/Counter 1 value upon TnB event

Reload register for Timer/

Counter 2

Capture Timer/Counter 1 value upon TnB event

Timer Counter 2

(TnCNT2)

System time or external event

Pulse counter

System timer

Time base for second timer

Capture B time base

3.13.2.1

MFT mode 1: processor-independent PWM

In mode 1, the Timer/Counter 1 (register TnCNT1) can be used to generate a PWM signal on an output pin of the device. In this mode, the PWM output can emulate a clock signal with customized duty-cycle. Indeed, the

TnCNT1 register is alternatively reloaded with the values in TnCRA and TnCRB registers. The initial value of the

PWM output signal can be selected by software to be either high or low thanks to the TnAOUT bit in TnMCTRL register. This bit impact, which reloads value, is used for high level and low level of the PWM signal as shown in

Figure 16. PWM signal on TnA pin

below.

DS11481 - Rev 10 page 96/167

DS11481 - Rev 10

BlueNRG-1

MFT

Figure 15. PWM signal on TnA pin

TnCRA TnCRA

TnMCTRL TnAOUT bit = 0

TnCNT1 TnCRB TnCRB

TnMCTRL TnAOUT bit = 1

TnCRA TnCRA

When started, the first time the Timer/Counter 1 starts with preprogrammed value in the register TnCNT1 and count down at the clock rate selected by the Timer/Counter 1 clock selector (TnCKC register). When an underflow occurs, the TnCNT1 register is reloaded alternatively with TnCRA and TnCRB registers (in this order) and counting proceeds downward from the loaded value.

Any time the counter is stopped by choosing "no-clock" in the TnCKC register, it obtains its first reload value after it has been started again from the TnCRA register. Each time the counter is stopped and then restarted, it obtains its first reload value from the TnCRA register. This is true whether the timer is restarted upon reset, after entering mode 1 from another mode, or after stopping and restarting the clock with the TnCKC register.

The mode 1 is selected in the TnMDSEL field of TnMCTRL register

In figure below the block diagram related to the MFT mode 1.

Figure 16. MFT mode 1 block diagram

Timer 1 clock

Reload A = TnCRA underflow

Timer/Counter 1

TnCNT1 underflow

Reload B = TnCRB

TnAPND

TnAIEN

TnAEN

TnBIEN

TnBPND

Timer

Interrupt A

TnA

Timer

Interrupt A

Timer 2 clock

Timer/Counter 2

TnCNT2

Timer

Interrupt B

TnDIEN

TnDPND

Clock selector

TnB

In this mode, the timer toggles the TnA output upon underflow, which is connected to PWMx pin of the device.

This generates a clock signal on TnA with the width and duty cycle controlled by the values stored in the TnCRA and TnCRB registers.

This is a "processor-independent" PWM clock because once the timer is set up, no more interaction is required

from the software and the CPU in order to generate a continuous PWM signal. Refer to Section 3.13.2.6 Timer

IO functions for additional details.

The timer can generate separate interrupts upon reload from TnCRA and TnCRB. The TnAPND or TnBPND flags, which are set by the hardware upon occurrence of a timer reload, indicate which interrupt has occurred.

Refer to

for detailed information.

In this mode, the Timer/Counter 2 can be used as a simple system timer or as an external-event counter.

page 97/167

BlueNRG-1

MFT

3.13.2.2

The Timer/Counter 2 counts down with the clock selected by Timer/Counter 2 clock selector (TnCKC register), and can be configured to generate an interrupt upon underflow if enabled by the TnDIEN bit.

The interrupts can be enabled or disabled by software.

MFT mode 1a: PWM pulse-train mode

The mode 1a is used to output a PWM signal thanks to the Timer/Counter 1 as for mode 1, but only in a time window defined by the Timer/Counter 2 (TnCNT2). Indeed, the Timer/Counter 2 is used to specify the number of pulses to output on the TnA pin.

The mode 1a corresponds to the mode 1 selected in the TnMDSEL field of TnMCTRL register with in addition the

TnPTEN bit set always in the TnMCTRL register. In mode 1a, the Timer/Counter 1 (TnCNT1 register) alternatively is reloaded by TnCRA and TnCRB registers after starting from the value in the TnCNT1 register as for the mode 1 and toggles the TnA output connected to PWMx GPIO each time an underflow occurs. In parallel, a trigger pulse is sent to the Timer/Counter 2 (TnCNT2 register), decrementing it by one. If the TnCNT2 register has reached the underflow condition and the end-of-pulse condition is detected by the trigger logic as well, the clock of the

Timer/Counter 1 is disabled immediately.

The figure below shows the block diagram related to the MFT mode 1a.

Figure 17. MFT mode 1a block diagram

Note:

Timer 1 clock

Reload A = TnCRA underflow

Timer/Counter 1

TnCNT1 underflow

Reload B = TnCRB underflow

Timer/Counter 2

TnCNT2

TnPTSE

TnPTET

TnAPND

TnAIEN

TnAEN

TnBIEN

TnBPND

Timer

Interrupt A

TnA

Timer

Interrupt A

TnDIEN

TnDPND

Timer

Interrupt B

TnB

In mode 1a, Timer/Counter 2 behaves differently from the way it behaves in the other modes. If an underflow condition occurs, the counter is preset to 0x0000 and not 0xFFFF.

The TnCNT1 register starts to count:

• either on an external event on TnB input,

• or by software if the enable TnPTSE bit has been set by setting the TnPTET bit.

The start of count request through TnPTET bit setting when software trigger option is chosen must be done after the MFT is enabled (TnEN bit in TnMCTRL register).

Any time the counter is stopped by choosing "no-clock" by the Timer/Counter 1 clock selector (TnCKC register), it obtains its first reload value after it has been started again from the TnCRA register. Upon reset, the MFT is disabled. Every time this mode starts, the first reload is from register TnCRA. Once the underflow condition for

TnCNT2 has been reached, TnCNT2 must be initialized again by the application. It is not reloaded by any reload register.

DS11481 - Rev 10 page 98/167

BlueNRG-1

MFT

3.13.2.3

Note:

Timer/Counter 2 can be configured to generate an interrupt upon underflow if enabled by the TnDIEN bit. Refer to

output signal can be selected by software to be either high or low. Refer to Section 3.13.2.6 Timer IO functions

for additional details.

In pulse-train mode, the value of TnCNT2 register specifies the number of pulses to be generated, plus one additional pulse (TnCNT2+1 number of pulses).

In pulse-train mode, the trigger logic uses events on TnB to enable the Timer/Counter 1 clock. This function has to be enabled by setting the TnPTSE bit to 0.

The TnB pin can be configured to sense either rising or falling edges.

The Timer/Counter 1 can be configured to toggle the TnA output bit upon underflow. This results in the generation of a pulse signal on TnA, with the width and duty cycle controlled by the values stored in the TnCRA and TnCRB registers. This is a processor-independent PWM signal because once the timer is set up, no more interactions are required from the software or the CPU in order to generate other PWM pulses. The initial value of the PWM

for additional details.

The timer can be configured to generate separate interrupts upon reload from TnCRA and TnCRB. The TnAPND or TnBPND flags, which are set by the hardware upon occurrence of a timer reload, indicate which interrupt has occurred. The interrupts can be enabled or disabled under software control. Refer to

Figure 19. MFT mode 2 block diagram below the block diagram related to the MFT mode 2.

for detailed information.

MFT mode 2: dual-input capture mode

The mode 2 is used to capture transitions on two selected input pads of the device. The Timer/Counter1 can be used to manage the dual-capture feature as follows:

• A transition on input pad connected to the TnA pin of the MFT generates a transfer of TnCNT1 register value in TnCRA register.

• A transition on input pad connected to the TnB pin of the MFT generates a transfer of TnCNT1 register value in TnCRB register.

The Timer/Counter2 can be used:

• As a system counter: to count down at the rate of the selected clock.

The device input pad selection is done using the register MFTX of the GPIO peripheral.

The transition edge to capture has to be defined in TnAEDG and TnBEDG bits of the TnMCTRL register.

The TnA and TnB inputs can be configured to perform a counter preset to 0xFFFF upon reception of a valid capture event using TnAEN and TnBEN bits in TnMCTRL register. In this case, the current value of the counter is transferred to the corresponding capture register and then the counter is preset to 0xFFFF. Using this approach directly allows the software to determine the on-time, off-time, or period of an external signal, while reducing CPU overhead.

DS11481 - Rev 10 page 99/167

BlueNRG-1

MFT

3.13.2.4

Figure 18. MFT mode 2 block diagram

TnAIEN

TnAPND

Timer

Interrupt A

Timer 1 clock

Capture A TnCRA

Timer/Counter 1

TnCNT1 preset

TnAEN underflow preset

TnBEN

Capture B TnCRB

TnCPND

TnCIEN

Timer

Interrupt A

TnA

TnB

TnBPND

Timer

Interrupt A

TnBIEN

Timer 2 clock

Timer/Counter 2

TnCNT2 underflow Timer

Interrupt B

TnDIEN

TnDPND

The input signal on TnA and TnB must have a pulse width equal to or greater than one system clock cycle. The value captured in the TnCRA register at different times reflects the elapsed time between transitions on the TnA pin. The same is true for the TnCRB register and TnB pin. Each input pin can be configured to sense either positive edge or negative edge transitions.

The timer can be configured to generate interrupts on reception of a transition on either TnA or TnB, which can be enabled or disabled separately by the TnAIEN and TnBIEN bits. An underflow of TnCNT1 can generate an interrupt if enabled by the TnCIEN bit. All three interrupts have individual pending flags associated with them. See

Section 3.13.2.8 Timer interrupts for further details.

The Timer/Counter 2 can be used as a simple system timer in this mode of operation. The TnCNT2 register counts down with the clock selected by the Timer/Counter 2 clock selector (TnCKC register), and can be configured to generate an interrupt upon underflow if enabled by the TnDIEN bit. See

for detailed information.

The Timer/Counter 1 cannot operate in the pulse-accumulate or external-event counter modes, since the TnB pin is used as a capture input. Selecting either of these modes for the Timer/Counter 1 causes the TnCNT1 register to be stopped. However, all available clock source modes may be selected for the Timer/Counter 2. Thus, it is possible to determine the number of capture events on TnB or the elapsed time between capture events on TnB by using the Timer/Counter 2.

•

MFT mode 3: dual independent timer/counter mode

This mode 3 allows using the Timer/ Counter 1 and Timer/ Counter 2 separately.

The Timer/ Counter1 can be used:

•

As a system counter: to count down at the rate of the selected clock.

To generate a 50% duty-cycle clock signal on TnA pin connected to the PWMx pin of the device (the

TnCNT1 register is reloaded with the value of the TnCRA register on underflow event).

To be an event counter using TnB pin as an external event or pulse-accumulate input.

The Timer/Counter 2 can be used:

• As a system counter: to count down at the rate of the selected clock.

• To be an event counter using TnB pin as an external event or pulse-accumulate input.

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3.13.2.5

Note:

In figure below the block diagram related to the MFT mode 3.

Figure 19. MFT mode 3 block diagram

Timer 1 clock

Reload A TnCRA underflow

Timer/Counter 1

TnCNT1

TnAPND

TnAIEN

TnAEN

Timer

Interrupt A

TnA

Timer 2 clock

Reload B TnCRB underflow

Timer/Counter 2

TnCNT2

Clock selector

TnDIEN

TnDPND

Timer

Interrupt B

TnB

In mode 3, the Timer/Counter is configured to operate as a dual independent system timer or dual external-event counter. In addition, the Timer/Counter 1 can generate a 50% duty cycle PWM signal on the TnA pin. The TnB pin can be used as an external-event input or pulse-accumulate input, and serve as the clock source to either

Timer/Counter 1 or Timer/Counter 2. Both counters can also be operated from the prescaled system clock.

The Timer/Counter 1 counts down at the rate of the selected clock. Upon underflow, TnCNT1 register is reloaded from the TnCRA register and counting proceeds. If enabled, the TnA pin toggles upon underflow of the TnCNT1 register. The initial value of the TnA output can be selected by software to be either high or low. See

for additional details.

In addition, the TnAPND interrupt-pending flag is set, and a timer interrupt A is generated if the TnAIEN bit is set.

See

for detailed information.

Since TnA toggles upon every underflow, a 50% duty-cycle PWM signal can be generated on TnA without requiring any interaction of the software or the CPU.

The Timer/Counter 2 counts down at the rate of the selected clock. Upon every underflow of the TnCNT2 register, the value contained in the TnCRB register is loaded into TnCNT2 and counting proceeds downward from that value.

In addition, the TnDPND interrupt-pending flag is set and a timer interrupt B is generated if the TnDIEN bit is set.

See

for detailed information.

MFT mode 4: input-capture plus timer mode

This mode 4 is combination of mode 3 and mode 2.

The Timer/Counter1 can be used:

• As a system counter: to count down at the rate of the selected clock.

• To generate a 50% duty-cycle clock signal on TnA pin connected to the PWMx pin of the device (the

TnCNT1 register is reloaded with the value of the TnCRA register on underflow event).

The Timer/Counter 2 can be used:

• As a system counter: to count down at the rate of the selected clock.

• A transition on input pad connected to TnB pin of the MFT generates a transfer of TnCNT2 register value in

TnCRB register.

The device input pad selection is done using the register MFTX of the GPIO peripheral.

The transition edge to capture has to be defined in TnBEDG bit of the TnMCTRL register. The TnB input can be configured to perform a counter preset to 0xFFFF upon reception of a valid capture event using TnBEN bit in

TnMCTRL register.

In figure below the block diagram related to the MFT mode 4.

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3.13.2.6

Timer 1 clock

Timer 2 clock

Figure 20. MFT mode 4 block diagram

TnAPND

Reload A TnCRA underflow

Timer/Counter 1

TnCNT1

TnAIEN

TnAEN

Timer

Interrupt A

TnA

Timer

Interrupt A

TnBIEN

TnBPND

TnB Capture B TnCRB

Timer/Counter 2

TnCNT2 preset

TnBEN TnDPND

Timer

Interrupt B

TnDIEN

This mode is a combination of mode 3 and mode 2, and makes it possible to operate Timer/Counter 2 as a single input-capture timer while the Timer/Counter 1 can be used as a system timer as described above.

The Timer/Counter 1 starts counting down once a clock has been enabled. Upon underflow, the TnCNT1 register is reloaded from the TnCRA register, and counting proceeds downward from that value. If enabled, the TnA pin toggles upon every underflow of the TnCNT1 register. The initial value of the TnA output signal can be selected by software to be either high or low. See

for additional details.

In addition, the TnAPND interrupt-pending flag is set and a timer interrupt A is generated if the TnAIEN bit is set.

See

also generate a timer interrupt B if enabled. See Section 3.13.2.8 Timer interrupts

for additional details.

Since TnA toggles upon every underflow, a 50% duty-cycle PWM signal can be generated on TnA without requiring any interaction with the software or the CPU.

The Timer/Counter 2 starts counting down once a clock has been enabled. When a transition is received on

TnB, the value contained in the TnCNT2 register is transferred to TnCRB register, and the interrupt-pending flag

TnBPND is set. A timer interrupt A is generated if enabled. The software can enable a preset of the counter to

0xFFFF upon detection of a transition on TnB. In this case, the current value of the TnCNT2 register is transferred to TnCRB register, followed by a preset of the counter to 0xFFFF. TnCNT2 starts counting downwards from

0xFFFF until the next transition is received on TnB, which causes the procedure of capture and preset to be repeated. The underflow of the TnCNT2 register causes the TnDPND interrupt-pending flag to be set, and can

for detailed information.

The input signal on TnB must have a pulse width equal to or greater than one system clock cycle. TnB can be configured to sense either rising or falling edges. The Timer/Counter 2 cannot operate in the pulse-accumulate or external-event counter modes since the TnB input is used as a capture input. Selecting either of these modes for the Timer/Counter 2 causes the TnCNT2 register to be stopped.

However, all available clock source modes may be selected for the Timer/Counter 1. Thus using the TnCNT1 register, it is possible to determine the number of capture events on TnB, or the elapsed time between capture events on TnB.

Timer IO functions

There are two pins associated with each instance of the MFTX. The pins are called TnA and TnB. The functionality of TnA and TnB depends on the mode of operation and the value of the TnAEN and TnBEN bits.

Table 145. MFT IO functions

shows the function of TnA and TnB for various modes of operation. Note that if TnA functions as a PWM output, TnAOUT defines the initial and present value of TnA. For example, if the user wishes to start with TnA high, TnAOUT needs to be set before enabling the timer clock.

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Table 145. MFT IO functions

Pin

TnAEN

TnBEN

Mode 1

PWM and counter

Mode 1a

PWM pulse train

Mode 2

Dual-input capture and counter

TnAEN = 0

TnBEN = X

TnA

TnAEN = 1

TnBEN = X

No output

Toggle output on underflow of TnCNT1

TnAEN = X

TnBEN = 0

TnB

TnAEN = X

TnBEN = 1

External event or pulse accumulate input

No output

Capture TnCNT1 into

TnCRA

Toggle output on underflow of TnCNT1

Capture TnCNT1 into

TnCRA and preset

TnCNT1

External event if

TnPTSE = 0

External event if

TnPTSE = 0

Capture TnCNT1 into

TnCRB

Capture TnCNT1 into

TnCRA and preset

TnCNT1

Mode 3

Dual independent counter

No output toggle

Toggle output on underflow of TnCNT1

Mode 4

Input capture plus timer

No output toggle

Toggle output on underflow of TnCNT1

External event or pulse accumulate input

Capture TnCNT2 into

TnCRB

Capture TnCNT2 into

TnCRB and preset

TnCNT2

3.13.2.7

3.13.2.8

•

IO configuration linked to MFT timers

The MFT timers can be connected to the GPIOs for the following features:

Input signal used to trigger the timer in capture mode.

Output signal when a PWM mode is used

In capture mode, the timer waits for an external IO event to start counting. The chosen IO for capture is programmed through the register MFTX of the GPIO peripheral. This register allows configuring input capture IO for Timer/Counter 1 and Timer/Counter 2 of both MFT1 and MFT2, depending on which timer(s) are configured in capture mode.

In PWM mode, the signal is output on PWM0 IO for MFT1 and PWM1 for MFT2. Those IOs are available at different GPIOs thanks to alternate option. So to output the chosen PWM signal, it is necessary to configure the

IO with the dedicated mode.

Timer interrupts

The MFT has four interrupt sources, which are mapped to two different system interrupts. All sources have a pending flag associated with them, and can be enabled or disabled by software. The pending flags are named

TnXPND, where n denotes the instance of the module, and X represents a letter from A to D. An interrupt enable flag (TnXIEN) is associated with each interrupt-pending flag. Interrupt sources A, B and C can each generate a timer interrupt MFT1A for MFT1 and MFT2A for MFT2, whereas interrupt source D can generate a timer interrupt

MFT1B for MFT1 and MFT2B for MFT2. Not all interrupt sources are available in all modes.

Table 146. MFT interrupt functions

shows which events can trigger an interrupt in which mode of operation.

MFT interrupt

Timer interrupt A

(MFT1A, MFT2A)

Timer interrupt B

(MFT1B, MFT2B)

Interrupt pending flag

TnAPND

TnBPND

TnCPND

TnDPND

Mode 1

PWM and counter

TnCNT1 reload from TnCRA

TnCNT1 reload from TnCRB

N/A

Table 146. MFT interrupt functions

TnCNT2 underflow

Mode 1a Mode 2

PWM pulse train

Dual-input capture and counter

TnCNT1 reload from TnCRA

TnCNT1 reload from TnCRB

N/A

TnCNT2 underflow

Input capture on

TnA transition

Input capture on

TnB transition

TnCNT1 underflow

TnCNT2 underflow

Mode 3

Dual independent counter

TnCNT1 reload from

TnCRA

N/A

TnCNT2 reload from

TnCRB

Mode 4

Input capture plus timer

TnCNT1 reload from TnCRA

Input capture on

TnB transition

N/A

TnCNT2 underflow

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3.13.3

MFT registers

MFT1 peripheral base address (MFT1_BASE_ADDR) 0x40D00000.

MFT2 peripheral base address (MFT2_BASE_ADDR) 0x40E00000.

Address offset Name

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

TnCNT1 RW

TnCRA RW

TnCRB RW

TnCNT2 RW

TnPRSC RW

TnCKC RW

TnMCTRL RW

0x1C

0x20

TnICTRL

TnICLR

Table 147. MFTX registers

Reset

0x00000000

Description

Timer / Counter1 register. Refer to the detailed description below.

Capture / Reload A register. Refer to the detailed description below.

Capture / Reload B register. Refer to the detailed description below.

Timer / Counter 2 register. Refer to the detailed description below.

Clock prescaler register. Refer to the detailed description below.

Clock unit control register. Refer to the detailed description below.

Timer mode control register. Refer to the detailed description below.

Timer interrupt control register. Refer to the detailed description below.

Timer interrupt clear register. Refer to the detailed description below.

Table 148. MFTX – TnCNT1 register description: address offset MFTX_BASE_ADDR+0x00

Bit Field name Reset RW

15:0

Description

TnCNT1 0x0000 RW

The Timer/Counter 1 register is a 16-bit RW register that is not altered by reset and thus contains random data upon power-up. Reading the register returns the current value of the Timer/Counter 1.

31:16 RESERVED 0x0 RW RESERVED

Table 149. MFTX – TnCRA register description: address offset MFTX_BASE_ADDR+0x04

Bit Field name Reset RW Description

15:0 TnCRA 0x0000 RW

The Capture/Reload A register is a 16-bit RW register that is not affected by reset and thus contains random data upon power-up. The software may read the register at any time. However, the register can only be written by the software when MFT is enabled

(TnEN = 1). When MFT is disabled (TnEN = 0), write operations on TnCRA register are ignored.

31:16 RESERVED 0x0 RW RESERVED

Table 150. MFTX – TnCRB register description: address offset MFTX_BASE_ADDR+0x08

Bit Field name Reset RW Description

15:0 TnCRB 0x0000 RW

The Capture/Reload B register is a 16-bit RW register that is not affected by reset and thus contains random data upon power-up. The software may read the register at any time. However, the register can only be written by the software when MFT is enabled

(TnEN = 1). When MFT is disabled (TnEN = 0), write operations on TnCRB register are ignored.

31:16 RESERVED 0x0 RW RESERVED

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Table 151. MFTX – TnCNT2 register description: address offset MFTX_BASE_ADDR+0x0C

Bit Field name Reset RW

15:0

Description

TnCNT2 0x0000 RW

The Timer/Counter 2 register is a 16-bit RW register that is not altered by reset and thus contains random data upon power-up. Reading the register returns the current value of the Timer/Counter 2.

31:16 RESERVED 0x0 RW RESERVED

Table 152. MFTX – TnPRSC register description: address offset MFTX_BASE_ADDR+0x10

Bit Field name Reset RW Description

7:0 TnPRSC 0x00 RW

The clock prescaler register is an 8-bit RW register. It contains the current value of the clock prescaler, which determines the timer clock prescaler ratio. The register value can be changed at any time. In all operating modes except pulse-train (mode1a), a modified value is used upon an underflow of the internal prescaler counter. In mode 1a, the new value is used either upon start of a new pulse train (a write to TnPTSE), or upon an event on TnB

(if TnPTET=1). The timer clock is generated by dividing the system clock by TnPRSC + 1.

Therefore, the maximum timer clock frequency is equal to the frequency of the system clock

(TnPRSC = 0x00), and the minimum timer clock is the frequency of the system clock divided by 256 (TnPRSC = 0xFF).

31:8 RESERVED 0x0 RW RESERVED

Table 153. MFTX - TnCKC register description: address offset MFTX_BASE_ADDR+0x14

Bit

2:0

5:3

31:6

Field name Reset RW

TnC1CSEL

TnC2CSEL

RESERVED

Description

0x0 RW

•

Determines the clock mode for the Timer/Counter 1:

000b: No clock (Timer/Counter 1 stopped).

001b: System clock with configurable prescaler (register TnPRSC).

010b: External event on TnB (mode 1 and 3 only).

011b: Pulse accumulate (mode 1 and 3 only).

0x0 RW

•

Determines the clock mode for the Timer/Counter 2:

000b: No clock (Timer/Counter 2 stopped).

001b: System clock with configurable prescaler (register TnPRSC).

010b: External event on TnB (mode 1 and 3 only).

011b: Pulse accumulate (mode 1 and 3 only).

0x0 RW RESERVED

Table 154. MFTX - TnMCTRL register description: address offset MFTX_BASE_ADDR+0x18

Bit Field name Reset RW Description

1:0 TnMDSEL 0x0 RW

•

MFT mode select:

00b: Mode 1 or 1a: PWM mode and system timer or pulse train mode

01b: Mode 2: Dual-input capture mode and system timer

10b: Mode 3: Dual independent mode Timer/Counter mode

11b: Mode 4: Single timer and single input capture mode

TnAEDG

TnBEDG

0x0 RW

Configure the TnA edge polarity for trigging an action:

0: Input is sensitive to falling edges.

1: Input is sensitive to rising edges.

0x0 RW

Configure the TnB edge polarity for trigging an action:

0: Input is sensitive to falling edges.

1: Input is sensitive to rising edges.

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Bit Field name Reset RW Description

TnAEN

TnBEN

TnAOUT

TnEN

0x0 RW

Enables TnA to either function as a preset input or as a PWM output depending on the mode of operation. If the bit is set (1) while operating in the dual-input capture mode (mode

2), a transition on TnA causes TnCNT1 to be preset to 0xFFFF. In the remaining modes of operation, setting TnAEN enables TnA to function as a PWM output

0: TnA input disable.

1: TnA input enable.

0x0 RW

TnB Enable: If set (1) and while operating in dual-input capture mode (mode 2) or input capture and timer mode (mode 4), a transition on TnB causes the corresponding Timer/

Counter to be preset to 0xFFFF. In mode 2, TnCNT1 is preset to 0xFFFF, while in mode 4,

TnCNT2 is preset to 0xFFFF. The bit has no effect while operating in any other modes than mode 2 or mode 4.

0: TnB input disable.

1: TnB input enable.

0x0 RW

The TnA output data contains the value of the TnA when used as PWM output. The bit will be set and cleared by the hardware and thus reflects the status of TnA. The bit can be read or written by software at any time. If the hardware is attempting to toggle the bit at the same time that software writes to the bit, the software write will take precedence over the hardware update. The bit has no effect when TnA is used as an input or when the module is disabled:

0: TnA pin is low.

1: TnA pin is high.

0x0 RW

MFT Enable: This bit enables or disables the MFT peripherals. When the bit is set (1), MFT is enabled, and when the bit is cleared (0), MFT is disabled. When MFT is disabled, all clocks to the counter unit are stopped, thus decreasing power consumption to a minimum.

For that reason, the Timer/Counter registers (TnCNT1, TnCNT2), the Capture/Reload registers (TnCRA, TnCRB) and the interrupt-pending bits (TnXPND) cannot be written by software. Furthermore, the 8-bit clock prescaler and the interrupt-pending bits are reset and the TnA I/O pin becomes an input:

0: MFT disable

1: MFT enable

TnPTEN

TnPTSE

TnPTET

0x0 RW

This bitfield enable the mode 1a. If set (1) while TnMDSEL is set to 00b, the Timer/Counter

1 operates in PWM pulse-train mode (mode 1a). The bit has no effect while TnMDSEL is set to any value other than 00b.

0: Mode 1a not selected.

1: Mode 1a selected (if TnMDSEL = 00b).

0x0 RW

Tn Pulse-Train software trigger enable: if set (1) while operating in PWM pulse-train mode

(mode 1a), the pulse-train generation can only be triggered by setting the TnPTET to 1. If the TnPTSE bit is reset (0), pulses are generated only if a transition occurs on TnB. The bit has no effect while operating in any other modes than timer mode 1a:

0: No effect

1: Pulse-train generation trigger (in mode 1a)

0x0 RW

Tn Pulse-Train event trigger: if set (1) while operating in pulse-train mode (mode 1a) and the TnPTSE bit is set (1), pulse-train generation is triggered. When Timer/Counter 2

(TnCNT2) reaches its underflow condition, this bit is reset (0). If the TnPTSE bit is not set (0) while operating in pulse-train mode (mode 1a), the TnPTET bit cannot be written.

Therefore, a 1 in TnPTET indicates that an external event started a pulse-train generation that is not yet finished. When the pulse-train is finished, the bit is reset to 0:

0: No pulse-train event trigger occurred.

1: Pulse-train event trigger occurred (in mode 1a).

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Note:

3.14

3.14.1

Bit

31:8

Table 155. MFTX - TNICTRL register description: address offset MFTX_BASE_ADDR+0x1C

Field name

TNAPND

TNBPND

TNCPND

TNDPND

TNAIEN

TNBIEN

TNCIEN

TNDIEN

RESERVED

Reset

0x0

Description

Timer interrupt A pending:·

0: No interrupt source pending.

1: Interrupt source pending.

Timer interrupt B pending:

0: No interrupt source pending.

1: Interrupt source pending.

Timer interrupt C pending:

0: No interrupt source pending.

1: Interrupt source pending.

Timer interrupt D pending:

0: No interrupt source pending.

1: Interrupt source pending.

Timer interrupt A enable:

0: Interrupt disabled.

1: Interrupt enabled.

Timer interrupt B enable:

0: Interrupt disabled.

1: Interrupt enabled.

Timer interrupt C enable:

0: Interrupt disabled.

1: Interrupt enabled

Timer interrupt D enable:

0: Interrupt disabled.

1: Interrupt enabled.

RESERVED

Bit

31:4

Table 156. MFTX - TNICLR register description: address offset MFTX_BASE_ADDR+0x20

Field name

TNACLR

TNBCLR

TNCCLR

TNDCLR

RESERVED

Reset

0x0

Description

1: clear the timer pending flag A

1: clear the timer pending flag B.

1: clear the timer pending flag C.

1: clear the timer pending flag D.

RESERVED

All RESERVED fields inside registers must always be written with their default value.

Watchdog

Introduction

The watchdog timer provides a way of recovering from software crashes.

The watchdog monitors the interrupt and asserts a reset signal if the interrupt remains unserved for the entire programmed period.

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Watchdog

3.14.2

3.14.3

•

The watchdog clock is used to generate a regular interrupt, depending on a programmed value. It is counting down at a fixed frequency around 32.768 kHz provided either by embedded RCO or by the external XO 32 kHz.

Main features are:

• 32-bit down counter at fixed frequency 32.768 kHz

Generate an interrupt each time the counter reaches zero

Generate an internal reset that reboot the system if the generated interrupt is not cleared by software and a second interrupt occurs

Functional description

The watchdog timer is a 32-bit down counter that divides the clock input to produce an interrupt. The divide ratio is fully programmable and controls the interrupt interval, which can be calculated as:

Interrupt interval = (WDT_LOAD + 1) / (clock frequency in Hz).

The table below shows examples of WDT_LOAD values.

WDT_LOAD

4294967295

65535

32767

4095

127

Table 157. Watchdog interrupt interval

Interrupt interval (ms)

131072000

2000

1000

125

3.90625

1.953125

0.0610

A watchdog interrupt is generated each time the counter reaches zero. The counter is then reloaded with the content of the WDT_LR register. The interrupt status should be cleared by writing to the interrupt clear register.

When the interrupt is cleared, the counter is reloaded with the WDT_LOAD value. If the interrupt status is not cleared and a new interrupt is generated, then a watchdog Reset is generated, rebooting the system.

The watchdog interrupt and Reset generation can be enabled or disabled as required by the system using the relevant bits in the control register. When the interrupt generation is disabled the watchdog counter is also stopped, and when the interrupt is enabled the counter will start from the programmed value, not the last-count value.

Write access to the registers within the watchdog timer can be disabled in the watchdog lock register. Writing a value of 0x1ACC_E551 to this WDT_LOCK register allows write access to all other registers; writing any other value disables write access. This feature is included to allow some protection against software that might otherwise disable the watchdog functionality.

Watchdog registers

WDG peripheral base address (WDG_BASE_ADDR) 0x40700000.

Address offset Name RW

0x00 LR RW

0x04

0x08

0x0C

VAL

ICR RW

0x10 RIS R

Table 158. WDG registers

Reset

0xFFFFFFFF

0x00000000

Description

Watchdog load register. Refer to the detailed description below.

Watchdog value register. Refer to the detailed description below.

Watchdog control register. Refer to the detailed description below.

Watchdog interrupt clear register. Refer to the detailed description below.

Watchdog raw interrupt status register. Refer to the detailed description below.

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Watchdog

Address offset Name RW

0x14

0xC00

MIS

LOCK

Reset

0x00000000

Description

Watchdog masked interrupt status register. Refer to the detailed description below.

Watchdog Lock register. Refer to the detailed description below.

31:0

Table 159. WDG - LR register description: address offset WDG_BASE_ADDR+0x00

Bit Field name

LOAD

Reset

0xFFFFFFFF

Description

Watchdog load value. Value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value.

Table 160. WDG - VAL register description: address offset WDG_BASE_ADDR+0x04

Bit Field name

31:0 WDTVAL

Reset

0xFFFFFFFF

Description

Watchdog current value. When read, returns the current value of the decrementing watchdog counter. A write has no effect.

Bit

31:2

Table 161. WDG - CR register description: address offset WDG_BASE_ADDR+0x08

Field name

INTEN

RESEN

RESERVED

Reset

0x0

Description

Watchdog interrupt enable. Enable the interrupt event:

0: watchdog interrupt is disabled.

1: watchdog interrupt is enabled.

Watchdog reset enable. Enable the watchdog reset output:

0: watchdog reset is disabled.

1: watchdog reset is enabled.

RW RESERVED

Table 162. WDG - ICR register description: address offset WDG_BASE_ADDR+0x0C

Bit Field name

31:0 WDTICLR

Reset

0x0

Description

Watchdog interrupt clear:

Writing any value will clear the watchdog interrupt and reloads the counter from the LR register.

A read returns zero.

Bit Field name

Table 163. WDG - RIS register description: address offset WDG_BASE_ADDR+0x10

RIS

31:1 RESERVED

Reset

0x0

RW Description

Watchdog raw interrupt status bit. Reflects the status of the interrupt status from the watchdog:

0: watchdog interrupt is not active.

1: watchdog interrupt is active.

Read-only bit. A write has no effect.

R RESERVED page 109/167

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Bit Field name

Table 164. WDG - MIS register description: address offset WDG_BASE_ADDR+0x14

MIS

31:1 RESERVED

Reset

0x0

Description

Watchdog masked interrupt status bit. Masked value of watchdog interrupt status:

0: watchdog interrupt is not active.

1: watchdog interrupt is active.

Read-only bit. A write has no effect.

R RESERVED

Note:

3.15

3.15.1

3.15.2

3.15.2.1

Table 165. WDG - LOCK register description: address offset WDG_BASE_ADDR+0xC00

Bit Field name

31:0 LOCKVAL

Reset

0x0

Description

Watchdog lock value. When read, returns the lock status:

0: Write access to all watchdog other registers is enabled.

1: Write access to all watchdog other registers is disabled.

When written, allows enabling or disabling write access to all other watchdog registers:

Writing 0x1ACCE551: Write access to all other registers is enabled.

Writing any other value: Write access to all other registers is disabled.

All RESERVED fields inside registers must always be written with their default value.

RTC

Introduction

The RTC timer can be used to provide an interrupt at regular time intervals. It generates an interrupt signal when it reaches zero after decrementing for a programmed number of cycles of the real-time clock input. The RTC timer can restart automatically from a load value when reaching zero if the auto restart mode is enabled, or it can stop when it reaches zero.

The RTC is clocked by the 32 kHz clock and is switched off in low-power modes which prevents this timer to be used for wake-up events.

Functional description

The RTC peripheral can be used either as real-time clock timer or as real-time clock watch.

•

Real-time clock timer

The real-time clock timer (RTC timer) can be used to provide an interrupt at regular time intervals.

The RTC timer can restart automatically from a load value when reaching zero if the auto restart mode is enabled, or it can stop when it reaches zero.

•

The RTC timer has the following features:

• 32-bit down-counter.

Interrupt generation when timer reaches zero.

Start, auto restart (after counts to zero) and stop capability.

On-the-fly register read and write access.

1/32 kHz minimum period.

Multiple modes: periodic interrupt and single interrupt generation.

Capability to switch between two load values in periodic mode. The timer reloads alternatively from one load value to the other and the down-counter starts decrementing every 31.25 μs (on average).

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RTC

Note:

3.15.2.2

The RTC timer is a 32-bit free-running counter, clocked by the 32 kHz clock signal (from an embedded 32 kHz

RC), that works in two modes: periodic and one-shot.

Table 166. RTC modes

RTTOS bit Mode

Description

Periodic

The counter generates an interrupt at a constant interval, reloading a load value after wrapping past zero. There are two load values: RTC_TLR1 for pattern value 0 and RTC_TLR2 for pattern value 1.

One-shot

The counter generates an interrupt once. When the counter reaches zero, it halts until the user restarts it by: setting bit RTTEN in the RTC_TCR register of writing a new value to the load register

RTC_TLR1

The RTC timer load registers define the values from which the counter restarts alternatively.

In periodic mode, the timer must be stopped by the software before writing to a load register. The counter loads a value from RTC_TLR1 or from RTC_TLR2, depending on the value of the current pattern value that crosses the pattern register to decide after each interrupt generation, which value to load. The number of pattern bits to be crossed periodically (from the 128 bits) is specified in RTC_TCR [10:4]. This process offers the possibility to have better precision of the average tick period.

In one-shot mode, the timer stops when it reaches zero, but the software can also stop it. Once the counter is halted, the load registers (RTC_TLR1, RTC_TLR2) can be written and the counter considers the new written value. After a write, RTTEN (RTC_TCR) is set if the timer is in self-start mode.

Writing to RTC_TLR1 or RTC_TLR2 has no effect when the counter is running (the registers contents are not changed).

Two consecutive write operations to the RTC_TCR register must be separated by at least 3 times the low speed clock period plus twice the system clock period. This time is about 140 us. If this time is not satisfied, the last written value cannot be guaranteed. The software can read back the RTC_TCR register value after at least 1 period of the low speed clock.

Real-time clock watch

The RTC clock watch consists of two counters and two alarm registers that have the following features:

• Two counters:

– Counts seconds, minutes, hours, days of the week, days of the month.

– Counts years.

• Two alarm registers:

– To trigger an interrupt at exact date and time.

The clock watch counters are split in two registers:

The RTC_CWDR register that holds:

• Seconds on six bits. Valid values are 0 to 59. (60, 61, 62 and 63 are invalid values, programming the

RTC_CWDR with these values leads to unpredictable behavior.) The seconds are incremented on the

CLK1HZ clock rate.

•

Minutes on six bits. Valid values are 0 to 59 (60, 61, 62 and 63 are invalid values, programming the

RTC_CWDR with these values leads to unpredictable behavior.)

Hours on five bits. Valid values are 0 to 23 (24 to 31 are invalid values, programming the RTC_CWDR with these values leads to unpredictable behavior.)

The day of the week on three bits. Valid values are 1 (Sunday) to 7 (Saturday) (0 is an invalid value, programming the RTC_CWDR with this value leads to unpredictable behavior.)

•

The day of the month on five bits. Valid values are 1 to 31 for January, March, May, July, August, October and December, 1 to 30 for April, June, September, and November, 1 to 29 for February on leap years, or 1 to 28 for February on non-leap years. All other values are invalid values. Programming the RTC_CWDR with these values leads to unpredictable behavior.)

The month on four bits. Valid values are 1 (January) to 12 (December). 0, 13, 14 and 15 are invalid values, programming the RTC_CWDR with these values leads to unpredictable behavior.

The RTC_CWYR register holds:

• The year, from 0 to 4096

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RTC

3.15.2.3

3.15.3

The clock watch time and date can be changed by writing new settings in the RTC_CWDLR and RTC_CWYLR load registers. The new setting is transferred to the clock watch counters on the next CLK1HZ rising edge after the RTC_CWDLR register has been written.

After each increment of the clock watch counters, the RTC_CWDR and RTC_CWYR registers are compared to the clock watch match registers, RTC_CWDMR and RTC_CWYMR.

If both pairs of registers match, the internal interrupt signal RTCWINTR is raised.

RTC interrupts

The RTC generates two internal interrupt signals:

• RTCINTR: raised when the two clock watch counter registers (RTC_CWDR and RTC_CWYR) match the two clock watch alarm registers (RTC_CWDMR and RTC_CWYMR). Some bit-fields can be ‘don’t care’ during the comparison if a zero value is used for year, month, day of month and day of week. The software must clear this interrupt by writing 1 in the bit RTCCWIC of RTC_ICR register.

• RTTINTR: raised when the full 32-bit down-counter RTC_TDR reaches zero and is only cleared by writing

1 in the bit RTTIC of the RTC_ICR register. The most significant carry bit of the counter detects the counter reaches zero. The software must clear this interrupt by writing 1 in the bit RTCTIC of the RTC_ICR register.

Each individual interrupt can be masked by writing 0b to its corresponding interrupt mask set/clear bit in the

RTC_IMSC register. Both the raw interrupt status (prior to masking) and the final interrupt status (after masking) for each individual interrupt signal can be read from the RTC_RIS and RTC_MIS status registers.

The RTC delivers also a single combined interrupt signal, RTUINTR. This interrupt line is the logical OR of the both internal interrupt signals described above and is the signal connected to the processor interrupt line.

RTC registers

RTC peripheral base address (RTC_BASE_ADDR) 0x40F00000.

Table 167. RTC registers

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x48

Address offset Name RW

0x00 CWDR R

Reset Description

0x02120000 Clockwatch data register. Refer to the detailed description below.

0x04

0x08

CWDMR

CWDLR

0x00000000 Clockwatch data match register. Refer to the detailed description below.

0x00000000 Clockwatch data load register. Refer to the detailed description below.

0x0C

0x10

0x14

CWYR R 0x00002000 Clockwatch year register. Refer to the detailed description below.

CWYMR RW 0x00002000 Clockwatch year match register. Refer to the detailed description below.

CWYLR RW 0x00000000 Clockwatch year load register. Refer to the detailed description below.

0x18

0x1C

0x20

0x24

CTCR RW 0x00007FFF Control trim and counter register. Refer to the detailed description below.

IMSC RW 0x00000000 RTC interrupt mask register. Refer to the detailed description below.

RIS

MIS

R 0x00000000 RTC raw interrupt status register. Refer to the detailed description below.

R 0x00000000

RTC masked interrupt status register. Refer to the detailed description below.

W 0x00000000 RTC interrupt clear register. Refer to the detailed description below.

ICR

TDR

TCR

0xFFFFFFFF RTC timer load value

0x00000000 RTC timer control register. Refer to the detailed description below.

TLR1

TLR2

RW 0x00000000 RTC timer first load register

RW 0x00000000 RTC timer second load Register

TPR1 RW 0x00000000 RTC timer pattern register (pattern[31:0])

TPR2 RW 0x00000000 RTC timer pattern register (pattern[63:32])

TPR3 RW 0x00000000 RTC timer pattern register (pattern[95:64])

TPR4 RW 0x00000000 RTC timer pattern register (pattern[127:96])

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RTC

Address offset Name RW

0x4C TIN R

Reset Description

0x00000000 RTC timer interrupt number register

Table 168. RTC - CWDR register description: address offset RTC_BASE_ADDR+0x00

Bit Field name

5:0 CWSEC

11:6 CWMIN

16:12 CWHOUR

19:17 CWDAYW

24:20 CWDAYM

28:25 CWMONTH

31:29 RESERVED

Reset

0x0

0x1

0x0

RW Description

R RTC clockwatch second value. Clockwatch seconds: 0 to 59 (max. 0x3B).

R RTC clockwatch minute value. Clockwatch seconds: 0 to 59 (max. 0x3B).

R RTC clockwatch hour value. Clockwatch seconds: 0 to 23 (max. 0x17).

RTC clockwatch day of week value. Clockwatch day of week:

001b: Sunday.

010b: Monday.

011b: Tuesday.

100b: Wednesday.

101b: Thursday.

110b: Friday.

111b: Saturday.

RTC clockwatch day of month value: 1 to 28/29/30 or 31. Range of value to program depends on the month:

1 to 28: February month, non-leap year.

1 to 29: February month, leap year.

1 to 30: April, June, September, November month.

1 to 31: January, March, May, July, August, October, December month.

RTC clockwatch month value:

0001b: January.

...

1100: December.

R RESERVED

5:0

11:6

Table 169. RTC - CWDMR register description: address offset RTC_BASE_ADDR+0x04

Bit Field name

CWSECM

CWMINM

16:12 CWHOURM

19:17 CWDAYWM

Reset

0x0

RW Description

RTC clockwatch second match value:

00 0000 to 11 1011: (0 to 59 or 0x00 to 0x3B) clockwatch seconds.

11 1100 to 11 1111 - (60 to 63 or 0x3C to 0x3F).

Non-valid data, match never occurs.

RTC clockwatch minute match value:

00 0000 to 11 1011: (0 to 59 or 0x00 to 0x3B) clockwatch minutes.

11 1100 to 11 1111 - (60 to 63 or 0x3C to 0x3F).

Non-valid data, match never occurs.

RTC clockwatch hour match value:

00000b to 10111b: (0 to 23 or 0x00 to 0x17) hour match value.

11000b to 11111b - (24 to 31 or 0x18 to 0x1F).

Non-valid data, match never occurs.

RW RTC clockwatch day of week match value: page 113/167

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Bit Field name

24:20 CWDAYMM

28:25 CWMONTHM

31:29 RESERVED

Reset

0x0

RW Description

000b: day of week does not care in the comparison. (Default value after

PORn).

001b to 111b: (1 to 7) day of week match value.

RTC clockwatch day of month match value:

0000b: (month does not care in the comparison. Default value after PORn).

1 to 31: day of month match value.

RTC clockwatch month match value:

0000b: (day of month does not in the comparison. Default value after PORn).

0001b to 1100b: (1 to 12) month match value.

1101b (13, 0xD) to 1111b (0xF) non-valid data, match never occurs.

RW RESERVED

5:0

11:6

Table 170. RTC - CWDLR register description: address offset RTC_BASE_ADDR+0x08

Bit Field name

CWSECL

CWMINL

16:12 CWHOURL

19:17 CWDAYWL

24:20 CWDAYML

28:25 CWMONTHL

31:29 RESERVED

Reset

0x0

RW Description

RTC clockwatch second load value. Clockwatch seconds from 0 to 59 (0x3B).

Other values must not be used.

RTC clockwatch minute load value. Clockwatch minutes from 0 to 59 (0x3B).

Other values must not be used.

RTC clockwatch hour load value. Clockwatch hours from 0 to 23 (0x17). Other values must not be used.

RTC clockwatch day of week load value. Clockwatch day of week:

000b: Must not be used.

001b: Sunday.

010b: Monday.

RW 011b: Tuesday.

100b: Wednesday.

101b: Thursday.

110b: Friday.

111b: Saturday.

RTC clockwatch day of month load value. 1 to 28/29/30 or 31 depending on month:

1 to 28: February month, non-leap year.

1 to 29: February month, leap year.

1 to 30: April, June, September, November month.

1 to 31: January, March, May, July, August, October, December month.

Other values must not be used.

RTC clockwatch month load value:

0001b: January.

...

1100: December.

Other values must not be used.

RW RESERVED page 114/167

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Table 171. RTC - CWYR register description: address offset RTC_BASE_ADDR+0x0C

Bit Field name

13:0 CWYEAR

31:14 RESERVED

Reset

0x2000

0x0

RW Description

R RTC clockwatch year value. Clockwatch year, in BCD format is from 0 to 4096.

R RESERVED

Table 172. RTC - CWYMR register description: address offset RTC_BASE_ADDR+0x10

Bit Field name

13:0 CWYEARM

31:14 RESERVED

Reset

0x2000

0x0

RW Description

RTC clockwatch year match value. Clockwatch year match value is in BCD format from 0 to 4096.

RW RESERVED

Table 173. RTC - CWYLR register description: address offset RTC_BASE_ADDR+0x14

Bit Field name

13:0 CWYEARL

31:14 RESERVED

Reset

0x0

RW Description

RTC clockwatch year load value. Clockwatch year load value is in BCD format from 0 to 4096.

RW RW RESERVED

Bit Field name

14:0

15 RESERVED

25:16 CKDEL

Table 174. RTC - CTCR register description: address offset RTC_BASE_ADDR+0x18

CKDIV

CWEN

31:27 RESERVED

Reset

0x7FFF

0x0

RW Description

Clock divider factor. This value plus one represents the integer part of the

CLK32K clock divider used to produce the reference 1 Hz clock.

0x000: CLK1HZ clock is similar to CLK32K for RTC timer and stopped for RTC clockwatch.

0x0001: 2 CLK32K clock cycles per CLK1HZ clock cycle.

...

0x7FFF: 32768 CLK32K clock cycles per CLK1HZ clock cycle (default value after PORn Reset).

...

0xFFFF: CLK32K clock cycles per CLK1HZ clock cycle.

Writing to this bit-field is disregarded if CWEN = 1. A read returns the value of the CKDIV bit-field.

RW RESERVED

Trim delete count. This value represents the number of CLK32K clock pulses to delete every 1023 CLK32K clock cycles to get a better reference 1 Hz clock for incrementing the RTC counter.

0x000: No CLK32K clock cycle is deleted every 1023 CLK1HZ clock cycles

(default value after PORn Reset).

0x001: 1 CLK32K clock cycle is deleted every 1023 CLK1HZ clock cycles.

...

0x3FF: 1023 CLK32K clock cycles are deleted every 1023 CLK1HZ clock cycles.

Writing to this bit-field is disregarded if CWEN = 1. A read returns the value of the CKDEL bit-field.

Clockwatch enable bit. When set to 1, the clockwatch is enabled. Once it is enabled, any write to this register has no effect until a Power-On-Reset. A read returns the value of the CWEN bit value.

RW RESERVED page 115/167

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Bit Field name

Table 175. RTC - IMSC register description: address offset RTC_BASE_ADDR+0x1C

WIMSC

TIMSC

31:2 RESERVED

Reset

0x0

RW Description

RTC clock watch interrupt enable bit:

When set to 0, clears the interrupt mask (default after PORn Reset). The interrupt is disabled.

When set to 1, the interrupt for RTC clockwatch interrupt is enabled.

RTC timer interrupt enable bit:

When set to 0, sets the mask for RTC timer interrupt (default after PORn reset).

The interrupt is disabled.

When set to 1, clears this mask and enables the interrupt.

RW RESERVED

Bit Field name

Table 176. RTC - RIS register description: address offset RTC_BASE_ADDR+0x20

WRIS

TRIS

31:2 RESERVED

Reset

0x0

Description

RTC clock watch raw interrupt status bit. Gives the raw interrupt state (prior to masking) of the RTC clock watch interrupt.

RTC timer raw interrupt status bit. Gives the raw interrupt state (prior to masking) of the RTC timer interrupt.

R RESERVED

Bit Field name

Table 177. RTC - MIS register description: address offset RTC_BASE_ADDR+0x24.

WMIS

TMIS

31:2 RESERVED

Reset

0x0

Description

RTC clock watch interrupt status bit. Gives the masked interrupt status (after masking) of the RTC clock watch interrupt WINTR.

RTC timer interrupt status bit. Gives the masked interrupt status (after masking) of the RTC timer interrupt TINTR.

R RESERVED

Bit Field name

WIC

TIC

Table 178. RTC - ICR register description: address offset RTC_BASE_ADDR+0x28

31:2 RESERVED

Reset

0x0

RW Description

RTC clock watch interrupt clear register bit. Clears the RTC clock watch interrupt WINTR.

0: No effect.

1: Clears the interrupt.

RTC timer interrupt clear register bit. Clears the RTC timer interrupt TINTR.

0: No effect.

1: Clears the interrupt.

W RESERVED

Bit

31:0

Table 179. RTC – TDR register description: address offset RTC_BASE_ADDR+0x2C

Field name

TDR

Reset

0xFFFFFFFF

Description

RTC time load value.

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RTC

Bit

10:4

Table 180. RTC - TCR register description: address offset RTC_BASE_ADDR+0x30

Field name

RESERVED

CLK

12 BYPASS_GATED

31:13 RESERVED

Reset

0x0

RW Description

RTC Timer one shot count.

0: Periodic mode (default). When reaching zero, the RTC timer raises its interrupt and is reloaded from the LD content.

1: One-shot mode. When reaching zero, the RTC timer raise its interrupt and stops.

RTC Timer enable bit.

0: The RTC timer is stopped on the next CLK32K cycle.

1: The RTC timer is enabled on the next CLK32K cycle.

When the RTC timer is stopped, the content of the counter is frozen. A read returns the value of the EN bit. This bit set by hardware when the

TLR register is written to while the counter is stopped. When the device is active, this bit is cleared by hardware when the counter reaches zero in one-shot mode.

RTC Timer self start bit. When written to 1b, each write in a load register or a pattern will set EN to 1b, so, start the counter in the next CLK32K cycle.

RW RESERVED

RTC Timer Pattern size. Number of pattern bits crossed by the pointer. It defines the useful pattern size.

RTC Timer clock.

0: The RTC timer is clocked by CLK32K.

1: The RTC timer is clocked by the trimmed clock.

Enable or disable the internal clock gating:

0: The internal clock gating is activated.

1: No clock gating, clock is always enabled.

RW RESERVED

Bit

31:0

Table 181. RTC – TLR1 register description: address offset RTC_BASE_ADDR+0x34

Field name

TLR1

Reset

0x00000000

RW Description

RW RTC timer first load value.

Bit

31:0

Table 182. RTC – TLR2 register description: address offset RTC_BASE_ADDR+0x38

Field name

TLR2

Reset

0x00000000

RW Description

RW RTC timer second load value.

Bit

31:0

Table 183. RTC – TPR1 register description: address offset RTC_BASE_ADDR+0x3C

Field name

TPR1

Reset

0x00000000

RW Description

RW RTC timer pattern register (pattern[31:0]).

Bit

31:0

Table 184. RTC – TPR2 register description: address offset RTC_BASE_ADDR+0x40

Field name

TPR2

Reset

0x00000000

RW Description

RW RTC timer pattern register (pattern[63:32]).

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RNG

Note:

3.16

3.16.1

3.16.2

3.16.3

Bit

31:0

Table 185. RTC – TPR3 register description: address offset RTC_BASE_ADDR+0x44

Field name

TPR3

Reset

0x00000000

RW Description

RW RTC timer pattern register (pattern[95:64]).

Bit

31:0

Table 186. RTC – TPR4 register description: address offset RTC_BASE_ADDR+0x48

Field name

TPR4

Reset

0x00000000

RW Description

RW RTC timer pattern register (pattern[127:96]).

Bit

31:0

Table 187. RTC – TIN register description: address offset RTC_BASE_ADDR+0x4C

Field name

TIN

Reset

0x00000000

Description

RTC timer interrupt number register.

All RESERVED fields inside registers must always be written with their default value.

RNG

Introduction

The RNG is a real random number generator based on a continuous analog noise that provides a 16-bit value to the host when read.

Functional description

The peripheral is normally used by the Bluetooth Stack, but the user can read the random value at any time by accessing the register VAL. The RNG peripheral is addressed through the AHB, so the access must be at 32-bit, otherwise hard fault is generated on Cortex M0.

The minimum period between two consecutive random numbers is about 1.25 µs.

RNG registers

RNG peripheral base address (RNG_BASE_ADDR) 0xB0000000

Table 188. RNG registers

Address offset Name RW

0x00 CR RW

Reset

0x00000000

Description

RNG configuration register. Refer to the detailed description below.

0x04

0x08

VAL

0x00000000

RNG status register. Refer to the detailed description below.

RNG 16-bit random value. Refer to the detailed description below.

Table 189. RNG – CR register description: address offset RNG_BASE_ADDR+0x00

Bit Field name Reset RW Description

1:0 RESERVED

2 DIS

0x0

RW RESERVED

•

Set the state of the random number generator.

0: RNG is enable.

1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block.

31:3 RESERVED 0x00000000 RW RESERVED

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PDM stream processor

Note:

3.17

3.18

3.19

3.19.1

Table 190. RNG – SR register description: address offset RNG_BASE_ADDR+0x04

Bit

Field name

RDY

Reset

0x0

Description

•

New random value ready.

0: The VAL register value is not yet valid. If performing a read access to VAL, the host will be put on hold until a random value is available.

1: The VAL register contains a valid random number.

This bit remains at 0 when the RNG is disabled (RNGDIS bit = 1b in CR)

31:1 RESERVED 0x00000000 R RESERVED

Bit

15:0

31:16

Table 191. RNG – VAL register description: address offset RNG_BASE_ADDR+0x08

Field name

RANDOM_VALUE

RESERVED

Reset

0x0000

Description

The 16-bit random value.

RESERVED

All RESERVED fields inside registers must always be written with their default value.

PDM stream processor

The BlueNRG-1 integrates a digital filter for processing PDM stream coming from a digital microphone and inputting into a GPIO pin. The BlueNRG-1 outputs a 0.8 MHz or 1.6 MHz signal into a GPIO pin for providing the digital microphone with a frequency clock.

System timer (SysTick)

The BlueNRG-1 includes a system timer (SysTick) that can be polled by software or can be configured to generate an interrupt. SysTick interrupt has its own entry in the vector table and therefore can have its own handler.

Public key accelerator (PKA)

The public key accelerator is for the computation of cryptographic public key primitives through elliptic curve cryptography (ECC) using a predefined prime modulus and a predefined curve.

PKA functional description

The PKA core is clocked by the system clock divided by two and the PKA memory is clocked by system clock.

This peripheral is addressed through the AHB, so the access must be at 32-bit or a hard fault is generated on the

Cortex M0.

•

The PKA works on a 4 kB dedicated RAM block located in 0xC0000400.

The main features of the PKA block are: elliptic curve Diffie-Hellman (ECDH) public-private key pair calculation accelerator based on the Montgomery method for fast modular multiplications built-in Montgomery domain inward and outward transformations

AMBA AHB lite slave interface with a reduced command set

• single port internal memory available for the system when the BlueNRG-1 PKA is not using it.

The PKA and the PKA RAM are clock gated by default after reset, so the clock must be enabled in CKGEN_SOC before using PKA functionality.

The input data, output data and data verification result have specific locations in the PKA RAM.

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Public key accelerator (PKA)

3.19.2

Parameter description

INPUT: ECC K value of kP

INPUT: input point P, coordinate X

INPUT: input point P, coordinate Y

OUTPUT: output point P, coordinate X

OUTPUT: output point P, coordinate Y

OUTPUT: error value

1. ECC operand size.

Table 192. PKA RAM data location

PKA RAM offset address

0x6C

0x90

0xB4

0x90

0xB4

0x00

Size (words)

EOS

Figure 22. BlueNRG-1 pin-out top view (QFN32) shows the QFN32 pin out and

EOS

An error value of 1 indicates that input point P does not satisfy the curve equation; in this case, the computation is very short. If the calculation returns an error value of 0, the result is valid.

The maximum length of data is calculated by:

Max. EOS = (max_ecc_size / word_size) + 1

If ECC P256 is used, the PKA core needs an operand of 9 (256/32 + 1) words. When loading a 256-bit (8 word) input, an additional word is requested and must be filled with zero.

The starting point P for the computation is:

• PX = (0x6B17D1F2, 0xE12C4247, 0xF8BCE6E5, 0x63A440F2, 0x77037D81, 0x2DEB33A0, 0xF4A13945,

0xD898C296)

• PY = (0x4FE342E2, 0xFE1A7F9B, 0x8EE7EB4A, 0x7C0F9E16, 0x2BCE3357, 0x6B315ECE, 0xCBB64068,

0x37BF51F5)

PKA registers

PKA peripheral base address (PKA_BASE_ADDR) 0xC0000000

Address offset

0x00

0x04

0x08

Name

CSR

ISR

IEN

Table 193. PKA registers

Reset

0x00000002

0x00000000

Description

Command and status register

Interrupt status register

Interrupt enable register

Table 194. PKA – CSR register description: address offset PKA_BASE_ADDR+0x00

Bit

Field name

READY

Reset

Description

•

PKA start processing command:

0: has no effect.

1: starts the processing.

After this bitfield is set to 1, it must be written back to 0 manually.

•

PKA readiness status:

0: the PKA is computing. It is not ready.

1: the PKA is ready to start a new process.

6:2 RESERVED 0x00 RW

7 SFT_RST 0 W

The rising edge of the READY bit set the PROC_END flag in the ISR register.

RESERVED

•

PKA software reset:

0: has no effect.

1: reset the PKA peripheral.

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Public key accelerator (PKA)

Bit

Bit Field name Reset RW

31:8 RESERVED 0x00 RW

Description

After this bitfield is set to 1, it must be written back to 0 manually.

RESERVED

Table 195. PKA – ISR register description: address offset PKA_BASE_ADDR+0x04

Bit

Field name

PROC_END

RESERVED

RAM_ERR

Reset

RW Description

•

PKA process ending interrupt. When read:

0: no event.

1: PKA process is ended.

•

When written:

0: no effect.

1: clears the PKA process ending interrupt.

After this bitfield is set to 1, it must be written back to 0 manually.

RW RESERVED

•

RAM read/write access error interrupt. When read:

0: all AHB read or write access to the PKA RAM occurred while the PKA was stopped.

1: All the AHB read or write accesses to the PKA RAM occurred while the PKA was operating and using the internal RAM. These reads or writes could not succeed as the PKA internal RAM is disconnected from the AHB bus when the

PKA is operating (READ bit low).

•

When written:

0: no effect.

1: clears the RAM access error interrupt.

After this bitfield is set to 1, it must be written back to 0 manually.

3 ADD_ERR 0 RW

•

AHB address error interrupt. When read:

0: All AHB read or write access to the PKA RAM occurred in a mapped address range.

1: All the AHB read or write access to the PKA RAM occurred in an unmapped address range.

•

When written:

0: no effect.

1: clears the AHB address error interrupt.

31:4 RESERVED 0x00000000 RW

After this bitfield is set to 1, it must be written back to 0 manually.

RESERVED

Table 196. PKA – IEN register description: address offset PKA_BASE_ADDR+0x08

Field name

PROCEND_EN

RESERVED

RAMERR_EN

ADDERR_EN

Reset

Description

•

Process ended interrupt enable.

0: interrupt disabled.

1: interrupt enabled.

RESERVED

•

RAM access error interrupt enable.

0: interrupt disabled.

1: interrupt enabled.

•

AHB address error interrupt enable.

0: interrupt disabled.

1: interrupt enabled.

page 121/167

BlueNRG-1

TX/RX event alert

Note:

3.20

Note:

3.21

3.21.1

3.22

3.22.1

Bit

31:4

Field name

RESERVED

Reset

Description

RESERVED

All RESERVED fields inside registers must always be written with their default value.

TX/RX event alert

The BlueNRG-1 is provided with the ANATEST1 (pin 14 for QFN32 package and pin D4 for WCSP34 package) signal which alerts forthcoming transmission or reception event. The ANATEST1 pin switches to high level before transmission and before reception. Then, it switches to low level at the end of the event. The signal can be used to control external antenna switching and to support coexistence with other wireless technologies.

In this mode, the DIO14 cannot be used and it must be set as default (input pull-down).

SWD debug feature

The BlueNRG-1 embeds the ARM serial wire debug (SWD) port. It is two pins (clock and single bi-directional data) debug interface, providing all the debug functionality plus real-time access to system memory without halting the processor or requiring any target resident code.

Pin functionality

SWCLK

SWDIO

Table 197. SWD port

Pin name

IO9

IO10

Pin description

SWD clock signal

SWD data signal

The Cortex-M0 subsystem of the BlueNRG-1 embeds two breakpoints and one watchpoint.

Debugging tips

There are certain situations where debug access is disabled and the chip cannot be accessed, including:

• application that disables debug pins

• application that set the device in sleep or standby state, in which the debug port is not powered.

These cases are common during application development and device can end up in a state where debug access is no longer possible. To recover this situation, it is recommended to force IO7 pin high and hardware reset the device in order to force execution of the updater code (see Pre-programmed bootloader). The user can then connect with SWD interface and erase the device Flash memory.

Bluetooth low energy radio

The BlueNRG-1 integrates an RF transceiver compliant to the Bluetooth specification and to the standard national regulations in the unlicensed 2.4 GHz ISM band.

The RF transceiver requires very few external discrete components. It provides 96 dB link budgets with excellent link reliability, keeping the maximum peak current below 15 mA.

In transmit mode, the power amplifier (PA) drives the signal generated by the frequency synthesizer out to the antenna terminal through a very simple external network. The power delivered as well as the harmonic content depends on the external impedance seen by the PA.

Radio operating modes

•

Several operating modes are defined for the BlueNRG-1 radio:

• Reset mode

Sleep mode

Active mode

DS11481 - Rev 10 page 122/167

3.23

Note:

3.24

BlueNRG-1

Pre-programmed bootloader

• Radio mode

– RX mode

– TX mode

In Reset mode, the BlueNRG-1 is in ultra-low power consumption: all voltage regulators, clocks and the RF interface are not powered. The BlueNRG-1 enters Reset mode by asserting the external Reset signal. As soon as it is de-asserted, the device follows the normal activation sequence to transit to active mode.

In sleep mode either the low speed crystal oscillator or the low speed ring oscillator are running, whereas the high speed oscillators are powered down as well as the RF interface. The state of the BlueNRG-1 is retained and the content of the RAM is preserved.

While in sleep mode, the BlueNRG-1 waits until an internal timer expires and then it goes into active mode.

In active mode the BlueNRG-1 is fully operational: all interfaces, including RF, are active as well as all internal power supplies together with the high speed frequency oscillator. The MCU core is also running.

Radio mode differs from active mode as also the RF transceiver is active and it is capable of either transmitting or receiving.

Pre-programmed bootloader

•

BlueNRG-1 device has a pre-programmed bootloader supporting UART protocol with automatic baudrate detection. Main features of the embedded bootloader are:

• Auto baudrate detection up to 460 kbps

Flash mass erase, section erase

Flash programming

Flash readout protection enable/disable

The pre-programmed bootloader is an application which is stored on the BlueNRG-1 internal ROM at manufacturing time by STMicroelectronics. This application allows upgrading the device Flash with a user application using a serial communication channel (UART).

Bootloader is activated by hardware by forcing IO7 high during power-up or hardware Reset, otherwise, application residing in Flash will be launched.

The customer application must ensure that IO7 is forced low during power up. Bootloader protocol is described in a separate application note.

Unique device serial number

The BlueNRG-1 device has a unique six-byte serial number stored at address 0x100007F4: it is stored as two words (8 bytes) at addresses 0x100007F4 and 0x100007F8 with unique serial number padded with 0xAA55.

DS11481 - Rev 10 page 123/167

BlueNRG-1

Pin description

Pin description

The BlueNRG-1 is proposed in two package versions: WCSP34 offering 14 GPIOs and QFN32 offering 15

GPIOs.

Figure 23. BlueNRG-1 ball out top view (WCSP34) shows the WCSP34 ball out.

Figure 21. BlueNRG-1 pin-out top view (QFN32)

DIO10

DIO9

DIO8

DIO7

DIO6

VBAT3

DIO5

DIO4

32 31 30 29 28 27 26 25

GND pad

9 10 11 12 13 14 15 16

VBAT1

SXTAL0

SXTAL1

RF0

RF1

VBAT2

FXTAL0

FXTAL1

DS11481 - Rev 10 page 124/167

Figure 22. BlueNRG-1 ball out top view (WCSP34)

BlueNRG-1

Pin description

DS11481 - Rev 10 page 125/167

Figure 23. BlueNRG-1 ball out bottom view (WCSP34)

BlueNRG-1

Pin description

DS11481 - Rev 10

QFN32

Pin

WCSP34

Name

IO10

IO9

IO8

IO7/BOOT (1)

IO6

VBAT3

IO5

IO4

IO3

IO2

IO1

IO0

ANATEST0/IO14 (2)

ANATEST1

0x2000_0000 – 0x2000_2FFF (1)

ADC1

I/O

I/O

VDD

I/O

Table 198. Pinout description

Description

General purpose digital I/O

Bootloader pin/

General purpose digital I/O

Battery voltage input

General purpose digital I/O

Analog output/

General purpose digital I/O

Analog output

ADC input 1 page 126/167

DS11481 - Rev 10

BlueNRG-1

Pin description

Pin

WCSP34

QFN32

Name I/O Description

SMPSFILT2

VDD1V2

IO13

IO12

TEST

IO11

GND

ADC2

FXTAL1

FXTAL0

VBAT2

RF1

RF0

SXTAL1

SXTAL0

VBAT1

RESETN

SMPSFILT1

VDD

I/O

VDD

I/O

GND

ADC input 2

16/32 MHz crystal

Battery voltage input

Antenna + matching circuit connection

32 kHz crystal

Battery voltage input

System reset

SMPS output to external filter

SMPS output to external filter/battery voltage input

1.2 V digital core output

General purpose digital Input

Test pin put to GND

General purpose digital I/O

Ground

1. The pin IO7/BOOT is monitored by bootloader after power up or hardware Reset and it should be low to prevent unwanted bootloader activation.

2. Pins used for the crystal startup measurement.

page 127/167

DS11481 - Rev 10

BlueNRG-1

Memory mapping

Memory mapping

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and highest numbered byte the most significant.

The addressable memory space is divided into 16 main blocks, each 256 MB. All the memory areas that are not allocated to on-chip memories and peripherals are considered “RESERVED”.

For the detailed mapping of an available memory and register areas, please refer to the memory map in table below and to the register lists detailed in each of the peripheral sections.

Address

0x0000_0000 – 0x0000_07FF

0x1000_0000 – 0x1000_07FF

0x1004_0000 – 0x1006_7FFF

0x2000_3000 – 0x2000_5FFF

0x2000_6000 – 0x3FFF_FFFF

0x4000_0000

0x4010_0000

0x4020_0000

0x4030_0000

0x4040_0000

0x4050_0000

0x4060_0000

0x4070_0000

0x4080_0000

0x4090_0000

0x40A0_0000

0x40B0_0000

0x40C0_0000

0x40D0_0000

0x40E0_0000

0x40F0_0000

0x4100_0000

0x4800_0000

0x4810_0000

0x5000_0000

0xA000_0000

0xB000_0000

0xC000_0000

0xC000_0400

Table 199. Memory mapping

Cortex-M0 address map

Code

SRAM0 always on

SRAM1 switchable

APB peripheral

AHB peripheral

4 kB

Size

2 kB

160 kB

12 kB

Description

ROM

Flash

SRAM

RESERVED

GPIO

Flash controller

System controller

UART

SPI

RESERVED

Watchdog

ADC

Clock generator

I2C2

I2C1 (2)

AHB up converter

MFT1

MFT2

RTC

RESERVED

BLE controller

BLE clock generator

RESERVED

DMA controller

RNG

PKA

PKA RAM page 128/167

BlueNRG-1

Memory mapping

Address

0xE000_0000 – 0xE00F_FFFF

0xE010_0000 – 0xEFFF_FFFF

0xF000_0000 – 0xFFFF_FFFF

Cortex-M0 address map

Private peripheral bus

RESERVED

1. 0x200000C0 - 0x200002CB reserved for radio controller.

2. The I²C 1 is not available in WLCSP34 package.

Size

1 MB

256 MB

Description

Cortex-M0 registers

RESERVED

All the peripherals are addressed by APB, except DMA, RNG and PKA peripherals that are addressed by AHB.

The peripherals DMA, RNG and PKA that are addressed through the AHB, must be accessed only with 32-bit accesses. Any 8-bit or 16-bit access generates an AHB error leading to a hard fault on Cortex-M0.

DS11481 - Rev 10 page 129/167

Application circuit

The schematics below are purely indicative.

Figure 24. Application circuit: active DC-DC converter QFN32 package

BlueNRG-1

Application circuit

Figure 25. Application circuit: non-active DC-DC converter QFN32 package

DS11481 - Rev 10 page 130/167

Figure 26. Application circuit: active DC-DC converter WCSP34 package

BlueNRG-1

Application circuit

Figure 27. Application circuit: non active DC-DC converter WCSP34 package

DS11481 - Rev 10 page 131/167

DS11481 - Rev 10

C10

C11

C12

C13

C14

C15

C16

C17

Component

BlueNRG-1

Application circuit

Figure 28. Application circuit: active DC-DC converter QFN32 package with BALF-NRG-02D3 balun

1.7 V to 3.6 V Power Supply

C2 C1

C19

C3 C4

C6 C7

C15

DIO10

DIO9

DIO8

DIO7

DIO6

DIO5

DIO4

DIO10

DIO9

DIO8

DIO7

DIO6

VBAT3

DIO5

DIO4

BlueNRG-1

VBAT1

SXTAL0

SXTAL1

RF0

RF1

VBAT2

FXTAL0

FXTAL1

XTAL1

BALF-NRG-02D3

C18

C17

XTAL2

C16

C10

C13

Table 200. External component list

Description

Decoupling capacitor

DC-DC converter output capacitor

Decoupling capacitor for 1.2 V digital regulator

Decoupling capacitor

32 kHz crystal loading capacitor

RF balun/matching network capacitor

Decoupling capacitor

16/32 MHz crystal loading capacitor

16/32 MHz crystal loading capacitor page 132/167

Component

C18

C19

XTAL1

XTAL2

Description

Decoupling capacitor

DC-DC converter output capacitor

32 kHz crystal filter inductor

16/32 MHz crystal filter inductor

RF balun/matching network inductor

32 kHz crystal (optional)

16/32 MHz crystal

BlueNRG-1

Application circuit

DS11481 - Rev 10 page 133/167

Note:

BlueNRG-1

Absolute maximum ratings and thermal data

Absolute maximum ratings and thermal data

Table 201. Absolute maximum ratings

Pin

VBAT3, VBAT2, VBAT1, RESETN, SMPSFILT1,

SMPSFILT2

VDD1V2

DIO0 to DIO14, TEST

ANATEST0, ANATEST1, ADC1, ADC2

FXTAL0, FXTAL1, SXTAL0, SXTAL1

RF0, RF1

TSTG

VESD-HBM

Parameter

DC-DC converter supply voltage input and output -0.3 to +3.9

DC voltage on linear voltage regulator

DC voltage on digital input/output pins

DC voltage on analog pins

DC voltage on XTAL pins

DC voltage on RF pins

Storage temperature range

Electrostatic discharge voltage

Value Unit

-0.3 to +1.3

-0.3 to +3.9

-0.3 to +1.4

-40 to +125 °C

±2.0

Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referred to GND.

Symbol

Rthj-amb

Table 202. Thermal data

Parameter

Thermal resistance junction-ambient

Rthj-c Thermal resistance junction-case

Value

34 (QFN32)

50 (WLCSP34)

2.5 (QFN32)

25 (WLCSP34)

Unit

°C/W

DS11481 - Rev 10 page 134/167

BlueNRG-1

General characteristics

General characteristics

Symbol

VBAT

Table 203. Recommended operating conditions

Parameter

Operating battery supply voltage

Operating ambient temperature range

Min.

1.7

-40

Typ.

Max.

3.6

+105

Unit

°C

DS11481 - Rev 10 page 135/167

9.1

BlueNRG-1

Electrical specifications

Electrical specifications

Electrical characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

= 3.0 V. All performance data are referred to a 50 Ω antenna connector, via reference design, QFN32 package version.

Symbol

BAT

Table 204. Electrical characteristics

Parameter

Supply current

Test conditions Min.

Power consumption when DC-DC converter active

Reset

Standby

Sleep mode: 32 kHz XO ON

(24 kB retention RAM)

–

Sleep mode: 32 kHZ RO ON

(24 kB retention RAM)

Active mode: CPU, Flash and

RAM on

–

– RX

TX +8 dBm

TX +4 dBm

TX +2 dBm

TX -2 dBm

TX -5 dBm

TX -8 dBm

TX -11 dBm

TX -14 dBm

–

Supply current

Power consumption when DC-DC converter not active

Reset –

– Standby

Sleep mode: 32 kHz XO ON

(24 kB retention RAM)

–

Sleep mode: 32 kHZ RO ON

(24 kB retention RAM)

Active mode: CPU, Flash and

RAM on

–

Supply current

TX +8 dBm

TX +4 dBm

TX +2 dBm

TX -2 dBm

–

TX -5 dBm

TX -8 dBm

TX -11 dBm

Typ.

500

0.9

2.1

1.9

8.3

7.7

7.1

6.8

6.6

7.7

15.1

10.9

500

0.9

2.1

3.3

14.5

28.8

20.5

17.2

15.3

12.3

Max.

–

Unit nA nA

µA mA mA mA nA nA

µA mA mA mA

DS11481 - Rev 10 page 136/167

9.1.1

BlueNRG-1

Electrical characteristics

Symbol

BAT

Parameter

Supply current

Test conditions

TX -14 dBm

Min.

–

Typ.

Symbol

T(RST)L

TC1

TC2

VIL

VIH

VOL

VOH

Test conditions

IOL (low drive strength)

IOL (high drive strength)

IOH (low drive strength)

IOH (high drive strength)

IOL = 3 mA

IOH = 3 mA

TC (VOL = 0.4 V)

TC1 (VOL = 0.42

TC2 (VOL = 0.45

TC (VOL = 0.4 V)

TC1 (VOL = 0.42

TC2 (VOL = 0.45

TC (VOH = 2.4 V)

TC1 (VOH = 1.72

TC2 (VOH = 1.35

TC (VOH = 2.4 V)

TC1 (VOH = 1.72

TC2 (VOH = 1.35

Static supply 1.7 V IPUD (current sourced/sinked from IOs with pull enabled)

Static supply 3.6 V

Table 205. Digital I/O specifications

Min.

Typ.

1.5

3.3

2.5

1.8

0.65*VDD

0.7*VDD

–

5.6

6.6

11.2

13.2

10.6

7.2

19.2

12.9

5.5

Peripheral current consumption

Peripheral

GPIO

Flash controller

System controller

Table 206. Peripheral current consumption

Typical consumption

= 3.0 V, T

= 25 °C

11.0

6.0

0.75

Max.

0.3*VDD

0.4

Max.

–

Unit ms

V mA

µA

Unit mA

Unit

μA

DS11481 - Rev 10 page 137/167

Note:

9.2

9.3

BlueNRG-1

RF general characteristics

Peripheral

UART

SPI

Watchdog

ADC

I2C1

I2C2

MFT1

MFT2

RTC

DMA

RNG

PKA

Typical consumption

= 3.0 V, T

= 25 °C

77.0

41.0

4.0

5.0

92.0

7.5

16.5

25.0

26.0

Unit

μA

The values are calculated as the increment to the current consumption when the peripheral is activated. The peripheral is activated if the related clock is provided.

RF general characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

=3.0 V. All performance data are referred to a 50 Ω antenna connector, via reference design, QFN32 package version.

Symbol

FREQ

FCH

RFch

Table 207. RF general characteristics

Parameter

Frequency range

Channel spacing

RF channel center frequency

Test conditions Min.

2400

–

2402

Typ.

–

Max.

2483.5

–

2480

Unit

MHz

RF transmitter characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

= 3.0 V. All performance data are referred to a 50 Ω antenna connector, via reference design, QFN32 package version.

Symbol Parameter

MOD Modulation scheme

BT Bandwidth-bit period product

Mindex Modulation index

DR Air data rate

PMAX Maximum output power

PRFC Minimum output power

Table 208. RF transmitter characteristics

Test conditions

At antenna connector

–

Min.

0.5

Typ.

Max. Unit

GFSK

–

-16.5

– Mbps

+10 dBm

– dBm

DS11481 - Rev 10 page 138/167

9.4

BlueNRG-1

RF receiver characteristics

Symbol Parameter Test conditions

PBW1M

6 dB bandwidth for modulated carrier (1

Mbps)

Using resolution bandwidth of

100 kHz

PRF1 1 st adjacent channel transmit power 2 MHz

Using resolution bandwidth of

100 kHz and average detector

PRF2

2 nd Adjacent channel transmit power >3

MHz

ZLOAD Optimum differential load

Using resolution bandwidth of

100 kHz and average detector

@ 2440 MHz

1. Simulated value.

500

Min.

–

Typ.

Max. Unit

– kHz

– -35 – dBm

– -40

–

25.4 + j20.8 (1)

–

– dBm

Ω

RF receiver characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

=3.0 V. All performance data are referred to a 50 Ω antenna connector, via reference design, QFN32 package version.

Table 209. RF receiver characteristics

Symbol Parameter Test conditions Min.

Typ.

RXSENS

PSAT zIN

Sensitivity

Saturation

Input differential impedance

BER <0.1%

@ 2440 MHz

RF selectivity with BLE equal modulation on interfering signal

C/ICOchannel

Co-channel interference

Wanted signal = -67 dBm, BER ≤

0.1%

C/I1 MHz

C/I2 MHz

C/I3 MHz

C/I≥4 MHz

C/I≥6 MHz

C/I≥25 MHz

Adjacent (+1 MHz) interference

Adjacent (+2 MHz) interference

Adjacent (+3 MHz) interference

Adjacent (≥ ± 4 MHz) interference

Adjacent (≥ ± 6 MHz) interference

Adjacent (≥ ±25 MHz) interference

Wanted signal = -67 dBm,

BER≤0.1%

Wanted signal = -67 dBm, BER ≤

0.1%

Wanted signal = -67 dBm, BER ≤

0.1%

Wanted signal = -67 dBm, BER ≤

0.1%

Wanted signal= -67 dBm BER ≤

0.1%

Wanted signal= -67 dBm, BER ≤

0.1%

C/IImage

Image frequency interference

-2 MHz

Adjacent (±1 MHz) interference to inband image frequency

C/IImage±1 MHz

-1 MHz

-3 MHz

P_IM(3)

P_IM(-3)

Wanted signal = -67 dBm, BER ≤

0.1%

Wanted signal = -67 dBm, BER ≤

0.1%

Intermodulation characteristics (CW signal at f

, BLE interfering signal at f

)

Input power of IM interferes at 3 and

6 MHz distance from wanted signal

Wanted signal = -64 dBm, BER ≤

0.1%

Input power of IM interferes at -3 and

-6 MHz distance from wanted signal

Wanted signal = -64 dBm, BER ≤

0.1%

-88

25.5-j14.2

-40

-47

-46

-48

-70

-16

-23

-34

-48

Max. Unit dBm dBm

Ω dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm dBm

DS11481 - Rev 10 page 139/167

9.5

9.5.1

BlueNRG-1

High speed crystal oscillator characteristics

Symbol

P_IM(4)

P_IM(5)

Parameter Test conditions

Input power of IM interferes at ±4 and

±8 MHz distance from wanted signal

Input power of IM interferes at ±5 and

±10 MHz distance from wanted signal

Wanted signal = -64 dBm, BER ≤

0.1%

Wanted signal = -64 dBm, BER ≤

0.1%

Min.

Typ.

-34

Max. Unit dBm

-34 dBm

High speed crystal oscillator characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

= 3.0 V.

Symbol fNOM fTOL

Table 210. High speed crystal oscillator characteristics

Parameter

Nominal frequency

Test conditions

Frequency tolerance

Includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance

ESR Equivalent series resistance

PD Drive level

Min. Typ. Max. Unit

– 16/32 – MHz

– – ±50 ppm

–

100 Ω

100 µW

High speed crystal oscillator

The BlueNRG-1 includes a fully integrated low power 16/32 MHz Xtal oscillator with an embedded amplitude regulation loop. In order to achieve low power operation and good frequency stability of the XTAL oscillator, certain considerations with respect to the quartz load capacitance C0 need to be taken into account.

Figure 30. High speed oscillator block diagram

shows a simplified block diagram of the amplitude regulated oscillator used on the BlueNRG-1.

DS11481 - Rev 10 page 140/167

BlueNRG-1

High speed crystal oscillator characteristics

Figure 29. High speed oscillator block diagram

DS11481 - Rev 10

Low power consumption and fast startup time is achieved by choosing a quartz crystal with a low load capacitance C0. A reasonable choice for capacitor C0 is 12 pF. To achieve good frequency stability, the following equation needs to be satisfied:

∁0 =

∁1′*∁2′

∁1 + ∁2

(6)

Where C

’=C and C

PCB2

PCB1

PAD

, C

’= C

PCB2

are PCB routing parasites and C

PAD

PAD, where C

and C

are external (SMD) components, C

PCB1

is the equivalent small-signal pad-capacitance. The value of C

PAD is around 0.5 pF for each pad. The routing parasites should be minimized by placing quartz and C

capacitors close to the chip, not only for an easier matching of the load capacitance C

, but also to ensure robustness against noise injection. Connect each capacitor of the Xtal oscillator to ground by a separate vias.

page 141/167

9.5.2

Note:

9.5.3

9.5.4

9.5.5

BlueNRG-1

High speed crystal oscillator characteristics

Low speed crystal oscillator characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

=3.0 V.

Symbol fNOM fTOL

Table 211. Low speed crystal oscillator characteristics

Parameter

Nominal frequency

Test conditions

Frequency tolerance

Includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance.

ESR Equivalent series resistance

PD Drive level

Min.

Typ.

Max. Unit

– 32.768

– kHz

–

±50 ppm

90 kΩ

0.1

µW

These values are the correct ones for NX3215SA-32.768 kHz-EXS00A-MU00003.

High speed ring oscillator characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

=3.0 V.

Symbol f

NOM

Parameter

Nominal frequency

Table 212. High speed ring oscillator characteristics

Test conditions Min.

Typ.

– 14

Max.

–

Unit

MHz

Low speed ring oscillator characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

=3.0 V, QFN32 package version.

Symbol

Table 213. Low speed ring oscillator characteristics

Parameter Test conditions

32 kHz ring oscillator (LSROSC)

Min.

Nominal frequency –

Typ.

Max.

Unit f

NOM

– kHz

N-fractional frequency synthesizer characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to T

= 25 °C, V

BAT

=3.0 V, f c

= 2440 MHz.

Symbol

PNSYNTH

LOCKTIME

TOTIME

Table 214. N-Fractional frequency synthesizer characteristics

Parameter

RF carrier phase noise

PLL lock time

PLL turn-on / hop time

Test conditions

At ±1 MHz offset from carrier

At ±3 MHz offset from carrier

Including calibration

Min.

Typ.

Max.

–

-113

-119

–

150

Unit dBc/Hz dBc/Hz

µs

DS11481 - Rev 10 page 142/167

9.5.6

BlueNRG-1

High speed crystal oscillator characteristics

Auxiliary block characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Typical values are referenced to T

= 25 °C, V

BAT

=3.0 V, f_

ADCclk

= 1 MHz. QFN32 package version.

Symbol

DDA

DDA, AVG

INP, iNN

Table 215. Auxiliary block characteristics

Parameter Test conditions

Analog-to-digital converter (ADC)

Analog supply voltage

Analog supply current Average current during conversion

Min.

Typ.

1.7

–

3.0

–

Input pin voltage With input attenuator -50 mV –

Max.

Unit

3.6

0.55

BAT

+50 mV) / input attenuation

V mA

SNR Diff

SNR SE 1

SNR SE 2

Signal-to-noise ratio

Differential input, with OSR = 200, PGA=0 dB. Sinewave with VinDC=0.6 V, Vpeak diff

= 0.85 V, Fin = 1 kHz

Single-ended input, with Vbias = 0.6 V,

OSR = 200, PGA=0 dB. Sinewave with

VinDC=0.6 V, Vpeak = 0.425 V, Fin = 1 kHz

Single-ended input, with Vbias = 1.2 V,

OSR = 200, PGA=0 dB. Sinewave with

VinDC=1.2 V, Vpeak = 0.85 V, Fin = 1 kHz

ENOB Diff Effective number of bits

ENOB SE 1a Effective number of bits

Differential input, with OSR = 200, PGA=0 dB. Sinewave with VinDC=0.6 V, Vpeak diff

= 0.85 V, Fin = 1 kHz

Single-ended input, with Vbias = 0.6 V,

OSR = 200, PGA=0 dB. Sinewave with

VinDC=0.6 V, Vpeak = 0.425 V, Fin = 1 kHz

ENOB SE 1b Effective number of bits

ENOB SE 2a Effective number of bits

ENOB SE 2b Effective number of bits

Single-ended input, with Vbias = 0.6 V,

OSR = 200, PGA=0 dB. Sinewave with

VinDC=0.6 V, Vpeak = 0.15 V, Fin = 1 kHz

Single-ended input, with Vbias = 1.2 V,

OSR = 200, PGA=0 dB. Sinewave with

VinDC=1.2 V, Vpeak = 0.85 V, Fin = 1 kHz

Single-ended input, with Vbias = 1.2 V,

OSR = 200, PGA=0 dB. Sinewave with

VinDC=1.2 V, Vpeak = 0.3 V, Fin = 1 kHz

Battery sensor

VBLTRANGE

VBLTERR

Battery level indicator range

Battery level indicator error

After calibration

Analog temperature sensor

TRANGE

TERR

Temperature range

Error in temperature

Brown-out reset (BOR)

VABOR

VDBOR

Ascending brown-out threshold

Descending brown-out threshold

–

1.8

-150

-40

-4

–

8.5

9.5

8.5

9.5

–

1.68

1.62

1.645

–

3.6

150

+105

1.7

– dB dB dB bit bit bit bit bit

V mV

°C

DS11481 - Rev 10 page 143/167

9.5.7

BlueNRG-1

High speed crystal oscillator characteristics

Symbol f

SCK f

PCLK

DuCy(CLK) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) tv(MO) th(SO) th(MO)

SPI characteristics

Parameter

SPI clock frequency

SPI duty cycle

Data input set-up time

Data input hold time

Data output access time

Data output disable time

Data output valid time

Data output hold time

Table 216. SPI characteristics

Conditions

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Master mode

Slave mode

Min.

4.7

0.00

6.4

6.3

-0.6

5.0

5.8

4.7

Typ.

12+(3/f

PCLK

)

2.00

Figure 30. SPI timing diagram - slave mode and CPHA = 0

Max.

20.2

21.0

20+(3/f

PCLK

)

13.4

Units

MHz

MHz ns ns ns ns

MHz

% ns ns ns ns ns ns

DS11481 - Rev 10 page 144/167

BlueNRG-1

High speed crystal oscillator characteristics

Figure 31. SPI timing diagram - slave mode and CPHA = 1

Figure 32. SPI timing diagram - master mode

DS11481 - Rev 10 page 145/167

BlueNRG-1

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

DS11481 - Rev 10 page 146/167

10.1

QFN32 package information

Figure 33. QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline

BlueNRG-1

QFN32 package information

DS11481 - Rev 10

QFN32_POA_8362854_B page 147/167

DS11481 - Rev 10

Dim.

K e

A3 b

BlueNRG-1

QFN32 package information

Table 217. QFN32 (5 x 5 x 1 pitch 0.5 mm) mechanical data

Min.

0.80

0.18

Typ.

0.85

0.02

0.20 REF

0.25

5.00 BSC

3.2

0.5 BSC

0.40

0.30

0°

0.20

Figure 34. QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A"

Max.

1.00

0.05

0.30

3.70

0.50

14° page 148/167

10.2

BlueNRG-1

WLCSP34 package information

Figure 35. WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline

See Note 1

DS11481 - Rev 10

WLCSP34_POA_8165249

The corner of terminal A1 must be identified on the top surface by using a laser marking dot.

page 149/167

BlueNRG-1

WLCSP34 package information

Table 218. WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data

Dim.

Min.

A1 b

E1 e f g ccc

2.50

2.60

1. The typical ball diameter before mounting is 0.25 mm.

2. D = f + D1 + f.

3. E = g + E1 + g.

mm.

Typ.

0.20

0.27

2.56

2.00

2.66

2.00

0.40

0.28

0.33

Max.

0.50

2.58

2.68

0.05