STMicroelectronics VD6283TX Datasheet
Reklama
Reklama
VD6283TX
Datasheet
Hybrid filter multispectral sensor with light flicker engine
Order code
VD6283TX45/1
Product version
Red, green, blue, visible, IR, and clear
Features
• Miniature optical module
– 1.83 x 1.0 x 0.55 mm
– Optical BGA, 6-balls, reflowable package
– Operates with cover glass on top
• ALS operation with 6 independent channels
– Advanced hybrid filters with high photocount response
– Parallel sensing of all channels: red, green, blue, IR, clear, and visible
– Operating conditions: 7 mLux to 30 kLux (green channel)
• Light flicker extraction
– Innovative readout architecture to extract AC light flicker signal
– From 100 Hz to 2 kHz frequency detection, sine or square wave
• Software driver provided by ST
• I2C interface up to 1 Mbit/s (Fast mode plus)
• 1.8 V power supply
• Low-power consumption
• Operating temperature -30 to 85 °C
Applications
• True tone color-sensing IC for screen brightness adjustment, and white balance color assistance
• Lux and CCT measurement
• Light frequency extraction for flicker correction assistance
Description
The VD6283 (1.83 x 1.0 x 0.55 mm) is ST's new color sensor with advanced light flicker extraction. Light measurement is fast and accurate thanks to an individual
ADC and a readout for each color channel. The VD6283 uses hybrid color filters with precise responses allowing accurate computation of the correlated color temperature
(CCT) and Lux information. The VD6283 can be used for display brightness management or scene light correction.
With a patented architecture and a high-performance photodiode design, the VD6283 can extract light flickering frequencies to avoid “banding effects” on videos, or check that they are safe for human eye. Additionally, the VD6283 is the only sensor able to extract different light flicker waveforms from 100 Hz and 2 kHz, including LED square signals, that can run flicker operations simultaneously with ALS operations.
DS13735 - Rev 1 - May 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
VD6283TX
Product overview
Product overview
Parameter
Package type
Product size
Operating voltage
Operating temperature
6 ALS channels
1 flicker channel
I2C
Table 1. Technical specifications
Value
Optical module with thin glass – 6 ball BGA
1.83 x 1.0 x 0.55 mm
1.8 V typical (1.65 V to 1.95 V)
-30 to 85 °C
Red, visible, blue, green, IR, and clear
Flicker channel using any single channel from above
(user selectable)
1 MHz Fast mode plus compatible, default address = 0x40h (write)
Figure 1. System block diagram (full options)
VDD
OSC OTP
AC Light Flicker
Extraction engine
PDM
GPIO1
GPIO2
Green
Clear
IR
Red
Blue
Visible
Dark
GND
ADC
ADC
ADC
ADC
ADC
ADC
ALS Control
&
Data engine
I²C
SCL
SDA
DS13735 - Rev 1 page 2/59
DS13735 - Rev 1
VD6283TX
Product overview
Table 2. VD6283TX45/1 channel affectation
Channel number
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Filter color
Red
Visible
Blue
Green
IR
Clear
Parameter
I2C
Channels
ADC type
Table 3. Key functional parameters
Exposure time (EXTIME)
Readout time
Analog gain
Inter measurement period
Light analog flicker detection
Value
Fast mode (400 kHz) and Fast mode plus (1 MHz)
Programmable I2C address (see Section 3.4.2 I2C new device address
)
6 color channels with independent, parallel reading for ALS or flicker operations: red, visible, blue, green, IR, and clear.
1 dedicated fast channel for light flicker measurement
1 internal dark channel
24 bit (16 bit + 8 bit, for high accuracy under low light)
Integration time step size: 1.6 ms typical
Number of integration steps: 1 to 1024 (1.6 ms to 1.6 s)
ALS readout: 6 ms typical (fixed) for all channels together.
This must be added to EXTIME for overall sensing operations.
For example, EXTIME 24 ms and readout 6 ms -> 30 ms overall operation (33 Hz).
AC flicker frequency: raw signal (PDM) is output continuously through GPIO2.
15 programmable gains for high-dynamic range: 66x, 50x,
33x, 25x, 16x, 10x, 7.1x, 5x, 3.33x, 2.5x, 1.67x, 1.25x, 1x,
0.83x, 0.71x.
Independent and selectable per channel
256 steps of 20 ms (from 0 ms to 5.12 s)
Minimum frequency detection: 100 Hz
Maximum frequency detection: 2 kHz
The PDM signal is routed out of GPIO2 and filtered by an external RC filter to get a continuous analog signal
(
Figure 4. Application schematic, ALS and flicker in analog format
)
FFT (Fast Fourier Transform) computation required at host level for highest frequency detection accuracy. This is recommended for better screening of the light fundamental and harmonic extraction, especially with respect to multi tone frequencies (combined light sources).
page 3/59
2
VD6283TX
Ballout and application information
Ballout and application information
The figure below shows the ballout of the VD6283 (top view with balls down and silicon/glass up).
The table below provides the ball description and voltages.
Figure 2. Ballout (top view)
DS13735 - Rev 1
Ball number
A1
A2
A3
B1
B2
B3
Signal name
VDD
SDA
VSS
GPIO2
GPIO1
SCL
Table 4. Ball description
Signal type
Supply
Digital input/output
Ground
Digital input/output
Digital input/output
Digital input
Typ. voltage
VDD
GND
VDD
Description
Supply, to be connected to main supply
I2C serial data
To be connected to main ground
AC flicker signal output (PDM data)
Interrupt output
I2C serial clock page 4/59
DS13735 - Rev 1
VD6283TX
Ballout and application information
Figure 3. Application schematic, ALS operation only with interrupt handshake
1v8
1v8
C2
1 µF
C1
100 nF
VDD
VSS
VD628x
GPIO1
SCL
SDA
GPIO2
20 k Rp Rp
Host
20k
1v8
C1
100nF
Figure 4. Application schematic, ALS and flicker in analog format
1v8
20k Rp Rp
VDD
VSS
VD628x
GPIO1
SCL
SDA
GPIO2
LPF
Freq Cutoff= 8kHz
20k
1nF
ADC_in
Host
I2C mode
Table 5. Recommended pull up resistors and SDA driver settings for I2C modes
Standard and Fast mode
I2C bus capacitive load range (pF)
10 - 115
115 - 225
225 - 400
Pull up resistor Rp
(Ω)
1.65 k
909
562
SDA driver configuration (mA)
SDA_DRV_CFG = ‘000’ (4 mA) or
SDA_DRV_CFG = ‘001’ (8 mA) or
SDA_DRV_CFG = ‘010’ (12 mA) or
SDA_DRV_CFG = ‘011’ (16 mA)
Fast mode plus
13 - 35
35 - 95
95 - 150
150 - 550
1.62 k
750
453
154
SDA_DRV_CFG = ‘100’ (20 mA) page 5/59
VD6283TX
System description
3
System description
3.1
Functional description
The figure below shows the system level functional description. The host customer application controls the
VD6283 device using a software (SW) driver API (application programming interface).
This software driver provides a set of high-level functions that allow the user to control the VD6283 without worrying about I2C register control. Such control includes: start/stop ALS sensing, color channel selection, activate AC flicker sensing and/or ALS sensing, set the exposure time or set the analog gain. This helps customer evaluation, software development, and prototype building.
Figure 5. System functional description
Customer
Application
driver
VD6283
Driver/API
I2C
VD6283
DIGITAL &
I2C regs
3.2
3.3
Sensing operation
The color channels can be individually enabled to optimize power consumption through the I2C (or SW API):
• Up to 6 ALS channels can be read in parallel (ALS mode): red, visible, blue, green, IR, and clear channels can be enabled individually.
• Up to 5 ALS channels can be read in parallel, together with 1 flicker channel (ALS and Flicker mode). The
RGB - IR- visible channels can be sensed in ALS mode while AC flicker mode is configured with the clear channel. Note that in this configuration, the selected channel routed to the AC light flicker module (i.e. clear) cannot provide an ALS value at the same time.
Exposure time (EXTIME) is defined by the user and is identical for all channels in ALS operation. EXTIME can be set from 1.6 ms up to 1.6 s. After each EXTIME duration, a fixed period of time of ~6 ms takes place to allow counts to be converted into digital information. This housekeeping time must be considered in the overall ALS speed framerate.
Individual analog gain (AGAIN) can be applied by the user for each channel, including the channel routed to the
AC light flicker module.
Operating modes
The VD6283 can stream the following data continuously: ALS color data over the I2C and raw flicker data over the GPIO2 ball. Streaming starts when the host microcontroller sends a “start/stop” command. Then, the N-1 data measurements are automatically overwritten in the I2C registers with the latest N measurement batch.
The user can set an intermeasurement period through the software driver. This goes from 0 to 5.1 seconds, in steps of 20 ms (256 steps). This can be useful to reduce sensing frame rate and power consumption, without having the master microcontroller host awake during the inter measurement period.
ALS and flicker sensing are totally independent and can be activated/stopped individually.
The VD6283 can also work in a "continuous gated” way. Once measurement N is finished, the VD6283 waits for the microcontroller handshake to carry on to measurement N+1. I2C data are not refreshed until the next acknowledgment, whilst the PDM data are still streaming over the GPIO2 ball. The handshake mechanism is performed via I2C polling.
DS13735 - Rev 1 page 6/59
3.3.1
3.3.2
3.3.3
VD6283TX
Operating modes
Raw and calibration data
The VD6283 features an OTP memory bank to store calibration data. ST performs a light calibration of each individual channel in production. A calibration factor per channel is then stored in the VD6283 OTP memory. The user can retrieve both raw data and calibration data through the software driver.
Power up/Power down sequence
Following power up (t
PU
= 0.03 ms) of the VD6283, some internal registers must be initialized before any mode
(e.g. ALS or Flicker) can operate. To ensure proper initialization of the sensor, one dedicated API function
(STALS_Init) is available in the VD6283 software driver and should be called right after power up.
Before power down of the VD6283, one dedicated API function (STALS_Term) must be called.
Please note the API function STALS_Term should be called only before power down of the actual sensor.
24 bit/16 bit ADC readout
The VD6283 features a 24 bit ADC which converts light information into digital format (i.e. counts). Each channel count data is proportional to channel irradiance. Note that the minimum reported irradiance level (guaranteed by design) is 0x000100.
Figure 6. 24 bit ADC readout vs. light level
DS13735 - Rev 1
At low light levels, the ADC data low byte (ALS_CHx_DATA_L) is useful for improving sensing resolution. During nominal light conditions, the ALS_CHx_DATA_L byte can be discarded and the application can read the sixteen most significant bits of the ADC (ALS_CHx_DATA_H and ALS_CHx_DATA_M) using the software driver (16 bit
ADC format).
page 7/59
3.3.4
Note:
Note:
Note:
3.3.5
3.3.6
VD6283TX
Operating modes
Saturation
•
•
If an excessive light level is sensed by the VD6283, a saturation condition may occur. Digital saturation defines the maximum channel count value software can read. This value is dependent on the exposure time programmed before the ALS operation started.
If EXTIME ≤ 113.6 ms (71 steps), the saturation level is 910 counts/step
If EXTIME > 113.6 ms (71 steps) the saturation level is 65535 counts
Values based on 16-bit ADC format
step = 1.6 ms (see Table 15. ALS operating characteristics
)
To ensure correct functioning of user applications, it is recommended that application software first checks
VD6283 channels are not saturated, before the calibration data are used further (e.g. for setting AWB, CCT etc.). This should be performed on VD6283 raw data.
AC light flicker extraction
The VD6283 features a digital module that extracts AC light signals (i.e. flicker) based on analog readouts over time. The AC signal produced is then coded in PDM format.
This PDM signal can be output on the GPIO2 pin. This digital signal can be filtered externally to produce a baseband analog signal of the AC flicker.
Flicker mapping configuration
Configuration
Analog flicker
Table 6. Flicker mapping configurations
GPIO1
Interrupt
GPIO2
PDM
External H/W
RC filter
Host I/F
ADC
Analog flicker connects the VD6283 flicker signal to an ADC module (i.e. host or other). External RC filtering is
DS13735 - Rev 1 page 8/59
3.4
3.4.1
VD6283TX
I2C interface
I2C interface
I2C protocol description
Device control and data transfer is performed through an I2C serial communication interface. The I2C interface uses two signals: the serial data line (SDA) and serial clock line (SCL). Each device connected to the bus uses a unique address and a simple master/slave relationship exists.
Both SDA and SCL lines are connected to a positive supply voltage using pull up resistors located on the host.
Lines are only active when driven low. When no data is transmitted both lines are high.
Clock signal (SCL) generation is performed by the master device. The master device initiates data transfer. The
I2C bus on the VD6283 has a maximum speed of 1 Mbit/s and the device supports a slave address of 0x40 (or
0x20 in 7 bits).
Figure 7. Data transfer protocol
Start condition
SDA
SCL
S
Acknowledge
MSB
1 2 3 4 5
Address or data byte
6 7
LSB
8
Ac/Am
Stop condition
P
Information is exchanged in 8 bit packets (bytes) always followed by an acknowledge bit, Ac for VD6283 acknowledge and Am for master acknowledge (host bus master). The internal data are produced by sampling
SDA at a rising edge of SCL. The external data must be stable during the high period of SCL. The exceptions to this are start (S) or stop (P) conditions when SDA falls or rises respectively, while SCL is high.
An I2C message contains a series of bytes preceded by a start condition and followed by either a stop or repeated start (another start condition but without a preceding stop condition) followed by another message. The first byte contains the device address and also specifies the data direction. If the least significant bit is low (that is,
0x40) the message is a master write command to the slave. If the LSB is set (that is, 0x41) then the message is a master read command from the slave.
Figure 8. I2C device address
MSBit
0 1 0 0 0 0 0
LSBit
R/W
All serial interface communications with the ambient light sensor must begin with a start condition. The sensor acknowledges reception of a valid address by driving the SDA line low. The state of the read/write bit (LSB of the address byte) is stored and the next byte of data, sampled from SDA, can be interpreted. During a write sequence the second byte received provides an 8 bit index which points to one of the internal 8 bit registers.
Figure 9. Data format (write)
Start
VD628x acknowledges valid address
S ADDRESS [7:0]
0x40 (write)
Ac INDEX[7:0]
Acknowledge from
Ac DATA[7:0]
VD628x
Ac P
Stop
As data are received by the slave, they are written bit by bit to a serial/parallel register. After each data byte has been received by the slave, an acknowledge is generated, the data are then stored in the internal register addressed by the current index.
During a read message, the contents of the register addressed by the current index are read out in the byte following the device address byte. The contents of this register are parallel loaded into the serial/parallel register and clocked out of the device by the falling edge of SCL.
DS13735 - Rev 1 page 9/59
DS13735 - Rev 1
VD6283TX
I2C interface
S
Figure 10. Data format (read)
0x40 (write)
ADDRESS[7:0] Ac INDEX[7:0] Ac P
S
0x41 (read)
ADDRESS[7:0] Ac DATA[7:0] Am P
At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device (that is, the VD6283 for a write and the host for a read).
A message can only be terminated by the bus master, either by issuing a stop condition or by a negative acknowledge (that is, not pulling the SDA line low) after reading a complete byte during a read operation.
The interface also supports auto-increment indexing. After the first data byte has been transferred, the index is automatically incremented by 1. The master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition. If the auto-increment feature is employed, the master does not have to send address indexes between each data byte.
Figure 11. Data format (sequential write)
S
0x40 (write)
ADDRESS[7:0] Ac INDEX[7:0] Ac
DATA[7:0] Ac DATA[7:0] Ac DATA[7:0] Ac P
Figure 12. Data format (sequential read)
S
0x40 (write)
ADDRESS[7:0] Ac INDEX[7:0] Ac P
S
0x41 (read)
ADDRESS[7:0] Ac DATA[7:0] Am DATA[7:0] Am
DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P page 10/59
3.4.2
Note:
Note:
Note:
Note:
Note:
3.4.3
VD6283TX
I2C interface
Symbol
F
I2C t
LOW t
HIGH t
SP t
BUF t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R t
F t
SU.STO
t
VD.DAT
Ci/o
Cin
C
L
I2C new device address
The VD6283 provides a feature to assign a new I2C device address which should be used by the system implementer. The dedicated procedure below needs to be followed to re-program the device address.
1.
The device should be in the OFF state (i.e. powered off) for more than 1 ms.
2.
The host drives the GPIO1 signal to low state (i.e. GND level).
3.
Then, the system powers up the VD6283.
4.
After power up time has elapsed (tpu = 0.03 ms) , the host can send a valid I2C command with the desired new device address.
5.
Finally, wait until the host can release the GPIO1 signal (i.e. the host output should be set in high impedance).
The VD6283 I2C address is now changed and should be used as a reference address to communicate with the
VD6283.
Once the VD6283 address is changed, any incoming I2C transactions with the default address (0x40) will be ignored by the VD6283.
If the host attempts to change the VD6283 I2C address after the first I2C transaction is received, the device will ignore such a request.
The new I2C device address procedure should be repeated at each VD6283 power up.
During the VD6283 power up phase, it is recommended to suspend any I2C transactions to avoid unwanted I2C device address assignment.
The external pull up resistor on GPIO1 is required to avoid unintended I2C device address assignment. Please refer to the recommended application schematics.
I2C interface timing characteristics
Timing characteristics are shown in the tables below. Please refer to the figure below for parameters details.
Table 7. I2C interface - timing characteristics for Fast mode plus (1 MHz)
Parameter
Operating frequency
Clock pulse width low
Clock pulse width high
Pulse width of spikes which are suppressed by the input filter
Bus free time between transmissions
Start hold time
Start set-up time
Data in hold time
Data in set-up time
SCL/SDA rise time
SCL/SDA fall time
Stop set-up time
Data valid time
Input/output capacitance (SDA)
Input capacitance (SCL)
Load capacitance
Minimum
0
0.5
0.26
—
—
—
0.26
—
—
—
—
0.5
0.26
0.26
0
50
Typical
—
—
—
—
—
—
—
—
—
—
140
—
—
—
—
—
Maximum
1000
—
—
50
120
120
—
0.4
10
4
550
—
—
—
0.9
—
Unit kHz
µs ns
µs ns
µs pF
DS13735 - Rev 1 page 11/59
DS13735 - Rev 1
VD6283TX
I2C interface
Symbol
F
I2C t
LOW t
HIGH t
SP t
BUF t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R t
F t
SU.STO
t
VD.DAT
Ci/o
Cin
C
L
SDA
Table 8. I2C interface - timing characteristics for Fast mode (400 kHz)
Parameter
Operating frequency
Clock pulse width low
Clock pulse width high
Pulse width of spikes which are suppressed by the input filter
Bus free time between transmissions
Start hold time
Start set-up time
Data in hold time
Data in set-up time
SCL/SDA rise time
SCL/SDA fall time
Stop set-up time
Data valid time
Input/output capacitance (SDA)
Input capacitance (SCL)
Load capacitance
Minimum
0
1.3
0.6
—
0
100
—
1.3
0.6
0.6
—
0.6
—
—
—
—
Typical
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
125
Maximum
400
—
—
50
0.9
—
250
—
—
—
250
—
0.8
10
4
400
Figure 13. I2C timing characteristics stop start start
...
V
IH
V
IL stop
Unit kHz
µs ns
µs ns
µs pF
SCL
V
IH
V
IL t
BUF t
HD.STA
t
LOW t
R t
HD.DAT
All timings are measured from either V
IL
or V
IH
.
t
F t
HIGH t
SU.DAT
...
t
SU.STA
t
HD.STA
t
SU.STO
page 12/59
VD6283TX
VD6283 registers
4
VD6283 registers
4.1
4.2
Disclaimer
The VD6283 register descriptions are for information only. Unless otherwise stated, the VD6283 registers should be accessed only through the VD6283 software driver provided by STMicroelectronics.
I2C interface register map
This section describes in detail all the user-accessible device registers.
Table 9. Register summary
Address
0x00
0x01
0x02
0x03
0x04
0x06
0x07
0x08
0x0A
0x0B
0x0C
0x0E
0x0F
0x10
0x12
0x13
0x14
0x1E
0x25
0x26
0x27
0x28
0x16
0x17
0x18
0x1A
0x1B
0x1C
0x1D
Register name
DEVICE_ID
REVISION_ID
INTERRUPT_CTRL
ALS_CTRL
ALS_PERIOD
ALS_CH1_DATA_H
ALS_CH1_DATA_M
ALS_CH1_DATA_L
ALS_CH2_DATA_H
ALS_CH2_DATA_M
ALS_CH2_DATA_L
ALS_CH3_DATA_H
ALS_CH3_DATA_M
ALS_CH3_DATA_L
ALS_CH4_DATA_H
ALS_CH4_DATA_M
ALS_CH4_DATA_L
ALS_CH5_DATA_H
ALS_CH5_DATA_M
ALS_CH5_DATA_L
ALS_CH6_DATA_H
ALS_CH6_DATA_M
ALS_CH6_DATA_L
ALS_EXPOSURE_M
ALS_EXPOSURE_L
ALS_GAIN_CH1
ALS_GAIN_CH2
ALS_GAIN_CH3
ALS_GAIN_CH4
DS13735 - Rev 1 page 13/59
Address
0x29
0x2A
0x2D
0x2E
0x31
0x32
0x3C
0x41
VD6283TX
I2C interface register map
Register name
ALS_GAIN_CH5
ALS_GAIN_CH6
CHANNEL6_ENABLE
ALS_CHANNEL_ENABLE
AC_MODE_CTRL
PEDESTAL_VALUE
SDA_DRV_CFG
GPIO1_DRV_CFG
DS13735 - Rev 1 page 14/59
VD6283TX
I2C interface register description
4.3
4.3.1
7
Address:
Type:
Reset:
Description:
I2C interface register description
Device identification register
6 5 4
DEV_ID[7:0]
R
3
0x00
R
0x70
DEVICE_ID
[7:0] DEV_ID: VD6283 device identification
4.3.2
7
Address:
Type:
Reset:
Description:
Silicon revision identification register
6 5 4
REV_ID[7:0]
R
3
0x01
R
0xBD
REVISION_ID
[7:0] REV_ID: VD6283 silicon revision identification
2 1 0
2 1 0
DS13735 - Rev 1 page 15/59
VD6283TX
I2C interface register description
4.3.3
7
Address:
Type:
Reset:
Description:
Interrupt control register
6 5
RESERVED
R/W
4
0x02
R/W
0x00
INTERRUPT_CTRL
[1]
[0]
3
INTR_ST: interrupt status
1: no interrupt has been triggered or the last interrupt has not cleared
CLR_INTR: clear interrupt flag (handshake mechanism)
INTR_ST interrupt flag is cleared by CLR_INTR = '1' followed by CLR_INTR = '0'
2 1
INTR_ST
R
0
CLR_INTR
R/W
DS13735 - Rev 1 page 16/59
VD6283TX
I2C interface register description
4.3.4
7
Address:
Type:
Reset:
Description:
ALS control register
6 5
RESERVED
R/W
0x03
R/W
0x00
ALS_CTRL
4 3 2
ALS_CONT[1:0]
R/W
1 0
ALS_EN
R/W
[2:1]
[0]
ALS_CONT: ALS continuous mode selection
00: ALS mode 1: single ALS measurement request
01: reserved
11: ALS mode 3: continuous ALS measurement request defined by ALS_PERIOD with handshake mechanism from host.
ALS_EN: enable ALS operation
0: ALS operation is stopped (i.e. idle)
1: ALS operation started with ALS_CONT mode
DS13735 - Rev 1 page 17/59
VD6283TX
I2C interface register description
4.3.5
7
ALS period register
6 5
Address:
Type:
Reset:
Description:
0x04
R/W
0x00
ALS_PERIOD
[7:0] ALS_IM_PER: inter-measurement period
LSB = 20.5 ms
Min = 0 ms and Max = 5.22 s
4
ALS_IM_PER[7:0]
R/W
3 2 1 0
4.3.6
ALS channel 1 data register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ALS_CH1_DATA_H[7:0] ALS_CH1_DATA_M[7:0]
R
8 7 6 5 4 3 2
ALS_CH1_DATA_L[7:0]
1 0
Address:
Type:
Reset:
Description:
0x06 to 0x08
R
0x00
ALS_CH1_DATA
[23:16]
[15:18]
[7:0]
ALS_CH1_DATA_H: ALS channel 1 data high byte
ALS_CH1_DATA_M: ALS channel 1 data medium byte
ALS_CH1_DATA_L: ALS channel 1 data low byte
DS13735 - Rev 1 page 18/59
VD6283TX
I2C interface register description
4.3.7
ALS channel 2 data register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ALS_CH2_DATA_H[7:0] ALS_CH2_DATA_M[7:0]
R
8 7 6 5 4 3 2
ALS_CH2_DATA_L[7:0]
1 0
Address:
Type:
Reset:
Description:
0x0A to 0x0C
R
0x00
ALS_CH2_DATA
[23:16]
[15:18]
[7:0]
ALS_CH2_DATA_H: ALS channel 2 data high byte
ALS_CH2_DATA_M: ALS channel 2 data medium byte
ALS_CH2_DATA_L: ALS channel 2 data low byte
4.3.8
ALS channel 3 data register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ALS_CH3_DATA_H[7:0] ALS_CH3_DATA_M[7:0]
R
8 7 6 5 4 3 2
ALS_CH3_DATA_L[7:0]
1 0
Address:
Type:
Reset:
Description:
0x0E to 0x10
R
0x00
ALS_CH3_DATA
[23:16]
[15:18]
[7:0]
ALS_CH3_DATA_H: ALS channel 3 data high byte
ALS_CH3_DATA_M: ALS channel 3 data medium byte
ALS_CH3_DATA_L: ALS channel 3 data low byte
DS13735 - Rev 1 page 19/59
VD6283TX
I2C interface register description
4.3.9
ALS channel 4 data register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ALS_CH4_DATA_H[7:0] ALS_CH4_DATA_M[7:0]
R
8 7 6 5 4 3 2
ALS_CH4_DATA_L[7:0]
1 0
Address:
Type:
Reset:
Description:
0x12 to 0x14
R
0x00
ALS_CH4_DATA
[23:16]
[15:18]
[7:0]
ALS_CH4_DATA_H: ALS channel 4 data high byte
ALS_CH4_DATA_M: ALS channel 4 data medium byte
ALS_CH4_DATA_L: ALS channel 4 data low byte
4.3.10
ALS channel 5 data register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ALS_CH5_DATA_H[7:0] ALS_CH5_DATA_M[7:0]
R
8 7 6 5 4 3 2
ALS_CH5_DATA_L[7:0]
1 0
Address:
Type:
Reset:
Description:
0x16 to 0x18
R
0x00
ALS_CH5_DATA
[23:16]
[15:18]
[7:0]
ALS_CH5_DATA_H: ALS channel 5 data high byte
ALS_CH5_DATA_M: ALS channel 5 data medium byte
ALS_CH5_DATA_L: ALS channel 5 data low byte
DS13735 - Rev 1 page 20/59
VD6283TX
I2C interface register description
4.3.11
ALS channel 6 data register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ALS_CH6_DATA_H[7:0] ALS_CH6_DATA_M[7:0]
R
8 7 6 5 4 3 2
ALS_CH6_DATA_L[7:0]
1 0
Address:
Type:
Reset:
Description:
0x1A to 0x1C
R
0x00
ALS_CH6_DATA
[23:16]
[15:18]
[7:0]
ALS_CH6_DATA_H: ALS channel 6 data high byte
ALS_CH6_DATA_M: ALS channel 6 data medium byte
ALS_CH6_DATA_L: ALS channel 6 data low byte
4.3.12
15 14
ALS exposure register
13 12 11
RESERVED
10 9 8
R/W
Address:
Type:
Reset:
Description:
0x1D to 0x1E
R/W
0x0032
ALS_EXPOSURE
[9:0] EXTIME: exposure time = (EXTIME[9:0] + 1) x 16384/Fosc
Fosc = 10.24 MHz
Default value = 80 ms (min. = 1.6 ms and max. = 1.6 s)
7 6 5 4
EXTIME[9:0]
3 2 1 0
DS13735 - Rev 1 page 21/59
VD6283TX
I2C interface register description
4.3.13
7
ALS gain channel 1 register
6 5
RESERVED
4
R/W
Address:
Type:
Reset:
Description:
0x25
R/W
0x00
ALS_GAIN_CH1
[3:0] AGAIN: channel1 analog gain
0000: reserved
0001: AGAIN = 66.6x
0010: AGAIN = 50x
0011: AGAIN = 33x
0100: AGAIN = 25x
0101: AGAIN = 16x
0110: AGAIN = 10x
0111: AGAIN = 7.1x
1000: AGAIN = 5x
1001: AGAIN = 3.33x
1010: AGAIN = 2.5x
1011: AGAIN = 1.67x
1100: AGAIN = 1.25x
1101: AGAIN = 1x
1110: AGAIN = 0.83x
1111: AGAIN = 0.71x
3 2
AGAIN[3:0]
1 0
DS13735 - Rev 1 page 22/59
VD6283TX
I2C interface register description
4.3.14
7
ALS gain channel 2 register
6 5
RESERVED
4
R/W
Address:
Type:
Reset:
Description:
0x26
R/W
0x00
ALS_GAIN_CH2
[3:0] AGAIN: channel2 analog gain
0000: reserved
0001: AGAIN = 66.6x
0010: AGAIN = 50x
0011: AGAIN = 33x
0100: AGAIN = 25x
0101: AGAIN = 16x
0110: AGAIN = 10x
0111: AGAIN = 7.1x
1000: AGAIN = 5x
1001: AGAIN = 3.33x
1010: AGAIN = 2.5x
1011: AGAIN = 1.67x
1100: AGAIN = 1.25x
1101: AGAIN = 1x
1110: AGAIN = 0.83x
1111: AGAIN = 0.71x
3 2
AGAIN[3:0]
1 0
DS13735 - Rev 1 page 23/59
VD6283TX
I2C interface register description
4.3.15
7
ALS gain channel 3 register
6 5
RESERVED
4
R/W
Address:
Type:
Reset:
Description:
0x27
R/W
0x00
ALS_GAIN_CH3
[3:0] AGAIN: channel3 analog gain
0000: reserved
0001: AGAIN = 66.6x
0010: AGAIN = 50x
0011: AGAIN = 33x
0100: AGAIN = 25x
0101: AGAIN = 16x
0110: AGAIN = 10x
0111: AGAIN = 7.1x
1000: AGAIN = 5x
1001: AGAIN = 3.33x
1010: AGAIN = 2.5x
1011: AGAIN = 1.67x
1100: AGAIN = 1.25x
1101: AGAIN = 1x
1110: AGAIN = 0.83x
1111: AGAIN = 0.71x
3 2
AGAIN[3:0]
1 0
DS13735 - Rev 1 page 24/59
VD6283TX
I2C interface register description
4.3.16
7
ALS gain channel 4 register
6 5
RESERVED
4
R/W
Address:
Type:
Reset:
Description:
0x28
R/W
0x00
ALS_GAIN_CH4
[3:0] AGAIN: channel4 analog gain
0000: reserved
0001: AGAIN = 66.6x
0010: AGAIN = 50x
0011: AGAIN = 33x
0100: AGAIN = 25x
0101: AGAIN = 16x
0110: AGAIN = 10x
0111: AGAIN = 7.1x
1000: AGAIN = 5x
1001: AGAIN = 3.33x
1010: AGAIN = 2.5x
1011: AGAIN = 1.67x
1100: AGAIN = 1.25x
1101: AGAIN = 1x
1110: AGAIN = 0.83x
1111: AGAIN = 0.71x
3 2
AGAIN[3:0]
1 0
DS13735 - Rev 1 page 25/59
VD6283TX
I2C interface register description
4.3.17
7
ALS gain channel 5 register
6 5
RESERVED
4
R/W
Address:
Type:
Reset:
Description:
0x29
R/W
0x00
ALS_GAIN_CH5
[3:0] AGAIN: channel5 analog gain
0000: reserved
0001: AGAIN = 66.6x
0010: AGAIN = 50x
0011: AGAIN = 33x
0100: AGAIN = 25x
0101: AGAIN = 16x
0110: AGAIN = 10x
0111: AGAIN = 7.1x
1000: AGAIN = 5x
1001: AGAIN = 3.33x
1010: AGAIN = 2.5x
1011: AGAIN = 1.67x
1100: AGAIN = 1.25x
1101: AGAIN = 1x
1110: AGAIN = 0.83x
1111: AGAIN = 0.71x
3 2
AGAIN[3:0]
1 0
DS13735 - Rev 1 page 26/59
VD6283TX
I2C interface register description
4.3.18
7
ALS gain channel 6 register
6 5
RESERVED
4
R/W
Address:
Type:
Reset:
Description:
0x2A
R/W
0x00
ALS_GAIN_CH6
[3:0] AGAIN: channel6 analog gain
0000: reserved
0001: AGAIN = 66.6x
0010: AGAIN = 50x
0011: AGAIN = 33x
0100: AGAIN = 25x
0101: AGAIN = 16x
0110: AGAIN = 10x
0111: AGAIN = 7.1x
1000: AGAIN = 5x
1001: AGAIN = 3.33x
1010: AGAIN = 2.5x
1011: AGAIN = 1.67x
1100: AGAIN = 1.25x
1101: AGAIN = 1x
1110: AGAIN = 0.83x
1111: AGAIN = 0.71x
3 2
AGAIN[3:0]
1 0
DS13735 - Rev 1 page 27/59
4.3.19
7
Address:
Type:
Reset:
Description:
Channel 6 enable register
6 5
0x2D
R/W
0x00
CHANNEL6_ENABLE
4
RESERVED
R/W
3
[0] CH6_EN: channel6 operation activation
0: Channel6 is disabled
1: Channel6 is enabled
2
VD6283TX
I2C interface register description
1 0
CH6_EN
DS13735 - Rev 1 page 28/59
VD6283TX
I2C interface register description
4.3.20
7
ALS channel enable register
6 5
RESERVED
4
R/W
Address:
Type:
Reset:
Description:
0x2E
R/W
0x00
ALS_CHANNEL_ENABLE
[4:0] ALS_CH_EN: ALS channel [1..5] operation
00000: no channel enabled
00001: enables channel 1
00010: enables channel 2
00100: enables channel 3
01000: enables channel 4
10000: enables channel 5
11111: all channels [1..5] enabled
3 2
ALS_CH_EN[4:0]
1 0
DS13735 - Rev 1 page 29/59
4.3.21
7
AC mode control register
6 5
0
4
R/W
Address:
Type:
Reset:
Description:
0x31
R/W
0x00
AC_MODE_CTRL
[6]
[5]
[4]
[3:1]
[0]
Pedestal feature enable/disable:
0: pedestal feature enabled (default)
1: pedestal feature disabled
Reserved
AC_OUT_SEL: AC flicker signal output selection
0: PDM data output on GPIO1 MUX (default)
1: PDM data output on GPIO2
Flicker operation channel selection:
000: no channel selected (default)
001: ALS channel 6 selected
010: ALS channel 1 selected
011: ALS channel 2 selected
100: ALS channel 3 selected
101: ALS channel 4 selected
110: ALS channel 5 selected
Flicker frequency extractor:
0: flicker frequency extractor feature disabled (default)
1: flicker frequency extractor feature enabled
3 2
VD6283TX
I2C interface register description
1 0
DS13735 - Rev 1 page 30/59
4.3.22
7
Pedestal value register
6 5
RESERVED
4 3
R/W
Address:
Type:
Reset:
Description:
0x32
R/W
0x05
PEDESTAL_VALUE
[2:0] Read/write of the pedestal value (applies for flicker operation only)
Recommended pedestal value = 3
VD6283TX
I2C interface register description
2 1
PDST_VAL[2:0]
0
DS13735 - Rev 1 page 31/59
VD6283TX
I2C interface register description
4.3.23
7
Address:
Type:
Reset:
Description:
SDA driver configuration register
6 5 4
RESERVED
R/W
3
SDA_LOAD
0x3C
R/W
0x09
SDA_DRV_CFG
[3]
[2:0]
SDA capacitive load line:
0: <95 pF
1: >95 pF (default)
SDA_DRV configures the SDA driver output current capability:
000: output driver 1 value (lowest)
001: output driver 2 value (default)
010: output driver 3 value
011: output driver 4 value
100: output driver 5 value (recommended for I2C Fast mode plus)
2 1
SDA_DRV[2:0]
0
DS13735 - Rev 1 page 32/59
4.3.24
7
GPIO1 driver configuration register
6 5 4
RESERVED
R/W
Address:
Type:
Reset:
Description:
0x41
R/W
0x00
GPIO1_DRV_CFG
[1:0] GPIO1_CFG: GPIO1 driver configuration
00: open drain output (default value)
01: push-pull output
10: output analog via series resistor (200 Ohms)
11: reserved
3 2
VD6283TX
I2C interface register description
1
GPIO1_CFG[1:0]
0
DS13735 - Rev 1 page 33/59
5
5.1
5.2
5.3
VD6283TX
Absolute maximum ratings, operating conditions and electrostatic discharge (ESD) values
Absolute maximum ratings, operating conditions and electrostatic discharge (ESD) values
Absolute maximum ratings
Parameters
VDD
SDA, SCL, GPIO1, GPIO2
Table 10. Absolute maximum ratings
Min.
-0.5
-0.5
Typ.
—
Max.
2.5
2.5
Unit
V
Stresses above those listed in the table above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended operating conditions
Table 11. Recommended operating conditions
Parameter
Voltage (VDD)
IO
Temperature (normal operating)
Storage temperature
Min.
1.65
1.65
-30
-40
Typ.
1.8
1.8
25
—
Max.
1.95
1.95
85
125
Unit
V
°C
Electrostatic discharge (ESD)
The VD6283 is compliant with the ESD values presented in the table below.
Table 12. ESD values
Parameter
Human body model
Specification
JS001 2017
JS002 2018
Conditions
25 °C, 1500 Ω, 100 pF
25 °C
Max. value
±2000
±500
1. For information only. The final package contributes to CDM performance. Consequently, STMicroelectronics cannot guarantee CDM performances in final packages.
Unit
V
DS13735 - Rev 1 page 34/59
6
Note:
Note:
Note:
VD6283TX
Electrical characteristics
Electrical characteristics
The table gives an overview of the VD6283 current consumption in different operating states.
Table 13. Current consumption in different operating states
Parameter
Idle (no I2C activity)
Inter measurement
ALS only
1 channel
ALS only
5 channels
Flicker only
1 channel
ALS + flicker
5 channels + 1 channel simultaneously
Min.
—
Typ.
3
5
350
450
640
760
Max.
5
10
400
500
800
850
Unit
µA
All current consumption values include silicon process variations.
In ambient light, temperature and voltage are at nominal conditions (25 °C and 1.8 V).
The flicker operation is performed as shown in
Figure 4. Application schematic, ALS and flicker in analog format
.
One possible application use is given in the figure below.
Figure 14. ALS only, Single shot mode
DS13735 - Rev 1 page 35/59
DS13735 - Rev 1
VD6283TX
Electrical characteristics
Table 14. Digital I/O electrical characteristics
Symbol
I
I
I
I
I
I
V
IL
V
IH
V
OL
V
OH
V
V
V
IL
IH
OL
OL1
OL2
OL3
OL4
OL5
IL/IH
Parameter
Low level input voltage
High level input voltage
Low level output voltage (IOUT = 4 mA)
Min.
GPIO1/GPIO2
—
0.7 * VDD
—
High level output voltage (IOUT = 4 mA) VDD – 0.4
I²C interface (SDA / SCL)
Low level input voltage
High level input voltage
Low level output voltage (IOUT = 2 mA in Standard and Fast modes)
Low level output current 1,
SDA_DRV_CFG = ’000’, V
OL
= 0.4 V
Low level output current 2,
SDA_DRV_CFG = ’001’, V
OL
= 0.4 V
Low level output current 3,
SDA_DRV_CFG = ’010’, VOL = 0.4 V
Low level output current 4,
SDA_DRV_CFG = ’011’, VOL = 0.4 V
Low level output current 5,
SDA_DRV_CFG = ’100’, VOL = 0.4 V
Leakage current, VDD = 0 V,
0.1*VDD < VIL <0.9*VDD
-0.5
0.7 * VDD
—
4
8
12
16
20
-10
Typ.
—
—
Max.
0.3 * VDD
—
0.4
—
0.3 * VDD
VDD + 0.5
0.2 * VDD
—
10
Unit
V
V mA
µA
page 36/59
7
DS13735 - Rev 1
VD6283TX
ALS and flicker performances
ALS and flicker performances
Table 15. ALS operating characteristics
Parameter
Exposure time
Inter measurement period
ADC count value before
Gain scaling
(relative to 1x)
Minimum detectable light
ALS readout RMS noise
Conditions
EXTIME step size
Number of EXTIME steps overall,
1.6 ms to 1.6 s
IM step size
Number of IM steps overall,
20 ms to 5.12 s
Minimum reported irradiance level
24-bit ADC readout
16-bit ADC readout
(w/o low byte)
24-bit ADC readout EXTIME =
0x001 to 0x047
(1.6 ms to 113.6
ms)
16-bit ADC readout
(w/o low byte)
EXTIME =
0x048 to 0x3FF
(115.2 ms to 1.6 s)
24-bit ADC readout
16-bit ADC readout
(w/o low byte)
AGAIN = 0.7x
AGAIN = 0.8x
AGAIN = 1x
AGAIN = 1.25x
AGAIN = 1.7x
AGAIN = 2.5x
AGAIN = 3.3x
AGAIN = 5x
AGAIN = 7.1x
AGAIN = 10x
AGAIN = 16x
AGAIN = 25x
AGAIN = 33.3x
AGAIN = 50x
AGAIN = 66.6x
16-bit ADC readout
AGAIN = 16x, EXTIME = 24 ms
Clear channel
Tamb = 25 °C, VDD = 1.8 V
Irradiance = 40 µW/cm 2
AGAIN = 66x, EXTIME = 113.6 ms
Clear channel
AGAIN = 66x, EXTIME = 113.6 ms
Min.
1.52
1
1
—
—
0
0
0
0
4.97
7
9.73
16.04
23.83
0.7
0.82
0.99
1.25
1.66
2.49
3.31
31.35
45.67
59.2
Typ.
1.6
20
256
1
5.04
7.17
10.07
16.76
25.1
0.71
0.83
1.00
1.25
1.68
2.52
3.36
33.3
50.12
66.78
Max.
1.68
1024
16777215
65535
5.08
7.27
10.23
17.18
26.2
0.74
0.85
1.01
1.27
1.69
2.54
3.38
35.07
54.39
73.01
256
—
—
233045
910
Counts
Counts/ steps
Counts
—
Unit ms
Steps ms
Steps
0.25
0.0015
0.007
Counts
Lux page 37/59
DS13735 - Rev 1
VD6283TX
ALS and flicker performances
Parameter
Minimum detectable light
Conditions
Min.
Maximum light level
Dark count noise
AGAIN = 0.7x, EXTIME = 1.6 ms
Clear channel
AGAIN = 0.7x, EXTIME = 1.6 ms,
Irradiance = 0 µW/m2 (i.e. total dark)
AGAIN = 66x, EXTIME = 100 ms
Tamb = 25 °C
6609
30369
1. Refer to Section 3.3.1 Raw and calibration data
and
Section 8.2 Channel sensitivity
2. Guaranteed by characterization (process and temperature variation included)
3. D65 s visible light source
Typ.
0
Max.
1.484
Unit
Lux
Counts
Table 16. Flicker operating characteristics
Unless otherwise stated, the flicker characteristics below are valid under the following host conditions: Flicker channel = Clear,
FFT method, 300 ms data capture time.
Parameter Conditions Min.
Typ.
Max.
Unit
Percent flicker ranges
White LED, 4000 K
(DC level) from 1 to 5 Lux
White LED, 4000 K
(DC level) from 5 to 4000 Lux
20
3
100
100
%
AC flicker frequency detection range
For above percent flicker ranges 100 2000 Hz
AC flicker frequency detection accuracy
Frequency range = 100 Hz to 2000 Hz
Light waveform = square (PWM)
Frequency range = 100 Hz / 120 Hz
Light waveform = sine wave
1
1
3.3
3.3
% page 38/59
8
Optical characteristics
8.1
Photodiode matrix
The sensing matrix is 25 photodiodes in total (5x5).
Figure 15. Photodiode matrix for VD6283TX45/1
C VIS R G
IR
G
C
IR
B
C
R G
VIS B
G G G C
•
•
•
•
•
Figure legends:
• B = blue
• R = red
G = green
I = IR
VIS = visible
C = clear photodiode (no filter)
D = dark channel
VD6283TX
Optical characteristics
DS13735 - Rev 1 page 39/59
8.2
VD6283TX
Channel sensitivity
Channel sensitivity
Unless otherwise stated: Tamb = 25 °C, typical supply (VDD) voltage = 1.8 V, and EXTIME = 50 ms. ST performs a light calibration of every part in production, with individual adjustment of counts into the product memory. A calibration factor is stored in the VD6283 OTP memory and calibrated data can be retrieved through the software driver.
Parameter
Clear channel, irradiance responsivity before calibration
Clear channel, irradiance responsivity after calibration
Conditions
Table 17. Clear channel
White LED (CCT = 4000 K)
16-bit ADC readout
AGAIN = 5x
Min.
49.9
56.1
Typ.
62.3
62.3
Max.
74.8
68.6
Unit
Counts/(µW/cm²)
Parameter
Visible channel, irradiance responsivity before calibration
Visible channel, irradiance responsivity after calibration
Conditions
Table 18. Visible channel
White LED (CCT = 4000 K)
16-bit ADC readout
AGAIN = 10x
Min.
39.7
44.7
Typ.
49.7
49.7
Parameter
Red channel, irradiance responsivity before calibration
Red channel, irradiance responsivity after calibration
Conditions
Table 19. Red channel
White LED (CCT = 4000 K)
16-bit ADC readout
AGAIN = 10x
Min.
11.7
13.1
Typ.
14.6
14.6
Parameter
Green channel, irradiance responsivity before calibration
Green channel, irradiance responsivity after calibration
Conditions
Table 20. Green channel
White LED (CCT = 4000 K)
16-bit ADC readout
AGAIN = 10x
Min.
23.6
26.5
Typ.
29.5
29.5
Max.
59.6
54.6
Max.
17.5
16.0
Max.
35.4
32.4
Unit
Counts/(µW/cm²)
Unit
Counts/(µW/cm²)
Unit
Counts/(µW/cm²)
DS13735 - Rev 1 page 40/59
Note:
Note:
Note:
VD6283TX
Channel sensitivity
Parameter
Blue channel, irradiance responsivity before calibration
Blue channel, irradiance responsivity after calibration
Conditions
Table 21. Blue channel
White LED (CCT = 4000 K)
16-bit ADC readout
AGAIN = 10x
Min.
11.6
13.1
Typ.
14.6
14.6
Max.
17.4
16.0
Unit
Counts/(µW/cm²)
Parameter
IR channel, irradiance responsivity before calibration
IR channel, irradiance responsivity after calibration
Conditions
Table 22. IR channel
Min.
IR LED (λ
P
= 850 nm)
16-bit ADC readout
AGAIN = 10x
68.8
77.4
Typ.
86.0
86.0
Max.
103.2
94.6
Unit
Counts/(µW/cm²)
Irradiance measurements are performed with an R203 radiometer RFF-Cos filter in the ST laboratories.
The main characteristic of white LED is a nominal color temperature of 4000 K
(reference: L130-4080001400001).
The main characteristics of IR LED are: peak wavelength of λ
P
= 850 nm, and spectral half width Δλ
IR
= 30 nm
(reference: MTE8600MT).
DS13735 - Rev 1 page 41/59
8.3
Spectral response
Figure 16. VD6283TX45/1 spectral response (full color set RGBIRClear)
VD6283TX
Spectral response
8.4
Angular response
Figure 17. VD6283 normalized angular response for each channel without diffuser and without aperture
DS13735 - Rev 1 page 42/59
9
Outline drawings
Figure 18. Outline drawing - FoV 60 °
1.008 ±0.025
0.279 ±0.030
0.450
0.555 ±0.060
0.305 ±0.020
0.435 ±0.045
VD6283TX
Outline drawings
0.120 ±0.030
DS13735 - Rev 1 page 43/59
DS13735 - Rev 1
Figure 19. Outline drawing - FoV 90 °
1.008 ±0.025
0.279 ±0.030
0.450
0.555 ±0.060
0.305 ±0.020
0.435 ±0.045
VD6283TX
Outline drawings
0.120 ±0.030 page 44/59
DS13735 - Rev 1
Figure 20. Outline drawing - FoV 120 °
1.008 ±0.025
0.279 ±0.030
0.450
0.555 ±0.060
0.435 ±0.045
0.305 ±0.020
VD6283TX
Outline drawings
0.120 ±0.030 page 45/59
10
10.1
10.2
VD6283TX
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
ECOPACK®2
The VD6283 is an ECOPACK® grade 2 product.
Tape and reel outline drawing
Figure 21. Tape and reel
Ball A1
(balls on bottom and glass on top)
Note: The drawing above is proposed. The dimensions may vary slightly from the actual carrier.
DS13735 - Rev 1 page 46/59
10.3
VD6283TX
Optical BGA 6-ball reflowable package information
Optical BGA 6-ball reflowable package information
Figure 22. Optical BGA 6-ball reflowable package outline
DS13735 - Rev 1
Ref.
Table 23. Optical BGA 6-ball reflowable mechanical data
Package body dimension X
Package body dimension Y
Package height
Ball height
Package body thickness
Thickness of glass surface to wafer
Ball diameter
Total ball count
Ball count X-axis
Ball count Y-axis
Ball pitch X-axis
Ball pitch Y-axis
Edge-to-ball center distance along X
Edge-to-ball center distance along Y
Symbol
D
N
N1
N2
J1
C
C1
A
B
C2
C3
J2
S1
S2
Min.
1807
983
495
90
390
285
170
436
249
Dimension (µm)
120
435
305
200
6
Typ.
1832
1008
555
3
2
450
450
466
279
Max.
1857
1033
615
150
480
325
230
496
309 page 47/59
VD6283TX
Optical BGA 6-ball reflowable package information
Figure 23. Visual anti-rotation mark
DS13735 - Rev 1 page 48/59
10.4
PCB layout and stencil drawing
Figure 24. PCB layout
VD6283TX
PCB layout and stencil drawing
- 0.045
- 0.020
0.450
DS13735 - Rev 1 page 49/59
Figure 25. PCB stencil drawing
VD6283TX
PCB layout and stencil drawing
0.450
0.450
Note: The above PCB stencil drawing is recommended in ST. However, it is permissible to work with a different stencil drawing in the production line.
DS13735 - Rev 1 page 50/59
10.5
Note:
Note:
VD6283TX
Lead-free solder reflow process
Lead-free solder reflow process
The table and figure below show the recommended and maximum values for the solder profile. Customers will have to tune the reflow profile depending on the PCB, solder paste, and material used. We expect customers to follow the “recommended” reflow profile, which is specifically tuned for the VD6283 package. For any reason, if a customer must perform a reflow profile which is different from the “recommended” one (especially peak >240 °C), this new profile must be qualified by the customer at their own risk. In any case, the profile has to be within the
“maximum” profile limit described in the figure below.
Table 24. Recommended soldering profile
Parameters
Minimum temperature (T
Smin
)
Maximum temperature (T
Smax
)
Time ts (T
Smin
to T
Smax
)
Temperature (T
L
)
Time (t
L
)
Ramp up
Temperature (T p-10
)
Time (as index)
Ramp up
Peak temperature (T p
)
Time to peak
Ramp down (peak to T
L
)
Recommended
100
180
80
180
110
1.5
230
—
0.5
240
220
-2
Maximum
150
200
60-120
217
60-150
3
250
30
3
260
480
-6
The temperature mentioned in the above table is measured on top of the VD6283 package.
The VD6283 can sustain up to three passes maximum through the recommended solder reflow profile.
Units
°C
°C s
°C s
°C/s
°C s
°C/s
°C s
°C/s
Figure 26. Soldering profile
DS13735 - Rev 1 page 51/59
VD6283TX
Handling and storage precautions
10.6
10.6.1
10.6.2
10.6.3
Handling and storage precautions
Part handling
The parts must be handled with non-marring ESD safe carbon, plastic, or teflon tweezers. Ranging modules are susceptible to damage or contamination. The customer is advised to use a clean assembly process after removing the tape from the parts, and until a protective cover glass is mounted.
Moisture sensitivity level
Moisture sensitivity for the VD6283 is level 3 (MSL) as described in IPC/JEDEC JSTD-020-E.
Storage temperature conditions
Parameter
Storage temperature
Table 25. Recommended storage conditions
Min.
-40
Typ.
23
Max.
125
Unit
°C
DS13735 - Rev 1 page 52/59
VD6283TX
Ordering information
11
Ordering information
Order code
VD6283TX45/1
Table 26. Order codes
Package
Optical WLCSP BGA 6-ball
Comment
Red, green, blue, IR, clear, and visible
DS13735 - Rev 1 page 53/59
12
VD6283TX
Acronyms and abbreviations
Acronyms and abbreviations
Table 27. Acronyms and abbreviations
Acronym/abbreviation
ALS
AWB
CCT
CWL
ESD
FFT
FoV
FWHM
I2C
PCB
PDM
RMS
VCSEL
Definition ambient light sensing auto white balance correlated color temperature central wavelength electrostatic discharge fast Fourier transform field of view full width at half maximum inter-integrated circuit (serial bus) printed circuit board pulse density modulation root mean square vertical cavity surface emitting laser
DS13735 - Rev 1 page 54/59
Revision history
Date
21-May-2021
Version
1
Table 28. Document revision history
Changes
Initial release
VD6283TX
DS13735 - Rev 1 page 55/59
VD6283TX
Contents
Contents
DS13735 - Rev 1 page 56/59
VD6283TX
Contents
DS13735 - Rev 1 page 57/59
VD6283TX
Contents
DS13735 - Rev 1 page 58/59
VD6283TX
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13735 - Rev 1 page 59/59
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