STMicroelectronics L6460 Datasheet
Reklamë
Reklamë
L6460
SPI configurable stepper and DC multi motor driver
Features
■
■
Operating supply voltage from 13 V to 38 V ■
■
■
■
4 full bridge driver configurable in multi-motor application to drive:
– 2 DC and 1 stepper motor
– 4 DC motor
Bridge 1 and 2 (R
DSon
= 0.60
Ω
) can be configured to work as:
– Dual full bridge driver
– Super DC driver
– 2 half bridge driver
– 1 super half bridge
– 2 power switches
– 1 super power switch
Bridge 3 and 4 (R
DSon
= 0.85
Ω
) can be configured to work as:
– Same as bridges 1 and 2, listed above
– Stepper motor driver: up to 1/16 microstepping
■
TQFP64 exposed pad
Auxiliary features
– Multi-channels 9 bit ADC
– 2 operational amplifiers
– Digital comparator
– 2 low voltage power switches
– 3 general purpose PWM generators
– 14 GPIOs
Description
■
– 2 buck regulators (bridge 3)
– 1 super buck regulator
– Battery charger (bridge 4)
Power supply management
– One switching buck regulator
– One switching regulator controller
– One linear regulator
– One battery charger
The L6460 is optimized to control and drive multimotor system providing a unique level of integration in term of control, power and auxiliary features. Thanks to the high configurability L6460 can be customized to drive different motor architectures and to optimize the number of embedded features, such as the voltage regulators, the high precision A/D converter, the operational amplifier and the voltage
■ Fully protected through Obsolete Product(s) - Obsolete Product(s)
– Overcurrent protection comparators. The possibility to drive simultaneously stepper and DC motor makes
L6460 the ideal solution for all the application featuring multi motors.
– Undervoltage lock-out
Table 1.
■ SPI interface Device summary
Programmable watchdog function Order code Package Packing
Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin
L6460
TQFP64
Tray
■ Very low power dissipation in shut-down mode
(~35 mW)
July 2010 Doc ID 17713 Rev 1 1/139 www.st.com
139
Contents
Contents
L6460
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SupplyInt
regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Sub-configurations for slave, master or single device modes . . . . . . . . . 41
2/139 Doc ID 17713 Rev 1
L6460 Contents
Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13 Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Switching regulator controller application considerations . . . . . . . . . . . . . 54
Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Obsolete Product(s) - Obsolete Product(s)
Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Synchronous buck regulator configuration (Bridge 3) . . . . . . . . . . . . . . 73
Battery charger or switching regulator (Bridge 4) . . . . . . . . . . . . . . . . . 76
Doc ID 17713 Rev 1 3/139
Contents L6460
Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) . 90
Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . . 90
Obsolete Product(s) - Obsolete Product(s)
4/139 Doc ID 17713 Rev 1
L6460
Contents
Schematic examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 5/139
L6460 List of tables
List of tables
Obsolete Product(s) - Obsolete Product(s)
6/139 Doc ID 17713 Rev 1
L6460 List of tables
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 7/139
L6460 List of figures
List of figures
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Obsolete Product(s) - Obsolete Product(s)
8/139 Doc ID 17713 Rev 1
L6460 List of figures
Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 135
Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 136
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 9/139
General description L6460
1.1 Overview
L6460 offers the possibility to control and power multi motor systems, through the management of simultaneous driving of stepper and DC motor. A number of features can be configured through the digital interface (SPI), including 3 voltage regulators, 1 high precision
A/D converter, 2 operational amplifiers and 14 configurable GPIOs.
The high flexibility allows the possibility to configure two, one full or half bridge to work as power stage featuring additional voltage buck regulators.
Figure 1.
Block diagram
6 '0)/?30) 6
3UPPLY
6
3UPPLY)NT #0( #0, 6 0UMP
'0)/S
#HARGE
PUMP
6 0UMP
6
3UPPLY
6
0UMP
X
/P!MP
S
#URRENT
$!#
07-
'ENERATORS
X
3WITCH
$#?-).53
$#?0,53 4HERMAL
-ANAGER
N2%3%4 )NT6OLTAGE2EFERENCE
-58 !$#
$IGITAL
#OMP
6 0UMP
6 3UPPLY
6 0UMP
'.$
3UPERVISORY
2ESET
-ANAGER
7$
(3 $#X?-).53
$#?-).53
$#?0,53 3TEPPER-OTOR
-ANAGER
$#$# ,3
$#X?-).53
(3
$#X?0,53
6
0UMP
6 3UPPLY
6
0UMP
'.$
#ONTROL
,OGIC
N33
3#,+
-)3/
-/3)
"ATTERY
#HARGER
-ANAGER
,3 $#X?0,53
$#?-).53
$#?0,53
6
0UMP
6 3UPPLY 6
0UMP
6
3UPPLY
6
3UPPLY
$#?3%.3%
6
3UPPLY
N!7!+%
6 0UMP
6 0UMP
6 6
$#?-).53
)NTERNAL
2EGULATOR
-AIN
3WITCHING
2EGULATOR
-AIN
,INEAR
2EGULATOR
3WITCHING
2EGULATOR
#ONTROLLER
$#?0,53
2EGOLATION
,OOP
$#
$#?3%.3% Obsolete Product(s) - Obsolete Product(s)
%?0!$
Note: See following
for a detailed description of possible configurations.
10/139 Doc ID 17713 Rev 1
L6460 General description
Figure 2.
Pin connection
DC1_PLUS 1
V SWDRV_SNS 2
V
SWDRV_FB
3
GPIO4 4
GPIO3 5
DC1_MINUS 6
DC1_MINUS 7
GND1 8
GND2 9
DC2_MINUS 10
DC2_MINUS 11
GPIO2 12
GPIO1 13
GPIO0 14 nSS 15
DC2_PLUS 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND_PAD
48 DC3_SENSE
47 GPIO5
46 GPIO9
45 GPIO10
44 GPIO11
43 N.C.
42 DC3_MINUS
41 DC3_SENSE
40 DC4_SENSE
39 DC4_MINUS
38 N.C.
37 GPIO14
36 GPIO13
35 GPIO12
34 nAWAKE
33 DC4_SENSE
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 11/139
General description L6460
Table 2.
Pin #
Pins configuration
Pin name Description Type
8
9
10
11
12
13
6
7
4
5
1
2
3
14
15
16
17
18
19
DC1_PLUS Bridge 1 phase “plus” output
V
SWDRV_SNS
V
SWDRV_FB
GPIO4
Switching regulator controller sense
Switching regulator controller feedback
General purpose I/O
GPIO3 General purpose I/O
DC1_MINUS Bridge 1 phase “minus” output
DC1_MINUS Bridge 1 phase “minus” output
GND1 Ground pin for bridge1
(1)(2)(3)
GND2 Ground pin for bridge2
(1)(2)(3)
DC2_MINUS Bridge 2 phase “minus” output
DC2_MINUS Bridge 2 phase “minus” output
GPIO2 General purpose I/O
GPIO1 General purpose I/O
GPIO0 nSS
General purpose I/O
SPI chip select pin
DC2_PLUS Bridge 2 phase “plus” output
DC2_PLUS Bridge 2 phase “plus” output
V
Supply
MISO
Main voltage supply
SPI serial data output
Output
Analog input
Analog input
Analog In/Out - CMOS bi-dir
Analog In/Out - CMOS bi-dir
Output
Output
Power/digital
Power/digital
Output
Output
Analog In/Out - CMOS bi-dir
Analog In/Out - CMOS bi-dir
Analog Input - CMOS input
CMOS input
Output
Output
Power input
CMOS output
20
21
22
MOSI SPI serial data input
V
LINmain_FB
V
LINmain_OUT
GPIO 8
Linear main regulator feedback
Linear main regulator output
General purpose I/O
CMOS input
Analog input
Power output
23 Analog In/Out - CMOS bi-dir
24
25
V
SWmain_SW
V
Supply
Main switching regulator switching output
Main voltage supply
Power output
Power Input
26
27
V
SWmain_FB
V
REF_FB
Main switching regulator feedback pin
Regulator voltage feedback
Analog input
Analog input
28 I
REF_FB
Regulator current feedback Analog input
29 SCLK SPI input clock pin CMOS input
V
Supply
Main voltage supply
DC4_PLUS Bridge 4 phase “plus” output
30
31
Power input
Output
32
33
34
N.C.
Not connected
DC4_SENSE Bridge 4 sense output
(4) nAWAKE Device wake up
Output
CMOS input
12/139 Doc ID 17713 Rev 1
L6460 General description
Table 2.
Pin #
Pins configuration (continued)
Pin name Description Type
42
43
44
45
46
47
48
49
38
39
40
41
35
36
37
53
54
55
56
57
50
51
52
GPIO12
GPIO13
GPIO14
N.C.
General purpose I/O
General purpose I/O
General purpose I/O
Not connected
DC4_MINUS Bridge 4 phase “minus” output
DC4_SENSE Bridge 4 sense output
(4)
DC3_SENSE Bridge 3 sense output
(4)
DC3_MINUS Bridge 3 phase “minus” output
N.C.
Not connected
GPIO11
GPIO10
GPIO9
General purpose I/O
General purpose I/O
General purpose I/O
Analog In/Out - CMOS bi-dir
Analog In/Out - CMOS bi-dir
Analog In/Out - CMOS bi-dir
Analog In/Out - CMOS bi-dir
Analog In/Out - CMOS bi-dir
Analog In/Out - CMOS bi-dir
GPIO5 General purpose I/O Analog In/Out - CMOS bi-dir
DC3_SENSE Bridge 3 sense output
(4)
Output
N.C.
Not connected
DC3_PLUS Bridge 3 phase “plus” output
V
Supply nRESET
Main voltage supply
Open drain system reset pin
Output
Power input
CMOS Input/output
V
3v3
V
SupplyInt
GPIO7
V
GPIO_SPI
GPIO6
Internal 3.3 volt regulator
Internal voltage supply
General purpose I/O
Low voltage pins power supply
General purpose I/O
Output
Output
Output
Output
Power Input/output
Power Input
Analog In/Out - CMOS bi-dir
Power input
Analog In/Out - CMOS bi-dir
58 Switching regulator controller source input Power input V
SWDRV_SW
59 V
SWDRV_GATE
60 V
Pump
Switching driver gate drive pin
Charge pump voltage
Analog output
Power Input/output
61 CPH Charge pump high switch pin Power Input/output
Obsolete Product(s) - Obsolete Product(s)
V
Supply
Charge pump low switch pin Power Input/output
63 Main voltage supply Power input
Output 64
E_Pad
DC1_plus Bridge 1 phase “plus” output
GND_PAD
(1)(2)(3)
1.
These pins must be connected all together to a unique PCB ground.
2.
Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the other is connected to exposed pad (E_Pad) ground ring. This makes the bond wires testing possible by forcing a current between E-Pad and GND1 or GND2 pins and using the other pin as sense pin to measure the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together).
3.
The analog ground is connected to exposed pad E-Pad.
4.
The pin must be tied to ground if bridge is not used as a stepper motor.
Doc ID 17713 Rev 1 13/139
L6460 L6460’s main features
2 L6460’s main features
L6460 includes the following circuits:
● Four widely configurable full bridges:
– Bridges 1 and 2:
– Diagonal R
DSon
: 0.6
Ω
typ.
– Max operative current = 2.5 A.
– Bridges 3 and 4:
– Diagonal R
DSon
: 0.85
Ω
typ.
– Max operative current = 1.5 A.
● Possible configurations for each bridge are the following:
– Bridge 1:
– DC motor driver.
– Super DC (bridge 1 and 2 paralleled form superbridge1).
– 2 independent half bridges.
– 1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form superhalfbridge1).
– 2 independent switches (high or low side).
– 1 super switch (high or low side).
●
– Bridge 2 has the same configurations of bridge 1.
– Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form superbridge2) plus the following:
– ½ stepper motor driver.
– 2 buck regulators (V
AUX1_SW
, V
AUX2_SW
).
– 1 Super buck regulator (V
AUX1//2_SW
).
– Bridge 4 has the same configurations of bridge 1 plus the following:
– ½ stepper motor driver.
– 1 super buck regulator (V
AUX3_SW
).
– Battery charger.
One buck type switching regulator (V
SWmain
) with:
– Output regulated voltage range: 1-5 Volts.
– Output load current: 3.0 A.
– Internal output power DMOS.
Obsolete Product(s) - Obsolete Product(s)
– Internal PWM generation.
– Switching frequency: ~250 kHz .
●
– Pulse skipping strategy control.
One switching regulator controller (V
SWDRV
) with:
– Output regulated voltage range: 1-30 Volts.
– Selectable current limitation.
●
– Internal PWM generation.
– Pulse skipping strategy control.
One linear regulator (V
LINmain
) that can be used to generate low current/low ripple
14/139 Doc ID 17713 Rev 1
L6460 L6460’s main features
●
●
●
●
●
●
●
●
● voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages.
One bidirectional serial interface with address detection so that different ICs can share the same data bus.
Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin.
Fourteen general purpose I/Os that can be used to drive/read internal/external analog/logic signals.
One 8-bit/9-bit A/D converter (100 kS/s @ 9-bit, 200 kS/s @8-bit). It can be used to measure most of the internal signals, of the input pins and a voltage proportional to IC temperature.
– Current sink DAC:
– Three output current ranges: up to 0.64/6.4/64 mA.
– 64 (6-bit programmable) available current levels for each range.
– 5 V output tolerant.
Two operational amplifiers:
– 3.3 V supply, rail to rail input compatibility, internally compensated.
– They can have all pins externally accessible or can be internally configured as a buffer o make internal reference voltages available outside of the chip.
– Unity gain bandwidth > 1 MHz.
– They can also be set as comparators with 3.3 V input compatibility and low offset.
Two 3.3 V pass switches with 1
Ω
R
DSon
and short circuit protected.
Programmable watchdog function.
Thermal shutdown protection with thermal warning capability.
Very low power dissipation in “low power mode” (~35 mW)
L6460 is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility L6460 includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to leave the possibility to assembly a switching regulator by only adding an external FET.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 15/139
Electrical specifications L6460
3.1 Absolute maximum rating
The following specifications define the maximum range of voltages or currents for L6460.
Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Table 3.
Absolute maximum ratings
Parameter Description
Test condition
Min Max Unit
V
V
V
V
V
Supply
GPIO_SPI
3V3pin
V
SW
SW_pulse
Pump
T
J
V
Supply
voltage
V
GPIO_SPI voltage
V
3V3 voltage
Switching regulators output pin voltage range
Switching regulators min pulsed voltage
Charge pump voltage tpulse <
500ns
(1)
Junction temperature
(2)
Storage
Operating
-0.3
-1
-3
-40
-40
V
40
3.9
3.9
Supply
15
190
TSD
V
V
1.
This value is useful to define the voltage rating for external capacitor to be connected from V
V
Supply
. V
Pump to provide voltage to external loads.
Pump
to
is internally generated and can never be supplied by external voltage source nor is intended
2.
TSD is the thermal shut down temperature of the device.
V
°C
°C
V
V
V
Table 4.
IC operating ratings
Parameter Description
Test condition
Min Max Unit
I
VGPIO_SPI
V
GPIO_SPI operative current
13
(1)
38 V
Supply
V
Supply
voltage range
I
Supply
I
Shut_down
V
Supply
operative current
V
Supply
shut down state current
(2)
15 Obsolete Product(s) - Obsolete Product(s) mA mA
V
GPIO_SPI
V
GPIO_SPI voltage range 2.4
3.6
V
(3)
0.4
V mA
V
3v3
3.3V input pin voltage range 3.6
V
(4)
V
LINmain_OUT
Output pin voltage range 0 V
Supply
V
Feedback pin voltage range 0 3.6
V V
LINmain_FB
V
SWmain_SW
V
SWDRV_SW
Output pin voltage range
(4)
-1
V
SWDRV_SW
pin voltage range
(4)
-1
V supply
V
V
Supply
V
16/139 Doc ID 17713 Rev 1
Table 4.
IC operating ratings
Parameter Description
Test condition
Min Max Unit
V
V
SWDRV_GATE
SWDRV_SNS
Gate drive pin voltage
Sense pin voltage
0 V
Pump
V
Supply
-3V
V
Supply
V
V
T
J
Junction temperature Operating -40 125
1.
For V
For V supply
lower than 21 V an external resistor between V supply
and V supply Int pins are required. supply
lower than 15 V external diodes for charge pump are required.
2.
Operating supply current is measured with system regulators operating but not loaded.
3.
Operating V
GPIO_SPI
current is measured with all circuits supplied by V
GPIO_SPI
(GPIO’s, operational amplifiers and pass switches) enabled but not loaded.
4.
The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range.
°C
Table 5.
Parameter
Electrical characteristics
Description Test condition Min Typ Max Unit
V
SupplyInt
regulator
V
S_Int
I
S_Int
V
V
SupplyInt
SupplyInt
Charge pump V
Pump
output voltage operative current
(1)
(2)
18 19.5
11
21 V mA
V
Pump
F
Pump
Charge pump voltage
V
Pump
clock frequency
V
Supply
=32V
F
OSC
= 16MHz typ
V
Supply
+ 10.5
V
Supply
+12.5
V
Supply
+ 14.5
F
OSC
4
/6
V kHz
V3V3 regulator
V
3V3
Power on reset
V
3v3
output voltage V
Supply
=32V 3.15
3.3
3.45
4 V
Supply_POR_valid
V
Supply voltage for POR valid I nRESET
= 1mA
6 8 V
Supply_POR_fall
V
Supply
POR falling threshold V
Supply falling
Obsolete Product(s) - Obsolete Product(s)
V
3V3_POR_fall
V
Supply
POR filter Time
V
3V3
falling 1.9
2.2
µs
V V
3v3
POR falling threshold
V
V
3V3
rising 2.7
V V
3V3_POR_rise
V
3V3_POR_hys
V
3v3
POR rising threshold
V
3v3
POR hysteresis
V
3v3
POR filter time
0.5
t
3V3_POR_filt
1.5
V
µs
V nRESET circuit
V nRST_L nRESET low level output voltage
I=10mA 0.4
V
V
Doc ID 17713 Rev 1 17/139
Electrical specifications L6460
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition t nRST_fall nRESET fall time
I=1mA
C=50pF
(3)
(4) t nRST_del
V
Supply_UV_f
V
Supply_UV_r
V
Supply_UV_hys t
Supply_UV
V
S_Int_UV_f
V
S_Int_UV_r
V
S_Int_UV_hys t
S_Int_UV nRESET delay time
V
Supply
falling threshold
V
Supply
rising threshold
V
Supply
hysteresis
V
Supply
UV filter time
V
SupplyInt
falling threshold
V
SupplyInt
rising threshold
V
SupplyInt
hysteresis
V
SupplyInt
UV filter time
V
Pump_UV_f
V
Pump_UV_r
V
IL
V
Pump
falling threshold
V
Pump
rising threshold
V
Pump_UV_hys t
Pump_UV
V
GPIO_SPI_UV_f
V
GPIO_SPI_UV_r
V
GPIO_SPI_hys t
GPIO_SPI_UV
TSD circuit
V
Pump
hysteresis
V
Pump
UV filter time
V
GPIO_SPI
falling threshold
V
GPIO_SPI
rising threshold
V
GPIO_SPI
hysteresis
V
GPIO_SPI
UV filter time nAWAKE low logic level voltage
Min Typ Max
15
10.2
10.5
0.3
9.7
10.6
0.4
10.7
11.4
0.7
3.5
11
11.5
0.5
3.5
150
11.8
12.5
0.7
11.7
12.2
1
V
Supply
+7
V
Supply
+ 7.5
V
Supply
+ 8
V
Supply
+ 7.5
V
Supply
+ 8
V
Supply
+ 8.5
0.3
0.7
1.8
0.5
3.5
2
200
2.2
250
3.5
2.4
300
Unit ns
V
µs
V
V ns
V
V
V
µs
V
V
T
TSD
T
WARM
T
DIFF
Thermal shut down temperature
Warming temperature
Thermal shut down to warming difference
170
140
30
Thermal shut down filter time 8 t
TSD_FILT t
WARM_FILT
Watchdog
Warming filter time 8
Obsolete Product(s) - Obsolete Product(s)
µs
WD_T clk
Watchdog clock period
T osc
2
22
* s
µs
°C
°C
°C
Internal clock
F osc
Oscillator frequency nAWAKE function
V
3V3
= 3.3 V 14.1
16 17.6
MHz
0.8
V
µs
V
V mV
µs
V
18/139 Doc ID 17713 Rev 1
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition
V
IH nAWAKE high logic level voltage nAWAKE input hysteresis V
HYS
I
OUT
I
INP t
AWAKEFILT nAWAKE pin output current nAWAKE pin input current
Filter time
Main linear regulator nAWAKE=0V
(5) nAWAKE=0.8V
(5)
Min
1.6
-0.72
0.2
Typ
0.25
1.2
Max
-2
0.4
Unit
V drop
Drop out voltage
I
PD
Internal switch pull down current
V
LINmain_Ref
I
LINmain_Ref
I outLINMax
Feedback reference voltage
Feedback pin input current
I short
Maximum output current
Output short circuit current
Load regulation
Δ
V out
/V o
Δ
V out
/
Δ
V
Supply
V loop_acc
V
LIN_UV_f
V
LIN_UV_r
V
LIN_UV_hys t prim_uv
Line regulation
Loop voltage accuracy
Undervoltage falling threshold
Undervoltage rising threshold
Undervoltage hysteresis
Under voltage deglitch filter
Main switching regulator
V drop
=
V supply
-V
LINmain_OUT
Linear Main Regulator disabled; V
LINmain_OUT
=1V
V
LINmain_OUT
= V supply
-2V
V
LINmain_OUT
=0V,
V
LINmain_FB
=0V
0
≤
I load
≤
I outLINMax
(6)
I load
=10mA
(6)
(7)
(7)
2
0.776
-2
10
12
84.5
90.5
3
0.8
24
±2.5
87
93
6
5
0.824
2
32
0.8
0.2
89.5
95.5
mA
V
µA mA mA
V
FBREF
Main switching regulator feedback reference voltage
SelFBref = ‘00’
SelFBref = ‘01’
(8)
SelFBref = ‘10’
0.776
0.97
2.425
0.8
1
2.5
0.824
1.03
2.575
SelFBref = ‘11’ 2.91
3 3.09
Obsolete Product(s) - Obsolete Product(s)
V
Supply
= 36V
-40 +40
I
Q_LP
Output leakage current in
-15 +15
µA
µA
“low power mode” T junction
= 125°C
V
-10 +10 µA I
SWmain_FB
V
SWmain_OUT
I load
V
SWmain_FB
pin current
Output voltage range
T junction
= 125°C
(9)
0.8
5
R
DSonHS
Maximum output load current V
Supply
= 36V
Internal high side R
DSon
I load
=1A
T junction
= 125°C
0.002
0.33
3
0.95
V
A
Ω
V
V
V
V
%
%
%
%
%
%
µs
V
V mA mA
μ s
Doc ID 17713 Rev 1 19/139
Electrical specifications L6460
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition
V loop
V
SW_UV_f
V
SW_UV_r
V
SW_UV_hys t prim_uv
I limit t deglitch t
I_lim t
I_limUV t r t f
F
SW_PWM
Loop voltage accuracy
Under voltage falling threshold
(10)
Under voltage rising threshold
(10)
Under voltage hysteresis
Under voltage deglitch filter
Current limit protection
SelIlimit =”0”
SelIlimit =”1”
Current limit deglitch time
Current limit response time
Normal operating mode (no
UV)
(11)
Current limit response time in
UV condition
Switching output rise time
Switching output fall time
Operating frequency
UV condition
Min Typ
(12)
200
V
Supply
= 36V,
R
LOAD
= 422
Ω (13)
V
Supply
= 36V,
R
LOAD
= 10
Ω (13)
84.5
90.5
3.3
2.3
50
5
5
±3%
87
93
6
5
5
3.5
450
Fosc/6
4
Switching regulator controller
Max
89.5
95.5
650
400
30
30
Unit ns kHz
V
GS_ext
Gate to source voltage for external FET
V
Pump
I
SOURCE
Source current
Sink current
Sink discharge pulse time
V
Pump
=V
Supply
+12V
V
SWCTR_GATE
=0V
V
SWCTR_GATE
= V
Supply
25
20
600
50 mA mA I
SINK t
SINK
R
SUSTAIN
I
Q
Gate-source sustain resistance
Output leakage current
(V
SWCTR_GATE
-
V
SWCTR_SRC
) = 0.2V
V
Supply
= 36V,
T junction
= 125°C
-40
650
+40
V
Supply
= 36V,
I Q_LP
Output leakage current in
Obsolete Product(s) - Obsolete Product(s)
SelFBref = ‘00’
-5
0.776
0.8
+5
0.824
µA
V
V
FBREF
Switching regulator feedback controller feedback reference voltage
SelFBref = ‘01’
SelFBref = ‘10’
0.97
2.425
1
2.5
1.03
2.575
V
V
SelFBref = ‘11’ 2.91
3 3.09
V
I
SWDRV_FB
V
SWDRV_FB
pin current
V
Supply
= 36V,
T junction
= 125°C
-10 +10 µA
V loop
Loop voltage accuracy ±3%
Ω
µA ns
V ns ns ns
%
%
%
µs
A
A ns
20/139 Doc ID 17713 Rev 1
Table 5.
Parameter
Electrical characteristics (continued)
V
SWD_UV_f
V
SWD_UV_r
V
SWD_UV_hys t prim_uv
V ovc t deglitch
Description
Under voltage falling threshold
(14)
Under voltage rising threshold
Under voltage hysteresis
Under voltage deglitch filter
Over current threshold voltage
Test condition t
I_lim t
I_limUV
Current limit deglitch time
Current limit response time
Current Limit response time in
UV condition.
UV condition
Operating frequency
Normal operating mode (no
F
SWD_PWM
Power bridges
R
DSon1_2
R
DSon3_4
I
MAX1_2
I
MAX3_4
I dss
I
Q_LP
I
OC_LS1_2
Bridge 1 and 2 diagonal R
DSon
I = 1.4A, V
Supply
= 36V,
T junction
= 125°C
Bridge 3 and 4 diagonal R
DSon
I = 1A, V
Supply
= 36V,
T junction
= 125°C
Bridge 1 and 2 operative rms current
Bridge 3 and 4 operative rms current
Output leakage current.
Output leakage current in “low power mode”
T junction
= 125°C
V
Supply
= 36V,
T junction
= 125°C
Low side current protection for bridges 1 and 2
(15)
MtrXSideYILimSel[1:0]=00
MtrXSideYILimSel[1:0]=01
MtrXSideYILimSel[1:0]=10
MtrXSideYILimSel[1:0]=11
(16)
Min
84.5
90.5
250
50
-50
-10
0.6
1.4
2.4
2.4
500
380
F osc
/64
0.6
0.85
3
3
1
2
Typ
87
93
6
5
300
Max
89.5
95.5
350
900
550
1.1
1.65
2.5
1.5
+50
+10
1.6
2.6
3.6
3.6
0.7
1 1.7
MtrXSideYILimSel[1:0]=00
I
OC_HS1_2 bridges 1 and 2
(15)
MtrXSideYILimSel[1:0]=01
High side current protection for
MtrXSideYILimSel[1:0]=10 Obsolete Product(s) - Obsolete Product(s)
6)
1.5
2.5
2.5
2
3
3
2.7
3.7
3.7
A
I
OC_LS3_4
I
OC_HS3_4 t filter
Low side current protection for bridges 3 and 4
(15)
MtrXSideYILimSel[1:0]=11
(17)(18)
High side current protection for bridges 3 and 4
(15)
MtrXSideYILimSel[1:0]=11
(1
7)(18)
Current limit filter time
1.55
1.6
2
2.5
2.5
5
A
A
μ s
Unit
µs mV ns
%
%
% ns ns kHz
Ω
Ω
A
A
µA
µA
A
Doc ID 17713 Rev 1 21/139
Electrical specifications L6460
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition t delay
Current limit delay time t
OC_off
Over current Off time
MtrXIlimitOffTimeY[1:0]=00
MtrXIlimitOffTimeY[1:0]=01
MtrXIlimitOffTimeY[1:0]=10
MtrXIlimitOffTimeY[1:0]=11
(19)
Min Typ
5
60
120
240
480
Max Unit
μ s t r1_2 t r3_4 t f1_2 t f3_4
Output rise time bridges 1 and 2
Output rise time bridges 3 and 4
Output fall time bridges 1 and 2
Output fall time bridges 3 and 4
V
Supply
= 36V, resistive load between outputs:
R= 25
Ω (20)
V
Supply
= 36V, resistive load between outputs:
R= 36
Ω (20)
V
Supply
= 36V, resistive load between outputs:
R= 25
Ω (20)
V
Supply
= 36V, resistive load between outputs:
R= 36
Ω (20)
100
50
100
50
180
100
180
125
250
200
250
250 ns ns ns ns t deadRise t deadFall
Anti crossover rising dead time
Anti crossover falling dead time
100
100
300
300
450
450 ns ns
F
PWM
Operating frequency
F osc
/51
2 kHz t resp
Bipolar stepper circuitry
V
STEPREF
Reference voltage
SelStepRef =0
SelStepRef =1
0.48
0.72
0.50
0.75
0.52
0.78
Sense comparator offset -12 12 V offset
StepBlkTime = ‘00’
0.65
0.95
1.25
StepBlkTime = ‘01’ 1 1.45
1.9
t blk
Blanking time Obsolete Product(s) - Obsolete Product(s)
StepBlkTime = ‘11’ 3 4.25
5.5
µs
µs
µs
µs mV
V
Synchronous buck regulator (bridge 3)
V
AUX_SW
I
Q
I
QLP
Delay from PWM to output transition
Output pin voltage range
(DC3x)
Output leakage current T junction
= 125°C
Output leakage current in “Low
Power Mode”
V
Supply
= 36V
T junction
= 125°C
-1
-50
-10
500
V
Supply
+50
+10 ns
V
µA
µA
µs
µs
µs
µs
22/139 Doc ID 17713 Rev 1
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition Min Typ Max
I
V
FBREF
GPIO_FB
V out
I load
R
DSonHS
V loop
V
REG_UV_f
V
REG_UV_r
V
REG_UV_hys t aux_UV
I limit t deglitch
Synchronous buck regulator feedback reference voltage
GPIO feedback pin current
Output voltage range
Output load current
Under voltage rising threshold
Under voltage hysteresis
Under voltage deglitch filter
Current limit protection
Current limit deglitch time
SelFBRef = ‘00’
SelFBRef = ‘01’
(21)
SelFBRef = ‘10’
(22)
SelFBRef = ‘11’
0.776
0.97
2.425
2.91
T junction
= 125°C
0V
≤
Feedback
≤
3V
-15
V
Supply
= 36V
(23)
0.8
0.002
V
Supply
= 36V
T junction
= 125°C; I load
=1A Internal high/low side R
DSon
Loop voltage accuracy
Under voltage falling threshold
(24)
t
I_lim
Current limit response time
Normal operating mode
(no UV)
t
I_limUV t t f r
Current limit response time in
UV condition.
UV condition
Switching output rise time
Switching output fall time
V
Supply
R
LOAD
= 36V,
= 422
Ω (25)
V
Supply
R
LOAD
= 36V,
= 10
t dead
F
REGPWM
Crossover dead time
Operating frequency
Battery charger (Bridge 4)
84.5
90.5
1.6
50
5
10
0.8
1
2.5
3
480
350
100
F osc
/64
0.6
±3%
87
93
6
5
0.824
1.03
2.575
3.09
15
30
1.5
0.8
89.5
95.5
2.5
700
500
30
50
µA ns ns ns ns ns kHz
V
AUX3_SW
I
Q
Output pin voltage range
(DC4x)
(26)
T
-1 junction
= 125°C
SelFBRef = ‘00’
-100
V
Supply
+100
1.37
1.412
1.455
V
µA
V
1.746
1.8
1.854
V
V
FBRef
Battery charger control loop feedback reference voltage
SelFBRef = ‘10’ 2.079
2.143
2.207
V
SelFBRef = ‘11’ 2.425
2.5
2.575
V
V
A
Ω
%
%
%
µs
A ns
Unit
V
V
V
V
Doc ID 17713 Rev 1 23/139
Electrical specifications L6460
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition
V
CurrRef
R
I
V out load
DSon
V loop
V
BC_UV_f
V
BC_UV_r
V
BC_UV_hys t aux_UV
I limit t deglitch
Battery charger control loop feedback reference current
SelCurrRef = ‘01’
SelCurrRef = ‘10’
Output voltage range
Output load current
Internal high/low side R
DSon
SelCurrRef = ‘11’
V
Supply
= 36V
(27)
V
Supply
= 36V
T junction
= 125°C;
I
LOAD
= 1.5A
Loop voltage accuracy
Under voltage falling threshold
(28)
Under voltage rising threshold
Under voltage hysteresis
Under voltage deglitch filter
Current limit protection
Current limit deglitch time t t
I_lim
I_limUV t t f r
Current limit response time
Switching output rise time
Switching output fall time
Normal operating mode
(no UV)
Current limit response time in
UV condition.
UV condition
V
Supply
= 36V,
R
LOAD
= 422
Ω
V
Supply
= 36V,
R
LOAD
= 10
t dead
Crossover dead time
F
BCPWM
Operating frequency
ADC with A2DType=0
(29)
Min Typ Max
0.873
0.9
0.927
1.394
1.437
1.48
1.746
1.8
1.854
2.182
2.25
2.318
1.412
30
0.002
3
84.5
90.5
3.2
50
5
10
0.3
±3%
87
93
6
5
480
350
100
F osc
/64
0.4
89.5
95.5
5
700
500
30
50
Ω
%
%
%
µs
A ns ns ns ns ns ns kHz
IMR Measurement range A2dType = 0 0
A2dType = 0
(30)(31)
V
3v3
±2 INL Integral non-linearity LSB
DNL
OE
Differential non-linearity
Offset error
A2dType = 0
A2dType = 0
(33)
±2 Obsolete Product(s) - Obsolete Product(s)
±4
LSB
LSB
V
OE
Drift
GE
Offset error drift
Gain error
A2dType = 0 over time and temperature
A2dType = 0
(34)
±3
±4
LSB
LSB
GE
Drift
Gain error drift
A2dType = 0 over time and temperature
±4 LSB t conv
Minimum conversion time
Resolution
55 µs bits
(35)
8
Unit
V
V
A
V
V
V
24/139 Doc ID 17713 Rev 1
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition Min Typ
(36)
C in
Input sampling capacitance
ADC with A2DType=1 (37)
0 IMR
INL
DNL
OE
OE
Drift
GE
GE
Drift
Measurement range
Integral non-linearity
Differential Non-Linearity
Offset error
Offset error drift
Gain error
Gain error drift
A2dType = 1
A2dType = 1 over time and temperature
A2dType = 1 over time and temperature t conv
Minimum conversion time
Resolution
Input sampling capacitance
9
C in
Current DAC
Max
4
V
3v3
±1
±1
±4
±3
±4
±4
10
4
Unit pF
V
LSB
LSB
LSB
LSB
LSB
LSB
µs bits pF
V
R
Pin voltage operative range
(GPIO8)
Output off leakage current
(38)
0.7
5.5
V
I
OUT_OFF
I
FULL_ERR
Full scale current error
DacValue[5:0] = 000000
DacRange[1:0] =xx
DacValue[5:0] = 111111
-1
-15
+1
+15
µA
% of
I
FULL typ
INL
10_11
DNL
10_11
INL
01
Integral non-linearity for 10 and 11 ranges
Differential non-linearity for 10 and 11 ranges
Integral non-linearity for 01 range
±2
±2
±1
LSB
LSB
LSB
DNL
01
Differential non-linearity for 01 range
±1 LSB
R
CurrDac_res
R
CurrDac_ratio
Gpio[8] divider total resistance
Gpio[8] divider ratio
(39)
45
3/5 k
Ω t set
Settling time 5 µs
Operational amplifier
(40)
V
GPIO_SPI
V
ICM
Operational amplifier supply voltage range
Input common mode voltage range
Output voltage
3.15
0
0.1
3.3
3.45
V
V
V V
OUT_MAX
I
LOAD
=± 1mA
V
GPIO_
SPI
3.2
Doc ID 17713 Rev 1 25/139
Electrical specifications L6460
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition
VOp1PlusRef
VOp2PlusRef
Operational amplifier 1 and 2 reference voltage
OpxRef[1:0]=00
OpxRef[1:0]=01
OpxRef[1:0]=10
OpxRef[1:0]=11
Unit Min
0.97
1.6
1.94
2.425
Typ
1
1.65
2
2.5
Max
1.03
1.7
2.06
2.575
V
Avd Open loop gain
V
ICM
=1.65V
I
LOAD
= 0mA
CMRR Common mode rejection ratio
PSRR Power supply rejection ratio
I
LOAD
= ±6mA
V
ICM
=1.65V
I
in _offs
I in _bias
V
in _offs
Input offset current
Input bias current
Input offset voltage
GBWP Gain bandwidth product
C load
=100pF V
ICM
=1.65V
R load
=330
Ω
to V
GPIO_SPI
V out
=1.65V
I out
I short_max
Output current
Short circuit current
SR Slew rate
I load
= 0
C
LOAD
=100pF
Operational amplifier used as comparator
(41)
90
80
-150
-500
-5
2
12
1.3
110
90
20
1.75
150
500
5
10 nA nA mV
MHz mA mA
V/µs
Output voltage 0.3
2.9
V
OUT_MAX
I load
=± 10mA t
OFF t
FALL t
ON
Turn off propagation delay
Fall time
Turn on propagation delay
V
CM
= 1.65V
Δ
Vi = -/+ 20mV
C
LOAD
=100pF
(42)(43)
V
CM
= 1.65V
Δ
Vi = -/+ 20mV
C
LOAD
V
CM
= 1.65V
Δ
Vi = -/+ 20mV
C
LOAD
0.6
0.15
0.25
1
0.4
0.5
V
CM
= 1.65V
Rise time 0.2
0.4
t
RISE
Obsolete Product(s) - Obsolete Product(s)
Low power switch
Δ
Vi = -/+ 20mV
C
LOAD
µs
µs
µs
µs
V dB dB dB
V
PSW
V
OUT_MAX
R
DSon
I
LIMIT t deglitch
Input voltage range
Output voltage
Switch R
DSon
resistance
Current limit
Current limit deglitch time
I load
=100mA
2.4
150
50
0.6
250
3.6
V
GPIO_
SPI
1
350
V
V
Ω mA ns
26/139 Doc ID 17713 Rev 1
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition t
I_lim
C
LOAD
Current limit response time
Max load capacitance t t
ON
OFF
Turn on propagation delay
Turn off propagation delay
V
GPIO_SPI
C
LOAD
=3.3V I
=100pF
(44)
LOAD
=1mA
V
GPIO_SPI
=3.3V
I
LOAD
=1mA
C
LOAD
Interrupt controller t
PULSE t
INTFILT
Pulse duration
Filter time
GPIO[0], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[6]
Min Typ
450
250
16*T osc
200
Max
650
2.5
650
450 t
V
IH
V
IL
V
HYS
V
OL
I
LEAKAGE
DELAY
High level input voltage
Low level input voltage
Input voltage hysteresis
Low level output voltage
Leakage current
Delay from serial write to pin
Low
I
OUT
0
≤
V
C
= 15mA out
LOAD
≤
V
3v3
=50 pF
(45)
GPIO[5], GPIO[7], GPIO[9], GPIO[10], GPIO[11], GPIO[12], GPIO[13], GPIO[14]
1.6
0.15
-1
V
IH
V
IL
V
HYS
V
OL
V
OH
I
LEAKAGE t
DELAY
High level input voltage
Low level input voltage
Input voltage hysteresis
Low level output voltage
High level output voltage
Leakage current
Delay from serial write to pin low
0.22
0.8
0.5
1
500
1.6
0.8
0.15
0.22
I
OUT
= 15mA
I
OUT
= 5mA
0
≤
V out
≤
V
3v3
2.75
-1
0.5
1
C
LOAD
Unit ns
µF
GPIO[8]
Obsolete Product(s) - Obsolete Product(s)
V
V
IL
Low level input voltage 0.8
V
Input voltage hysteresis 0.13
0.22
V V
HYS
V
OL
Low level output voltage I
OUT
= 15mA, 0.4
V
I
LEAK_0
Leakage current
EnGpio8DigIn=0,
0
≤
Vout
≤
5V
-1 1 µA
I
LEAK_1
Leakage current
EnGpio8DigIn=1,
0
≤
Vout
≤
5V
-1 5 µA ns ns
µs ns
V
V
V
V
µA ns
V
V
V
V
V
µA ns
Doc ID 17713 Rev 1 27/139
Electrical specifications L6460
Table 5.
Parameter
Electrical characteristics (continued)
Description Test condition Min Typ Max Unit
I
AD
A/D path absorbed current
ADChannelX[4:0]
=10001 and bit EnDacScale=0
-1 1 µA t
DELAY
Delay from serial write to pin low
C
LOAD
ns
SPI interface
V
IH
V
IL
V
HYS
V
OH
V
OL t
SCLK t
SCLK_rise t
SCLK_fall t
SCLK_high t
SCLK_low t nSS_setup t nSS_hold t nSS_min t
MOSI_setup t
MOSI_hold t
MISO_rise t
MISO_fall t
MISO_valid t
MISO_disable
C
LOAD
High level input voltage
Low level input voltage
Input voltage hysteresis
High level output voltage
Low level output voltage
SCLK period
SCLK rise time
SCLK fall time
SCLK high time
SCLK low time nSS setup time nSS hold time nSS high minimum time
MOSI setup time
MOSI hold time
MISO rise time
MISO fall time
MISO valid from clock low
MISO disable time
MOSI maximum load
I
I
(46)
OUT
OUT
C
= -10mA,
LOAD
C
LOAD
=50pF
=50pF
(47)
(48)
1.6
0.15
2.75
62.5
20
20
10
10
30
10
10
0
0
0.22
0.8
0.4
2
2
9
9
15
15
200
1.
This value is useful to define the voltage rating for external capacitor to be connected from V
Supply
to V
SupplyInt
.
2.
This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple
V
V
V
V
V ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF recommendations on
).
3.
Measured between 10% and 90% of output voltage transition.
4.
Measured from a fault detection to 50% of output voltage transition.
5.
Current is defined to be positive when flowing into the pin.
6.
Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This is to avoid change on output voltage due to heating effect.
7.
Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V
LINmain_FB
).
8.
Default state.
9.
The regulated voltage can be calculated using the formula: V
SWmain_OUT =
V
FBREF
*(R a
+R b
)/R b
.
28/139 Doc ID 17713 Rev 1
10. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V
SW_main_FB
).
11. This condition is intended to simulate an extra current on output.
12. This condition is intended to simulate a short circuit on output.
13. Rise and fall time are measured between 10% and 90% V
SWmain
output voltage.
14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V
SWDRV_FB
).
15. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The protection is performed by switching off the output bridge when current reaches values higher than the I protection could be guaranteed for values in the middle range between I
MAX
and I
OC
OC
max. No
16. In this cell X stands for 1 or 2, Y stands for A or B
17. In this cell X stands for 3 or 4, Y stands for A or B
18. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value
(MtrXSideYILimSel[1:0]= 11) is available.
19. Overcurrent Off time can be configured using SPI.
20. Rise and fall time are measured between 10% and 90% of DC output voltage. With device in full bridge configuration
(resistive load between outputs).
21. Default state for Aux1
22. Default state for Aux2
23. The regulated voltage can be calculated using the formula: V
AUX_SW
= V
FBREF
*(R a
+R b
)/R b
.
24. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (GPIO1 and/or GPIO2)
25. Rise and fall time is measured between 10% and 90% of output voltage.
26. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range.
27. The regulated voltage can be calculated using the formula: V
AUX3_SW
= V
FBREF
*(R a
+R b
)/R b
.
28. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (V
REF_FB
).
29. The definition of LSB for this table is LSB=IMRmax/(2
7.5
-1).
30. Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the
“best straight line” approximating the ADC transfer curve.
31. The ADC ensures monotonic characteristic and no missing codes.
32. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1
LSB.
33. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB).
34. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 - 0.5 LSB), after adjusting for offset error.
35. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is reduced when the ADC is used in the 8- bit resolution mode.
36. Actual input capacitance depends on the pin that must be converted.
37. The definition of LSB for this table is LSB=IMRmax/(2
9
-1).
38. All parameters are guaranteed in the range between V
OL
and V
R Max
.
39. Measured from DacValue[5:0] change in SPI interface.
40. V
GPIO_SPI
= 3.3 V unless otherwise specified
43. Measured between 50% of input and output signal.
44. Time measured from change in SPI interface to 50% of external pin transition.
45. Measured between nSS rising edge and 50% of V out
.
46. Specification applies to nSS, SCLK and MOSI pins.
47. Current is considered to be positive when flowing towards the IC
48. These times are measured at the pin output between specified V
OH
and V
OL
.
Doc ID 17713 Rev 1 29/139
Internal supplies L6460
L6460 includes three internal regulators used to provide a regulated voltage to internal circuits.
The internal regulators are the following:
- V
SupplyInt
regulator.
- Charge pump regulator.
- V
3v3
regulator.
4.1 V
SupplyInt
regulator
V
SupplyInt
is the output of an internal regulator used to supply some internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected to this pin (preferably towards
V
Supply
pin), recommended value is in the range 80 ÷ 120 nF.
Figure 3.
V
SupplyInt
pin
Vsupply VsupplyInt
IS_Int_TYP
L6460 internal circuits
L6460
GND
The V
SupplyInt
pin may also be externally connected to V
Supply
pin by means of an external resistor R
EXT
: this allows R
EXT
, particularly when V
Supply
is at the max values of the operative supply range, to dissipate power that otherwise would be dissipated inside the chip. The choice of the optimal resistor depends on the application since it is strictly depending on both V
Supply
and the current used inside the chip (that is changing with the chosen configuration).
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I
S_Int max is depending from the chosen configuration and represents the total current needed by the circuits connected to this pin.
For example, with V
Supply
= 32 V and I
S_Int
= 12 mA a typical resistor value is 1 k
Ω
.
30/139 Doc ID 17713 Rev 1
L6460 Internal supplies
L6460 implements a charge pump regulator to generate a voltage over V
Supply
.This voltage is used to drive internal circuits and the external FET driver and cannot be used for any other purpose.
This circuit is always under the supervisory circuit control, so no regulator can start before the V
Pump
voltage reaches its undervoltage rising threshold. If V
Pump
voltage falls down below its under voltage falling threshold, all the regulators will be switched off.
The charge pump circuit is disabled when L6460 is in “low power mode”.
Figure 4.
Charge pump block diagram
V SupplyInt
V
Supply
C
BOOST
V Pump
CPH
EnVPump
Driver
M2
M1
CPL
CLK
BOOST
-
+
Ref
An example of capacitors value is: C
FLY
= 100 nF and C
BOOST
= 1 µF for V
Supply
lower than 15V, external diodes are required
C
FLY
V3v3 is the output of an internal regulator used to supply some low voltage internal circuits.
This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected from this pin to GND,
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Doc ID 17713 Rev 1 31/139
Supervisory system L6460
5.1
The supervisory circuitry monitors the state of several functions inside L6460 and resets the device (and other ICs if connected to nRESET pin) when the monitored functions are outside their normal range. Supervisory circuitry can be divided into three main blocks:
– Power on reset (POR) generation circuitry.
– nRESET (nRST_int) generation circuitry.
– Thermal shut down (TSD) generation circuitry.
POR circuitry monitors the voltages that L6460 needs to guarantee its own functionality; nRESET circuitry controls if L6460’s main voltages are inside the normal range; TSD is the thermal shut down of the chip in case of overheating.
Power on reset (POR) circuit
Power on reset circuit monitors V
Supply
, and V
3V3
voltages. The purpose of this circuit is to set the device is in a stable and controlled status until the minimum supply voltages that guarantee the device functionality are reached. The output signal of this circuit (in the following indicated as “POR”) becomes active when V
Supply
or V
3V3
go under their falling threshold.
When POR output signal is active, all functions and all flags inside L6460 are set in their reset state; once POR signal comes back from off state (meaning monitored voltages are above their rising threshold), the power up sequence is re-initialized.
5.2 nRESET generation circuit
The nRESET circuit monitors V
Supply
, V
SupplyInt
, V
Pump
, V
GPIO_SPI
and all system regulators
(V
System
) voltages. The purpose of this circuit is to prevent the device functionality until the monitored voltages reach their operative value (please note that V
3v3
is monitored by POR, so it must be above its minimum value, otherwise nRESET circuit is not active).
This circuit generates an internal reset signal (in the following indicated as “nRST_int”) that will also be signaled to external circuits by pulling low the nRESET pin.
The signal nRST_int becomes active in the following cases:
1.
When one of the following voltages is lower than its own under voltage threshold:
– V
Supply
and V
SupplyInt
.
– V
Pump
.
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– V
GPIO_SPI
.
2. When watchdog timer counter (see
Chapter 6 ) elapse the watchdog timeout time (only
if watchdog function is enabled).
3. When L6460 is in “Low Power mode”.
4. When EnExtSoftRst bit in SoftResReg register is at logic level = “1” and a “SoftRes” command is applied (see SoftResReg register description in
When an nRST_int event is caused by above cases, the nRESET pin will stay low for a
“stretch” time that starts from the moment that nRST_int signal returns in the operative
32/139 Doc ID 17713 Rev 1
L6460 Supervisory system state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register according to following table.
Table 6.
Stretch time selection
ID[1]
1
1
0
0
ID[0]
0
1
0
1
Selected stretch time
Typ
16ms
32ms
48ms
64ms
Note
Default state
When nRST_int becomes active (logic level = “0”) it sets in their reset state some of the functions inside L6460. The main functions that will be reset by nRST_int signal are the following:
– Serial interface will be reset and will not accept any other command.
– The bridges 1 and 2 will place their outputs in high impedance and PWM and direction signals will be reset.
– AD converter will be powered off.
– GPIOs will be powered off.
– Current DAC will be powered off.
– Operational amplifiers will be powered off.
– Watchdog count will be reset (while Watchdog flags won’t be reset).
– Interrupt controller will be powered off.
– Digital comparator will be powered off.
Additionally the system regulators will be powered off but only if the voltage that caused the nRST_int event is checked before the system regulator in the power up sequence. This means that:
– all system regulators will be powered off if nRST_int is caused by V
Supply
,
V
SupplyInt
, V
Pump
(and also if V3v3 causes a POR);
– no one of the system regulators will be powered off if nRST_int is caused by
V
GPIO_SPI
;
– only the system regulators that follows the system regulator that caused the nRST_int in power up sequence will be powered off.
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Doc ID 17713 Rev 1 33/139
Supervisory system
Figure 5.
nReset generation circuit
L6460 t nRST_i nt
Filter
V
Supply UV comparator
UV Filter
V
Supply
UV
V
SupplyInt
UV comparator
UV Filter
V
SupplyInt
UV
V
Pump
UV comparator
UV Filter
V
Pump
UV
V
SysX
UV comparator
UV Filter
System regulators UV nGateCtrl nRESET pin Driver
POR nRESET pin
Note:
V
SysY UV comparator
UV Filter to SPI
All regulator voltages included in power up sequence (V
SysX
– V
SysY
in
considered as nRESET circuit voltages.
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34/139 Doc ID 17713 Rev 1
L6460
5.3
Supervisory system
Thermal shut down generation circuit
The third component of the supervisory circuit is the thermal shut down generation circuit.
This circuit generates two different flags depending on the IC temperature:
– the “TSD” flag indicates that the IC temperature is greater than the maximum allowable temperature.
– the “Warm” flag, that can be read using serial interface, becomes active at a lower temperature respect to TSD signal, therefore it can be used to prevent the IC from reaching over temperature.
When a TSD event occurs, L6460 will enter in the reset state placing the bridges in high impedance and turning off all regulators and other circuits until the internal temperature decreases below the Warm temperature. At this point, L6460 will restart the power up sequence and TSD bit will be set and will be readable as soon as L6460 will come out from the reset state.
This TSD bit can be reset in three ways:
– by writing a logic level ‘1’ in the ClearTSD bit in the ICTemp register (see
– by a POR event;
– by entering in “Low Power Mode”.
The Warm bit, set by L6460 when IC is working over the warming temperature, can be read using the SPI interface. Once this bit is set it can be reset in three ways:
– by writing a logic level ‘1’ in the ClearWarm bit;
– by a POR event;
– by entering in “Low Power Mode”.
The thermal sensor voltage can be converted using the internal A/D: this way the microcontroller can directly measure the IC temperature.
To avoid unwanted commutation especially when temperature is near the thresholds, the output signal is filtered for both TSD and Warm.
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Doc ID 17713 Rev 1 35/139
Watchdog circuit L6460
The Watchdog timer can be used to reset L6460 if it is not serviced by the firmware that can periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register.
This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the
WDEnable bit in the WatchDogCfg register.
When the Watchdog timeout event happens, L6460 sets to ‘1’ a latched bit WDTimeOut in theWatchDogStatus register that can be read using SPI interface; once this bit is set it can be cleared in three ways:
– by writing a ‘1’ in the WDClear bit in the WatchDogStatus register.
– by writing a ‘1’ in the SoftReset bit in the WatchDogStatus register.
– by a POR event.
The Watchdog function includes also a warning bit WDWarning to indicate, via serial
interface or via the circuit called Interrupt Controller (see Chapter 21
) that the watchdog is near to its timeout; this bit is asserted to logic level “1” exactly one watch dog clock period
(WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut signal to cause an “nRst_int” event by setting to logic ‘1’ the WDEnnRst bit.
Figure 6.
Watchdog circuit block diagram
To nRSTint generation circuit
Fosc
Frequency divider
WD_clk Watchdog counter
To SPI
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The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective programmed WD time is changed in the register only when the watchdog circuit is serviced by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of the WD delay value is loaded.
The watchdog timer can be programmed to generate different timeouts using the
WDdelay[3:0] bits in the WatchDogCfg register according to following table.
36/139 Doc ID 17713 Rev 1
L6460
Table 7.
Watchdog timeout specifications
WDdelay[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Watchdog circuit
WD timeout
Typ
8*WD_Tclk
9*WD_Tclk
10*WD_Tclk
11*WD_Tclk
12*WD_Tclk
13*WD_Tclk
14*WD_Tclk
15*WD_Tclk
16*WD_Tclk
17*WD_Tclk
18*WD_Tclk
19*WD_Tclk
20*WD_Tclk
21*WD_Tclk
22*WD_Tclk
23*WD_Tclk
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Doc ID 17713 Rev 1 37/139
Internal clock oscillator
7 Internal clock oscillator
L6460
L6460 includes a free running oscillator that does not require any external components.
This circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16 MHz.
The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is stopped only when in “low power mode”.
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38/139 Doc ID 17713 Rev 1
L6460 Start-up configurations
Note:
L6460 start-up configuration is selected by setting in different states the GPIO[0], GPIO[3] and GPIO[4] pins. Each of these is a three state input pin and is able to distinguish among the following situations:
Table 8.
Possible start-up pins state symbol
Pin condition
Shorted to ground
Shorted to V
3v3
pin
Floating
State symbol
0
1
Z
“Shorted” means: R
≤
1KOhm; “Z” means: R
≥
10KOhm, C
≤
200pF
When V
Supply
voltage is applied to L6460, the internal regulator V3v3, used to supply the logic circuits inside the device, starts its functionality. When it reaches its final value, L6460 enables the GPIO[0] pin state read circuitry, and, after a time TpinSample, it will sample the
GPIO[0] state. If it is found to be in high impedance, L6460 does not consider GPIO[3] and
GPIO[4] pins state and starts its “Basic device” mode sequence. If GPIO[0] is found to be connected to ground or to V3v3, L6460 checks the state of GPIO[3] and GPIO[4] pins to select its start-up configuration.
The possible configurations can be classified in four “Major” modes:
1.
Basic device.
Hereafter is reported the correspondence table between GPIO[X] state and L6460 configurations.
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Doc ID 17713 Rev 1 39/139
Start-up configurations L6460
Table 9.
Start-up correspondence
Pin state
(1)
GPIO[3] GPIO[4]
Major mode Minor mode
(2)
GPIO[0]
0
0
1
1
0
Z
Z
Z
1
1
1
Z
1
Z
Z
0
0
X
0
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
Z
0
1
0
0
Z
Z
1
X
0
Z
1
0
Z
1
0
Z
1
0
Z
1
Basic
Single
Master
Slave
Bridge
Primary regulator
Regulators
Simple regulator
Bridge + VEXT
(3)
Secondary regulators
Bridge
Primary regulator
Regulators
Simple regulator
Secondary regulators
Bridge
Primary regulator
Regulators
Simple regulator
Secondary regulators.
1.
“X” means “don’t care”.
2.
The description of these modes is in the following
3.
VEXT is the regulator output voltage obtained using the switching regulator controller with external FET.
8.2 Basic device mode
The basic device mode is selected by leaving the GPIO[0] pin floating. In this mode L6460 doesn’t use GPIO[3] and GPIO[4] as configuration pins, leaving them free for other uses.
1.
Auxiliary switching regulator1 (V
AUX1_SW
).
2. Auxiliary switching regulator2 (V
AUX2_SW
).
3. Main linear regulator (V
SWmain
).
switching regulator (V
SWmain
) (Not system regulator).
40/139 Doc ID 17713 Rev 1
L6460 Start-up configurations
8.4
In slave device mode, L6460 consider the nAWAKE pin as an input enable. Since this is now a digital pin, the current pull up source inside the nAWAKE circuit is disabled.
At the startup, if the nAWAKE pin is found to be low for a period higher than t
AWAKEFILT
,
L6460 enters directly in the “Low Power mode”; when nAWAKE pin is pulled high for a period higher than t
AWAKEFILT
, L6460 begins its start up procedure.
Master device mode
In master device mode, L6460 begins its start up procedure without waiting for any external enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices.
During the whole start up time, it forces its GPIO[5] pin at logic level “0” in order to maintain all slave devices in “Low Power mode” as previously described. When start up operations are completed, L6460 forces the GPIO[5] output to logic level “1” to enable the slave devices and keeps GPIO[5] output at high level until it senses an under-voltage on any of its System regulators. If firmware writes in the PwrCtrl register to set Master L6460 in “Low Power mode” it immediately forces GPIO[5] output to logic level “0” to force the slave devices to enter in “Low Power mode”, then it waits for T
MASTWAIT
time and it starts its “Low Power mode” sequence.
8.6
In single device mode, the device behaves similarly to master device mode but:
1.
It doesn’t use the GPIO[5] pin to drive slave devices.
2. It doesn’t wait for T
MASTWAIT
before entering in “Low Power mode”.
Sub-configurations for slave, master or single device modes
Each slave, master or single device modes can be divided in other minor modes depending on the start-up sequence needed for L6460 internal regulators.
Unless otherwise specified, in all the following modes the regulators included in the start up sequence are considered system regulators and they start in the sequence indicated.
In this configuration bridges 3 and 4 are not used as regulators and therefore can be
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When in this mode the power-up sequence is:
1.
Main switching regulator (V
SWmain
).
2. Main linear regulator (V
LINmain
).
Doc ID 17713 Rev 1 41/139
Start-up configurations
8.6.2
L6460
Primary regulator mode (KP)
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence
(V
AUX2_SW
) is not considered a system regulator.
When in this mode the power-up sequence is:
1.
Auxiliary switching regulator1 (V
AUX1_SW
).
switching regulator (V
SWmain
) together with main linear regulator (V
LINmain
).
3. Auxiliary switching regulator2 (V
AUX2_SW
) (Not system regulator).
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators, but the start up sequence is different previous one.
When in this mode the power-up sequence is:
1.
Main switching regulator (V
SWmain
).
2. Auxiliary switching regulator1 (V
AUX1_SW
)
3. Auxiliary switching regulator2 (V
AUX2_SW
)
Also in this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence
(V
SWmain
) is not considered a system regulator.
When in this mode the power-up sequence is:
1.
Auxiliary switching regulator1 (V
AUX1_SW
).
2. Auxiliary switching regulator2 (V
AUX2_SW
)
3. Main linear regulator (V
LINmain
) switching regulator (V
SWmain
) (not system regulator).
+ mode
In this configuration bridges 3 and 4 are not used as regulators and the regulator obtained using the switching regulator controller (V
SWDRV
) is included in start-up.
When in this mode the power-up sequence is:
1.
Main switching regulator (V
SWmain
).
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3. Main linear regulator (V
LINmain
).
42/139 Doc ID 17713 Rev 1
L6460
8.6.6
Start-up configurations
Secondary regulators mode
In this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (V
AUX_(1//2)SW
).
When in this mode the power-up sequence is:
1.
Main switching regulator (V
SWmain
).
2. Auxiliary switching regulator (V
AUX(1//2)_SW
).
3. Main linear regulator (V
LINmain
).
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Doc ID 17713 Rev 1 43/139
Power sequencing L6460
As soon as V
Supply
and V
SupplyInt
are above their power on reset level, L6460 will start the charge pump circuit; once V
Pump
voltage reaches its under voltage rising threshold, L6460 begins a sequence that starts the regulators considered system regulators.
A regulator is considered a System regulator if:
– It has to start in on state without any user action.
– It is included in the power-up sequence.
– Its under-voltage event is considered by L6460 as an error condition to be signaled through nRESET pin.
Once V
Supply
and V
SupplyInt
, V
Pump
and all the system regulators are over their under voltage rising threshold, L6460 enters in the normal operating state, that will release nRESET pin and will wait for SPI commands.
L6460 will reduce the noise introduced in the system by switching out of phase all its power circuits (switching regulators, bridges and charge pump).
The L6460's startup sequence of operation is the following:
– start V
3v3
internal linear regulator
– sample startup configuration
– wait enable if slave device
– start charge pump
–
start system regulators (see order in Section 8.6
)
– if master send enable to slave device
– wait until V
GPIO_SPI
becomes ok
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44/139 Doc ID 17713 Rev 1
L6460 Power saving modes
Saving power is very important for today platforms: L6460 implements different functions to achieve different levels of power saving. Sections here below describe these different power saving modes.
Almost all low voltage circuitry inside L6460 are powered by V
3v3
internal regulator; this regulator is a linear regulator powered by V
SupplyInt.
This means that all the current provided by V
3v3
regulator is directly coming from V
SupplyInt
and therefore the total power consumption is:
Low voltage power = V
Supply
* I
V3v3
.
because V
SupplyInt
is feeded by V
Supply
, directly or with a resistor in series.
This power could be reduced by using a switching buck regulator to supply V
3v3
: in this case, assuming the buck regulator efficiency near to 100%, the dissipated power would become:
Low voltage power
≈
3.3V * I
V3v3
.
To achieve this result there is the need to switch off the internal V
3v3
linear regulator and to use an additional pin to provide a 3.3 V supply to internal circuits. L6460 can do this by using the low voltage switch implemented on GPIO6 pin. This switch internally connects
V
GPIO_SPI
voltage to GPIO6 output so, by externally connecting GPIO6 to V
3v3
pin, the
V
GPIO_SPI
voltage can be provided to low voltage circuitry inside L6460.
Figure 7.
Standby mode function description
VSupplyInt
VGPIOSpi
StdByMode
3.3 V
0
1.9 V
1
GPIO6
External connection
+
-
V3v3
Regulator
The StdByMode bit used to switch off V
3v3
and switch on the power switch can be set to ‘1’ by writing the standby command in the StdByMode register. L6460 exits standby mode if a reset event happens or “Low Power mode” is selected.
Because all internal low voltage circuitry powered by V
3v3
are designed to work with a 3.3V voltage rail, when the standby mode is used, V
GPIO_SPI
is requested to be at 3.3V.
Doc ID 17713 Rev 1 45/139
Power saving modes L6460
L6460’s hibernate mode allows the firmware to switch off some (or all) selected System
Regulators leaving in on state only those necessary to resume L6460 to operative condition when waked-up by an external signal.
Hibernate mode is selected when the firmware writes the command word in the
HibernateCmd register. When in hibernate mode L6460 will force regulators in the state
(on/off) selected by the firmware by writing in the HibernateCmd register and will force nRESET pin low.
The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5 pin if L6460 is in Slave mode); L6460 will also exit from hibernate mode if an undervoltage event happens on V
Supply
, V
SupplyInt
, V
Pump
or V
3v3
.
When the exit from hibernate mode is due to an external command, L6460 sets to ‘1’ the bit
HibModeLth in the HibernateStatus register.
10.3 Low power mode
When in normal operating mode, the microcontroller can place L6460 in “Low Power mode”.
In this condition L6460 sets all bridges outputs in high impedance, powers down all regulators (including system regulators and charge pump) and disables almost all its circuits including internal clock reducing as much as possible power consumption.
The only circuits that remain active are:
– V
3V3
internal regulator.
– nAWAKE pin current pull-up.
– nRESET pin that will be pulled low.
– POR circuit.
The entering in low power mode is obtained in different ways depending if L6460 is configured as slave device or not. When L6460 is configured as slave device the low power mode is directly controlled by nAWAKE pin that acts as an enable: if this pin is low for a time longer then t
AWAKEFILT
, Low Power mode is entered; if this pin is high L6460 exits from Low
Power mode.
In all other start-up configurations, Low Power mode is entered by writing a Low Power mode command in the PowerModeControl register; once L6460 is in Low Power mode it starts checking the nAWAKE pin status: if it is found low for a time longer than t
AWAKEFILT
,
L6460 exits from Low Power mode and restarts its startup sequence. When the nAWAKE pin is externally pulled low, the “AWAKE” event is stored and it is readable through SPI.
Obsolete Product(s) - Obsolete Product(s)
Note: When in “Low power mode” V
Supply
is monitored only for its power on reset level.
46/139
At the start up, before L6460 has identified the required operation mode (see
current sink I
INP is always active to pull down nAWAKE pin. As soon as the operation mode
(basic, slave, master or single device) is detected, the functionality of nAWAKE pin will be different.
Doc ID 17713 Rev 1
L6460 Power saving modes
If L6460 is not configured as slave device a current source I
OUT
will be active on this pin, while the current sink I
INP
will be disabled. If L6460 is configured as a Slave device, the current sink I
INP
will be active until nAWAKE pin is detected high for the first time; after that both current sources I
INP
and I
OUT
will be disabled and the nAWAKE pin can be considered as a digital input.
Here below is reported the nAWAKE pin simplified schematic.
Figure 8.
nAWAKE function block diagram
V
3 v 3
S l a veMode
I
OUT
AWAKE_re q
AWAKE nAWAKE s een high for the fir s t time a fter s t a rt u p.
I
INP
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 47/139
Linear main regulator
11 Linear main regulator
L6460
The linear main regulator is directly powered by V
Supply
voltage and it is one of the regulators that L6460 could consider as a system regulator. This means that the voltage generated by this regulator is not used to power any internal circuit, but L6460 will check that the feedback voltage V
LINmain_FB
is in the good value range before enabling all its internal functions. When an under-voltage event (with a duration longer than period t prim_uv defined by the deglitch filter) is detected during normal operation, L6460 will enter in reset state and it will signal this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal blocks.
Here are summarized the primary features of the regulator:
– Regulated output voltage from 0.8V to V
Supply
-2V with a maximum load of 10mA.
– Band gap generated internal reference voltage.
– Short circuit protected (output current is clamped to 22mA typ).
– Under voltage signal (both continuous and latched) accessible through serial interface.
– Low power dissipation mode.
The internal series element is a P-channel MOS device. The voltage regulator will regulate its output so that feedback pin equals V
LINmain_FB
, therefore the regulated voltage can be calculated using the formula:
V
LINmain_OUT
= V
LINmain_ref
*(R a
+R b
)/R b
Figure 9.
Linear main regulator
V supply
Body Diode
V
LINmain_OUT
Cc
R a
+
- V
LINmain_FB
R b
V
LINmain_ref
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48/139
To extend the output current capability this regulator can be used as a controller for an external active component able to provide higher current (i.e. a Darlington device); the external power element allows the handling of an higher current since it dissipates the power externally (the power dissipated by a linear driver supplied at V
Supply
and regulating a voltage V
LINmain_OUT
with an output current I
OUT
is about: P d
= (V
Supply
-V
LINmain_OUT
)*I
OUT
.
Doc ID 17713 Rev 1
L6460 Linear main regulator
Figure 10.
Linear main regulator with external bipolar for high current
V su pply
Body Diode
V
LINm a in_OUT
C lo a d R a
+
-
V
LINm a in_Ref
V
LINm a in_FB
R b
●
●
●
●
Whichever configuration is used (regulator or controller), a ceramic capacitor must be connected on the output pin towards ground to guarantee the stability of the regulator; the value of this capacitance is in the range of 100 nF to 1 µF depending on the regulated voltage;
V
LINmain_OUT
0.8V< V
2.5V= V
V
LINmain_OUT
= 0.8 V --> 1 µF
LINmain_OUT
LINmain_OUT
< 2.5 V --> 0.68 µF
5 V --> 0.33 µF
> 5 V --> 0.1 F
When this regulator is disabled, the whole circuit is switched off and the current consumption is reduced to a very low level both from V3v3 and from V
Supply
. When in this condition, the output pin is pulled low by an internal switch.
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Doc ID 17713 Rev 1 49/139
Main switching regulator
12 Main switching regulator
L6460
Main switching regulator is an asynchronous switching regulator intended to be the source of the main voltage in the system. It implements a soft start strategy and could be a system regulator so even if its output voltage V
SWmain
is not used to power any internal circuit,
L6460 will check that it is in the good value range before enabling all its internal functions.
When L6460 detects a system regulator under-voltage event with a duration longer than the period defined by the deglitch filter (t prim_uv
), it will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal block
(e.g. bridges, GPIOs, …).
The output voltage will be externally set by a divider network connected to feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to choose between four feedback voltage references (and, as a consequence, four under-voltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef bits in the MainSwCfg register.
Here after are summarized the primary features of this regulator:
– Internal power switch.
– Soft start circuitry to limit inrush current flow from primary supply.
– Internally generated PWM (250 kHz switching frequency).
– Nonlinear pulse skipping control.
– Protected against load short circuit.
– Cycle by cycle current limiting using internal current sensor.
– Under voltage signal (both continuous and latched) accessible through SPI.
When L6460 is in “low power mode”, this regulator will be disabled.
In order to save external components and power when using two or more L6460 IC’s on the same board, the primary switching regulator can be disabled by serial interface. Care must be paid using this function because an under-voltage on this regulator, as previously seen, will be read as a fault condition by L6460.
12.1 Pulse skipping operation
Pulse skipping is a well known, non linear, control strategy used in switching regulators.
In this technique (see
Figure 11 ) the feedback comparator output is sampled at the
beginning of each switching cycle. At this time, if the sampled value shows that output voltage is lower than requested one, the complete PWM duty cycle is applied to power
Obsolete Product(s) - Obsolete Product(s) applied to power element only a current limit event can disable the power switch before the whole duty cycle is finished.
50/139 Doc ID 17713 Rev 1
Figure 11.
Main switching regulator functional blocks
VSupply
Current Sense
Charge pump Voltage
High Side
Driver
VSWmain_SW
La
C
R a
From Central Logic Control
Logic
Regulator Freq
Regulator Ref
Voltage
Loop Control
-
+
Under voltage flag
To Central Logic
Filter
-
+ Under voltage
Threshold
VSWmain_FB R b
In pulse skipping control the duty cycle must be chosen by the user depending on supply voltage and output regulated voltage. Therefore the switching regulator has 4 possible duty cycles that can be changed by writing the VmainSwSelPWM bits in the MainSwCfg register according to following
Table 10.
Main switching regulator PWM specification
MainSwCfg register Duty cycle value
Comments
VmainSwSelPWM[1:0]
00
01
10
11
Typical
12%
15%
26%
63.5%
Default state
The output current is limited to a value that can be set by means of SelIlimit bit in the
MainSwCfg register according to following
Obsolete Product(s) - Obsolete Product(s)
Table 11.
Main switching regulator current limit
SelIlimit Current limit (min) Comments
0
1
3.3A
2.3A
Default state
Doc ID 17713 Rev 1 51/139
Switching regulator controller
13 Switching regulator controller
L6460
This circuit controls an external FET to implement a switching buck regulator using a non linear pulse skipping control with internally generated PWM signal.
The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four undervoltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef bits in the SwCtrCfg.
This regulator is switched off when L6460 is powered up for the first time and can be enabled using L6460’s SPI interface.
Here after are summarized the main features of the regulator:
– Soft start circuitry to limit inrush current flow from primary supply.
– Changeable feedback reference voltage
– Internally generated PWM (250 kHz switching frequency).
– Nonlinear pulse skipping control.
– Protected against load short circuit.
– Cycle by cycle current limiting using internal current sensor.
– Under voltage signal (both continuous and latched) accessible through SPI.
Obsolete Product(s) - Obsolete Product(s)
52/139 Doc ID 17713 Rev 1
Figure 12.
Switching regulator controller functional blocks
V supply
Charge pump Voltage
Driver
Current Sense
R sense
V
SWDRW_sns
V
SWDRV_gate
V
SWDRV SW
N-CH Fet
La
From Central Logic Control
Logic
Voltage
Loop Control
-
+
SelFBRef[1:0]
Vref = 3 V
Vref = 3V
Vref=0.8V
Vref=0.8V under voltage flag
Filter
To Central Logic
SelFBRef
Uv Threshold 1
Uv Threshold 2
Regulator Freq
VFBRef
-
+
Under voltage
Threshold
V
SWDRV FB
C
R a
V out
R b
13.1 Pulse skipping operation
Pulse skipping strategy has already been explained on main switching regulator section.
This regulator has 4 possible PWM duty cycles that can be changed writing in the
SelSwCtrPWM bits in the SwCtrCfg register using SPI.
Table 12.
Switching regulator controller PWM specification
SwCtrCfg register Duty cycle value
Comments
SelSwCtrPWM[1:0] Typical
00
01
9% Obsolete Product(s) - Obsolete Product(s)
10 22.5% Default state
11 58%
Doc ID 17713 Rev 1 53/139
Switching regulator controller
The switching regulator controller output driving stage can be represented with an
equivalent circuit as in the Figure 13 :
Figure 13.
Switching regulator controller output driving: equivalent circuit
VPUMP
I
S OURCE
S o u rce comm a nd
S ink p u l s e comm a nd
T s ink
S ink comm a nd
I
S INK
R
S U S TAIN
V
S WDRV_g a te
V
S WDRV_ S W
L6460
As can be seen from the above figure, the external switch gate is charged with a current generator I
SOURCE
and it is discharged towards ground with a current generator I
SINK
that is applied for a T
SINK
pulse while an equivalent resistor R
SUSTAIN
is connected between gate and source until the sink command is present.
13.3 Switching regulator controller application considerations
This controller can implement a step-down switching regulator used to provide a regulated voltage in the range 0.8 V – 32 V. Such kind of variation could be managed by considering some constraints in the application and particularly by choosing the correct feedback
reference voltage as indicated in the Table 13
.
Table 13.
Switching regulator controller application: feedback reference Obsolete Product(s) - Obsolete Product(s)
0.8V
≤
V out
< 5V
5V
≤
V out
≤
32V
0.8V - 1V
2.5V - 3V
54/139 Doc ID 17713 Rev 1
An example of application can be considered the following, supposing the external mosfet type STD12NF06L:
– Max DC current load = 3 A
– Typ Over current threshold = 3 A * 1.5 = 4.5 A
– L = 150 µH
– C = 220-330 µF
In this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the V
Supply
range.
Other application configurations could be evaluated before being implemented.
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Doc ID 17713 Rev 1 55/139
Power bridges L6460
L6460 includes four H bridge power outputs (each one made by two independent half bridges) that are configurable in several different configurations.
Each half bridge is protected against: over-current, over-temperature and short circuit to ground, to supply or across the load. When an over current event occurs, all outputs are turned off (after a filter time), and the over current bit is stored in the internal status register that can be read through SPI.
Positive and negative voltage spikes, which occur when switching inductive loads, are
limited by integrated freewheeling diodes (see Figure 14 ).
Figure 14.
H Bridge block diagram
7TVQQMZ
(IGHSIDE
$RIVER
(IGHSIDE
$RIVER
#ONTROL,OGIC
#ONTROL,OGIC
,OWSIDE
$RIVER
,OWSIDE
$RIVER
(/%
PS
4&/4&
During the start up procedure the bridges are in high impedance and after that they can be enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the bridges return in their start-up condition and they need to be re-enabled from the micro controller.
The bridges can use PWM signals internally generated or externally provided (supplied through the GPIO pins). Internally generated PWM signals will run at approximately
31.25kHz with a duty cycle that, through serial interface, can be programmed and incremented in steps of 1/(512*F osc
). To reduce the peak current requested from supply Obsolete Product(s) - Obsolete Product(s) of-phase.
Each half bridge will use the PWM signal selected by the respective
MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if two half bridges are configured as a full bridge, only the PWM signal chosen for side A will be used to drive the resulting H bridge.
More in detail the PWM selection truth table will be as describe in the following tables:
56/139 Doc ID 17713 Rev 1
L6460 Power bridges
Table 14.
PWM selection truth table for bridge 1 or 2
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] Selected PWM
(1)
0
0
0
1
1
1
0
1
1.
In this table X stands for 1 or 2, Y stands for A or B.
MotorXPWM (Configurable by means of MtrXCfg register).
AuxXPWM (Configurable by means of
AuxPwmXCtrl register).
ExtPWM1 (from GPIO 9 input)
ExtPWM2 (from GPIO 10 input)
Table 15.
PWM selection truth table for bridge 3 or 4
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] Selected PWM
(1)
0
0
0
1
1
1
0
1
1.
In this table X stands for 3 or 4, Y stands for A or B.
MotorXPWM (Configurable by means of
MtrXCfg register).
AuxXPWM (Configurable by means of
AuxPwmXCtrl register).
ExtPWM3 (from GPIO 2 input)
ExtPWM4 (from GPIO 11 input)
In
Figure 15 is reported a block diagram representing the possible PWM choices for each
L6460 half bridges. The figure is related only to bridges 1 and 2, but it could be assumed to be valid also for bridges 3 and 4, with few differences due to different possible configurations of these last drivers.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 57/139
L6460 Power bridges
Figure 15.
Bridge 1 and 2 PWM selection
Mtr1SelPWMSide A[1:0]
00 Motor1 PWM
01 Aux1PWM
10 ExtPWM1
11 ExtPWM2
Mtr1SelPWMSideB [1:0]
00 Motor1 PWM
01Aux1PWM
10ExtPWM1
11ExtPWM2
Motor 1 side A
Logic Table
Mtr1_2Parallel
Mtr1Tablel[1:0]
Motor 1 sideB
Logic Table
Bridge1
Mtr2SelPWMSideA[1:0]
Mtr1_2Parallel
Mtr2Tablel[1:0]
00 Motor2 PWM
01Aux2Pwm
10ExtPwm1
Motor 2 side A
Logic Table
11ExtPwm2
Mtr2SelPWMSide B [1:0]
Mtr1_2Parallel
Mtr2Tablel[1:0]
00 Motor2 PWM
Motor 2 sideB
Logic Table 01 Aux2Pwm
10 ExtPwm1
11 ExtPwm2
Bridge 2
Obsolete Product(s) - Obsolete Product(s)
58/139 Doc ID 17713 Rev 1
L6460 Power bridges
The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0] bits in the MtrXCfg register. The table below shows the correspondence between
MtrXTable[1:0] bits and the bridge configuration.
Table 16.
Bridge selection
MtrXTable[1] MtrXTable[0]
1
1
0
0
0
1
0
1
Bridge configuration
Full bridge
High or low side switch
Half bridge
High or low side switch
Bridge 1 & 2 can be paralleled by means of Mtr1_2Parallel bit in the Mtr1_2Cfg register:
Bridge 1 and 2 paralleled will form superbridge1, bridge X side A and bridge X side B paralleled form SuperHalfBridgeX or SuperSwitchX.
Bridge 3 & 4 can be configured by means of Mtr3_4CfgTable[1:0] bits in the Mtr3_4Cfg register according to following table:
Table 17.
Bridge 3 and 4 configuration
Mtr3_4CfgTable[1] Mtr3_4CfgTable[0]
1
1
0
0
0
1
0
1
Bridge 3 and 4 configuration
Two independent bridges
Two bridges in parallel
Stepper motor
Stepper motor
The possible configurations for the bridges are described in the following.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 59/139
Power bridges L6460
Note:
When in full bridge configuration, the drivers will behave according to the following truth table:
Table 18.
Full bridge truth table
TSD nRESET
Low power mode
Enable
Current limit
MtrXCtrl
SideA
MtrXCtrl
SideB
PWM OUT+ OUT-
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
X
0
1
1
1
1
0
0
0
1
0
X
X
0
0
0
0
1
1
1
X
0
X
X
1
1
1
1
1
0
0
X
X
X
X
0
0
0
0
X
0
0
X
X
X
X
0
1
1
1
X
0
1
X
X
X
X
1
0
0
1
X
X
0
X
X
X
X
1
0
1
X
Z
0
1
Z
Z
Z
Z
0
1
1
1
Z
0
1
Z
Z
Z
Z
1
1
0
1
Note: When “low power mode” is active, the bridges will enter in low power state and will reduce its biasing thus contributing to the power saving.
When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the off time.
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60/139 Doc ID 17713 Rev 1
L6460 Power bridges
Bridges 1, 2, 3 and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one super bridge thus enabling the driving of loads (motors) requiring high currents. In this configuration the half bridges will be paralleled and will work as one phase of the superbridge just created: the two phases + will become phase + of the newly created superbridge while the two phases - will become phase –.
Figure 16.
Super bridge configuration
Parallel Full Bridge
+ +
When this configuration is chosen for bridges 1 (3) and 2 (4), the resulting bridge will use the driving logic of bridge 1 (3) so for programming it must be used the bridge 1 (3) control and status bits (direction, PWM, ...): i.e. the used PWM signal will be chosen by
Mtr1SideAPwmSel[1:0] (Mtr3SideAPwmSel[1:0]) bits in SPI.
If the bridges are not configured to be used in parallel, each side of the bridge will use the
PWM selected by the respective MtrXPWMYSel[1:0] bits in the SPI, but if one of the two drivers is configured as a full bridge only one of the two selected PWM will be used to drive the motor and this is the PWM chosen for side A.
In order to avoid any problem coming from different propagation times of PWM signals the anti-crossover dead times are slightly increased when the bridges are paralleled.
Obsolete Product(s) - Obsolete Product(s)
Each bridge can be configured to be used as 2 independent half bridges or as 1 super half
bridge (see Figure 17 ). It is also possible to parallel more than one bridge and use all of
them as a single super half bridge.
Doc ID 17713 Rev 1 61/139
Power bridges
Figure 17.
Half bridge configuration
V pump
Control Signals
From SPI
Control
Logic
High side
Driver
Low side
Driver
V
Supply
DCX Phase output
L6460
In this case each half bridge will behave according to the following truth table.
Table 19.
Half bridge truth table
TSD nReset
Low power mode
Enable
Current limit
MtrXCtrl
SideA/B
PWM OUT
0
0
0
0
0
1
0
1
1
1
1
1
X
0
1
0
0
0
0
X
X
X
0
1
1
1
X
X
X
X
0
0
0
X
X
X
X
0
0
1
X
X
X
X
0
1
0
X
X
0 1 0 1 0 1 1 1
0 1 0 1 1 X X Z Obsolete Product(s) - Obsolete Product(s)
Note: When “low power mode” bit is active the bridges will reduce its biasing thus contributing to the power saving.
When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the off time.
Z
Z
Z
0
Z
Z
Z
62/139 Doc ID 17713 Rev 1
L6460 Power bridges
Each bridge can be configured to be used as 2 independent switches that connects the output to supply or to ground. It is also possible to parallel the two switches and use them as a single super switch.
All resulting switches will behave according to the following truth table.
Table 20.
Switch truth table
TSD nReset
Low power mode
0
0
0
0
0
0
1
0
1
1
1
1
1
1
X
0
0
0
0
0
1
0
X
X
Enable
1
1
1
1
X
0
X
X
Current limit
0
1
0
0
X
X
X
X
MtrXCtrl
SideA/B
1
X
0
1
X
X
X
X
PWM
1
X
X
0
X
X
X
X
OUT
0
Z
Z
1
Z
Z
Z
Z
Note: When “low power mode” bit is active the bridge will reduce its biasing thus contributing to the whole power saving.
When a current limit event occurs this event will be latched and the bridge will remain in high impedance state for the toff time.
14.1.5 Bipolar stepper configuration
The bridges 3 and 4 can be configured to be used as a micro-stepping, bidirectional driver for bipolar stepper motors.
The primary features of the driver are the following:
– Internal PWM current control.
– Micro stepping.
– Fast, mixed and slow current decay modes.
Each H-bridge is controlled with a fixed and selectable off-time PWM current control circuit that limits the load current to a value set by choosing V
STEPREF
voltage by means of the Obsolete Product(s) - Obsolete Product(s)
The max current level could be calculated using the formula:
I
MAX
=V
STEPREF
/R
SENSE
To obtain the best current profile, the user can choose three different current decay modes: slow, fast and mixed. Initially, during Ton, a diagonal pair of source and sink power MOS is enabled and current flows through the motor winding and the sense resistor. When the voltage across the sense resistor reaches the programmed DAC output voltage, the control logic will change the status of the bridge according to the selected decay mode (slow, fast or mixed). In slow decay mode the current is recirculated through the path including both high
Doc ID 17713 Rev 1 63/139
Power bridges L6460 side power MOS for the whole off time. In fast decay mode the current is recirculated through the high and low side power MOS opposite respect to those forcing current to increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay followed by slow decay) and allows the user to find the best trade off between load current ripple and fast current levels transition. Additionally, by setting the
SeqMixedOnlyInDecreasingPh bit in the StpCfg1 register, the user can choose to apply the fast decay percentage in mixed mode always or only when the current is decreasing (i.e from 90° to 180° and from 270° to 360° of the sinusoidal wave).
●
●
●
●
●
●
●
By using SPI interface the user can choose:
Control type (external firmware control, half step, normal drive, wave drive, micro-step).
Up to 16 current levels (quasi-sinusoidal increments) for each bridge.
Current direction.
Decay mode.
Blanking time.
Off time (32 values from 2 µ s to 64 µ s).
Percentage of fast decay respect to toff (when in mixed decay mode).
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64/139 Doc ID 17713 Rev 1
L6460
Figure 18.
Bipolar stepper configuration
Power bridges
DC3
SENSE
VRefA
DC3
_PH-
V supply
DC3
_PH+
Supply
PH-
Sense
PH+
Bridge Driver
- Control Logic
- Toff generation
- DAC reference selection
Bridge Driver
Stepper
Motor
Supply
DC4
PH-
PH-
Sense
PH+
DC4
PH+
Ref1
Ref2
SelStepRef
V
STEPREF
VRefA
VRefB
StepperDACPhA
StepperDACPhB
VRefB
DC4
SENSE internally generate the stepping levels. In these cases and depending on the StepFromGpio bit in the StpCfg1 register the Stepper driver will move to next step each time the StepCmd bit is set at logic level “1” or at each pulse transition longer than ~1 µ s externally applied on
GPIO12 (StepReq signal), according to Table 21
.
Doc ID 17713 Rev 1 65/139
Power bridges L6460
Table 21.
Sequencer driver
StepFromGpio
0
1
Sequencer driver
StepCmd bit in StepCmd register.
GPIO12 input pin.
The allowable control modes are as follows:
1.
Stepping sequence left to external microcontroller: in this mode the current level in each motor winding is set by the microcontroller via the serial interface.
2. Full step: in this mode the electrical angle will change by 90° steps at each StepReq signal transition. There are two possibilities:
– Normal step (two phases on): in normal step mode both windings are energized simultaneously and the current will be alternately reversed. The resulting electrical angles will be 45°, 135°, 225° and 315°.
– Wave drive (one phase on): In wave drive mode each winding is alternately energized and reversed. The resulting electrical angles will be 90°, 180° and 270° and 360°.
3. Half step: in this mode, one motor winding is energized and then two windings alternately so the electrical angles the motor will do when rotating in clockwise direction and using the same current limit in both the phases are: 45°, 90°, 135°, 180°, 225°,
270°, 315° and 360°.
4. Microstepping: in this mode the current in each motor winding has a quasi sinusoidal profile. The increment between each step is obtained at each transition of StepCmd bit in StepCmd register. The difference between each step could be chosen (4, 8 or 16 levels for each phase) according to following table:
Table 22.
Stepper driving mode
StepCtrlMode[2:0] Control mode Description
000 or 111
001
010
011
No Control
Half Step
Normal Step
Wave Drive
Stepping sequence control left to the external controller
Half step
Full step (two phases on)
Full step (one phase on)
100 1/4 Step Four micro steps
110 1/16 Step Sixteen micro steps Obsolete Product(s) - Obsolete Product(s)
Note:
101 1/8 Step Eight micro steps
When in 1/16 step mode, the best phase approximation of sinusoidal wave, is obtained by repeating the “F” step as follows: 0, 1, 2, 3, … , D, E, F, F, F, E, D, … , 3, 2, 1, 0
When internal stepping sequence generation is used, the stepping direction is set by the
StepDir bit according to the
.
66/139 Doc ID 17713 Rev 1
L6460
Note:
Power bridges
Table 23.
Stepper sequencer direction
StepDir
0
1
Direction
Counter clockwise (CCW)
Clockwise (CW)
It is intended as clockwise the sequence that forces a clockwise rotation of the versors representing the current module and phase.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 67/139
Power bridges L6460
An internal DAC is used to digitally control the output regulated current. The available values are chosen to provide a quasi sinusoidal profile of the current. The current limit in each phase is decided by PhADAC[3:0] bits for phase A and PhBDAC[3:0] bits for phase B. The table below describes the relation between the value programmed in the stepper DAC and the current level.
Table 24.
DAC
PhXDAC [3:0]
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Phase current ratio respect to I
MAX
Typ Max
77.3
83.1
88.2
92.4
95.7
98.1
I
MAX
(Hi-Z)
9.8
19.5
29.0
38.3
47.1
55.6
63.4
70.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
% of I
MAX
% of I
MAX
% of I
MAX
% of I
MAX
% of I
MAX
% of I
MAX
% of I
MAX
% of I
MAX
% of I
MAX
% of I
MAX
% of IMAX
% of I
MAX
% of I
MAX
% of I
MAX
Note: The min and max values are guaranteed by testing the percentage of VSTEPREF that allows the commutation of the Rsense comparator.
I
MAX
=V
STEPREF
/ R
SENSE
.
To obtain the best phase approximation of a sinusoidal wave, the user needs to repeat the final (100%) value. So the full values sequence should be as follows: 0, 1, 2, 3 … D, E, F, F,
F, E, D … 3, 2, 1, 0.
Obsolete Product(s) - Obsolete Product(s) guaranteed by design.
When the internal sequencer the minimum angle resolution is nominally 5.625°, so depending on the control mode chosen, the selectable steps are
68/139 Doc ID 17713 Rev 1
L6460 Power bridges
Table 25.
Internal sequencer
Control mode
Typical output current (% of IMAX)
Resulting electrical angle
Half step
1
Full step
(2 phases on)
Full step
(1 phase on)
1
1/4 step
1
1/8 step
1
2
3
4
2
1
2
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
25
26
27
28
29
30
31
1/16 step
Phase A
(sin)
Phase B
(cos)
Electrical degrees
11
12
13
14
15
16
5
6
7
8
9
10
3
4
1
2
20
21
22
23
17
18
19
19.5
9.8
HiZ
-9.8
-19.5
-29.0
70.7
63.4
55.6
47.1
38.3
29.0
-38.3
-47.1
-55.6
98.1
95.7
92.4
88.2
83.1
77.3
70.7
77.3
83.1
88.2
92.4
95.7
98.1
100
100
100
-98.1
-100
-100
-100
-98.1
-95.7
-70.7
-77.3
-83.1
-88.2
-92.4
-95.7
-92.4
-88.2
-83.1
-19.5
-29.0
-38.3
-47.1
-55.6
-63.4
70.7
63.4
55.6
47.1
38.3
29.0
19.5
9.8
HiZ
-9.8
168.8°
174.4°
180°
185.6°
191.2°
196.9°
135°
140.6°
146.2°
151.9°
157.5°
163.1°
202.5°
208.1°
213.8°
101.2°
106.9°
112.5°
118.1°
123.8°
129.4°
45°
50.6°
56.2°
61.9°
67.5°
73.1°
78.8°
84.4°
90°
95.6°
Doc ID 17713 Rev 1 69/139
Power bridges L6460
Table 25.
Internal sequencer (continued)
Control mode
Typical output current (% of IMAX)
Resulting electrical angle
Half step
Full step
(2 phases on)
Full step
(1 phase on)
1/4 step
1/8 step
1/16 step
Phase A
(sin)
Phase B
(cos)
Electrical degrees
5
6
7
3
4
3
9
10
11
12
13
17
18
19
20
21
22
23
24
25
26
40
41
42
43
44
45
36
37
38
39
32
33
34
35
49
50
51
52
53
46
47
48
-100
-100
-100
-98.1
-95.7
-92.4
-63.4
-70.7
-77.3
-83.1
-88.2
-92.4
-95.7
-98.1
-88.2
-83.1
-77.3
-70.7
-63.4
-55.6
-47.1
-38.3
-9.8
HiZ
9.8
19.5
29.0
38.3
-77.3
-70.7
-63.4
-55.6
-47.1
-38.3
-29.0
-19.5
47.1
55.6
63.4
70.7
77.3
83.1
88.2
92.4
264.4°
270°
275.6°
281.2°
286.9°
292.5°
219.4°
225°
230.6°
236.2°
241.9°
247.5°
253.1°
258.8°
298.1°
303.8°
309.4°
315°
320.6°
326.2°
331.9°
337.5° 14 27
54 -29.0
95.7
343.1°
28 55 -19.5
98.1
348.8° Obsolete Product(s) - Obsolete Product(s)
56 -9.8
100 354.4°
8 4 15 29 57 HiZ 100 360°/0°
16
30
31
58
59
60
61
62
9.8
19.5
29.0
38.3
47.1
100
98.1
95.7
92.4
88.2
5.6°
11.2°
16.9°
22.5°
28.1°
70/139 Doc ID 17713 Rev 1
L6460 Power bridges
Table 25.
Internal sequencer (continued)
Control mode
Typical output current (% of IMAX)
Resulting electrical angle
Half step
Full step
(2 phases on)
Full step
(1 phase on)
1/4 step
1/8 step
32
1/16 step
Phase A
(sin)
Phase B
(cos)
Electrical degrees
63
64
55.6
63.4
83.1
77.3
33.8°
39.4°
The voltage spikes on R sense
could be filtered by selecting an appropriate blanking time on the output of current sense comparator. The Blanking time selection is made by using the
StepBlkTime[1:0] bits in the StpCfg1 register.
The stepper driver off time could be programmed by means of the StepOffTime[4:0] bits in
StpCfg1 register.
Table 26.
Stepper off time
Off time
StepOffTime[4:0] Unit
Typ
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
2
4
6
8
10
12
14
16
18
20
01010
01011
22
24
µs
µs
01100 26 µs Obsolete Product(s) - Obsolete Product(s)
01101 28 µs
01110 30 µs
01111
10000
10001
10010
10011
32
34
36
38
40
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Doc ID 17713 Rev 1 71/139
Power bridges
Table 26.
Stepper off time (continued)
StepOffTime[4:0]
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Off time
Typ
50
52
54
56
58
60
62
64
42
44
46
48
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
L6460
By means of MixDecPhA[4:0] and MixDecPhB[4:0] in StepCfg2 register, the percentage of off time during which each phase will stay in fast decay mode could be programmed according to
.
Obsolete Product(s) - Obsolete Product(s)
72/139 Doc ID 17713 Rev 1
L6460 Power bridges
Table 27.
Stepper fast decay
MixDecPhX[4:0]
00111
01000
01001
01010
01011
01100
01101
01110
01111
1xxxx
00000
00001
00010
00011
00100
00101
00110
Fast decay percentage during off time
Typ
43.75
50
56.25
62.5
68.75
75
81.25
87.5
93.75
100
0
6.25
12.5
18.75
25
31.25
37.6
Unit
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
14.1.6 Synchronous buck regulator configuration (Bridge 3)
Bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as a single high current synchronous buck regulator using GPIOs pins in order to close the voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control loop using an internally generated PWM signal. The voltage will be set externally with a divider network and PWM duty cycle that can be programmed in order to ensure a proper regulation.
The regulator will be enabled/disabled using serial interface and will implement a soft start strategy similar to that used by primary switching regulator.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 73/139
Power bridges L6460
Here after are summarized the primary features of the regulator(s):
– Synchronous rectification
– Automatic low side disabling when current in the inductance reaches 0 to optimize efficiency at low load
– Pulse skipping control
– Internally generated PWM
– Cycle by cycle current limiting using internal current sensor
– Protected against load short circuit
– Soft start circuitry
– Under voltage signal (both continuous and latched) accessible through serial interface.
Figure 19.
Regulator block diagram
V su pply
C u rrent en s e
Ch a rge p u mp Volt a ge
High S ide
Driver
H a lf Bridge OUT
L a
V o u t
R a
Low S ide
Driver C
Bridge S en s e
From Centr a l Logic Control
Logic
Reg u l a tor Fre q
Reg u l a tor Ref
Volt a ge
Loop Control
-
+
GPIO U S ED as FB
R b
Vref= 3 V
N.C.
N.C.
Vref= 0.
8 V
S elFBRef
O b t a ined us ing s p a re a n a lo g /di g it a l b lock s
To Centr a l Logic
-
Filter
Under volt a ge +
Thre s hold
Obsolete Product(s) - Obsolete Product(s)
Depending on the load current, there could be the necessity to add a Schottky diode on output to reduce internal thermal dissipation. This diode must be placed near to the pin and must be fast recovery and low series resistance type.
For detail about pulse skipping please refer to main switching regulator
.
The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under-
74/139 Doc ID 17713 Rev 1
L6460 Power bridges voltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef[1:0] bits in the Aux1SwCfg or Aux2SwCfg registers.
The switching regulators have four possible PWM duty cycles that can be changed using
.
Table 28.
PWM specification
AuxXPWMTable[1:0] Typical duty cycle value
00
01
10
11
10%
13%
24%
61%
Comments
Default state for AUX1
Default state for AUX2
As seen before L6460 contains 2 regulation loops for switching regulators that are used when bridge 3 is used as a regulator. These loops are assembled using internal comparators and filters similar to that used in main switching regulator.
When bridge 3 is not used for this purpose or when only one regulation loop is needed, the control loop is available on a GPIO output thus enabling the customer to assembly a basic buck switching regulator using an external Power FET. The comparators used in the above mentioned regulation loops are general purpose low voltage (3.3 V) comparators; when the
relative regulation loop is not used they can be accessed as shown in the Figure 20 .
Figure 20.
Internal comparator functional block diagram
GPIOx GPIOy
GPIOx
DECODE
LOGIC
GPIOy
DECODE
LOGIC
GPIOyMode
+
V
3 v 3
GPIOz
GPIOzMod e
GPIOz V a l u e From S PI
GPIOz
DECODE
LOGIC
Driver
Doc ID 17713 Rev 1 75/139
Power bridges L6460
14.1.8 Battery charger or switching regulator (Bridge 4)
The functionality of this circuit is obtained by using the bridge 4 output stage. This circuit is powered directly from V
Supply
and it is intended to be used as a battery charger or a switching regulator.
The control loop block diagram is shown in the Figure 21 .
Figure 21.
Battery charger control loop block diagram
L6460
PULSE SKIPPING
BURST
CONTROL LOGIC
PEAK CURRENT
MODE CONTROL
LOGIC
PWM
Ilimit
IREF_FB
COMP_I
VREF_FB
COMP_V
BRIDGE 4
PARALLELED
POWER
STAGE
DC4_plus
DC4_minus
FBRef
SelFBRef<1:0>
SelCurrRef<1:0>
CurrRef
DIFF
AMPLI
TO
LOAD
The battery charger control loop implements an asynchronous switching regulator intended to be used as a constant voltage/constant current programmable source.
When used as a simple switching regulator, it could be a system regulator depending on startup configurations
When a system regulator under-voltage event is detected L6460 will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal blocks.
When the control loop is intended to be used as a battery charger, the Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. This is because in this case the undervoltage event that will be sure present when charging a battery (see battery charger
Obsolete Product(s) - Obsolete Product(s)
The regulated output voltage will be externally set by a resistor divider network connected to
V
REF_FB
pin. L6460 has the possibility to choose between four voltage references (and, as a consequence, four under-voltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef[1:0] bits in the Aux3SwCfg1 register.
The regulation of the output current can be done externally, by using a sense resistor connected in series on the path that provides current to the load. By using an external differential amplifier the customer can set the desired V = f(I) characteristic, and therefore
76/139 Doc ID 17713 Rev 1
L6460 Power bridges the regulated current: the voltage provided at the I
REF_FB
pin will be compared to the internal reference. L6460 has the possibility to choose between four voltage references using the serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register.
Regardless of the CurrRef voltage, if the I
REF_FB
pin remains below the chosen threshold, the internal current limitation will work (typical Ilimit current 4A).
The battery charge profile can be chosen by fixing the desired CurrRef and FBRef internal reference voltages and by choosing the desired V = f(I) trans-characteristic of the external differential amplifier.
In the
Figure 22 is shown a typical Li-Ion battery charge profile.
Figure 22.
Li-ion battery charge profile
Voltage or Current
Veochrg
Blue=Battery Voltage FBRef depending
Vchrg
Ichrg
Red=Battery Current
CurrRef depending
Iprechrg
Ieochrg
Time
Precharge phase
Rapid charge phase
Constant V. phase
End Of Charge
The battery charge loop control can be used to implement a buck type switching regulator.
The regulated output voltage will be externally set by a resistor divider network connected to
V
REF_FB
pin, as already described and the current protection will be the one implemented
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 77/139
Power bridges
Figure 23.
Simple buck regulator
L6460
IREF_FB
PULSE SKIPPING
BURST
CONTROL LOGIC
PEAK CURRENT
MODE CONTROL
LOGIC
PWM
Ilimit
COMP_I VREF_FB
COMP_V
BRIDGE 4
PARALLELED
POWER
STAGE
DC4_plus
DC4_minus
FBRef
SelFBRef<1:0>
SelCurrRef<1:0>
CurrRef
L6460
TO
LOAD
When this control loop is intended to be used as a simple buck regulator, the proper
Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register.
The regulator will also implement a soft start strategy.
When L6460 “low power mode” is enabled this regulator will be disabled.
Here after are summarized the primary features of the regulator:
– Internal power switch.
– Nonlinear pulse skipping control.
– Internally generated PWM (250 KHz switching frequency).
– Cycle by cycle current limiting using internal current sensor/ external current sense differential amplifier.
– Protected against load short circuit.
– Soft start circuitry to limit inrush current flow from primary supply.
Obsolete Product(s) - Obsolete Product(s)
– Over temperature protection.
In pulse skipping control PWM the duty cycle must be decided by the user depending on supply voltage and regulated voltage.
Therefore the switching regulator has 4 possible PWM duty cycles that can be changed writing in the Aux3PWMTable[1:0] bits in the Aux3SwCfg1 register according to the
.
78/139 Doc ID 17713 Rev 1
L6460 Power bridges
Table 29.
Battery charger regulator controller PWM specification
Aux3PWMTable [1:0] Typical duty cycle value Comments
00
01
10
11
10%
13%
24%
61%
Default state
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 79/139
AD converter L6460
L6460 integrates and makes accessible via SPI a general purpose multi-input channel 3.3V analog to digital converter (ADC).
●
●
The ADC can be configured to be used as:
8-bit resolution ADC.
9-bit resolution ADC.
The result of the conversion will always be a 9-bit word; the difference between the two configurations is that, to speed up the conversion, the resolution is reduced when the ADC is used in the 8-bit resolution mode.
The ADC is seen at software level as a 2 channel ADC with different programmable sample times; a finite state machine will sample the requests done through the SPI interface on both the channel and will execute them in sequence.
When used as 8-bit resolution the ADC can achieve a higher throughput and, if the minimum sample time is used, one conversion is completed in t = 5.5 µs. When used as 9-bit resolution ADC the circuit is slower and the minimum sample times are disabled. In that case the conversion will be completed in a time t= 10 µs.
The use of ADC type must be decided at the start-up by writing in the one time programmable ADC configuration register; no A/D conversion will be enabled if this register is not set from last power-up sequence.
This ADC can be used to measure some external pins as well as some L6460’s internal voltages. The converter is based on a cyclic architecture with an internal sample-and-hold circuit. Sample time can be changed using serial interface to enable good measure of higher impedance sources.
Obsolete Product(s) - Obsolete Product(s)
80/139 Doc ID 17713 Rev 1
L6460
Figure 24.
A2D block diagram
V su pply
V p u mp
V
3 v 3
V
LINm a in FB
V
S Wm a in FB
V
S WDRV_F
GPIO[0:14]
RefOpAmpX
O u t S trip S tepperPHX
C u rrent DAC
Temp S en s or s
An a log M u x
S &H
A2D
AD converter
Conver s ion
Addre ss 0
Conver s ion
Addre ss 1
To S PI
The A2D system is enabled by setting the A2DEnable bit to ‘1’ in the A2DControl register.
The A2DType bit in the A2DConfigX registers selects the A2D active configuration (8-bit resolution or 9-bit) according to the
Table 30.
ADC truth table
A2DEnable
0
1
1
X
0
1
Disabled
ADC working as a 8-bit ADC
ADC working as a 9-bit ADC
A2DChannel2[4:0] bits in the A2DConfigX register; the channel addresses table is reported in the
.
Doc ID 17713 Rev 1 81/139
AD converter L6460
Table 31.
Channel addresses
A2DChannelX[4:0] (bin.) Converted channel
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
00000
00001
00010
00011
00100
00101
0011X
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11101
11110
11111
V
Supply
scaled
V
SupplyInt
scaled
V ref_2_5V
Temp Sensor1
Temp Sensor2
V
3v3
scaled
Not used
Not used
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8] clamp
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
MuxRefOpAmp1
MuxRefOpAmp2
OutStripStepperPhA
OutStripStepperPhB
Not used
ST reserved
ST reserved
ST reserved
Note
See voltage divider specification.
See voltage divider specification.
Temperature sensor1
Temperature sensor2
See voltage divider specification.
See current DAC circuit
References AUX1 switching reg.
0.8V reference voltage
1.65V reference voltage
The sample time can be changed by modifying the A2DSampleX[2:0] bits in the
A2DConfigX register; depending on which is the A2DType bit, the available sample times
and
.
82/139 Doc ID 17713 Rev 1
L6460 AD converter
Table 32.
ADC sample times when working as a 8-bit ADC
Sample time
A2DSampleX[2:0] (binary)
Typ
100
101
110
111
000
001
010
011
16*T osc
32*T osc
64*T osc
128*T osc
256*T osc
512*T osc
1024*T osc
2048*T osc
Table 33.
ADC sample time when working as a 9-bit ADC
Sample time
A2DSampleX[2:0] (binary)
Typ
100
101
110
111
000
001
010
011
32*T osc
64*T osc
128*T osc
256*T osc
512*T osc
1024*T osc
2048*T osc
4096*T osc
A conversion on channel 1 can be triggered by writing a logic ‘1’ in the A2DTrig1 bit in the
A2DConfigX register and a conversion on channel 2 can be triggered writing a logic ‘1’ in the
A2DTrig2 bit in the same register. While a request on a channel is pending but not yet completed L6460 will force to logic ‘0’ the corresponding A2DdoneX bit in the A2DResultX registers and L6460 will not accept other conversion request on that channel.
Continuous conversion on one channel can be accomplished by setting to logic ‘1’ the
Obsolete Product(s) - Obsolete Product(s) conversions can be accomplished on the other channel; these conversions will be inserted between two conversions of the other channel and the end of the conversion will be signaled using A2DdoneX bit. Of course when a channel is in continuous mode its sample time and channel address cannot be changed.
Continuous conversions on both 2 channels can be also accomplished by setting to logic ‘1’ the A2Dcontinuous1 and A2Dcontinuous2 bits; the conversions are made in sequence.
Unit
µs
µs
µs
µs
µs
µs
µs
µs
Unit
µs
µs
µs
µs
µs
µs
µs
µs
Doc ID 17713 Rev 1 83/139
AD converter L6460
15.1 Voltage divider specifications
As can be seen in the A2D block diagram, in order to report some voltages in the A2D working range, they are scaled with a resistor divider before the conversion.
Here below are reported the resistor voltage divider specifications:
Table 34.
Voltage divider specification
Parameter Description
R
Supply_ratio
R
SupplyInt_ratio
R
V3V3_ratio
V
Supply
divider ratio
V
Supply Int
divider ratio
V
3v3 divider ratio
Notes Min
-
-
-
Typ
1/15
1/15
1/2
Max
-
-
-
Unit
Obsolete Product(s) - Obsolete Product(s)
84/139 Doc ID 17713 Rev 1
L6460
16 Current DAC circuit
Current DAC circuit
L6460 includes a multiple range 6-bit current sink DAC. The LSB value of this DAC can be selected using the DacRange[1:0] bits in the CurrDacCtrl register.
The output of this circuit is connected to GPIO[8] that is a 5 V tolerant pin. The value of this pin can be converted using ADC. The pin value can be scaled before being converted by enabling the internal resistor divider connected to this pin. If the current sunk by resistor divider is not acceptable the pin voltage can be converted without scaling its value. When the conversion without scaling resistor is chosen a clamping connection is used to avoid voltage compatibility of the pin to the ADC system. The clamping circuit will sink a typical current of half microampere from the pin during the sampling time.
Figure 25.
Current DAC block diagram
V a3
D a cR a nge [1:0]
Reference C u rrent
Gener a tor
EnD a c
D a cV a l u e[5:0]
D a cR a nge[1:0]
Gpio 8 Cl a mp
(to ADC)
C u rrent S ink
DAC
Cl a mp circ u it
RC u rrD a c
Gpio[ 8 ]
EnD a c
A2DCh a nnel1 [4 0] Com b in a tori a l
M as k
Addre ss
Recognized
A2DCh a nnel2 [4 0] Com b in a tori a l
M as k
Addre ss
Recognized
EnD a c S c a le
Gpio[ 8 ] Digit a l Driver
Obsolete Product(s) - Obsolete Product(s)
The circuit is enabled by setting to logic ‘1’ the EnDac bit in the CurrDacCtrl register then the desired sunk current value is chosen by changing the value of the DacValue[5:0] bits in the same register being DacValue[0] the least significant bit and DacValue[5] the most significant bit.
Doc ID 17713 Rev 1 85/139
Current DAC circuit L6460
The current DAC has three possible current ranges that can be selected using the
DacRange[1:0] bits in the CurrDacCtrl register. The DAC range selection table is shown in
.
Table 35.
Current DAC truth table
DacRange[1]
1
1
0
0
DacRange[0]
0
1
0
1
LSB typical current
I
LSB
typ
Disabled
10 µA
100 µA
1 mA
Full scale typical current I
FULL
typ
Disabled
0.63 mA
6.3 mA
63 mA
By changing LSB current value, all steps will change following this relation:
I step
(N) = N * I
LSB where N is the value of DacValue[5:0] bits.
Obsolete Product(s) - Obsolete Product(s)
86/139 Doc ID 17713 Rev 1
L6460 Operational amplifiers
L6460 contains two rail to rail output, high bandwidth internally compensated operational amplifiers supplied by V
GPIO_SPI
pin. The operative supply range is 3.3 V ± 4.5%
Each operational amplifier can have all pin accessible or, to save pins, can be internally configured as a buffer. They can also be used as comparators; to do that the user must disable internal compensation by writing a logic level “1” in the OpXCompMode bit in the
OpAmpXCtrl register.
in
are reported the block diagrams of the two operational amplifiers.
Figure 26.
Configurable 3.3 V operational amplifiers
Op1Ref[1:0]
GPIO[11]
Op1EnIntRef
Op1PlusRef
To A/D System
Op1CompMode
V
GPIO_SPI
OpAmp 1
+
-
EnOp1
Op1BufConf
Op1EnPlusPin
Op1EnMinusPin
GPIO[9]
GPIO[10]
Op2EnMinusPin EnOp2 Op2BufConf
GPIO[13]
GPIO[12]
Op2CompMode
Op2EnPlusPin
V
GPIO_SPI
Obsolete Product(s) - Obsolete Product(s)
Op2EnIntRef
Op2PlusRef
Op2Ref[1:0]
GPIO[14]
Note: Op1EnPlusRef and Op2EnPlusRef cannot be used to drive external pin so the user must be sure not to enable the path between one of these voltage references and the external pin.
Doc ID 17713 Rev 1 87/139
Operational amplifiers L6460
The operational amplifiers are capable to drive a capacitive load in buffer configuration up to a maximum of 100 pF; for higher capacitance it is necessary to add resistive loads to increase the OP output current, and/or to add a low resistor (10
Ω
) in series to the load capacitance.
To use the operational amplifiers as comparators the user must disable internal compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register.
Obsolete Product(s) - Obsolete Product(s)
88/139 Doc ID 17713 Rev 1
L6460
18 Low voltage power switches
Low voltage power switches
Low voltage power switches are analog switches designed to operate from a single +2.4 V to +3.6 V V
GPIO_SPI
supply. They are intended to provide and remove power supply to low voltage devices. When switched on, they connect the V
GPIO_SPI
pin to their output pin
(GPIO[6] for low voltage power switch 1 or GPIO[7] for low voltage power switch 2) thus powering the device connected to it. The turning on and off of each switch can be controlled through serial interface.
L6460 provides 2 low voltage power switches, each of them has current limitation to minimum 150mA to limit inrush current when charging a capacitive load. When the limit current has been reached, for more than a T filter
time, then a flag is activated; this flag is latched in the central logic and can be cleared by the firmware. Please note that, in case of capacitive load, the current limit is reached the first time the low power switch is turned on: therefore the user will find a limit flag that must be cleared.
The 2 low voltage power switches can be externally paralleled to obtain a single super low voltage power switch. Low voltage pass switches sink current needed for their functionality from pin V
GPIO_SPI
, they never inject current on this pin.
Figure 27.
Low power switch block diagram
V
GPIO_ S PI
EnLowV S w[x]
LowV S wIlim[x]
To S PI
S
LowV S wIlimLth[x]
R
C u rrent
Limit
S en s or
ClrLowVr S wLth
Re s et S t a te
GPIO[6]/GPIO[7]
Driver
GPIO[6] (LP S 1) or
GPIO[7] (LP S 2)
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 89/139
General purpose PWM
19 General purpose PWM
L6460
L6460 includes three general purpose PWM generators that can be redirected on GPIO pins (see
). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with a fixed period F
OSC
/512 and have a programmable duty cycle; the other one (GP_PWM) has a programmable base time clock and a programmable time for both high and low levels.
19.1 General purpose PWM generators 1 and 2 (AuxPwm1 and
AuxPwm2)
The Duty cycle of these PWM generators can be changed by writing the AuxPwmXCtrl bits
(where X can be 1 or 2) in the AuxPwm1Ctrl and AuxPwm2Ctrl registers. Their positive duty cycle will change according to the equation:
PWM_X_DUTY = AuxPwmXCtrl 9:0
]
/512
According to this equation a programmed “0” value will cause a 0% duty cycle (output always at logic level 0).
19.2 Programmable PWM generator (GpPwm)
GpPWM has a programmable base clock that can be changed by programming the
GpPwmBase[6:0] bits in the GpPwmBase register. The clock will change according to the equation:
PWM_BASE_PERIOD =
(
GpPwmBase 6:0
]
+ 1
) ×
Tosc
The high and low level duration (expressed in base clock periods), can be programmed writing the GpPwmHigh[7:0] and GpPwmLow[7:0] bits in the GpPwmCtrl register so they will change according to following equations:
High_level_Time = GpPwmHigh 7:0
] ×
PWM_BASE_PERIOD
Low_level_Time = GpPwmLow 7:0
] ×
PWM_BASE_PERIOD
The resulting period of the PWM will be:
GpPwmHigh 7:0
]
+
[ ] )
+ PWM_BASE_PERIOD Period =
(
Obsolete Product(s) - Obsolete Product(s) and the positive duty cycle will result:
DutyCycle =
High_level_Time + Low_level_Time
=
GpPwmHigh 7:0
]
GpPwmHigh 7:0
]
+
[ ]
A programmed value of 0 in GpPwmHigh[7:0] and GpPwmLow[7:0] bits will force the PWM generator output to be always at logic level “0”.
90/139 Doc ID 17713 Rev 1
L6460 Interrupt controller
L6460 contains one programmable interrupt controller that can be used to advice the firmware, through the serial interface, when a certain event happens inside the IC. The output of the interrupt circuit can be also redirected on a GPIO pin therefore the event can be signaled directly to the external circuits.
Figure 28.
Interrupt controller diagram
IntCtrlAutoDisab le
EnIntCtrlPulse
DisableMonitor Disable Pulse
Generation log i c
DisableSignals
Pulse
Generator
To Gpio
Monitored signals
Enable signals
EnIntCtrl
The
contains the events that can be monitored by the interrupt controller.
Table 36.
Interrupt controller event
Event Event description Notes
Mtr1Fault Bridge 1 fault (Ilimit event)
Mtr2Fault Bridge 2 fault (Ilimit event)
Mtr3Fault Bridge 3 fault (Ilimit event) Obsolete Product(s) - Obsolete Product(s)
Mtr4Fault Bridge 4 fault (Ilimit event) nAWAKE
SwRegCtrl Ilimit
VMainSW Ilimit
LowPowSw 1
LowPowSw 2
Warm nAWAKE pin low
Switching regulator controller Ilimit event.
Main switching regulator Ilimit event.
Low voltage power switch 1 Ilimit event.
Low voltage power switch 2 Ilimit event
Warming event
Doc ID 17713 Rev 1 91/139
Interrupt controller L6460
Table 36.
Interrupt controller event (continued)
Event Event description
WDWarn
WD
DigCmp
ADCDone1
ADCDone2
Vloop1Ilim
Watch dog warning event
Watch dog event
Digital comparator
ADC conversion done 1
ADC conversion done 2
AUX1 Ilimit event.
1.
This event is disabled if the related ADC channel is configured in continuous mode.
Notes
(1)
(1)
Any event detection can be enabled and disabled by setting at logic level 1 the relative enable bit in the interrupt controller configuration register (IntCrtlCfg).
The interrupt controller can be programmed to give a pulse when a monitored event happens or to continuously maintaining the output active until the interrupt condition is finished.
When programmed to signal the enabled events by giving pulses, the interrupt controller can be configured to disable the event that caused the interrupt request until the firmware reenables it writing the relative bit in the control register (IntCrtlCtrl) or to continue to monitor the event.
The GPIO output of this circuit can be programmed to be active high or active low.
Obsolete Product(s) - Obsolete Product(s)
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L6460 Digital comparator
L6460 includes one digital comparator that can be used to signal, through serial interface, that a channel converted by the ADC is greater, greater-equal, lesser, lesser equal, or equal than a fixed value set by serial interface or than the value converted by the other ADC channel.
This circuit can be used to monitor the temperature of the IC advising the firmware when it reaches a certain value decided by the firmware by setting one ADC channel to do continuous conversions of the temperature sensor.
The circuit operation can be enabled or disabled changing the EnDigCmp bit in the configuration register DigCmpCfg. By setting the DigCmpUpdate[1:0] bits in the configuration register, the comparator can be programmed to update its output in one of the following ways:
● DigCmpUpdate[1:0]=00
●
– Continuously (each clock).
DigCmpUpdate[1:0]=01
●
– Each time a conversion is performed on ADC channel 0.
DigCmpUpdate[1:0]=10
●
– Each time a conversion is performed on ADC channel 1.
DigCmpUpdate[1:0]=11
– ADC state machine driven.
When the last option is selected, the digital comparator will update its output in two different ways depending on the configuration of the ADC converter. If ADC converter is configured to do continuous conversions on both channels, the output of the comparator will be updated when the double conversion is completed. If ADC converter is not configured to do continuous conversions on both channels, the output of the comparator will be updated each time a conversion is completed.
The comparator output can be digitally filtered so that the programmed condition has to be found for three consecutive checks before to be signaled.
The
shows the block diagram of digital comparator.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 93/139
Digital comparator
Figure 29.
Digital comparator block diagram
L6460
DigCmpV a l u e[9:0]
A2DRe su lt0[ 8 :0]
A2DRe su lt1[ 8 :0]
DigCmp S elCh0[1]
DigCmp S elCh0[0]
DigCmp S elCh1[0]
ADC F S M
Upd a te
S ign a l
D a t a 0[9:0]
D a t a 1 [9:0]
COMPARATOR
DigCmpUpd a te[1:0]
Three check filter
CmpO u t
DigCmp S elCh1[1]
In
Table 37 is reported the comparison type truth table.
Table 37.
Comparison type truth table
EnDigCmp SelCmpType[1] SelCmpType[0]
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Comparison type
Disabled
Data0[9:0]
≤
1³1
÷
Data1[9:0]
Data0[9:0] = Data1[9:0]
Data0[9:0] > Data1[9:0]
Data0[9:0]
≤
= Data1[9:0]
Obsolete Product(s) - Obsolete Product(s)
Table 38.
DataX selection truth table
DigCmpSelChX[1] DigCmpSelChX[0] DataX[9:0]
0
1
1
X
0
1
DigCmpValue[9:0]
A2DResult1[8:0]
A2DResult1[8:0]
94/139 Doc ID 17713 Rev 1
L6460 GPIO pins
Some of the pins of L6460 are indicated as GPIO (General purpose I/O). These pins can be configured to be used in different ways depending on customer application. All GPIOs can be used as digital input/output pins with digital value settable/readable using serial interface or as analog input pins that can be converted using the A2D system. Some of the pins can be used for special purposes: i.e. two of them can be used to access to the pass switch function, other two are used as feedback pins for the auxiliary synchronous switching regulators.
All input Schmitt triggers and output circuitry used for start-up purposes are powered by the internally generated V
3v3
, while the digital output buffers are powered by V
GPIO_SPI
pin. To ensure independency between V
3v3
and V
GPIO_SPI
the GPIOs output drivers are open-drain driver or the high side MOS is in back-to-back configuration to avoid the presence of the body diode between output and supply.
All digital output signals can be inverted before being provided on the relative GPIO pins.
Here below is reported the table with GPIO functions.
Table 39.
GPIO functions description
Function
(1)
Pin
Name
Input Output
Analog
GPIO[1]
- ADC input
- Comp1 In-
- Vaux1 F.B.
GPIO[2]
- ADC input
- Comp2 In-
- Vaux2 F.B.
Digital
GPIO[0] - ADC input - SPI IN
- SPI IN
- SPI IN
- IN PWM
Analog Digital
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm2
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm2
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
- SPI OUT
Special
Notes
Start-up configuration pin
Open drain output
Open drain output
Open drain output
Start-up configuration pin
Open drain output
GPIO[4] - ADC input - SPI IN
GPIO[5] - ADC input - SPI IN
- SPI OUT
- Interrupt ctrl.
- AuxPwm1
- AuxPwm3
- SPI OUT
- Reg. loop 1
- Comp1 out
- AuxPwm3
Start-up configuration pin
Open drain output
Slave Control
Full driver BB powered by
V
3v3
Doc ID 17713 Rev 1 95/139
GPIO pins L6460
Table 39.
GPIO functions description (continued)
Function
(1)
Pin
Name
Input Output
Analog Digital Analog Digital
Special
Notes
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
- ADC input
- ADC input
- ADC input
- ADC input
- OpAmp1 in+
- ADC input
- OpAmp1 in-
GPIO[11] - ADC input
- SPI IN
- SPI IN
- SPI IN
- SPI IN
- ID 1
- IN PWM
- SPI IN
- ID 2
- IN PWM
- SPI IN
(2)
- IN PWM
- Low Pow Sw 1
- SPI OUT
- A2DGpo
- AuxPwm2
- Comp2 out
- Low Pow Sw 2
- CurrDAC
- SPI OUT
- AuxPwm1
- AuxPwm3
- Comp1 out
- SPI OUT
- AuxPwm1
- AuxPwm3
- Comp2 out
- OpAmp1 Out
- SPI OUT
- Interrupt contr.
- AuxPwm1
- Reg. loop 3
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
- SPI OUT
- A2DGpo
- AuxPwm1
- AuxPwm2
5 volt input tolerant
Full driver connected to
V
GPIO_SPI
Full driver connected to
V
GPIO_SPI
Open drain output
Full driver connected to
V
GPIO_SPI
Full driver connected to
V
GPIO_SPI
Full driver connected to
V
GPIO_SPI
GPIO[12]
- ADC input
- OpAmp2 in+
- SPI IN
- STEP_REQ
- SPI OUT
- Interrupt ctrl
- Comp2 out
- Reg. loop 2
Full driver BB
(can be powered by
V
3v3
with a metal change)
- ADC input
- OpAmp2 in-
GPIO[14] - ADC input
- SPI IN
- SPI IN - OpAmp2 Out
- SPI OUT
- AuxPwm1
- Reg. loop 3
- AuxPwm3
- SPI OUT
- Interrupt ctrl.
- AuxPwm2
- AuxPwm3
Full driver connected to
Full driver connected to
V
GPIO_SPI
1.
In this table are used the abbreviations of the following In Table 40 .
2.
GPIO[8] input Schmitt trigger is disabled by default (after a reset) to be able to read the digital value from this pin it needs to be enabled writing a logic ‘1’ in the EnGpio8DigIn in CurrDacCtrl register.
96/139 Doc ID 17713 Rev 1
L6460 GPIO pins
Table 40.
Abbreviations
Abbreviation Meaning
ADC input
SPI IN
SPI OUT
BB
Comp1 IN -
Comp2 IN -
Input to the ADC system.
Digital state of this pin is readable through SPI.
Digital state of this pin can be set through SPI.
Back to back high side driver.
This pin can be used as minus input for comparator 1.
Vaux1 FB
A2DGpo
Reg. Loop 3
This pin can be used as minus input for comparator 2.
This pin can be used as feedback input for AUX1 regulator obtained by using bridge 3.
This pin can be used to carry out the A2DGpo value related to the ADC conversion L6460 is doing.
This pin can be used as output of the regulation loop used by AUX3 regulator obtained by using bridge 4.
This pin can be used to request a stepper sequencer evolution step.
STEP_REQ
Interrupt Ctrl
Vaux2 FB
IN PWM
This pin can be used to carry out the interrupt controller circuit output.
This pin can be used as feedback pin by AUX2 regulator obtained by using bridge 3
This pin can be used to provide an external PWM to bridges.
Reg. Loop 1
This pin can be used as output of the regulation loop used by AUX1 regulator.
This pin can be used as output of the comparator 1.
Comp1 OUT
AuxPwm1 This pin can be used to carry out the PWM generated by AuxPwm1 circuit.
Low Volt. Pow. Sw. 1 This pin can be used as output of low voltage power switch 1.
Reg. Loop 2
Comp2 OUT
This pin can be used as output of the regulation loop used by AUX2 regulator.
This pin can be used as output of the comparator 2.
AuxPwm2 This pin can be used to carry out the PWM generated by AuxPwm2 circuit.
Low Volt. Pow. Sw. 2 This pin can be used as output of low voltage power switch 2.
Reg. Loop 3
This pin can be used as output of the regulation loop used by AUX3 regulator.
AuxPwm3
CurrDAC
This pin can be used to carry out the PWM generated by AuxPwm3 circuit.
Obsolete Product(s) - Obsolete Product(s)
AuxPwm4 This pin can be used to carry out the PWM generated by AuxPwm4 circuit.
OpAmp1 in+
OpAmp1 in-
OpAmp1 Out
OpAmp2 in+
OpAmp2 in-
This pin can be used as operational amplifier 1 non-inverting input.
This pin can be used as operational amplifier 1 inverting input.
This pin can be used as operational amplifier 1 output.
This pin can be used as operational amplifier 2 non-inverting input.
This pin can be used as operational amplifier 2 inverting input.
Doc ID 17713 Rev 1 97/139
GPIO pins L6460
Table 40.
Abbreviations (continued)
Abbreviation
OpAmp2 Out
ID 1
ID 2
Slave Control
Meaning
This pin can be used as operational amplifier 2 output.
This pin is used to determine the SPI ID1 bit value.
This pin is used to determine the SPI ID2 bit value.
This pin is used as slave control when the IC is configured as master.
Hereafter are reported the detailed specifications for each GPIO.
To enable the functionality of the GPIO as output pin, the relative GpioOutEnable[14:0] bit must be enabled in GpioOutEnable register.
Each GPIO could be configured by setting the appropriate GpioXMode[2:0] in the GpioCtrlX register.
Obsolete Product(s) - Obsolete Product(s)
98/139 Doc ID 17713 Rev 1
L6460 GPIO pins
22.1 GPIO[0]
The GPIO[0] truth table is (for the abbreviation list please refer to
Table 41.
GPIO[0] truth table
GPIO[0] SPI BITS
State at
StartUp GpioOut
Enable [0]
Mode[2] Mode[1] Mode[0]
Function Note
1
0
0
0
0
0
0
0
0
0
X
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
Detection of StartUp config
See
HiZ (SPI_IN)
SPI OUT
InterruptCtrl
AuxPwm1
AuxPwm2
(1)
(1)
(1)
(1)
(1)
SPI OUT inverted
InterruptCtrl inverted
AuxPwm1 inverted
AuxPwm2 inverted
(1)
(1)
(1)
1.
In all configurations in which GPIO[0] is enabled as output: a) the GPIO[0] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[0] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[0] pin is an open drain output.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 99/139
GPIO pins
Figure 30.
GPIO[0] block diagram
V
3 v 3
To S eri a l Interf a ce
To ADC
To Control Logic
From S eri a l
Interf a ce
En S t a rtUpDtc
From Power Up
F S M
V
3 v 3
Logic Decode
V
3 v 3
S t a rtu p pin S t a te
Detect circ u it
V
3 v 3
GPIO[0] Driver
GPIO[0]
L6460
Obsolete Product(s) - Obsolete Product(s)
100/139 Doc ID 17713 Rev 1
L6460 GPIO pins
22.2 GPIO[1]
The GPIO[1] truth table is (for the abbreviation list please refer to
Table 42.
GPIO[1] truth table
GPIO[1] SPI BITS
AUX1Enable or
AUX1System
GpioOut
Enable [1]
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
1
0
0
0
0
0
X
0
0
1
1
1
1
1
1
1
1
X
0
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
AUX1 FB
HiZ (SPI_IN)
Comp1 IN -
SPI OUT
AuxPwm1
AuxPwm2
InterruptCtrl
SPI OUT inverted
AuxPwm1 inverted
AuxPwm2inverted
IntCtrlinverted
(1)
(2)
(2)
(2)
(2)
(2)
(2)
1.
AUX1Enable or AUX1System bit =1 represent the case in which AUX1 is used as a system or not system regulator.
2.
In all configurations in which GPIO[1] is enabled as output: a) the GPIO[1] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[1] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[1] pin is an open drain output.
(2)
(2)
(2)
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 101/139
GPIO pins
Figure 31.
GPIO[1] block diagram
To ADC
To Serial Interface
To AUX1 Feedback comparator
From Serial
Interface
V
3v3
Logic Decode
V
3v3
V
3v3
Gpio[1] Driver
GPIO[1]
L6460
Obsolete Product(s) - Obsolete Product(s)
102/139 Doc ID 17713 Rev 1
L6460 GPIO pins
22.3 GPIO[2]
The GPIO[2] truth table is (for the abbreviation list please refer to
Table 43.
GPIO[2] truth table
GPIO[1] SPI BITS
AUX2Enable or
AUX2System
GpioOut
Enable [1]
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
0
1
0
0
0
0
X
0
0
1
1
1
1
1
1
1
1
X
0
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
AUX2 FB
HiZ (SPI_IN)
Comp1 IN -
SPI OUT
AuxPwm2
AuxPwm3
InterruptCtrl
SPI OUT inverted
AuxPwm2 inverted
AuxPwm3 inverted
IntCtrlinverted
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1.
AUX2Enable or AUX2System bit =1 represent the case in which AUX1 is used as a System or Not System regulator.
2.
In all configurations in which GPIO[2] is enabled as output: a) the GPIO[2] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[2] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[2] output is directly connected to ExtPWM3 input for Bridge 3 or 4 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM3 is selected for bridge 3 or 4; d) the GPIO[2] pin is an open drain output.
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GPIO pins
Figure 32.
GPIO[2] block diagram
To ExtPWM3
To Serial Interface
To ADC
To AUX2 Feedback comparator
V
3v3
From Serial
Interface
V
3v3
Logic Decode
V
3v3
Gpio[2] Driver
GPIO[2]
L6460
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L6460 GPIO pins
22.4 GPIO[3]
The GPIO[3] truth table is (for the abbreviation list please refer to
Table 44.
GPIO[3] truth table
GPIO[3] SPI BITS
State at
StartUp GpioOut
Enable [3]
Mode[2] Mode[1] Mode[0]
Function Note
1
0
0
0
0
0
0
0
0
0
X
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
Detection of StartUp config
See
HiZ (SPI_IN)
SPI OUT
AuxPwm1
AuxPwm2
(1)
(1)
(1)
(1)
AuxPwm2
SPI OUT inverted
AuxPwm1 inverted
AuxPwm2 inverted
AuxPwm3 inverted
(1)
(1)
(1)
(1)
1.
In all configurations in which GPIO[3] is enabled as output: a) the GPIO[3] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[3] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[3] pin is an open drain output.
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GPIO pins
Figure 33.
GPIO[3] block diagram
To S eri a l Interf a ce
V
3 v 3
To ADC
To Control Logic
From S eri a l
Interf a ce
En S t a rtUpDtc
From Power Up
F S M
V
3 v 3
Logic Decode
V
3 v 3
S t a rtu p pin S t a te
Detect circ u it
V
3 v 3
Gpio[ 3 ] Driver
GPIO[ 3 ]
L6460
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L6460 GPIO pins
22.5 GPIO[4]
The GPIO[4] truth table is (for the abbreviation list please refer to
Table 45.
GPIO[4] truth table
GPIO[4] SPI BITS
State at
StartUp GpioOut
Enable [4]
Mode[2] Mode[1] Mode[0]
Function Note
1
0
0
0
0
0
0
0
0
0
X
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
Detection of StartUp config
See
HiZ (SPI_IN)
SPI OUT
Interrupt Ctrl
AuxPwm1
(1)
(1)
(1)
(1)
AuxPwm3
SPI OUT inverted
Interrupt Ctrl
AuxPwm1 inverted
AuxPwm3 inverted
(1)
(1)
(1)
(1)
1.
In all configurations in which GPIO[4] is enabled as output: a) the GPIO[4] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[4] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[4] pin is an open drain output.
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GPIO pins
Figure 34.
GPIO[4] block diagram
To Serial Interface
V
3v3
To ADC
To Control Logic
From Serial
Interface
EnStartUpDtc
FSM
V
3v3
Logic Decode
V
3v3
Start-up pin State
Detect circuit
V
3v3
Gpio[4] Driver
GPIO[4]
L6460
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L6460 GPIO pins
22.6 GPIO[5]
The GPIO[5] truth table is (for the abbreviation list please refer to
Table 46.
GPIO[5] truth table
Master
(1)
AUX1 system and
Vloop1 external
(2)
GpioOut enable[5]
GPIO[5] SPI BITS
Mode[2] Mode[1] Mode[0]
Function Note
1
0
X
1
X
X
X
X
X
X
X
X
Slave control
Reg Loop1 OUT
(3)
0
0
0
0
0
1
X
0
X
0
X
0
HiZ (SPI_IN)
SPI OUT
(3)
0
0
0
0
1
1
0
0
0
1
1
0
Comp1OUT
Reg Loop1 OUT
(3)
(3)
0 0 1 0 1 1 AuxPwm3
(3)
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
SPI OUT inverted
Comp1OUT inverted
Reg Loop1 OUT inverted
AuxPwm3 inverted
(3)
(3)
(3)
0 0 1 1 1 1
(3)
1.
Master bit is at logic level “1” when L6460
is used as a master device (see Chapter 8 )
2.
This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized
(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in
CoreConfigReg register.
3.
In all configurations in which GPIO[5] is enabled as output: a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[5] pin is a rail to rail, back to back output supplied by V
3v3
.
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GPIO pins
Figure 35.
GPIO[5] block diagram
To internal Logic & SPI V
3v3
To ADC
From Control logic
V
3v3
Logic Decode
V
3V3
Back to Back
Driver
GPIO[5]
L6460
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L6460 GPIO pins
22.7 GPIO[6]
The GPIO[6] truth table is (for the abbreviation list please refer to
Table 47.
GPIO[6] truth table
GPIO[6] SPI BITS
StdByMode
AEnLow
VSw[1]
GpioOut enable[6]
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
0
0
0
1
0
X
1
0
0
0
0
0
0
0
0
X
X
0
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
X
X
X
0
0
1
1
0
0
1
X
X
X
0
1
0
1
0
1
1
Low Volt. Pow. Sw. 1
Low Volt. Pow. Sw. 1
HiZ (SPI_IN)
SPI OUT
A2DGpo
AuxPwm2
Comp2OUT
A2DGpo inverted
AuxGpPwm2 inverted
Comp2OUT inverted
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1.
When EnLowVSw[1]= ‘1’ the GpioOutEnable[6] bit is forced to 0.
2.
In all configurations in which GPIO[6] is enabled as output: a) the GPIO[6] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[6] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[6] pin is a rail to rail output supplied by V
GPIO_SPI.
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GPIO pins
Figure 36.
GPIO[6] block diagram
V
GPIO_SPI
Power Switch 1
To internal
Logic & SPI
V
3v3
To ADC
From Serial
Interface
Stand By mode
V
3v3
Logic Decode
V
3v3
Gpio[6] Driver
GPIO[6]
L6460
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L6460 GPIO pins
22.8 GPIO[7]
The GPIO[7] truth table is (for the abbreviation list please refer to
Table 48.
GPIO[7] truth table
GPIO[7] SPI BITS
EnLowVSw[2]
GpioOut enable[7]
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
0
0
1
0
X
0
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
X
X
0
0
1
1
0
0
1
X
X
0
1
0
1
0
1
1
Low Volt. Pow. Sw. 2
HiZ (SPI_IN)
SPI OUT
AuxPwm1
AuxPwm3
Comp1OUT
AuxPwm1 inverted
AuxPwm3 inverted
Comp1OUT inverted
(1)
(2)
(2)
(2)
(2)
1.
When EnLowVSw[2] = ‘1’ the GpioOutEnable[7] bit is forced to 0.
2.
In all configurations in which GPIO[7] is enabled as output: a) the GPIO[7] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[7] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[7] pin is a rail to rail output supplied by V
GPIO_SPI.
(2)
(2)
(2)
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GPIO pins
Figure 37.
GPIO[7] block diagram
V
GPIO_SPI
Power Switch 2
To internal
Logic & SPI
V
3v3
To ADC
From Serial
Interface
V
3v3
Logic Decode
V
GPIO_SPI
GPIO[7]
L6460
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L6460 GPIO pins
22.9 GPIO[8]
The GPIO[8] truth table is (for the abbreviation list please refer to
Table 49.
GPIO[8] truth table
GPIO[8] SPI bits
EnDac
(1)
Function
(2)
Note
GpioOut enable[8]
Mode[2] Mode[1] Mode[0]
1
0
0
0
0
0
0
0
X
0
1
1
1
1
1
1
X
X
0
0
0
0
1
1
X
X
0
0
1
1
0
0
X
X
0
1
0
1
0
1
CurrDAC
HiZ (SPI_IN)
SPI OUT
AuxPwm1
AuxPwm3
Comp2OUT
AuxPwm1 inverted
AuxPwm3 inverted
Comp2OUT inverted
(3)
(4)
(4)
(4)
(4)
0 1 1 1 1
(4)
1.
The EnDAC bit in the CurrDacCtrl register enables the Current DAC (see
)
2.
This pin is 5 volt input tolerant.
3.
When EnDAC = ‘1’ the GpioOutEnable[8] bit is forced to 0. The current DAC circuit is directly connected to
GPIO[8] pin so as soon as it is enabled it will sink current from pin.
4.
The GPIO[8] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function). To avoid affecting the precision of CurrDAC when this is used to sink very low currents, it is necessary to enable the digital input functionality of GPIO[8]. Therefore to read their values through SPI interface (SPI_IN function), it is necessary to enable the EnGpio8DigIn bit in the CurrDacCtrl register.
(4)
(4)
(4)
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GPIO pins
Figure 38.
GPIO[8] block diagram
V
3v3
To internal Logic & SPI
EnGpio8DigIn
To ADC
V
3v3
From Serial
Interface
Logic Decode
V
3v3
From Serial
Interface
Gpio[8] Driver
Current Sink
Circuit
L6460
GPIO[8]
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L6460 GPIO pins
22.10 GPIO[9]
The GPIO[9] truth table is (for the abbreviation list please refer to
Table 50.
GPIO[9] truth table
GPIO[9] SPI bits
Op1EnPlusPin
(1)
GpioOut enable[9]
Mode[2] Mode[1] Mode[0]
Function
(2)
Note
0
0
0
0
0
0
0
1
0
X
0
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
X
X
0
0
1
1
0
0
1
X
X
0
1
0
1
0
1
1
OpAmp1 in+
HiZ (SPI_IN)
SPI OUT
Interrupt Ctrl
AuxPwm2
Reg Loop 3
Interrupt Ctrl inverted
AuxPwm2 inverted
Reg Loop 3 inverted
(3)
(4)
(4)
(4)
(4)
1.
The Op1EnPlusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to
GPIO[9] pin.
2.
The GPIO[9] pin is used by the system when firmware requires the ID read action (
)
3.
When Op1EnPlusPin = ‘1’ the GpioOutEnable[9] bit is forced to 0.
4.
In all configurations in which GPIO[9] is enabled as output: a)the GPIO[9] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[9] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c)please note that GPIO[9] output is directly connected to ExtPWM1 input for Bridge 1 or 2 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM1 is selected for bridge 1 or 2; d)the GPIO[9] pin is a rail to rail output supplied by V
GPIO_SPI.
(4)
(4)
(4)
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GPIO pins
Figure 39.
GPIO[9] block diagram
ID1
SampleID
To ADC
To internal Logic & SPI
V
3v3
Pin State Sample
Circuit
V
GPIO_SPI
V
3v3
From SPI Logic Decode
Gpio[9] Driver
To OpAmp1 In+
L6460
GPIO[9]
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L6460 GPIO pins
22.11 GPIO[10]
The GPIO[10] truth table is (for the abbreviation list please refer to
).
Table 51.
GPIO[10] truth table
GPIO[10] SPI bits
Op1EnPlusPin
(1)
GpioOut enable[10]
Mode[2] Mode[1] Mode[0]
Function
(2)
Note
0
0
0
0
0
0
0
1
0
X
0
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
0
X
X
0
0
1
1
0
0
0
X
X
0
1
0
1
0
1
0
OpAmp1 in-
HiZ (SPI_IN)
SPI OUT
Interrupt Ctrl
AuxPwm2
AuxPwm3
Interrupt Ctrl inverted
AuxPwm2 inverted
AuxPwm3 inverted
(3)
(4)
(4)
(4)
(4)
1.
The Op1EnMinusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to
GPIO[10] pin.
2.
The GPIO[10] pin is used by the system when firmware requires the ID read action (
3.
When Op1EnPlusPin = ‘1’ the GpioOutEnable[10] bit is forced to 0.
4.
In all configurations in which GPIO[10] is enabled as output: a) the GPIO[10] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[10] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[10] output is directly connected to ExtPWM2 input for bridge 1 or 2 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM2 is selected for bridge 1 or 2; d) the GPIO[10] pin is a rail to rail output supplied by V
GPIO_SPI.
(4)
(4)
(4)
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GPIO pins
Figure 40.
GPIO[10] block diagram
ID2
SampleID
To ADC
To internal Logic & SPI
V
3v3
Pin State Sample
Circuit
V
GPIO_SPI
V
3v3
From SPI Logic Decode
Gpio[10] Driver
To OpAmp1 In-
L6460
GPIO[10]
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L6460 GPIO pins
22.12 GPIO[11]
The GPIO[11] truth table is (for the abbreviation list please refer to
).
Table 52.
GPIO[11] truth table
GPIO[11] SPI bits
EnOpl
(1)
GpioOut enable[11]
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
0
0
0
1
0
X
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
OpAmp1 Out
HiZ (SPI_IN)
SPI OUT
A2DGpo
AuxPwm1
AuxPwm2
SPI OUT inverted
A2DGpo inverted
AuxPwm1 inverted
AuxPwm2 inverted
(2)
(3)
(3)
(3)
(3)
(3)
1.
The EnOp1 bit in the OpAmp1Ctrl register enables the operational amplifier 1.
2.
When EnOp1 = ‘1’ the GpioOutEnable[11] bit is forced to 0.
3.
In all configurations in which GPIO[11] is enabled as output: a) the GPIO[11] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[11] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[11] output is directly connected to ExtPWM4 input for bridge 3 or 4 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM4 is selected for bridge 3 or 4; d) the GPIO[11] pin is a rail to rail output supplied by V
GPIO_SPI.
(3)
(3)
(3)
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GPIO pins
Figure 41.
GPIO[11] block diagram
To internal Logic & SPI
V
3v3
To ADC
From Central
Logic
V
3v3
Logic Decode
V
GPIO_SPI
OpAmp 1
L6460
GPIO[11]
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L6460 GPIO pins
22.13 GPIO[12]
The GPIO[12] truth table is (for the abbreviation list please refer to
.
Table 53.
GPIO[12] truth table
AUX2enable or
AUX2syste m
(1)
Op2En
PlusPin
GpioOut enable[12]
GPIO[12] SPI bits
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
0
0
1
0
0
X
1
0
0
0
0
0
0
0
0
X
X
0
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
X
X
X
0
0
1
1
0
0
1
X
X
X
0
1
0
1
0
1
1
RegLoop2
OpAmp2 in+
HiZ (SPI_IN)
SPI OUT
Interrupt Ctrl
Comp2OUT
RegLoop2
Interrupt Ctrl inverted
Comp2OUT inverted
RegLoop2 inverted
(2)
(3)
(3)
(3)
(3)
1.
AUX2Enable or AUX2System bit =1 represent the case in which AUX2 is used as a regulator (system or not system).
2.
When Op2EnPlusPin = ‘1’ the GpioOutEnable[11] bit is forced to 0.
3.
In all configurations in which GPIO[12] is enabled as output: a) the GPIO[12] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[12] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[12] output is directly connected to StepCmd input for stepper driver and therefore particular care must be taken in order to avoid wrong PWM signals when StepCmd is selected for stepper driver (STEP_REQUEST function) d) the GPIO[12] pin is a rail to rail, back to back output supplied by V
GPIO_SPI.
(3)
(3)
(3)
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GPIO pins
Figure 42.
GPIO[12] block diagram
To internal Logic & SPI
V
3v3
To ADC
V
3v3
From SPI Logic Decode
V
GPIO_SPI
To OpAmp2 In+
Back to Back
Driver
L6460
GPIO[12]
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L6460 GPIO pins
22.14 GPIO[13]
The GPIO[13] truth table is (for the abbreviation list please refer to
).
Table 54.
GPIO[13] truth table
GPIO[13] SPI BITS
Op2En mimusPin
(1) GpioOut enable[13]
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
0
0
1
0
X
0
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
X
X
0
0
1
1
0
0
1
X
X
0
1
0
1
0
1
1
OpAmp2 in-
HiZ (SPI_IN)
SPI OUT
AuxPwm1
Reg Loop 3
AuxPwm3
AuxPwm1 inverted
Reg Loop 3 inverted
AuxPwm3 inverted
(2)
(3)
(3)
(3)
(3)
1.
The Op2EnMinusPin bit in the OpAmp2Ctrl register enables the connection of the positive input of Op1 to
GPIO[13] pin.
2.
When Op2EnMinusPin = ‘1’ the GpioOutEnable[13] bit is forced to 0.
3.
In all configurations in which GPIO[9] is enabled as output: a) the GPIO[13] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[13] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[13] pin is a rail to rail output supplied by V
GPIO_SPI.
(3)
(3)
(3)
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 125/139
GPIO pins
Figure 43.
GPIO[13] block diagram
To internal Logic & SPI
V
3v3
To ADC
V
3v3
From SPI Logic Decode
V
GPIO_SP
Gpio[13] Driver
To OpAmp2 In-
L6460
GPIO[13]
Obsolete Product(s) - Obsolete Product(s)
126/139 Doc ID 17713 Rev 1
L6460 GPIO pins
22.15 GPIO[14]
The GPIO[14] truth table is (for the abbreviation list please refer to
).
Table 55.
GPIO[14] truth table
GPIO[14] SPI bits
EnOp2
(1)
GpioOut enable[14]
Mode[2] Mode[1] Mode[0]
Function Note
0
0
0
0
0
0
0
0
1
0
X
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
OpAmp2 Out
HiZ (SPI_IN)
SPI OUT
Interrupt Ctrl
AuxPwm2
AuxPwm3
SPI OUT inverted
Interrupt Ctrl inverted
AuxPwm2 inverted
AuxPwm3 inverted
(2)
(3)
(3)
(3)
(3)
(3)
1.
The EnOp2 bit in the OpAmp2Ctrl register enables the operational amplifier 2.
2.
When EnOp2 = ‘1’ the GpioOutEnable[14] bit is forced to 0.
3.
In all configurations in which GPIO[14] is enabled as output: a) the GPIO[14] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[14] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[14] pin is a rail to rail output supplied by V
GPIO_SPI.
(3)
(3)
(3)
Obsolete Product(s) - Obsolete Product(s)
Doc ID 17713 Rev 1 127/139
GPIO pins
Figure 44.
GPIO[14] block diagram
To internal Logic & SPI
V
3v3
To ADC
From Central
Logic
V
3v3
Logic Decode
V
GPIO_SP
Gpio[14] Driver
OpAmp 2
L6460
GPIO[14]
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128/139 Doc ID 17713 Rev 1
L6460 Serial interface
L6460 can communicate with an external microprocessor by using an integrated slave SPI
(serial protocol interface). Through this interface almost all L6460 functionalities can be controlled and all the ICs can be seen as a register map made by 128 register of 16-bit each.
The SPI is a simple industry standard communications interface commonly used in embedded systems and it has the following four I/O pins:
– MISO (master input slave output)
– MOSI (master output slave input)
– SCLK (serial clock [controlled by the master])
– nSS (slave select active low [controlled by the master])
The “MISO” (master in, slave out) signal carries synchronous data from the slave to the master device. The MOSI (master out, slave in) signal carries synchronous data from the master to the slave device. The SCLK signal is driven by the master, synchronizing all data transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master output pin. Slave devices do not respond to transactions unless their nSS input signal is driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for each slave device.
L6460 will maintain its MISO pin in high impedance until it does not recognize its address in serial frame.
A read transaction (see
) is always started by the master device that lowers the nSS pin. The other bits are then sent on the MOSI pin with this order:
1.
7-bit representing the address of the register that must be read (MSB first [A
6
…A
0
]);
2. 2-bit that must be “10” for a read transaction;
3. 2-bit representing L6460 IC address;
4. 1-bit reserved for future use that must be set at “0”.
At this point the data stored in the register at the selected address will be shifted out on the
MISO pin.
The read operation is terminated by raising the signal on nSS pin.
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Serial interface
Figure 45.
SPI read transaction nSS
S CLK
MO S I
MI S O
A6
Register
Address field
A0
Control
Field
IC address
High Impedance
D15
Data Field
D0
L6460
A write transaction (see
) is always started by the master lowering the signal on nSS pin. The other bits are then sent on the MOSI pin with this order:
1.
7-bit representing the address of the register that must be written (MSB first [A6…A0]);
2. 2-bit that must be “01” for a read transaction;
3. 2-bit representing L6460 IC address;
4. 1-bit reserved for future use that must be set at “0”.
The data to be written (MSB first D15…D0) are then read from MOSI pin. The length of data field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. Data is latched on rising edge of the nSS line.
Figure 46.
SPI write transaction n SS
S CLK
Regi s ter
Addre ss field
Control
Field
IC a ddre s
D a t a Field
A6 A0 D15 D0
MO S I
MI S O High Imped a nce Obsolete Product(s) - Obsolete Product(s)
The SPI input and output timing definitions are shown in the
130/139 Doc ID 17713 Rev 1
L6460
Figure 47.
SPI input timing diagram
T n ss s et u p n SS
SCLK
MOSI
T mo s i s et u p
T mo s i hold
Figure 48.
SPI output timing diagram
T n ss s et u p n SS
SCLK
MOSI
MISO
T mi s o v a lid
Serial interface
T s clk period
T n ss hold
T n ss min
T s clk hig
T s clk low
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
T s clk ri s e
T s clk f a ll
T s clk period
T s clk high
T s clk low
T n ss hold
T n ss min
V
V
IH
IL
V
IH
V
IL
T s clk ri s e
T s clk f a ll
T mi s o di sab le
V
OH
V
OL
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Doc ID 17713 Rev 1 131/139
Registers list L6460
Many of the L6460 functionalities are controlled or can be supervised by accessing to the relative register through serial interface. All these registers can be seen from the user
(microcontroller) point of view as a register table. Each register is one word wide (16-bit) and can be read using a 7-bit address
Table 56.
Register address map
Address[6:0]
(binary)
Name Comment
Address[6:0]
(binary)
Name Comment
000_0000
000_0001
000_0010
000_0011
000_0100
000_0101
000_0110
000_0111
000_1000
000_1001
000_1010
000_1011
000_1100
000_1101
000_1110
000_1111
001_0000
001_0001
001_0010
DevName
CoreConfigReg
ICTemp
ICStatus
EnTestRegs
SampleID
WatchDogCfg
WatchDogStatus
SoftResReg
Read only 100_0000
100_0001
100_0010
100_0011
100_0100
100_0101
100_0110
100_0111
100_1000
100_1001
100_1010
100_1011
HibernateStatus
HibernateCmd
100_1100
100_1101
100_1110
Mtr1_2PwrCtrl
MainVSwCfg
100_1111
101_0000
101_0001
MainlinCfg 101_0010
AuxPwm1Ctrl
AuxPwm2Ctrl
GpPwm3Base
GpPwm3Ctrl
IntCtrlCfg
IntCtrlCtrl
DigCmpCfg
DigCmpValue
A2DControl
A2DConfig1
A2DResult1
001_0011 101_0011 A2DConfig2
001_0100
001_0101
SwCtrCfg 101_0100
101_0101
A2DResult2 Obsolete Product(s) - Obsolete Product(s)
001_0110 101_0110
001_0111 101_0111
StdByMode 001_1000
001_1001
001_1010
001_1011
101_1000
101_1001
101_1010
101_1011
GpioOutEnable
GpioCtrl1
GpioCtrl2
GpioCtrl3
132/139 Doc ID 17713 Rev 1
L6460 Registers list
Table 56.
Register address map (continued)
Address[6:0]
(binary)
Name Comment
Address[6:0]
(binary)
Name Comment
Mtrs1_2Cfg
Mtr1Cfg
Mtr1Ctrl
Mtr1Limit
Mtr2Cfg
Mtr2Ctrl
Mtr2Limit
Mtrs3_4Cfg
Mtr3Cfg
Mtr3Ctrl
Mtr3ILimit
Mtr4Cfg
Mtr4Ctrl
Mtr4ILimit
GpioPadVal
GpioOutVal
LowVSwitchCtrl
OpAmpCtrl1
OpAmpCtrl2
Read only
010_1010
010_1011
010_1100
010_1101
010_1110
010_1111
011_0000
011_0001
011_0010
011_0011
011_0100
011_0101
001_1100
001_1101
001_1110
001_1111
010_0000
010_0001
010_0010
010_0011
010_0100
010_0101
010_0110
010_0111
010_1000
010_1001
StpCfg1
StpCfg2
StpCtrl
StpCmd
StpTest
Aux1SwCfg
110_1010
110_1011
110_1100
110_1101
110_1110
110_1111
111_0000
111_0001
111_0010
111_0011
111_0100
111_0101
101_1100
101_1101
101_1110
101_1111
110_0000
110_0001
110_0010
110_0011
110_0100
110_0101
110_0110
110_0111
110_1000
110_1001
011_0110
011_0111
Aux2SwCfg
Aux3SwCfg1
111_0110
111_0111
011_1000 Aux3SwCfg2 111_1000
011_1001
Power Mode
Control
111_1001
011_1010
011_1011
011_1100
111_1010
111_1011
111_1100 CurrDacCtrl
REV_MFCT
RESERVED
Doc ID 17713 Rev 1 133/139
Registers list
Table 56.
Register address map (continued)
Address[6:0]
(binary)
Name Comment
Address[6:0]
(binary)
011_1101
011_1110
011_1111
111_1101
111_1110
111_1111
Name
RESERVED
RESERVED
RESERVED
L6460
Comment
Obsolete Product(s) - Obsolete Product(s)
134/139 Doc ID 17713 Rev 1
L6460 Schematic examples
Figure 49.
Application with 2 DC motors, 1 stepper motor and 3 power supplies
3 2
Gpio3
Gpio4
Gpio1
Gpio2 nSS
Gpio0
8
9
10
11
12
13
14
15
16
5
6
7
1
2
3
4
70
71
72
73
DC1_plus
VSWDRV_sns
VSWDRV_FB
Gpio4
Gpio3
DC1_minus
DC1_minus
GND1
GND2
DC2_minus
DC2_minus
Gpio2
Gpio1
Gpio0 nSS
DC2_plus
TAB
TAB
TAB
TAB
DC3_sense
Gpio5
Gpio9
Gpio10
Gpio11
N.C.
DC3_minus
DC3_sense
DC4_sense
DC4_minus
N.C.
Gpio14
Gpio13
Gpio12 nAWAKE
DC4_sense
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Gpio13
Gpio14
Gpio12
Gpio9
Gpio5
Gpio10
Gpio11
3 2
Obsolete Product(s) - Obsolete Product(s)
3 2
Doc ID 17713 Rev 1 135/139
Schematic examples L6460
Figure 50.
Application with 2 DC motors, a battery charger and 5 power supplies
3 2
3 2
8 4
Gpio4
Gpio3
Gpio2
Gpio1
Gpio0 nSS
9
10
6
7
8
1
2
3
4
5
11
12
13
14
15
16
70
71
72
73
DC1_plus
VSWDRV_sns
VSWDRV_FB
Gpio4
Gpio3
DC1_minus
DC1_minus
GND1
GND2
DC2_minus
DC2_minus
Gpio2
Gpio1
Gpio0 nSS
DC2_plus
TAB
TAB
TAB
TAB
DC3_sense
Gpio5
Gpio9
Gpio10
Gpio11
N.C.
DC3_minus
DC3_sense
DC4_sense
DC4_minus
N.C.
Gpio14
Gpio13
Gpio12 nAWAKE
DC4_sense
44
43
42
41
40
48
47
46
45
39
38
37
36
35
34
33
Gpio5
Gpio9
Gpio10
Gpio11
Gpio14
Gpio13
Gpio12
3 2
8 4
Obsolete Product(s) - Obsolete Product(s)
3 2 2 3
4
2 3
136/139 Doc ID 17713 Rev 1
L6460
26 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 51.
TQFP64 mechanical data an package dimensions
E2
E3 e
D2
D3
E
E1
L
L1 k ccc c
D
D1
A
A1
A2 b
DIM.
mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.05
0.95
0.17
1.00
0.22
1.20
0.15
0.002
0.0472
0.006
1.05
0.0374 0.0393 0.0413
0.27
0.0066 0.0086 0.0086
0.09
0.20
0.0035
0.0078
11.80
12.00
12.20
0.464
0.472
0.480
9.80
10.00
10.20
0.386
0.394
0.401
2.00
0.787
7.50
0.295
11.80
12.00
12.20
0.464
0.472
0.480
9.80
10.00
10.20
0.386
0.394
0.401
2.00
0.787
7.50
0.50
0.295
0.0197
0.45
0˚
0.60
1.00
3.5˚
0.75
0.0177 0.0236 0.0295
0.0393
7˚
0.080
0˚ 3.5˚ 7˚
0.0031
OUTLINE AND
MECHANICAL DATA
TQFP64 (10x10x1.0mm)
Exposed Pad Down
Obsolete Product(s) - Obsolete Product(s)
7278840 B
137/139 Doc ID 17713 Rev 1
Revision history
Table 57.
Document revision history
Date Revision
02-Jul-2010 1 Initial release.
Changes
L6460
Obsolete Product(s) - Obsolete Product(s)
138/139 Doc ID 17713 Rev 1
L6460
Please Read Carefully:
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Information in this document supersedes and replaces all information previously supplied.
Obsolete Product(s) - Obsolete Product(s)
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2010 STMicroelectronics - All rights reserved
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Doc ID 17713 Rev 1 139/139
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