STMicroelectronics SPEAr600 Datasheet
إعلان
إعلان
SPEAr600
Embedded MPU with dual ARM926 core, flexible memory support, powerful connectivity features and programmable LCD interface
Datasheet
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production data
Features
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Dual ARM926EJ-S core up to 333 MHz:
– Each with 16 Kbytes instruction cache + 16
Kbytes data cache
High performance 8-channel DMA
Dynamic power saving features
Up to 733 DMIPS
Memory:
– External DRAM interface: 8/16-bit DDR1-
333 / DDR2 - 666
– 32 Kbytes BootROM / 8 Kbytes internal
SRAM
– Flexible static memory controller (FSMC) supporting parallel NAND Flash memory interface, ONFI 1.0 support, internal 1-bit
ECC or external 4-bit ECC
– Serial NOR Flash Memory interface
Connectivity:
– 2 x USB 2.0 Host
– USB 2.0 Device
– Giga Ethernet (GMII port)
– I
2
C and fast IrDA interfaces
– 3 x SSP Synchronous serial peripheral
(SPI, Microwire or TI protocol) ports
– 2 x UART interfaces
Peripherals supported:
– TFT/STN LCD controller (resolution up to
1024 x 768 and colors up to 24 bpp)
– Touchscreen support
Miscellaneous functions
– Integrated real-time clock, watchdog, and system controller
– 8-channel 10-bit ADC, 1 Msps
– JPEG codec accelerator
– 10 GPIO bidirectional signals with interrupt capability
– 10 independent 16-bit timers with programmable prescaler
32-bit width External local bus (EXPI interface).
PBGA420 (2 3 x 2 3 x 2.06 mm)
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3 x I
2
S interfaces for audio features:
– One stereo input and two stereo outputs
(audio 3.1 configuration capable)
Customizable logic with 600 Kgate standard cell array
Software:
– System compliant with all operating systems (including Linux)
Applications
■ The SPEAr
®
embedded MPU family targets networked devices used for communication, display and control. This includes diverse consumer, business, industrial and life science applications such as:
– IP phones, thin client computers, printers, programmable logic controllers, PC docking stations,
– Medical lab/diagnostics equipment, wireless access devices, home appliances, residential control and security systems, digital picture frames, and bar-code scanners/readers.
Table 1.
Order code
Device summary
Temp. range
Package
SPEAR600-2 -40 to 85 °C
PBGA420
(23 x 23 x
2.06 mm)
Packing
Tray
May 2012
This is information on a product in full production.
Doc ID 16259 Rev 3 1/97 www.
s t.com
1
Contents
Contents
SPEAr600
Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR/DDR2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flexible static memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Multichannel DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Synchronous Serial Peripheral (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
S audio block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reconfigurable array subsystem connectivity (RAS) . . . . . . . . . . . . . . . . 22
External Port Controller (EXPI I/F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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SPEAr600
Contents
Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin descriptions listed by functional block . . . . . . . . . . . . . . . . . . . . . . . . 24
Disable NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
All processors disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power on reset (MRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ADC electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DDR2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DDR2 read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DDR2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DDR2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
EXPI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CLCD timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 71
Doc ID 16259 Rev 3 3/97
Contents
SPEAr600
CLCD timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 72
FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Ether MAC 10/100/1000 Mbps (GMAC-Univ) timing characteristics . . . . 80
GMII Transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
GMII-MII Receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . 82
MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SMI timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SPI master mode timings (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SPI master mode timings (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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SPEAr600
List of tables
List of tables
Low voltage TTL DC input specification (3 V< V
DD
<3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . 57
Low voltage TTL DC output specification (3 V< V
<3.6 V) . . . . . . . . . . . . . . . . . . . . . . . 57
C in high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C in fast-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C in standard-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Doc ID 16259 Rev 3 5/97
List of tables SPEAr600
PBGA420 thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6/97 Doc ID 16259 Rev 3
SPEAr600
List of figures
List of figures
2
C output pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2
C input pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Output command signal waveforms for 8-bit NAND Flash configuration . . . . . . . . . . . . . . 76
Output address signal waveforms for 8-bit NAND Flash configuration. . . . . . . . . . . . . . . . 77
In/out data address signal waveforms for 8-bit NAND Flash configuration. . . . . . . . . . . . . 77
Output command signal waveforms 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . 78
Output address signal waveforms 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . 79
Doc ID 16259 Rev 3 7/97
Description
1 Description
SPEAr600
The SPEAr600 is a member of the SPEAr family of embedded MPUs for networked devices, it is based on dual ARM926EJ-S processors (up to 333 MHz), widely used in applications where high computation performance is required.
Both processors have an MMU supporting virtual memory management and making the system compliant with the Linux operating system. They also offer 16 KBytes of data cache,
16 KBytes of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations.
To expand its range of target applications, SPEAr600 can be extended by adding additional peripherals through the external local bus (EXPI interface).
Figure 1.
Functional block diagram
NAND
Flash controller
DDR1/DDR2 memory controller
Serial Flash
Interface
32 KBytes BootRom
8 KBytes SRAM
LCD controller
1024*768
Ethernet Controller
10/100/1000 Mbps
EXPI I/f
ARM926EJ-S
@333 MHz
System controller
Interrupt controller
MMU
ICache
DCache
ARM926EJ-S
@333 MHz
System controller
Interrupt controller
MMU
ICache
DCache
RTC
Watchdog
Timers
PLLs
MultiChannel DMA controller
JPEG Codec accelerator
USB Host 2.0 +Phy
USB Host 2.0 +Phy
USB Device 2.0 +Phy
I 2 C master/slave
2x UART
Fast IrDA
3x SSP
GPIO
10x Timers
ADC 10-bit 8ch
3x I2S
8/97 Doc ID 16259 Rev 3
SPEAr600 Description
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Dual core ARM926EJ-S 32-bit RISC CPU, up to 333 MHz, each with:
– 16 Kbytes of instruction cache, 16 Kbytes of data cache
– 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, byte Java mode (Jazelle™) for direct execution of Java code.
– Tightly Coupled Memory
– AMBA bus interface
32-KByte on-chip BootROM
8-KByte on-chip SRAM
Dynamic memory controller managing external DDR1 memory up to 166 MHz and external DDR2 memory up to 333 MHz
Serial memory interface
8/16-bits NAND Flash controller
Possible NAND Flash or serial NOR flash booting
Multichannel DMA controller
Color LCD Controller for STN/TFT display panels
– Up to 1024 x 768 resolution
– 24 bpp true color
Ethernet GMAC 10/100/1000 Mbps (GMII/MII PHY interface)
Two USB 2.0 host (high-full-low speed) with integrated PHY transceiver
One USB 2.0 device (high-full speed) with integrated PHY transceiver
10 GPIO bidirectional signals with interrupt capability
JPEG codec accelerator 1clock/pixel
ADC 10-bit, 1 Msps 8 inputs/1-bit DAC
3 SSP master/slave (supporting Motorola, Texas instruments, National Semiconductor protocols) up to 40 Mbps
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C master/slave interface (slow/ fast/high speed, up to 1.2 Mb/s)
10 independent 16-bit timers with programmable prescaler
I/O peripherals
– Two UARTs (speed rate up to 460.8 kbps)
– Fast IrDA (FIR/MIR/SIR) 9.6 Kbps to 4 Mbps speed-rate
Audio block with 3-I2Ss interfaces to support Audio Play (Up to 3.1) and Audio Record functionality.
Advanced power saving features
– Normal, Slow, Doze and Sleep modes, CPU clock with software-programmable frequency
– Enhanced dynamic power-domain management
– Clock gating functionality
– Low frequency operating mode
– Automatic power saving controlled from application activity demands
Vectored interrupt controller
System and peripheral controller
Doc ID 16259 Rev 3 9/97
Description
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– RTC with separate power supply allowing battery connection
– Watchdog timer
– Miscellaneous registers array for embedded MPU configuration.
External local bus (EXPI I/f) that is an AMBA AHB like interface
Programmable PLLs for CPU and system clocks
JTAG IEEE 1149.1 boundary scan
ETM functionality multiplexed on primary pins.
Supply voltages
– 1.0 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs 1.8 V RTC and 3.3 V I/Os
Operating temperature: - 40 to 85 °C
ESD rating: HBM class 2, CDM class II
PBGA420 (23 x 23 x 2.06 mm, pitch 1 mm)
SPEAr600
10/97 Doc ID 16259 Rev 3
SPEAr600 Architecture overview
shows an example of a typical SPEAr600 based system.
Figure 2.
Typical system architecture using SPEAr600
Internet
Access
Phy
FSMC
SMI
DDR memory controller
JTAG
ETM9
ADC
SPEAr600
LCD controller
ARM 926EJ up to 333 MHz
MMU
Interrupt/
Syst controller
8-Channel DMA
10 Timers / WD
ARM 926EJ up to 333 MHz
MMU
Interrupt/
Syst controller
8 KB Embed. SRAM
32 KB Embed. ROM FIdDA
RTC
Clock, Reset
RAS EXPI I/f
I2C
3xI2S Uart1 Uart2 3xSSP
30 MHz 32 kHz
The core of the SPEAr600 is the dual ARM926EJ-S reduced instruction set computer
(RISC) processor.
It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes.
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Each ARM CPU:
Is clocked at a frequency up to 333 MHz
Embeds 16 Kbytes instruction cache + 16 Kbytes data cache
Features a memory management unit (MMU) which makes it fully compliant with Linux and VxWorks operating systems.
The SoC includes three major subsystems logic domains which control the following function blocks:
Configurable Cell Array Subsystem
This block contains the Reconfigurable Array Subsystem logic (RAS) made by an array of
600Kgate equivalent standard cells freely customizable by means of a few metal and via mask layer changes during the customization process. The programmable logic allows reducing the SoC NRE cost, the development cycle time improving the devices time to
Doc ID 16259 Rev 3 11/97
Architecture overview SPEAr600
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130 Kbyte of static memory arranged in four 32 KB macro group and one 2 KB group.
Up to 17 selectable source clocks (either internal or external)
DMA support (up to 16 configurable dma input/output request lines)
Power management I/F
Interrupts line (12 outputs - 64 inputs)
4 AHB output master ports interconnected with the multi-channel memory controller
5 AHB input slave ports
1 interconnection port with the Expansion Interface bus (EXPI)
9 LVDS (8 outputs - 1 input) signals
88/112 PL_GPIOs primary input/output signals
Caution: PL GPIO pins are not configurable by software.
Common Subsystem
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This block consists of four different logic subsystems used to control the SoC basic functions:
● I/O connectivity:
– Low speed: UARTs, SSPs, I2C and IrDA
– High speed: MII 10/100/1000, USB 2.0 host and devices
Hardware accelerator: JPEG-codec and DMA
Video: Color LCD interface
Common resources: Timers, GPIOs, RTC and Watchdog
Power management functionality
SoC configurability: Miscellaneous control logic
CPU Subsystem
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The SPEAr600 has a symmetric processor architecture with:
● 2 equivalent subsystems including the ARM926 and its private subsystem logic
(GPIOs, Interrupt controller and Timer) providing the essential hardware resources to support a generic Operating System
● The subsystem is replicated twice so both processors have the same memory map.
This structure enables a true symmetric multi-processor architecture were both processors can simultaneously execute the same OS (all interrupt sources are handled by both processors)
All internal peripherals are shared, allowing flexible and efficient software partitions.
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High aggregate throughput can be sustained by splitting critical tasks either onto additional CPUs and optional hardware accelerator engines.
Both processors are equipped with ICE and ETM configurable debug interfaces. for real-time CPU activity tracing and debugging.
4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode is supported, with normal or half-rate clock.
The internal architecture is also based on several shared subsystem logic blocks interconnected through a multilayer interconnection matrix. The switch matrix structure
12/97 Doc ID 16259 Rev 3
SPEAr600 Architecture overview allows different subsystem data flows to be executed in parallel improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller reducing the memory access latency. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted roundrobin arbitration mechanism.
The SPEAr600 has two embedded memory units
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32 Kbytes of BootROM
8 Kbytes of SRAM
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SPEAr600 integrates a high performance multi-channel memory controller able to support
DDR1 and DDR2 double data rate memory devices. The multi-port architecture ensures that memory is shared efficiently among different high-bandwidth client modules.
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Main features:
● Multi channel AHB interfaces:
– Seven independent AHB ports
– Separate AHB memory controller programming interface
– Support all AHB burst types
– Lock transaction are not supported
Internal efficient port arbitration scheme to ensure high memory bandwidth utilization
Programmable register interface to control memory device parameters and protocols
DRAM controller supports both DDR1 and DDR2 memory devices:
– DDR1 up to 166 MHz
– DDR2 up to 333 MHz
Memory frequency with DLL enable configurable from 100 MHz to 333 MHz
Wide range of memory devices supported:
– 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit, 2 Gbit
– Two chip selects.
– 8 or 16-bit data width
Serial memory interface
SPEAr600 provides a Serial Memory Interface (SMI), acting as an AHB slave interface
(32-, 16- or 8-bit) to SPI-compatible off-chip memories.
These serial memories can be used either as data storage or for code execution.
Doc ID 16259 Rev 3 13/97
Architecture overview SPEAr600
Main features:
● Supports the following SPI-compatible Flash and EEPROM devices:
– STMicroelectronics M25Pxxx, M45Pxxx
– STMicroelectronics M95xxx, except M95040, M95020 and M95010
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– ATMEL AT25Fxx
– YMC Y25Fxx
– SST SST25LFxx
Acts always as a SPI master and supports up to 3 SPI slave memory devices (with separate chip select signals), with up to 16 MB address space each
SMI clock (SMICLK) is generated by SMI (and input to all slaves) using a clock provided by the AHB bus
SMI_CLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can be controlled by 7 programmable bits.
2.4
Note:
Flexible static memory controller
Root part number 1 provides Flash Nand Static Memory Controller (FSMC) which is intended to interface an AHB bus to external NAND Flash memories.
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Main purpose of FSMC is then:
Translate AHB protocol into the appropriate external storage device protocol
Meet the timing of the external devices, slowing down and counting an appropriate number of HCLK (AHB clock) cycles to complete the transaction to the external device
The external s torage device cannot be fa s ter than one AHB cycle.
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Main features of the FSMC are listed below:
The FSMC is an AMBA slave module connected to the AHB
Provides an interface between AHB system bus and Nand Flash memory devices with
8 and 16 bits wide data paths
FSMC performs only one access at a time and only one external device is accessed
Support little-endian and big-endian memory architectures
Handles AHB burst transfers to reduce access time to external devices
Supplies an independent configuration for each memory bank
Provides programmable timings to support a wide range of devices:
– Programmable wait states (up to 31)
– Programmable bus turn around cycles (up to 15)
– Programmable output enable and write enable delays (up to 15)
Provides only one chip select for the first memory bank
Shares the address bus and the data bus with all the external peripherals, whereas only chips selects are unique for each peripheral
Offers an external asynchronous wait control
Offers configurable size at reset for boot memory bank using external control pins.
14/97 Doc ID 16259 Rev 3
SPEAr600
2.5
Architecture overview
Multichannel DMA controller
Within its basic subsystem, SPEAr600 provides a DMA controller (DMAC) able to service up to 8 independent DMA channels for serial data transfers between a single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to-memory, and peripheral-to-peripheral).
Each DMA channel can support unidirectional transfers, with one internal four-word FIFO per channel.
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Main features:
Resolution programmable up to 1024 x 768
16-bpp true-color non-palletized, for color STN and TFT
24-bpp true-color non-palletized, for color TFT
Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8bit interfaces
Supports single and dual-panel color and monochrome STN displays
Supports thin film transistor (TFT) color displays
15 gray-level mono, 3375 color STN, and 32 K color TFT support
1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN
1, 2, 4 or 8-bpp palletized color displays for color STN and TFT
Programmable timing for different display panels
256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line and pixel clock signals
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AC bias signal for STN and data enable signal for TFT panels patented gray scale algorithm
Supports little-endian, big-endian and WinCE data formats
2.7 GPIOs
The General Purpose Input/Outputs (GPIOs) provide programmable inputs or outputs.
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Each input/output can be controlled in two distinct modes:
Software mode, through an APB interface
Hardware mode, through a hardware control interface.
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SPEAr600 provides up to 10 GPIO lines:
Individually programmable input/output pins (default to input at reset)
An APB slave acting as control interface in "software mode"
Programmable interrupt generation capability on any number of pins
Bit masking in both read and write operations through address lines
Doc ID 16259 Rev 3 15/97
Architecture overview SPEAr600
Main features:
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Compliance with the baseline JPEG standard (ISO/IEC 10918-1)
Single-clock per pixel encoding/decoding
Support for up to four channels of component color
8-bit/channel pixel depths
Programmable quantization tables (up to four)
Programmable Huffman tables (two AC and two DC)
Programmable minimum coded unit (MCU)
Configurable JPEG headers processing
Support for restart marker insertion
Use of two DMA channels and of two 8 x 32-bits FIFOs (local to the JPEG) for efficient transferring and buffering of encoded/decoded data from/to the codec core.
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Main features:
Successive approximation ADC
10-bit resolution @1 Msps
Hardware over sampling and accumulation up to 128 samples
Eight analog input (AIN) channels, ranging from 0 to 2.5 V
INL ± 1 LSB, DNL ± 1 LSB
Programmable conversion speed, (min. conversion time is 1 µs)
Programmable averaging of results from 1 (No averaging) up to 128
16/97
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Main features:
● Supports the default Gigabit Media Independent Interface (GMII)/Media Independent
Interface (MII) defined in the IEEE 802.3 specifications.
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Supports 10/100/1000 Mbps data transfer rates with any one or a combination of the above PHY interfaces
Supports both half-duplex and full-duplex operation. In half-duplex operation,
CSMA/CD protocol is provided for, as well as packet bursting and frame extension at
1000 Mbps
● Programmable frame length to support both Standard and Jumbo Ethernet frames with size up to 16 Kbytes
32-bit data transfer interface on system-side
A variety of flexible address filtering modes are supported
A set of control and status registers (CSRs) to control GMAC Core operation.
Complete network statistics with RMON Counters (MMC, MAC Management
Counters).
Doc ID 16259 Rev 3
SPEAr600 Architecture overview
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Native DMA with single-channel Transmit and Receive engines, providing 32/64/128-bit data transfers
DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining
A set of CSRs to control DMA operation
An AHB slave acting as programming interface to access all CSRs, for both DMA and
GMAC core subsystems
An AHB master for data transfer to system memory
32-bit AHB master bus width, supporting 32-bit wide data transactions
Supports both big-endian and little-endian byte ordering
Power Management Module (PMT) with Remote Wake-up and Magic Packet frame processing options
2.11 USB2 host controller
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SPEAr600 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks:
EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)
OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)
Local 2-Kbyte FIFO
Local DMA
Integrated USB2 transceiver (PHY)
Both hosts can manage an external power switch, providing a control line to enable or disable the power, and an input line to sense any over-current condition detected by the external switch.
Both host controllers can perform high speed transfer simultaneously.
2.12 USB2 device controller
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Main features:
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Supports 480 Mbps high-speed mode (HS) for USB 2.0, as well as 12 Mbps full-speed
(FS) and the low-speed (LS modes) for USB 1.1
Supports 16 physical endpoints, which can be assigned to different interfaces and configurations to implement logical endpoints
Integrated USB transceiver (PHY)
Local 4 Kbyte FIFO shared by all endpoints
DMA mode and slave-only mode are supported
In DMA mode, the UDC supports descriptor-based memory structures in application memory
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In both modes, an AHB slave is provided by UDC-AHB, acting as programming interface to access to memory-mapped control and status registers (CSRs)
An AHB master for data transfer to system memory is provided, supporting 8, 16, and
32-bit wide data transactions on the AHB bus
● A USB plug detect (UPD) which detects the connection of a cable.
Doc ID 16259 Rev 3 17/97
Architecture overview SPEAr600
2.1
3
Synchronous Serial Peripheral (SSP)
The SPEAR600 has three Synchronous Serial Peripherals (SSPs) (SPI, Microwire or TI protocol).
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Main features:
●
●
Maximum speed of 40 Mbps
Programmable choice of interface protocol:
– SPI (Motorola)
– Microwire (National Semiconductor)
– TI synchronous serial
Programmable data frame size from 4 to 16-bit.
Master and slave mode capability.
DMA interface
2.14 I2C
●
●
●
Main features:
● Compliance to the I
2
C bus specification (Philips)
● I
2
C v2.0 compatible.
● Supports three modes:
– Standard (100 kbps)
– Fast (400 kbps)
– High-speed (3.4 Mbps)
Master and slave mode configuration possible
Slave Bulk data transfer capability
DMA interface
2.15 UARTs
The SPEAr600 has two UARTs.
●
●
Main features:
Hardware flow control
Separate 16x8 (16 locations deep x 8 bits wide) transmit and 16 x 12 receive FIFOs to reduce CPU interrupts
● Speed up to 3 Mbps
18/97 Doc ID 16259 Rev 3
SPEAr600 Architecture overview
The SPEAr600 has a Fast IrDA controller.
●
●
●
●
●
●
Main features:
● Supports the following standards:
– IrDA serial infrared physical layer specification (IrPHY), version 1.3
●
– IrDA link access protocol (IrLAP), version 1.1
Supports the following infrared modes and baud rates:
– Serial infrared (SIR), with rates 9.6 kbps, 19.2 kbps, 38.4 kbps, 57.6 kbps and
115.2 kbps
– Medium Infrared (MIR), with rates 576 kbps and 1.152 Mbps
●
– Fast Infrared (FIR), with rate 4 Mbps
Transceiver interface compliant to all IrDA transceivers with configurable TX and RX signal polarity
Half-duplex infrared frame transmission and reception
16-bit CRC algorithm for SIR and MIR, and 32-bit CRC algorithm for FIR
Generates preamble, start and stop flags
Uses the RZI (Return-to-Zero Inverted) modulation/demodulation scheme for SIR and
MIR, and the 4PPM (4 Pulse Position Modulation) modulation/demodulation scheme for FIR
Provides synchronization by means of a DPLL in FIR mode
Easily adaptable to different bus systems with 32-bit register interface and FIFO with configurable FIFO size
2.17 I
2
S audio block
SPEAr600 contains three I
2
S interfaces providing the following features.
●
●
●
Main features:
● Conversion of AHB protocol to I
2
S protocol and vice versa
● Supports 2.0, 2.1 and 3.1 audio outputs (I
2
S master mode)
32 (16L + 16R) and 64 bit (32L + 32R) of raw PCM data length supported
MIC/Line-In (2.0) recording (I2S master/slave mode)
Stereo headphone out
The System Controller provides an interface for controlling the operation of the overall system.
●
●
●
Main features:
Power saving system mode control
Crystal oscillator and PLL control
Configuration of system response to interrupts
Doc ID 16259 Rev 3 19/97
Architecture overview
●
●
Reset status capture and soft reset generation
Watchdog module clock enable
SPEAr600
Using three mode control bits, the system controller switch the SPEAr600 to any one of four different modes: DOZE, SLEEP, SLOW and NORMAL.
● SLEEP mode : In this mode the system clocks, HCLK and CLK, are disabled and the
System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz).
When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters
DOZE mode. Additionally, the operating mode setting in the system control register automatically changes from SLEEP to DOZE.
●
●
DOZE mode : In this mode the system clocks, HCLK and CLK, and the System
Controller clock SCLK are driven by a low speed oscillator. The System Controller moves into SLEEP mode from DOZE mode only when none of the mode control bits are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL mode is required the system moves into the XTAL control transition state to initialize the crystal oscillator.
SLOW mode : During this mode, both the system clocks and the System Controller clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode control bits are set, the system goes into the "Switch from XTAL" transition state.
● NORMAL mode : In NORMAL mode, both the system clocks and the System Controller clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the system goes into the "Switch from PLL" transition state.
2.19 Clock and reset system
The clock system is a fully programmable block that generates all the clocks for the
SPEAr600.
The default operating clock frequencies are:
●
●
●
●
●
Clock @ 333 MHz for the CPUs.
Clock @ 166 MHz for AHB bus and AHB peripherals. (PLL1 source)
Clock @ 83 MHz for, APB bus and APB peripherals. (PLL1 source)
Clock @ 100-333 MHz for DDR memory interface. (PLL1, PLL2 source)
Clock @ 12 MHz, 30 MHz and 48 MHz for USBs (PLL3 source)
The above frequencies are the maximum allowed values.
All these clocks are generated by three PLLs.
PLL1 and PLL2 sources are fully programmable through dedicated registers.
The clock system consists of 2 main parts: a multi clock generator block and two internal
PLLs.
The multi clock generator block, takes a reference signal (which is usually delivered by the
PLL), generates all clocks for the IPs of SPEAr600 according to dedicated programmable registers.
20/97 Doc ID 16259 Rev 3
SPEAr600 Architecture overview
Each PLL uses an oscillator input of 30 MHz to generate a clock signal at a frequency corresponding to the highest of the group. This is the reference signal used by the multi clock generator block to obtain all the other required clocks for the group. Its main feature is electromagnetic interference reduction capability.
The user can set up the PLL in order to modulate the VCO with a triangular wave. The resulting signal has a spectrum (and power) spread over a small programmable range of frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic emissions. This method replaces all the other traditional methods of EMI reduction, such as filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal shielding and so on. This gives the customer appreciable cost savings.
In sleep mode the SPEAr600 runs with the PLL disabled so the available frequency is 30
MHz or a sub-multiple (/2, /4, /16 and /32) or 32 KHz.
PLL3 is used to generate the USB controller clocks and it is not configured through registers.
2.20 Vectored interrupt controller (VIC)
Each ARM Subsystem of SPEAr600 offers Vectored Interrupted Controller (VIC) blocks, providing a software interface to the interrupt system.
Acting as an interrupt controller, the VIC determines the source that is requesting service and where its interrupt service routine (ISR) is loaded, doing that in hardware.
In particular, the VIC supplies the starting address, or vector address, of the ISR corresponding to the highest priority requesting interrupt source.
●
●
●
●
Main features of the VIC are listed below:
● Support for 32 standard interrupt sources (a total of 64 lines are available for each CPU from its two daisy-chained VICs).
● Generation of both Fast Interrupt request (FIQ) and Interrupt Request (IRQ. IRQ is used for general interrupts, whereas FIQ is intended for fast, low-latency interrupt handling.
Support for 16 vectored interrupts (IRQ only);
Hardware interrupt priority
– FIQ interrupt has the highest priority
– followed by vectored IRQ interrupts, from vector 0 to vector 15
– then non-vectored IRQ interrupts with the lowest priority
Interrupt masking/ interrupts request status
Software interrupt generation
2.21 General purpose timers
SPEAr600 provides five general purpose timers (GPTs) acting as APB slaves.
Each GPT consists of 2 channels, each one made up of a programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock division by 1 up to 256, and different input frequencies can be chosen through SPEAr600 configuration registers (frequencies up to 83 MHz can be synthesized).
Doc ID 16259 Rev 3 21/97
Architecture overview SPEAr600
Two different modes of operation are available:
● Auto-reload mode, an interrupt source is activated, the counter is automatically cleared and then it restarts incrementing.
● Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT is disabled.
The ARM watchdog module consists of a 32-bit down counter with a programmable time-out interval that has the capability to generate an interrupt and a reset signal on timing out. The watchdog module is intended to be used to apply a reset to a system in the event of a software failure.
2.2
3
RTC
The RTC provides a 1-second resolution clock. This keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update.
●
●
●
●
Main features:
Time-of-day clock in 24 hour mode
Calendar
Alarm capability
Isolation mode, allowing RTC to work even if power is not supplied to the rest of the device.
2.24 Reconfigurable array subsystem connectivity (RAS)
●
●
●
●
●
●
The Reconfigurable Logic Array consists of an embedded macro where it is possible to implement a custom project by mapping up to 600k equivalent standard cells. The user can design custom logic and special function using various features offered by the
Reconfigurable Logic Array and by the SPEAr600 system listed here below.
4 AHB bus master interfaces
5 AHB bus slave interfaces
Dedicated interface with CPU1 to customize the Tightly Couple Memory
Dedicated interface with CPU1 to customize the Coprocessor
Dedicated interface with CPU2 to customize the Tightly Coupled Memory
Interfaces towards a dedicated 130 kB Memory Array Subsystem provided of functional
BIST driven by SoC via software and divided in the following ST memory cuts:
– 3 single port memory cuts (48 words x 128 bits)
– 4 single port memory cuts (2048 words x 32 bits)
– 8 single port memory cuts (1024 words x 32 bits)
– 16 single port memory cuts (512 words x 32 bits)
– 8 dual port memory cuts (512 words x 32 bits)
22/97 Doc ID 16259 Rev 3
SPEAr600 Architecture overview
●
●
●
●
●
●
●
●
●
●
– 4 dual port memory cuts (1024 words x 32 bits)
Clock system constituted by:
– 5 clocks coming from the external balls
– 4 clocks coming from the integrated frequency synthesizers
– CPU core clock frequency
– Pll2 frequency
– 48 MHz clock (USB Pll)
– 30 MHz clock (Main Oscillator)
– 32.768 kHz clock (RTC Oscillator)
– APB clock (programmable)
– AHB clock (programmable)
– User Configurable sync/async clock towards Memory Controller port 2 (M2)
Connection with 84/112 I/Os
Connection with 9 LVDS lines
12 interrupt lines towards CPU1 and CPU2
64 interrupt input lines from the various platform IP sources
16 peripheral DMA request lines
64 user configurable (in the SoC) general purpose input lines
64 user configurable (in the RAS) general purpose output lines
SoC dynamic power management control interface;
50 specific ATE Test interface signals dedicated to RAS
The port controller is a socket communication interface between the SPEAr600 and an external FPGA device; it implements a simple AHB bidirectional protocol used to compress a couple of std AHB master/slave bus onto 84 PL_GPIOs and 4 PL_CLK primary signals.
Caution: PL_GPIO pins are not configurable by software.
ST provide a symmetric port controller logic solution to be embedded inside the external
FPGA with the purpose of interfacing the EXPI bus directly and decompressing the same pair of AHB master/slave ports on the FPGA side in order to interconnect the customer logic as follows (more slave and master agents can be connected to the EXPI):
SPEAr600_AHB-master >> FPGA_AHB-slave
SPEAr600_AHB-slave << FPGA_AHB-master (AHB-full)
The EXPI interface is based on two main groups of signals:
●
●
AHB bidirectional signal bus driven alternatively from the SPEAr600 and FPGA side.
Unidirectional signals continuously driven from both the SPEAr600 and FPGA sides.
Table 36: EXPI - pad s ignal a ss ignment
lists the EXPI signal names. Further details in these signals are given in the SPEAr600 user manual (UM0510)
Doc ID 16259 Rev 3 23/97
Pin description
3
Pin
SPEAr600
The following tables describe the pinout of the SPEAr600 listed by functional block.
This description refers to the default configuration of SPEAr600 (full features).
●
●
●
●
●
●
●
●
●
●
●
●
●
●
More details on the configuration of each pin are given in Table 16: Multiplexing s cheme
.
Table 2: Sy s tem re s et, ma s ter clock, RTC and configuration pin s
Table 5: SMI, SSP, UART, FIRDA and I2C pin
List of abbreviations:
PU = Pull Up
PD = Pull Down
3
.1 Required components
1.
DDR_COMP_1V8: place an external 121 k
Ω resistor between ball V7 and ball V8
2. DDR_COMP_2V5: place an external 121 k
Ω resistor between ball V9 and ball V8
3. USB_RREF: connect an external 1.5 k
Ω pull-down resistor to ball U4
4. DIGITAL_REXT: place an external 121 k
Ω
resistor between ball E11 and ball E126.
3
.2 Pin descriptions listed by functional block
Table 2.
Group
SYSTEM
RESET
System reset, master clock, RTC and configuration pins
Signal name Ball Direction Function
MRESET
CONFIG DIGITAL_REXT
C17
E11
Input
Ref
Main reset
Configuration
Pin type
TTL Schmitt trigger input buffer,
3.3 V tolerant, PU
Analog,
3.3 V capable,
See
24/97 Doc ID 16259 Rev 3
SPEAr600 Pin description
Table 2.
Group
Master clock
RTC
System reset, master clock, RTC and configuration pins (continued)
Signal name Ball Direction Function Pin type
MCLK_XI
MCLK_XO
RTC_XI
RTC_XO
Y1
Y2
A9
B9
Input
Output
Input
Output
30 MHz crystal I
30 MHz crystal O
32 kHz crystal I
32 kHz crystal O
Oscillator,
2.5 V capable
Oscillator,
1.8 V capable
Table 3 .
Group
Power supply pins
Signal name
DIGITAL
GROUND
ANALOG
GROUND
I/O
CORE
Ball
GND
RTC_GNDE
DITH_VSS
DDR_MEM_PLL_VSS_DIG
DIGITAL_GNDBGCOMP
ADC_AGND
DDR_MEM_PLL_VSS_ANA
USB_VSSC2V5
USB_HOST1_VSSBS
USB_HOST2_VSSBS
USB_DEV_VSSBS
USB_PLL_VSSP
USB_PLL_VSSP2V5
MCLK_GND
MCLK_GNDSUB
DITH_VSS2V5
VDDE3V3
VDD
J9, J10, J11, J12, J13, J14, K9, K10,
K11, K12, K13, K14, L9, L10, L11,
L12, L13, L14, M9, M10, M11, M12,
M13, M14, N9, N10, N11, N12, N13,
N14, P9, P10, P11, P12, P13, P14,
M18, N18, P18, T5, V6
A10
U5
U17
E12
V16
V17
T4
R1
N2
U2
W3
W2
Y3
AA3
V5
J6, H6, F8, F9, F16, H17, K17, L17,
N17, P17, M6, F17
G6, L6, G17, M17, R17, F10, F13,
F15, J17, T6, U13, U10, U16
HOST1/HOST2
USB PHY
USB_HOST_VDD3V3 R3
HOST2 USB
PHY
USB_HOST2_VDDBC
USB_HOST2_VDDBS
N1
N3
Value
0 V
0 V
3.3 V
1.0 V
3.3V
2.5 V
1.0 V
Doc ID 16259 Rev 3 25/97
Pin description SPEAr600
Table 3 .
Group
Power supply pins (continued)
Signal name Ball Value
HOST1 USB
PHY
DEVICE USB
PHY
USB PLL
USB_HOST1_VDDBC
USB_HOST1_VDDBS
USB_DEV_VDDBC
USB_DEV_VDDBS
USB_DEV_VDD3V3
USB_PLL_VDDP
USB_PLL_VDDP2V5
OSCI (MASTER
CLOCK)
PLL1
DDR I/O
ADC
PLL2
(1)
LVDS I/O
OSCI RTC
MCLK_VDD
MCLK_VDD2V5
DITH_VDD2V5
DITH_VDD
SSTL_VDDE1V8
ADC_AVDD
DDR_MEM_PLL_VDD_ANA
DDR_MEM_PLL_VDD_DIG
LVDS_VDDE2V5
RTC_VDDE_1V8
P3
R2
U1
U3
T3
V3
W1
AA1
AA2
V4
U6
U7, U8, U9, U11, U12, U14, U15
W16
W17
T17
F11, F12, F14
B10
1.
For DDRI the supply voltage must be 2.5 V, instead for DDRII the supply voltage must be 1.8 V.
1.0 V
2.5 V
2.5 V
1.0 V
1.8/2.5 V
2.5 V
2.5 V
1.0 V
2.5 V
1.8 V
2.5 V
1.0 V
2.5 V
1.0 V
3.3 V
1.0 V
2.5 V
26/97 Doc ID 16259 Rev 3
SPEAr600
Table 4.
Group
Debug pins
Signal name
BOOT_SEL
TEST_0
TEST_1
TEST_2
TEST_3
TEST_4
TEST_5
DEBUG nTRST
Ball
K18
E15
E14
D14
D13
E13
D12
Direction
Input
Function
Boot selection
Input
Pin type
Pin description
Configuration ports
TTL input buffer, 3.3 V tolerant, PD
TDO
TCK
TDI
TMS
D17
E17
E16
D16
D15
Input
Output
Input
Input
Input
Test reset Input
Test clock
Test data input
Test mode select
TTL Schmitt trigger, input buffer, 3.3 V tolerant, PU
Test data outpuT
TTL output buffer, 3.3 V capable, 4 mA
TTL Schmitt trigger, input buffer, 3.3 V tolerant, PU
Table 5.
Group
SMI, SSP, UART, FIRDA and I2C pins
Signal name Ball Direction
SMI_DATAIN L21 Input
SMI
SMI_DATAOUT
SMI_CLK
SMI_CS_0
SMI_CS_1
L20
L22
L19
L18
Output
Function
Serial Flash input data
Serial Flash output data
Serial Flash clock
Serial Flash chip selects
Pin type
TTL input buffer, 3.3 V
TTL output buffer, 3.3 V capable,
4 mA
Doc ID 16259 Rev 3 27/97
Pin description SPEAr600
Table 5.
Group
SSP
UART
FIRDA
SMI, SSP, UART, FIRDA and I2C pins (continued)
Signal name
SSP_1_MOSI
SSP_1_MISO
SSP_1_SCLK
SSP_1_SS
SSP_2_MOSI
SSP_2_MISO
SSP_2_SCLK
SSP_2_SS_0
SSP_3_MOSI
SSP_3_MISO
SSP_3_SCLK
SSP_3_SS
UART1_TXD
UART2_TXD
UART1_RXD
UART2_RXD
FIRDA_TXD
FIRDA_RXD
Ball
AA21
AB21
AB22
AA22
K20
K21
K22
K19
J20
J21
J22
J19
AA19
AA20
AB19
AB20
AA18
AB18
Direction
I/O
Output
Input
Output
Input
Function Pin type
Master out slave in
Master in slave out
Serial clock
Slave select
Master out slave in
Master in slave out
Serial clock
Slave select
TTL bidir buffer, 3.3 V capable,
8 mA,
3.3 V tolerant,
PU
(1)
Master out slave in
Master in slave out
Serial clock
Slave select
Serial data out
Serial data in
Serial data out
Serial data in
TTL output buffer, 3.3 V capable, 4 mA
TTL input buffer, 3.3 V tolerant, PD
TTL output buffer, 3.3 V capable, 4mA
TTL input buffer, 3.3 V tolerant, PU
I2C
SDA
SCL
Y18
Y19
I/O
I/O
Serial data in/out
Serial clock
TTL bidir buffer, 3.3V capable, 4 mA,
3.3 V tolerant,
PU
1.
When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
28/97 Doc ID 16259 Rev 3
SPEAr600
Table 6.
Group
USB
USB pins
Signal name
USB_DEV_DP
USB_DEV_DM
USB_DEV_VBUS
USB_HOST1_DP
USB_HOST1_DM
USB_HOST1_VBUS
USB_HOST1_OVRC
USB_HOST2_DP
USB_HOST2_DM
USB_HOST2_VBUS
USB_HOST2_OVRC
USB_USB_RREF
T1
T2
P5
Ball
V1
V2
R4
P6
P1
P2
R5
R6
U4
Pin description
Direction
I/O
Function Pin type
USB Device D+
USB Device D-
Bidirectional analog buffer,
5 V tolerant
Input
USB Device
VBUS
TTL input buffer,
3.3 V tolerant,
PD
I/O
Output
USB HOST1
D+
USB HOST1 D-
Bidirectional analog buffer
5 V tolerant
USB HOST1
VBUS
TTL output buffer, 3.3 V capable, 4 mA
Input
USB Host1
Over-current
TTL input buffer,
3.3V tolerant, active low
I/O
Output
USB HOST2
D+
USB HOST2 D-
Bidirectional analog buffer,
5 V tolerant
USB HOST2
VBUS
TTL output buffer, 3.3 V capable, 4 mA
Input
Output
USB Host2
Over-current
TTL input buffer,
3.3 V tolerant, active low
Ext.Reference resistor
Analog, see
Doc ID 16259 Rev 3 29/97
Pin description
Table 7.
Group
Ethernet pins
Signal name
GMII_TXCLK
Ethernet
GMII_TXCLK125
MII_TXCLK
TXD_0
TXD_1
TXD_2
TXD_3
GMII_TXD_4
GMII_TXD_5
GMII_TXD_6
GMII_TXD_7
TX_ER
TX_EN
RX_ER
RX_DV
RX_CLK
RXD_0
RXD_1
RXD_2
RXD_3
GMII_RXD_4
GMII_RXD_5
GMII_RXD_6
GMII_RXD_7
COL
CRS
MDIO
Ball
F22
E22
D22
F21
E21
F20
E20
D21
D20
C22
C21
D18
D19
C20
C19
A22
B22
B21
A21
B20
A20
B19
A18
A19
A17
B17
B18
MDC C18
SPEAr600
Direction
Output
Input
I/O
Function Pin type
Transmit clock
(GMII)
TTL output buffer,
3.3 V capable,
8 mA
Ext. Clock
Transmit clock
MII
TTL input buffer,
3.3 V tolerant, PD
Output
TTL output buffer,
3.3 V capable,
8 mA
Transmit data
I/O
Output
Input
TTL bidirectional buffer, 3.3 V capable, 8 mA,
3.3 V tolerant, PD
Transmit error TTL output buffer,
3.3 V capable,
Transmit enable
8 mA
Receive error
Receive data valid
Receive clock
TTL input buffer,
3.3 V tolerant, PD
I/O
Input
I/O
Output
Receive data
TTL bidirectional buffer, 3.3 V capable, 8 mA,
3.3 V tolerant, PD
Collision detect
Carrier sense
TTL input buffer,
3.3 V tolerant, PD
Management data I/O
Management data clock
TTL bidirectional buffer, 3.3 V capable, 4 mA,
3.3 V tolerant, PD
TTL output buffer,
3.3 V capable,
4 mA
30/97 Doc ID 16259 Rev 3
SPEAr600 Pin description
Table 8.
Group
GPIO pins
Signal name Ball Direction Function Pin type
GPIO
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
W18
V18
U18
T18
W19
V19
U19
T19
R19
R18
I/O
General purpose I/O
TTL bidirectional buffer, 3.3 V capable, 8mA,
3.3 V tolerant,
PU
(1)
1.
When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
Table 9.
Group Direction Function Pin Type
ADC
ADC pins
Signal name
AIN_0
AIN_1
AIN_2
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
ADC_VREFN
ADC_VREP
Ball
W11
V11
V12
W12
W13
V13
V14
W14
W15
V15
Input
ADC analog input channel
ADC negative voltage
ADC positive voltage
Analog buffer,
2.5 V tolerant
Doc ID 16259 Rev 3 31/97
Pin description SPEAr600
Table 10.
NAND Flash I/F pins
Group Signal name Ball Direction Function Pin Type
NF_IO_0
NF_IO_1
NF_IO_2
NF_IO_3
NF_IO_4
NF_IO_5
NF_IO_6
H19
H18
G19
G18
F19
F18
E18
I/O Data
TTL bidirectional buffer,
3.3 V capable,
4 mA,
3.3 V tolerant,
PU
(1)
NAND
FLASH
I/F
NF_IO_7
NF_CE
NF_RE
NF_WE
E19
G20
G22
H20
Chip enable
Read enable
Write enable
TTL output buffer,
3.3 V capable,
4 mA, active low
NF_ALE
NF_CLE
H21
G21
Output Address latch enable
Command latch enable
Write protect
TTL output buffer,
3.3 V capable,
4 mA
NF_WP J18
NF_RB H22 Input Read/busy
TTL input buffer
3.3 V tolerant, PU
1.
When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
32/97 Doc ID 16259 Rev 3
SPEAr600
Table 11.
DDR I/F pins
Group Signal name
DDR
I/F
DDR_ADD_0
DDR_ADD_1
DDR_ADD_2
DDR_ADD_3
DDR_ADD_4
DDR_ADD_5
DDR_ADD_6
DDR_ADD_7
DDR_ADD_8
DDR_ADD_9
DDR_ADD_10
DDR_ADD_11
DDR_ADD_12
DDR_ADD_13
DDR_ADD_14
DDR_BA_0
DDR_BA_1
DDR_BA_2
DDR_RAS
DDR_CAS
DDR_WE
DDR_CLKEN
DDR_CLK_P
DDR_CLK_N
DDR_CS_0
DDR_CS_1
DDR_ODT_0
DDR_ODT_1
DDR_DATA_0
DDR_DATA_1
DDR_DATA_2
DDR_DATA_3
DDR_DATA_4
AB9
Y8
W8
AB2
AB1
AB11
AA10
AB10
Y10
Y11
Ball
AA5
AB5
AB6
AA6
Y6
W6
W7
Y7
Y9
W9
AB3
AB4
AA4
Y4
W4
W5
Y5
W10
AB7
AA7
AA8
AB8
AA9
Direction Function
Output
Address line
Pin description
Pin type
SSTL_2/
SSTTL_18
Output
Output
Output
Output
Output
Bank select
Row strobe
Column strobe
Write enable
Clock enable
Differential
Clock
Chip select
Chip select
On-die
Termination
Enable lines
Differential
SSTL_2/
SSTTL_18
SSTL_2/
SSTTL_18
I/O
Data lines
(lower byte)
Doc ID 16259 Rev 3 33/97
Pin description
Table 11.
DDR I/F pins (continued)
Group Signal name Ball
DDR_DATA_5
DDR_DATA_6
DDR_DATA_7
DDR_DQS_0
Y12
AB12
AA12
AB13
DDR_nDQS_0 AA13
DDR
I/F
DDR_DM_0
DDR_GATE_0
DDR_DATA_8
DDR_DATA_9
DDR_DATA_10
DDR_DATA_11
DDR_DATA_12
DDR_DATA_13
DDR_DATA_14
DDR_DATA_15
DDR_DQS_1
AA11
Y13
AB15
AA16
AB16
Y16
Y15
Y14
AB14
AA14
AB17
DDR_nDQS_1
DDR_DM_1
DDR_GATE_1
DDR_VREF
DDR_COMP_2V5
DDR_COMP_GN
D
AA17
AA15
Y17
V10
V9
V8
DDR_COMP_1V8 V7
DDR2_EN D11
SPEAr600
Direction Function Pin type
Data lines
(Lower byte)
I/O
Output
I/O
Differential lower
Data Strobe
Lower data mask
Lower gate open
SSTL_2
/SSTTL_18
Differential
SSTL_2/
SSTTL_18
I/O
Data lines
(Upper byte)
SSTL_2/
SSTTL_18
I/O
Output
I/O
Input
Ref
-
Ref
Input
Differential upper
Differential
Data strobe
SSTL_2/
SSTTL_18
Upper data mask
Upper gate open
Ref. voltage
SSTL_2/
SSTTL_18
Ext. ref resistor
Analog
Analog, see
Common return for Ext. resistors
Power
Ext. ref. resistor
Configuration
Analog, see
TTL input buffer,
3.3 V tolerant, PU
34/97 Doc ID 16259 Rev 3
SPEAr600
Table 12.
LCD I/F pins
Group Signal name
LCD I/F
CLD_7
CLD_8
CLD_9
CLD_10
CLD_11
CLD_12
CLD_13
CLD_14
CLD_15
CLD_16
CLD_0
CLD_1
CLD_2
CLD_3
CLD_4
CLD_5
CLD_6
CLD_17
CLD_18
CLD_19
CLD_20
CLD_21
CLD_22
CLD_23
CLAC
CLCP
CLFP
CLLP
CLLE
CLPOWER
Pin description
Ball
V21
V22
U22
U21
U20
T20
T21
R21
R20
P19
Y20
Y21
Y22
W22
W21
W20
V20
P20
P21
N21
N20
N19
M20
M21
T22
R22
P22
N22
M22
M19
Direction Function
Output
LCD Data
STN AC bias drive TFT Data
Enable
LCD Panel
Clock
STN Frame
Pulse\TFT
Vertical Sync
STN Line
Pulse\TFT
Horizontal Sync
Line End
LCD Power
Enable
Pin Type
TTL output buffer,
3.3 V capable,
8 mA
Doc ID 16259 Rev 3 35/97
Pin description
Table 1 3 .
LVDS I/F pins
Group Signal name
LVDS I/F
PH3n
PH4
PH4n
PH5
PH5n
PH6
PH6n
PH0
PH0n
PH1
PH1n
PH2
PH2n
PH3
PH7
PH7n
PH8
PH8n
Ball
B14
C14
C13
A13
B13
A12
B12
C12
C11
A11
B11
A16
B16
C16
C15
A15
B15
A14
Direction Function
Input
SPEAr600
Pin Type
Output General purpose I/O
With LVDS transceiver
LVDS Driver
LVDS Receiver
36/97 Doc ID 16259 Rev 3
SPEAr600 Pin description
Table 14.
EXPI/I2S pins
Group Signal name Ball Direction Function Pin Type
PL_GPIO_47/
ADO_REC_DIN
PL_GPIO_48/
ADO_REC_WS
PL_GPIO_50/
ADO_WS_OUT
PL_GPIO_51/
ADO_DOUT2
EXPI/I2S
PL_GPIO_52/
ADO_DOUT1
PL_GPIO_53/
ADO_CLK_in_529
PL_GPIO_54/
MCLK_out_309
PL_GPIO_55/
ADO_RECORD_CLK
C2
C1
A1
B2
A2
C3
B3
A3
I/O Logic I/O
TTL bidirectional buffer
3.3 V capable,
3.3 V tolerant,
4 mA,
PU
(1)
PL_CLK_4/
ADO_CLK_OUT
A4 Output
Logic External
Clock
TTL bidirectional buffer, 3.3 V capable, 8 mA,
3.3 V tolerant,
PU
1.
When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
Doc ID 16259 Rev 3 37/97
Pin description
Table 15.
EXPI pins
Group Signal name
EXPI
PL_GPIO_17
PL_GPIO_18
PL_GPIO_19
PL_GPIO_20
PL_GPIO_21
PL_GPIO_22
PL_GPIO_23
PL_GPIO_24
PL_GPIO_25
PL_GPIO_26
PL_GPIO_27
PL_GPIO_28
PL_GPIO_29
PL_GPIO_30
PL_GPIO_31
PL_GPIO_0
PL_GPIO_1
PL_GPIO_2
PL_GPIO_3
PL_GPIO_4
PL_GPIO_5
PL_GPIO_6
PL_GPIO_7
PL_GPIO_8
PL_GPIO_9
PL_GPIO_10
PL_GPIO_11
PL_GPIO_12
PL_GPIO_13
PL_GPIO_14
PL_GPIO_15
PL_GPIO_16
SPEAr600
Ball
J4
J5
H5
H4
H3
H2
H1
G1
G2
K3
K2
K1
J1
J2
J3
L3
L4
L5
M2
M1
L1
L2
K6
K5
K4
N6
M5
M4
M3
P4
N4
N5
Direction Function
I/O Logic I/O
Pin Type
TTL bidirectional buffer
3.3 V capable,
3.3 V tolerant,
4 mA,
PU
(1)
38/97 Doc ID 16259 Rev 3
SPEAr600
Table 15.
EXPI pins (continued)
Group Signal name Ball
EXPI
PL_GPIO_32
PL_GPIO_33
PL_GPIO_34
PL_GPIO_35
PL_GPIO_36
PL_GPIO_37
PL_GPIO_38
PL_GPIO_39
PL_GPIO_40
PL_GPIO_41
PL_GPIO_42
PL_GPIO_43
PL_GPIO_44
PL_GPIO_45
PL_GPIO_46
PL_GPIO_49
PL_GPIO_56
PL_GPIO_57
PL_GPIO_58
PL_GPIO_59
PL_GPIO_60
PL_GPIO_61
PL_GPIO_62
PL_GPIO_63
B1
B4
C4
D4
E5
D5
C5
B5
B6
F1
E4
E3
E2
E1
D3
D2
D1
F5
F4
F3
F2
G3
G4
G5
Direction Function Pin Type
I/O
Pin description
Logic I/O
TTL bidirectional buffer
3.3 V capable,
4 mA,
3.3 V tolerant,
PU
Doc ID 16259 Rev 3 39/97
Pin description SPEAr600
Table 15.
EXPI pins (continued)
Group Signal name Ball Direction Function Pin Type
EXPI
PL_GPIO_64
PL_GPIO_65
PL_GPIO_66
PL_GPIO_67
PL_GPIO_68
PL_GPIO_69
PL_GPIO_70
PL_GPIO_71
PL_GPIO_72
PL_GPIO_73
PL_GPIO_74
PL_GPIO_75
PL_GPIO_76
PL_GPIO_77
PL_GPIO_78
C6
D6
E6
F6
F7
E7
D7
C7
B7
E8
D8
C8
B8
A8
C9
I/O
Logic I/O
TTL bidirectional buffer
3.3 V capable,
3.3 V tolerant,
4 mA,
PU
PL_GPIO_79
PL_GPIO_80
PL_GPIO_81
D9
E9
E10
PL_GPIO_82
PL_GPIO_83
PL_CLK_1
D10
C10
A7
PL_CLK_2
PL_CLK_3
A6
A5
Logic External
Clock
TTL bidirectional buffer, 3.3 V capable, 8 mA,
3.3 V tolerant,
PU
1.
When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed
40/97 Doc ID 16259 Rev 3
SPEAr600 Pin description
3
.
3
Configuration
The previous tables show the connectivity of the pins in the default configuration mode (full features). On top of this SPEAr600 can be also configured in different modes.
This section describes the main operating modes created by disabling some IPs to enable other ones.
●
●
●
●
●
●
●
●
The following modes can be selected by setting the TEST_0 .. TEST_5 pins at the appropriate values. This setting is used to program the control register (SOC_CFG_CTR) present in the Miscellaneous registers block (MISC). Please refer to the section 11.4.3 of the
SPEAr600 reference manual (RM0305)
Mode 0: Full features
Mode 1: Disable_nand_flash
Mode 2: Disable_LCD_ctr
Mode 3: Disable_GMAC_ctr
Mode 4: self_cfg4
Mode 5: self_cfg5
Mode6: Full RAS
Mode7: All_Process_disable
Table 16: Multiplexing s cheme shows all the alternate functions available in each mode.
Mode 0 is the default mode for SPEAr600.
3 .
3 .1 Full
Default configuration, I/O standard features.
3 .
3 .2 Disable NAND Flash
The NAND Flash interface is disabled and alternatively the following features are provided:
●
●
UART extension for modem flow control
One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user manual for more details).
3 .
3 .
3 Disable ctr
●
●
●
●
The Color LCD controller interface is disabled and alternatively the following features are provided:
UART extension for modem flow control
One additional clock programmable trought GPT registers. Please refer to the
SPEAr600 user manual (UM0510) for more details.
Additional 8 data lines of NAND Flash interface not otherwise available.
One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user manual for more details).
Doc ID 16259 Rev 3 41/97
Pin description SPEAr600
3 .
3 .4 Disable ctr
The GMAC interface is disabled and alternatively the following features are provided:
● Two UARTs : one with extension for modem flow control and one with simplified hardware flow control
● One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user manual for more details).
● Four additional clocks programmable trough the GPT registers. Please refer to the
SPEAr600 user manual (UM0510) for more details.
3 .
3 .5 Self
In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this mode source clock and reset signals are provided from the external application logic.
3 .
3 .6 Self
In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this mode source clock and reset signals are internally provided.
3 .
3 .7 All processors disabled
This mode configures the SoC as an I/O slave target device controlled by an external master application (the internal processors can be disabled).
42/97 Doc ID 16259 Rev 3
Table 16.
Multiplexing scheme
Ball Mode 0 Mode 1
U19
T19
R19
R18
AB18
AA18
AB19
AA19
AB20
AA20
Y18
Y19
U18
T18
W19
V19
W15
V15
W18
V18
W13
V13
V14
W14
W11
V11
V12
W12
EXPI_6
EXPI_7
EXPI_8
EXPI_9
FIRDA_RXD
FIRDA_TXD
UART1_RXD
UART1_TXD
UART2_RXD
UART2_TXD
SDA
SCL
AIN_0
AIN_1
AIN_2
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
ADC_VREFN
ADC_VREFP
EXPI_0
EXPI_1
EXPI_2
EXPI_3
EXPI_4
EXPI_5
Mode 2 Mode 3 Mode 4
EXPI_6
EXPI_7
EXPI_8
EXPI_9
FIRDA_RXD
FIRDA_TXD
UART1_RXD
UART1_TXD
UART2_RXD
UART2_TXD
SDA
SCL
AIN_0
AIN_1
AIN_2
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
ADC_VREFN
ADC_VREFP
EXPI_0
EXPI_1
EXPI_2
EXPI_3
EXPI_4
EXPI_5
Mode 5
EXPI_6
EXPI_7
EXPI_8
EXPI_9
FIRDA_RXD
FIRDA_TXD
UART1_RXD
UART1_TXD
UART2_RXD
UART2_TXD
SDA
SCL
AIN_0
AIN_1
AIN_2
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
ADC_VREFN
ADC_VREFP
EXPI_0
EXPI_1
EXPI_2
EXPI_3
EXPI_4
EXPI_5
Full RAS Mode 7
EXPI_6
EXPI_7
EXPI_8
EXPI_9
FIRDA_RXD
FIRDA_TXD
UART1_RXD
UART1_TXD
UART2_RXD
UART2_TXD
SDA
SCL
AIN_0
AIN_1
AIN_2
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
ADC_VREFN
ADC_VREFP
EXPI_0
EXPI_1
EXPI_2
EXPI_3
EXPI_4
EXPI_5
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
V22
U22
U21
U20
W21
W20
V20
V21
Y20
Y21
Y22
W22
AB22
AB21
AA21
AA22
P19
P20
P21
N21
N20
T20
T21
R21
R20
CLD_12
CLD_13
CLD_14
CLD_15
CLD_16
CLD_17
CLD_18
CLD_19
CLD_20
CLD_4
CLD_5
CLD_6
CLD_7
CLD_8
CLD_9
CLD_10
CLD_11
SSP_1_SCLK
SSP_1_MISO
SSP_1_MOSI
SSP_1_SS
CLD_0
CLD_1
CLD_2
CLD_3
N19
M20
M21
CLD_21
CLD_22
CLD_23
Mode 2
GPIO_basic[7]
GPIO_basic[6]
GPIO_basic[5]
GPIO_basic[4]
GPIO_basic[3]
GPIO_basic[2]
GPIO_ARM1[7]
GPIO_ARM2[7] nUART1RTS nUART1CTS nUART1DCD nUART1DTR nUART1DSR nUART1RI
SMICS_OUT_3
GPIO_ARM1[6]
GPIO_ARM1[5]
GPIO_ARM1[4]
GPIO_ARM2[6]
GPIO_ARM2[5]
GPIO_ARM2[4]
Tmr1_app_MT_INT
1_CLK
NFIO_15_o
NFIO_14_o
Mode 3 Mode 4
CLD_12
CLD_13
CLD_14
CLD_15
CLD_16
CLD_17
CLD_18
CLD_19
CLD_20
CLD_4
CLD_5
CLD_6
CLD_7
CLD_8
CLD_9
CLD_10
CLD_11
SSP_1_SCLK
SSP_1_MISO
SSP_1_MOSI
SSP_1_SS
CLD_0
CLD_1
CLD_2
CLD_3
CLD_21
CLD_22
CLD_23
Mode 5
CLD_12
CLD_13
CLD_14
CLD_15
CLD_16
CLD_17
CLD_18
CLD_19
CLD_20
CLD_4
CLD_5
CLD_6
CLD_7
CLD_8
CLD_9
CLD_10
CLD_11
SSP_1_SCLK
SSP_1_MISO
SSP_1_MOSI
SSP_1_SS
CLD_0
CLD_1
CLD_2
CLD_3
CLD_21
CLD_22
CLD_23
Full RAS Mode 7
CLD_12
CLD_13
CLD_14
CLD_15
CLD_16
CLD_17
CLD_18
CLD_19
CLD_20
CLD_4
CLD_5
CLD_6
CLD_7
CLD_8
CLD_9
CLD_10
CLD_11
SSP_1_SCLK
SSP_1_MISO
SSP_1_MOSI
SSP_1_SS
CLD_0
CLD_1
CLD_2
CLD_3
CLD_21
CLD_22
CLD_23
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
H19
H18
G19
G18
J22
J21
J20
J19
F19
F18
E18
E19
K21
K20
K18
K19
L22
L19
L18
K22
N22
M19
L21
L20
T22
R22
P22
M22
SSP_3_SCLK
SSP_3_MISO
SSP_3_MOSI
SSP_3_SS
NF_IO_0
NF_IO_1
NF_IO_2
NF_IO_3
NF_IO_4
NF_IO_5
NF_IO_6
NF_IO_7
CLAC
CLCP
CLFP
CLLE
CLLP
CLPOWER
SMI_DATAIN
SMI_DATAOUT
SMI_CLK
SMI_CS_0
SMI_CS_1
SSP_2_SCLK
SSP_2_MISO
SSP_2_MOSI
BOOT_SEL
SSP_2_SS_0
GPIO_basic[7]
GPIO_basic[6]
GPIO_basic[5]
GPIO_basic[4]
GPIO_basic[3]
GPIO_basic[2]
GPIO_ARM1[7]
GPIO_ARM2[7]
Mode 2
NFIO_13_o
NFIO_12_o
NFIO_11_o
NFIO_10_o
NFIO_9_o
NFIO_8_o
Mode 3 Mode 4
CLAC
CLCP
CLFP
CLLE
CLLP
CLPOWER
SMI_DATAIN
SMI_DATAOUT
SMI_CLK
SMI_CS_0
SMI_CS_1
SSP_2_SCLK
SSP_2_MISO
SSP_2_MOSI
SSP_2_SS_0
SSP_3_SCLK
SSP_3_MISO
SSP_3_MOSI
SSP_3_SS
NF_IO_0
NF_IO_1
NF_IO_2
NF_IO_3
NF_IO_4
NF_IO_5
NF_IO_6
NF_IO_7
Mode 5
CLAC
CLCP
CLFP
CLLE
CLLP
CLPOWER
SMI_DATAIN
SMI_DATAOUT
SMI_CLK
SMI_CS_0
SMI_CS_1
SSP_2_SCLK
SSP_2_MISO
SSP_2_MOSI
SSP_2_SS_0
SSP_3_SCLK
SSP_3_MISO
SSP_3_MOSI
SSP_3_SS
NF_IO_0
NF_IO_1
NF_IO_2
NF_IO_3
NF_IO_4
NF_IO_5
NF_IO_6
NF_IO_7
Full RAS Mode 7
CLAC
CLCP
CLFP
CLLE
CLLP
CLPOWER
SMI_DATAIN
SMI_DATAOUT
SMI_CLK
SMI_CS_0
SMI_CS_1
SSP_2_SCLK
SSP_2_MISO
SSP_2_MOSI
SSP_2_SS_0
SSP_3_SCLK
SSP_3_MISO
SSP_3_MOSI
SSP_3_SS
NF_IO_0
NF_IO_1
NF_IO_2
NF_IO_3
NF_IO_4
NF_IO_5
NF_IO_6
NF_IO_7
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
E21
F20
E20
D21
E22
F22
D22
F21
D14/TEST_2
D13/TEST_3
E13/TEST_4
D12/TEST_5
G21
H22
J18
C17
G20
H20
G22
H21
D11
D17
E16
D15
D16
E17
E15/TEST_0
E14/TEST_1
0
0
TDI
TDO
DDR2_EN nTRST
TCK
TMS
NF_CE
NF_WE
NF_RE
NF_ALE
NF_CLE
NF_RB
NF_WP
MRESET
0
0
0
0
GMII_TXCLK125
GMII_TXCLK
MII_TXCLK
TXD_0
TXD_1
TXD_2
TXD_3
GMII_TXD_4
0
1
0
0
0
0 nUART1RTS nUART1CTS nUART1DCD nUART1DTR nUART1DSR nUART1RI
SMICS_OUT_3
0
0
0
0
1
0
Mode 2
0
1
0
0
1
0
Mode 3
GPIO_basic[7]
GPIO_basic[6]
GPIO_basic[5]
GPIO_basic[4]
GPIO_basic[3]
GPIO_basic[2]
GPIO_ARM1[7]
Mode 4
0
0
TDI
TDO
DDR2_EN nTRST
TCK
TMS
NF_CE
NF_WE
NF_RE
NF_ALE
NF_CLE
NF_RB
NF_WP
MRESET
0
1
0
0
GMII_TXCLK125
GMII_TXCLK
MII_TXCLK
TXD_0
TXD_1
TXD_2
TXD_3
GMII_TXD_4
Mode 5
0
0
TDI
TDO
DDR2_EN nTRST
TCK
TMS
NF_CE
NF_WE
NF_RE
NF_ALE
NF_CLE
NF_RB
NF_WP
MRESET
0
1
0
1
GMII_TXCLK125
GMII_TXCLK
MII_TXCLK
TXD_0
TXD_1
TXD_2
TXD_3
GMII_TXD_4
0
0
0
0
1
1
Full RAS Mode 7
0
0
TDI
TDO
DDR2_EN nTRST
TCK
TMS
NF_CE
NF_WE
NF_RE
NF_ALE
NF_CLE
NF_RB
NF_WP
MRESET
1
1
1
0
GMII_TXCLK125
GMII_TXCLK
MII_TXCLK
TXD_0
TXD_1
TXD_2
TXD_3
GMII_TXD_4
A17
B17
B16
C16
C15
A15
C18
B18
E11
A16
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
B22
B21
A21
B20
A20
B19
D18
A22
C19
C20
D20
C22
C21
D19
GMII_TXD_5
GMII_TXD_6
GMII_TXD_7
TX_EN
TX_ER
RX_CLK
RX_DV
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
GMII_RXD_4
GMII_RXD_5
Mode 2
A18 GMII_RXD_6
A19 GMII_RXD_7
COL
CRS
MDC
MDIO
DIGITAL_REXT
PH0
PH0n
PH1
PH1n
PH2
Mode 3 Mode 4
GPIO_ARM2[7] nUART1RTS nUART1CTS nUART1DCD nUART1DTR nUART1DSR nUART1RI
SMICS_OUT_3
GMII_TXD_5
GMII_TXD_6
GMII_TXD_7
TX_EN
TX_ER
RX_CLK
RX_DV
RX_ER
GPIO_ARM1[6]
GPIO_ARM1[5]
GPIO_ARM1[4]
GPIO_ARM2[6]
RXD_0
RXD_1
RXD_2
RXD_3
GPIO_ARM2[5]
GPIO_ARM2[4]
GMII_RXD_4
GMII_RXD_5
Tmr1_app_MT_INT
1_CLK
GMII_RXD_6
Tmr1_app_MT_INT
2_CLK
GMII_RXD_7
Tmr2_app_MT_INT
1_CLK
COL
Tmr2_app_MT_INT
2_CLK
CRS nUART2RTS nUART2CTS
MDC
MDIO
DIGITAL_REXT
PH0
PH0n
PH1
PH1n
PH2
Mode 5
GMII_TXD_5
GMII_TXD_6
GMII_TXD_7
TX_EN
TX_ER
RX_CLK
RX_DV
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
GMII_RXD_4
GMII_RXD_5
GMII_RXD_6
GMII_RXD_7
COL
CRS
MDC
MDIO
DIGITAL_REXT
PH0
PH0n
PH1
PH1n
PH2
Full RAS Mode 7
GMII_TXD_5
GMII_TXD_6
GMII_TXD_7
TX_EN
TX_ER
RX_CLK
RX_DV
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
GMII_RXD_4
GMII_RXD_5
GMII_RXD_6
GMII_RXD_7
COL
CRS
MDC
MDIO
DIGITAL_REXT
PH0
PH0n
PH1
PH1n
PH2
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
D10
E10
E9
D9
A6
A5
A4
C10
C9
A8
B8
C8
B11
B9
A9
A7
B12
C12
C11
A11
C13
A13
B13
A12
B15
A14
B14
C14
PH6n
PH7
PH7n
PH8
PH8n
RTC_XO
RTC_XI
PH2n
PH3
PH3n
PH4
PH4n
PH5
PH5n
PH6
Mode 2 Mode 3 Mode 4
PH6n
PH7
PH7n
PH8
PH8n
RTC_XO
RTC_XI
PH2n
PH3
PH3n
PH4
PH4n
PH5
PH5n
PH6
Mode 5
PH6n
PH7
PH7n
PH8
PH8n
RTC_XO
RTC_XI
PH2n
PH3
PH3n
PH4
PH4n
PH5
PH5n
PH6
Full RAS Mode 7
PH6n
PH7
PH7n
PH8
PH8n
RTC_XO
RTC_XI
PH2n
PH3
PH3n
PH4
PH4n
PH5
PH5n
PH6
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
B3
C3
A2
B2
D4
C4
B4
A3
A1
B1
C1
C2
B5
C5
D5
E5
E6
D6
C6
B6
D7
E7
F7
F6
D8
E8
B7
C7
Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
H4
H5
J5
J4
G1
H1
H2
H3
J3
J2
J1
K1
G5
G4
G3
G2
F2
F3
F4
F5
E2
E3
E4
F1
D1
D2
D3
E1
Mode 2 Mode 3 Mode 4 Mode 5 Full RAS Mode 7
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
P5
R5
P6
R6
N5
N4
P4
R4
P1
P2
T1
T2
M3
M4
M5
N6
L2
L1
M1
M2
K6
L5
L4
L3
K2
K3
K4
K5
USB_DEV_VBUS
USB_HOST1_VBUS
USB_HOST2_VBUS
USB_HOST1_OVRC
USB_HOST2_OVRC
USB_HOST2_DP
USB_HOST2_DM
USB_HOST1_DP
USB_HOST1_DM
Mode 2 Mode 3 Mode 4 Mode 5 Full RAS
USB_DEV_VBUS USB_DEV_VBUS
USB_HOST1_VBUS USB_HOST1_VBUS
USB_HOST2_VBUS USB_HOST2_VBUS
USB_HOST1_OVRC USB_HOST1_OVRC
USB_HOST2_OVRC USB_HOST2_OVRC
USB_HOST2_DP
USB_HOST2_DM
USB_HOST2_DP
USB_HOST2_DM
USB_HOST1_DP
USB_HOST1_DM
USB_HOST1_DP
USB_HOST1_DM
Mode 7
USB_DEV_VBUS
USB_HOST1_VBUS
USB_HOST2_VBUS
USB_HOST1_OVRC
USB_HOST2_OVRC
USB_HOST2_DP
USB_HOST2_DM
USB_HOST1_DP
USB_HOST1_DM
Table 16.
Multiplexing scheme (continued)
Ball Mode 0 Mode 1
V1
V2
U4
Y2
Y1
USB_DEV_DP
USB_DEV_DM
USB_USB_RREF
MCLK_XO
MCLK_XI
Mode 2 Mode 3
Table 17.
Table shading
Shading
GPIO
UART
SMI
GPT
TEST
Pin group
GPIO pins
UART pins
SMI pins
GPT pins
Test mode configuration pins
Mode 4
USB_DEV_DP
USB_DEV_DM
USB_USB_RREF
MCLK_XO
MCLK_XI
Mode 5
USB_DEV_DP
USB_DEV_DM
USB_USB_RREF
MCLK_XO
MCLK_XI
Shading
FSMC
Full RAS Mode 7
USB_DEV_DP
USB_DEV_DM
USB_USB_RREF
MCLK_XO
MCLK_XI
FSMC pins
Pin group
SPEAr600 Memory map
Table 18.
Memory map
Start address End address
0x0000.0000
0x4000.0000
0x4000.0800
0x4000.0821
0x3FFF.FFFF
0x4000.07FF
0x4000.0820
0xBFF.FFFF
0xD280.0000
0xD300.0000
0xD800.0000
0xD808.0000
0xD810.0000
0xD818.0000
0xD820.0000
0xD828.0000
0xE000.0000
0xE080.0000
0xE100.0000
0xE110.0000
0xE120.0000
0xE130.0000
0xE180.0000
0xC000.0000
0xCFFF.F800
0xD000.0000
0xD008.0000
0xD010.0000
0xD018.0000
0xD020.0000
0xD028.0000
0xD080.0000
0xD100.0000
0xD180.0000
0xD200.0000
0xD2FF.FFFF
0xD7FF.FFFF
0xD807.FFFF
0xD80F.FFFF
0xD817.FFFF
0xD81F.FFFF
0xD827.FFFF
0xDFFF.FFFF
0xE07F.FFFF
0xE0FF.FFFF
0xE10F.FFFF
0xE11F.FFFF
0xE12F.FFFF
0xE17F.FFFF
0xE18F.FFFF
0xCFFF.F7FF
0xCFFF.FFFF
0xD007.FFFF
0xD00F.FFFF
0xD017.FFFF
0xD01F.FFFF
0xD027.FFFF
0xD07F.FFFF
0xD0FF.FFFF
0xD17F.FFFF
0xD1FF.FFFF
0xD27F.FFFF
Peripheral
External DRAM
R.F.U
I2S
R.F.U
AHB_EH2H expansion interface
AHB_EH2H registers
UART 1
UART 2
SSP 1
SSP 2
I2C
-
JPEG Codec
Fast IrDA
FSMC
SRAM
-
Timer 1
Timer 2
GPIO
SSP 3
ADC
-
-
Ethernet controller
USB 2.0 device
USB 2.0 device
USB 2.0 device
-
USB2.0 EHCI 1
Description
DDR1 or DDR2
Reserved
I2S dual port memory
Reserved
Reserved
NAND Flash memory
Static RAM shared memory
(8 Kbytes)
Reserved
Reserved
Reserved
GMAC
FIFO
Configuration registers
Plug detect
Reserved
Doc ID 16259 Rev 3 53/97
Memory map
Table 18.
Memory map (continued)
Start address End address Peripheral
0xE190.0000
0xE1A0.0000
0xE200.0000
0xE210.0000
0xE220.0000
0xE280.0000
0xE290.0000
0xE800.0000
0xF000.0000
0xF010.0000
0xF020.0000
0xF100.0000
0xF110.0000
0xF120.0000
0xF800.0000
0xFC00.0000
0xFC20.0000
0xFC40.0000
0xFC60.0000
0xFC80.0000
0xFC88.0000
0xFC90.0000
0xFC98.0000
0xFCA0.0000
0xFCA8.0000
0xFCB0.0000
0xFF00.0000
0xE19F.FFFF
0xE1FF.FFFF
0xE20F.FFFF
0xE21F.FFFF
0xE27F.FFFF
0xE28F.FFFF
0xE7FF.FFFF
0xEFFF.FFFF
0xF00F.FFFF
0xF01F.FFFF
0xF0FF.FFFF
0xF10F.FFFF
0xF11F.FFFF
0xF7FF.FFFF
0xFBFF.FFFF
0xFC1F.FFFF
0xFC3F.FFFF
0xFC5F.FFFF
0xFC7F.FFFF
0xFC87.FFFF
0xFC8F.FFFF
0xFC97.FFFF
0xFC9F.FFFF
0xFCA7.FFFF
0xFCAF.FFFF
0xFEFF.FFFF
0xFFFF.FFFF
USB2.0 OHCI 1
-
USB2.0 EHCI 2
USB2.0 OHCI 1
-
USB AHB-Master Layer arbiter
-
-
Timer
GPIO
-
ITC Secondary
ITC Primary
-
Serial Flash Memory
Serial Flash Controller
LCD Controller
DMA Controller
SDRAM Controller
Timer 1
Watchdog Timer
Real time Clock
General Purpose I/O
System Controller
Miscellaneous Registers
-
Internal ROM
Description
Reserved
Reserved
Reserved
Reserved
Boot
SPEAr600
Reserved
Configuration register
Reserved
Reserved
54/97 Doc ID 16259 Rev 3
SPEAr600 Electrical characteristics
5.1
5.2
Note:
Absolute maximum ratings
This product contains devices to protect the inputs against damage due to high/low static voltages. However it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages.
The Absolute maximum rating is the maximum stress that can be applied to a device without causing permanent damage. However, extended exposure to minimum/maximum ratings may affect long-term device reliability.
Table 19.
Absolute maximum ratings
Symbol Parameter
V
DD
1.0
V
DD
3.3
V
DD
2.5
V
DD
1.8
T
STG
T
J
Supply voltage at 1.0
Supply voltage at 3.3
Supply voltage at 2.5
Supply voltage at 1.8
Storage temperature
Junction temperature
Minimum value Maximum value
- 0.3
- 0.3
- 0.3
- 0.3
-55
-40
1.2
3.9
3
2.16
150
125
Unit
V
V
V
V
°C
°C
Maximum power consumption
The following table includes the maximum current and power consumption for each power domain.
The s e value s take into con s ideration the wor s t ca s e s of proce ss variation and voltage range and mu s t be u s ed to de s ign the power s upply s ection of the board.
Table 20.
Maximum current and power consumption
Symbol Description Max Unit
V
DD
1.0
V
DD
1.8
V
DD
2.5
V
DD
3.3
Supply voltage at 1.0 V
Supply voltage at 1.8 V
Supply voltage at 2.5 V
Supply voltage at 3.3 V
(1)
(2)
1000
130
22
60 mA mA mA mA
V
DD
RTC Supply voltage at 1.8 V 10 µA
P
D
Maximum power consumption 1500
(3)
1.
Average current with Linux memory test [50% write and 50% read] plus DMA reading memory.
2.
With 30 logic channels connected to the device and simultaneously switching at 10 MHz.
mW
Doc ID 16259 Rev 3 55/97
Electrical characteristics
5.
3
SPEAr600
3.
The maximum current and power values listed above, obtained with typical supply voltages, are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different results.
1 V current and power are primarily dependent on the applications that are running and the use of internal chip functions (DMA, USB, Ethernet, and so on).
3.3 V current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
DC electrical characteristics
The recommended operating conditions are listed in the following table:
Table 21.
Recommended operating conditions
Symbol Parameter
Supply voltage at 1.0
V
DD
1.0
V
DD
3.3
V
DD
2.5
V
DD
1.8
V
DD
RTC
T
A
T
J
Supply voltage at 3.3
Supply voltage at 2.5
Supply voltage at 1.8
Supply voltage at 1.8
Ambient temperature
Junction temperature
1.70
1.62
-40
-40
Min
0.95
3
2.25
Typ
1
3.3
2.5
1.8
1.8
1.9
1.98
85
125
Max
1.10
3.6
2.75
°C
°C
V
V
Unit
V
V
V
5.4 Overshoot undershoot
This product can support the following values of overshoot and undershoot.
Table 22.
Overshoot and undershoot specifications
Parameter 3 V 3 I/Os 2V5 I/Os 1V8 I/Os
500 mV 500 mV 500 mV Amplitude
Ratio of overshoot (or undershoot) duration with respect to pulse width
1/3 1/3 1/3
Note:
If the amplitude of the overshoot/undershoot increases (decreases), the ratio of overshoot/undershoot width to the pulse width decreases (increases). The formula relating the two is:
Amplitude of OS/US = 0.75*(1- ratio of OS (or US) duration with respect to pulse width)
The value of over s hoot/under s hoot s hould not exceed the value of 0.5 V. However, the duration of the over s hoot/under s hoot can be increa s ed by decrea s ing it s amplitude.
56/97 Doc ID 16259 Rev 3
SPEAr600
5.5
Electrical characteristics
3
.
3
V I/O characteristics
The 3.3 V I/Os are compliant with JEDEC standard JESD8b
Table 2 3 .
Low voltage TTL DC input specification ( 3 V< V
DD
< 3 .6 V)
Symbol Parameter Min Max
0.8
V
IL
V
IH
Vhyst
Low level input voltage
High level input voltage
Schmitt trigger hysteresis
2
300 800
Unit
V
V mV
Table 24.
Low voltage TTL DC output specification ( 3 V< V
DD
< 3 .6 V)
Symbol Parameter Test Condition Min Max
V
V
OL
OH
Low level output voltage
High level output voltage
I
OL
= X mA
(1)
I
OH
= -X mA
1.
For the max current value (X mA) refer to Section 3: Pin de s cription
.
V
DD
- 0.3
0.3
Table 25.
Pull-up and pull-down characteristics
Symbol Parameter Test Condition
R
PU
R
PD
Equivalent pull-up resistance
Equivalent pull-down resistance
V
I
= 0 V
V
I
= V
DDE
3V3
Min.
29
29
Max
67
103
Unit
V
V
Unit
K
Ω
K
Ω
Table 26.
DC characteristics
Symbol Parameter
V
IL
V
IH
Low level input voltage
High level input voltage
Test Condition
SSTL2
SSTL18
SSTL2
SSTL18
V hyst
Input voltage hysteresis
Min.
Max
-0.3
-0.3
V
REF
+0.15
V
DDE
2V5+0.3
V
REF
+0.125
V
DDE
1V8+0.3
200
V
REF
-0.15
V
REF
-0.125
Unit
V
V
V
V mV
Table 27.
Driver characteristics
Symbol Parameter
Output impedance (strong value)
R
O
Output impendance (weak value)
Min
18.9
Typ
21
32.9
35
Max Unit
23.1
Ω
37.1
Ω
Doc ID 16259 Rev 3 57/97
Electrical characteristics
Table 28.
On die termination
Symbol Parameter
RT1*
Termination value of resistance for on die termination
RT2*
Termination value of resistance for on die termination
Min.
Typ.
75
150
SPEAr600
Max Unit
Ω
Ω
Table 29.
Reference voltage
Symbol Parameter
V
REFIN
Voltage applied to core/pad
Min.
0.49 *
V
DDE
Typ.
0.500 *
V
DDE
Max
0.51 *
V
DDE
Unit
V
5.8
No particular sequence is required. It is only required that the various power supplies reach the correct range in less than 10 msec.
Power on reset (MRESET)
The MRESET must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 µs when one of the power supplies goes out of the correct range.
Figure 3 .
Power on reset timing diagram
All Vdd are stable
MRESET
OSCI 30MHz resets_o sclk npor_o hresetn arm_fetching pll_lock
10 ms synch
2.95 us synch
60 clock cycles synch
17 sclk clock cycles (at 30MHz)
DOZE MODE
Pll lock time (note 2)
NORMAL
MODE
58/97 Doc ID 16259 Rev 3
SPEAr600 Electrical characteristics
Note: 1 The o s cillator generate s a s table clock 1.5 m s after the power s upply become s s table.
2 The Pll lock time i s given by the following formula:
Lock time = 4 m s / (decimal equivalent of PLL charge pump bit s etting + 1)
The PLL charge pump (CP) bit s are in the PLL1/2_CTR regi s ter in the Mi s cellaneou s regi s ter block. Plea s e refer to the u s er manual for more detail s .
For example, if the application s oftware s et s CP = 01110 = 14 (decimal), then:
Lock time = 4 m s / 15 = 267 μ s .
5.9 ADC electrical parameters
Table 3 0.
ADC characteristics
Parameters
Analog Input
Input range (absolute)
Conversion Range
Input Capacitance
Power Supply
Input Mux Resistance (Total equivalent Sampling Resistance
Analog Supply AV
DD
Digital Supply V
DD
VREFP External
Reference voltages
Clock
Frequency
VREFN
Performance parameters
INL
DNL
Gain error
Offset error
Temperature range
Current
Consumption
AV
DD
(External reference mode)
AV
DD
(Power down mode EN=0)
V
DD
(Functional mode)
V
DD
(Power down mode)
-40
0.6
0.1
Min
0-0.3
VREFN
5
1.5K
2.25
0.9
1.0
0
Typ
6.4
2K
2.5
1.0
2.5
0
3 14
± 1
Max
AV
DD
+0.3
VREFP
8
2.5K
2.8
1.1
2.8
0.7
Unit
V
V pF
Ω
V
V
V
V
MHz
LSB
25
0.8
0.15
± 2
± 2
125
1
0.4
0.2
1
LSB
LSB
°C mA
µA mA
µA
Doc ID 16259 Rev 3 59/97
Timing characteristics SPEAr600
6.1.1
The characterization timing is done considering an output load of 10 pF on all the DDR pads. The operating conditions are in worst case V = 0.90 V T
A
= 125 °C and in best case
V=1.10 V T
A
= 40 °C.
DDR2 read cycle timings
Figure 4.
DDR2 read cycle waveforms
DQS t4 t5 t4 t5 t4
DQ
Figure 5.
DDR2 read cycle path t3
DQ t1
DQS
DLL
Table 3 1.
DDR2 read cycle path timings without pad delay t 3
MAX
(t1 + t2)
MIN t 3
MIN
Rising best
Falling best
Rising worst
Falling worst
133 ps
134 ps
336 ps
348 ps
212 ps
205 ps
611 ps
550 ps
125 ps
127 ps
311 ps
324 ps t2
(t1 + t2)
MAX
244 ps
239 ps
646 ps
590 ps
Table 3 2.
DDR2 read cycle timings without pad delay
Period (T) Frequency t4
MAX
3 ns
3.75 ns
333 MHz
266 MHz
814 ps
996 ps t5
MAX
343 ps
532 ps
D SET Q
CLR
Q
60/97 Doc ID 16259 Rev 3
SPEAr600 Timing characteristics
Table 3 2.
DDR2 read cycle timings without pad delay (continued)
Period (T)
5 ns
Frequency
200 MHz t4
MAX
1.31 ns
6 ns
7.5 ns
166 MHz
133 MHz
1.56 ns
1.93 ns t5
MAX
842 ps
1.10 ns
1.47 ns
Note:
6.1.2
shows the internal chip timing without the contribution of the pads.
These values are obtained considering the nominal setting of DLL at T/4 period, in fact, the
DDR memory launches data (DQ) and data strobe (DQS) aligned. Internally the DQS is delayed by T/4 (DLL) to guarantee correct data capture.
refers to the pad or memory side: so the data move around the edges of DQS signals. In this case, we consider the maximum values for t4 and t5 to obtain the minimum data valid window. For correct data capture (at the controller side) the last arrival time of the data (last variation) must precede the first arrival of the data strobe: t4
MAX
= DQS (delay)
MIN
- DQ (delay)
MAX
= (t1
MIN
+ t2
MIN
+ T/4 ±one DLL element
t3
MAX t5 can be expressed in a similar way: t5
MAX
= DQ (delay)
MIN element
- DQS (delay)
(a)
) = T/4 + t3
MAX
= (T/2 + t3
MIN
) - (t1
MAX
+ t2
MAX
+ T/4 ± one DLL
MIN
- t1
MAX
- t2
MAX
± one DLL element
DQS (delay) i s the combination of delay s experienced by the DQS (data s trobe) s ignal, DQ
(delay) i s the combination of delay s experienced by the DQ (data) s ignal (both until the capture i s performed by the controller).
DQS (delay) depend s on t1 and t2 while DQ (delay) depend s on t3.
DDR2 write cycle timings
Figure 6.
DDR2 write cycle waveforms
DQS t4 t5 t4 t5 t4 t5
DQ a.
The value “one DLL element” stands for the DLL accuracy, so we put ± one DLL element in the formulas. One
DLL element = 15 ps in best case and 85 ps in worst case.
Doc ID 16259 Rev 3 61/97
Timing characteristics
Figure 7.
DDR2 write cycle path
CLK
D SET Q
CLR
Q t1
DLL2 t2
SPEAr600
DQS
62/97
D SET Q
CLR
Q t3 DQ
DLL1
Table 33 .
DDR2 write cycle path timings without pad delay
Rising best
Falling best t 3
MAX
2.19 ns
2.21 ns
(t1 + t2)
MIN
2.08 ns
2.11 ns t 3
MIN
1.91 ns
1.95 ns
Rising worst
Falling worst
5.55 ns
5.54 ns
5.28 ns
5.30 ns
5.2 ns
5.3 ns
(t1 + t2)
MAX
2.13 ns
2.15 ns
5.33 ns
5.35 ns
Table 3 4.
DDR2 write cycle timings without pad delay
Period (T) Frequency
3 ns
3.75 ns
5 ns
6 ns
7.5 ns
333 MHz
266 MHz
200 MHz
166 MHz
133 MHz t4
MIN
396 ps
585 ps
895 ps
1.15 ns
1.52 ns t5
MIN
492 ps
681 ps
991 ps
1.25 ns
1.62 ns
shows the internal chip timing without the contribution of the pads.
These values are obtained considering the nominal setting of DLL at T period for DQS path and T*3/4 for DQ path, in fact the memory controller launches data (DQ) and data strobe
(DQS) misaligned. Internally the clock is delayed by T to produce the DQS and the same clock is delayed by T*3/4 to clock the data DQ, in order to perform a correct write to the memory. The table values are measured in a particular pad configuration:
Drive strength = strong (zprog_out = L)
Slope : prog_a = L ; prog_b = H (corresponding to 266 MHz)
refer to the pad or memory side, so the DQS edges are centered on the data valid window. In this case, we consider the minimum values for t4 and t5 in order to obtain the minimum data valid window. For a correct data write (on the memory side) the last variation of the data must precede the first arrival of the data strobe. In other words, we can consider t4 as the t
SETUP
of the data that can be defined as the time range where the
Doc ID 16259 Rev 3
SPEAr600
Note:
6.1.
3
Timing characteristics data are stable before the arrival of the DQS. To have a positive quantity the delay obtained by the DQ (maximum delay or last variation) must be less than one obtained by the DQS
(minimum delay).
So: t4
MIN
= DQS (delay)
MIN
± one DLL element
- DQ (delay)
MAX
MAX
= (t1
) = t1
MIN
MIN
+ T ± one DLL element
+ T/4 + t2
MIN
(a)
+ t2
MIN
) - (T*3/4
- t3
MAX t5 can be expressed in a similar way, and can be defined as the t
HOLD
of the data: t5
MIN
= DQ (delay)
MIN
- DQS (delay)
(t1
MAX
+ T ± one DLL element
MAX
= (T/2 + T*3/4 ± one DLL element
MAX
) =
+ t3
MIN
) -
= T/4 + t3
MIN
- t2
MAX
- t1
MAX
± one DLL element
DQS (delay) i s the combination of delay s experienced by the DQS (data s trobe) s ignal, DQ
(delay) i s the combination of delay s experienced by the DQ (data) s ignal (both until the capture performed by the controller).
DDR2 command timings
Figure 8.
DDR2 command waveforms
CLK
ADDRESS, STROBEs, and CONTROL LINES t4 t5
Figure 9.
DDR2 command path
ADDRESS, STROBEs, and CONTROL LINES
CLK
D SET Q
CLR
Q t2
ADDRESS, STROBEs, and CONTROL LINES t3 CLK
For the command and control timings, we have to consider that the commands are launched on the negative edge of the clock and are captured on the next positive edge of the clock. a.
The value “one DLL element” stands for the DLL accuracy, so we put ± one DLL element in the formulas. One
DLL element = 15 ps in best case and 85 ps in worst case.
Doc ID 16259 Rev 3 63/97
Timing characteristics
Note:
SPEAr600
Therefore, we have to add the value T to the clock path and the value T/2 to the command path.
The waveform shown in Figure 8
refers to the pad or memory side, so the CLK edges are centered on the command valid window. In this case, we consider the minimum values for t4 and t5 in order to obtain the minimum command valid window. We can consider t4 as the t
SETUP
of the commands that can be defined as the time range where the commands are stable before the arrival of the clock. To have a positive quantity the delay obtained by the commands (maximum delay or last variation) must be less than the one obtained by the clock (minimum delay).
So: t4
MIN
= CLK (delay)
MIN
- CMD (delay)
MAX
=(T + t3
MIN
) - (T/2 + t2
MAX
) = T/2 - t2
MAX
+ t3
MIN t5 can be expressed in a similar way, and can be defined as the t
HOLD
of the commands: t5
MIN
= CMD (delay)
MIN
- CLK (delay)
MAX
= (T + T/2 + t2
MIN
) - (T + t3
MAX
) = T/2 - t3
MAX
+t2
MIN
CLK(delay) i s the combination of delay s experienced by the CLK s ignal, CMD(delay) i s the combination of delay s experienced by the command/ctrl/addre ss s ignal (both until the capture performed by the memory).
Table 3 5.
DDR2 command timings without pad delay
Period (T) Frequency t4
MIN
3 ns
3.75 ns
5 ns
6 ns
7.5 ns
333 MHz
266 MHz
200 MHz
166 MHz
133 MHz
977 ps
1.35 ns
1.98 ns
2.49 ns
3.23 ns t5
MIN
1.33 ns
1.71 ns
2.33 ns
2.84 ns
3.59 ns
shows the internal chip timing without the contribution of the pads.
64/97 Doc ID 16259 Rev 3
SPEAr600
6.2
Timing characteristics
EXPI timing characteristics
The characterization timing is done for an output load of 10 pF on PL_CLKx and 5 pF on
PL_GPIO_x .The operating conditions are in worst case V=0.90 V TA =125 °C and in best case V=1.10 V TA= 40 °C.
The timings are measured using TEST [5:0] = 101xxx: (Selg_cfg5 = EXPI with internal clock). Please refer to the user manual for the description of the SoC_cfg bits in the MISC registers.
Figure 10.
AHB EXPI transfer waveforms
Table 3 6.
EXPI - pad signal assignment
EXPI signal Direction
HAdd(19:00)
HAdd(21:20)
HAdd(23-:22)
HRWData(07:00)
HRWData(15:08)
HRWData(31:16)
HSize(2-0)
HWrite
HBurst(2-0)
HTrans(1-0)
Bidir.
Bidir.
Bidir.
Bidir.
Bidir.
Bidir.
Bidir.
Bidir.
Bidir.
Bidir.
Doc ID 16259 Rev 3
PL_GPIOs signal assignment
PL_GPIO(19:00)
PL_GPIO(56:55)
PL_GPIO(82:81)
PL_GPIO(27:20)
PL_GPIO(64:57)
PL_GPIO(80:65)
PL_GPIO(30:28)
PL_GPIO(31)
PL_GPIO(34:32)
PL_GPIO(36:35)
65/97
Timing characteristics SPEAr600
Table 3 6.
EXPI - pad signal assignment (continued)
EXPI signal Direction
HLock
HMastlock
HBreq
HGrant
HResp(1-0)
HReady_mst
HReady_out
HReady_in
HSel
Out.
Out.
DMA_LREQ(1:0)/ HAdd(25:24) Inp.
DMA_REQ(1:0) / HAdd(27:26) Inp.
DMACCLR(1:0)/ HAdd(29:28) Out.
DMACTC(1:0) / HAdd(31:30)
INT_IN_2
CLK
Out.
Inp.
Bidir.
Reset
INT_IN_1
INT_OUT
Inp.
Out.
Inp.
Out.
Bidir.
Out.
Inp.
Bidir.
Inp.
Out.
PL_GPIOs signal assignment
PL_GPIO_37
PL_GPIO_38
PL_GPIO_39
PL_GPIO_40
PL_GPIO(42:41)
PL_GPIO_43
PL_GPIO_44
PL_GPIO_45
PL_GPIO_46
PL_GPIO(48:47)
PL_GPIO(50:49)
PL_GPIO(52:51)
PL_GPIO(54:53)
PL_GPIO_83
PL_CLK_1
PL_CLK_2
PL_CLK_3
PL_CLK_4
Note:
6.2.1
Note:
For more detail s plea s e refer to the Expan s ion interface (EXPI) chapter of the u s er manual.
Pad delay disabled
Figure 11.
Pad delay disabled block diagram
Q SET D
CLK t ck_ff
Q
CLR
D SET Q
CLR
Q t ck _pa d t i n t o ut PL_GPIO[ x]
PL _C LK1
The pad of the clock i s di s abled or enabled u s ing the expi_clk_retim bit in the
EXPI_CLK_CFG regi s ter. Refer to the MISC regi s ter s chapter of the u s er manual).
66/97 Doc ID 16259 Rev 3
SPEAr600
Figure 12.
EXPI signal timing waveforms
PL_CLK1
Tclock
Input
PL_GPIO[ x]
Output t m in t setup t max
Table 3 7.
EXPI clock and reset parameters
Parameter Value (ns)
CLK period
Tf CLK fall
Tr CLK rise
15
0.81
0.81
Output
Signals t min
(ns)
Reset 0.84 t h old
Table 3 8.
SOC-master
Output
Signals t min
(ns)
HADDR -1.11
HSIZE,HWRITE, HBURST,
HTRANS, HMASTLOCK, HSEL,
HReady_in (45)
-0.92
HWDATA -1.00
Input
HReady_out(44), HRESP
HRDATA t
SETUP
(ns)
7
6.32
I
Table 3 9.
SOC-slave
Input
Signals t
SETUP
(ns)
HADDR 7.77
Doc ID 16259 Rev 3
Tf
Timing characteristics t max
(ns)
6
Tr
Frequency (MHz)
66.6 t max
(ns)
5.93
4.71
7.3
t
HOLD
(ns)
-2.09
-1.94
t
HOLD
(ns)
-1.94
67/97
Timing characteristics
Table 3 9.
SOC-slave (continued)
Note:
6.2.2
Note:
SPEAr600
HSIZE,HWRITE, HBURST,
HTRANS, HLOCK, HBUSREQ,
HWDATA
HGRANT, HReady_mst(43),
HRESP
HRDATA
Input
7.02
6.17
Output t min
(ns)
-0.66
-1.09
-1.94
-1.94
t max
(ns)
4.21
7.34
Input path:
t
SETUP
= t
SETUP_FF
+ t
IN(max)
+ t
CK_PAD(max)
- t
CK_FF t
HOLD
= t
HOLD_FF
- t
IN(min)
- t
CK_PAD(min)
+ t
CK_FF
Output Path:
t max
= (t
OUT
+ t
CK_FF
)(max) - t
CK_PAD
(min) t min
= (t
OUT
+ t
CK_FF
)(min) - t
CK_PAD
(max)
For t
SETUP
, t
HOLD
and t max
are taken the maximum value from wor s t ca s e and be s t ca s e, while the minimum value i s taken for t min
.
Pad delay enabled
Figure 1 3 .
EXPI pad delay enabled block diagram
Q
SET
D
Q
CL R
D SET
Q t ck_ff
CLK
CL R
Q t ck_pad t in t out
PL_GPIO[x]
PL_CLK1
The pad of the clock i s di s abled or enabled u s ing the expi_clk_retim bit in the
EXPI_CLK_CFG regi s ter. Refer to the MISC regi s ter s chapter of the u s er manual).
68/97 Doc ID 16259 Rev 3
SPEAr600
Figure 14.
EXPI signal timing waveforms
PL_ CLK1
T cloc k
Input
PL _GPIO [x]
Output t m in t setup t max
Table 40.
Clock and Reset
Parameter
CLK period
Tf CLK fall
Tr CLK rise
Output
Value
15
0.81 ns
0.81 ns t h old
Reset 0.84
Table 41.
SOC-master
Output
Signals Tmin(ns)
HADDR
HSIZE,HWRITE, HBURST,
HTRANS, HMASTLOCK, HSEL,
HReady_in (45)
2.66
2.85
HWDATA 2.77
Input
HReady_out(44), HRESP
HRDATA
Tsetup(ns)
0.6
-0.08
Table 42.
SOC-slave
Input
Signals Tsetup(ns)
HADDR
HSIZE,HWRITE, HBURST,
HTRANS, HLOCK, HBUSREQ,
HWDATA
1.37
0.62
0.23
Doc ID 16259 Rev 3
Tf
Timing characteristics
Frequency
66.6 MHz
6
Tmax(ns)
12.33
11.11
13.7
Thold(ns)
1.68
1.83
Thold(ns)
1.83
1.83
1.83
T r
69/97
Timing characteristics
Table 42.
SOC-slave (continued)
HGRANT, HReady_mst(43),
HRESP
HRDATA
Input
Output
Tmin(ns)
3.11
2.68
Tmax(ns)
10.61
13.74
SPEAr600
70/97 Doc ID 16259 Rev 3
SPEAr600
6.
3
6.
3 .1
Timing characteristics
CLCD timing characteristics
The characterization timing is done considering an output load of 10 pF on all the outputs.The operating conditions are in worst case V=0.90 V T=125 °C and in best case
V=1.10 V T= 40 °C.
The CLCD has a wide variety of configurations and setting and the parameters change accordingly. Two main scenarios will be considered, one with direct clock to output (166
MHz), setting BCD bit to '1', and the second one with the clock passing through a clock divider (83 MHz), setting BCD bit to '0'. Please refer to the Table 477 for more information on the significance of bit BCD).
CLCD timing characteristics direct clock
Figure 15.
CLCD waveform with CLCP direct
CLCP
Tmax
Tclock
Tmin
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
Tstable
Tf Tr
Figure 16.
CLCD block diagram with CLCP direct t1
CLCDCLK
D SET Q t2
CLR
Q
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
CLCP t3
Table 4 3 .
CLCD timings with CLCP direct
Parameter Value
Tclock direct max (Tclock)
Tclock direct max rise (Tr)
Tclock direct max (Tf)
Tmin
Tmax
Tstable
6 ns
0.81 ns
0.87 ns
-0.04 ns
3.62 ns
2.34 ns
Doc ID 16259 Rev 3
Frequency
166 MHz
71/97
Timing characteristics SPEAr600
Note: 1 T s table = Tclock direct max - (Tmax + Tmin)
2 For Tmax the maximum value i s taken from the wor s t ca s e and be s t ca s e, while for Tmin the minimum value i s taken from the wor s t ca s e and be s t ca s e.
3 CLCP s hould be delayed by {Tmax + [Tclock direct max - (Tmax + Tmin)]/2} = 4.7915 n s
6.
3 .2 CLCD timing characteristics divided clock
Figure 17.
CLCD waveform with CLCP divided
CLCP
Tmax
Tclock
Tmin
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
Tstable
Tf Tr
Figure 18.
CLCD block diagram with CLCP divided t1
CLCDCLK
D SET Q t2
CLR
Q
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
CLCP
D SET Q t3
CLR
Q
Table 44.
CLCD timings with CLCP divided
Parameter Value
Tclock divided max
Tclock divided max rise (Tr)
Tclock divided max (Tf)
Tmin
Tmax
Tstable
12 ns
0.81 ns
0.87 ns
-0.49 ns
2.38 ns
9.13 ns
Frequency
83.3 MHz
72/97 Doc ID 16259 Rev 3
SPEAr600 Timing characteristics
Note: 1 T s table = Tclock direct max - (Tmax + Tmin)
2 For Tmax the maximum value i s taken from the wor s t ca s e and for Tmin the minimum value i s taken from the be s t ca s e.
3 CLCP s hould be delayed by {Tmax + [Tclock direct max - (Tmax + Tmin)]/2} = 6.945 n s
The characterization timing is given for an output load of 10 pF on SCL and SDA.
The operating conditions are V=0.90 V, T=125 °C in worst case and V=1.10 V, T
A
= 40 °C in best case.
Figure 19.
I
2
C output pads
HCLK
D
SET
Q
CLR
Q
SCL
D SET Q
CL R
Q
SDA
Figure 20.
I
2
C input pads
SCL D SET Q
CLR
Q
D SET Q
CL R
Q
HCLK
SDA D SET Q
CLR
Q
D SET Q
CL R
Q
The flip-flops used to capture the incoming signals are re-synchronized with the AHB clock: so no input delay calculation is required.
Doc ID 16259 Rev 3 73/97
Timing characteristics
Figure 21.
Output signal waveforms for I
2
C signals
SPEAr600
74/97
SCL
T
SCLHigh
T
SU-STA
T
SCLLow
T
HD- STA
SDA
T
HD-DAT
T
SU-DAT
T
SU-STO
T
HD- STO
The timings of high and low level of SCL (TSCLHigh and TSCLLow) are programmable.
Table 45.
Timing characteristics for I
2
C in high-speed mode
Parameter Min
TSU-STA
THD-STA
TSU-DAT
THD-DAT
TSU-STO
THD-STO
163.31 ns
487.73 ns
313.38 ns
7.04 ns
642.98 ns
4.74 µs
Table 46.
Timing characteristics for I
2
C in fast-speed mode
Parameter Min
TSU-STA
THD-STA
TSU-DAT
THD-DAT
TSU-STO
THD-STO
643.27 ns
601.73 ns
1.19 µs
7.04 ns
642.98 ns
4.74 µs
Table 47.
Timing characteristics for I
2
C in standard-speed mode
Parameter Min
TSU-STA
THD-STA
TSU-DAT
THD-DAT
TSU-STO
THD-STO
4.73 µs
3.99 µs
4.67 µs
7.04 ns
4.03 µs
4.74 µs
Doc ID 16259 Rev 3
SPEAr600
Note:
Note:
Timing characteristics
The timing s s hown in
depend on the programmed value s of TSCLHigh and
TSCLLow: s o, the value s pre s ent in
Table 45 to Table 47 have been calculated u
s ing the minimum programmable value s of:
IC_HS_SCL_HCNT=19 and IC_HS_SCL_LCNT=53 regi s ter s (for High-Speed mode)
IC_FS_SCL_HCNT=99 and IC_FS_SCL_LCNT=215 regi s ter s (for Fa s t-Speed mode)
IC_SS_SCL_HCNT=664 and IC_SS_SCL_LCNT=780 regi s ter s (for Standard-Speed mode).
These minimum values depend on the AHB clock frequency, which is 166 MHz.
A device may internally require a hold time of at lea s t 300 n s for the SDA s ignal (referred to the VIHmin of the SCL s ignal) to bridge the undefined region of the falling edge of SCL
(Plea s e refer to the I2C Bu s Specification v3-0 Jun 2007). However, the SDA data hold time in the I2C controller of SPEAr600 i s one-clock cycle ba s ed (7 n s with the HCLK clock at 166
MHz). Thi s time may be in s ufficient for s ome s lave device s . A few s lave device s may not receive the valid addre ss due to the lack of SDA hold time and will not acknowledge even if the addre ss i s valid. If the SDA data hold time i s in s ufficient, an error may occur.
Workaround: If a device need s more SDA data hold time than one clock cycle, an RC delay circuit i s needed on the SDA line a s illu s
Figure 22.
RC delay circuit
SDA from SPEAr pad R SDA to Device
C
For example, R=K and C=200 pF.
Doc ID 16259 Rev 3 75/97
Timing characteristics
6.5
SPEAr600
FSMC timing characteristics
The characterization timing is done using primetime considering an output load of 3 pF on the data, 15 pF on NF_CE, NF_RE and NF_WE and 10 pF on NF_ALE and NF_CLE.
The operating conditions are V=0.90 V, T=125 °C in worst case and V=1.10 V, T= 40 °C in best case.
Figure 2 3 .
Output pads for 8-bit NAND Flash configuration
D SET Q
HCLK
...
CLR
Q
...
D SET Q
CLR
Q
Figure 24.
Input pads for 8-bit NAND Flash configuration
NFRB
HCLK
...
D SET Q
CLR
Q
NFCLE
NFCE
NFWE
NFRE
NFRWPRT
NFALE
NFIO_0..7
NFIO_0..7
D SET Q
CLR
Q
Figure 25.
Output command signal waveforms for 8-bit NAND Flash configuration
NFCE
T
CLE
NFCLE
T
WE
NFWE
T
IO
NFIO Command
76/97 Doc ID 16259 Rev 3
SPEAr600 Timing characteristics
Figure 26.
Output address signal waveforms for 8-bit NAND Flash configuration
NFCE
T
ALE
NFALE
T
WE
NFWE
T
IO
NFIO Address
Figure 27.
In/out data address signal waveforms for 8-bit NAND Flash configuration
NFCE
T
WE
NFWE
NFIO (out)
T
IO
T
RE
Data Out
T
READ
(3)
NFRE
T
RE -> IO
T
NFIO -> FFs
NFIO (in)
Table 48.
Timing characteristics for 8-bit NAND Flash configuration
Parameter Min Max
TCLE
TALE
TWE (s=1)
(1)
TIO (h=1)
(2)
-16.85 ns
-16.84 ns
11.10 ns
11.18 ns
3.43 ns
-19.38 ns
-19.37 ns
13.04 ns
13.05 ns
8.86 ns
1.
TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE, respectively. Both are composed by the algebric sum of a fixed part (due to the internal delays of Spear) and a programmable one in a FSMC register. The programmable one is equal to (s+1)*Thclk where s=Tset. The values shown in the table are calculated using s=1
2.
TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on the min or the max timing. It's composed by the algebric sum of a fixed part (due to the internal delays of
Spear) and a programmable one in a FSMC register. The programmable one is equal to h*Thclk where h=Thiz. The values shown in the table are calculated using h=1.
3.
TREAD is the timing between the falling edge and the rising edge of NFRE. This value is fully programmable and it's equal to
T(read) = (w+1)*T(hclk) >= T(re->io) + T(nfio->FFs) where w=Twait; T(re->io) is the output delay of the NAND Flash and T(nfio->FFs) is the SPEAr600 internal delay (~9 ns).
Doc ID 16259 Rev 3 77/97
Timing characteristics
Note: Value s in
THCLK = 6 n s .
are referred to the common internal
s ource clock which ha s
SPEAr600
a period of
Figure 28.
Output pads for 16-bit NAND Flash configuration
HCLK
...
D SET Q
CLR
Q
...
D SET Q
CLR
Q
...
NFCLE
NFCE
NFWE
NFRE
NFRWPRT
NFALE
NFIO_0..7
CLPOWER
CLLP
CLLE
CLFP
CLCP
CLAC
CLD_23..22
(NFIO_8..15)
Figure 29.
Input pads for 16-bit NAND Flash configuration
NFRB
NFIO_0..7
HCLK
CLPOWER
CLLP
CLLE
CLFP
CLCP
CLAC
CLD_23..22
(NFIO_8..15) ...
D SET
D
CLR
Q
...
SET
Q
Q
CLR
Q
Figure 3 0.
Output command signal waveforms 16-bit NAND Flash configuration
NFCE
NFCLE
T
CLE
T
WE
NFWE
T
IO
NFIO Command
78/97 Doc ID 16259 Rev 3
SPEAr600 Timing characteristics
Figure 3 1.
Output address signal waveforms 16-bit NAND Flash configuration
NFCE
T
ALE
NFALE
T
WE
NFWE
T
IO
NFIO Address
Figure 3 2.
In/out data signal waveforms for 16-bit NAND Flash configuration
NFCE
T
WE
NFWE
NFIO (out)
T
IO
T
RE
Data Out
T
READ
(3)
NFRE
T
RE -> IO
T
NFIO -> FFs
NFIO (in)
Table 49.
Timing characteristics for 16-bit NAND Flash configuration
Parameter Min Max
TCLE
TALE
TWE (s=1)
(1)
TIO (h=1)
(2)
-16.85 ns
-16.84 ns
11.10 ns
11.18 ns
-19.38 ns
-19.37 ns
13.04 ns
13.05 ns
3.27 ns 11.35 ns
1.
TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE, respectively. Both are composed by the algebric sum of a fixed part (due to the internal delays of Spear) and a programmable one in a FSMC register. The programmable one is equal to (s+1)*Thclk where s=Tset. The values shown in the table are calculated using s=1
2.
TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on the min or the max timing. It's composed by the algebric sum of a fixed part (due to the internal delays of
Spear) and a programmable one in a FSMC register. The programmable one is equal to h*Thclk where h=Thiz. The values shown in the table are calculated using h=1.
3.
TREAD is the timing between the falling edge and the rising edge of NFRE. This value is fully programmable and it's equal to
T(read) = (w+1)*T(hclk) >= T(re->io) + T(nfio->FFs) where w=Twait; T(re->io) is the output delay of the NAND Flash and T(nfio->FFs) is the SPEAr600 internal delay (~9 ns).
Doc ID 16259 Rev 3 79/97
Timing characteristics
Note: Value s in
THCLK = 6 n s .
are referred to the common internal
s ource clock which ha s
SPEAr600
a period of
6.6 Ether MAC 10/100/1000 Mbps (GMAC-Univ) timing characteristics
The characterization timing is given for an output load of 5 pF on the GMII TX clock and 10 pF on the other pads. The operating conditions are in worst case V=0.90 V, T=125 ° C and in best case V=1.10 V, T= 40 ° C.
Figure 33 .
GMII TX waveforms
GMIITX_CLK
Tmax
Tclock
Tmin
TXD0-TXD3,
GMIITX_D4-GMIITX_D7,
TXEN, TXER
Figure 3 4.
Block diagram of GMII TX pins
TX[0..3], GMII_TX[4..7],
TXEN, TXER
CLK
D SET Q
CLR
Q t2
Tf Tr
TX[0..3], GMII_TX[4..7],
TXEN, TXER t3 GMII_TXCLK
Table 50.
GMII TX timing
Parameter t rise
(t r
) t fall
(t f
) t max
= t2 max
- t3 min t min
= t2 min
- t3 max t
SETUP
Value using GMII [t
CLK
period = 8 ns 125 MHz]
<1 ns
<1 ns
2.8 ns
0.4 ns
5.19 ns
80/97 Doc ID 16259 Rev 3
SPEAr600
Note:
Timing characteristics
To calculate the t
SETUP
value for the PHY you have to con s ider the next t
CLK you have to apply the following formula: t
SETUP
= t
CLK
- t max
ri s ing edge, s o
Figure 3 5.
MII TX waveforms
TX_CLK
Tmax
Tclock
Tmin
TXD0-TXD3
Figure 3 6.
Block diagram of MII TX pins
TX[0..3]
D SET Q
CLR
Q t2
Tf Tr
TXD[0..3]
Note: t3 TX_CLK
Table 51.
MII TX timings
Parameter t max
= t2 max
- t3 min t min
= t2 min
- t3 max t
SETUP
Value using MII 100 Mb [t period = 40 ns 25 MHz]
CLK
6.8 ns
2.9 ns
33.2 ns
Value using MII 10 Mb [t
CLK period = 400 ns 2.5 MHz]
6.8 ns
2.9 ns
393.2 ns
To calculate the t
SETUP
value for the PHY you have to con s ider the next t
CLK you have to apply the following formula: t
SETUP
= t
CLK
- t max
ri s ing edge, s o
Doc ID 16259 Rev 3 81/97
Timing characteristics
6.6.
3 GMII-MII Receive timing specifications
Figure 3 7.
GMII-MII RX waveforms
RX_CLK
Tclock
SPEAr600
Note:
RXD0-RXD3,
GMIIRX_D4-GMIIRX_D7,
RX_ER, RX_DV
Ts
Th Tf Tr
Figure 3 8.
Block diagram of GMII-MII RX pins t2
RX[0..3], GMII_RX[4..7],
RX_ER, RX_DV t1
D
SET Q
CLR
Q
RX_CLK
Table 52.
GMII-MII RX timings
Parameter
Value using GMII [t
CLK period = 8 ns
125 MHz]
Value using MII 100Mb
[t
CLK
period = 40 ns
25 MHz]
Value using MII 10
Mb [t
CLK
period = 400 ns 2.5 MHz] t
SETUPmax
(t
S
)= t2 max
t1 min t
HOLDmin
(t
H
)= t2 min
t1 max
2.26 ns
-0.11 ns
2.26 ns
-0.11 ns
2.26 ns
-0.11 ns
The input s tage i s the s ame for all the interface s (GMII and MII10/100) s o t
SETUP
and t value s are equal in all the ca s e s .
HOLD
The receive path i s optimized for the GMII interface: thi s al s o en s ure s correct capture of data for the MII10/100 interface.
82/97 Doc ID 16259 Rev 3
SPEAr600 Timing characteristics
Note:
Figure 3 9.
MDC waveforms
MDC
Tclock
MDIO
Input Tsetup Thold
Tf Tr
Output Tmax
Tmi n
Figure 40.
Paths from MDC/MDIO pads
INPUT
Q SET D
Q
CLR
CLK
OUTPUT
D SET Q t3
CLR
Q
Table 5 3 .
MDC/MDIO timing
Parameter t
CLK
period t
CLK
fall (t f
) t
CLK
rise (t r
) t max
= ~t
CLK
/2 t min
= ~t
CLK
/2 t
SETUPmax
= t1 max
- t3 min t
HOLDmin
= t1 min
- t3 max
Value
614.4 ns
1.18 ns
1.14 ns
Output
307 ns
307 ns
Input
6.88 ns
-1.54 ns t1 t2 MDIO
MDC
Frequency
1.63 MHz
When MDIO i s u s ed a s output the data are launched on the falling edge of the clock a s s hown in
.
Doc ID 16259 Rev 3 83/97
Timing characteristics
6.7
6.7.1
SPEAr600
SMI timing characteristics
The characterization timing is given for an output load of 5 pF on the clock and 10 pF on the other pads. The operating conditions are in worst case V=0.90 V, T
A
=125° C and in best case V=1.10 V, T
A
= 40° C.
SMI timing specifications
Figure 41.
SMI waveforms
SMI_CLK
Tclock
Thold
SMI_DATAIN
Tsetup
T f Tr
SM I_DATAOUT
Tmin
Tmax
SM I_CS_0
SM I_CS_1
SM I_CS_3
Tfmin Tfmax Trmin Trmax
Figure 42.
Block diagram of the SMI pins
Q S ET D
Q
C LR
SMI_CLK
D S ET Q
C LR
Q
HCLK
SMI_DATAOUT
SMI_CS_n
(n= 0,1,3)
D S ET Q
C LR
Q
SMI_DATAIN
SMI_CLK
SMI_DATAOUT
SMI_CS_n
(n= 0,1,3)
Table 54.
SMI timings in default configuration
Signal Parameter Value
SMI_CLK
SMI_DATAIN t
CLK t
CLK t r t f t
SETUP t
HOLD
50 ns
20 ns
0.8 ns
0.84 ns
4.5 ns
-0.08 ns
Description
SMI period (normal mode).
SMI period (fast read mode).
Transition times.
Max setup time and min hold time of data in, referred to SMI_CLK rising edge.
84/97 Doc ID 16259 Rev 3
SPEAr600 Timing characteristics
Table 54.
SMI timings in default configuration (continued)
Signal Parameter Value
SMI_DATAOUT
SMI_CS_0
SMI_CS_1 t max t min t rmax t rmin t fmax t fmin t rmax t rmin t fmax t fmin
0.65 ns
-0.41 ns
0.59 ns
-0.52 ns
0.46 ns
-052 ns
0.67 ns
-0.27 ns
0.54 ns
-0.3 ns
Description
Max and min delay time of data out, referred to SMI_CLK falling edge.
Max and min delay time of chip select
0 rising edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
0 falling edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
0 rising edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
1 falling edge, referred to SMI_CLK falling edge.
Table 55.
SMI Timings of SMI_CS_ 3 in non-default configurations
Signal Parameter Value Description
2.64 ns
NF_WP (SMI_CS_3 in
Disable_nand_flash)
CLD_14 (SMI_CS_3 in
Disable_LCD_ctr)
RX_ER (SMI_CS_3 in
Disable_GMAC_ctr) t rmin t fmax t fmin t rmax t rmin t fmax t fmin t rmin t fmax t fmin t rmax t rmin t fmax t fmin t rmax
1.32 ns
2.47 ns
-0.31 ns
0.71ns
-0.08 ns
0.52 ns
0.36 ns
3.99 ns
0.6 ns
3.91 ns
1.56 ns
1.32 ns
2.47 ns
1.56 ns
Max and min delay time of chip select
3 rising edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
3 falling edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
3 rising edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
3 falling edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
3 rising edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
3 falling edge, referred to SMI_CLK falling edge.
Max and min delay time of chip select
3 falling edge, referred to SMI_CLK falling edge.
Doc ID 16259 Rev 3 85/97
Timing characteristics
6.8
SPEAr600
SSP timing characteristics
●
●
●
The device SPEAr600 contains 3 SSP modules. The Low Speed Connectivity Subsystem contains SSP1 and SSP2, the Application Subsystem contains SSP3. These 3 identical modules provide a programmable length shift register which allows serial communication with other SSP devices through a 3 or 4 wire interface (SSP_SCLK, SSP_MISO,
SSP_MOSI and SSP_SS). The SSP module supports the following features:
Master/Slave mode operations
Programmable clock bit rate and prescaler
Programmable choice of interface operation: SPI, Microwire or TI synchronous serial
Programmable data frame size from 5 to 16 bits
● Separate transmit and receive FIFO, 16 bits wide, 8 locations deep
The features of the Motorola SPI-compatible interface are:
● Full duplex, four-wire synchronous transfers (SSP_SCLK, SSP_MISO, SSP_MOSI and
SSP_SS)
● Programmable Clock Polarity (CPOL) and Clock Phase (CPHA)
The following Tables show the Timing Requirements of the SPI four-wire synchronous transfer for the 3 SSP modules present in the Spear600 configured in master mode
(indicated in the tables as SPI1, SPI2 and SPI3). Both the Timings on MISO (master input slave output) pad and MOSI (master output slave input) pad are provided.
1
2
3
Table 56.
Timing requirements for SSP (all modes)
No.
parameters
Tc(CLK)
Tw(CLKH)
Tw(CLKL)
Cycle time, SSP_SCLK
Pulse duration, SSP_SCLK high
Pulse duration, SSP_SCLK low value
24 (min)
.49T - .51T
.51T - .49T
unit ns ns ns
T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a configurable divider.
Figure 4 3 .
SSP_CLK timing
86/97 Doc ID 16259 Rev 3
SPEAr600
6.8.1
Timing characteristics
The Motorola SPI interface is a four-wire interface where SSP_SS signal behaves as a slave select.
The main feature of the Motorola SPI format is that the inactive state and phase of the output clock signal are programmable through the CPOL (clock polarity) and CPHA (clock phase) parameters inside an IP control register.
● CPOL, clock polarity:
When CPOL clock polarity control parameter is low, it produces a steady state low value on the output clock pin. If this parameter is high, a steady state high value is placed on the output clock pin when data is not being transferred.
● CPHA, clock phase:
The CPHA clock phase control parameter selects the clock edge that captures data and allows it to change state. When CPHA is low, data is captured on the first clock edge transition after slave selection and is changed on the second clock edge transition. If the CPHA clock phase control parameter is high, data is captured on the second clock edge transition after the slave selection and is changed on the first clock edge transition.
SPI master mode timings (CPHA = 0)
Table 57.
Timing requirements for SPI mode on MISO pad [CPHA = 0]
No parameters CPOL SPI1 SPI2 SPI 3
13
14
15
16
Setup time, MISO (input) valid before SSP_SCLK
(output) rising edge
Setup time, MISO (input) valid before SSP_SCLK
(output) falling edge
Hold time, MISO (input) valid after SSP_SCLK
(output) rising edge
Hold time, MISO (input) valid after SSP_SCLK
(output) falling edge
0
1
0
1
9.563
9.632
-8.849
-8.956
10.759
10.804
-10.112
-10.149
10.357
10.427
-9.753
-9.785
unit ns ns ns ns
Table 58.
Timing requirements for SPI mode on MOSI pad [CPHA = 0]
No parameters CPOL SPI1 SPI2 SPI 3
17
18
Delay time, SSP_SCLK
(output) falling edge to
MOSI (output) transition
Delay time, SSP_SCLK
(output) rising edge to
MOSI (output) transition
0
1
-0.675
-0.607
-1.141
-1.097
-1.638
-1.568
unit ns ns
Doc ID 16259 Rev 3 87/97
Timing characteristics SPEAr600
Table 58.
Timing requirements for SPI mode on MOSI pad [CPHA = 0] (continued)
No parameters CPOL SPI1 SPI2 SPI 3 unit
19
20
Delay time, SSP_SS
(output) falling edge to first
SSP_SCLK (output) rising or falling edge
Delay time, SSP_SCLK
(output) rising or falling edge to SSP_SS (output) rising edge
T
T/2 ns ns
Figure 44.
SPI master mode external timing (CPHA = 0)
6.8.2 SPI master mode timings (CPHA = 1)
Table 59.
Timing requirements for SPI mode on MISO pad [CPHA = 1]
No parameters CPOL SPI1 SPI2 SPI 3
4
5
Setup time, MISO (input) valid before SSP_SCLK
(output) falling edge
Setup time, MISO (input) valid before SSP_SCLK
(output) rising edge
0
1
9.632
9.563
10.804
10.759
10.427
10.357
unit ns ns
88/97 Doc ID 16259 Rev 3
SPEAr600 Timing characteristics
Table 59.
Timing requirements for SPI mode on MISO pad [CPHA = 1] (continued)
No parameters CPOL SPI1 SPI2 SPI 3 unit
6
7
Hold time, MISO (input) valid after SSP_SCLK
(output) falling edge
Hold time, MISO (input) valid after SSP_SCLK
(output) rising edge
0
1
-8.956
-8.849
-10.149
-10.112
-9.785
-9.753
ns ns
Table 60.
Timing requirements for SPI mode on MOSI pad [CPHA = 1]
No parameters CPOL SPI1 SPI2 SPI 3
8
9
10
11
Delay time, SSP_SCLK
(output) rising edge to
MOSI (output) transition
Delay time, SSP_SCLK
(output) falling edge to
MOSI (output) transition
Delay time, SSP_SS
(output) falling edge to first
SSP_SCLK (output) rising or falling edge
Delay time, SSP_SCLK
(output) rising or falling edge to SSP_SS (output) rising edge
0
1
-0.607
-0.675
T/2
T/2
-1.097
-1.141
-1.568
-1.638
Figure 45.
SPI master mode external timing (CPHA = 1) unit ns ns ns ns
Doc ID 16259 Rev 3 89/97
Package information SPEAr600
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.
s t.com
.
ECOPACK
®
is an ST trademark.
SPEAr600 is ROHS-6 compliant.
90/97 Doc ID 16259 Rev 3
SPEAr600
7.1 Package mechanical data
Table 61.
PBGA420 (2 3 x 2 3 x 2.06 mm) mechanical data mm
Dim.
Min.
Typ.
Max.
Min.
2.06
F ddd eee fff
D2
E
E1
E2 e
A4 b
D
D1
A
A1
A2
A3
0.24
0.40
22.80
22.80
0.56
0.97
1.53
0.50
23.00
21.00
20.00
23.00
21.00
20.00
1.00
1.00
0.60
23.20
23.20
0.20
0.25
0.10
0.0094
0.0157
0.8976
0.8976
Package information inches
Typ.
0.0220
0.0382
0.0602
0.0197
0.9055
0.8268
0.7874
0.9055
0.8268
0.7874
0.0394
0.0394
Max.
0.0811
0.0236
0.9134
0.9134
0.0079
0.0098
0.0039
Doc ID 16259 Rev 3 91/97
Package information
Figure 46.
PBGA420 (2 3 x 2 3 x 2.06 mm) package top view
SPEAr600
92/97 Doc ID 16259 Rev 3
SPEAr600
Figure 47.
PBGA420 (2 3 x 2 3 x 2.06 mm) package bottom view
Package information
Table 62.
SPEAr600 PBGA420 thermal resistance characteristics
Parameter Symbol
Θ
JA
Θ
JB
Θ
JC
Ψ
JC
Thermal resistance junction-to-ambient
(1)
Thermal resistance junction-to-board
Thermal resistance junction-to-case 9.9
Junction-to-case thermal characterisation parameter
Value
26.7
18.2
0.38
1.
Measured on JESD51 2s2p test board.
Unit
°C/W
Doc ID 16259 Rev 3 93/97
Revision history
Table 6 3 .
Document revision history
Date Revision
22-Sep-2009 1 Initial release.
Changes
SPEAr600
94/97 Doc ID 16259 Rev 3
SPEAr600 Revision history
Table 6 3 .
Document revision history (continued)
Date Revision Changes
8-Feb-2010 2
Added I2S to
Modified pin list of I2S and EXPI Table 14: EXPI/I2S pin s
and
.
Updated sections
improving the description of I2S feature.
Updated
Table 19: Ab s olute maximum rating s
Updated section DDR2 timing characteri s tic s
.
Updated
Table 27: Driver characteri s tic s
.
Updated
Section 5.1: Ab s olute maximum rating s
Updated
Table 21: Recommended operating condition s
.
Updated
Updated introduction of Chapter 7: Package information
Updated
Table 10: NAND Fla s h I/F pin s .
Updated
Table 3: Power s upply pin s .
Updated
.
Updated
Figure 1: Functional block diagram and
Figure 2: Typical s y s tem architecture u s ing SPEAr600
Changed “SPI” with “SSP” where necessary.
Inserted the new
Section 6.8: SSP timing characteri s tic s
Corrected the frequency of DDR1.
Separated the Electrical characteri s tic s
in two chapters
Changed the title of the Section 5.5: 3.3V I/O characteri s tic s
Added
Table 62: SPEAr600 PBGA420 thermal re s i s tance characteri s tic s
.
Updated
,
,
,
Added a line of explanation in the introduction of Section 3: Pin de s cription
.
Added new Section 3.3: Configuration mode s
.
Added new Section 2.25: External Port Controller (EXPI I/F) .
Doc ID 16259 Rev 3 95/97
Revision history SPEAr600
Table 6 3 .
Document revision history (continued)
Date Revision Changes
09-May-2012 3
Modified FSMC feature on page 1
Figure 2: Typical s y s tem architecture u s ing SPEAr600
:
– Deleted SRAM and ROM blocks which were connected to the
FSMC block
– Substituted SSP with 3xSSP
– Added the RAS block.
Section 1.1: Main feature s on page 9 :
– Deleted the word “/parallel” from bullet seven (about FSMC)
– Replaced SPI with SSP in bullet sixteen.
– Modified number of GPIOs to 10
– Added information about RAS (Reconfigurable Array Subsystem)
Chapter 2: Architecture overview
: reviewed the first introduction part.
Section 2.4: Flexible s tatic memory controller :
– Updated the introduction.
– Main features: changed the sentence “Provides independent chip select for each memory bank" by "Provides only one chip select for the first memory bank"
: swapped ball R1 from the “Digital ground group” to the “Analog ground group”.
Section 2.15: UART s : corrected the value of the baud rate to 3 Mbps
Table 48: Timing characteri s tic s for 8-bit NAND Fla s h configuration
and Table 49: Timing characteri s tic s for 16-bit NAND Fla s h configuration
: added three footnotes.
: swapped ball R1 from the “Digital ground group” to the “Analog ground group”.
Section 2.15: UART s : corrected the value of the baud rate in 3 Mbps
Table 48: Timing characteri s tic s for 8-bit NAND Fla s h configuration
and Table 49: Timing characteri s tic s for 16-bit NAND Fla s h configuration
: added three footnotes.
Created the new Section 2.24: Reconfigurable array s ub s y s tem connectivity (RAS) .
Section 3.3: Configuration mode s
and
Section Table 16.: Multiplexing s cheme
: removed additional PL_GPIOs, PL_CLK signals and renamed GPIOs to EXPI IOs
Section 6.6.3: GMII-MII Receive timing s pecification s
: added
Table 52: GMII-MII RX timing s
.
Changed parameter T
O
to T
A
and added T
Recommended operating condition s
J in
Updated
Table 62: SPEAr600 PBGA420 thermal re s i s tance characteri s tic s
.
96/97 Doc ID 16259 Rev 3
SPEAr600
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