STMicroelectronics ST1S10 Datasheet
تبلیغات
تبلیغات
ST1S10
3 A, 900 kHz, monolithic synchronous step-down regulator IC
DFN8 (4 x 4 mm) PowerSO-8
Features
• Step-down current mode PWM regulator
• Output voltage adjustable from 0.8 V
• Input voltage from 2.5 V up to 18 V
• 2% DC output voltage tolerance
• Synchronous rectification
• Inhibit function
• Synchronizable switching frequency from 400 kHz up to 1.2 MHz
• Internal soft start
• Dynamic short-circuit protection
• Typical efficiency: 90%
• 3 A output current capability
• Standby supply current: max. 6 µA over temperature range
• Operative junction temp.: from -40 °C to 125 °C
Applications
• Consumer
– STB, DVD, DVD recorders, TV, VCR, car audio, LCD monitors
• Networking
– XDSL, modems, DC-DC modules
• Computer
– Optical storage, HD drivers, printers, audio/graphic cards
• Industrial and security
– Battery chargers, DC-DC converters, PLD,
PLA, FPGA, LED drivers
Datasheet
-
production data
Description
The ST1S10 is a high efficiency step-down PWM current mode switching regulator capable of providing up to 3 A of output current. The device operates with an input supply range from 2.5 V to
18 V and provides an adjustable output voltage from 0.8 V (V
FB
) to 0.85 * V
IN_SW
[V
OUT
= V
FB
*
(1 + R1/R2)]. It operates either at a 900 kHz fixed frequency or can be synchronized to an external clock (from 400 kHz to 1.2 MHz). The high switching frequency allows the use of tiny SMD external components, while the integrated synchronous rectifier eliminates the need for a
Schottky diode. The ST1S10 provides excellent transient response, and is fully protected against thermal overheating, switching overcurrent and output short-circuit.
The ST1S10 is the ideal choice for point of load regulators or LDO pre-regulation.
Table 1. Device summary
Order code
Part number
DFN8 (4x4 mm) PowerSO-8
ST1S10 ST1S10PUR ST1S10PHR
February 2020
This is information on a product in full production.
DocID13844 Rev 7 1/30 www.st.com
Contents
Contents
ST1S10
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
> 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
OUT
< 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 12
> 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
< 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OCP (overcurrent protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SCP (short-circuit protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SCP and OCP operation with high capacitive load . . . . . . . . . . . . . . . . 14
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN8 (4 x 4) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Contents
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List of tables
List of tables
ST1S10
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ST1S10
List of figures
List of figures
Application schematic for low output voltage (V
Application schematic for low output voltage (V
< 2.5 V) and 2.5 V < V
IN
< 2.5 V) and 8 V < V
IN
< 8 V . . . . . 16
< 16 V . . . . . . 16
Efficiency vs. output current at V out
Efficiency vs. output current at V out
Efficiency vs. output current at V out
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
= 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Application circuit
1 Application circuit
Figure 1. Typical application circuit
ST1S10
AGND PGND
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ST1S10
2 Pin configuration
Pin configuration
Figure 2. Pin connections (top view for PowerSO-8, bottom view for DFN8)
Pin no.
1
2
3
4
5
6
7
8 epad
Symbol
V
IN_A
INH (EN)
V
FB
AGND
SYNC
V
IN_SW
SW
PGND epad
DFN8 (4x4) PowerSO-8
Table 2. Pin description
Name and function
Analog input supply voltage to be tied to V
IN
supply source
Inhibit pin active low. Connect to V
IN_A
if not used
Feedback voltage for connection to external voltage divider to set the V
OUT from 0.8V up to 0.85*V
IN_SW
)
(see Section 5.5: Output voltage selection on
Analog ground
Synchronization and frequency select. Connect SYNC to GND for 900 kHz
operation, or to an external clock from 400 kHz to 1.2 MHz. (see Section 5.8.1:
Power input supply voltage to be tied to V
IN
power supply source
Switching node to be connected to the inductor
Power ground
Exposed pad to be connected to ground
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Maximum ratings
3 Maximum ratings
ST1S10
Symbol
V
IN_SW
V
IN_A
V
INH
V
SW
V
FB
I
FB
Sync
T
STG
T
OP
Table 3. Absolute maximum ratings
Parameter
Positive power supply voltage
Positive supply voltage
Inhibit voltage
Output switch voltage
Feedback voltage
FB current
Synchronization
Storage temperature range
Operating junction temperature range
Value
-0.3 to 20
-0.3 to 20
-0.3 to V
IN_A
-0.3 to 20
-0.3 to 2.5
-1 to +1
-0.3 to 6
-40 to 150
-40 to 125
Note: Absolute maximum ratings are the values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Symbol
R thJA
R thJC
Table 4. Thermal data
Parameter PowerSO-8
Thermal resistance junction ambient
Thermal resistance junction case
40
12
DFN8
40
4
Unit
°C/W
°C/W
Symbol
ESD
Table 5. ESD protection
Test conditions
HBM
CDM
MM
Value
2
500
200
Unit kV
V
V
Unit
V
V
V
V
V mA
V
°C
°C
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ST1S10
4 Electrical characteristics
Electrical characteristics
V
IN
= V
IN_SW
= V
IN_A
= V
INH
C
IN
= 4.7 µF +0.1 µF, C
OUT
= 12 V, V
SYNC
= GND, V
OUT
= 22 µF, L1 = 3.3 µH, T
J
= 5 V, I
OUT
= 10 mA,
= -40 to 125 °C (unless otherwise specified, refer to the typical application circuit. Typical values assume T
J
= 25 °C).
Symbol
V
FB
I
FB
I
Q
I
OUT
V
INH
I
INH
Parameter
Table 6. Electrical characteristics
Test conditions
Feedback voltage
T
J
= 25 °C
T
J
= -25 °C to 125 °C
V
FB
pin bias current
Quiescent current
Output current
(1)
Inhibit threshold
V
INH
> 1.2 V, not switching
V
INH
< 0.4 V
V
IN
= 2.5 V to 18 V
V
OUT
= 0.8 V to 13.6 V
(2)
Device ON
Device OFF
Inhibit pin current
%V
OUT
/ Δ V
IN
Reference line regulation 2.5 V < V
IN
< 18 V
%V
OUT
/
Δ I
OUT
PWM fs
Reference load regulation 10 mA < I
OUT
< 3 A
V
FB
T
J
= 0.7 V, Sync = GND
= 25 °C
Min.
Typ. Max.
784
776
800 816
800 824
600
1.5
2.5
2 6
3.0
1.2
0.7
2
0.4
0.5
0.4
0.9
1.1
Unit mV mV nA mA
µA
A
D
MAX
R
DSon
-N
R
DSon
-P
I
SWL
ν
PWM switching frequency
Maximum duty cycle
(2)
NMOS switch on resistance
PMOS switch on resistance
Switch current limitation
Efficiency
I
SW
= 750 mA
I
SW
= 750 mA
I
OUT
= 100 mA to 300 mA
I
OUT
= 300 mA to 3 A
85 90
0.10
0.12
5.0
85
90
150
15
%
°C
°C
%
Ω
Ω
A
%
V
V
µA
%V
OUT
/
Δ V
IN
%V
OUT
/
Δ I
OUT
MHz
T
SHDN
T
HYS
Thermal shutdown
Thermal shutdown hysteresis
V
OUT
/ Δ I
OUT
Output transient response
V
OUT
@I
/ Δ I
OUT
O
=short
Short-circuit removal response
(overshot)
SYNC frequency capture range F
SYNC
SYNC
WD
V
IL_SYNC
SYNC pulse width
SYNC input threshold low
100 mA < I
OUT
≥ 500 ns
< 1 A, t
R
= t
F
10 mA < I
OUT
< short
V
IN
= 2.5 V to 18 V, V
SYNC
=
0 to 5 V
V
IN
= 2.5 V to 18 V
V
IN
= 2.5 V to 18 V
0.4
250
± 5
± 10
1.2
0.4
%V
O
%V
O
MHz ns
V
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Electrical characteristics ST1S10
Symbol
Table 6. Electrical characteristics (continued)
Parameter Test conditions
V
IH_SYNC
I
IL,
I
IH
UVLO
SYNC input threshold high
SYNC input current
Under voltage lock-out threshold
V
IN
= 2.5 V to 18 V
V
IN
= 2.5 V to 18 V,
V
SYNC
= 0 or 5 V
V
IN rising
Hysteresis
1. Guaranteed by design, but not tested in production.
2. See
Section 5.5: Output voltage selection
for maximum duty cycle conditions.
Min.
Typ. Max.
1.6
-10
2.3
200
+10
Unit
V
µA
V mV
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5 Application information
5.1
Application information
Description
The ST1S10 is a high efficiency synchronous step-down DC-DC converter with inhibit function. It provides up to 3 A over an input voltage range of 2.5 V to 18 V, and the output voltage can be adjusted from 0.8 V up to 85% of the input voltage level. The synchronous rectification removes the need for an external Schottky diode and allows higher efficiency even at very low output voltages.
A high internal switching frequency (0.9 MHz) allows the use of tiny surface-mount components, as well as a resistor divider to set the output voltage value. In typical application conditions, only an inductor and 3 capacitors are required for proper operation.
The device can operate in PWM mode with a fixed frequency or synchronized to an external frequency through the SYNC pin. The current mode PWM architecture and stable operation with low ESR SMD ceramic capacitors results in low, predictable output ripple. No external compensation is needed.
To maximize power conversion efficiency, the ST1S10 works in pulse skipping mode at light load conditions and automatically switches to PWM mode when the output current increases.
The ST1S10 is equipped with thermal shutdown protection activated at 150 °C (typ.).
Cycle-by-cycle short-circuit protection provides protection against shorted outputs for the application and the regulator. An internal soft start for start-up current limiting and power ON delay of 275 µs (typ.) helps to reduce inrush current during start-up.
5.2 External components selection
Input capacitor
The ST1S10 features two V
IN
pins: V
IN_SW switching peak current is drawn, and V
IN_A drivers.
for the power supply input voltage where the
to supply the ST1S10 internal circuitry and
The V
IN_SW
input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the IC. A high power supply source impedance requires larger input capacitance.
For the V
IN_SW
input capacitor the RMS current rating is a critical parameter that must be higher than the RMS input current. The maximum RMS input current can be calculated using the following equation:
Equation 1
I I
⋅
-
⋅ ⋅ where
η
is the expected system efficiency, D is the duty cycle and I current. The duty cycle can be derived using
.
O
is the output DC
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Application information ST1S10
Equation 2
D = (V
OUT
+ V
F
) / (V
IN
-V
SW
) where V
F
is the voltage drop across the internal NMOS, and V
SW
represents the voltage drop across the internal PDMOS. The minimum duty cycle (at V
IN_max
) and the maximum duty cycle (at V
IN_min
) should be considered in order to determine the max I
RMS through the input capacitor.
flowing
A minimum value of 4.7 µF for the V
IN_SW
and a 0.1 µF ceramic capacitor for the V suitable in most application conditions. A 10 µF or higher ceramic capacitor for the V
IN_SW and a 1 µF or higher for the V
IN_A
IN_A
are
are recommended in cases of higher power supply source impedance or where long wires are needed between the power supply source and the V
IN pins. The above higher input capacitor values are also recommended in cases where an output capacitive load is present (47 µF < C
LOAD
< 100 µF), which could impact the switching peak current drawn from the input capacitor during the start-up transient.
In cases of very high output capacitive loads (C
LOAD
> 100 µF), all input/output capacitor values shall be modified as described in
Section 5.8.5: SCP and OCP operation with high capacitive load .
The input ceramic capacitors should have a voltage rating in the range of 1.5 times the maximum input voltage and be located as close as possible to V
IN pins.
5.3 Output capacitor (V
OUT
> 2.5 V)
The most important parameters for the output capacitor are the capacitance, the ESR and the voltage rating. The capacitance and the ESR affect the control loop stability, the output ripple voltage and transient response of the regulator.
The ripple due to the capacitance can be calculated with the following equation:
Equation 3
V
RIPPLE(C)
= (0.125 x Δ I
SW
) / (F
S x C
OUT
) where F
S is the PWM switching frequency and current, which can be calculated as:
Δ
I
SW
is the inductor peak-to-peak switching
Equation 4
Δ I
SW
= [(V
IN
- V
OUT
) / (F
S x L)] x D where D is the duty cycle.
The ripple due to the ESR is given by:
Equation 5
V
RIPPLE
(ESR) = Δ I
SW
x ESR
The equations above can be used to define the capacitor selection range, but final values should be verified by testing an evaluation circuit.
Lower ESR ceramic capacitors are usually recommended to reduce the output ripple voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower output ripple voltage.
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ST1S10 Application information
Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors usually have very low ESL, making ripple voltages due to the ESL negligible. In order to reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection paths should be kept as short as possible.
The ST1S10 has been designed to perform best with ceramic capacitors. Under typical application conditions a minimum ceramic capacitor value of 22 µF is recommended on the output, but higher values are suitable considering that the control loop has been designed to work properly with a natural output LC frequency provided by a 3.3 µH inductor and 22 µF output capacitor. If the high capacitive load application circuit shown in
a 47 µF (or 2 x 22 µF capacitors in parallel) could be needed as described in
SCP and OCP operation with high capacitive load .
The use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum output voltage is recommended.
5.4
5.5
Output capacitor (0.8 V < V
OUT
< 2.5 V)
For applications with lower output voltage levels (V out
< 2.5 V) the output capacitance and inductor values should be selected in a way that improves the DC-DC control loop behavior.
In this output condition two cases must be considered: V
IN
> 8 V and V
IN
< 8 V.
For V
IN
< 8 V the use of 2 x 22 µF capacitors in parallel to the output is recommended, as
For V
IN
> 8 V, a 100 µF electrolytic capacitor with ESR < 0.1 Ω should be added in parallel to
the 2 x 22 µF output capacitors as shown in Figure 5.
Output voltage selection
The output voltage can be adjusted from 0.8 V up to 85% of the input voltage level by connecting a resistor divider (see R1 and R2 in the typical application circuit) between the output and the V
FB
pin. A resistor divider with R2 in the range of 20 k Ω is a suitable compromise in terms of current consumption. Once the R2 value is selected, R1 can be calculated using the following equation:
Equation 6
R1 = R2 x (V
OUT
- V
FB
) / V
FB where V
FB
= 0.8 V (typ.).
Lower values are suitable as well, but will increase current consumption. Be aware that duty cycle must be kept below 85% at all application conditions, so that:
Equation 7
D = (V
OUT
+ V
F
) / (V
IN
-V
SW
) < 0.85
where V
F
is the voltage drop across the internal NMOS, and V
SW
represents the voltage drop across the internal PDMOS.
Note that once the output current is fixed, higher V
OUT levels increase the power dissipation of the device leading to an increase in the operating junction temperature. It is recommended to select a V
OUT level which maintains the junction temperature below the
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Application information ST1S10 thermal shut-down protection threshold (150°C typ.) at the rated output current. The following equation can be used to calculate the junction temperature (T
J
):
Equation 8
T
J
= {[V
OUT
x I
OUT
x R thJA
x (1η )] / η} +T
AMB where R thJA
is the junction to ambient thermal resistance,
I
OUT
current and T
AMB
is the ambient temperature.
η
is the efficiency at the rated
To ensure safe operating conditions the application should be designed to keep T
J
< 140°C.
5.6 Inductor (V
OUT
> 2.5 V)
The inductor value fixes the ripple current flowing through output capacitor and switching peak current. The ripple current should be kept in the range of 20-40% of I
OUT_MAX example it is 0.6 - 1.2 A at I
OUT the following equation:
(for
= 3 A). The approximate inductor value can be obtained with
Equation 9
L = [(V
IN
- V
OUT
) / Δ I
SW
] x T
ON where T
ON is the ON time of the internal switch, given by:
T
ON
= D/F
S
The inductor should be selected with saturation current (I
SAT
) equal to or higher than the inductor peak current, which can be calculated with the following equation:
Equation 10
I
PK
= I
O
+ ( Δ I
SW
/2), I
SAT
≥ I
PK
The inductor peak current must be designed so that it does not exceed the switching current limit.
5.7
5.8
5.8.1
Inductor (0.8 V < V
OUT
< 2.5 V)
For applications with lower output voltage levels (V out
< 2.5 V) the description in the previous section is still valid but it is recommended to keep the inductor values in a range from 1µH to 2.2 µH in order to improve the DC-DC control loop behavior, and increase the output capacitance depending on the V
IN
and
application conditions a 2.2 µH inductor is the best compromise between DC-DC control loop behavior and output voltage ripple.
Function operation
Sync operation
The ST1S10 operates at a fixed frequency or can be synchronized to an external frequency with the SYNC pin. The ST1S10 switches at a frequency of 900 kHz when the SYNC pin is connected to ground, and can synchronize the switching frequency between 400 kHz to 1.2
MHz from an external clock applied to the SYNC pin. When the SYNC feature is not used,
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ST1S10
5.8.2
5.8.3
5.8.4
5.8.5
Application information this pin must be connected to ground with a path as short as possible to avoid any possible noise injected in the SYNC internal circuitry.
Inhibit function
The inhibit pin can be used to turn OFF the regulator when pulled down, thus drastically reducing the current consumption down to less than 6 µA. When the inhibit feature is not used, this pin must be tied to V
IN
to keep the regulator output ON at all times. To ensure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section under V
INH
Any slew rate can be used to drive the inhibit pin.
.
OCP (overcurrent protection)
The ST1S10 DC-DC converter is equipped with a switch overcurrent protection. In order to provide protection for the application and the internal power switches and bonding wires, the device goes into a shutdown state if the switch current limit is reached and is kept in this condition for the T
OFF
(T
ON(OCP)
period (T
OFF(OCP)
= 135 µs typ.) and turns on again for the T
ON
period
= 22 µs typ.) under typical application conditions. This operation is repeated cycle by cycle. Normal operation is resumed when no overcurrent is detected.
SCP (short-circuit protection)
In order to protect the entire application and reduce the total power dissipation during an overload or an output short-circuit condition, the device is equipped with dynamic shortcircuit protection which works by internally monitoring the V
FB
(feedback voltage).
In the event of an overload or output short-circuit, if the V
OUT feedback voltage (V
FB
T
OFF
time (T
OFF(SCP)
(T
ON(SCP) resumed when no overload is detected (V
FB
voltage is reduced causing the
) to drop below 0.3 V (typ.), the device goes into shutdown for the
= 288 µs typ.) and turns on again for the T
ON
period
= 130 µs typ.). This operation is repeated cycle by cycle, and normal operation is
> 0.3 V typ.) for the full T
ON
period.
This dynamic operation can greatly reduce the power dissipation in overload conditions, while still ensuring excellent power-on startup in most conditions.
SCP and OCP operation with high capacitive load
Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from short-circuit and overload.
However, a highly capacitive load on the output may cause difficulties during start-up. This
can be resolved by using the modified application circuit shown in Figure 3
, in which a minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for
C
LOAD
> 100 µF, it is necessary to add the C4 capacitor in parallel to the upper voltage
divider resistor (R1) as shown in Figure 3.
The recommended value for C4 is 4.7 nF.
Note that C4 may impact the control loop response and should be added only when a capacitive load higher than 100 µF is continuously present. If the high capacitive load is variable or not present at all times, in addition to C4 an increase in the output ceramic capacitor C2 from 22 µF to 47 µF (or 2 x 22 µF capacitors in parallel) is recommended. Also in this case it is suggested to further increase the input capacitors to a minimum of 10 µF for
C1 and a 4.7 µF ceramic capacitor for C3 as shown in
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Application information
Figure 3. Application schematic for heavy capacitive load
ST1S10
AGND PGND
(*) see OCP and SCP descriptions for C2 and C4 selection.
Figure 4. Application schematic for low output voltage (V
OUT
< 2.5 V) and 2.5 V < V
IN
< 8 V
AGND PGND
Figure 5. Application schematic for low output voltage (V
OUT
< 2.5 V) and 8 V < V
IN
< 16 V
16/30
AGND PGND
DocID13844 Rev 7
ST1S10
6 Layout considerations
Layout considerations
The layout is an important step in design for all switching power supplies.
High speed operation (900 kHz) of the ST1S10 device demands careful attention to PCB layout. Care must be taken in board layout to get device performance, otherwise the regulator could show poor line and load regulation, stability issues as well as EMI problems.
It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths.
The input capacitor must be placed as close as possible to the IC pins as well as the inductor and output capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to minimize the effects of ground noise. Connect these ground nodes together underneath the device and make sure that small signal components returning to the AGND pin and do not share the high current path of C
IN
and C
OUT
.
The feedback voltage sense line (V
FB
) should be connected right to the output capacitor and routed away from noisy components and traces (e.g.: SW line). Its trace should be minimized and shielded by a guard-ring connected to the ground.
Figure 6. PCB layout suggestion - top
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Layout considerations
Figure 7. PCB layout suggestion - bottom
ST1S10
I I
Thermal considerations
The lead frame die pad, of the ST1S10, is exposed at the bottom of the package and must be soldered directly to a properly designed thermal pad on the PCB, the addition of thermal vias from the thermal pad to an internal ground plane will help increase power dissipation.
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ST1S10
7 Diagram
Figure 8. Block diagram
Diagram
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Typical performance characteristics
8 Typical performance characteristics
ST1S10
Unless otherwise specified, refer to the typical application circuit under the following
I conditions: T
J
= 25 °C, V
OUT
= 10 mA, C
IN
IN
= V
IN-SW
= V
= 4.7 µF + 0.1 µF, C
IN-A
= V
OUT
INH
= 12 V, V
SYNC
= GND, V
OUT
= 5 V,
= 22 µF, L1 = 3.3 µH.
Figure 9. Voltage feedback vs. temperature Figure 10. Oscillator frequency vs. temperature
100 125
Figure 11. Max. duty cycle vs. temperature Figure 12. Inhibit threshold vs. temperature
-50 -25 100 125 -50 -25 100 125
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ST1S10
Figure 13. Reference line regulation vs. temperature
Typical performance characteristics
Figure 14. Reference load regulation vs. temperature
Figure 15. ON mode quiescent current vs. temperature
Figure 16. Shutdown mode quiescent current vs. temperature
Figure 17. PMOS ON-resistance vs. temperature Figure 18. NMOS ON-resistance vs. temperature
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Typical performance characteristics
Figure 19. Efficiency vs. temperature
ST1S10
Figure 20. Efficiency vs. output current at V out
= 5 V
100 125
Figure 21. Efficiency vs. output current at V out
= 3.3 V
Figure 22. Efficiency vs. output current at
V out
= 12 V
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ST1S10
9 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
9.1 Power SO-8 package information
Figure 23. Power SO-8 (exposed pad) package outline
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Package information
Symbol c c1
D
D1
(option1)
D1
(option2)
E
E1
E2
(option1)
A3 b b1
A
A1
A2
θ2
θ3
θ4
R
R1 h
θ1
E2
(option2) e
L
L1
L2
Table 7. Power SO-8 (exposed pad) package mechanical data
Dimensions (mm)
Min.
1.5
0.00
1.25
0.50
0.38
0.37
0.17
0.17
4.80
Typ.
1.55
0.10
1.40
0.60
0.42
0.20
4.90
Max.
1.70
0.15
1.65
0.70
0.51
0.47
0.25
0.23
5.00
3.10
3.30
3.50
2.09
5.80
3.80
2.20
2.09
1.17
0.45
0.07
0.07
0.30
15°
11°
15°
11°
2.29
6.00
3.90
2.40
2.29
1.27
0.60
1.04 REF
0.25 BSC
0.40
17°
13°
17°
13°
2.49
1.37
0.80
0.50
19°
15°
19°
15°
2.49
6.20
4.00
2.60
ST1S10
Note: “D1” and D2 are variables depending on die pad sizes.
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ST1S10 Package information
Figure 24. Power SO-8 (exposed pad) recommended footprint
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Package information
Figure 25. Power SO-8 (exposed pad) tape and reel dimensions
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26/30
Symbol
Table 8. Power SO-8 (exposed pad) tape and reel mechanical data
Dimensions (mm)
Min.
Typ.
Max.
T
Ao
Bo
Ko
D
N
A
C
Po
P
12.8
20.2
60
8.1
5.5
2.1
3.9
7.9
330
13.2
22.4
8.5
5.9
2.3
4.1
8.1
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ST1S10
9.2 DFN8 (4 x 4) package information
Figure 26. DFN8 (4 x 4) package outline
Package information
7869653B
Symbol
E2 e
L
D
D2
E
A
A1
A3 b
Table 9. DFN8 (4 x 4) package mechanical data
Dimensions (mm)
Min.
0.80
0
0.23
3.90
2.82
3.90
2.05
0.40
Typ.
0.90
0.02
0.20
0.30
4.00
3.00
4.00
2.20
0.80
0.50
DocID13844 Rev 7
Max.
1.00
0.05
0.38
4.10
3.23
4.10
2.30
0.60
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Package information
Figure 27. DFN8 (4x4) tape and reel dimensions
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28/30
Symbol
N
T
Ao
Bo
A
C
D
Ko
Po
P
Table 10. DFN8 (4x4) tape and reel mechanical data
Dimensions (mm)
Min.
Typ.
Max.
330
13.2
12.8
20.2
99 101
14.4
4.35
4.35
1.1
4
8
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10 Revision history
Revision history
Date
28-Aug-2007
24-Sep-2007
25-Oct-2007
16-Mar-2010
31-May-2012
27-Mar-2015
17-Feb-2020
Revision
Table 11. Document revision history
Changes
1
2
3
4
5
6
7
Initial release.
Add R thJC
on Table 4.
Added new paragraph 6: Layout considerations .
Updated PowerSO-8 package mechanical data.
Updated SO-8 (epad) and DFN8 (4x4) mechanical data.
Changed temperature min from 25 °C to 40 °C in Table 4 , and in
Section 4 .
Added
Table 5: ESD protection on page 8
.
Added and updated cross-references throughout document.
Updated titles of
Figure 6 on page 17
and
Figure 7 on page 18
.
Updated Section 9: Package information on page 23 (updated/added titles, headers, reformatted section).
Minor modifications throughout document.
Section 9: Package information
.
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ST1S10
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
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