STMicroelectronics STM32L552QC Datasheet

I2Cx (x=1...4)

(7)

LPTIMx (x=1,2)

***

All other peripherals are frozen

N/A

Any interrupt or event

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

LPUART1

LPTIMx (x=1,2)

USB_FS

(8)

Mode

Stop 1

Stop 2

Regulator and SMPS mode

(1)

LPR

Table 10. STM32L552xx modes overview (continued)

CPU Flash SRAM Clocks DMA and Peripherals

(2)

Off

LSE

LSI

LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

LPUART1

LPTIMx (x=1,2)

***

All other peripherals are frozen

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3

(7)

LPUART1

LPTIMx (x= 1,3)

***

All other peripherals are frozen

Wakeup source

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

LPUART1

LPTIMx (x=1,2)

USB_FS

(8)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3

(7)

LPUART1

LPTIMx (x= 1,3)

Table 10. STM32L552xx modes overview (continued)

Mode

Regulator and SMPS mode

(1)

CPU Flash SRAM Clocks DMA and Peripherals

(2)

Standby

Shutdown

LPR

OFF

Powered

Off

Powered

Off

SRAM2 ON

Powered

Off

Powered

Off

LSE

LSI

LSE

BOR, RTC, IWDG

***

All other peripherals are powered off

***

I/O configuration can be floating, pull-up or pull-down

RTC

***

All other peripherals are powered off

***

I/O configuration can be floating, pull-up or pull-down

(10)

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

4. The SRAM1 and SRAM2 clocks can be gated on or off independently.

5. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.

6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. USB_FS wakeup by resume from suspend and attach detection protocol event.

9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Wakeup source

Reset pin

5 I/Os (WKUPx)

(9)

BOR, RTC, IWDG

Reset pin

5 I/Os (WKUPx)

(9)

RTC

STM32L552xx Functional overview

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the Low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode to detect their wake-up condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The Brownout reset (BOR) always remains active in Standby mode.

The state of each I/O during Standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, the full SRAM2 or 4 Kbytes can be retained in Standby mode, supplied by the low-power regulator (standby with RAM2 retention mode).

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Functional overview STM32L552xx

The BORL (brown out detector low) can be configured in ultra-low-power mode to further reduce power consumption during standby mode.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the

HSI16, the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

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Peripheral

Functional overview

Table 11. Functionalities depending on the working mode (1)

Stop 0/1 Stop 2 Standby Shutdown

Run Sleep

Lowpower run

Lowpower sleep -

VBAT

CPU

(

Flash memory

512 Kbyte )

SRAM1

(192 Kbytes)

SRAM2 (64 Kbytes)

FSMC

OCTOSPI

Backup registers

Brownout reset

(BOR)

Programmable voltage detector

(PVD)

Peripheral voltage monitor (PVMx; x=1,2,3,4)

DMA

High speed internal

(HSI16)

Oscillator HSI48

High speed external

(HSE)

Low speed internal

(LSI)

Low speed external

(LSE)

Multi speed internal

(MSI)

Clock security system (CSS)

Clock security system on LSE

(2)

(3)

O O

Table 12 for more details.

(4)

Y Y

O O O O O -

O O O O

(5)

O O O O O O

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Functional overview STM32L552xx

Table 11. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

VBAT

voltage monitoring, temperature monitoring

RTC / TAMP

Number of RTC

Tamper pins

USB, UCPD

USARTx

(x=1,2,3,4,5)

Low-power UART

(LPUART)

I2Cx (x=1,2,4)

I2C3

SPIx (x=1,2,3)

FDCAN1

SDMMC1

SAIx (x=1,2)

DFSDM1

ADCx (x=1,2)

DAC1

VREFBUF

OPAMPx (x=1,2)

COMPx (x=1,2)

Temperature sensor

Timers (TIMx)

Low-power timer 1,

3 (LPTIM1 and

LPTIM3)

Low-power timer 2

(LPTIM2)

Independent watchdog (IWDG)

(8)

O O O O O O O -

(6)

(7)

O O O O -

O O -

O O O

O O O -

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STM32L552xx Functional overview

Table 11. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

VBAT

Window watchdog

(WWDG)

SysTick timer

Touch sensing controller (TSC)

Random number generator (RNG)

CRC calculation unit

(8)

GPIOs O O O O O O O O

(9)

5 pins

(10)

(11)

5 pins

(10)

1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.

Gray cells highlight the wakeup capability in each mode.

2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.

3. The SRAM clock can be gated on or off.

4. 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling ranges 0 and 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

The VBAT pin allows the device VBAT domain to be powered from an external battery, an external supercapacitor, or from V

when there is no external battery and when an external

DS12737 Rev 6 47/340

Functional overview

Note:

3.9.8

STM32L552xx supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode.

The VBAT operation is automatically activated when V

is not present. An internal VBAT battery charging circuit is embedded and can be activated when V

is present.

When the microcontroller is supplied from VBAT, neither external interrupts nor RTC alarm/events exit the microcontroller from the VBAT operation.

PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in

TrustZone security mode.

The PWR TrustZone security allows to secure the following configuration:

• Low-power mode

• Wake-up (WKUP) pins

• Voltage detection and monitoring

• VBAT mode

Other PWR configuration bits are secure when:

• The system clock selection is secure in RCC, the voltage scaling (VOS) configuration is secure

• A GPIO is configured as secure, it's corresponding bit for Pull-up/Pull-down in standby mode is secure

• The RTC is secure, the backup domain write protection bit in PWR is secure.

3.10 Peripheral interconnect matrix

Several peripherals have direct connections between them, which allow autonomous communication between them and support the saving of CPU resources (thus power supply consumption). In addition, these hardware connections allow fast and predictable latency.

Depending on the peripherals, these interconnections can operate in Run, Sleep, Lowpower run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See

Table 12. STM32L552xx peripherals interconnect matrix

Interconnect source

Interconnect destination

Interconnect action

TIMx

ADC

DAC1

DFSDM1

DMA

COMPx

Timers synchronization or chaining

Conversion triggers

Memory to memory transfer trigger

Comparator output blanking

Y Y Y Y -

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STM32L552xx Functional overview

Table 12. STM32L552xx peripherals interconnect matrix (continued)

Interconnect source

Interconnect destination

Interconnect action

COMPx

ADCx

RTC

TIM1, 8

TIM2, 3

LPTIMERx

TIM1, 8

TIM16

LPTIMERx

Timer input channel, trigger, break from analog signals comparison

Y Y Y Y -

Low-power timer triggered by analog signals comparison

Timer triggered by analog watchdog

Timer input channel from RTC events

Low-power timer triggered by RTC alarms or tampers

Y Y Y Y Y

(1)

Y Y Y Y -

Y Y Y Y Y

Clock source used as input channel for

RC measurement and trimming

Timer triggered by USB SOF

All clocks sources (internal and external)

TIM2

TIM15, 16, 17

USB

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

DFSDM1 (analog watchdog, short circuit detection)

TIM2

TIM1,8

TIM15,16,17

TIMx

GPIO

LPTIMERx

ADC

DAC1

DFSDM1

1. LPTIM1 and LPTIM3 only.

Timer break

External trigger

Conversion external trigger

The clock controller (see Figure 7

DS12737 Rev 6 49/340

Functional overview STM32L552xx

3.11 Reset and clock controller (RCC)

) distributes the clocks coming from the different oscillators to the core and to the peripherals. It also manages the clock gating for low-power modes and ensures the clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

• Clock security system: clock sources can be changed safely on the fly in Run mode through a configuration register.

• Clock management: to reduce the power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: four different clock sources can be used to drive the master clock SYSCLK:

– 4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the

USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 110 MHz.

• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output on the MCO.

• UCPD kernel clock : it is derived from HSI16 clock. The HSI16 RC oscillator must be enabled prior to the UCPD kernel clock use.

• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to output a 250 Hz as source clock.

• Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,

I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.

Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs.

• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software

50/340 DS12737 Rev 6

STM32L552xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt.

• Clock-out capability:

– MCO (microcontroller clock output): it outputs one of the internal clocks for external use by the application

– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes

(except VBAT).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 110 MHz.

DS12737 Rev 6 51/340

Functional overview STM32L552xx

Figure 7. STM32L552xx clock tree to IWDG

LSI RC 32 kHz

LSCO

OSC32_OUT to RTC

LSE OSC

32.768 kHz

/32

OSC32_IN

MCO

OSC_OUT

OSC_IN

PLL

PLLSAI1

/ 1→16

HSI RC

16 MHz

MSI RC

100 kHz – 48 MHz

/ R

RC 48 MHz

/ P

/ Q

/ R

/ P

/ Q

HSE OSC

4-48 MHz

Clock detector

PLLSAI3CLK

/ M

PLL48M1CLK

PLLCLK

PLLSAI1CLK

PLL48M2CLK

/ M

PLLADC1CLK

LSE

LSI

MSI

HSI16

HSE

SYSCLK

PLLCLK

HSI48

HSI16

PLLSAI2

/ P

/ Q

/ R

PLLSAI2CLK

/ M

HSI16

MSI

HSI16

HSE

HSE

MSI

HSI16

MSI

HSI16

HSE

MSI

HSI16

HSE

Clock source control

SYSCLK

MSI

AHB PRESC

/ 1,2,..512

HCLK

/ 8 to PWR to AHB bus, core, memory and DMA

FCLK Cortex free running clock to Cortex system timer

APB1 PRESC

/ 1,2,4,8,16

PCLK1 to APB1 peripherals

LSE

HSI16

SYSCLK x1 or x2 to TIMx x=2..7

to USARTx

X=2..5

to LPUART1

HSI16

SYSCLK

LSI

LSE

HSI16 to I2Cx x=1,2,3,4 to LPTIMx x=1,2

APB2 PRESC

/ 1,2,4,8,16

OCTOSPI clock

CRS clock

PCLK2 to APB2 peripherals x1 or x2 to TIMx x=1,8,15,16,17

LSE

HSI16

SYSCLK to

USART1

MSI

MHz

SDMMC clock

48 MHz clock to USB, RNG

SYSCLK to ADC

FDCAN

HSI16

To UCPD1

HSE

MSI

HSI16

DFSDM audio clock to SAI1

SAI1_EXTCLK

SAI2_EXTCLK to SAI2

MSv49302V2

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STM32L552xx Functional overview

TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in

TrustZone security mode.

The RCC TrustZone security allows to secure some RCC system configuration and peripheral configuration clock from being read or modified by non-secure accesses:

• RCC system security:

– HSE, HSE-CSS, HSI, MSI, LSI, LSE, LSE-CSS, HSI48 configuration and status bits

– Main PLL, PLLSAI1, PLLSAI2, AHB prescaler configuration and status bits

– System clock SYSCLK and HSI48 source clock selection and status bits

– MCO clock output configuration and STOPWUCK bit

– Reset flag RMVF configuration bit

• RCC peripheral security:

– When a peripheral is secure, the related peripheral clock, reset, clock source selection and clock enable during low power modes control bits are secure.

• A peripheral is in secure state when:

– For securable peripherals, when it's corresponding SEC security bit is set in the

TZSC (TrustZone security controller)

– For TrustZone-aware peripherals, a security feature of this peripheral is enabled through its dedicated bits.

The devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on

CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

After reset, all GPIOs are in Analog mode to reduce power consumption.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

GPIO TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O pin is configured as secure, its corresponding configuration bits for alternate function, mode selection, I/O data are secure against a non-secure access. The associated registers bit access is restricted to a secure software only. After reset, all GPIO ports are secure.

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Functional overview STM32L552xx

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, SDMMC1) and the slaves (Flash memory, RAM, FMC, OCTOSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 8. Multi-AHB bus matrix

CORTEX

-M33 with TrustZone and FPU

DMA1 DMA2 SDMMC1

8 KB I-Cache

Legend

Bus multiplexer Master Interface

Slave Interface

MPCBBx: Memory protection controller block based

MPCWMx: Memory protection controller Watermark

MPCBB1

MPCBB2

MPCWM1

MPCWM2

MPCWM3

FLASH

512 KB

SRAM1

SRAM2

AHB1 peripherals

AHB2 peripherals

OctoSPI1

FSMC

BusMatrix-S

MSv61198V1

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STM32L552xx Functional overview

3.15 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 13: DMA1 and DMA2 implementation for the

features implementation.

Direct memory access (DMA) is used in order to provide a high-speed data transfer between peripherals and memory as well as from memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps the CPU resources free for other operations.

The two DMA controllers have 16 channels in total, each one dedicated to manage memory access requests from one or more peripherals. Each controller has an arbiter for handling the priority between DMA requests.

The DMA supports 8 channels for each DMA1 and DMA2, independently configurable:

• Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

• Priority between the requests is programmable by software (4 levels per channel: very high, high, medium, low) or by hardware in case of equality (such as request 1 has priority over request 2).

• Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size.

• Support of transfers from/to peripherals to/from memory with circular buffer management.

• Programmable number of data to be transferred: 0 to 2 18 - 1.

• Generation of an interrupt request per channel. Each interrupt request is caused from any of the three DMA events: transfer complete, half transfer, or transfer error.

• TrustZone support:

– Support for AHB secure and non-secure DMA transfers, independently at a first channel level, and independently at a source and destination sub-level

– TrustZone-aware AHB slave port, protecting any secure resource (register, register field) from a non-secure software access

• Privileged / unprivileged support:

– Support for AHB privileged and unprivileged DMA transfers, independently at a channel level

– Privileged-aware AHB slave port.

Table 13. DMA1 and DMA2 implementation

Feature DMA1

Number of DMA channels

TrustZone

1 (supported)

DMA2

1 (supported)

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Functional overview STM32L552xx

3.16 DMA request router (DMAMUX)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the

DMA request is pending until it is served and the corresponding DMA request line is reset.

The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product.

An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs.

DMAMUX main features

• 16-channel programmable DMA request line multiplexer output

• 4-channel DMA request generator

• 23 trigger inputs to DMA request generator

• 23 synchronization inputs

• Per DMA request generator channel:

– DMA request trigger input selector

– DMA request counter

– Event overrun flag for selected DMA request trigger input

• Per DMA request line multiplexer channel output:

– 90 input DMA request lines from peripherals

– One DMA request line output

– Synchronization input selector

– DMA request counter

– Event overrun flag for selected synchronization input

– One event output, for DMA request chaining

• TrustZone support:

– Support for AHB secure and non-secure DMA transfers, independently at a channel level.

– TrustZone-aware AHB slave port, protecting any secure resource (register, register field) from a non-secure software access, with configurable interrupt event.

– Two secure and non-secure interrupt requests, resulting from any of the respectively secure and non-secure channels. Each channel event being caused from any of the two DMAMUX input events: trigger or synchronization overrun, associated with a respectively secure and non-secure channels.

• Privileged / Unprivileged support:

– Support for AHB privileged and unprivileged DMA transfers, independently, at a channel level.

– Privileged-aware AHB slave port.

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STM32L552xx Functional overview

3.17.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 8 priority levels, and to handle up to 109 maskable interrupt channels plus the 16 interrupt lines of the

Cortex

-M33.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

• TrustZone support. The NVIC registers are banked across secure and non-secure states

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.17.2 Extended interrupt/event controller (EXTI)

The Extended interrupts and event controller (EXTI) manages the individual CPU and system wakeup through configurable and direct event inputs. It provides wakeup requests to the power control, and generates an interrupt request to the CPU NVIC and events to the

CPU event input. For the CPU an additional Event Generation block (EVG) is needed to generate the CPU event signal.

The EXTI wakeup requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can also be used in RUN modes. The

EXTI also includes the EXTI mux IOport selection.

The EXTI main features are the following:

• 43 input events supported

• All event inputs allow to wake up the system.

• Events which do not have an associated wakeup flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI.

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Functional overview STM32L552xx

The asynchronous event inputs are classified in 2 groups:

• Configurable events (signals from I/Os or peripherals able to generate a pulse)

– Configurable events have the following features:

Selectable active trigger edge

Interrupt pending status register bit independent for the rising and falling edge.

Individual interrupt and event generation mask, used for conditioning the CPU wakeup, interrupt and event generation.

SW trigger possibility

• Direct events (interrupt and wakeup sources from peripherals having an associated flag which requiring to be cleared in the peripheral)

– Direct events have the following features:

Fixed rising edge active trigger

No interrupt pending status register bit in the EXTI. (The interrupt pending status flag is provided by the peripheral generating the event.)

Individual interrupt and event generation mask, used for conditioning the CPU wakeup and event generation.

No SW trigger possibility

• TrustZone secure events

– The access to control and configuration bits of secure input events can be made secure.

• EXTI IO port selection

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size.

Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity.

The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location.

3.19 Flexible static memory controller (FSMC)

The flexible static memory controller (FSMC) includes two memory controllers:

• The NOR/PSRAM memory controller

• The NAND/memory controller

This memory controller is also named flexible memory controller (FMC).

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The main features of the FSMC controller are the following:

• Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (four memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

– Ferroelectric RAM (FRAM)

• 8-,16- bit data bus width

• Independent chip select control for each memory bank

• Independent configuration for each memory bank

• Write FIFO

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

TrustZone security

When the TrustZone security is enabled, the whole FSMC banks are secure after reset.

Non-secure area can be configured using the TZSC MPCWMx controller.

• The FSMC NOR/PSRAM bank:

– Up to two non-secure area can be configured thought the TZSC MPCWM2 controller with a granularity of 64 Kbytes.

• The FSMC NAND bank:

– Can be either configured as fully secure or fully non-secure using the TZSC

MPCWM3 controller.

The FSMC registers can be configured as secure through the TZSC controller.

The OCTOSPI is a specialized communication interface targetting single, dual, quad or octal

SPI memories. It can operate in any of the three following modes:

• Indirect mode: all the operations are performed using the OCTOSPI registers

• Status polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting

• Memory-mapped mode: the external memory is memory mapped and is seen by the system as if it were an internal memory supporting read and write operation

The OCTOSPI supports two frame formats:

• Classical frame format with command, address, alternate byte, dummy cycles and data phase over 1, 2, 4 or 8 data pins

• HyperBus TM frame format

The OCTOSPI offers the following features:

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• Three functional modes: indirect, status-polling, and memory-mapped

• Read and write support in memory-mapped mode

• Supports for single, dual, quad and octal communication

• Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two quad memories in parallel.

• SDR and DTR support

• Data strobe support

• Fully programmable opcode for both indirect and memory mapped mode

• Fully programmable frame format for both indirect and memory mapped mode

• Each of the five following phases can be configured independently (enable, length, single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

• HyperBus TM support

• Integrated FIFO for reception and transmission

• 8, 16, and 32-bit data accesses are allowed

• DMA channel for indirect mode operations

• Timeout management

• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error

TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.

Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a granularity of 64 Kbytes.

The OCTOSPI registers can be configured as secure through the TZSC controller.

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3.21 Analog-to-digital converter (ADC)

The device embeds two successive approximation analog-to-digital converters with the following features:

• 12-bit native resolution, with built-in calibration

• 5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution)

• Up to 16 external channels

• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3 and DAC1 outputs

• One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

• Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals

– Results stored into a data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast context switching

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 input channels which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Table 14. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

TS ADC raw data acquired at a temperature of 130 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x0BFA 05A8 - 0x0BFA 05A9

0x0BFA 05CA- 0x0BFA 05CB

3.21.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 15. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x0BFA 05AA - 0x0BFA 05AB

3.21.3 V

BAT

battery voltage monitoring

This embedded hardware enables the application to measure the V

BAT the internal ADC channel ADC1_IN18. As the V

BAT

battery voltage using

voltage may be higher than the VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third of the V

BAT

voltage.

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3.22 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital interface supports the following features:

• Up to two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

The devices embed a voltage reference buffer which can be used as voltage reference for

ADC, DACs and also as voltage reference for external components through the VREF+ pin.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available.

Figure 9. Voltage reference buffer

VREFBUF

Bandgap +

DDA

DAC, ADC

VREF+

Low frequency cut-off capacitor

100 nF

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The devices embed two rail-to-rail comparators with programmable reference voltage

(internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output channels

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can also be combined into a window comparator.

The devices embed two operational amplifiers with external or internal follower routing and

PGA capability.

The operational amplifier features:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.26 Digital filter for sigma-delta modulators (DFSDM)

The devices embed one DFSDM with four digital filters modules and eight external input serial channels (transceivers) or alternately eight internal parallel inputs support.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs).

The DFSDM can also interface the PDM (pulse density modulation) microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into

DFSDM).

The DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators) and the DFSDM digital filter modules perform digital processing according to the user’s selected filter parameters with up to 24-bit final ADC resolution.

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The DFSDM peripheral supports:

• Up to 4 multiplexed input digital serial channels:

– Configurable SPI interface to connect various Σ∆ modulators

– Configurable Manchester coded 1 wire interface support

– Clock output for Σ∆ modulator(s)

• Alternative inputs from up to 4 internal digital parallel channels:

– Inputs with up to 16 bit resolution

– Internal sources: ADCs data or memory (CPU/DMA write) data streams

• Adjustable digital signal processing:

– Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

– Integrator: oversampling ratio (1..256)

• Up to 24-bit output data resolution:

– Right bit-shifter on final data (0..31 bits)

• Signed output data format

• Automatic data offset correction (offset stored in register by user)

• Continuous or single conversion

• Start-of-conversion synchronization with:

– Software trigger

– Internal timers

– External events

– Start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)

• Analog watchdog feature:

– Low value and high value data threshold registers

– Own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

– Input from output data register or from one or more input digital serial channels

– Continuous monitoring independently from standard conversion

• Short-circuit detector to detect saturated analog input values (bottom and top ranges):

– Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream

– Mnitoring continuously each channel (4 serial channel transceiver outputs)

• Break generation on analog watchdog event or short-circuit detector event

• Extremes detector:

– Store minimum and maximum values of output data values

– Refreshed by software

• DMA may be used to read the conversion data

• Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock absence

• “Regular” or “injected” conversions:

– “Regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions.

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3.27 Touch sensing controller (TSC)

Note:

The touch sensing controller provides a simple solution to add capacitive sensing functionality to any application. A capacitive sensing technology is able to detect finger presence near an electrode that is protected from direct touch by a dielectric (glass, plastic or other). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

The main features of the touch sensing controller are the following:

• Proven and robust surface charge transfer acquisition principle

• Supports up to 22 capacitive sensing channels

• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time

• Spread spectrum feature to improve system robustness in noisy environments

• Full hardware management of the charge transfer acquisition sequence

• Programmable charge transfer frequency

• Programmable sampling capacitor I/O pin

• Programmable channel I/O pin

• Programmable max count value to avoid long acquisition when a channel is faulty

• Dedicated end of acquisition and max count error flags with interrupt capability

• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components

• Compatible with proximity, touchkey, linear and rotary touch sensor implementation

• Designed to operate with STMTouch touch sensing firmware library

The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability.

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3.28 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.

The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a non-deterministic random bit generator (NDRBG).

The true random number generator:

• delivers 32-bit true random numbers, produced by an analog entropy source conditioned by a NIST SP800-90B approved conditioning stage,

• can be used as entropy source to construct a non-deterministic random bit generator

(NDRBG),

• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz

(256 RNG clock cycles otherwise),

• embeds start-up and NIST SP800-90B approved continuous health tests (repetition count and adaptive proportion tests), associated with specific error management,

• can be disabled to reduce power consumption, or enabled with an automatic low-power mode (default configuration),

• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses only (else an AHB bus error is generated, and the write accesses are ignored).

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-

1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the

HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.

It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,

SHA-224, SHA-256 or MD5 hash function twice.

3.30 Timers and watchdogs

The devices include two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.

Table 16 compares the features of the advanced control, general-purpose and basic timers.

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Timer type

Advanced control

Generalpurpose

Basic

Timer

TIM1, TIM8

TIM2, TIM5

TIM3, TIM4

TIM15

TIM16, TIM17

TIM6, TIM7

Table 16. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

16-bit

32-bit

16-bit

Up, down,

Up/down

Up, down,

Up/down

Up, down,

Up/down

Any integer between 1 and 65536

Yes

Capture/ compare channels

Complementary outputs

3.30.1 Advanced-control timer (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers.

The four independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled in order to turn off any power switches driven by these outputs.

Many features are shared with the general-purpose TIMx timers (described in

Section 3.30.2

) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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TIM17)

There are up to seven synchronizable general-purpose timers embedded in the

STM32L552xx devices (see

Table 16

for differences).

Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

• TIM2, TIM3, TIM4 and TIM5

They are full-featured general-purpose timers:

– TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.

These timers feature four independent channels for input capture/output compare,

PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has two channels and one complementary channel

– TIM16 and TIM17 have one channel and one complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.30.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode.

LPTIM1 and LPTIM3 are active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

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This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode (LPTIM1 only).

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

The Cortex

-M33 with TrustZone embeds two SysTick timers.

When TrustZone is activated, two SysTick timer are available:

• SysTick, Secure instance.

• SysTick, Non-secure instance.

When TrustZone is disabled, only one SysTick timer is available.

This timer (secure or non-secure) is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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The RTC supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

BAT

mode.

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.

• TrustZone support:

– RTC fully securable

– Alarm A, alarm B, wakeup Timer and timestamp individual secure or non-secure configuration

The RTC is supplied through a switch that takes power either from the V

DD present or from the V

BAT

pin.

supply when

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE), divided by a prescaler in the RCC.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup the device from the low-power modes.

3.32 Tamper and backup registers (TAMP)

32 32-bit backup registers are retained in all low-power modes and also in VBAT mode.

They can be used to store sensitive data as their content is protected by an tamper detection circuit. 8 tamper pins and 7 internal tampers are available for anti-tamper detection.

The external tamper pins can be configured for edge detection, or level detection with or without filtering, or active tamper which increases the security level by auto checking that the tamper pins are not externally opened or shorted.

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TAMP main features:

• 32 backup registers:

– The backup registers (TAMP_BKPxR) are implemented in the RTC domain that remains powered-on by VBAT when the VDD power is switched off

• 8 external tamper detection events

– Each external event can be configured to be active or passive

– External passive tampers with configurable filter and internal pull-up

• 5 internal tamper events

• Any tamper detection can generate a RTC timestamp event

• Any tamper detection can erase the backup registers

• TrustZone support:

– Tamper secure or non-secure configuration.

– Backup registers configuration in 3 configurable-size areas:

1 read/write secure area

1 write secure/read non-secure area

1 read/write non-secure area

• Monotonic counter.

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The device embeds four I2C. Refer to

Table 17: I2C implementation for the features

implementation.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I

C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

• Power system management protocol (PMBus TM ) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to

Figure 7: STM32L552xx clock tree

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 17. I2C implementation

I2C features

(1)

I2C1

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop 0, Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

I2C2

I2C3

I2C4

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Functional overview STM32L552xx

(USART)

The devices have three embedded universal synchronous receiver transmitters (USART1,

USART2 and USART3) and two universal asynchronous receiver transmitters (UART4,

UART5).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 driver enable. They are able to communicate at speeds of up to

10 Mbit/s.

The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant) and an SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx

(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 18. USART/UART/LPUART features

USART modes/features (1) USART1 USART2 USART3 UART4 UART5 LPUART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain

Wakeup from Stop 0 / Stop 1 modes

Wakeup from Stop 2 mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver enable

LPUART/USART data length

1. X = supported.

X (4 modes)

X X

7, 8 and 9 bits

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(LPUART)

The devices embed one low-power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half-duplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

The LPUART interface can be served by the DMA controller.

3.36 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

The devices embed two SAI. Refer to Table 19: SAI implementation for the features

implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol.

The SAI peripheral supports:

• Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO.

• 8-word integrated FIFOs for each audio sub-block.

• Synchronous or asynchronous mode between the audio sub-blocks.

• Master or slave configuration independent for both audio sub-blocks.

• Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode.

• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

• Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out.

DS12737 Rev 6 75/340

Functional overview STM32L552xx

• Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame.

• Number of bits by frame may be configurable.

• Frame synchronization active level configurable (offset, bit length, level).

• First active bit position in the slot is configurable.

• LSB first or MSB first for data transfer.

• Mute mode.

• Stereo/Mono audio frame capability.

• Communication clock strobing edge configurable (SCK).

• Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection.

– Anticipated frame synchronization signal detection in slave mode.

– Late frame synchronization signal detection in slave mode.

– Codec not ready for the AC’97 mode in reception.

• Interruption sources when enabled:

– Errors.

– FIFO requests.

• DMA interface with two dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block.

Table 19. SAI implementation

SAI features (1) SAI1

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97

Mute mode

Stereo/Mono audio frame capability.

16 slots

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

FIFO size

SPDIF

PDM

1. X: supported

X (8 Word)

SAI2

X (8 Word)

(SDMMC)

The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices.

76/340 DS12737 Rev 6

STM32L552xx Functional overview

The SDMMC features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit

• Full compatibility with previous versions of MultiMediaCards (backward compatibility)

• Full compliance with SD Memory Card Specifications Version 4.1. (SDR104

SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported)

• Full compliance with SDIO Card Specification Version 4.0: card support for two different databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported)

• Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO speed)

• Data and command output enable signals to control external bidirectional drivers.

3.39 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN modules and message

RAM memory.

The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

A 1 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers.

3.40 Universal serial bus (USB FS)

The devices embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and battery charging detection according to Battery Charging Specification Revision

1.2.

The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 link power management. It has software-configurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume support.

This interface requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator (HSI48) in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.

3.41 USB Type-C™ / USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB

Power Delivery Rev. 3.0 specifications.

DS12737 Rev 6 77/340

Functional overview STM32L552xx

The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors

• “Dead battery” support

• USB Power Delivery message transmission and reception

• FRS (fast role swap) support

The digital controller handles notably:

• USB Type-C level detection with debounce, generating interrupts

• FRS detection, generating an interrupt

• Byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible)

• USB Power Delivery timing dividers (including a clock pre-scaler)

• CRC generation/checking

• 4b5b encode/decode

• Ordered sets (with a programmable ordered set mask at receive)

• Frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

The Arm

SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using two pins only instead of five required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.42.2 Embedded Trace Macrocell™

The Arm ® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

78/340 DS12737 Rev 6

STM32L552xx

4 Pinouts and pin description

Pinouts and pin description

Figure 10. STM32L552xx LQFP48 pinout

VBAT

PC13

PC14_OSC32_IN

PC15_OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP48

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

1. The above figure shows the package top view.

Figure 11. STM32L552xxxxP LQFP48 external SMPS pinout

MSv49322V1

VBAT

PC13

PC14-OSC_IN

PC15-OSC_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP48

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PA13

PA12

PA11

PA10

MSv49311V1

1. The above figure shows the package top view.

DS12737 Rev 6 79/340

137

Pinouts and pin description

Figure 12. STM32L552xx UFQFPN48 pinout

STM32L552xx

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

UFQFPN48

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

1. The above figure shows the package top view.

Figure 13. STM32L552xxxxP UFQFPN48 external SMPS pinout

MSv49321V2

VBAT

PC13

PC14-OSC_IN

PC15-OSC_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

UFQFPN48

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

MSv49310V2

1. The above figure shows the package top view.

80/340 DS12737 Rev 6

STM32L552xx Pinouts and pin description

Figure 14. STM32L552xx LQFP64 pinout

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP64

VDDUSB

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

MSv49323V1

1. The above figure shows the package top view.

Figure 15. STM32L552xxxxQ LQFP64 SMPS step down converter pinout

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP64

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

VDD

VDDUSB

VSS

PA13

PA12

PA11

PA10

PA9

MSv49316V1

1. The above figure shows the package top view.

DS12737 Rev 6 81/340

137

Pinouts and pin description

Figure 16. STM32L552xxxxP LQFP64 external SMPS pinout

STM32L552xx

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP64

PC7

PC6

PB15

PB14

PB13

PB12

VDDUSB

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

MSv49312V2

1. The above figure shows the package top view.

Figure 17. STM32L552xxxxQ WLCSP81 SMPS step down converter ballout

1 2 3 4 5 6 7 8 9

PC6

PB15

PB14

VDD

VDDUSB

PA11

PA9

PC10

VSS

PA12

PA13

PC7

PB13

PB12

VSS

PD2

PC12

PC11

PA14

PA10

PC8

PC9

VLXSMPS

V15SMPS_1 VSSSMPS VDDSMPS PB10

PG13

PG12

PG10

PG9

PA15

PA8

PC4

PB11

PG11

PA3

PA6

PB1

PB2

VDDIO2

VSS

PG15

PG14

PA2

PA5

PB0

PB5

PB4

PB6

PB7

PB3

PA1

PB9 V15SMPS_2

PC13 VSS

PB8

PC15-

OSC32_OUT

PC14-

OSC32_IN

PH3-BOOT0

PH1-

OSC_OUT

PH0-OSC_IN

PC0 VSS

VBAT

NRST

PC2 PC1

VDD

PC3

PA4

PA7

VREF+

PA0

VDD

VSSA/VREF-

VDDA

VSS

MSv49317V1

1. The above figure shows the package top view.

82/340 DS12737 Rev 6

STM32L552xx Pinouts and pin description

Figure 18. STM32L552xxxxP WLCSP81 external SMPS ballout

1 2 3 4 5 6 7 8 9

VDD

VDDUSB

PA11

PA9

PC6

PB15

PB14

VDD

VDD12_1

PA15

PA8

PC4

PE14

PE13

PG13

PG12

PG10

PG9

PD2

PC12

PC11

PA14

PA10

PC8

PC9

PE15

PB10

PC7

PB13

PB12

VSS

PB11

PC10

VSS

PA12

PA13

PG11

PA3

PA6

PB1

PB2

VDDIO2

VSS

PG15

PG14

PA2

PA5

PB0

PB5

PB4

PB6

PB7

PB3

PA1

PB9 VDD12_2

PC13 VSS

PB8

PC15-

OSC32_OUT

PC14-

OSC32_IN

PH3-BOOT0

PH1-

OSC_OUT

PH0-OSC_IN

PC0 VSS

VBAT

NRST

PC2 PC1

VDD

PC3

PA4

PA7

VREF+

PA0

VDD

VSSA/VREF-

VDDA

VSS

MSv49313V1

1. The above figure shows the package top view.

Figure 19. STM32L552xx LQFP100 pinout

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VSS

VDD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

1. The above figure shows the package top view.

LQFP100

DS12737 Rev 6

PA10

PA9

PA8

PC9

PC8

PC7

VDD

VSS

VDDUSB

PA13

PA12

PA11

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

MSv49324V1

83/340

137

Pinouts and pin description STM32L552xx

Figure 20. STM32L552xxxxQ LQFP100 SMPS step down converter pinout

PC14-OSC32_IN

PC15-OSC32_OUT

VSS

VDD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC0

PC1

PC2

PC3

VSSA/VREF-

VREF+

VDDA

PA0

PA1

PA2

PA3

LQFP100

PC9

PC8

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

VDD

VSS

VDDUSB

PA13

PA12

PA11

PA10

PA9

PA8

MSv49318V1

1. The above figure shows the package top view.

84/340 DS12737 Rev 6

STM32L552xx Pinouts and pin description

Figure 21. STM32L552xx UFBGA132 ballout

3 4 5 6 7 8 9 10 1 2

PE5 PE3

VBAT

PC14-

OSC32_IN

PC15-

OSC32_OUT

PF2

PE4

PE6

PF0

PF1

PE1

PE2

PC13

PF3

PF4

PH0-OSC_IN

PH1-

OSC_OUT

VSSA/VREF-

PF5

NRST

PC0

VREF+ PA0

PC2

PC1

OPAMP1_VI

PC5

VDDA PA2 PA7

PB9 PB6

PG15 PH3-BOOT0

PG12

PB4

PE0

VDD

VSS

PC3

PA1

VSS

VDD

PB2

PB8

PB7

PF14

PF11

PB3

PB5

VSS

VDD

PE8

PG1

PD6

PG9

PG10

PD7

VDD

VSS

PE10

PE7

PD5

PD4

PD3

VDDIO2

PE12

PE14

VSS

PG6

PG4

VSS

VDD

PB10

PD2

PD1

PD0

VDD

PC11

PC12

PA13

PA9

PC7

PG7

PG2

PD14

PD9

PB13

PA14

PA10

PC9

PC6

PA15

PC10

PG3

PD13

PD11

PB14

L PA3 PA6

OPAMP2_VI

PA4 PB1 PF12 PF15 PE11 PE15 PB11 VSS PB12 PD8

M PA5 PC4 PB0 PF13 PG0 PE9 PE13 PG14 PG13 PG11 PD10

MSv49325V1

1. The above figure shows the package top view.

Figure 22. STM32L552xxxxQ UFBGA132 SMPS step down converter ballout

1 2 3 4 5 6 7 8 9 10 11 12

A PE5 PE3 PE1 PB9 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB

PG9

PG10

PD7

VBAT

PC14-

OSC32_IN

PC15-

OSC32_OUT

PF2

PE4

PE6

PF0

PF1

PE2

PC13

PF3

PF4

V15SMPS_2 PH3-BOOT0

PE0

VDD

VSS

PH0-OSC_IN

PH1-

OSC_OUT

VSSA/VREF-

PF5

NRST

PC0

VREF+ PA0

PC2

PC1

OPAMP1_VI

PC5

PC3

PA1

VSS

VDD

PB8

PB7

VDDA

PA3

PA5

PA2

PA6

OPAMP2_VI

PA7

PA4

PC4

PB2

PB1

PB0

PF14

PF11

PF12

PF13

VSS

VDD

PE8

PG1

PF15

PG0

PB4

PB3

PB5

VDD

VSS

PE10

PE7

PE11

PE9

PD4

PD3

VDDIO2

PE12

PE14

PE15

PE13

PG6

PG4

VSS

VDD

PB10

PB11

PD1

PD0

VDD

VSS

PC12

PA13

PA9

PC7

PG7

PG2

PD14

PD9

PB13

VSSSMPS

PC6

PG3

PD13

PD11

PC10

PA14

PA10

PC9

PB14

PB12

PG8

PG5

PD15

PD12

PA12

PA11

PA8

PC8

PB15

PD8

VDDSMPS VLXSMPS V15SMPS_1 PD10

MSv49319V1

1. The above figure shows the package top view.

VDDUSB

PA12

PA11

PA8

PC8

PG8

PG5

PD15

PD12

PB15

DS12737 Rev 6 85/340

137

Pinouts and pin description

Figure 23. STM32L552xx LQFP144 pinout

STM32L552xx

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

1. The above figure shows the package top view.

LQFP144

100

108 VDD

107 VSS

106

105

104

VDDUSB

PA13

PA12

103 PA11

102 PA10

101 PA9

PA8

PC9

PC8

PC7

PC6

VDDIO2

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

MSv49326V1

86/340 DS12737 Rev 6

STM32L552xx Pinouts and pin description

Figure 24. STM32L552xxxxQ LQFP144 SMPS step down converter pinout

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VREF+

VDDA

PA0

PA1

PA2

PA3

LQFP144

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

VDD

VSS

VDDUSB

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VDDIO2

108

107

106

105

104

103

102

101

100

MSv49320V1

1. The above figure shows the package top view.

DS12737 Rev 6 87/340

137

Name

Pin name

Pin type

I/O structure

Abbreviation

Table 20. Legend/abbreviations used in the pinout table

Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

RST

Input / output pin

5 V tolerant I/O

3.6 V tolerant I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

Option for TT or FT I/Os

(1)

(2)

(3)(4)

(5)

I/O, Fm+ capable

I/O, with USB function supplied by V

DDUSB

I/O, with Analog switch function supplied by V

DDA

I/O supplied only by V

DDIO2

I/O, USB Type-C PD capable

I/O, USB Type-C PD dead battery function

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Pin functions

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

1. The related I/O structures in

are: FT_f, FT_fa.

2. The related I/O structures in

are: FT_u.

3. The related I/O structures in

are: FT_a, FT_fa, TT_a.

4. The analog switch for the TSC function is supplied by V

5. The related I/O structures in

are: FT_s, FT_fs.

STM32L552xxxxP

Pin Number

STM32L552xxxxQ

Table 21. STM32L552xx pin definitions

STM32L552xx

Alternate functions

Additional functions

1 B3 1 -

2 A2 2

3 B2 3

4 A1 4 -

1 B3 1

2 A2 2

3 B2 3

4 A1 4

PE2 I/O FT -

PE3 I/O FT -

PE4 I/O FT -

PE5 I/O FT -

TRACECK, TIM3_ETR,

SAI1_CK1,

TSC_G7_IO1,

FMC_A23,

SAI1_MCLK_A,

EVENTOUT

TRACED0, TIM3_CH1,

OCTOSPI1_DQS,

TSC_G7_IO2,

FMC_A19,

SAI1_SD_B,

EVENTOUT

TRACED1, TIM3_CH2,

SAI1_D2,

DFSDM1_DATIN3,

TSC_G7_IO3,

FMC_A20, SAI1_FS_A,

EVENTOUT

TRACED2, TIM3_CH3,

SAI1_CK2,

DFSDM1_CKIN3,

TSC_G7_IO4,

FMC_A21,

SAI1_SCK_A,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

E2 11

1 1 1 B9 1 B9 6 B1 6 1

PE6

VBAT

PC13

I/O FT

S -

I/O FT

(1)

(2)

TRACED3, TIM3_CH4,

SAI1_D1, FMC_A22,

SAI1_SD_A,

EVENTOUT

WKUP3,

TAMP_IN3/TAMP_

OUT6

WKUP2,

RTC_TS/RTC_

OUT1,

TAMP_IN1/TAMP_

OUT2

PC14-

OSC3

2_IN

(PC14)

I/O FT

PC15-

OSC3

2_OUT

(PC15)

I/O FT

PF0

PF1

I/O

EVENTOUT

I2C2_SDA, FMC_A0,

EVENTOUT

I2C2_SCL, FMC_A1,

EVENTOUT

OSC32_IN

OSC32_OUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

E3 14

F2 15

10 F6 16

11 F7 17

18 -

19 -

20 -

E1 12 PF2 I/O FT -

D3 13 PF3 I/O FT -

E3 14 PF4 I/O FT -

F2 15 PF5 I/O FT -

VSS

VDD

18 PF6 I/O FT -

19 PF7 I/O FT -

20 PF8 I/O FT -

I2C2_SMBA, FMC_A2,

EVENTOUT

LPTIM3_IN1, FMC_A3,

EVENTOUT

LPTIM3_ETR,

FMC_A4, EVENTOUT

LPTIM3_OUT,

FMC_A5, EVENTOUT

TIM5_ETR, TIM5_CH1,

OCTOSPI1_IO3,

SAI1_SD_B,

EVENTOUT

TIM5_CH2,

OCTOSPI1_IO2,

SAI1_MCLK_B,

EVENTOUT

TIM5_CH3,

OCTOSPI1_IO0,

SAI1_SCK_B,

EVENTOUT

TAMP_IN6/TAMP_

OUT3

TAMP_IN7/TAMP_

OUT8

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

5 5

22 -

5 D9 5 D9 12 F1 23 5 5

21 PF9 I/O FT -

22 PF10 I/O FT -

TIM5_CH4,

OCTOSPI1_IO1,

SAI1_FS_B,

TIM15_CH1,

EVENTOUT

OCTOSPI1_CLK,

DFSDM1_CKOUT,

SAI1_D3, TIM15_CH2,

EVENTOUT

TAMP_IN8/TAMP_

OUT7

PH0-

OSC_I

(PH0)

PH1-

OSC_

OUT

(PH1)

I/O FT

7 14 G2 25 NRST I-O

EVENTOUT

OSC_IN

OSC_OUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

8 E7 8 E7 15 H2 26

9 F8 9 F8 16 G3 27 -

8 15 H2 26 PC0 I/O

_fa

9 16 G3 27 PC1 I/O

_fa

10 F7 10 F7 17 F3 28 10 17 F3 28 PC2 I/O

LPTIM1_IN1,

OCTOSPI1_IO7,

I2C3_SCL,

LPUART1_RX,

SDMMC1_D5,

SAI2_FS_A,

LPTIM2_IN1,

EVENTOUT

TRACED0,

LPTIM1_OUT,

SPI2_MOSI,

I2C3_SDA,

LPUART1_TX,

OCTOSPI1_IO4,

SAI1_SD_A,

EVENTOUT

LPTIM1_IN2,

SPI2_MISO,

DFSDM1_CKOUT,

OCTOSPI1_IO5,

EVENTOUT

ADC12_IN1

ADC12_IN2

ADC12_IN3

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

8 12 G9 12 G9 19 H1 30 8

11 G7 11 G7 18 F4 29 -

G8 G8 20 J1 31

H9 H9 21 K1 32 -

13 13 9

11 18 F4 29 PC3 I/O

9 13

19 30 VSSA S

31 VREFS

VSSA/

VREF-

21 J1 32

VREF

22 K1 33 VDDA S

VDDA/

VREF

LPTIM1_ETR,

LPTIM3_OUT,

SAI1_D1, SPI2_MOSI,

OCTOSPI1_IO6,

SAI1_SD_A,

LPTIM2_ETR,

EVENTOUT

ADC12_IN4

VREFBUF_OUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

10 10 14 H8 14 H8 22 J2 33 10 10 14 23 J2 34 PA0 I/O

TIM2_CH1, TIM5_CH1,

TIM8_ETR,

USART2_CTS/USART

2_NSS, UART4_TX,

SAI1_EXTCLK,

TIM2_ETR,

EVENTOUT

OPAMP1_VINP,

ADC12_IN5,

WKUP1,

TAMP_IN2/TAMP_

OUT1

H3 H3 -

OPAM

P1_VI

I TT -

11 11 15 F6 15 F6 23 G4 34 11 11 15 24 G4 35 PA1 I/O

TIM2_CH2, TIM5_CH2,

I2C1_SMBA,

SPI1_SCK,

USART2_RTS/USART

2_DE, UART4_RX,

OCTOSPI1_DQS,

TIM15_CH1N,

EVENTOUT

OPAMP1_VINM,

ADC12_IN6,

TAMP_IN5/TAMP_

OUT4

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

12 12 16 G6 16 G6 24 K2 35 12 12 16 25 K2 36 PA2 I/O

13 13 17 F5 17 F5 25 L1 36 13 13 17 26 L1 37 PA3 I/O

VSS

VDD

14 14 20 H7 20 H7 28 L3 39 14 14 20 29 L3 40 PA4 I/O

TIM2_CH3, TIM5_CH3,

USART2_TX,

LPUART1_TX,

OCTOSPI1_NCS,

UCPD1_FRSTX1,

SAI2_EXTCLK,

TIM15_CH1,

EVENTOUT

TIM2_CH4, TIM5_CH4,

SAI1_CK1,

USART2_RX,

LPUART1_RX,

OCTOSPI1_CLK,

SAI1_MCLK_A,

TIM15_CH2,

EVENTOUT

OCTOSPI1_NCS,

SPI1_NSS, SPI3_NSS,

USART2_CK,

SAI1_FS_B,

LPTIM2_OUT,

EVENTOUT

ADC12_IN7,

WKUP4/LSCO,

COMP1_INP

OPAMP1_VOUT,

ADC12_IN8

ADC12_IN9,

DAC1_OUT1

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

15 15 21 H6 21 H6 29 M1 40 15 15 21 30 M1 41 PA5 I/O

16 16 22 G5 22 G5 30 L2 41 16 16 22 31 L2 42 PA6 I/O

TIM2_CH1, TIM2_ETR,

TIM8_CH1N,

SPI1_SCK,

LPTIM2_ETR,

EVENTOUT

TIM1_BKIN,

TIM3_CH1,

TIM8_BKIN,

SPI1_MISO,

USART3_CTS/USART

3_NSS,

LPUART1_CTS,

OCTOSPI1_IO3,

TIM16_CH1,

EVENTOUT

M2 M2 -

OPAM

P2_VI

I TT -

ADC12_IN10,

DAC1_OUT2

OPAMP2_VINP,

ADC12_IN11

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

17 17 23 J7 23 J7 31 K3 42 17 17 23 32 K3 43 PA7 I/O

_fa

24 G4 G4 M3 -

24 33 M3 44 PC4 I/O

J3 25 34 J3 45 PC5 I/O

18 18 25 J6 24 J6 32 M4 43 18 18 26 35 M4 46 PB0 I/O

TIM1_CH1N,

TIM3_CH2,

TIM8_CH1N,

I2C3_SCL,

SPI1_MOSI,

OCTOSPI1_IO2,

TIM17_CH1,

EVENTOUT

USART3_TX,

OCTOSPI1_IO7,

EVENTOUT

SAI1_D3,

USART3_RX,

EVENTOUT

TIM1_CH2N,

TIM3_CH3,

TIM8_CH2N,

SPI1_NSS,

USART3_CK,

OCTOSPI1_IO1,

COMP1_OUT,

SAI1_EXTCLK,

EVENTOUT

OPAMP2_VINM,

ADC12_IN12

COMP1_INM,

ADC12_IN13

ADC12_IN14,

WKUP5,

TAMP_IN4/TAMP_

OUT5,

COMP1_INP

OPAMP2_VOUT,

ADC12_IN15

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

PB1

PB2

I/O

TIM1_CH3N,

TIM3_CH4,

TIM8_CH3N,

DFSDM1_DATIN0,

USART3_RTS/USART

3_DE,

LPUART1_RTS/LPUA

RT1_DE,

OCTOSPI1_IO0,

LPTIM2_IN1,

EVENTOUT

LPTIM1_OUT,

I2C3_SMBA,

DFSDM1_CKIN0,

OCTOSPI1_DQS,

UCPD1_FRSTX1,

EVENTOUT

K5 49 PF11 I/O FT -

OCTOSPI1_NCLK,

EVENTOUT

L5 50 PF12 I/O FT FMC_A6, EVENTOUT

50 -

51 VSS S

52 VDD S

53 PF13

I/O FT -

I2C4_SMBA, FMC_A7,

EVENTOUT

COMP1_INM,

ADC12_IN16

RTC_OUT2,

COMP1_INP

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

J5 51 -

L6 52

K6 54

36 J6 56

37 M7 57 -

PF14

PF15

I/O

M6 56 PG0 I/O FT -

K6 57 PG1 I/O FT -

38 K7 58 PE7 I/O FT -

39 J6 59 PE8 I/O FT -

40 M7 60 PE9 I/O FT -

I2C4_SCL,

TSC_G8_IO1,

FMC_A8, EVENTOUT

I2C4_SDA,

TSC_G8_IO2,

FMC_A9, EVENTOUT

TSC_G8_IO3,

FMC_A10, EVENTOUT

TSC_G8_IO4,

FMC_A11, EVENTOUT

TIM1_ETR,

DFSDM1_DATIN2,

FMC_D4, SAI1_SD_B,

EVENTOUT

TIM1_CH1N,

DFSDM1_CKIN2,

FMC_D5,

SAI1_SCK_B,

EVENTOUT

TIM1_CH1,

DFSDM1_CKOUT,

OCTOSPI1_NCLK,

FMC_D6, SAI1_FS_B,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

H1 -

38 J7 60

39 L7 61

40 J8 62

41 M8 63 -

L10

VSS

VDD

41 J7 63 PE10 I/O FT -

42 L7 64 PE11 I/O FT -

43 J8 65 PE12 I/O FT -

44 M8 66 PE13 I/O FT -

TIM1_CH2N,

TSC_G5_IO1,

OCTOSPI1_CLK,

FMC_D7,

SAI1_MCLK_B,

EVENTOUT

TIM1_CH2,

TSC_G5_IO2,

OCTOSPI1_NCS,

FMC_D8, EVENTOUT

TIM1_CH3N,

SPI1_NSS,

TSC_G5_IO3,

OCTOSPI1_IO0,

FMC_D9, EVENTOUT

TIM1_CH3, SPI1_SCK,

TSC_G5_IO4,

OCTOSPI1_IO1,

FMC_D10, EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

45 K8 67 PE14 I/O FT -

46 L8 68 PE15 I/O FT -

47 K9 69 PB10 I/O

TIM1_CH4,

TIM1_BKIN2,

SPI1_MISO,

OCTOSPI1_IO2,

FMC_D11, EVENTOUT

TIM1_BKIN,

SPI1_MOSI,

OCTOSPI1_IO3,

FMC_D12, EVENTOUT

TIM2_CH3,

LPTIM3_OUT,

I2C4_SCL, I2C2_SCL,

SPI2_SCK,

USART3_TX,

LPUART1_RX,

TSC_SYNC,

OCTOSPI1_CLK,

COMP1_OUT,

SAI1_SCK_A,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

29 J2 H4 45 L9 67 22 22 30 48 L9 70 PB11 I/O

TIM2_CH4, I2C4_SDA,

I2C2_SDA,

USART3_RX,

LPUART1_TX,

OCTOSPI1_NCS,

COMP2_OUT,

EVENTOUT

69 -

VDDS

MPS

VLXS

MPS

L10

VSSS

MPS

VDD12

23 23 31 B2 31 B2 49 E9 71 23 23 31 49 E9 71 VSS S

32 J1 50 M11 72 -

V15S

MPS_

24 24 32 A1 33 A1 51 D4 73 24 24 32 50 D4 72 VDD S

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

L11

K10

25 25 33 51 L11 73 PB12 I/O FT -

26 26 34 52 K10 74 PB13 I/O

TIM1_BKIN,

I2C2_SMBA,

SPI2_NSS,

DFSDM1_DATIN1,

USART3_CK,

LPUART1_RTS/LPUA

RT1_DE,

TSC_G1_IO1,

OCTOSPI1_NCLK,

SAI2_FS_A,

TIM15_BKIN,

EVENTOUT

TIM1_CH1N,

LPTIM3_IN1,

I2C2_SCL, SPI2_SCK,

DFSDM1_CKIN1,

USART3_CTS/USART

3_NSS,

LPUART1_CTS,

TSC_G1_IO2,

UCPD1_FRSTX2,

SAI2_SCK_A,

TIM15_CH1N,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

K11

K12

L12

J10

K11

K12

PB14

PB15

I/O

_fd

55 L12 77 PD8 I/O FT -

56 J10 78 PD9 I/O FT -

TIM1_CH2N,

LPTIM3_ETR,

TIM8_CH2N,

I2C2_SDA,

SPI2_MISO,

DFSDM1_DATIN2,

USART3_RTS/USART

3_DE, TSC_G1_IO3,

SAI2_MCLK_A,

TIM15_CH1,

EVENTOUT

RTC_REFIN,

TIM1_CH3N,

TIM8_CH3N,

SPI2_MOSI,

DFSDM1_CKIN2,

SAI2_SD_A,

TIM15_CH2,

EVENTOUT

USART3_TX,

FMC_D13, EVENTOUT

USART3_RX,

FMC_D14,

SAI2_MCLK_A,

EVENTOUT

UCPD1_DB2

UCPD1_CC2

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

J11

J12

H11

83 -

J12

H11

PD10

PD12

PD13

VSS

I/O FT

58 J11 80 PD11 I/O FT -

I/O

USART3_CK,

TSC_G6_IO1,

FMC_D15,

SAI2_SCK_A,

EVENTOUT

I2C4_SMBA,

USART3_CTS/USART

3_NSS, TSC_G6_IO2,

FMC_A16,

SAI2_SD_A,

LPTIM2_ETR,

EVENTOUT

TIM4_CH1, I2C4_SCL,

USART3_RTS/USART

3_DE, TSC_G6_IO3,

FMC_A17, SAI2_FS_A,

LPTIM2_IN1,

EVENTOUT

TIM4_CH2, I2C4_SDA,

TSC_G6_IO4,

FMC_A18,

LPTIM2_OUT,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

61 H10 85

62 H12 86 -

G10 87 -

G11 88 -

G9 89 -

G12 90 -

84 VDD S -

61 H10 85 PD14 I/O FT -

62 H12 86 PD15 I/O FT -

G10 87

G11 88

G9 89

G12 90

PG2

PG3

PG4

PG5

I/O

TIM4_CH3, FMC_D0,

EVENTOUT

TIM4_CH4, FMC_D1,

EVENTOUT

SPI1_SCK, FMC_A12,

SAI2_SCK_B,

EVENTOUT

SPI1_MISO, FMC_A13,

SAI2_FS_B,

EVENTOUT

SPI1_MOSI, FMC_A14,

SAI2_MCLK_B,

EVENTOUT

SPI1_NSS,

LPUART1_CTS,

FMC_A15,

SAI2_SD_B,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

F9 91 -

F10 92 -

F12 93

95 -

91 PG6 I/O

F12 93 PG8 I/O

94 VSS S

VDDIO

F10 92 PG7 I/O

_fs

OCTOSPI1_DQS,

I2C3_SMBA,

LPUART1_RTS/LPUA

RT1_DE,

UCPD1_FRSTX1,

EVENTOUT

SAI1_CK1, I2C3_SCL,

DFSDM1_CKOUT,

LPUART1_TX,

UCPD1_FRSTX2,

FMC_INT,

SAI1_MCLK_A,

EVENTOUT

I2C3_SDA,

LPUART1_RX,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

37 E1 37 E1 63 F11 96 -

38 E2 38 E2 64 E10 97 -

39 F3 39 F3 65 E12 98 -

37 63 F11 96 PC6 I/O FT -

38 64 E10 97 PC7 I/O FT -

39 65 E12 98 PC8 I/O FT -

TIM3_CH1, TIM8_CH1,

DFSDM1_CKIN3,

SDMMC1_D0DIR,

TSC_G4_IO1,

SDMMC1_D6,

SAI2_MCLK_A,

EVENTOUT

TIM3_CH2, TIM8_CH2,

DFSDM1_DATIN3,

SDMMC1_D123DIR,

TSC_G4_IO2,

SDMMC1_D7,

SAI2_MCLK_B,

EVENTOUT

TIM3_CH3, TIM8_CH3,

TSC_G4_IO3,

SDMMC1_D0,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

66 E11 99

67 D12 100

66 E11 99

67 D12 100

PC9

PA8

I/O

30 30 42 D1 42 D1 68 D10 101 30 30 42 68 D10 101 PA9 I/O

_fu

31 31 43 E3 43 E3 69 D11 102 31 31 43 69 D11 102 PA10 I/O

_fu

TRACED0,

TIM8_BKIN2,

TIM3_CH4, TIM8_CH4,

TSC_G4_IO4,

USB_NOE,

SDMMC1_D1,

SAI2_EXTCLK,

EVENTOUT

MCO, TIM1_CH1,

SAI1_CK2,

USART1_CK,

SAI1_SCK_A,

LPTIM2_OUT,

EVENTOUT

TIM1_CH2, SPI2_SCK,

USART1_TX,

SAI1_FS_A,

TIM15_BKIN,

EVENTOUT

TIM1_CH3, SAI1_D1,

USART1_RX,

CRS_SYNC,

SAI1_SD_A,

TIM17_BKIN,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

70 C12 103

71 B12 104

70 C12 103

71 B12 104

PA11

PA12

I/O

34 34 46 D2 46 D2 72 C10 105 34 34 46 72 C10 105

47 47 47 -

PA13

(JTMS/

SWDI

I/O FT

VSS S -

A12 106

H4 107

D9 108

36 -

48 73 A12 106

VDDU

74 H4 107 VSS S

75 D9 108 VDD S

(3)

TIM1_CH4,

TIM1_BKIN2,

SPI1_MISO,

USART1_CTS/USART

1_NSS, FDCAN1_RX,

USB_DM, EVENTOUT

TIM1_ETR,

SPI1_MOSI,

USART1_RTS/USART

1_DE, FDCAN1_TX,

USB_DP, EVENTOUT

JTMS/SWDIO,

IR_OUT, USB_NOE,

SAI1_SD_B,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

C11 109

A11 110

B11 111

C11 109

A11 110

B11 111

PA14

(JTCK/

SWCL

PA15

(JTDI)

PC10

I/O FT

I/O

I/O FT

JTCK/SWCLK,

LPTIM1_OUT,

I2C1_SMBA,

I2C4_SMBA,

SAI1_FS_B,

EVENTOUT

JTDI, TIM2_CH1,

TIM2_ETR,

USART2_RX,

SPI1_NSS, SPI3_NSS,

USART3_RTS/USART

3_DE,

UART4_RTS/UART4_

DE, SAI2_FS_B,

EVENTOUT

TRACED1,

LPTIM3_ETR,

SPI3_SCK,

USART3_TX,

UART4_TX,

TSC_G3_IO2,

SDMMC1_D2,

SAI2_SCK_B,

EVENTOUT

UCPD1_CC1

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

52 C3 52 C3 79 A10 112 -

53 B3 53 B3 80 B10 113 -

81 C9 114 -

82 B9 115 -

52 79 A10 112 PC11 I/O FT -

53 80 B10 113 PC12 I/O FT -

81 C9 114 PD0 I/O FT -

82 B9 115 PD1 I/O FT -

LPTIM3_IN1,

OCTOSPI1_NCS,

SPI3_MISO,

USART3_RX,

UART4_RX,

TSC_G3_IO3,

UCPD1_FRSTX2,

SDMMC1_D3,

SAI2_MCLK_B,

EVENTOUT

TRACED3,

SPI3_MOSI,

USART3_CK,

UART5_TX,

TSC_G3_IO4,

SDMMC1_CK,

SAI2_SD_B,

EVENTOUT

SPI2_NSS,

FDCAN1_RX,

FMC_D2, EVENTOUT

SPI2_SCK,

FDCAN1_TX,

FMC_D3, EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

A9 116

84 C8 117 -

85 B8 118 -

86 A8 119 -

120 -

121 -

54 83 A9 116 PD2 I/O FT -

84 C8 117 PD3 I/O FT -

85 B8 118 PD4 I/O FT -

86 A8 119 PD5 I/O FT -

120

121

VSS

VDD

TRACED2, TIM3_ETR,

USART3_RTS/USART

3_DE, UART5_RX,

TSC_SYNC,

SDMMC1_CMD,

EVENTOUT

SPI2_SCK,

SPI2_MISO,

DFSDM1_DATIN0,

USART2_CTS/USART

2_NSS, FMC_CLK,

EVENTOUT

SPI2_MOSI,

DFSDM1_CKIN0,

USART2_RTS/USART

2_DE, OCTOSPI1_IO4,

FMC_NOE,

EVENTOUT

USART2_TX,

OCTOSPI1_IO5,

FMC_NWE,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

D4 -

A7 122

D7 123

B7 124

C4 C4 C7 125 -

87 A7 122 PD6 I/O FT -

88 D7 123 PD7 I/O FT -

B7 124

C7 125

PG9

PG10

I/O

SAI1_D1, SPI3_MOSI,

DFSDM1_DATIN1,

USART2_RX,

OCTOSPI1_IO6,

FMC_NWAIT,

SAI1_SD_A,

EVENTOUT

DFSDM1_CKIN1,

USART2_CK,

OCTOSPI1_IO7,

FMC_NCE/FMC_NE1,

EVENTOUT

SPI3_SCK,

USART1_TX,

FMC_NCE/FMC_NE2,

SAI2_SCK_A,

TIM15_CH1N,

EVENTOUT

LPTIM1_IN1,

SPI3_MISO,

USART1_RX,

FMC_NE3,

SAI2_FS_A,

TIM15_CH1,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

D5 -

B8 -

A5 -

D5 -

126

127 -

128

H9 129

D8 130 -

M11 126

127

128

PG11

PG12

PG13

I/O

_fs

M9 129 PG14 I/O

_fs

H9 130 VSS S

D8 131

VDDIO

S -

LPTIM1_IN2,

OCTOSPI1_IO5,

SPI3_MOSI,

USART1_CTS/USART

1_NSS,

SAI2_MCLK_A,

TIM15_CH2,

EVENTOUT

LPTIM1_ETR,

SPI3_NSS,

USART1_RTS/USART

1_DE, FMC_NE4,

SAI2_SD_A,

EVENTOUT

I2C1_SDA,

USART1_CK,

FMC_A24, EVENTOUT

I2C1_SCL, FMC_A25,

EVENTOUT

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

131

C6 132

B4 132

C6 133

PG15

PB3

(JTDO/

TRAC

ESWO

)

I/O

40 40 55 B6 56 B6 90 B6 133 40 40 56 90 B6 134

PB4

(NJTR

ST)

I/O

_fa

Table 96 represent the total MCU consumption

LPTIM1_OUT,

I2C1_SMBA,

EVENTOUT

JTDO/TRACESWO,

TIM2_CH2, SPI1_SCK,

SPI3_SCK,

USART1_RTS/USART

1_DE, CRS_SYNC,

SAI1_SCK_B,

EVENTOUT

NJTRST, TIM3_CH1,

I2C3_SDA,

SPI1_MISO,

SPI3_MISO,

USART1_CTS/USART

1_NSS,

UART5_RTS/UART5_

DE, TSC_G2_IO1,

SAI1_MCLK_B,

TIM17_BKIN,

EVENTOUT

COMP2_INM

COMP2_INP

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

41 41 56 A6 57 A6 91 D6 134 41 41 57 91 D6 135 PB5 I/O

42 42 57 C6 58 C6 92 A5 135 42 42 58 92 A5 136 PB6 I/O

_fa

LPTIM1_IN1,

TIM3_CH2,

OCTOSPI1_NCLK,

I2C1_SMBA,

SPI1_MOSI,

SPI3_MOSI,

USART1_CK,

UART5_CTS/UART5_

NSS, TSC_G2_IO2,

COMP2_OUT,

SAI1_SD_B,

TIM16_BKIN,

EVENTOUT

LPTIM1_ETR,

TIM4_CH1,

TIM8_BKIN2,

I2C1_SCL, I2C4_SCL,

USART1_TX,

TSC_G2_IO3,

SAI1_FS_B,

TIM16_CH1N,

EVENTOUT

UCPD1_DB1

COMP2_INP

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

43 43 58 D6 59 D6 93 D5 136 43 43 59 93 D5 137 PB7 I/O

_fa

44 44 59 D7 60 D7 94 B5 137 44 44 60 94 B5 138

PH3-

BOOT

I/O FT -

LPTIM1_IN2,

TIM4_CH2,

TIM8_BKIN,

I2C1_SDA, I2C4_SDA,

USART1_RX,

UART4_CTS,

TSC_G2_IO4,

FMC_NL,

TIM17_CH1N,

EVENTOUT

45 45 60 C7 61 C7 95 C5 138 45 45 61 95 C5 139 PB8 I/O

TIM4_CH3, SAI1_CK1,

I2C1_SCL,

DFSDM1_CKOUT,

SDMMC1_CKIN,

FDCAN1_RX,

SDMMC1_D4,

SAI1_MCLK_A,

TIM16_CH1,

EVENTOUT

COMP2_INM,

PVD_IN

STM32L552xxxxP

Pin Number

Table 21. STM32L552xx pin definitions (continued)

STM32L552xxxxQ STM32L552xx

Alternate functions

Additional functions

139

C4 140

141

140

PB9

VDD12

I/O

47 47 63 E8 62 E8 98 E4 142 47 47 63 99 E4 143 VSS S

63 A8 99 B4 143 -

V15S

MPS_

48 48 64 F9 64 F9 100 J9 144 48 48 64 100 J9 144 VDD S

97 C4 141 PE0 I/O FT -

98 A3 142 PE1 I/O FT -

IR_OUT, TIM4_CH4,

SAI1_D2, I2C1_SDA,

SPI2_NSS,

SDMMC1_CDIR,

FDCAN1_TX,

SDMMC1_D5,

SAI1_FS_A,

TIM17_CH1,

EVENTOUT

TIM4_ETR,

FMC_NBL0,

TIM16_CH1,

EVENTOUT

FMC_NBL1,

TIM17_CH1,

EVENTOUT

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (for example to drive a LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0438 reference manual.

3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

Port

PA7

PA8

PA9

PA10

PA11

PA1

PA2

PA3

PA4

PA5

PA6

Port

PA0

AF0

SYS_AF

MCO

AF1

TIM1/2/5/8/L

PTIM1

TIM2_CH1

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_CH1

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

PA12 TIM1_ETR

PA13 JTMS/SWDIO IR_OUT

PA14 JTCK/SWCLK LPTIM1_OUT

PA15 JTDI TIM2_CH1

Table 22. Alternate function AF0 to AF7 (1)

AF2 AF3 AF4

TIM1/2/3/4/5/

LPTIM3

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

I2C1/2/3/4

AF5

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

AF6

SPI3/I2C3/DFS

DM1/COMP1/

AF7

USART1/2/3

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

TIM2_ETR

TIM3_CH1

TIM3_CH2

TIM1_BKIN2

TIM2_ETR

TIM8_ETR

SAI1_CK1

OCTOSPI1_NCS

TIM8_CH1N

TIM8_BKIN

TIM8_CH1N

SAI1_CK2

SPI2_SCK

SAI1_D1

USART2_RX

I2C1_SMBA

I2C3_SCL

I2C1_SMBA

SPI1_SCK

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI1_MISO

SPI1_MOSI

I2C4_SMBA

SPI1_NSS

SPI3_NSS

USART2_CTS_

NSS

USART2_RTS_

USART2_TX

USART2_RX

USART2_CK

USART3_CTS_

NSS

USART1_CK

USART1_TX

USART1_RX

USART1_CTS_

NSS

USART1_RTS_

USART3_RTS_

Port

PB0

PB1

PB2

PB3

JTDO/TRACE

SWO

PB4

PB5

PB6

PB7

Port

PB8

PB9

PB10

PB11

PB12

PB13

PB14

AF0

SYS_AF

NJTRST

AF1

TIM1/2/5/8/L

PTIM1

TIM1_CH2N

TIM1_CH3N

LPTIM1_OUT

TIM2_CH2

LPTIM1_IN1

LPTIM1_ETR

LPTIM1_IN2

IR_OUT

TIM2_CH3

TIM2_CH4

TIM1_BKIN

Table 22. Alternate function AF0 to AF7 (1) (continued)

AF2

TIM1/2/3/4/5/

LPTIM3

TIM3_CH3

TIM3_CH4

TIM3_CH1

TIM3_CH2

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

LPTIM3_OUT

TIM1_CH1N LPTIM3_IN1

TIM1_CH2N LPTIM3_ETR

PB15 RTC_REFIN TIM1_CH3N -

AF3

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

TIM8_CH2N

TIM8_CH3N

OCTOSPI1_NCLK

TIM8_BKIN2

TIM8_BKIN

SAI1_CK1

SAI1_D2

I2C4_SCL

I2C4_SDA

TIM1_BKIN

TIM8_CH2N

TIM8_CH3N

AF4

I2C1/2/3/4

I2C1_SMBA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C3_SMBA

I2C3_SDA

I2C1_SCL

I2C2_SMBA

I2C2_SCL

I2C2_SDA

AF5 AF6 AF7

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

SPI3/I2C3/DFS

DM1/COMP1/

USART1/2/3

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

I2C4_SCL

I2C4_SDA

DFSDM1_CKOU

SPI2_NSS

SPI2_SCK

SPI2_NSS

SPI2_SCK

SPI2_MISO

SPI2_MOSI

DFSDM1_DATI

DFSDM1_CKI

USART3_CK

USART3_RTS_

SPI3_SCK

SPI3_MISO

SPI3_MOSI

USART1_RTS_

USART1_CTS_

NSS

USART1_CK

USART1_TX

USART1_RX

USART3_TX

DFSDM1_DATI

DFSDM1_CKI

DFSDM1_DATI

DFSDM1_CKI

USART3_RX

USART3_CK

USART3_CTS_

NSS

USART3_RTS_

Port

PC0

PC1

PC2

PC3

PC4

PC5

PC6 -

Port

PC7 -

PC8 -

PC9 TRACED0

PC10 TRACED1

PC11 -

PC12 TRACED3

PC13

PC14

PC15

AF0

SYS_AF

LPTIM1_IN1

TRACED0 LPTIM1_OUT

AF1

TIM1/2/5/8/L

PTIM1

LPTIM1_IN2

LPTIM1_ETR LPTIM3_OUT

TIM8_BKIN2

Table 22. Alternate function AF0 to AF7 (1) (continued)

AF2

TIM1/2/3/4/5/

LPTIM3

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

LPTIM3_ETR

LPTIM3_IN1

AF3

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

OCTOSPI1_IO7

SPI2_MOSI

SAI1_D1

SAI1_D3

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH4

AF4

I2C1/2/3/4

I2C3_SCL

I2C3_SDA

AF5 AF6

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

SPI3/I2C3/DFS

DM1/COMP1/

SPI2_MISO

DFSDM1_CKO

SPI2_MOSI

DFSDM1_CKI

DFSDM1_DATI

SPI3_SCK

OCTOSPI1_NCS SPI3_MISO

SPI3_MOSI

AF7

USART1/2/3

USART3_TX

USART3_RX

USART3_TX

USART3_RX

USART3_CK

Port

PD0

PD1

PD2

PD3

PD4

PD5

PD6

Port

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

AF0

SYS_AF

TRACED2

AF1

TIM1/2/5/8/L

PTIM1

Table 22. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM1/2/3/4/5/

LPTIM3

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

I2C1/2/3/4

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

SPI2_NSS

SPI2_SCK

TIM3_ETR

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

SPI2_SCK

SAI1_D1

I2C4_SMBA

I2C4_SCL

I2C4_SDA

SPI2_MOSI

SPI3_MOSI

SPI2_MISO

AF6

SPI3/I2C3/DFS

DM1/COMP1/

AF7

USART1/2/3

USART3_RTS_

DFSDM1_DATI

USART2_CTS_

NSS

DFSDM1_CKI

DFSDM1_DATI

DFSDM1_CKI

USART2_RTS_

USART2_TX

USART2_RX

USART2_CK

USART3_TX

USART3_RX

USART3_CK

USART3_CTS_

NSS

USART3_RTS_

Port

PE5

PE6

Port

PE7

PE8

PE0

PE1

PE2

PE3

PE4

PE9

PE10

PE11

PE12

PE13

PE14

PE15

AF0

SYS_AF

TRACECK

TRACED0

TRACED1

TRACED2

TRACED3

AF1

TIM1/2/5/8/L

PTIM1

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

Table 22. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM1/2/3/4/5/

LPTIM3

TIM4_ETR

TIM3_ETR

TIM3_CH1

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

SAI1_CK1

OCTOSPI1_DQS

I2C1/2/3/4

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM1_BKIN2

SAI1_D2

SAI1_CK2

SAI1_D1

TIM1_BKIN2

TIM1_BKIN

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

AF6

SPI3/I2C3/DFS

DM1/COMP1/

DFSDM1_DATI

DFSDM1_CKI

DFSDM1_DATI

DFSDM1_CKI

DFSDM1_CKO

AF7

USART1/2/3

AF0

Port

Port

PF4

PF5

PF6

PF7

PF8

PF9

PF0

PF1

PF2

PF3

PF10

PF11

PF12

PF13

PF14

PF15

SYS_AF

TIM5_ETR

AF1

TIM1/2/5/8/L

PTIM1

Table 22. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM1/2/3/4/5/

LPTIM3

LPTIM3_IN1

LPTIM3_ETR

LPTIM3_OUT

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

I2C1/2/3/4

I2C2_SDA

I2C2_SCL

I2C2_SMBA

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

OCTOSPI1_CLK

OCTOSPI1_NCLK

I2C4_SMBA

I2C4_SCL

I2C4_SDA

AF6

SPI3/I2C3/DFS

DM1/COMP1/

DFSDM1_CKO

AF7

USART1/2/3

Port

PG8

Port

PG9

PG1

PG11

PG1

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

AF0

SYS_AF

LPTIM1_IN1

AF1

TIM1/2/5/8/L

PTIM1

LPTIM1_IN2

LPTIM1_ETR

Table 22. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM1/2/3/4/5/

LPTIM3

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

OCTOSPI1_DQS

I2C1/2/3/4

I2C3_SMBA

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI1_NSS

SAI1_CK1 I2C3_SCL -

I2C3_SDA

AF6

SPI3/I2C3/DFS

DM1/COMP1/

OCTOSPI1_IO5

I2C1_SDA -

AF7

USART1/2/3

DFSDM1_CKO

SPI3_SCK

SPI3_MISO

SPI3_MOSI

SPI3_NSS

USART1_TX

USART1_RX

USART1_CTS_

NSS

USART1_RTS_

USART1_CK

I2C1_SCL -

LPTIM1_OUT I2C1_SMBA -

Port

AF0

SYS_AF

AF1

TIM1/2/5/8/L

PTIM1

Port

PH0

PH1

PH3

1. Refer to

Table 23

for AF8 to AF15.

Table 22. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

TIM1/2/3/4/5/

LPTIM3

SPI2/SAI1/I2C4/

USART2/TIM1/8/

OCTOSPI1

I2C1/2/3/4

SPI1/2/3/I2C4/

DFSDM1/

OCTOSPI1

AF6

SPI3/I2C3/DFS

DM1/COMP1/

AF7

USART1/2/3

Port

PA0

PA1

PA2

PA3

PA4

PA5

PA6

Port

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

AF8 AF9

Table 23. Alternate function AF8 to AF15 (1)

AF10 AF11 AF12 AF13

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

UART4_TX

UART4_RX

LPUART1_TX

LPUART1_RX

LPUART1_CTS

_NSS

UART4_RTS_D

FDCAN1_

USB/OCTOSPI1 UCPD1

OCTOSPI1_DQS -

OCTOSPI1_NCS UCPD1_FRSTX1

OCTOSPI1_CLK

SDMMC1/COMP1

/2/TIM1/8/FMC

SAI1/2/TIM8

SAI1_EXTCLK

SAI2_EXTCLK

SAI1_MCLK_A

SAI1_FS_B

OCTOSPI1_IO3

OCTOSPI1_IO2

CRS_SYNC

USB_DM

USB_DP

USB_NOE

TIM1_BKIN

TIM1_BKIN2

TIM8_BKIN

SAI1_SCK_A

SAI1_FS_A

SAI1_SD_A

SAI1_SD_B

SAI1_FS_B

SAI2_FS_B

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

EVENTOUT

TIM2_ETR EVENTOUT

TIM15_CH1N EVENTOUT

TIM15_CH1 EVENTOUT

TIM15_CH2 EVENTOUT

LPTIM2_OUT EVENTOUT

LPTIM2_ETR EVENTOUT

TIM16_CH1

TIM17_CH1 EVENTOUT

LPTIM2_OUT EVENTOUT

TIM15_BKIN EVENTOUT

TIM17_BKIN EVENTOUT

EVENTOUT

AF8 AF9

Table 23. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11

Port

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

USB/OCTOSPI1 UCPD1

Port

PB0

PB1

PB2

PB3

PB4

PB5

LPUART1_RTS_

UART5_RTS_D

UART5_CTS_N

TSC_G2_

IO1

TSC_G2_

IO2

PB6

PB7

UART4_CTS_N

TSC_G2_

IO3

TSC_G2_

IO4

PB8 SDMMC1_CKIN

PB9 SDMMC1_CDIR

FDCAN1_

PB10 LPUART1_RX

TSC_SY

PB11 LPUART1_TX

PB12

LPUART1_RTS_

PB13

LPUART1_CTS

_NSS

PB14

PB15 -

TSC_G1_

IO1

TSC_G1_

IO2

TSC_G1_

IO3

OCTOSPI1_IO1

OCTOSPI1_IO0

OCTOSPI1_DQS

CRS_SYNC

OCTOSPI1_CLK

OCTOSPI1_NCS

OCTOSPI1_NCLK

UCPD1_FRSTX1

UCPD1_FRSTX2

AF12

SDMMC1/COMP1

/2/TIM1/8/FMC

COMP1_OUT

COMP2_OUT

TIM8_BKIN2

FMC_NL

SDMMC1_D4

SDMMC1_D5

COMP1_OUT

COMP2_OUT

AF13

SAI1/2/TIM8

SAI1_EXTCLK

SAI1_SCK_B

SAI1_MCLK_B

SAI1_SD_B

SAI1_FS_B

TIM8_BKIN

SAI1_MCLK_A

SAI1_FS_A

SAI1_SCK_A

SAI2_FS_A

SAI2_SCK_A

SAI2_MCLK_A

SAI2_SD_A

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

EVENTOUT

EVENTOUT

LPTIM2_IN1

TIM17_BKIN

TIM16_BKIN

EVENTOUT

TIM16_CH1N EVENTOUT

TIM17_CH1N EVENTOUT

TIM16_CH1

TIM17_CH1

TIM15_BKIN

EVENTOUT

TIM15_CH1N EVENTOUT

TIM15_CH1

TIM15_CH2

EVENTOUT

AF8 AF9

Port

Port

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

LPUART1_RX

LPUART1_TX

SDMMC1_D0DI

SDMMC1_D123

DIR

UART4_TX

UART4_RX

UART5_TX

TSC_G3_

IO1

TSC_G1_

IO4

TSC_G4_

IO1

TSC_G4_

IO2

TSC_G4_

IO3

TSC_G4_

IO4

TSC_G3_

IO2

TSC_G3_

IO3

TSC_G3_

IO4

Table 23. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

USB/OCTOSPI1

OCTOSPI1_IO4

OCTOSPI1_IO5

OCTOSPI1_IO6

OCTOSPI1_IO7

USB_NOE

UCPD1

UCPD1_FRSTX2

SDMMC1/COMP1

/2/TIM1/8/FMC

SDMMC1_D5

SDMMC1_D6

SDMMC1_D7

SDMMC1_D0

SDMMC1_D1

SDMMC1_D2

SDMMC1_D3

SDMMC1_CK

SAI1/2/TIM8

SAI2_FS_A

SAI1_SD_A

SAI2_MCLK_A

SAI2_MCLK_B

SAI2_EXTCLK

SAI2_SCK_B

SAI2_MCLK_B

SAI2_SD_B

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

LPTIM2_IN1

EVENTOUT

EVENTOUT

LPTIM2_ETR EVENTOUT

TIM8_BKIN2

EVENTOUT

Port

PD0

PD1

PD2

PD3

PD4

PD5

PD6

Port

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

AF8 AF9

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

UART5_RX

FDCAN1_

TSC_SY

Table 23. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

USB/OCTOSPI1

OCTOSPI1_IO4

OCTOSPI1_IO5

OCTOSPI1_IO6

OCTOSPI1_IO7

UCPD1

SDMMC1/COMP1

/2/TIM1/8/FMC

FMC_D2

FMC_D3

SDMMC1_CMD

SAI1/2/TIM8

FMC_CLK

FMC_NOE

FMC_NWE

FMC_NWAIT

FMC_NCE/FMC_

NE1

FMC_D13

FMC_D14

SAI1_SD_A

SAI2_MCLK_A

TSC_G6_

IO1

TSC_G6_

IO2

TSC_G6_

IO3

TSC_G6_

IO4

FMC_D15

FMC_A16

FMC_A17

FMC_A18

FMC_D0

FMC_D1

SAI2_SCK_A

SAI2_SD_A

SAI2_FS_A

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

EVENTOUT

EVENTOUT

LPTIM2_ETR EVENTOUT

LPTIM2_IN1

LPTIM2_OUT EVENTOUT

EVENTOUT

Port

Port

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

AF8 AF9

Table 23. Alternate function AF8 to AF15 (1) (continued)

AF10

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

USB/OCTOSPI1

TSC_G5_

IO1

TSC_G5_

IO2

TSC_G5_

IO3

TSC_G5_

IO4

TSC_G7_

IO1

TSC_G7_

IO2

TSC_G7_

IO3

TSC_G7_

IO4

OCTOSPI1_NCLK

OCTOSPI1_CLK

OCTOSPI1_NCS

OCTOSPI1_IO0

OCTOSPI1_IO1

OCTOSPI1_IO2

OCTOSPI1_IO3

AF11

UCPD1

AF12

SDMMC1/COMP1

/2/TIM1/8/FMC

FMC_NBL0

FMC_NBL1

FMC_A23

FMC_A19

FMC_A20

FMC_A21

FMC_A22

FMC_D4

FMC_D5

FMC_D6

FMC_D7

FMC_D8

FMC_D9

FMC_D10

FMC_D11

FMC_D12

AF13

SAI1/2/TIM8

SAI1_SD_A

SAI1_SD_B

SAI1_SCK_B

SAI1_FS_B

SAI1_MCLK_A

SAI1_SD_B

SAI1_FS_A

SAI1_SCK_A

SAI1_MCLK_B

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

TIM16_CH1

TIM17_CH1

EVENTOUT

EVENTOUT

Port

Port

PF7

PF8

PF9

PF10

PF11

PF12

PF13

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF14

PF15

AF8 AF9

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

TSC_G8_

IO1

TSC_G8_

IO2

Table 23. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

USB/OCTOSPI1

OCTOSPI1_IO3

OCTOSPI1_IO2

OCTOSPI1_IO0

OCTOSPI1_IO1

UCPD1

SDMMC1/COMP1

/2/TIM1/8/FMC

FMC_A0

FMC_A1

FMC_A2

FMC_A3

FMC_A4

FMC_A5

FMC_A6

FMC_A7

SAI1/2/TIM8

SAI1_SD_B

SAI1_MCLK_B

SAI1_SCK_B

SAI1_FS_B

SAI1_D3

FMC_A8

FMC_A9 -

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

TIM15_CH1

TIM15_CH2

EVENTOUT

EVENTOUT

AF8 AF9

Port

Port

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

PG0

PG1 -

PG2

PG3

PG4 -

PG5

PG6

LPUART1_CTS

_NSS

LPUART1_RTS_

PG7 LPUART1_TX

PG8 LPUART1_RX

TSC_G8_

IO3

TSC_G8_

IO4

Table 23. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

USB/OCTOSPI1

UCPD1

UCPD1_FRSTX1

SDMMC1/COMP1

/2/TIM1/8/FMC

FMC_A10

FMC_A11

FMC_A12

FMC_A13

FMC_A14

FMC_A15

SAI1/2/TIM8

SAI2_SCK_B

SAI2_FS_B

SAI2_MCLK_B

SAI2_SD_B

SAI1_MCLK_A

PG9

PG10

PG11

PG12

PG13

PG14

PG15

UCPD1_FRSTX2

FMC_INT

FMC_NCE/FMC_

NE2

FMC_NE3

FMC_NE4

FMC_A24

FMC_A25

SAI2_SCK_A

SAI2_FS_A

SAI2_MCLK_A

SAI2_SD_A

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

EVENTOUT

TIM15_CH1N EVENTOUT

TIM15_CH1

TIM15_CH2

EVENTOUT

AF8 AF9

Port

UART4/5/LPUA

RT1/SDMMC1

FDCAN1/

TSC

Port

PH0

PH1

PH3 -

1. Refer to

Table 22

for AF0 to AF7.

Table 23. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

USB/OCTOSPI1

UCPD1

SDMMC1/COMP1

/2/TIM1/8/FMC

SAI1/2/TIM8

AF14 AF15

TIM2/8/15/16/17/

LPTIM2

EVENTOUT

EVENTOUT

Electrical characteristics STM32L552xx

5.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 25

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 26 .

Figure 25. Pin loading conditions Figure 26. Pin input voltage

MCU pin MCU pin

C = 50 pF

MS19210V1

MS19211V1

138/340 DS12737 Rev 6

STM32L552xx

5.1.6

Electrical characteristics

Power supply scheme

Figure 27. STM32L552xx and STM32L562xx power supply overview

VBAT

1.55 – 3.6 V

Backup circuitry

(LSE, RTC,

Backup registers)

Power switch

DD V

CORE n x VDD n x 100 nF

+1 x 4.7 μF

GPIOs m x100 nF

+4.7 μF n x VSS

DDIO2 m x VDDIO2

GPIOs m x VSS

Regulator

DDIO1

OUT

DDIO2

OUT

IO logic

Kernel logic

(CPU, Digital

& Memories)

IO logic

10 nF

+1 μF

DDA

REF

VDDA

100 nF +1 μF

REF+

REF-

ADCs/

DACs/

OPAMPs/

COMPs/

VREFBUF

VSSA

MSv62917V1

DS12737 Rev 6 139/340

307

Electrical characteristics STM32L552xx

Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview

VBAT

1.55 – 3.6 V

Backup circuitry

(LSE, RTC,

Backup registers)

Power switch

2 x VDD12

1.05 – 1.32 V

DD n x VDD

CORE n x 100 nF

+1 x 4.7 μF

GPIOs n x VSS m x100 nF

+4.7 μF

DDIO2 m x VDDIO2

GPIOs m x VSS

Regulator

DDIO1

OUT

DDIO2

OUT

IO logic

Kernel logic

(CPU, Digital

& Memories)

IO logic

Note:

10 nF

+1 μF

DDA

REF

VDDA

100 nF +1 μF

REF+

REF-

ADCs/

DACs/

OPAMPs/

COMPs/

VREFBUF

VSSA

MSv62918V1

If the selected package has the external SMPS option but no external SMPS is used by the application (the embedded LDO is used instead), the VDD12 pins are kept unconnected.

140/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview

VBAT

1.55 – 3.6 V

Backup circuitry

(LSE, RTC,

Backup registers)

Power switch

VDDSMPS

VLXSMPS

2 x V15SMPS

VSSSMPS

SMPS

DD V

CORE n x VDD

Regulator

DDIO1

OUT n x 100 nF

+1 x 4.7 μF

GPIOs

IO logic

Kernel logic

(CPU, Digital

& Memories) n x VSS m x100 nF

+4.7 μF

DDIO2 m x VDDIO2

GPIOs m x VSS

DDIO2

OUT

IO logic

10 nF

+1 μF

DDA

REF

VDDA

100 nF +1 μF

REF+

REF-

ADCs/

DACs/

OPAMPs/

COMPs/

VREFBUF

VSSA

MSv62919V1

Note:

1. Refer to Figure 3

for SMPS step down converter power supply scheme.

If the selected package has the SMPS step down converter option but the application does not ever use the SMPS, it is recommended to set the SMPS power supply pins as follows:

VDDSMPS and VLXSMPS connected to VSS

V15SMPSconnected to VDD.

Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DS12737 Rev 6 141/340

307

Electrical characteristics STM32L552xx

The I

DD_ALL

parameters given in

Table 33 to

including the current supplying V

DD device embeds the SMPS.

, V

DDIO2

, V

DDA

, V

DDUSB

, V

BAT

and V

DDSMPS

if the

Figure 30. Current consumption measurement

BAT

5.2

DDA

DDUSB

DDSMPS

DDIO2

MSv62920V1

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 24: Voltage characteristics

Table 25: Current characteristics

and

Table 26: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol

DDX

- V

DD12

- V

Table 24. Voltage characteristics (1)

Ratings Min

External main supply voltage (including V

DDA

, V

DDIO2

REF+

)

, V

DDUSB

, V

BAT

, V

DDSMPS

External SMPS supply voltage

All ranges

0/1/2

-0.3

Max

4.0

1.4

Unit

(2)

Input voltage on FT_xxx pins except FT_c pins

Input voltage on FT_c pins

Input voltage on any other pins

-0.3

min (V

DDIO2

, V

DDA

DDUSB,

)

+ 4.0

5.5

4.0

142/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

Table 24. Voltage characteristics (1) (continued)

Ratings Min Max

REF+

- V

DDA

| ∆ V

SSx

DDx

-V

Allowed voltage difference for V

REF+

> V

DDA

Variations between different V

DDX pins of the same domain

power

Variations between all the different ground pins

(5)

0.4

1. All main power (V , V

DDA

, V , V

DDUSB

, V

BAT

) and ground (V

, V

SSA

) pins must always be

Unit

V mV

2. V

maximum must always be respected. Refer to

Table 25: Current characteristics for the maximum

allowed injected current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Table 25. Current characteristics

Symbol

∑

∑ IV

DD(PIN)

SS(PIN)

Ratings

Total current into sum of all V

power lines (source)

(1) (2)

Total current out of sum of all V

ground lines (sink)

(1) (2)

Maximum current into each V

power pin (source)

Maximum current out of each V

ground pin (sink)

Output current sunk by any I/O and control pin except FT_f

Max

160

100

IO(PIN)

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 20

∑ I

IO(PIN)

Total output current sunk by sum of all I/Os and control pins

(3)

Total output current sourced by sum of all I/Os and control pins

Voltage characteristics

100

Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0

(5)

INJ(PIN)

(4)

Injected current on PA4, PA5

∑ |I

INJ(PIN)

| Total injected current (sum of all I/Os and control pins) (6)

-5/0

+/-25

1. All main power (V , V

DDA

, V , V

DDUSB

, V

BAT

) and ground (V

, V

SSA

) pins must always be

Unit mA

2. Valid also for V

DD12

on SMPS package.

3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count

QFP packages.

4. Positive injection (when V

> V

DDIOx

) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. A negative injection is induced by V

< V

. I

INJ(PIN)

must never be exceeded. Refer also to

Table 24:

for the minimum allowed input voltage values.

6. When several inputs are submitted to a current injection, the maximum ∑ |I the negative injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of

DS12737 Rev 6 143/340

307

Electrical characteristics

Symbol

STG

STM32L552xx

Table 26. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

-65 to +150

150

Unit

°C

5.3.1 General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Table 27. General operating conditions

Parameter Conditions Min

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage -

1.71

(1)

DDSMPS

DD12

Supply voltage for the internal SMPS step-down converter

DDSMPS

= V

Standard operating voltage

Up to 110 MHz

Up to 80 MHz

Up to 26 MHz

1.71

1.14

1.08

1.05

(2)

DDIO2

DDA

PG[15:2] I/Os supply voltage

Analog supply voltage

At least one I/O in

PG[15:2] used

PG[15:2] not used

ADC or COMP used

DAC or OPAMP used

VREFBUF used

ADC, DAC, OPAMP,

COMP, VREFBUF not used

1.08

1.62

1.8

2.4

Max

110

3.6

1.32

3.6

Unit

MHz

3.6

144/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

BAT

Table 27. General operating conditions (continued)

Parameter Conditions Min

Backup operating voltage 1.55

Max

3.6

Unit

USB used 3.0

3.6

DDUSB

USB supply voltage V

USB not used 0 3.6

I/O input voltage

Power dissipation at

= 85 °C for suffix 6

(5)

Power dissipation at

= 125 °C for suffix 3

Thermal characteristics for

TT_xx I/O

FT_c I/O

All I/O except FT_c and

TT_xx

LQFP48

UFQFPN48

LQFP64

WLCSP81

LQFP100

UFBGA132

LQFP144

LQFP48

UFQFPN48

LQFP64

WLCSP81

LQFP100

UFBGA132

LQFP144

-0.3

DDIOx

+0.3

-0.3

MIN(MIN(V

DDA

, V

DDIO2

DDUSB

)

+3.6 V,

5.5 V)

(3)(4)

See Section 6.8:

application appropriate thermal resistance and package. Power dissipation is then calculated according ambient temperature

) and maximum junction temperature

) and selected thermal resistance.

See Section 6.8:

Thermal characteristics for

application appropriate thermal resistance and package. Power dissipation is then calculated according ambient temperature

) and maximum junction temperature

) and selected thermal resistance.

V mW mW

DS12737 Rev 6 145/340

307

Electrical characteristics

5.3.2

STM32L552xx

Symbol

Table 27. General operating conditions (continued)

Parameter Conditions Min Max Unit

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 3 version

Junction temperature range

Maximum power dissipation

Low-power dissipation

(6)

Maximum power dissipation

Low-power dissipation

software. Refer to Table 28: SMPS modes summary .

Suffix 6 version

Suffix 3 version

–40

105

125

130

105

130

°C

1. When RESET is released functionality is guaranteed down to V

BOR0

Min.

2. For Flash erase and program operation, V

DD12

min must be 1.08 V.

3. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between MIN(V

DDUSB

)+3.6 V and 5.5V.

, V

DDA

, V

DDIO2

4. For operation with voltage higher than Min (V

Pull-Down resistors must be disabled.

, V

DDA

, V

DDIO2

, V

DDUSB

) +0.3 V, the internal Pull-up and

5. If T

is lower, higher P characteristics ).

values are allowed as long as T

does not exceed T

Jmax

(see Section 7.7: Thermal

6. In low-power dissipation state, T

can be extended to this range as long as T

Section 7.7: Thermal characteristics ).

does not exceed T

Jmax

(see

SMPS step-down converter

The device embeds an SMPS step down converter which requires the external components shown in below figure.

Figure 31. External components for SMPS step down converter

SMPS Regulator

CORE

L = 4.7 μH typ

C = 4.7 μF typ

VDDSMPS

VLXSMPS

2 x V15SMPS

VSSSMPS

146/340

MSv62972V2

The following table summarizes the SMPS behavior depending on the main regulator range,

VDD and consumption.

DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 28. SMPS modes summary

SMPS mode

Ranges Max AHB clock V

CORE

≤ 2.05 V V

> 2.05 V

Range 0

Range 1

Range 2

110 MHz

80 MHz

26 MHz

1.28 V

1.2 V

1.0 V

Automatic Bypass mode

15SMPS

= V

Automatic Bypass mode

15SMPS

= V

Software Bypass mode

(1)

15SMPS

= V

HP mode

Max current consumption = 120 mA

15SMPS

= 1.6 V

HP mode

Max current consumption = 80 mA

15SMPS

= 1.5 V

LP mode or HP mode

Max current consumption = 30 mA

15SMPS

= 1.3 V

1. There is no automatic SMPS bypass in Range 2. The user application should use PVD0 to monitor V the SMPS Bypass mode.

supply and request

Symbol

Table 29. SMPS characteristics

(1)

Parameter Conditions Min

VDDSMPS SMPS power supply

V15SMPS SMPS output voltage

Range 0

Range 1

Range 2

1.71

(2)

1.55

1.45

1.25

Typ

1.6

1.5

1.3

Max

3.6

1.65

1.55

1.35

Unit

SMPS output slew rate

Fast startup disabled

SMPSFSTEN = 0

Fast startup enabled

SMPSFSTEN = 1

600

120 -

1. Guaranteed by design.

2. When VDDSMPS is less than 2.05V, the SMPS bypass mode is forced by hardware in Range 0 and

Range 1. In Range 2, there is no automatic switch into SMPS bypass mode. It should be requested by

µs/V

DS12737 Rev 6 147/340

307

Electrical characteristics STM32L552xx

5.3.4

The parameters given in

Table 30 are derived from tests performed under the ambient

temperature condition summarized in

Table 27 .

Symbol

Table 30. Operating conditions at power-up / power-down

(1)

Parameter Conditions t t t t

VDD

VDDA

VDDUSB

VDDIO2

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

DDUSB

rise time rate

DDUSB

fall time rate

DDIO2

rise time rate

DDIO2

fall time rate

1. At power-up, the V

DD12

voltage should not be forced externally.

Min

Max

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in

Table 31 are derived from tests performed under the ambient

temperature conditions summarized in Table 27: General operating conditions

Table 31. Embedded reset and power control block characteristics

Symbol Parameter Conditions

(1)

Min Typ Max t

RSTTEMPO

(2)

Reset temporization after

BOR0 is detected

DD rising 250 400

BOR0

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.76

2.1

2.26

2.15

1.62

1.6

2.06

1.96

2.26

2.16

2.56

2.47

2.85

2.81

2.15

2.05

2.31

2.20

1.66

1.64

2.1

2.31

2.20

2.61

2.52

2.90

2.86

2.19

2.1

2.36

2.25

1.7

1.69

2.14

2.04

2.35

2.24

2.66

2.57

2.95

Unit

μ s

148/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 31. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

PVD2

PVD3

PVD4

PVD5

PVD6 hyst_BORH0

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage of BORH0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Hysteresis in continuous mode

Hysteresis in other mode

V hyst_BOR_PVD

(BOR_PVD)

PVM3

Hysteresis voltage of BORH

(except BORH0) and PVD

BOR

(3)

(except BOR0) and

PVD consumption from V

DDA

peripheral voltage monitoring

PVM4

V hyst_PVM3

V hyst_PVM4

(PVM1/PVM2)

DDA

peripheral voltage monitoring

PVM3 hysteresis

PVM4 hysteresis

PVM1 and PVM2 consumption from V

Rising edge

Falling edge

Rising edge

Falling edge

2.69

2.59

2.85

2.75

2.41

2.31

2.56

2.47

2.92

2.84

1.61

1.6

1.78

1.77

100

1.1

1.65

1.64

1.82

1.81

2.74

2.64

2.91

2.81

2.46

2.36

2.61

2.52

2.98

2.90

0.2

1.69

1.68

1.86

1.85

2.79

2.69

2.96

2.86

2.51

2.41

2.66

2.57

3.04

2.96

1.6

V mV mV

µA

V mV mV

µA

(PVM3/PVM4)

Table 32 are derived from tests performed under the ambient

PVM3 and PVM4 consumption from V

2 µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables.

DS12737 Rev 6 149/340

307

Electrical characteristics STM32L552xx

The parameters given in

temperature and supply voltage conditions summarized in Table 27: General operating conditions

Symbol

Table 32. Embedded internal voltage reference

Parameter Conditions Min Typ Max Unit t t

REFINT

S_vrefint

(1) start_vrefint

Internal reference voltage

ADC sampling time when reading the internal reference voltage

Start time of reference voltage buffer when

ADC is enable

–40 °C < T

< +130 °C 1.182 1.212

1.232

(2)

8 12

∆

REFINTBUF

REFINT

Coeff

)

REFINT

buffer consumption from V

DD when converted by

ADC

Internal reference voltage spread over the temperature range

Average temperature coefficient

= 3 V

–40°C < T

< +130°C

12.5

7.5

Coeff

DDCoeff

Long term stability

Average voltage coefficient

1000 hours, T = 25°C

3.0 V < V

< 3.6 V -

300

250

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1000

1200

Section 5.1.7: Current consumption measurement .

µs

µA mV ppm/°C ppm ppm/V

REFINT

150/340 DS12737 Rev 6

STM32L552xx

1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20

Electrical characteristics

Figure 32. V

REFINT

versus temperature

0 20

Mean

Min

Max

80 100 120 °C

MSv40169V2

DS12737 Rev 6 151/340

307

Electrical characteristics

5.3.6 Supply current characteristics

STM32L552xx

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code

The current consumption is measured as described in

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0438 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

• The voltage scaling range is adjusted to f

HCLK

frequency as follows:

– Voltage Range 0 for 80 MHz < f

HCLK

<= 110 MHz

– Voltage Range 1 for 26 MHz < f

HCLK

<= 80 MHz

– Voltage Range 2 for f

HCLK

<= 26 MHz

The parameters given in

Table 33 to

Table 81 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 27: General operating conditions

152/340 DS12737 Rev 6

Symbol

I DD

(Run)

I DD

(LPRun)

Table 33. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ICACHE ON in 2-way

Conditions TYP MAX

Parameter

Voltage scaling f

HCLK 25°C 55°C 85°C

105°

125°C 25°C 55°C 85°C 105°C 125°C

Unit

Supply current in

Run mode

Supply current in

Low-power run mode f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled f HCLK = f

Range 2

26 MHz 3.20

16 MHz 2.05

3.54

4.47

5.80

8.10

4.38

6.84

12.12

18.82

29.63

2.38

3.31

4.62

6.92

3.24

5.69

10.95

17.63

28.39

8 MHz 1.14

1.45

2.38

3.68

5.97

2.33

4.77

10.02

16.68

27.42

4 MHz 0.675

0.99

1.91

3.22

5.50

1.87

4.30

9.55

16.20

26.92

2 MHz 0.441

0.758

1.67

2.97

5.25

1.64

4.07

9.31

15.96

26.68

1 MHz 0.326

0.639

1.54

2.86

5.14

1.59

4.01

9.26

15.90

26.62

100 KHz 0.223

0.533

1.45

2.74

5.03

1.43

3.85

9.09

15.73

26.56

Range 0 110 MHz 16.7

17.3

18.7

20.5

23.7

19.07 21.53

31.38

41.23

56.59

Range 1

MSI all peripherals disabled

80 MHz 11.4

72 MHz 10.3

64 MHz 9.20

48 MHz 6.97

32 MHz 4.73

24 MHz 3.62

16 MHz 2.51

2 MHz 424

1 MHz 296

400 KHz 192

100 KHz 163

11.9

10.8

9.68

7.44

5.18

4.06

2.93

779

648

561

528

13.2

12.0

10.9

8.64

6.36

5.22

4.08

14.8

13.7

12.6

10.3

7.97

6.82

5.67

17.7

16.6

15.4

13.1

10.8

9.6

8.4

1816 3274 5719

1686 3124 5588

1594 3047 5499

1559 3012 5469

13.33 16.89

12.22 15.76

11.10 14.64

8.85

6.61

5.49

4.37

2026

1905

1832

1799

12.38

10.12

8.99

7.85

5001

4941

4762

4573

24.17

23.03

21.89

19.62

17.32

16.17

15.02

12861

11969

11881

11877

33.07

31.92

30.78

28.48

26.15

24.99

23.83

20164

18559

18519

18469

46.91

45.75

44.60

42.29

39.93

38.82

37.64

31407

31355

31266

31247 mA

µA

Symbol

I DD

(Run)

I DD

(LPRun)

Table 34. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ICACHE ON in 1-way

Conditions TYP MAX

Parame ter

Voltag e scaling f

HCLK 25°C

Range

Supply current in Run mode f HCLK = f HSE up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disabled

Range

Supply current in Lowpower run mode

26 MHz 3.10

16 MHz 2.00

8 MHz 1.11

4 MHz

2 MHz

0.65

0.43

1 MHz 0.32

100 KHz 0.22

110 MHz 16.1

f HCLK = f

Range

MSI all peripherals disabled

80 MHz 11.0

72 MHz 10.0

64 MHz 8.90

48 MHz 6.75

32 MHz 4.59

24 MHz 3.51

16 MHz 2.43

2 MHz 416

1 MHz 291

400 KHz 194

100 KHz 147

55°C

3.44

2.32

1.42

0.98

0.74

0.62

0.52

16.7

5.03

3.94

2.85

770

11.5

10.5

9.38

7.21

633

557

519

85°C

4.37

3.23

2.33

1.87

1.65

1.53

1.43

18.2

105°C 125°C

5.69

8.01

4.55

6.86

3.64

5.93

3.19

5.48

2.97

5.24

2.85

5.10

2.75

5.01

25°C

12.8

11.7

10.6

8.41

14.5

17.3

12.97

13.4

16.2

11.89

12.3

15.1

10.81

10.0

12.8

8.63

6.22

5.10

7.82

10.6

6.72

9.5

6.46

5.38

3.99

5.59

8.4

4.3

1781 3249 5708 2014

1659 3127 5575 1899

1583 3043 5502 1827

4.28

3.18

2.30

1.86

1.64

1.58

1.43

20.0

23.2

18.54

1542 3020 5462 1795

55°C

6.74

5.63

4.73

4.29

4.06

4.01

3.85

22.63

4584

16.53

15.44

14.35

12.16

9.97

8.88

7.8

4968

4930

4765

85°C

12.02

10.89

9.99

9.53

9.31

9.25

9.09

30.86

23.82

22.72

21.62

19.41

17.18

16.07

15.0

12892

11960

11905

11898

105°C 125°C

18.70

17.55

16.64

16.18

15.95

15.89

15.73

40.70

32.71

31.60

30.48

28.26

46.57

45.46

44.30

42.09

26.00

24.88

39.87

38.73

23.7

37.6

19856 31311

18568 31264

18328 31256

29.46

28.30

27.37

26.89

26.66

26.61

26.44

56.07

18312 31238

Unit mA

µA

Symbol

I DD

(Run)

I DD

(LPRun)

Parame ter

Table 35. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ICACHE disabled

Conditions TYP MAX

Voltage scaling f

HCLK 25°C 55°C 85°C 105°C 125°C

Supply current in Lowpower run mode f HCLK = f MSI all peripherals disabled

26 MHz 4.08

4.43

Supply current in Run mode

16 MHz 2.65

2.98

3.91

5.22

8 MHz 1.43

1.76

2.67

3.99

f HCLK = f HSE up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripher als disabled

Range 2 4 MHz

2 MHz

1 MHz

0.82

0.51

0.36

100 KHz 0.22

Range 0 110 MHz 18.8

Range 1

80 MHz 14.1

72 MHz 12.8

48 MHz 8.87

1.14

0.82

0.68

0.53

19.4

14.6

13.3

2.05

1.75

1.59

1.45

20.9

15.9

14.5

64 MHz 11.79

12.30

13.5

3.36

3.05

2.89

2.76

22.8

17.6

16.2

15.2

9.37

10.63

12.3

32 MHz 6.12

6.58

7.80

9.44

24 MHz 4.66

16 MHz 3.26

2 MHz

1 MHz

511

344

400 KHz 203

100 KHz 159

5.11

3.70

866

692

591

531

5.36

6.72

9.02

7.55

6.26

25.9

20.5

19.1

18.1

5.65

5.31

5.16

5.00

6.29

4.86

7.92

6.47

15.1

12.2

10.7

9.2

1890 3353 5834

1715 3168 5642

1603 3062 5505

1553 3018 5468

25°C

19.97

16.16

14.80

13.90

10.97

8.22

6.70

5.28

5.38

3.93

2.67

2.04

1.73

1.65

1.43

2122

1949

1852

1802

55°C 85°C

32.25

27.01

25.64

24.74

21.78

18.98

17.42

15.97

13.14

11.67

10.38

9.73

9.41

9.33

9.11

12721

12001

11924

11905

24.02

19.71

18.34

17.45

14.51

11.74

10.20

8.77

7.84

6.38

5.11

4.48

4.16

4.08

3.86

5256

5022

4828

4590

105°C

42.05

35.88

34.50

33.60

30.62

27.78

26.20

24.74

19.81

18.32

17.02

16.36

16.04

15.96

15.73

20681

18581

18580

18301

125°C

Unit

57.42

49.75

48.37

47.45

44.47

41.68

40.09

38.61

30.60

29.09

27.77

27.11

26.78

26.70

26.47

31502

31161

31131

30947 mA

µA

I DD

(Run)

I DD

(Run)

Symbol Parameter

Supply current in

Run mode

Supply current in

Run mode

Table 36. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 2-way and power supplied by internal SMPS step down converter

Conditions TYP

Voltage scaling

MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit f HCLK = f HSE up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disabled

Range 2

SMPS

LP mode

Range 0

SMPS

HP mode

26 MHz 1.87

16 MHz 1.23

8 MHz

4 MHz

2 MHz

1 MHz

0.72

0.46

0.33

0.27

100 KHz 0.21

1.95

1.33

0.83

0.58

0.46

0.39

0.34

2.41

1.78

1.28

1.03

0.91

0.84

0.78

3.09

2.45

1.95

1.69

1.55

1.49

1.44

5.03

4.33

3.79

3.52

3.38

3.311

3.25

1.92

1.31

0.81

0.56

0.44

0.41

0.32

2.72

2.09

1.59

1.33

1.21

1.17

1.08

110 MHz 11.21

11.76

12.72

13.98

17.58

11.49

13.03

80 MHz 7.00

7.28

8.37

9.41

11.92

7.52

8.94

f HCLK = f HSE up to

48MHz included, bypass mode PLL

ON above

48 MHz all peripherals disabled

Range 1

SMPS

HP mode

72 MHz 6.34

64 MHz 5.68

48 MHz 4.36

32 MHz 3.03

24 MHz 2.36

16 MHz 1.69

6.61

5.94

4.61

3.25

2.57

1.90

7.57

6.73

5.28

3.91

3.21

2.53

8.67

7.96

6.49

4.86

4.13

3.43

11.20

10.44

8.97

7.48

6.73

5.97

6.87

6.19

4.82

3.43

2.73

2.03

8.25

7.55

6.15

4.73

4.01

3.3

4.63

3.99

3.47

3.22

3.09

3.05

2.96

16.3

7.11

6.46

5.93

5.67

5.54

5.51

5.42

11.84

15.22

20.62

11.19

14.55

19.93

10.53

13.92

19.26

9.18

7.7

6.98

6.24

12.6

11.29

10.63

9.95

17.89

16.52

15.82

15.14

11.08

10.42

9.88

9.62

9.48

9.45

9.35

20.32

26.73

Symbol

I DD

(Run)

I DD

(Run)

Parameter

Table 37. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 1-way and power supplied by internal SMPS step down converter

Conditions

Voltage scaling

TYP MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Supply current in

Run mode

Supply current in

Run mode

26 MHz 1.82

1.90

2.36

3.03

4.96

1.88

2.67

4.58

7.06

11.03

f HCLK = f HSE up to 48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 2

SMPS

LP mode

Range 0

SMPS

HP mode

110 MHz 10.80

11.38

12.35 13.61 17.20

11.18

12.71 15.98 19.99 26.39

80 MHz 6.79

7.06

8.152

9.17

11.65

7.32

8.74

11.64

15.01

20.4

f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 1

SMPS

HP mode

16 MHz 1.20

1.30

1.75

2.41

4.31

1.28

2.06

3.96

6.43

10.39

8 MHz 0.70

0.82

1.27

1.93

3.75

0.8

1.57

3.46

5.92

9.87

4 MHz 0.45

0.58

1.02

1.68

3.51

0.56

1.32

3.21

5.67

9.61

2 MHz 0.33

0.45

0.90

1.55

3.37

0.44

1.2

3.08

5.54

9.48

1 MHz 0.26

0.39

0.84

1.49

3.30

0.4

1.17

3.05

5.51

9.45

100 KHz 0.21

0.33

0.78

1.43

3.24

0.32

1.08

2.96

5.42

9.35

72 MHz 6.15

6.42

7.38

8.46

10.92

6.68

8.06

11.01

14.37 19.73

64 MHz 5.51

5.77

6.62

7.77

10.22

6.02

7.38

10.36 13.75 19.09

48 MHz 4.23

4.48

5.15

6.34

8.814

4.69

6.02

9.05

12.48 17.76

32 MHz 2.94

3.17

3.82

4.76

7.341

3.34

4.64

7.62

11.21

16.43

24 MHz 2.29

2.51

3.15

4.06

6.62

2.66

3.95

6.91

10.56 15.76

16 MHz 1.65

1.85

2.49

3.39

5.89

1.99

3.25

6.2

9.91

15.09

Symbol

I DD

(Run)

Parameter

Supply current in

Run mode

Table 38. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE disabled and power supplied by internal SMPS step down converter

Conditions

Voltage scaling

TYP MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Range 2

SMPS

LP mode

Range 1

SMPS

HP mode

26 MHz 2.38

2.44

2.91

3.60

5.55

2.43

3.23

5.15

7.63

11.61

16 MHz 1.57

1.66

2.11

2.79

4.68

1.64

2.43

4.34

6.8

10.77

8 MHz 0.89

0.99

1.45

2.11

3.97

0.98

1.76

3.65

6.11

10.06

4 MHz 0.54

0.67

1.11

1.77

3.59

0.65

1.41

3.3

5.76

9.7

2 MHz 0.37

0.50

0.94

1.60

3.42

0.48

1.24

3.13

5.59

9.52

1 MHz 0.29

0.41

0.86

1.52

3.33

0.44

1.2

3.09

5.54

9.48

100 KHz 0.21

0.34

0.78

1.43

3.24

0.32

1.08

2.97

5.42

9.36

f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 0

SMPS

HP mode

110 MHz 12.87 13.29 14.25 15.62 18.91 13.02 14.59 17.89 21.92 28.32

80 MHz 8.69

9.01

10.21 11.24 13.82

9.35

10.76

13.6

17.02 22.47

72 MHz 7.88

8.23

9.30

10.34 12.83

8.53

9.98

12.77 16.15 21.57

64 MHz 7.28

7.56

8.67

9.70

12.17

7.86

9.27

12.16 15.54 20.94

48 MHz 5.56

5.81

6.66

7.79

10.30

6.1

7.44

10.46 13.82 19.16

32 MHz 3.87

4.11

4.79

5.87

8.40

4.33

5.65

8.63

12.16 17.41

24 MHz 2.99

3.21

3.87

4.84

7.41

3.41

4.7

7.67

11.28

16.5

16 MHz 2.15

2.36

3.00

3.92

6.45

2.52

3.79

6.73

10.42 15.62

Symbol Parameter

Table 39. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ICACHE ON in 2-way

Conditions TYP MAX

Voltage scaling f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

I DD

(Run)

I DD

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run mode

26 MHz 3.19

16 MHz 2.05

8 MHz 1.13

3.53

2.38

1.45

4.57

3.41

2.47

6.08

4.90

3.95

8.87

7.67

6.71

4.38

3.24

2.33

6.84

5.69

4.77

12.13

10.96

10.03

Range 2 4 MHz 0.67

0.99

1.98

3.48

6.22

1.87

4.30

9.56

f HCLK = f HSE up to

48MHz included, bypass mode PLL

ON above

48 MHz all peripherals disabled

2 MHz

1 MHz

0.43

0.32

100 KHz 0.22

Range 0 110 MHz 16.66

17.28

18.84

20.97

24.75

19.07

23.15

31.38

80 MHz 11.39

11.91

13.30

15.22

18.68

13.33

16.88

24.17

72 MHz 10.28

10.79

12.16

14.08

17.52

12.22

15.76

23.03

64 MHz 9.18

0.75

0.63

0.53

1.76

1.63

1.53

3.24

3.13

3.00

5.97

5.85

5.75

1.64

1.59

1.43

4.07

4.02

3.85

9.32

9.26

9.10

9.68

11.02

12.93

16.35

11.10

14.64

21.89

Range 1 48 MHz 6.95

32 MHz 4.72

24 MHz 3.61

16 MHz 2.50

7.43

5.17

4.05

2.92

8.76

10.63

14.02

8.85

12.38

19.62

6.48

8.33

11.68

6.61

10.12

17.32

5.35

4.20

7.20

6.04

10.50

9.33

5.49

4.37

8.98

7.85

16.17

15.02

56.65

46.97

45.80

44.63

42.33

39.96

38.85

37.67

29.69

28.45

27.47

26.97

26.73

26.66

26.48

41.18

33.02

31.87

30.72

28.43

26.10

24.94

23.77

18.79

17.60

16.64

16.16

15.92

15.86

15.70

f HCLK = f MSI all peripherals disabled

2 MHz 402.64 785.95

1919 3558 6501 2025 4984 12805 20319 31556

1 MHz 274.43 651.32

1775 3435 6367 1907 4958 11887 18764 31438

400 KHz 184.36 568.08

1697 3359 6278 1835 4759 11810 18426 31274

100 KHz 164.07 526.82

1660 3306 6238 1797 4578 11807 18139 30765

Unit mA

µA

Table 40. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ICACHE ON in 1-way

Conditions TYP MAX

Symbol Parameter

Voltage scaling f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C

I DD

(Run)

I DD

(LPRun)

Supply current in

Run mode

Range 2 4 MHz 0.65

0.97

1.96

3.47

6.19

1.86

4.29

9.52

f HCLK = f HSE up to

48MHz included, bypass mode PLL

ON above

48 MHz all peripherals disabled

2 MHz 0.43

0.76

1 MHz 0.31

0.63

100 KHz 0.21

0.53

1.75

1.63

1.52

3.24

3.14

3.01

5.97

5.84

5.75

1.64

1.58

1.43

4.06

4.01

3.85

9.29

9.24

9.08

Range 0 110 MHz 16.14 16.75

18.31

20.43

24.12

18.54

22.62

30.83

80 MHz 11.03 11.54

12.91

14.83

18.22

12.97

16.52

23.79

72 MHz 9.96

10.46

11.81

13.73

17.10

11.89

15.44

22.69

64 MHz 8.89

9.39

10.72

12.62

16.00

10.81

14.35

21.59

Range 1

Supply current in

Low-power run mode f HCLK = f MSI all peripherals disabled

26 MHz 3.10

3.44

16 MHz 1.99

2.32

8 MHz 1.10

1.42

48 MHz 6.74

7.21

32 MHz 4.58

5.04

24 MHz 3.50

3.94

16 MHz 2.42

2.85

2 MHz

1 MHz

400 KHz

100 KHz

395.2

289.9

186.6

165.5

772.8

641.7

557.5

523.3

4.45

3.33

2.43

8.52

6.31

5.22

4.10

1907

1775

1698

1666

5.99

4.84

3.93

8.76

7.60

6.67

10.41

13.77

8.19

11.47

7.07

5.93

10.36

9.21

3571 6492

3418 6339

3343 6271

3299 6245

4.28

3.18

2.30

8.63

6.46

5.38

4.30

2013

1907

1823

1799

6.74

5.63

4.73

12.01

10.88

9.97

12.16

19.38

9.97

17.16

8.87

7.78

16.04

14.93

4976 12833 20077

4922 11903

4765 11840

4595 11826

18462

18375

18345

40.64

32.65

31.54

30.43

28.20

25.95

24.82

23.69

18.65

17.51

16.59

16.13

15.90

15.85

15.69

125°C

31507

31382

31356

30923

56.06

46.57

45.44

44.31

42.08

39.86

38.72

37.57

29.47

28.31

27.37

26.90

26.67

26.61

26.45

Unit mA mA

µA

Symbol Parameter

Table 41. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ICACHE disabled

Conditions TYP MAX

Voltage scaling f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

I DD

(Run)

I DD

(LPRun)

Supply current in

Low-power run mode

26 MHz 4.17

4.52

16 MHz 2.73

3.07

8 MHz 1.47

1.80

5.55

4.09

2.81

7.10

5.63

4.32

9.86

8.40

7.05

5.38

3.93

2.67

7.84

6.38

5.11

13.11

19.77

30.58

11.64

18.28

29.07

10.35

16.98

27.75

Supply current in Run mode

Range 2 4 MHz 0.84

1.166

2.16

3.66

6.39

2.04

4.47

9.70

16.33

27.08

f HCLK = f HSE up to

48MHz included, bypass mode PLL

ON above

48 MHz all peripherals disabled

2 MHz 0.52

0.84

1 MHz 0.36

0.68

100 KHz 0.22

0.53

1.84

1.68

1.53

3.33

3.18

3.03

6.05

5.89

5.74

1.73

1.65

1.43

4.16

4.08

3.86

9.38

9.30

9.08

16.00

26.76

15.92

26.67

15.70

26.44

Range 0 110 MHz 17.20

17.81

19.35

21.47

25.17

19.96

24.02

32.20

42.00

57.39

80 MHz 13.93

14.47

15.86

17.80

21.23

16.17

19.70

26.96

35.83

49.73

72 MHz 12.60

13.12

14.51

16.45

19.86

14.80

18.34

25.59

34.46

48.34

64 MHz 11.82

12.34

13.73

15.65

19.05

13.90

17.45

24.69

33.55

47.42

f HCLK = f

Range 1

MSI all peripherals disabled

48 MHz 8.922

9.42

10.78

12.69

16.08

10.97

14.51

21.73

30.58

44.45

32 MHz 6.24

6.72

8.03

9.92

13.28

8.22

11.74

18.93

27.74

41.65

24 MHz 4.75

5.21

16 MHz 3.38

3.83

6.50

5.09

8.35

6.93

11.67

10.22

6.70

5.28

10.20

8.77

17.37

15.92

26.16

24.70

40.06

38.58

2 MHz

1 MHz

400 KHz

100 KHz

483.6

332.2

206.5

156.4

889.5

705.1

588.2

527.8

2022

1836

1722

1666

3671

3468

3355

3315

6622

6424

6314

6247

2109

1954

1849

1809

5283

5032

4802

4600

12566

11918

11889

11847

20777

18517

18449

18240

31527

31263

31148

30791

Unit mA

µA

Symbol

I DD

(Run)

Parameter

Table 42. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE ON in 2-way and power supplied by internal SMPS step down converter

Conditions TYP

Voltage scaling

MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Supply current in

Run mode f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 2

SMPS

LP mode

26 MHz 1.85

1.94

2.41

3.14

4.40

1.93

2.73

4.65

7.13

11.13

16 MHz 1.21

1.33

1.79

2.48

3.76

1.31

2.09

3.99

6.46

10.43

8 MHz 0.70

0.83

1.29

1.98

3.25

0.81

1.59

3.47

5.94

9.89

4 MHz 0.45

0.58

1.03

1.77

3.00

0.56

1.33

3.22

5.68

9.62

2 MHz 0.32

0.46

0.90

1.60

2.88

0.44

1.21

3.09

5.54

9.49

1 MHz 0.26

0.39

0.84

1.54

2.79

0.41

1.17

3.05

5.51

9.46

100 KHz 0.20

0.33

0.79

1.51

2.74

0.32

1.08

2.96

5.42

9.36

Range 0

SMPS

HP mode

110 MHz 11.05

11.73 12.72 14.01 16.84 11.49 13.03 16.31 20.32 26.75

Range 1

SMPS

HP mode

80 MHz 6.96

7.27

8.38

9.46

11.35

7.53

8.94

11.84

15.22 20.64

72 MHz 6.30

6.61

7.62

8.69

10.58

6.87

8.26

11.2

14.56 19.94

64 MHz 5.65

5.94

6.80

8.00

9.88

6.19

7.55

10.53 13.92 19.27

48 MHz 4.33

4.60

5.29

6.51

8.40

4.83

6.15

9.18

12.6

17.9

32 MHz 3.00

3.25

3.92

4.92

6.92

3.43

4.73

7.7

11.29 16.53

24 MHz 2.33

2.57

3.22

4.15

6.15

2.73

4.01

6.98

10.63 15.83

16 MHz 1.67

1.89

2.53

3.47

5.33

2.03

3.3

6.24

9.95

15.15

Symbol

I DD

(Run)

Parameter

Table 43. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE ON in 1-way and power supplied by internal SMPS step down converter

Conditions TYP

Voltage scaling

MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Supply current in Run mode

Range 2

SMPS

LP mode

26 MHz 1.80

1.89

2.37

3.07

4.35

1.88

2.67

4.58

7.06

11.04

16 MHz 1.18

1.30

1.76

2.46

3.72

1.28

2.06

3.96

6.43

10.39

8 MHz 0.69

0.82

1.27

1.98

3.23

0.8

1.57

3.46

5.92

9.87

4 MHz 0.44

0.58

1.02

1.72

2.98

0.56

1.32

3.21

5.67

9.61

2 MHz 0.32

0.46

0.90

1.59

2.86

0.44

1.2

3.08

5.54

9.48

f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 0

SMPS

HP mode

1 MHz 0.26

0.39

0.84

1.53

2.79

0.4

1.17

3.05

5.51

9.45

100 KHz 0.20

0.33

0.78

1.48

2.73

0.32

1.08

2.96

5.42

9.36

110 MHz 10.51

11.37

12.33 13.63

16.26

11.18

12.72

15.98

20 26.4

80 MHz 6.75

7.06

8.15

9.21

11.07

7.33

8.74

11.64

15.01

20.41

72 MHz 6.12

6.41

7.39

8.50

10.37

6.68

8.06

11.01

14.37

19.75

64 MHz 5.48

5.77

6.65

7.82

9.68

6.02

7.38

10.37 13.75

19.1

Range 1

SMPS

HP mode

48 MHz 4.20

4.48

5.15

6.38

8.25

4.69

6.02

9.06

12.48

17.77

32 MHz 2.92

3.16

3.82

4.79

6.81

3.34

4.64

7.62

11.21

16.44

24 MHz 2.27

2.51

3.15

4.12

6.06

2.66

3.95

6.91

10.56

15.76

16 MHz 1.63

1.85

2.49

3.44

5.26

1.99

3.25

6.2

9.91

15.1

Symbol

I DD

(Run)

Parameter

Table 44. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE disabled and power supplied by internal SMPS step down converter

Conditions TYP

Voltage scaling

MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Supply current in

Run mode

26 MHz 2.40

2.49

2.97

3.67

4.94

2.47

3.28

5.2

7.68

11.67

Range 2

SMPS

LP mode f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 0

SMPS

HP mode

1 MHz 0.286

0.42

0.87

1.55

2.81

0.44

1.21

3.09

5.55

9.49

100 KHz 0.20

0.34

0.79

1.48

2.74

0.32

1.08

2.97

5.42

9.36

110 MHz 11.59

12.15 13.24

14.24 16.59

11.99

13.58

16.92 20.93

27.3

80 MHz 8.53

8.95

10.06

11.12

13.07

9.31

10.7

13.49 16.89 22.35

72 MHz 7.74

8.07

9.20

10.26 12.17

8.47

9.9

12.69 16.07

21.5

Range 1

SMPS

HP mode

16 MHz 1.61

1.71

2.17

2.87

4.16

1.68

2.48

4.39

6.86

10.83

8 MHz 0.90

1.02

1.47

2.18

3.44

1 1.78

3.67

6.14

10.09

4 MHz 0.55

0.67

1.12

1.82

3.07

0.66

1.43

3.31

5.77

9.72

2 MHz 0.37

0.51

0.95

1.64

2.89

0.49

1.25

3.14

5.59

9.54

64 MHz 7.26

7.57

8.71

9.75

11.64

7.95

9.38

12.21 15.58

48 MHz 5.54

5.82

6.66

7.87

9.74

6.15

7.51

10.51 13.86

19.2

32 MHz 3.92

4.18

4.85

5.98

7.91

4.42

5.74

8.74

12.24

17.5

24 MHz 3.03

3.27

3.92

4.91

6.93

3.48

4.78

7.75

11.33

16.55

16 MHz 2.20

2.43

3.07

4.03

5.95

2.59

3.87

6.81

10.49 15.69

Table 45. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1

Conditions TYP MAX

Symbol Parameter

I DD

(Run)

I DD

(LPRun)

Voltage scaling f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Supply current in

Run mode

Supply current in

Low-power run mode

26 MHz 3.25

16 MHz 2.08

8 MHz 1.15

3.59

2.41

1.47

4.62

3.43

2.47

6.12

4.93

3.97

8.92

7.69

6.73

4.44

6.89

12.15

18.80

29.60

3.27

5.72

10.96

17.61

28.38

2.35

4.78

10.01

16.64

27.40

f HCLK = f HSE up to 48MHz included, bypass mode PLL

ON above 48

MHz all peripherals disabled

Range 2 4 MHz

2 MHz

0.68

0.44

1 MHz 0.32

100 KHz 0.22

1.00

0.76

0.64

0.53

1.99

1.75

1.64

1.52

3.51

3.25

3.14

3.03

6.23

5.97

5.86

5.76

1.88

4.31

1.65

4.07

1.59

4.01

1.42

3.84

9.53

16.16

26.91

9.30

15.92

26.67

9.24

15.86

26.61

9.06

15.68

26.43

Range 0 110 MHz 16.99

17.57

19.10

21.22

24.94

19.40

23.45

31.63

41.44

56.82

80 MHz 11.63

12.13

13.48

15.38

18.76

13.57

17.11

24.35

33.21

47.09

72 MHz 10.50

10.99

12.33

14.22

17.62

12.42

15.96

23.19

32.04

45.92

64 MHz 9.37

9.85

11.18

13.07

16.43

11.28

14.81

22.04

30.87

44.74

f HCLK = f

Range 1

MSI all peripherals disabled

FLASH in power-down

48 MHz 7.10

32 MHz 4.826

24 MHz 3.68

16 MHz 2.54

7.56

5.27

4.11

2.97

8.87

6.55

5.37

4.22

10.74

14.10

8.99

12.51

19.71

28.54

42.40

8.40

11.70

6.70

10.20

17.38

26.18

40.08

7.23

6.05

10.54

9.34

5.55

4.41

9.05

7.89

16.21

15.04

24.99

23.81

38.88

37.68

2 MHz 385.23

772.80

1911 3545

1 MHz 271.61

633.31

1776 3405

400 KHz 198.95

554.43

1694 3337

100 KHz 142.82

517.78

1638 3286

6506

6382

6298

6267

2010

1896

1818

1423

4724

4686

4633

3848

12895

12648

10788

9073

21185

20905

18052

15687

30901

30715

30448

26433

Unit mA

µA

Symbol

I DD

(Run)

Parameter

Table 46. Current consumption in Run mode, code with data processing running from SRAM1 and power supplied by internal SMPS step down converter

Conditions TYP

Voltage scaling

MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Supply current in Run mode

Range 2

SMPS

LP mode

26 MHz 1.88

1.99

2.46

3.15

4.42

1.96

2.76

4.67

7.14

11.12

16 MHz 1.24

1.35

1.81

2.51

3.76

1.33

2.11

4.01

6.48

10.44

8 MHz 0.72

0.85

1.29

1.99

3.24

0.82

1.6

3.48

5.94

9.89

4 MHz 0.46

0.59

1.04

1.73

2.97

0.57

1.34

3.22

5.68

9.62

2 MHz 0.32

0.46

0.91

1.60

2.85

0.44

1.21

3.09

5.54

9.48

f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 0

SMPS

HP mode

1 MHz 0.26

0.40

0.84

1.53

2.77

0.41

1.18

3.06

5.51

9.45

100 KHz 0.20

0.34

0.78

1.48

2.71

0.32

1.08

2.96

5.41

9.34

110 MHz 11.28

12.01 12.99 14.29 17.00 12.06 14.37 19.01 24.79

33.4

80 MHz 7.10

7.42

8.55

9.55

11.47

8.33

10.16 13.97 18.72 26.04

72 MHz 6.44

6.74

7.80

8.84

10.70

7.52

9.42

13.31 18.02

25.3

64 MHz 5.76

6.05

6.89

8.10

9.95

6.8

8.74

12.64 17.33 24.58

Range 1

SMPS

HP mode

48 MHz 4.42

4.69

5.37

6.60

8.46

5.34

7.29

11.35

15.96 23.16

32 MHz 3.06

3.31

3.96

4.93

6.93

3.86

5.79

9.98

14.58

21.7

24 MHz 2.38

2.61

3.26

4.20

6.16

3.15

5.05

9.26

13.88 20.98

16 MHz 1.70

1.92

2.55

3.51

5.32

2.45

4.31

8.52

13.19 20.25

Symbol

Table 47. Current consumption in Run and Low-power run modes, code with data processing running from SRAM2

Conditions TYP MAX

Parameter

Voltage scaling f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

I DD

(Run)

I DD (LPRu n)

26 MHz 3.20

16 MHz 2.05

8 MHz 1.13

3.53

2.38

1.45

4.55

3.40

2.46

6.08

4.90

3.97

8.86

7.67

6.71

4.33

3.19

2.28

6.79

12.05

18.6

29.56

5.63

10.88

17.41

28.32

4.71

9.94

16.46

27.34

Range 2 4 MHz 0.67

0.99

1.99

3.47

6.21

1.82

4.25

9.47

15.98

26.84

Supply current in Run mode f HCLK = f HSE up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disabled

2 MHz

1 MHz

0.43

0.32

100 KHz 0.22

0.76

0.63

0.53

1.75

1.63

1.53

3.24

3.13

3.01

5.97

5.86

5.74

1.59

1.53

1.37

4.01

3.96

3.79

9.24

15.74

26.59

9.18

15.68

26.52

9 15.5

26.33

Range 0 110 MHz 16.71

17.32

18.86

20.97

24.66

19.04

23.09

31.27

40.87

56.41

80 MHz 11.43

11.94

13.30

15.21

18.64

13.29

16.83

24.07

32.71

46.77

72 MHz 10.32

10.82

12.16

14.07

17.48

12.17

15.71

22.94

31.55

45.6

64 MHz 9.219

9.70

11.03

12.94

16.31

11.05

14.58

21.79

30.39

44.44

Range 1 48 MHz 6.98

7.44

32 MHz 4.746

5.19

24 MHz 3.62

16 MHz 2.50

4.06

2.93

8.77

10.63

13.98

8.79

12.31

19.5

28.16

42.12

6.48

8.33

11.65

6.54

10.04

17.2

25.84

39.83

5.33

4.19

7.17

6.02

10.49

9.29

5.42

4.29

8.9

7.76

16.05

14.9

24.67

23.51

38.64

37.45

Supply current in Low-power run mode f HCLK = f MSI all peripherals disabled

FLASH in power-down

2 MHz 386.41 774.71

1901 3546 6475 1946 2886 7270 11761 20360

1 MHz 276.23 635.13

1767 3445 6360 1829 2796 6688 12192 20188

400 KHz 196.75 552.97

1679 3339 6278 1757 2749 6961 11520 19976

100 KHz 146.57 513.87

1644 3299 6249 1373 2313 5697 10033 17534 mA

µA

Symbol

I DD

(Run)

Parameter

Table 48. Current consumption in Run mode, code with data processing running from SRAM2 and power supplied by internal SMPS step down converter

Conditions

Voltage scaling

TYP MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

Range 2

SMPS LP mode

26 MHz 1.86

1.96

2.43

3.12

4.43

2.22

3.49

6.48

10.14 15.89

16 MHz 1.22

1.33

1.79

2.50

3.75

1.61

2.87

5.83

9.48

15.21

8 MHz 0.71

0.83

1.28

1.99

3.24

1.11

2.37

5.32

8.95

14.64

4 MHz 0.456

0.58

1.03

1.74

2.99

0.86

2.12

5.07

8.69

14.36

2 MHz 0.32

0.46

0.90

1.60

2.86

0.74

1.99

4.94

8.56

14.22

1 MHz 0.26

0.40

0.84

1.54

2.79

0.71

1.96

4.9

8.52

14.18

100 KHz 0.20

0.34

0.78

1.49

2.73

0.62

1.87

4.81

8.43

14.07

Range 0

SMPS HP mode

110 MHz 11.04

11.78

12.75 14.05 16.87 12.16 14.52 19.77 25.94 35.47

80 MHz 7.00

7.29

8.40

9.44

11.33

8.23

10.44 14.63 19.73

27.8

Range 1

SMPS HP mode

72 MHz 6.34

6.62

7.64

8.72

10.59

7.49

9.79

13.98 19.05 27.08

64 MHz 5.68

5.95

6.82

8.00

9.86

6.8

8.97

13.41 18.39 26.39

48 MHz 4.35

4.61

5.30

6.51

8.38

5.39

7.53

12.27 17.03 24.99

32 MHz 3.02

3.26

3.91

4.89

6.89

3.98

6.11

10.94 15.72 23.52

24 MHz 2.35

2.58

3.22

4.18

6.11

3.28

5.4

10.17

15.11

22.8

16 MHz 1.68

1.90

2.53

3.49

5.31

2.58

4.68

9.42

14.54 22.09

Symbol

I DD (Run)

I DD

(LPRun)

Parameter

Supply current in

Run mode

Supply current in

Low-power run f

Table 49. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ICACHE ON (2-way)

Conditions

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

Unit

Voltage scaling

HCLK =f HSE up to

48 MHZ included, bypass mode

PLL ON above

48 MHz all peripherals disabled f

Range2

HCLK =26MHz

Range 1 fHCLK=80 MHz

Range 0 f HCLK = 110 MHz f HCLK = f MSI = 2 MHz all peripherals disabled

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

19.1

15.8

14.5

424

10.8

9.9

16.7

18.0

447

477

427

350

2.77

11.4

12.2

13.1

3.20

3.43

3.66

3.06

25°C

19.0

15.8

14.5

403

10.8

9.9

16.7

18.0

415

432

383

369

2.77

11.4

12.2

13.0

3.19

3.43

3.64

3.05

mA mA mA

µA

TYP

Dual

Bank

Mode

25°C

173

143

131

201

135

123

152

163

207

216

192

185

106

142

153

163

123

132

140

117

Unit

µA/MHz

TYP

Single

Bank

Mode

25°C

174

143

131

212

135

123

152

163

224

239

214

175

106

143

153

163

123

132

141

118

Symbol

I DD

(Run)

Parameter

Supply current in

Run mode f

Table 50. Typical current consumption in Run mode with SMPS, with different codes running from Flash, ICACHE ON (2-way)

Conditions

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

25°C

HCLK =f HSE up to

48 MHZ included, bypass mode PLL ON above 48 MHz all peripherals disabled

Voltage scaling

Range2, SMPS

LP f HCLK =26 MHz

Range 1, SMPS

HP fHCLK=80 MHz

Range 0, SMPS

HP f HCLK = 110 MHz

Code 25°C

Reduced code

1.88

Coremark 2.00

Dhrystone2.1

2.13

Fibonacci

While

Reduced code

1.79

1.65

7.0

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

11.2

Coremark 12.2

Dhrystone2.1

13.0

Fibonacci

While

10.6

9.3

7.5

8.0

6.7

6.1

1.85

12.1

12.9

10.6

9.3

7.5

7.9

6.6

6.1

1.98

2.09

1.77

1.64

7.0

11.1

Unit

mA mA mA

TYP

Single

Bank

Mode

25°C

TYP

Dual

Bank

Mode

25°C

100

102

111

118

101

110

117

Unit

µA/MHz

Symbol

I DD

(LPRu n)

(Run)

Parameter

Supply current in

Run mode

Supply current in

Low-power run f f

Table 51. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ICACHE ON (1-way)

Conditions

TYP

Single Bank

Mode

TYP

Dual

Bank

Mode

Unit

HCLK

=f disabled

= f

HSE up to

48 MHZ included, bypass mode PLL

ON above 48 MHz all peripherals

MSI disabled

Voltage scaling f

Range2

HCLK =26 MHz

Range 1 fHCLK=80 MHz

Range 0 f HCLK = 110

MHz

= 2 MHz all peripherals

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

18.1

15.2

14.2

395

10.4

9.7

16.1

17.0

389

405

375

372

2.72

11.0

11.6

12.4

3.10

3.26

3.47

2.95

25°C

18.2

15.2

14.2

416

10.4

9.7

16.1

17.0

425

451

392

355

2.73

11.0

11.6

12.4

3.10

3.26

3.48

2.95

mA mA mA

µA

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

25°C

165

138

129

208

130

121

147

154

213

226

196

178

105

138

145

155

119

125

134

114

25°C

164

138

129

198

130

121

147

154

194

203

188

186

105

138

145

155

119

125

133

113

Unit

µA/MHz

Symbol

I DD

(Run)

Parameter

Supply current in Run mode

Table 52. Typical current consumption in Run mode with SMPS, with different codes running from Flash, ICACHE ON (1-way)

Conditions

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

Voltage scaling

Code 25°C 25°C f HCLK =f HSE up to

48 MHZ included, bypass mode PLL ON above 48 MHz all peripherals disabled f

Range2,

SMPS LP

HCLK =26

MHz

Range 1,

SMPS HP fHCLK=80

MHz

Range 0,

SMPS HP f HCLK =

110 MHz

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

11.5

12.4

10.0

9.2

7.6

6.4

6.0

10.8

1.82

1.91

2.03

1.74

1.63

6.8

7.1

11.4

12.2

10.0

9.1

7.6

6.4

6.0

10.5

1.80

1.89

2.00

1.72

1.61

6.8

7.1

Unit mA mA mA

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

25°C

105

112

25°C

104

111

Unit

µA/MHz

Symbol

I DD

(Run)

I DD (LPR un)

Parameter

Supply current in

Run mode

Supply current in

Low-power run

Table 53. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ICACHE disabled

Conditions

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

Unit

Voltage scaling f HCLK =f HSE up to

48 MHZ included, bypass mode PLL ON above 48 MHz all peripherals disabled f HCLK = f MSI

Range 1 fHCLK=80

MHz

Range 0 f HCLK = 110 MHz

= 2MHz all peripherals disabled f

Range2

HCLK =26 MHz

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

17.7

16.6

15.9

511

12.1

10.9

18.8

17.5

577

599

470

416

3.04

14.1

13.6

12.5

4.08

4.42

4.56

3.62

25°C

15.5

15.1

16.5

484

11.3

17.2

15.2

550

551

462

398

3.14

13.9

12.2

12.5

4.17

4.22

4.41

3.55

mA mA mA

µA

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

25°C

161

151

145

255

151

136

171

159

289

299

235

208

117

176

171

156

157

170

175

139

25°C

141

138

150

242

142

141

156

138

275

231

199

121

174

152

156

160

162

170

137

Unit

µA/MHz

Symbol

I DD

(Run)

Parameter

Supply current in Run mode

Table 54. Typical current consumption in Run mode with internal SMPS, with different codes running from Flash, ICACHE disabled

Conditions

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

Unit

Voltage scaling f HCLK =f HSE up to 48

MHZ included, bypass mode PLL ON above

48 MHz all peripherals disabled

Range2, SMPS f HCLK

=26 MHz

Range 1, SMPS

HP fHCLK=80

MHz

Range 0, SMPS

HP f HCLK = 110 MHz

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

7.5

6.8

12.9

11.9

12.0

11.3

10.7

1.80

8.7

8.4

8.6

2.38

2.59

2.67

2.13

25°C

7.0

11.6

10.1

10.4

10.1

11.1

1.86

8.5

7.5

7.7

2.41

2.44

2.55

2.07

mA mA mA

TYP

Single

Bank

Mode

TYP

Dual

Bank

Mode

25°C

117

109

102

109

106

107

100

103

25°C

105

101

107

Unit

µA/MHz

Symbol

DD (Run)

I DD (LPRun)

Parameter

Supply current in

Run mode

Supply current in

Low-power run

Table 55. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1

Conditions TYP

Voltage scaling f HCLK =f HSE up to 48 MHZ included, bypass mode PLL f

ON above 48 MHz all peripherals disabled

HCLK = f MSI f

Range2

HCLK =26MHz

Range 1 fHCLK=80

MHz

Range 0 f HCLK = 110 MHz

= 2MHz all peripherals disabled

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

12.5

13.93

17.0

17.88

17.4

18.3

20.4

385

3.26

3.41

3.35

3.50

3.82

11.6

12.22

11.9

421

384

409

442

Unit mA mA mA

µA

TYP

25°C

159

166

186

193

157

174

154

163

211

192

204

221

147

145

153

149

125

131

129

134

Unit

µA/MHz

Symbol Parameter

I DD (Run)

Supply current in Run mode

Table 56. Typical current consumption in Run mode with internal SMPS, with different codes running from SRAM1

Conditions TYP

Voltage scaling f HCLK =f HSE up to 48 MHZ included, bypass mode PLL

ON above 48 MHz all peripherals disabled f

Range2, LP

HCLK =26MHz

Range 1, HP fHCLK=80 MHz

Range 0, HP f HCLK = 110 MHz

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

7.6

8.51

11.3

11.32

11.7

12.3

13.9

2.22

7.1

7.25

7.3

1.89

1.9

1.94

2.01

Unit mA mA mA

TYP

25°C

106

103

107

112

126

Unit

µA/MHz

Symbol

I DD (Run)

I DD

(LPRun)

Parameter

Table 57. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM2

Conditions TYP

Voltage scaling

Supply current in Run mode

Supply current in Lowpower run f HCLK =f HSE up to 48 MHZ included, bypass mode PLL

ON above 48 MHz all peripherals disabled f HCLK = f MSI f

Range2

HCLK =26MHz

Range 1 fHCLK=80 MHz

Range 0 f HCLK = 110 MHz

= 2MHz all peripherals disabled

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

414

373

393

436

12.0

13.24

16.7

17.44

16.6

17.5

19.5

386

3.20

3.33

3.20

3.34

3.66

11.4

11.92

11.4

Unit mA mA mA

µA

TYP

25°C

151

159

177

193

149

165

152

159

207

187

196

218

141

143

149

142

123

128

123

129

Unit

µA/MHz

Symbol

I DD (Run)

Parameter

Supply current in Run mode

Table 58. Typical current consumption in Run mode with internal SMPS, with different codes running from SRAM2

Conditions TYP

Voltage scaling f HCLK =f HSE up to 48 MHZ included, bypass mode

PLL ON above 48 MHz all peripherals disabled f

Range2, LP

HCLK =26MHz

Range 1,HP fHCLK=80 MHz

Range 0, HP f HCLK = 110 MHz

Code

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

25°C

7.3

8.05

11.0

11.1

11.2

11.8

13.1

2.14

7.0

1.90

2.08

1.90

1.98

Unit mA mA mA

TYP

25°C

101

100

101

102

108

119

Unit

µA/MHz

Table 59. Current consumption in Sleep and Low-power sleep mode, Flash ON

Conditions TYP MAX

Symbol Parameter

I DD

(Sleep)

(LPSl eep)

Voltage scaling f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Supply current in

Sleep mode

Supply current in

Low-power sleep mode f HCLK = f HSE up to 48MHz included, bypass mode

PLL ON above 48

MHz all peripherals disabled f HCLK = f

Range 2

26 MHz 1.04

16 MHz 0.72

8 MHz 0.46

4 MHz

2 MHz

1 MHz

0.33

0.27

0.24

100 KHz 0.211

0.52

Range 0 110 MHz 4.73

Range 1

MSI all peripherals disabled

80 MHz 3.31

72 MHz 3.01

64 MHz 2.71

48 MHz 2.10

32 MHz 1.49

24 MHz 1.18

16 MHz 0.88

1.37

1.04

0.79

0.65

0.58

0.55

5.23

3.74

3.44

3.14

2.53

1.91

1.60

1.29

2.36

2.04

1.78

1.65

1.58

1.55

1.52

6.62

5.01

4.71

4.41

3.79

3.17

2.84

2.53

3.88

3.55

3.29

3.14

3.07

3.03

3.01

6.62

6.30

6.01

5.85

5.78

5.73

5.72

2.25

4.69

1.93

4.36

1.67

4.10

1.54

3.97

1.48

3.90

1.46

3.88

1.42

3.84

9.93

9.60

9.33

9.19

9.12

9.11

9.06

16.57

27.36

16.23

27.00

15.95

26.70

15.80

26.55

15.73

26.48

15.72

26.46

15.67

26.41

8.65

12.21

7.00

11.02

19.15

28.98

44.29

6.88

10.19

5.20

8.71

15.92

24.74

38.70

6.56

6.26

5.62

4.98

4.67

4.34

9.86

9.56

8.92

8.27

7.93

7.60

4.90

4.60

3.98

3.37

3.06

2.75

8.40

8.10

7.47

6.84

6.52

6.21

15.61

15.29

14.66

14.00

13.68

13.35

24.42

24.10

23.45

22.78

22.44

22.10

38.36

38.03

37.38

36.67

36.32

35.96

2 MHz 205.22 584.41

1712 3383 6283 1843 4745 12643 19003 31504

1 MHz 192.80 547.20

1678 3343 6248 1815 4665 12037 18615 31391

400 KHz 143.73 520.85

1655 3313 6222 1793 4567 11872 18346 30902

100 KHz 137.82 519.15

1650 3308 6219 1786 4554 11814 18206 30849

Unit mA

µA

Table 60. Current consumption in Low-power sleep mode, Flash in power-down

Conditions TYP MAX

Symbol Parameter

I DD

(LPSleep)

Voltage scaling f

HCLK 25°C 55°C 85°C

Supply current in

Low-power sleep mode

2 MHz 197.64

567.40

1699 f HCLK = f MSI all peripherals disabled

1 MHz 165.99

540.66

1672

400 KHz 145.78

510.80

1640

100 KHz 143.34

506.41

1629

105°C

3374

3313

3312

3288

125°C

6136

6109

6084

6062

25°C

1839

1805

1785

1423

55°C

4641

4599

4578

3848

85°C 105°C 125°C

12810 20855 31559

12189 20334 31071

10816 17908 30945

9087 15694 26452

Unit

µA

I DD

(Sleep)

Symbol Parameter

Supply current in

Sleep mode

Table 61. Current consumption in Sleep mode,

Flash ON and power supplied by internal SMPS step down converter

Conditions TYP

Voltage scaling

MAX f

HCLK 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Range 2

SMPS LP mode

26 MHz 0.69

16 MHz 0.50

8 MHz 0.35

4 MHz 0.27

2 MHz 0.23

f HCLK = f HSE up to 48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disabled

1 MHz 0.21

100 KHz 0.20

Range 0

SMPS HP mode

110 MHz 3.22

80 MHz 2.22

72 MHz 2.04

64 MHz 1.85

Range 1

SMPS HP mode

48 MHz 1.48

32 MHz 1.10

24 MHz 0.91

16 MHz 0.72

0.82

0.64

0.48

0.40

0.37

0.35

0.33

3.49

2.44

2.26

2.07

1.70

1.32

1.12

0.93

1.27

1.09

0.93

0.85

0.82

0.79

0.78

4.24

3.09

2.90

2.71

2.34

1.94

1.74

1.55

1.99

1.80

1.65

1.55

1.52

1.50

1.48

5.40

4.06

3.89

3.70

3.31

2.91

2.71

2.52

3.22

3.05

2.88

2.81

2.77

2.73

7.70

5.98

5.78

5.53

5.11

4.62

4.40

4.18

0.8

0.62

0.47

0.39

0.35

0.34

0.32

3.81

2.6

2.41

2.22

1.83

1.44

1.24

1.04

5.39

3.9

3.7

3.51

3.1

2.69

2.48

2.28

1.57

1.39

1.23

1.16

1.12

1.11

1.08

3.47

3.27

3.11

3.03

2.99

2.98

2.95

5.93

5.73

5.57

5.48

5.44

5.43

5.4

6.89

10.56

15.77

6.68

10.37

15.58

6.48

10.19

15.38

6.07

5.64

5.42

5.2

9.81

9.39

9.18

8.97

14.58

14.38

14.17

9.88

9.67

9.5

9.42

9.37

9.36

9.33

9.01

12.92

19.03

Symbol

Table 62. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 2-way and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V

110 MHz 6.69

80 MHz 4.1

72 MHz

64 MHz

3.7

3.31

VDD12=1.1V

48 MHz

32 MHz

26 KHz

16 MHz

2.51

1.7

1.76

1.14

8 MHz

4 MHz

2 MHz

1 MHz

100 KHz

0.62

0.35

0.22

0.16

0.1

6.93

4.77

4.33

3.88

2.98

2.08

1.91

1.29

0.76

0.49

0.36

0.29

0.23

7.5

5.28

4.83

4.38

3.47

2.55

2.31

1.69

1.15

0.88

0.75

0.69

0.63

8.23

5.94

5.49

5.04

4.12

3.2

2.9

2.25

1.72

1.45

1.32

1.25

1.19

5.27

4.32

3.89

3.26

9.5

7.1

6.65

6.18

2.7

2.44

2.29

2.23

2.16

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 63. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE ON in 1-way and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V 110 MHz 6.47

80 MHz 3.97

72 MHz 3.58

64 MHz 3.2

VDD12=1.1V

6.71

4.15

3.76

3.37

7.28

4.6

4.21

3.82

8.03

5.2

4.81

4.41

9.28

6.23

5.82

5.43

48 MHz 2.43

32 MHz 1.65

2.59

1.81

3.02

2.24

3.61

2.81

4.62

3.81

26 KHz 1.337

1.484

1.885

2.455

3.455

16 MHz 0.863

1.001

1.393

1.963

2.959

8 MHz 0.479

0.613

1.005

1.57

2.558

4 MHz 0.285

0.423

0.807

1.376

2.364

2 MHz 0.185

0.324

0.712

1.281

2.26

1 MHz 0.138

0.272

0.66

1.229

2.2

100 KHz 0.095

0.229

0.617

1.186

2.161

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 64. Current consumption in Run mode, code with data processing running from Flash in single bank, ICACHE disabled and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V 110 MHz 7.55

80 MHz 5.07

72 MHz 4.58

64 MHz 4.24

VDD12=1.1V

7.8

5.26

4.77

4.42

8.37

5.72

5.22

4.87

9.13

6.34

5.83

5.48

10.39

7.36

6.87

6.5

48 MHz 3.19

32 MHz 2.2

3.37

2.37

3.82

2.8

4.42

3.39

5.43

4.4

26 KHz 1.76

1.911

2.312

2.899

3.891

16 MHz 1.143

1.285

1.687

2.252

3.257

8 MHz 0.617

0.759

1.152

1.721

2.7

4 MHz 0.354

0.492

0.884

1.449

2.437

2 MHz 0.22

0.358

0.755

1.316

2.291

1 MHz 0.155

0.293

0.686

1.247

2.226

100 KHz 0.099

0.233

0.625

1.191

2.157

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 65. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE on in 2-way and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V 110 MHz 6.69

80 MHz 4.09

72 MHz

64 MHz

3.7

3.3

VDD12=1.1V

6.93

4.28

3.88

3.48

7.56

4.78

4.37

3.97

8.41

5.47

5.06

4.65

9.93

6.72

6.3

5.88

48 MHz

32 MHz

2.5

1.7

2.67

1.86

3.15

2.33

3.82

2.99

5.04

4.2

26 KHz 1.147

1.269

1.643

2.189

3.189

16 MHz 0.737

0.856

1.226

1.765

2.761

8 MHz 0.406

0.521

0.888

1.424

2.412

4 MHz 0.241

0.356

0.715

1.255

2.24

2 MHz 0.158

0.273

0.633

1.168

2.15

1 MHz 0.115

0.23

0.586

1.129

2.103

100 KHz 0.079

0.191

0.554

1.078

2.067

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 66. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE on in 1-way and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V 110 MHz 6.47

80 MHz 3.97

72 MHz 3.58

64 MHz 3.2

VDD12=1.1V

6.72

4.15

3.76

3.38

7.34

4.64

4.25

3.86

8.02

5.33

4.94

4.54

9.68

6.55

6.15

5.75

48 MHz 2.42

32 MHz 1.65

2.59

1.81

3.06

2.27

3.74

2.95

4.95

4.13

26 KHz 1.114

1.237

1.603

2.157

3.153

16 MHz 0.719

0.834

1.201

1.74

2.732

8 MHz 0.399

0.514

0.877

1.416

2.401

4 MHz 0.237

0.352

0.708

1.251

2.229

2 MHz 0.155

0.273

0.629

1.165

2.15

1 MHz 0.115

0.23

0.586

1.129

2.103

100 KHz 0.079

0.194

0.55

1.086

2.067

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 67. Current consumption in Run mode, code with data processing running from Flash in dual bank, ICACHE disabled and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V 110 MHz 6.9

80 MHz 5.01

72 MHz 4.53

64 MHz 4.25

VDD12=1.1V

7.15

5.21

4.72

4.44

7.76

5.7

5.22

4.94

8.61

6.4

5.91

5.63

10.1

7.63

7.14

6.85

48 MHz 3.21

32 MHz 2.25

3.39

2.42

3.88

2.89

4.57

3.57

5.78

4.77

26 KHz 1.499

1.625

1.999

2.552

3.544

16 MHz 0.985

1.107

1.474

2.024

3.02

8 MHz 0.532

0.647

1.01

1.557

2.538

4 MHz 0.302

0.421

0.776

1.316

2.301

2 MHz 0.187

0.302

0.665

1.197

2.178

1 MHz 0.133

0.248

0.604

1.147

2.117

100 KHz 0.079

0.194

0.554

1.089

2.063

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 68. Current consumption in Run mode, code with data processing running from SRAM1, and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V 110 MHz 6.81

80 MHz 4.18

72 MHz 3.78

64 MHz 3.37

VDD12=1.1V

7.05

4.36

3.95

3.54

7.66

4.85

4.43

4.02

8.51

5.53

5.12

4.7

6.75

6.34

5.91

48 MHz 2.55

32 MHz 1.74

2.72

1.89

3.19

2.35

3.86

3.02

5.07

4.21

26 KHz 1.172

1.294

1.661

2.204

3.21

16 MHz 0.751

0.87

1.233

1.776

2.764

8 MHz 0.413

0.532

0.892

1.427

2.419

4 MHz 0.244

0.359

0.719

1.262

2.243

2 MHz 0.158

0.273

0.633

1.168

2.15

1 MHz 0.119

0.23

0.593

1.129

2.11

100 KHz 0.079

0.194

0.55

1.093

2.071

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 69. Current consumption in Run mode, code with data processing running from SRAM2, and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

Supply current in Run mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.2V 110 MHz 6.7

80 MHz 4.11

72 MHz 3.71

64 MHz 3.31

VDD12=1.1V

6.95

4.29

3.89

3.49

7.56

4.78

4.37

3.97

8.41

5.47

5.06

4.65

9.89

6.7

6.28

5.87

48 MHz 2.51

32 MHz 1.71

2.68

1.87

3.16

2.33

3.82

5.03

4.19

26 KHz 1.15

1.273

1.639

2.186

3.185

16 MHz 0.741

0.856

1.222

1.761

2.757

8 MHz 0.41

0.525

0.888

1.427

2.412

4 MHz 0.241

0.356

0.715

1.251

2.236

2 MHz 0.158

0.273

0.629

1.168

2.15

1 MHz 0.115

0.23

0.59

1.129

2.11

100 KHz 0.079

0.194

0.55

1.086

2.067

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol

Table 70. Current consumption in Sleep mode, Flash ON and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

VDD12 f

HCLK 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Sleep)

Supply current in

Sleep mode f HCLK = f HSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.20V 110 MHz 1.90

80 MHz 1.19

72 MHz 1.08

64 MHz 0.98

VDD12=1.10V

2.10

1.35

1.24

1.13

2.66

1.80

1.70

1.59

3.47

2.47

2.36

2.25

4.90

3.67

3.54

3.44

48 MHz 0.76

32 MHz 0.54

0.91

0.69

1.36

1.14

2.02

1.79

3.21

2.97

26 MHz 0.453

0.591

1.022

1.678

2.860

16 MHz 0.315

0.453

0.880

1.531

2.718

8 MHZ 0.203

0.341

0.768

1.424

2.593

4 MHz 0.147

0.285

0.712

1.355

2.528

2MHz 0.116

0.255

0.682

1.329

2.498

1 MHz 0.104

0.242

0.669

1.307

2.476

100 Khz 0.091

0.229

0.656

1.298

2.472

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency

= 85%.

Symbol Parameter

Table 71. Current consumption in Run mode, code with data processing running from Flash,

ICACHE on (2-way) and power supplied by external SMPS

Conditions

TYP single bank mode

Unit

TYP single bank mode

Unit

VDD12 fHCLK code 25°C 25°C 25°C 25°C

IDD(Run)

Supply current in

Run mode fHCLK = fHSE up to

48MHz included, bypass mode PLL ON above 48

MHz all peripherals disabled

VDD12=1.00V

VDD12=1.10V

fHCLK=26MHz fHCLK=26MHz fHCLK=80MHz

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

(1)

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

VDD12=1.20V fHCLK=110MHz

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

4.7

3.88

3.55

6.69

1.39

1.26

4.1

4.4

7.2

7.66

6.32

5.8

1.04

1.45

1.56

1.66

1.2

1.29

1.37

1.15

1.2

1.29

1.37

1.14

1.04

1.45

1.56

1.65

1.38

1.26

4.09

4.4

4.68

3.88

3.55

6.69

7.2

7.62

6.32

5.8

mA mA mA mA

46.15

49.62

52.69

44.23

55.77

63.85

53.46

48.46

51.25

58.75

48.5

44.38

60.82

65.45

69.64

57.45

52.73

53.08

48.46

51.13

58.5

48.5

44.38

60.82

46.15

49.62

52.69

43.85

55.77

63.46

65.45

69.27

57.45

52.73

µA/MHz

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =

85%.

Symbol Parameter

Table 72. Current consumption in Run mode, code with data processing running from Flash,

ICACHE on (1-way) and power supplied by external SMPS

Conditions

(1)

TYP

Single

Bank mode

TYP

Single

Bank mode

Unit

TYP

Single

Bank mode

TYP

Single

Bank mode

Unit

VDD12 fHCLK code 25°C 25°C 25°C 25°C

IDD(Run)

Supply current in

Run mode fHCLK = fHSE up to

48MHz included, bypass mode PLL ON above 48

MHz all peripherals disabled

VDD12=1.00V

VDD12=1.10V

fHCLK=26MHz fHCLK=26MHz fHCLK=80MHz

VDD12=1.20V fHCLK=110MHz

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

4.47

3.73

3.49

6.47

1.34

1.24

3.97

4.16

6.81

7.28

6.09

5.71

1.02

1.41

1.48

1.58

1.16

1.22

1.31

1.11

1.16

1.22

1.3

1.11

1.02

1.41

1.48

1.58

1.34

1.24

3.97

4.16

4.45

3.73

3.49

6.47

6.81

7.25

6.09

5.7

mA mA mA mA

44.62

46.92

50.38

42.69

39.23

54.23

56.92

60.77

51.54

47.69

49.63

55.88

46.63

43.63

58.82

61.91

66.18

55.36

51.91

51.54

47.69

49.63

55.63

46.63

43.63

58.82

44.62

46.92

42.69

39.23

54.23

56.92

60.77

61.91

65.91

55.36

51.82

µA/MHz

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =

85%.

Symbol Parameter

Table 73. Current consumption in Run mode, code with data processing running from Flash,

ICACHE disabled and power supplied by external SMPS

Conditions

(1)

TYP

Single

Bank mode

TYP

Single

Bank mode

Unit

TYP

Single

Bank mode

TYP

Single

Bank mode

Unit

VDD12 fHCLK code 25°C 25°C 25°C 25°C

IDD(Run)

Supply current in

Run mode fHCLK = fHSE up to

48MHz included, bypass mode PLL ON above 48

MHz all peripherals disabled

VDD12=1.00V

VDD12=1.10V

fHCLK=26MHz fHCLK=26MHz fHCLK=80MHz

VDD12=1.20V fHCLK=110MHz

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

4.49

4.34

3.9

7.55

1.64

1.38

5.07

4.91

7.03

7.08

6.64

6.39

1.14

1.85

2.01

2.07

1.53

1.66

1.71

1.36

1.56

1.58

1.65

1.33

1.18

1.89

1.92

1.61

1.43

5.01

4.37

4.49

4.07

4.04

6.9

6.09

6.2

6.07

6.63

mA mA mA mA

58.85

63.85

65.77

52.31

43.85

71.15

77.31

79.62

63.08

53.08

63.38

61.38

56.13

54.25

48.75

68.64

63.91

64.36

60.36

58.09

61.92

62.63

54.63

56.13

50.88

50.5

62.73

60.77

63.46

51.15

45.38

72.69

73.85

76.92

55.36

56.36

55.18

60.27

µA/MHz

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =

85%.

Symbol

Table 74. Current consumption in Run mode, code with data processing running from SRAM1, and power supplied by external SMPS

Conditions

(1)

TYP

Parameter Unit

VDD12 fHCLK code 25°C

TYP

Unit

25°C

IDD(Run) Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.00V

VDD12=1.10V

fHCLK=26MHz fHCLK=26MHz fHCLK=80MHz

VDD12=1.20V fHCLK=110MHz

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

4.29

4.5

5.01

6.81

1.59

1.73

4.18

1.84

2.97

7.34

8.19

1.43

1.48

0.69

1.52

1.22

0.57

1.26

1.31

mA mA mA mA

61.15

66.54

52.25

53.63

56.25

62.63

61.91

46.92

21.92

48.46

50.38

56.92

26.54

58.46

63.64

66.73

74.45

µA/MHz

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =

85%.

Symbol

Table 75. Current consumption in Run mode, code with data processing running from SRAM2, and power supplied by external SMPS

Conditions

(1)

Parameter

TYP

Unit

VDD12 f

HCLK code 25°C

TYP

25°C

Unit

IDD(Run) Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disabled

VDD12=1.00V fHCLK=26MHz

VDD12=1.10V

fHCLK=26MHz fHCLK=80MHz

VDD12=1.20V fHCLK=110MHz

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Reduced code

Coremark

Dhrystone2.1

Fibonacci

While

Table 102: I/O static characteristics

1.20

0.57

1.20

1.25

1.37

1.45

0.69

1.45

1.52

1.66

4.11

1.84

4.09

4.30

4.76

6.70

2.97

6.67

7.01

7.80

mA mA mA mA

46.15

21.92

46.15

48.08

52.69

55.77

26.54

55.77

58.46

63.85

51.38

23.00

51.13

53.75

59.50

60.91

27.00

60.64

63.73

70.91

µA/MHz

1. All values are obtained by calculation based on measurements done with internal voltage regulator and using following parameters: SMPS input = 3.3 V, SMPS efficiency =

85%.

Symbol Parameter

I DD

(Stop 2)

Supply current in Stop 2 mode,

RTC disabled

Conditions

Table 76. Current consumption in Stop 2 mode

TYP

RTC clocked by LSI

I DD

(Stop 2 with RTC)

RTC clocked by LSI with LPCAL = 1,

ULPEN = 1

Supply current in Stop 2 mode,

RTC enabled

RTC clocked by LSE bypassed at 32768 Hz with LPCAL = 0,

ULPEN = 0

RTC clocked by LSE bypassed at 32768 Hz with LPCAL = 1,

ULPEN = 1

MAX

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

3.07

16.61

68.35 158.43 332.53 19.03

67.19 202.18 407.53 797.08

3.09

16.86

69.13 160.32 335.88 19.08

67.43 201.94 409.7 802.29

3.13

17.24

69.5

161.75 341.1

19.18

67.79 203.72 412.34 812.99

3.2

17.42

71.15 164.99 349.3

19.39

68.67 205.04 415.22 816.69

3.66

17.32

68.52 159.57 333.56

19.7

67.81 202.19 408.09 797.2

3.88

17.74

69.73 160.86 338.16 20.07

68.34 202.52 410.27 802.48

4.2

17.94

70.57 163.39 342.82 20.37

68.62 205.35 413.58 813.45

4.42

18.71

72.31 166.43 348.19 20.79

69.72 205.83 416.46 818.3

3.5

17.14

69.36 159.76 332.52

3.62

17.68

70.03 161.58 336.53

3.82

4.06

18.2

18.8

71 163.7 343.17

72.72 168.58 351.22

3.44

17.15

68.39 159.57 333.37

3.58

17.35

69.8

161.86 336.47

3.79

17.77

70.33 163.41 342.2

4.59

18.34

72.03 166.18 350.97

3.18

16.98

69.4

160.31 335.07

3.27

17.29

69.65 161.79 339.1

3.41

17.91

71.21 163.77 343.27

4.16

18.5

72.62 167.08 350.59

Unit

µA

Symbol Parameter

Table 76. Current consumption in Stop 2 mode (continued)

Conditions TYP

MAX

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

RTC clocked by LSE quartz in low drive mode

I DD

(Stop 2 with RTC)

(continued)

Supply current in Stop 2 mode,

RTC enabled

(continued) RTC clocked by LSE quartz in low drive mode with LPCAL = 1,

ULPEN = 1

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

3.48

16.53

66.1

151.2 295.85

3.58

16.86

66.79 153.07 299.45

3.71

17.18

67.57 155.09 302.75

3.91

17.74

68.97 158.26 309.93

3.16

16.68

66.32 151.87 296.04

3.21

16.99

66.91 153.42 299.34

3.27

17.39

68.27 155.45 304.73

3.42

17.93

69.41 158.77 310.4

I DD

(wakeup from

Stop 2)

Wakeup clock is

MSI = 48 MHz, voltage Range 1

Supply current during wakeup from Stop 2 mode

Wakeup clock is

MSI = 4 MHz, voltage

Range 2

Wakeup clock is

HSI = 16 MHz, voltage Range 1

3 V

1.96

1.09

1.72

Unit

µA mA

Symbol Parameter

I DD

(Stop 1)

I DD

(Stop 1 with RTC)

Conditions

Table 77. Current consumption in Stop 1 mode

TYP

DD 25°C 55°C 85°C 105°C 125°C 25°C

Supply current in

Stop 1 mode,

RTC disabled

1.8 V

2.4 V

3 V

3.6 V

91.47

91.94

92.51

93.26

372.36

375.16

375.46

380.59

1243

1251

1249

1270

Supply current in

Stop 1 mode,

RTC enabled

RTC clocked by LSI

RTC clocked by LSE bypassed at

32768 Hz

1.8 V 92.46

373.25

1248

2.4 V 92.48

372.19

1250

3 V 93.34

374.54

1253

3.6 V 93.38

378.64

1267

1.8 V 92.35

371.81

1248

2.4 V 92.31

374.21

1245

3 V 93.59

375.92

1256

3.6 V 93.19

377.07

1262

RTC clocked by LSE quartz in low drive mode

1.8 V 100.67

381.08

1214

2.4 V 101.20

380.64

1224

3 V 102.04

378.49

1228

3.6 V 103.34

387.73

1239

2527

2531

2549

2567

4611

4652

4675

4721

4617

4643

4683

4712

4605

4640

4673

4713

2518

2528

2541

2559

2518

2521

2534

2551

2442

2447

2466

2480

1196

1199

1204

1215

1196

1201

1206

1213

55°C

3403

3418

3427

3433

3405

3433

3424

3434

MAX

85°C

8100

8133

8174

8158

8103

8135

8185

8176

105°C 125°C

13853

13906

13988

22830

22920

23189

14083

13874

13924

13994

14091

23335

22793

22927

23140

23336

Unit

µA

Symbol Parameter

Conditions

Table 77. Current consumption in Stop 1 mode (continued)

TYP

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C

I DD

(wakeup from Stop

Supply current during wakeup from Stop

1 mode

Wakeup clock is MSI = 48

MHz, voltage

Range 1

Wakeup clock is MSI = 4

MHz, voltage

Range 2

Wakeup clock is HSI = 16

MHz, voltage

Range 1

3 V

2.02

0.58

1.27

MAX

85°C 105°C 125°C

Unit

Symbol Parameter

I DD

(Stop 0)

Supply current in

Stop 0 mode,

RTC disabled

Conditions

DD 25°C

1.8 V 192.69

2.4 V 194.69

3 V 196.09

3.6 V 197.54

Table 78. Current consumption in Stop 0 mode

TYP

55°C

494.92

495.31

495.47

497.36

85°C

1425

1430

1431

1434

105°C

2797

2804

2812

2814

125°C

5106

5108

5124

5155

25°C

1395

1396

1397

1399

55°C

3797

3798

3799

3802

MAX

85°C

8974

8953

8996

8967

105°C

15426

15440

15465

15488

125°C

25827

25851

25967

26025

Unit

µA

Symbol

I DD

(Standby)

Parameter

Table 79. Current consumption in Standby mode

Conditions TYP

Supply current in

Standby mode

(backup registers retained),

RTC disabled

No independent watchdog

With independent watchdog

MAX

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

347

405

483

596

108

119

134

183

382

476

591

827

2374 7132 19259

2795 8332 22151

3215 9665 26746

4232 12128 31763

572

708

609

999

237

361

411

558

2269 6948 12467

2497 7770 14021

2716 8919 15987

3214 9577 17816

2578 7079 12599

2832 7868 14061

2913 8597 16110

3466 10069 18212

31340

40505

45394

50551

31388

39741

44085

48579

Unit nA

Symbol

I DD

(Standby with RTC)

Parameter

Table 79. Current consumption in Standby mode (continued)

Conditions TYP

MAX

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

RTC clocked by LSI, no independent watchdog

RTC clocked by LSI, no independent watchdog with

LPCAL = 1,

ULPEN = 1

Supply current in

Standby mode

(backup registers retained),

RTC enabled

RTC clocked by LSI, with independent watchdog

RTC clocked by LSE bypassed at

32768 Hz

RTC clocked by LSE bypassed at

32768 Hz with

LPCAL = 1,

ULPEN = 1

1.8 V

2.4 V

717

887

971 2924 7693 19714 930 2760 7456 12882

1266 3589 9054 22856 1224 3096 8393 14557

3 V 1113 1584 4206 10666 27521 1303 3509 9212 16779

3.6 V 1394 2059 5515 13394 32693 1828 3889 10504 18898

1.8 V

2.4 V

3 V

457

582

740

779

1080

1425

3075

4082

5195

8179

9786

11380

20106

23298

28044

3.6 V

1.8 V

2.4 V

3 V

766

948

1196

3.6 V 1492

1.8 V 435

2.4 V

3 V

569

768

711

954

2650 7592 19645

3254 8972 22787

1247 3963 10303 27154

3.6 V 1024 1686 5174 13141 32293

1.8 V 166 -

2.4 V

3 V

236

356

3.6 V

955

575

1905 6884 14210 33407

847 2549 7430 12888

1267 3171 8250 14679

1561 3610 9492 16773

1896 4136 10423 19143

31665

40166

44936

48363

31689

40296

44760

48559

Unit nA

Symbol

I DD

(Standby with RTC)

(continued)

I DD

(SRAM2)

I DD

(SRAM)

I DD (wakeup from

Standby)

Parameter

Supply current in

Standby mode

(backup registers retained),

RTC enabled

(continued)

RTC clocked by LSE quartz in low drive mode

RTC clocked by LSE quartz in low drive mode with

LPCAL = 1,

ULPEN = 1

Table 79. Current consumption in Standby mode (continued)

Conditions TYP

MAX

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

491

574

696

870

222

250

297

3.6 V 403 -

Supply current to be added in

Standby mode when Full SRAM2

(64KB) is retained

Supply current to be added in

Standby mode when partial

SRAM2 (4 KB) is retained

Supply current during wakeup from Standby mode

Wakeup clock is

MSI = 4 MHz

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

3 V

668

704

739

840

164

201

231

326

1.11

3089 13834 34240 75362 1834 8192 28470 36317 135595

3193 14412 35468 78515 1859 8376 28905 36890 140894

3283 14722 36843 82664 1907 8514 29857 37533 144576

3571 15867 38708 88150 1973 8919 30509 38460 149487

658 3378 9485 23856 518 2685 8359 8164 39054

764

871

3853

4319

10707

12043

26844

31160

585

606

2758

3243

9134

9975

8842

9601

47739

51857

1128 5250 14470 36553 723 3570 10872 10707 55419

Unit nA mA

Conditions

Table 80. Current consumption in Shutdown mode

TYP

Symbol Parameter

I DD

(Shutdown)

Supply current in

Shutdown mode

(backup registers retained)

RTC disabled

I DD

(Shutdown with RTC)

Supply current in

Shutdown mode

(backup registers retained)

RTC enabled

RTC clocked by LSE bypassed at

32768 Hz with

LPCAL = 0

RTC clocked by LSE bypassed at

32768 Hz with

LPCAL = 1

RTC clocked by LSE quartz in low drive mode with

LPCAL = 0

RTC clocked by LSE quartz in low drive mode with

LPCAL = 1

DD 25°C

1.8 V 17.0

2.4 V 18.0

3 V 44.0

3.6 V 127.0

1.8 V 307

2.4 V 485

3 V 689

3.6 V 974

1.8 V 116

2.4 V 221

3 V 339

3.6 V 535

1.8 V 405

2.4 V 486

3 V 604

3.6 V 768

1.8 V 207

2.4 V 232

3 V 272

3.6 V 345

55°C

198

269

361

587

325

491

656

996

525

746

1015

1435

85°C

1533

1803

2314

3159

105°C 125°C

5195 15336

6166 17522

7212 21381

9534 26115

1905

2363

2905

5592

6676

7919

15801

18041

22214

4082 10392 26856

1711

2100

2636

3645

5423 15551

6395 17909

7450

9998

21753

26420

25°C

115

141

196

55°C

590

679

800

990

MAX

85°C

3169

3610

4108

4877

105°C 125°C

9252 26038

10477 29468

11860 32843

13734 37480

Unit nA

Symbol Parameter

Table 80. Current consumption in Shutdown mode (continued)

Conditions TYP

MAX

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

I DD

(wakeup from

Shutdown)

Supply current during wakeup from

Shutdown mode

Wakeup clock is

MSI = 4 MHz

3 V 0.53

Unit mA

Symbol Parameter

I DD

(VBAT)

Backup domain supply current

Conditions

Table 81. Current consumption in VBAT mode

TYP

MAX

BAT 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

RTC disabled

RTC enabled and clocked by LSE bypassed at

32768 Hz with

LPCAL = 0

RTC enabled and clocked by LSE bypassed at

32768 Hz with

LPCAL=1

RTC enabled and clocked by LSE quartz with

LPCAL = 0

RTC enabled and clocked by LSE quartz with

LPCAL = 1

1.8 V

2.4 V

3.4

3.9

3 V 5.9

3.6 V 13.4

1.8 V 330

2.4 V 446

3 V 632

3.6 V 867

1.8 V 130

2.4 V 183

3 V 288

3.6 V 392

1.8 V 387

2.4 V 461

3 V 568

3.6 V 700

1.8 V 187

2.4 V 202

3 V 229

3.6 V 275

381

406

441

518

136

307

358

447

786

966 2699

1097 2995

1350 3699

2303 6528

369

528

654

843

1303

1595

727 1119 2045

996 1680 3247 -

692

738

841

1163

1369

1499

1761

2707

Electrical characteristics STM32L552xx

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see ), the

I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

206/340 DS12737 Rev 6

STM32L552xx

AHB

Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 82 . The MCU is placed

under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 24:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 82 . The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 82. Peripheral current consumption

Peripheral

Bus matrix

DMA1

DMA2

DMAMUX1

FLASH

SRAM1

CRC

TSC

GTZC

ICACHE

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

SRAM2

ADC AHB clock domain

ADC independent clock domain

Range 0

0.21

0.16

0.14

0.22

0.21

2.34

4.16

0.08

0.76

1.24

0.27

0.30

0.17

4.09

2.54

2.56

4.96

3.69

1.43

0.27

0.26

0.17

0.18

0.26

0.27

3.08

5.49

0.14

0.99

1.67

0.36

0.38

0.41

0.23

5.47

3.38

3.43

6.64

4.95

1.90

0.31

0.30

0.19

0.21

0.32

0.29

3.32

5.92

0.15

1.05

1.77

0.38

0.40

0.25

5.85

3.67

3.71

7.11

5.32

2.03

Range 1 Range 2

Low-power run and sleep

0.37

0.26

0.21

0.19

0.31

0.25

2.90

5.11

0.14

0.95

1.49

0.35

1.00

0.32

0.22

5.36

3.16

3.20

6.16

4.59

1.75

Unit

µA/MHz

DS12737 Rev 6 207/340

307

Electrical characteristics STM32L552xx

AHB

(Cont)

APB1

HASH

RNG AHB clock domain

RNG independent clock domain

SDMMC1 AHB clock domain

SDMMC1 independent clock domain

FMC

OSPI1 AHB clock domain

OPSPI1 independent clock domain

ALL AHB peripherals

AHB to APB1 bridge

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

RTCAPB

WWDG

SPI2

SPI3

USART2 APB clock domain

USART2 independent clock domain

USART3 APB clock domain

USART3 independent clock domain

UART4 APB clock domain

UART4 independent clock domain

UART5 APB clock domain

Table 82. Peripheral current consumption (continued)

Peripheral Range 0

2.73

6.49

2.60

5.26

2.58

3.32

0.52

2.34

2.22

3.14

5.99

47.47

0.43

6.19

5.08

5.02

6.47

1.04

1.16

3.64

2.27

6.12

19.07

6.63

10.39

10.00

0.11

2.96

6.96

2.81

5.59

2.75

3.50

0.58

2.52

2.39

3.40

6.41

47.58

0.41

6.65

5.46

5.38

6.92

1.12

1.24

3.91

2.44

4.55

20.52

4.92

11.17

10.77

0.12

Range 1 Range 2

Low-power run and sleep

2.57

6.09

2.48

4.85

2.45

3.08

0.48

2.25

2.16

3.03

5.53

350.76

0.61

5.81

4.75

4.73

6.08

0.98

9.90

9.57

1.00

3.44

Unit

µA/MHz

2.12

4.86

1.99

3.95

1.99

2.50

0.40

1.78

1.69

2.39

4.50

55.06

0.36

4.67

3.82

3.78

4.86

0.79

0.86

7.82

7.61

0.04

2.74

208/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

APB1

(Cont)

APB2

UART5 independent clock domain

I2C1 APB clock domain

I2C1 independent clock domain

I2C2 APB clock domain

I2C2 independent clock domain

I2C3 APB clock domain

I2C3 independent clock domain

CRS

PWR

DAC1

OPAMP

LPTIM1 APB clock domain

LPTIM1 independent clock domain

LPUART1 APB clock domain

LPUART1 independent clock domain

I2C4 APB clock domain

I2C4 independent clock domain

LPTIM2 APB clock domain

LPTIM2 independent clock domain

LPTIM3 APB clock domain

LPTIM3 independent clock domain

FDCAN APB clock domain

FDCAN independent clock domain

USBFS APB clock domain

USBFS independent clock domain

UCPD1

AHB to APB2 bridge

SYSCFG

TIM1

SPI1

TIM8

USART1 APB clock domain

Table 82. Peripheral current consumption (continued)

Peripheral Range 0

0.16

3.51

4.53

2.67

6.64

0.75

9.40

2.69

8.94

3.16

3.31

1.36

3.80

1.02

3.16

7.99

1.54

2.89

0.34

1.10

3.37

1.66

3.43

1.40

3.33

1.14

2.75

0.35

5.59

1.42

3.47

1.32

Range 1

0.22

3.25

6.08

2.46

6.16

0.71

8.74

2.51

8.34

2.92

3.11

1.26

3.58

0.93

2.98

7.41

1.44

2.69

0.36

1.01

3.18

1.54

3.24

1.28

3.11

1.05

2.58

0.30

5.19

1.34

3.22

1.24

Range 2

Low-power run and sleep

(1)

8.43

0.67

8.33

2.43

8.06

3.09

2.90

1.15

3.35

0.94

2.80

6.70

4.05

1.22

2.43

1.00

0.87

3.07

1.61

2.99

1.24

3.06

0.90

2.61

0.50

4.79

1.22

3.12

1.10

Unit

µA/MHz

3.20

1.84

4.68

0.54

6.57

1.90

6.29

2.23

2.34

0.96

2.66

0.74

2.21

5.56

1.03

2.03

0.23

0.78

2.39

1.19

2.44

0.97

2.37

0.81

1.97

0.22

3.90

1.00

2.46

0.93

DS12737 Rev 6 209/340

307

Electrical characteristics STM32L552xx

Table 82. Peripheral current consumption (continued)

Peripheral

APB2

(Cont)

ALL

USART1 independent clock domain

TIM15

TIM16

TIM17

SAI1 APB clock domain

SAI1 independent clock domain

SAI2 APB clock domain

SAI2 independent clock domain

DFSDM1

1. The UCPD1 is always clocked by the HSI16.

Range 0

3.04

2.20

3.32

2.14

7.01

4.93

3.27

3.76

8.18

275.73

Range 1

2.84

2.92

3.07

2.94

6.54

4.60

3.05

3.49

7.61

256.25

2.12

2.85

2.30

4.91

3.45

2.29

2.62

5.73

188.42

Range 2

Low-power run and sleep

0.50

2.5

2.99

6.01

4.45

2.83

3.40

7.42

233

Unit

µA/MHz

210/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

5.3.7

Sleep

Stop 0

Stop 1

Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in

Table 83 are the latency between the event and the execution of

the first user instruction.

The device goes in low-power mode after the WFE (wait for event) instruction.

Parameter

Table 83. Low-power mode wakeup timings

(1)

Conditions Typ

Wakeup time from Sleep mode to Run mode

Wakeup time from Lowpower sleep mode to Lowpower run mode

Sleep Power Down

(SLEEP_PD=1 in FLASH_ACR) and with clock

MSI = 2 MHz

Flash

SRAM1

Flash

SRAM1

Flash

SRAM1

Range 1

Range 2

Range 1

Range 2

Range 1

Range 2

Range 1

Range 2

Low Power

Run (LPR=1)

MSI48

HSI16

MSI24

5.83

5.23

18.48

HSI16 17.56

MSI4 23.36

MSI48 1.79

HSI16

MSI24

HSI16

2.79

2.43

2.80

MSI4 9.66

MSI48 9.74

HSI16 9.22

MSI24

HSI16

21.84

20.98

MSI4 25.48

MSI48

HSI16

MSI24

5.58

6.68

5.69

HSI16 6.18

MSI4 11.04

81.2

MSI2

17.8

Max

Unit

Number of

CPU cycles

µs

10.88

10.22

9.67

22.63

21.81

26.34

6.26

5.46

18.96

17.94

24.59

2.16

3.01

2.82

3.03

5.95

7.06

6.24

6.88

11.99

82.5

DS12737 Rev 6 211/340

307

Electrical characteristics

Stop 2

Standby

Table 83. Low-power mode wakeup timings (1) (continued)

Parameter Conditions Typ Max

Flash

SRAM1

Flash

Flash with

SRAM2

Range 1

Range 2

Range 1

Range 2

Shutdown Flash Range 2

1. Guaranteed by characterization results.

MSI48

HSI16

MSI24

HSI16

11.20

10.35

23.76

22.24

MSI4 27.81

MSI48 6.19

HSI16

MSI24

7.33

6.31

HSI16 6.89

MSI4 11.69

MSI8

MSI4

52.5

52.58

MSI8 52.5

MSI4 52.60

MSI4 276.48

7.22

12.36

55.73

55.78

55.74

55.73

292.42

11.64

10.77

24.15

22.62

28.46

6.61

7.75

6.64

STM32L552xx

Unit

µs

Symbol

Table 84. Regulator modes transition times (1)

Parameter Conditions t t

WULPRUN

VOST

Wakeup time from Low- power run mode to Run mode (2)

Code run with MSI 2 MHz

Regulator transition time from

Range 2 to Range 1 or

Range 1 to Range 2

(3)

Code run with MSI 24 MHz

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Typ Max Unit

5 7

μ s

20 40

Symbol

Table 85. Wakeup time using USART/LPUART (1)

Parameter t t

WUUSART

WULPUART

Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when

USART/LPUART clock source is

HSI

1. Guaranteed by design.

Conditions

Stop mode 0

Stop mode 1/2

Typ Max Unit

1.7

8.5

μ s

212/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.15

. However,

Symbol

Table 86. High-speed external user clock characteristics (1)

Parameter Conditions Min f

HSE_ext

User external clock source frequency

Voltage scaling

Range 0 and 1

Voltage scaling

Range 2

t t

HSEH

HSEL w(HSEH) w(HSEL)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

Voltage scaling

Range 0 and 1

Voltage scaling

Range 2

1. Guaranteed by design.

0.7 V

DDIOx

Typ

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

Figure 33. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

DS12737 Rev 6 213/340

307

Electrical characteristics STM32L552xx

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.15

. However,

Symbol

Table 87. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

User external clock source frequency

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL)

OSC32_IN high or low time

1. Guaranteed by design.

Conditions

Min

0.7 V

DDIOx

250

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 34. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tw(LSEL) t

MS19215V2

214/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 88 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 88. HSE oscillator characteristics (1)

Parameter Conditions

(2)

Min Typ Max Unit

I f

OSC_IN

DD(HSE)

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 30 Ω ,

CL = 5 pF@48 MHz

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@48 MHz

200

0.44

0.45

0.68

0.94

5.5

MHz k Ω mA

= 3 V,

Rm = 30 Ω ,

CL = 20 pF@48 MHz

1.77

G m

Maximum critical crystal transconductance

Startup 1.5

mA/V t

SU(HSE)

(4)

Startup time V

is stabilized 2 ms

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 35

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

DS12737 Rev 6 215/340

307

Electrical characteristics

Note:

STM32L552xx

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 35. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN f

HSE

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 89 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

216/340 DS12737 Rev 6

STM32L552xx

Note:

Electrical characteristics

Symbol

Table 89. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions

(2)

Min Typ Max Unit

DD(LSE)

LSE current consumption

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

250

315

500

630 -

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

0.5

0.75

Gm critmax

Maximum critical crystal gm

1.7

µA/V

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

2.7

SU(LSE)

(3)

Startup time V

is stabilized 2 -

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 36. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

DS12737 Rev 6 217/340

307

Electrical characteristics

5.3.9 Internal clock source characteristics

STM32L552xx

The parameters given in

Table 90 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 27: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol

Table 90. HSI16 oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit

DuCy(HSI16)

(2) t

∆

Temp

VDD t su stab

DD f

HSI16

TRIM

(HSI16)

HSI16 Frequency

HSI16 user trimming step

=3.0 V, T

=30 °C 15.88

Trimming code is not a multiple of 64

0.2

Trimming code is a multiple of 64

-4

45 Duty Cycle

HSI16 oscillator frequency drift over temperature

= 0 to 85 °C

= -40 to 125 °C

HSI16 oscillator frequency drift over V

HSI16 oscillator start-up time

=1.62 V to 3.6 V

-1

-2

-0.1

HSI16 oscillator stabilization time

HSI16 oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

0.3

-6

0.8

16.08 MHz

0.4

-8

1.5

0.05

1.2

μ s

155 190 μ A

218/340 DS12737 Rev 6

STM32L552xx

MHz

16.4

16.3

16.2

16.1

15.9

15.8

15.7

15.6

-40 -20

Electrical characteristics

Figure 37. HSI16 frequency versus temperature

+2 %

+1.5 %

+1 %

Mean

-1 %

-1.5 %

-2 %

40 min

60 80 max

100 120 °C

MSv39299V2

DS12737 Rev 6 219/340

307

Electrical characteristics STM32L552xx

Multi-speed internal (MSI) RC oscillator

Symbol f

MSI

∆

TEMP

(MSI)

Parameter

MSI frequency after factory calibration, done at V

=3 V and

=30 °C

MSI oscillator frequency drift over temperature

MSI mode

PLL mode

XTAL=

32.768 kHz

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

= -0 to 85 °C

MSI mode

= -40 to 125 °C

Table 91. MSI oscillator characteristics

(1)

Conditions Min

98.7

197.4

394.8

7896

0.987

1.974

3.948

7.896

15.79

23.69

31.58

47.38

-3.5

-8

Typ

98.304

196.608

393.216

786.432

1.016

1.999

100

200

400

800

3.998

7.995

15.991

23.986

32.014

48.005

Max Unit

101.3

202.6

405.2

810.4

kHz

1.013

2.026

4.052

8.104

MHz

16.21

24.31

32.42

48.62

kHz

MHz

220/340 DS12737 Rev 6

STM32L552xx

Symbol

Table 91. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min

∆

VDD

(MSI)

(2)

CC jitter(MSI)

(4)

P jitter(MSI)

MSI oscillator frequency drift over V

(reference is

3 V)

MSI mode

Range 0 to 3

Range 4 to 7

=1.62 V to 3.6 V

=2.4 V to 3.6 V

=1.62 V to 3.6 V

=2.4 V to 3.6 V

Range 8 to 11

=1.62 V to 3.6 V

=2.4 V to 3.6 V

= -40 to 85 °C Frequency variation in sampling mode

(3)

MSI mode

= -40 to 125 °C

RMS cycle-tocycle jitter

PLL mode Range 11

RMS Period jitter PLL mode Range 11 -

t t

(MSI)

STAB

(MSI)

MSI oscillator start-up time

Range 0

Range 1

Range 2

Range 3

MSI oscillator stabilization time

Range 4 to 7

Range 8 to 11

PLL mode

Range 11

10 % of final frequency

5 % of final frequency

1 % of final frequency

-1.2

-0.5

-2.5

-0.8

-5

-1.6

Electrical characteristics

Typ

2.5

0.25

0.5

Max Unit

0.5

0.7

0.5

ps ps us

1.25

2.5

DS12737 Rev 6 221/340

307

Electrical characteristics

Symbol

Table 91. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min

(MSI)

MSI oscillator power consumption

MSI and

PLL mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Guaranteed by design.

Typ

1.9

4.7

6.5

0.6

0.8

1.2

18.5

110

155

STM32L552xx

Max Unit

2.5

1.2

1.7

110

130

190

µA

Figure 38. Typical current consumption versus MSI frequency

222/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 92. HSI48 oscillator characteristics

(1)

Parameter Conditions Min Typ Max Unit f

HSI48

TRIM

HSI48 Frequency

HSI48 user trimming step

=3.0V, T

=30°C

USER TRIM

COVERAGE

ACC

D t

HSI48_REL

VDD su

(HSI48)

HSI48 user trimming coverage

DuCy(HSI48) Duty Cycle

±32 steps

±3

(3)

Accuracy of the HSI48 oscillator over temperature

(factory calibrated)

HSI48 oscillator frequency drift with V

= 3.0 V to 3.6 V,

= –15 to 85 °C

= 1.65 V to 3.6 V,

= –40 to 125 °C

= 3 V to 3.6 V

= 1.65 V to 3.6 V -

HSI48 oscillator start-up time

(HSI48)

jitter

HSI48 oscillator power consumption

Next transition jitter

Accumulated jitter on 28 cycles

(4)

Paired transition jitter

Accumulated jitter on 56

cycles (4)

0.11

±3.5

(2)

0.025

0.05

2.5

340

1. V

= 3 V, T

= –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

+/-0.15

+/-0.25

0.18

Table 94 are derived from tests performed under temperature and

MHz

±3

±4.5

0.05

0.1

380

μ s

A ns ns

DS12737 Rev 6 223/340

307

Electrical characteristics STM32L552xx

Figure 39. HSI48 frequency versus temperature

-2

-4

-6

-50 -30 -10

Avg

10 30 min

50 70

Low-speed internal (LSI) RC oscillator

Symbol

Table 93. LSI oscillator characteristics (1)

Parameter Conditions t t

STAB

DD f

LSI

(LSI)

(2)

LSI Frequency

= 3.0 V,

= 30 °C

= 1.62 to 3.6 V,

= -40 to 125 °C

LSI oscillator start-up time

LSI oscillator stabilization time

5% of final frequency

LSI oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

Min

31.04

29.5

90 max

110 130

°C

MSv40989V1

Typ

125

110

Max Unit

32.96

130

180

180 kHz

μ s

μ s nA

224/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

The parameters given in

supply voltage conditions summarized in

Symbol

Table 94. PLL, PLLSAI1, PLLSAI2 characteristics

(1)

Parameter

PLL input clock

(2)

Conditions

Min

2.66

Typ Max Unit

16 MHz f f

PLL_IN

PLL_P_OUT

PLL input clock duty cycle

PLL multiplier output clock P

Voltage scaling Range 1 2.0645

Voltage scaling Range 0 2.0645

Voltage scaling Range 2 2.0645

PLL_Q_OUT

PLL multiplier output clock Q

Voltage scaling Range 1

Voltage scaling Range 0

Voltage scaling Range 2

Voltage scaling Range 1 f

PLL_R_OUT

PLL multiplier output clock R Voltage scaling Range 0

Voltage scaling Range 2

Voltage scaling Range 1

64 f

VCO_OUT

PLL VCO output t

LOCK

Jitter

PLL lock time

RMS cycle-to-cycle jitter

RMS period jitter

Voltage scaling Range 2

System clock 80 MHz

(PLL)

PLL power consumption on

VCO freq = 64 MHz

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz -

110

344

128

30 -

150 200

200 260

300 380

520 650

MHz

μ s

±ps

μ A

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 3 PLLs.

DS12737 Rev 6 225/340

307

Electrical characteristics STM32L552xx t

Symbol t prog prog_row t prog_page

Table 95. Flash memory characteristics (1)

Parameter

64-bit programming time

One row (64 double word) programming time

One page (4 Kbytes) programming time

Conditions

Normal programming

Fast programming

Normal programming

Fast programming

Typ

81.69

2.61

20.91

NA t

ERASE

Page (4 Kbytes) erase time

22.02

t prog_bank

One bank (1 Mbyte) programming time

Normal programming

Fast programming

2.68

NA t

Mass erase time

(one or two banks)

22.13

Average consumption from V

Maximum current (peak)

Write mode

Erase mode

Write mode

Erase mode

3.1

1. Guaranteed by design.

Symbol

Table 96. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle (2) at T

= 85 °C

= 105 °C

= 125 °C

10 kcycles

at T

= 55 °C

10 kcycles

(2) at T

= 85 °C

10 kcycles

The test results are given in Table 97

at T

= 105 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Min (1)

Unit kcycles

Years

Max Unit

83.35

µs

2.67

21.34

NA ms

24.47

2.73

NA s

24.59

NA mA

226/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 97. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SS f

= 3.3 V, T

HCLK

= +25 °C,

= 110 MHz, conforming to IEC 61000-4-2 f

= 3.3 V, T

HCLK

= +25 °C,

= 110 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

DS12737 Rev 6 227/340

307

Electrical characteristics STM32L552xx

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol Parameter

EMI

Peak level

Table 98. EMI characteristics

Conditions

= 3.6 V,

A =

25°C,

LQFP144 package compliant with IEC

61967-2

Monitored frequency band

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

Max vs

HSE

HCLK

]

8 MHz / 110 MHz

3.5

Unit dB μ V

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 99. ESD absolute maximum ratings

Symbol Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

ESD(CDM)

Electrostatic discharge voltage (charge device model)

= +25 °C, conforming to

ANSI/ESDA/JEDEC JS-001

= +25 °C, conforming to

ANSI/ESDA/JEDEC

JS-002

LQFP144, LQFP100,

WLCSP81

Other packages

1. Guaranteed by characterization results.

C2a

2000

250

500

228/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Static latch-up

Two complementary static tests are required on three parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78E IC latch-up standard.

Symbol

Parameter

Table 100. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78E

Class

Class II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 101

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol

Table 101. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Unit

INJ

(1)

Injected current on all pins except TT_a, PB0, PB15,

PE9, PG0

Injected current on pins PB0, PB15, PE9, PG0

Injected current on TT_a pins

1. Guaranteed by characterization.

-5

0 mA

DS12737 Rev 6 229/340

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Sym bol

General input/output characteristics

Unless otherwise specified, the parameters given in Table 102 are derived from tests performed under the conditions summarized

in Table 27: General operating conditions

. All I/Os are designed as CMOS- and TTL-compliant.

Parameter

(1)

I/O input low level voltage

I/O input high level voltage

All IOs except FT_c

FT_c

hys

Input hysteresis

All IOs except FT_c

FT_c

TT_xx, FT_xx and

NRST

FT_sx

Table 102. I/O static characteristics

Conditions

1.62 V < V

DDIOx

< 3.6 V

1.62 V < V

DDIOx

< 3.6 V

1.08 V < V

DDIOx

< 1.62 V

1.62 V < V

DDIOx

< 3.6 V

1.62 V < V

DDIOx

< 3.6 V

1.08 V < V

DDIOx

< 1.62 V

1.62 V < V

DDIOx

< 3.6 V

1.62 V < V

DDIOx

< 3.6 V

1.08 V < V

DDIOx

< 1.62 V

1.62 V < V

DDIOx

< 3.6 V

1.08 V < V

DDIOx

< 1.62 V

1.62 V < V

DDIOx

< 3.6 V

1.08 V < V

DDIOx

< 1.62 V

Min Typ Max Unit

0.7×V

DDIOx

0.49×V

DDIOX

+0.26

0.61×V

DDIOX

+0.05

0.7×V

0.7×V

200

0.3×V

DDIOx

(2)

0.39×V

DDIOx

-0.06

0.43×V

DDIOx

-0.1

0.3×V

0.25×V

0.2×V

V mV

150 -

Table 102. I/O static characteristics (continued)

Sym bol

Parameter Conditions Min Typ Max Unit

I lkg

Input leakage current

FT_xx

FT_u

TT_xx

(3)

OPAMPx_VINM(x=1,2)

FT_c

FT_d

0 < V

≤ Max(V

DDXXX

)

(4)(5)

Max(V

DDXXX

) ≤ V

≤ Max(V

DDXXX

) + 1 V

Max(V

DDXXX

) + 1 V < V

≤

5.5 V

0 <V

≤ Max(V

DDXXX

)

Max(V

DDXXX

) ≤ V

≤ Max(V

DDXXX

) +1 V

Max(V

DDXXX

) +1 V < VIN ≤

5.5 V

(4)(5)(7)

≤ Max(V

DDXXX

)

Max(V

DDXXX

) ≤ V

< 3.6 V

0 <V

≤ Max(V

DDXXX

)

Max(V

DDXXX

) < V

≤

5 V

(3)(5)(6)

0 <V

≤ Max(V

DDXXX

)

Max(V

DDXXX

) < V

≤ 5.5 V

(3)(4)(5)

= V

DDIOx

±100

650

200

±150

2500

(6)

250

±150

2000

Figure 40: I/O input characteristics

(8)

2000

3000

4500

9000

Weak pull-up equivalent resistor

Weak pull-down equivalent resistor

I/O pin capacitance

1. Refer to

2. Guaranteed by design.

3. All FT_xx IO except FT_u and FT_c.

4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula: I applied on the pad] × I lkg

(Max).

Total_Ileak_max

= 10 μ A + [number of IOs where V

5. Max(V

DDXXX

) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.

6. To sustain a voltage higher than MIN(V

, V

DDA

, V

DDIO2

and V

DDUSB

) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled.

7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

8. Refer to I bias

Table 119: OPAMP characteristics for the values of the OPAMP dedicated input leakage current.

nA k Ω k Ω pF

Electrical characteristics STM32L552xx

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 40

for standard I/Os, and in

Figure 40

for

5 V tolerant I/Os.

Figure 40. I/O input characteristics

Vil – Vih all IO

TTL requirement Vih min = 2V

min = 0

.7xV

DDIO x

DDIOx

+0.2

6 for V

DDIOx

>1.6

DDIOx

<1.62 or

0.49xV

Teste d in production CMOS requirement Vih on Vi h min = 0.

lation V il max

61xV

DDIOx

=0.43xV

DDIOx

+0.05

for 1.08<V

-0.1 for 1.08

<V DDIOx

<1.62 or 0.39xV

ax = 0.3xVdd

DDIOx

-0.06 for V

DDIO x

>1.62

TTL requirement Vil max = 0.8V

Based on simu uirement Vil m

Tested in produ ction CMOS req

MSv62973V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

• The sum of the currents sourced by all the I/Os on V

DDIOx, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see Table 24: Voltage characteristics ).

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating

Table 24: Voltage characteristics

Σ I

VSS

(see

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 27: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

232/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

Table 103. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

DDIOx

(2)

= 2 mA for FT_c

| = 8 mA for other I/Os

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

TTL port

DDIOx

= 2 mA for FT_c

|= 8 mA for other I/Os

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

All I/Os except FT_c

| = 20 mA

DDIOx

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

| = 1 mA for FT_c

| = 4 mA for other I/Os

1.62 V ≤ V

DDIOx

≤ 3.6 V

DDIOx

2.4

DDIOx

-0.4

-1.3

-0.45

0.4

1.3

0.4

Voltage characteristics

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

| = 1 mA for FT_c

| = 2 mA for other I/Os

1.08 V ≤ V

DDIOx

< 1.62 V

0.65

ₓ

DDIOx

0.35

ₓ

DDIOx

Output low level voltage for an FT I/O pin in FM+ mode

(FT I/O with "f" option)

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA

1.62 V ≤ V

DDIOx

≤ 3.6 V

| = 2 mA

1.08 V ≤ V

DDIOx

< 1.62 V

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 24:

, and the sum of respect the absolute maximum ratings the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

Σ I

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 41

and

Table 104

, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 27: General operating conditions

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Electrical characteristics STM32L552xx

Table 104. I/O AC characteristics (All I/Os except FT_c) (1)(2)

Speed Symbol Parameter Conditions Min Max

Fmax

Tr/Tf

Fmax

Tr/Tf

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

140

110

1.5

0.1

4.5

Unit

MHz ns

234/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 104. I/O AC characteristics (All I/Os except FT_c) (1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit

Fm+

Fmax

Tr/Tf

Fmax

Tr/Tf

Fmax

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=30 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=30 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=30 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=30 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=30 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=30 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

Maximum frequency

Output fall time

(4)

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 3.6 V

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the

SYSCFG_CFGR1 register. Refer to the RM0438 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 110 MHz.

4. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

110

180

(3)

2.5

3.3

37.5

5.8

100

MHz ns

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Electrical characteristics STM32L552xx

Speed Symbol

Table 105. FT_c I/O AC characteristics (1)(2)

Parameter Conditions Min Max Unit

Fmax

Tr/Tf

Fmax

Tr/Tf

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 3.6 V -

0.1

170

330

3300

0.7

400

1. The I/O speed is configured using the OSPEEDRy[0] bit. Refer to the RM0438 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

MHz ns

Figure 41. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t r(IO)out t f(IO)out

T when loaded by the specified capacitance.

MS32132V2

1. Refer to Table 104: I/O AC characteristics (All I/Os except FT_c)

5.3.16 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 106: NRST pin characteristics

236/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

Table 106. NRST pin characteristics (1)

Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

V hys(NRST)

F(NRST)

NF(NRST)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST input filtered pulse

NRST input not filtered pulse

= V

1.71 V ≤ V

≤ 3.6 V

0.7

ₓ V

DDIOx

350

200

0.3

ₓ V

DDIOx

V mV k Ω ns ns

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

Figure 42. Recommended NRST pin protection

External reset circuit

(1) V

NRST

(2)

Filter

Internal reset

0.1 μF

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

. Otherwise the reset is not taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.17 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is detected by the event controller.

Table 107. EXTI input characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

PLEC

Pulse length to event controller

1. Guaranteed by design.

20 ns

DS12737 Rev 6 237/340

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Electrical characteristics STM32L552xx

5.3.18 Analog switches booster

Symbol

Table 108. Analog switches booster characteristics (1)

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3 .6 V

1. Guaranteed by design.

Min

1.62

Typ

Max

3.6

240

250

500

900

Unit

µs

µA

238/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Note:

Unless otherwise specified, the parameters given in

Table 109 are preliminary values

derived from tests performed under ambient temperature, f

PCLK frequency and V voltage conditions summarized in

Refer to Section 4: Pinouts and pin description for further details.

DDA

supply

It is recommended to perform a calibration after each power-up.

Symbol

DDA

REF+

REFf

ADC f s f

TRIG

AIN

(3)

AIN

ADC

Table 109. ADC characteristics

(1) (2)

Parameter Conditions Min Typ

Analog supply voltage

Positive reference voltage

Negative reference voltage

DDA

≥ 2 V

< 2 V

ADC clock frequency

Sampling rate for FAST channels

Sampling rate for SLOW channels

External trigger frequency

Range 0 and 1

Range 2

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits f

ADC

= 80 MHz

Resolution = 12 bits

Conversion voltage range(2)

External input impedance

Internal sample and hold capacitor

1.62

DDA

SSA

Max

3.6

DDA

5.33

6.15

7.27

8.88

4.21

4.71

5.33

6.15

5.33

REF+

Unit

MHz

Msps

MHz

1/f

ADC

V k Ω pF t

STAB t

CAL

Power-up time -

Calibration time f

ADC

= 80 MHz

1.45

116 conversi on cycle

µs

1/f

ADC

DS12737 Rev 6 239/340

307

Electrical characteristics STM32L552xx

Symbol

Table 109. ADC characteristics (1) (2) (continued)

Parameter Conditions Min Typ Max Unit t t t

LATR

LATRINJ t s

ADCVREG_STU

Trigger conversion latency Regular and injected channels without conversion abort

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Trigger conversion latency Injected channels aborting a regular conversion

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Sampling time f

ADC

= 80 MHz

ADC voltage regulator startup time

Total conversion time

(including sampling time) f

ADC

= 80 MHz

Resolution = 12 bits

1.5

2.5

0.03125

2.5

0.1875

2.5

2.0

2.25

2.125

3.5

3.0

3.25

3.125

8.00625

640.5

8.1625

1/f

ADC

µs

ADC

µs

I t

CONV

DDA

(ADC)

DDV_S

DDV_D

(ADC)

ADC consumption from the V

DDA supply

ADC consumption from the V

REF+ single ended mode

ADC consumption from the V

REF+ differential mode fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps ts + 12.5 cycles for successive approximation

= 15 to 653

730 830

160

130

0.6

260

1.3

220

160

310

1/f

ADC

µA

1. Guaranteed by design

2. The I/O analog switch voltage booster is enable when V

SYSCFG_CFGR1 when V

DDA

< 2.4V). It is disable when V

< 2.4 V (BOOSTEN = 1 in the

DDA

≥ 2.4 V.

REF+

can be internally connected to V the package.

DDA

and V

REF-

can be internally connected to V

SSA

, depending on

240/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

The maximum value of R

AIN

can be found in Table 110: Maximum ADC RAIN

Resolution

Table 110. Maximum ADC R

AIN

(1)(2)

Sampling cycle

@80 MHz

Sampling time

[ns] @80 MHz

AIN

max ( Ω )

Fast channels

(3)

12 bits

10 bits

8 bits

6 bits

92.5

247.5

640.5

2.5

6.5

12.5

640.5

2.5

6.5

12.5

24.5

47.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

8006.75

31.25

81.25

156.25

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

306.25

593.75

1156.25

3093.75

8006.75

6800

15000

50000

220

560

1200

47000

180

470

1000

1800

2700

39000

120

390

820

1500

2200

5600

12000

100

330

680

1500

2200

4700

12000

2700

3900

8200

18000

50000

5600

12000

50000

N/A

330

1000

39000

N/A

270

680

1500

2200

33000

N/A

180

560

1200

1800

4700

10000

N/A

100

470

1200

1800

3900

10000

2200

3300

6800

15000

50000

(4)

DS12737 Rev 6 241/340

307

Electrical characteristics

1. Guaranteed by design.

2. The I/O analog switch voltage booster is enable when V

SYSCFG_CFGR1 when V

DDA

< 2.4V). It is disable when V

< 2.4 V (BOOSTEN = 1 in the

DDA

≥ 2.4 V.

3. Fast channels are: PC0, PC1, PC2, PC3, PA0.

4. Slow channels are: all ADC inputs except the fast channels.

STM32L552xx

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STM32L552xx Electrical characteristics

Table 111. ADC accuracy - limited test conditions 1 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= VREF+ = 3 V,

TA = 25 °C

(ADC clock frequency ≤

58 MHz for LQFP144)

Single ended

Differential

Single ended

Differential

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

3.5

1 2

1.5

2.5

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

1.5

2.5

Fast channel (max speed) 10.4 10.5

Slow channel (max speed) 10.4 10.5

Fast channel (max speed) 10.8 10.9

4 5

3.5

4.5

3.5

4.5

1 2.5

1.5

2.5

1.5

2.5

4.5

2.5

4.5

2.5

3.5

2.5

3.5

Slow channel (max speed) 10.8 10.9

Fast channel (max speed) 64.4 65 -

Slow channel (max speed) 64.4 65 -

Fast channel (max speed) 66.8 67.4

Slow channel (max speed) 66.8 67.4

Fast channel (max speed) 65 66 -

Slow channel (max speed) 65 66

Fast channel (max speed) 67 68

Slow channel (max speed) 67 68

LSB bits dB

DS12737 Rev 6 243/340

307

Electrical characteristics STM32L552xx

Table 111. ADC accuracy - limited test conditions 1 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= V

REF+

= 3 V,

TA = 25 °C

(ADC clock frequency ≤

58 MHz for LQFP144)

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -73

-79 -76

-79 -76 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

244/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 112. ADC accuracy - limited test conditions 2 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA

(ADC clock frequency ≤

58 MHz for LQFP144)

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) 1 3.5

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed) -

3.5

2.5

4.5

2.5

4.5

1 3

Slow channel (max speed) 1 2.5

Fast channel (max speed) 10 10.5

Slow channel (max speed) 10 10.5

Fast channel (max speed) 10.7 10.9

Slow channel (max speed) 10.7 10.9

Fast channel (max speed) 62 65 -

4 6.5

3.5

5.5

3.5

5.5

1 4.5

1 5

1.5

2.5

3.5

2.5

3.5

Slow channel (max speed) 62 65

Fast channel (max speed) 66 67.4

Slow channel (max speed) 66 67.4

Fast channel (max speed) 64 66

Slow channel (max speed) 64 66

Fast channel (max speed) 66.5 68

Slow channel (max speed) 66.5 68

LSB bits dB

DS12737 Rev 6 245/340

307

Electrical characteristics STM32L552xx

Table 112. ADC accuracy - limited test conditions 2 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA

(ADC clock frequency ≤

58 MHz for LQFP144)

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -65

-74 -67

-79 -70

-79 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

246/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 113. ADC accuracy - limited test conditions 3 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

(ADC clock frequency ≤

58 MHz for LQFP144)

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) 1 3.5

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed) -

3.5

2.5

4.5

2.5

4.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10 10.4

Slow channel (max speed) 10 10.4

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 62 64 -

5.5

7.5

4.5

6.5

4.5

7.5

4.5

5.5

2 5

2.5

2 3.5

2.5

4.5

3.5

Slow channel (max speed) 62 64

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 63 65

Slow channel (max speed) 63 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

LSB bits dB

DS12737 Rev 6 247/340

307

Electrical characteristics STM32L552xx

Table 113. ADC accuracy - limited test conditions 3 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

(ADC clock frequency ≤

58 MHz for LQFP144)

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-69 -67

-71 -67

-72 -71

-72 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

248/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 114. ADC accuracy - limited test conditions 4 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

= VREF+ ≤

Voltage scaling Range 2

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) 1 1.5

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed)

Slow channel (max speed)

Fast channel (max speed) -

1.5

1.2

2.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10.2 10.5

Slow channel (max speed) 10.2 10.5

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 63 65 -

5 5.4

3.5

4.5

2 4

2 3.5

4 4.5

Slow channel (max speed) 63 65

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 64 65

Slow channel (max speed) 64 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

LSB bits dB

DS12737 Rev 6 249/340

307

Electrical characteristics STM32L552xx

Table 114. ADC accuracy - limited test conditions 4 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

≤

= VREF+ ≤

Voltage scaling Range 2

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-71 -69

-73 -72

-73 -72 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

250/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Figure 43. ADC accuracy characteristics

SSA

4095

4094

4093

E O

1 LSB

IDEAL

1 2 3 4 5 6 7

(2)

E D

(3)

(1)

E G

4093 4094 4095 4096

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

= total unajusted error : maximum deviation

between the actual and ideal transfer curves.

= offset error : maximum deviation

between the first actual transition and

the first ideal one.

= gain error : deviation between the last

ideal transition and the last actual one.

= differential linearity error : maximum

deviation between actual steps and the ideal ones.

= integral linearity error : maximum deviation

between any actual transition and the end point

correlation line.

DDA

MS19880V2

Figure 44. Typical connection diagram using the ADC

DDA

AIN

(1)

AINx

C parasitic

(2)

I lkg

(3)

Sample and hold ADC converter

ADC

12-bit converter

ADC

MS33900V5

1. Refer to Table 109: ADC characteristics for the values of R

AIN

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 102: I/O static characteristics

for the value of the pad capacitance). A high

C parasitic

value downgrades the conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 102: I/O static characteristics for the values of I

lkg

General PCB design guidelines

Power supply decoupling should be performed as shown in the corresponding power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DS12737 Rev 6 251/340

307

Electrical characteristics STM32L552xx

Symbol

DDA

REF+

Parameter

Table 115. DAC characteristics (1)

Analog supply voltage for

DAC ON

Conditions Min

DAC output buffer OFF, DAC_OUT pin not connected (internal connection only)

1.71

Other modes 1.80

Positive reference voltage

DAC output buffer OFF, DAC_OUT pin not connected (internal connection only)

Other modes

1.71

1.80

REF-

BON

BOFF

Negative reference voltage -

Resistive load

Output Impedance

Output impedance sample and hold mode, output buffer ON

Output impedance sample and hold mode, output buffer OFF

Capacitive load

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

= 2.7 V

= 2.0 V

= 2.7 V

= 2.0 V

DAC output buffer ON

Sample and hold mode

DAC_OUT t

SETTLING t

WAKEUP

(2)

PSRR

Voltage on DAC_OUT output

DAC output buffer ON

DAC output buffer OFF

±0.5 LSB

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±0.5LSB, ±1 LSB,

±2 LSB, ±4 LSB, ±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 k Ω

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until final value ±1 LSB

DDA

supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 k Ω , DC

0.2

9.6

Typ Max Unit

3.6

DDA

1.7

1.6

1.55

1.48

1.4

SSA

11.7

0.1

13.8

3.5

16.5

18.0

REF+

– 0.2

REF+

2.9

2.85

2.8

2.75

2 2.5

V k Ω k Ω k Ω k Ω pF

µF

µs

4.2

-80

7.5

-28

µs dB

252/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

W_to_W t

SAMP

I leak

CI int t

TRIM

V offset

DDA

(DAC)

Table 115. DAC characteristics (1) (continued)

Parameter Conditions Min

Minimal time between two consecutive writes into the

DAC_DORx register to guarantee a correct

DAC_OUT for a small variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] =

000 or 001

DAC_MCR:MODEx[2:0] =

010 or 011

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when

DACOUT reaches final value ±1LSB)

Output leakage current

CL ≤ 50 pF, RL ≥ 5 k Ω

CL ≤ 10 pF

DAC_OUT pin connected

DAC output buffer

ON, C

= 100 nF

DAC output buffer

OFF, C

= 100 nF

DAC_OUT pin not connected

(internal connection only)

DAC output buffer

OFF

Sample and hold mode,

DAC_OUT pin connected

Internal sample and hold capacitor

Middle code offset trim time DAC output buffer ON

Middle code offset for 1 trim code step

REF+

= 3.6 V

REF+

= 1.8 V

DAC output buffer ON

No load, middle code (0x800)

No load, worst code

(0xF1C)

DAC consumption from

DDA

DAC output buffer OFF

No load, middle code (0x800)

1.4

5.2

Sample and hold mode, C

100 nF

Typ

0.7

10.5

1500

750

315

450

Max

3.5

(3)

670

0.2

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

8.8

500

Unit

µs ms

µs nA pF

µs

µV

µA

DS12737 Rev 6 253/340

307

Electrical characteristics STM32L552xx

Symbol

DDV

(DAC)

Table 115. DAC characteristics (1) (continued)

Parameter Conditions Min

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

DAC consumption from

REF+

Sample and hold mode, buffer ON,

= 100 nF, worst case

Typ

185

340

155

Max

240

400

205

185 ₓ

Ton/(Ton

+Toff)

400 ₓ

Ton/(Ton

+Toff)

Unit

µA

Sample and hold mode, buffer OFF,

= 100 nF, worst case

155 ₓ

Ton/(Ton

+Toff)

205 ₓ

Ton/(Ton

+Toff)

3. Refer to Table 102: I/O static characteristics

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0351 reference manual for more details.

Figure 45. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

Buffer

(1)

LOAD

12-bit digital to analog converter

DACx_OUT

LOAD ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

254/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

DNL

INL

Parameter

Table 116. DAC accuracy ranges 0/1 (1)

Conditions

Differential non linearity

(2) monotonicity

Integral non linearity

(3)

DAC output buffer ON

DAC output buffer OFF

10 bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Min

Typ

guaranteed

Max

±2

±4

±12

Offset

Offset1

Offset error at code 0x800

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Offset error at code 0x001

(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer OFF

CL ≤ 50 pF, no RL

REF+

= 3.6 V

= 1.8 V

OffsetCal

Gain

TUE

TUECal

SNR

THD

Offset Error at code 0x800 after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

REF+

= 3.6 V

REF+

= 1.8 V

Gain error

Total unadjusted error

(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Total unadjusted error after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

1 kHz, BW 500 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

71.2

71.6

-78

-79

±25

±8

±5

±7

±0.5

±30

±12

±23

Unit

LSB

LSB dB dB

DS12737 Rev 6 255/340

307

Electrical characteristics STM32L552xx

Symbol Parameter

Table 116. DAC accuracy ranges 0/1 (1) (continued)

Conditions Min Typ Max Unit

SINAD

ENOB

Signal-to-noise and distortion ratio

Effective number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

70.4

11.4

11.5

dB bits

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

REF+

– 0.2) V when buffer is ON.

256/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol Parameter

Table 117. VREFBUF characteristics (1)

Conditions

REFBUF_

OUT

∆ V

REFOUT_

VD D

DDA

TRIM

CL esr load line_reg load_reg

Analog supply voltage

Voltage reference output

Normal mode

Degraded mode

(2)

Normal mode load

=100 µA/T=30°C

Degraded mode

= 0

= 1

= 0

= 1

= 0

= 1

= 0

= 1

Voltage reference output spread over the main supply range

Trim step resolution

Load capacitor

Normal mode

VRS=0

VRS=1

Equivalent

Serial Resistor of Cload

Static load current

Line regulation 2.8 V ≤ V

DDA

≤ 3.6 V

I load

= 500 µA

I load

= 4 mA

Load regulation

500 μ A ≤ I load

≤ 4 mA Normal mode

Min

2.4

2.8

1.65

2.044

2.496

DDA

-250 mV

DDA

-250 mV

0.5

±0.05

Typ

2.048

2.5

100

Coeff

PSRR t

START

Temperature coefficient

-40 °C < TJ < +125 °C

0 °C < TJ < +50 °C

Power supply rejection

Start-up time

100 kHz

CL = 0.5 µF (3)

CL = 1.1 µF

CL = 1.5 µF

2. Refer to Table 32: Embedded internal voltage reference

300

500

650

Max

2.052

2.504

DDA

3.6

2.4

2.8

±0.1

1.5

Unit

V mV mV

µF

Ω

2000

500 mA ppm/V

500 ppm/mA

T coeff_ vrefint +

T coeff_ vrefint

350

650

800 ppm/ °C dB

µs

DS12737 Rev 6 257/340

307

Electrical characteristics STM32L552xx

Symbol

INRUSH

Parameter

Table 117. VREFBUF characteristics (1) (continued)

Conditions Min Typ

Control of maximum DC current drive on VREFBUF_

OUT during start-up phase

(4)

Max

Unit mA

DDA

(VREF

BUF)

VREFBUF consumption from V

DDA

I load

= 0 µA

I load

= 500 µA

I load

= 4 mA -

µA

1. Guaranteed by design and characterization result, unless otherwise specified.

2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (V voltage).

DDA

- drop

3. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

4. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for V

= 0 and V

= 1.

DDA

voltage should be in

Figure 46. VREFBUF in case VRS = 0

2.06

2.055

2.05

2.045

2.04

2.035

2.03

2.025

-40 -20 0 20

Mean

Min

Max

80 100 120 °C

MSv62522V1

258/340 DS12737 Rev 6

STM32L552xx

Figure 47. VREFBUF in case VRS = 1

Electrical characteristics

2.51

2.505

2.5

2.495

2.49

2.485

2.48

2.475

-40 -20 0 20

Mean

Min

Max

80 100 120 °C

MSv62523V1

DS12737 Rev 6 259/340

307

Electrical characteristics STM32L552xx

Symbol Parameter

Table 118. COMP characteristics (1)

Conditions

DDA

Analog supply voltage

Comparator input voltage range

Scaler input voltage

(2)

Scaler offset voltage

BRG_EN=0 (bridge disable)

DDA

(SCALER)

Scaler static consumption from V

DDA t

START_SCALER

Scaler startup time t

START

V t

(3) offset

BRG_EN=1 (bridge enable)

Comparator startup time to reach propagation delay specification

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low-power mode

Propagation delay for

200 mV step with 100 mV overdrive

Comparator offset error

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

DDA

≥ 2.7 V

Medium mode

DDA

< 2.7 V

Ultra-low-power mode

Full common mode range

V hys

Comparator hysteresis

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis -

Min Typ Max Unit

1.62

3.6

V 0 V

DDA

0.55

0.65

0.8

100

REFINT

±5

200

±10

300

200

100

0.9

±5 ±20

µs ns

µs mV mV nA

µA

µs

260/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

DDA

(COMP)

Table 118. COMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

400 600

Ultra-lowpower mode

Comparator consumption from V

DDA

Medium mode

High-speed mode

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

1200

100 nA

µA

I bias

Comparator input bias current

1. Guaranteed by design, unless otherwise specified.

3. Guaranteed by characterization results.

4. Mostly I/O leakage when used in analog mode. Refer to I lkg

parameter in Table 102: I/O static characteristics .

(4) nA

Symbol

DDA

CMIR

OFFSET

∆ VI

OFFSET

Parameter

Table 119. OPAMP characteristics (1)

Conditions

Analog supply voltage

Common mode input range

Input offset voltage

Input offset voltage drift

25 °C, No Load on output.

All voltage/Temp.

Normal mode

Low-power mode

TRIMOFFSETP

TRIMLPOFFSETP

TRIMOFFSETN

TRIMLPOFFSETN

Offset trim step at low common input voltage

(0.1 ₓ V

DDA

)

Offset trim step at high common input voltage

(0.9 ₓ V

DDA

)

Min

1.8

Typ

Max

3.6

Unit

±5

±10

DDA

±1.5

±3

V mV

μ V/°C

0.8

1.1

1.35

DS12737 Rev 6 261/340

307

Electrical characteristics

Symbol

LOAD

LOAD_PGA

LOAD

LOAD_PGA

LOAD

CMRR

PSRR

GBW

(2)

OHSAT

OLSAT

φ m

STM32L552xx

Table 119. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Drive current

Drive current in

PGA mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

≥ 2 V

DDA

≥ 2 V

Resistive load

(connected to

VSSA or to

VDDA)

Normal mode

Low-power mode

DDA

< 2 V

Typ

Max

500

100

450

Unit

µA

Resistive load in PGA mode

(connected to

VSSA or to

DDA

)

Capacitive load

Power supply rejection ratio

Low saturation voltage

Phase margin

Normal mode

Low-power mode

Common mode rejection ratio

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Gain Bandwidth

Product

Low-power mode

Normal mode

Low-power mode

Slew rate

(from 10 and

90% of output voltage)

Open loop gain

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

High saturation voltage

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

< 2 V

4.5

40 -

-85

-90

LOAD

≤ 50 pf,

≥ 4 k Ω DC

LOAD

≤ 50 pf,

≥ 20 k Ω DC

DDA

≥ 2.4 V

(OPA_RANGE = 1)

DDA

< 2.4 V

(OPA_RANGE = 0)

≥ 2.4 V

< 2.4 V

I load

= max or R load min Input at V

DDA

100

DDA

load

= max or R load min Input at 0.

90 -

550 1600 2200

100 420 600

250

700

180

950

280

700

180

300

80 -

110

110 -

100

k Ω pF dB dB kHz

V/ms dB mV

262/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol

GM t

WAKEUP

I bias

PGA gain

Table 119. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Gain margin

Wake up time from OFF state.

OPAMP input bias current

Normal mode

Low-power mode

Normal mode

Low-power mode

LOAD

≤

≥ follower

50 pf,

4 k Ω configuration

LOAD

≤

≥ follower

50 pf,

20 k Ω configuration

General purpose input (all packages except UFBGA132)

Dedicated input

(UFBGA132)

≤ 75 °C

≤ 85 °C

≤ 105 °C

≤ 125 °C

Non inverting gain value

PGA Gain = 2

R network

R2/R1 internal resistance values in PGA mode

(4)

PGA Gain = 4

PGA Gain = 8

PGA Gain = 16

Delta R

Resistance variation (R1 or

R2)

PGA gain error PGA gain error

Gain = 2

-15

-1

PGA BW

PGA bandwidth for different non inverting gain

Gain = 4

Gain = 8

Gain = 16 -

Typ

GBW/

80/80

120/

140/

150/

Max

(3)

Unit dB

µs nA

k Ω /k Ω

MHz

DS12737 Rev 6 263/340

307

Electrical characteristics STM32L552xx

Symbol

Table 119. OPAMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit en

Voltage noise density

Normal mode

Low-power mode

Normal mode

Low-power mode at 1 kHz, Output loaded with 4 k Ω at 1 kHz, Output loaded with 20 k Ω at 10 kHz, Output loaded with 4 k Ω at 10 kHz, Output loaded with 20 k Ω

500

600

180

290 -

nV/ √

DDA

(OPAMP)

Table 102: I/O static characteristics .

OPAMP consumption from V

DDA

Normal mode

Low-power mode no Load, quiescent mode

120

260

100

1. Guaranteed by design, unless otherwise specified.

2. Guaranteed by characterization results.

3. Mostly I/O leakage, when used in analog mode. Refer to I lkg

parameter in

4. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between

OPAMP inverting input and ground. The PGA gain =1+R2/R1

µA

264/340 DS12737 Rev 6

STM32L552xx

Electrical characteristics

5.3.24 Temperature sensor characteristics

Symbol

(1)

Avg_Slope

(2)

30 t

START

(TS_BUF)

I t t

S_temp

Table 120. TS characteristics

Parameter

linearity with temperature

Average slope

Voltage at 30°C (±5 °C)

(3)

Sensor Buffer Start-up time in continuous mode

(4)

Start-up time when entering in continuous mode

Table 14: Temperature sensor calibration values

ADC sampling time when reading the temperature

Temperature sensor consumption from V

DD when selected by ADC

Min

2.3

0.742

Typ

±1

2.5

0.76

4.7

Max

±2

2.7

0.785

120

Unit

°C mV/°C

µs

µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at V

DDA

= 3.0 V ±10 mV. The V

ADC conversion result is stored in the TS_CAL1 byte. Refer to

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

5.3.25 V

BAT monitoring characteristics

Symbol

Table 121. V

BAT

monitoring characteristics

(1)

Parameter

(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q t

S_vbat

ADC sampling time when reading the VBAT

1. 1.55 V < V

BAT

< 3.6 V

2. Guaranteed by design.

Min

-10

Typ

Max

Unit k Ω

µs

Symbol

Table 122. V

BAT

charging characteristics

Parameter Conditions Min Typ

Battery charging resistor

VBRS = 0

VBRS = 1 -

1.5

Max

Unit k Ω

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307

Electrical characteristics STM32L552xx

5.3.26 Temperature and V

thresholds monitoring

Temperature and upper V

DD detailed in the table below:

voltage monitoring characteristics for tamper detection are

Symbol

Table 123. Temp and V

monitoring characteristics

Parameter

TEMP

VDD high low high

TPWM on

High temperature threshold monitoring

Low temperature threshold monitoring

High VDD supply monitoring

Minimum PWM ON time in case of periodic monitoring

1. Guaranteed by characterization results.

2. Guaranteed by design.

Conditions

Min

115

-45

3.6

Typ

123

(1)

-36 (1)

3.65

Unless otherwise specified, the parameters given in Table 124

400

(2)

Max

130

-30

3.7

Unit

°C

μ s

for DFSDM are derived from tests performed under the ambient temperature, f

APB2

frequency and V

conditions summarized in Table 27: General operating conditions

supply voltage

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 x V

Refer to Section 5.3.15: I/O port characteristics

for more details on the input/output alternate function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for

DFSDM).

266/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol Parameter

Table 124. DFSDM measured timing 1.71 to 3.6 V (1)

Conditions f

DFSDMCLK f f

CKIN

(1/T

DuCy

CKIN

CKOUT

)

CKOUT

DFSDM clock

1.71 < V

< 3.6 V

Input clock frequency

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

2.7 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0] ≠ 0),

1.71 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0] ≠ 0),

2.7 < V

< 3.6 V

Output clock frequency

Output clock frequency duty cycle

1.71 < V

< 3.6 V

T t t wh(CKIN) wl(CKIN) t t su h

Manchester

Input clock high and low time

Data input setup time

Data input hold time

Manchester data period

(recovered clock period)

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < V

< 3.6 V

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < V

< 3.6 V

Manchester mode

(SITP[1:0]=2,3),

Internal clock mode

(SPICKSEL[1:0] ≠ 0),

1.71 < V

< 3.6 V

1. Data based on characterization results, not tested in production.

Min

TCKIN/2-0.5

2.5

(CKOUTDIV

+1) *

DFSDMCLK

Typ

CKIN

Max f

SYSCLK

(2*CKOUTDI

V) *

DFSDMCLK

Unit

MHz

% ns

DS12737 Rev 6 267/340

307

Electrical characteristics

Figure 16: DFSDM timing diagram

63,&.6(/

6,73

63,&.6(/

6,73

5HFRYHUHGFORFN

5HFRYHUHGGDWD

STM32L552xx

06Y9

The parameters given in the following tables are guaranteed by design.

Refer to Section 5.3.15: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

268/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Symbol Parameter

Table 125. TIMx (1) characteristics

Conditions Min Max Unit t res(TIM)

Timer resolution time

TIMxCLK

= 110 MHz

8.33

TIMxCLK

55 t

TIMxCLK ns

MHz t f

EXT

Res

TIM

COUNTER

Timer external clock frequency on CH1 to

CH4

Timer resolution

16-bit counter clock period f

TIMxCLK

= 110 MHz

TIMx (except TIM2 and TIM5)

TIM2 and TIM5

TIMxCLK

= 110 MHz

0.009

MAX_COUNT

Maximum possible count with 32-bit counter f

TIMxCLK

= 110 MHz -

1. TIMx

, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

MHz

16 bit

65536

595.78

TIMxCLK

µs

65536 × 65536 t

TIMxCLK

39.045

Table 126. IWDG min/max timeout period at 32 kHz (LSI) (1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.125

0.250

0.500

1.0

2.0

4.0

8.0

512

1024

2048

4096

8192

16384

32768 ms

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 127. WWDG min/max timeout value at 110 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.037

0.074

0.149

0.298

2.368

4.736

9.536

19.072

Unit ms

DS12737 Rev 6 269/340

307

Electrical characteristics STM32L552xx

5.3.29 Communication interfaces characteristics

I

C interface characteristics

The I2C interface meets the timings requirements of the I 2 C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0351 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but is still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 5.3.15: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 128 below for the analog

filter characteristics:

Symbol

Table 128. I2C analog filter characteristics

(1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

270/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

SPI characteristics

Unless otherwise specified, the parameters given in

Table 129

for SPI are derived from tests performed under the ambient temperature, f

PCLKx frequency and supply voltage conditions summarized in

Refer to Section 5.3.15: I/O port characteristics

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol fSCK

1/tc(SCK) tsu(NSS) th(NSS) tw(SCKH) tw(SCKL)

Parameter

Table 129. SPI characteristics

(1)

Conditions

Master mode

2.7<VDD<3.6

Voltage ranges 0/1

Master mode

1.71<VDD<3.6

Voltage ranges 0/1

Master transmitter mode

1.71<VDD<3.6

Voltage ranges 0/1

SPI clock frequency

Slave receiver mode 1.71<VDD<3.6

Voltage ranges 0/1

Slave mode transmitter/full duplex

2.7<VDD<3.6

Voltage ranges 0/1

Slave mode transmitter/full duplex

1.71<VDD<3.6

Voltage ranges 0/1

Slave mode transmitter/full duplex

1.71<VDD<3.6

Voltage range 2

Slave mode transmitter/full duplex

1.08<VDD<1.32

(3)

NSS setup time Slave mode, SPI presc = 2

NSS hold time Slave mode, SPI presc = 2

SCK high and low time

Master mode

Min

4×Tpclk

2TTpclk

Typ

Max

(2)

Tpclk-1 Tpclk Tpclk+1

Unit

MHz

DS12737 Rev 6 271/340

307

Electrical characteristics STM32L552xx

Symbol Parameter

Table 129. SPI characteristics (1) (continued)

Conditions Min Typ Max (2) Unit tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO)

Data input setup time

Master mode

Slave mode

Data input hold time

Master mode

Slave mode

Data output access time

Slave mode

Data output disable time

Slave mode

1.5

7.5

16 tv(SO)

Data output valid time

Slave mode 2.7<VDD<3.6V

Voltage ranges 0/1

Slave mode 1.71<VDD<3.6V

Voltage ranges 0/1

Slave mode 1.71<VDD<3.6V

Voltage range 2

Slave mode

1.08<VDD<1.32V

Master mode

11.5

28.5

13.75

21.5

24.5

40.5

ns tv(MO) 0 1 th(SO)

Data output hold time

Slave mode

1.71<VDD<3.6V

Slave mode

Table 27: General operating conditions

1.08<VDD<1.32V

7.5

21 -

th(MO) Master mode 0 -

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

3. SPI mapped on GPIOG port which is supplied by VDDIO2 specified down to 1.08 V. SPI is tested in this voltage.

272/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Figure 48. SPI timing diagram - slave mode and CPHA = 0

NSS input t w(SCKH) t c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t su(NSS) t w(SCKL)

First bit OUT t h(SI) t v(SO) t su(SI)

MOSI input First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t h(NSS) t f(SCK)

Last bit OUT t dis(SO)

Last bit IN

MSv41658V1

Figure 49. SPI timing diagram - slave mode and CPHA = 1

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO)

First bit OUT t su(SI) t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

DS12737 Rev 6 273/340

307

Electrical characteristics

Figure 50. SPI timing diagram - master mode

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

STM32L552xx

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

SAI characteristics

Unless otherwise specified, the parameters given in

Table 130

for SAI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

supply voltage conditions summarized in

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 5.3.15: I/O port characteristics

for more details on the input/output alternate function characteristics (CK,SD,FS).

274/340 DS12737 Rev 6

STM32L552xx

Table 130. SAI characteristics (1)

Symbol Parameter Conditions f

MCK f

SAI Main clock output -

Master Transmitter

2.7<=VDD<=3.6

Voltage ranges 0/1

SAI clock frequency

(2)

Master Transmitter

1.71<=VDD<=3.6

Voltage ranges 0/1

Master Receiver

Voltage ranges 0/1

Slave Transmitter

2.7<=VDD<=3.6

Voltage ranges 0/1

Slave Transmitter

1.71<=VDD<=3.6

Voltage ranges 0/1

Slave Receiver

Voltage ranges 0/1

Voltage range 2

Electrical characteristics

23.5

MHz

DS12737 Rev 6 275/340

307

Electrical characteristics

Table 130. SAI characteristics (1) (continued)

Symbol Parameter Conditions t v(FS)

FS valid time

Master mode

2.7<=VDD<=3.6

Master mode

1.71<=VDD<=3.6

t t t t t t t t h(FS) su(FS) h(FS) su(SD_A_MR) su(SD_B_SR) h(SD_A_MR) h(SD_B_SR) v(SD_B_ST)

FS hold time

FS setup time

Master mode

Slave mode

FS hold time Slave mode

Master receiver

Data input setup time

Slave receiver

Master receiver

Data input hold time

Slave receiver

Slave transmitter (after enable edge)

2.7<=VDD<=3.6

Data output valid time

Slave transmitter (after enable edge)

1.71<=VDD<=3.6

Data output hold time Slave transmitter (after enable edge) t h(SD_B_ST) t v(SD_A_MT)

Data output valid time

Master transmitter (after enable edge)

2.7<=VDD<=3.6

Master transmitter (after enable edge)

1.71<=VDD<=3.6

t h(SD_A_MT)

Data output hold time Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. 2.APB clock frequency must be at least twice SAI clock frequency.

Figure 51. SAI master timing waveforms

1/fSCK

1.5

2.5

STM32L552xx

19 ns

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

MS32771V1

276/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Figure 52. SAI slave timing waveforms

1/fSCK

SAI_SCK_X tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n

Slot n+2 th(SD_ST)

SAI_SD_X

(receive)

MS32772V1

Symbol f

SCK

CAN (controller area network) interface

Refer to Section 5.3.15: I/O port characteristics

for more details on the input/output alternate function characteristics (FDCAN_TX and FDCAN_RX).

USART characteristics

Unless otherwise specified, the parameters given in

Table 131 for USART are derived from

tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 27: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C=30pF

• Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 5.3.15: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART).

Parameter

Table 131. USART characteristics

(1)

Conditions Min

SPI clock frequency

Master mode

1.71<VDD<3.6

Slave receiver mode

1.71<VDD<3.6

Slave mode transmitter

2.7<VDD<3.6

Slave mode transmitter

1.71<VDD<3.6

Typ

Max

Unit

MHz

DS12737 Rev 6 277/340

307

Electrical characteristics STM32L552xx

Symbol

Table 131. USART characteristics (1) (continued)

Parameter Conditions tsu(NSS) th(NSS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) tv(SO) tv(MO) th(SO) th(MO)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Slave mode

Master mode

Slave mode

Master mode

Slave mode

2.7<VDD<3.6V

Slave mode

1.71<VDD<3.6V

Master mode

Slave mode

1.71<VDD<3.6V

Master mode

1. Guaranteed by characterization results, not tested in production.

Min

Tker +4

Max

1/fsck/2-1 1/fsck/2 1/fsck/2+1

22.5

Typ

14.5

1.5

Unit

Figure 53. USART master mode timing diagram tc(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

TX t su(RX)

LSB t w(SCKH) t w(SCKL)

LSB t h(RX) t v(TX) t h(TX) t r(SCK) t f(SCK)

MSB

MSv64015V1

278/340 DS12737 Rev 6

STM32L552xx

NSS input

Electrical characteristics

Figure 54. USART slave mode timing diagram

SCK input

MISO

OUTPUT

MOSI

INPUT

(SI)

MSB OUT

MSB IN

(SI)

BIT6 OUT

BIT1 IN

LSB OUT

LSB IN

Unless otherwise specified, the parameters given in

Table 132 to

Table 145

for the FMC interface are derived from tests performed under the ambient temperature, f

HCLK and V

DD with the following configuration:

frequency

supply voltage conditions summarized in

Table 27: General operating conditions ,

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 x V

Refer to Section 5.3.15: I/O port characteristics for more details on the input/output

characteristics.

Asynchronous waveforms and timings

Figure 55

through Figure 58 represent asynchronous waveforms and

Table 132

through

Table 139

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• AddressSetupTime (ADDSET) = 0x1

• AddressHoldTime (ADDHLD) = 0x1

• DataHoldTime = 0x1

• ByteLaneSetup (NBLSET) = 0x1

• DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode,

DataSetupTime = 0x5)

• DataHoldTime (DATAHLD) = 0x1 (1THCLK for read operations and 2THCLK for write operations)

• BusTurnAroundDuration = 0x0

• Capacitive load CL = 30 pF

In all timing tables, the THCLK is the HCLK clock period.

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Electrical characteristics STM32L552xx

Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0] t v(A_NE) t v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32753V1

280/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Table 132. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)

Symbol Parameter Min Max Unit

3 THCLK+1 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(A_NOE) tsu(Data_NE) tsu(Data_NOE) th(Data_NOE) th(Data_NE) tv(NADV_NE) tw(NADV)

FMC_NE low time

FMC_NEx low to

FMC_NOE low

FMC_NOE low time

FMC_NOE high to

FMC_NE high hold time

FMC_NEx low to

FMC_A valid

Address hold time after

FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after

FMC_NOE high

Data hold time after

FMC_NEx high

FMC_NEx low to

FMC_NADV low

FMC_NADV low time

3THCLK– 0.5

2THCLK -0.5

THCLK

2THCLK-1

THCLK +14

1. Guaranteed by characterization results, not tested in production.

2THCLK + 1

THCLK+1.5

Table 133. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings

(1)

Symbol Parameter Min Max Unit tw(NE) FMC_NE low time tw(NOE) FMC_NWE low time tw(NWAIT) FMC_NWAIT low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high

8THCLK-0.5

8THCLK+1

7THCLK -0.5 7THCLK +0.5

THCLK -

5THCLK

+12.5

ns th(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results, not tested in production.

4THCLK+12 -

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Electrical characteristics STM32L552xx

Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data t v(NADV_NE) tw(NADV) t h(NE_NWE)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32754V1

Table 134. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

(1)

Symbol Parameter Min Max Unit

Ns tw(NE) tv(NWE_NE) tw(NWE)

FMC_NE low time

FMC_NEx low to FMC_NWE low

4THCLK-0.5

4THCLK+1

THCLK-0.5

THCLK +1

THCLK-0.5

THCLK+1 th(NE_NWE) tv(A_NE) th(A_NWE) tv(BL_NE)

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

2THCLK-0.5

2THCLK-1

th(BL_NWE) FMC_BL hold time after FMC_NWE high 2THCLK-0.5

tv(Data_NE) FMC_NEx low to Data valid -

THCLK

THCLK+3 th(Data_NWE) tv(NADV_NE)

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low tw(NADV) FMC_NADV low time

1. Guaranteed by characterization results, not tested in production.

2THCLK+1

THCLK+ 1.5

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STM32L552xx Electrical characteristics

Table 135. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings (1)

Symbol Parameter Min Max Unit tw(NE) tw(NWE)

FMC_NE low time

FMC_NWE low time

9THCLK-0.5

9THCLK+1.5

6THCLK-0.5

6THCLK+1 tsu(NWAIT_

NE)

FMC_NWAIT valid before FMC_NEx high 7THCLK+13 th(NE_NWA

IT)

FMC_NEx hold time after FMC_NWAIT invalid 5THCLK+13 -

1. Guaranteed by characterization results, not tested in production.

Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_ NE tv(NOE_NE) t h(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_ A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL th(Data_NE)

FMC_ AD[15:0] t v(NADV_NE) t v(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32755V1

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Electrical characteristics STM32L552xx

Table 136. Asynchronous multiplexed PSRAM/NOR read timings (1)

Symbol Parameter Min Max tw(NE) FMC_NE low time tv(NOE_NE) FMC_NEx low to FMC_NOE low tw(NOE) FMC_NOE low time

4THCLK-0.5

2THCLK -0.5

THCLK-0.5

4THCLK

2THCLK

THCLK+

0.5 th(NE_NOE)

FMC_NOE high to FMC_NE high hold time tv(A_NE) FMC_NEx low to FMC_A valid tv(NADV_NE) FMC_NEx low to FMC_NADV low tw(NADV) FMC_NADV low time

THCLK-1

0.5

THCLK

1.5

THCLK+

1.5

th(AD_NADV) th(A_NOE)

FMC_AD(address) valid hold time after FMC_NADV high)

Address hold time after

FMC_NOE high tsu(Data_NE) Data to FMC_NEx high setup time tsu(Data_NOE) th(Data_NE) th(Data_NOE)

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

THCLK-3

Address holded until next

1. Guaranteed by characterization results, not tested in production.

read operation

THCLK+14

Unit

Table 137. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings (1)

Symbol Parameter Min Max Unit tw(NE) tw(NOE)

FMC_NE low time

FMC_NOE low time

8THCLK-0.5

9THCLK+1

5THCLK -0.5 6THCLK +1

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+12 th(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid

4THCLK+11 -

1. Guaranteed by characterization results, not tested in production.

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STM32L552xx Electrical characteristics

Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE)

FMC_ NEx

FMC_NOE

FMC_NWE

FMC_ A[25:16]

FMC_ NBL[1:0]

FMC_ AD[15:0] t v(NADV_NE) tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) t v(A_NE)

Address th(A_NWE)

Address th(BL_NWE)

NBL tv(Data_NADV)

Data th(AD_NADV) tw(NADV) t h(NE_NWE) th(Data_NWE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32756V1

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Electrical characteristics STM32L552xx

Table 138. Asynchronous multiplexed PSRAM/NOR write timings (1)

Symbol Parameter Min Max tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time

FMC_AD(adress) valid hold time after

FMC_NADV high)

5THCLK-0.5 5THCLK+1

THCLK– 0.5 THCLK+ 1

2THCLK-0.5

2THCLK+0.

2THCLK-0.5

0 1

THCLK+0.5 THCLK+1.5

THCLK-3 th(A_NWE) Address hold time after FMC_NWE high th(BL_NWE) tv(BL_NE)

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid tv(Data_NADV) th(Data_NWE)

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

1. Guaranteed by characterization results, not tested in production.

Address holded until next write operation

2THCLK-0.5

2THCLK+0.5

THCLK

THCLK+2

Unit ns

Table 139. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings

(1)

Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 10THCLK-0.5 10THCLK+1 tw(NWE) FMC_NWE low time 7THCLK-0.5

7THCLK+0.5

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7THCLK+11.5

th(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid

5THCLK+12.5

1. Guaranteed by characterization results, not tested in production.

Synchronous waveforms and timings

Figure 59

through

Figure 62

represent synchronous waveforms and Table 140

through Table 143

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• BurstAccessMode = FMC_BurstAccessMode_Enable

• MemoryType = FMC_MemoryType_CRAM

• WriteBurst = FMC_WriteBurst_Enable

• CLKDivision = 1

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

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In all timing tables, the T

HCLK

is the HCLK clock period.

• Maximum FMC_CLK =55MHz for CLKDIV=0x1 and 42MHz CLKDIV=0x0 for

2.7V<VDD<3.6V

• Maximum FMC_CLK =55MHz for CLKDIV=0x1 and 26MHz CLKDIV=0x0 for

1.71V<VDD<1.9V with CL=20pF

Figure 59. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)

AD[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) th(CLKH-NWAITV)

MS32757V1

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Electrical characteristics STM32L552xx

Table 140. Synchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period R*THCLK-0.5

) td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R*THCLK/2+1

td(CLKL-NADVL) FMC_CLK low to FMC_NADV low td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid

(x=16…25)

R*THCLK/2 + 1 (2)

td(CLKL-NOEL) td(CLKH-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data before FMC_CLK high

FMC_A/D[15:0] valid data after FMC_CLK high

R*THCLK/2+1

4 tsu(NWAIT-

CLKH) th(CLKH-NWAIT)

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1.5

2.5

5.5

1. Guaranteed by characterization results, not tested in production.

2. Clock ratio R = (HCLK period /FMC_CLK period).

288/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Figure 60. Synchronous multiplexed PSRAM write timings

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Electrical characteristics STM32L552xx

Table 141. Synchronous multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period, VDD range= 2.7 to 3.6 V R*THCLK-0.5

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)

R*THCLK/2+1

td(CLKL-NADVL) FMC_CLK low to FMC_NADV low td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid

(x=16…25)

R*THCLK/2+1 (2)

td(CLKL-NWEL) td(CLKH-NWEH) td(CLKL-ADV) td(CLKL-ADIV) td(CLKL-DATA) td(CLKL-NBLL) td(CLKH-NBLH)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_CLK low to to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results, not tested in production.

2. Clock ratio R = (HCLK period /FMC_CLK period).

1.5

2.5

5.75

3.5

290/340 DS12737 Rev 6

STM32L552xx Electrical characteristics

Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL)

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

FMC_D[15:0] tsu(DV-CLKH) tsu(NWAITV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

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307

Electrical characteristics STM32L552xx

Table 142. Synchronous non-multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period R*THCLK-0.5

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) R*THCLK/2+1

td(CLKL-NADVL) FMC_CLK low to FMC_NADV low td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=0…25)

FMC_CLK high to FMC_Ax invalid

(x=0…25)

R*THCLK/2+0.5

R*THCLK/2+1

Unless otherwise specified, the parameters given in Table 146 ,

td(CLKL-NOEL) td(CLKH-NOEH) tsu(DV-CLKH) th(CLKH-DV)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high tsu(NWAIT-

CLKH)

FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high

1.5

1. Guaranteed by characterization results, not tested in production.

2. Clock ratio R = (HCLK period /FMC_CLK period).

2.5

5.5

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STM32L552xx Electrical characteristics

Figure 62. Synchronous non-multiplexed PSRAM write timings

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DS12737 Rev 6 293/340

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Electrical characteristics STM32L552xx

Table 143. Synchronous non-multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max Unit tw(CLK) td(CLKL-NExL) td(CLKH-NExH)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x=

0…2) td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=0…25)

FMC_CLK high to FMC_Ax invalid

(x=0…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high td(CLKL-NWEL) td(CLKH-NWEH) td(CLKL-Data)

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low td(CLKL-NBLL) td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results, not tested in production.

2. Clock ratio R = (HCLK period /FMC_CLK period).

R*THCLK-0.5

1.5

2.5

5.5

3.5

NAND controller waveforms and timings

Figure 63

through

Figure 66

represent synchronous waveforms, and

Table 144

and

Table 145

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• COM.FMC_SetupTime = 0x01

• COM.FMC_WaitSetupTime = 0x03

• COM.FMC_HoldSetupTime = 0x02

• COM.FMC_HiZSetupTime = 0x01

• ATT.FMC_SetupTime = 0x01

• ATT.FMC_WaitSetupTime = 0x03

• ATT.FMC_HoldSetupTime = 0x02

• ATT.FMC_HiZSetupTime = 0x01

• Bank = FMC_Bank_NAND

• MemoryDataWidth = FMC_MemoryDataWidth_16b

• ECC = FMC_ECC_Enable

• ECCPageSize = FMC_ECCPageSize_512Bytes

• TCLRSetupTime = 0

• TARSetupTime = 0

294/340 DS12737 Rev 6

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In all timing tables, the T

HCLK

is the HCLK clock period.

Figure 63. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE t d(NCE-NOE) t h(NOE-ALE)

FMC_NOE (NRE) t su(D-NOE) t h(NOE-D)

FMC_D[15:0]

MSv38003V1

FMC_NCEx

Figure 64. NAND controller waveforms for write access

ALE (FMC_A17)

CLE (FMC_A16) t d(NCE-NWE)

FMC_NWE t h(NWE-ALE)

FMC_NOE (NRE)

FMC_D[15:0] t v(NWE-D) t h(NWE-D)

MSv38004V1

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Electrical characteristics STM32L552xx

Figure 65. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) t d(NCE-NOE) t h(NOE-ALE)

FMC_NWE t w(NOE)

FMC_NOE t su(D-NOE) t h(NOE-D)

FMC_D[15:0]

MSv38005V1

Figure 66. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) t d(NCE-NWE)

FMC_NWE t w(NWE) t h(NOE-ALE)

FMC_NOE t d(D-NWE) t v(NWE-D) t h(NWE-D)

FMC_D[15:0]

MSv38006V1

Table 144. Switching characteristics for NAND Flash read cycles

(1)

Symbol Parameter Min Max

Tw(N0E)

Tsu(D-NOE)

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

Th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high

Td(ALE-NOE) FMC_ALE valid before FMC_NOE low

Th(NOE-ALE) FMC_NWE high to FMC_ALE invalid

4THCLK - 0.5 4THCLK+0.5

3THCLK-0.5

3THCLK-1

1. Guaranteed by characterization results, not tested in production.

Unit ns

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STM32L552xx Electrical characteristics

Table 145. Switching characteristics for NAND Flash write cycles (1)

Symbol Parameter Min Max

Tw(NWE)

Tv(NWE-D)

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

Th(NWE-D)

Td(D-NWE)

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

Td(ALE_NWE) FMC_ALE valid before FMC_NWE low

Th(NWE-ALE) FMC_NWE high to FMC_ALE invalid

1. Guaranteed by characterization results, not tested in production.

4THCLK - 0.5

4THCLK+0.5

0 -

2THCLK -

5THCLK - 1

3THCLK-0.5

3THCLK-1

Unit ns

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Electrical characteristics STM32L552xx

Symbol

F(CLK) tw(CKH) tw(CKL) tw(CKH) tw(CKL)

Table 147

and Table 148 for

OCTOSPI are derived from tests performed under the ambient temperature, f

AHB

frequency and V

supply voltage conditions summarized in

Table 27: General operating conditions ,

with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• For DTR(with DQS)/HyperBus the delay resister is set to DLYCFGR[3:0]=4

Refer to Section 5.3.15: I/O port characteristics

for more details on the input/output alternate function characteristics.

The following table summarizes the parameters measured in SDR mode.

Table 146. OCTOSPI (1) characteristics in SDR mode (2)

Parameter Conditions Min Typ Max Unit

OCTOSPI clock frequency

1.71<V

<3.6

Voltage ranges 0/1

20 pF

2.7<V

<3.6

Voltage ranges 0/1

20pF

1.71<V

<3.6

Voltage ranges 0/1

15pF

1.71<V

<3.6

Voltage range 2

CL=20pF

OCTOSPI clock high and low time

PRESCALER[7:0] = n = 0,1,3,5

MHz

OCTOSPI clock high and low time

Odd division

PRESCALER[7:0] = n = 2,4,6,8 ts(IN) th(IN)

Data input setup time

Data input hold time tv(OUT) Data output valid time th(OUT) Data output hold time

Voltage ranges 0/1

Voltage range 2

Voltage ranges 0/1

Voltage range 2

Voltage ranges 0/1

Voltage range 2

Voltage ranges 0/1

Voltage range 2

1. Values in the table applies to octal and quad SPI mode.

2. Guaranteed by characterization results.

t(CK)/2 - 0.5

t(CK)/2 -0.5

(n/2)×t(CK)/

(n+1)- 0.5

(n/2+1)×t(CK)/

(n+1) -0.5

1.5

5.25

-0.5

-0.75

0.5

t(CK)/2 t(CK)/2

(n/2)×t(CK)

/(n+1)

(n/2+1)× t(CK)/(n+1)

1.5

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The following table summarizes the parameters measured in DTR mode (no DQS).

Symbol

Table 147. OCTOSPI (1) characteristics in DTR mode (no DQS) (2)

Parameter Conditions Min Typ Max

F(CLK) tw(CKH) tw(CKL) tw(CKH) tw(CKL) tsr(IN), tsf(IN) thr(IN),thf(IN) tvr(OUT), tvf(OUT) thr(OUT), thf(OUT)

OCTOSPI clock frequency

1.71<V

<3.6

Voltage ranges 0/1

20 pF

2.7<V

<3.6

Voltage ranges 0/1

20 pF

1.71<V

<3.6

Voltage ranges 0/1

15 pF

1.71<V

<3.6

Voltage range 2

OCTOSPI clock high and low time

Odd division

Data input setup time

PRESCALER[7:0] = n = 0,1,3,5

PRESCALER[7:0] = n = 2,4,6,8

Voltage ranges 0/1

Voltage range 2

Data input hold time

Data output valid time

Voltage ranges 0/1

Voltage range 2

DHQC=0

Voltage ranges

0/1

DHQC=1

Pres=1,2

…

Data output hold time

Voltage range 2

DHQC=0

Voltage ranges

0/1

DHQC=1

Pres=1,2

…

Voltage range 2

DHQC=0 t(CK)/2

-0.5

t(CK)/2

-0.5

(n/2)×t(CK)/(n+1)-

0.5

(n/2+1)×t(CK)/

(n+1) -0.5

2.5

1.5

Tpclk/4

-0.25

1. Values in the table applies to octal and quad SPI mode.

2. Guaranteed by characterization results.

26 t(CK)/2+0.5

t(CK)/2+0.5

5.5

Tpclk

+0.5

(n/2)×t(CK)/(n+1)+

0.5

(n/2+1)×t(CK)/

(n+1)+0.5

7.25

Tpclk/4

Unit

MHz ns

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Electrical characteristics STM32L552xx

The following table summarizes the parameters measured in DTR mode (with DQS) /

HyperBus.

Table 148. OCTOSPI characteristics in DTR mode (with DQS) (1) /Octal and HyperBus

Symbol Parameter Conditions Min Typ Max Unit

F(CLK)

OCTOSPI clock frequency

1.71<V

<3.6

Voltage ranges 0/1

20 pF

2.7<V

<3.6

Voltage ranges 0/1

20 pF

1.71<V

<3.6

Voltage range 2

20 pF

(2)

MHz tw(CKH) tw(CKL) tw(CKH) tw(CKL)

OCTOSPI clock high and low time

Even division

t(CK)/2

-1 t(CK)/2

-0.5

(n/2)×t(CK)/(n+1)

-0.5

(n/2+1)×t(CK)/

(n+1) - 0.5

t(CK)/2

+0.5

t(CK)/2+0.5

(n/2)×t(CK)/(n+1)

+0.5

(n/2+1)*×(CK)/

(n+1)+0.5

ns tv(CK) th(CK)

V ODr( CK)

(3)

V ODf(

CK)

OCTOSPI clock high and low time

Odd division

Clock valid time

Clock hold time

CK,CK# crossing level on CK rising edge

CK,CK# crossing level on CK falling edge

=1v8

t(CK)/2

-0.5

832

840 -

t(CK) + 2

1050

1071 mV

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STM32L552xx Electrical characteristics

Table 148. OCTOSPI characteristics in DTR mode (with DQS) (1) /Octal and HyperBus (continued)

Symbol Parameter Conditions Min Typ Max Unit tw(CS) tv(DQ) tv(DS) th(DS) tv(RWDS)

Chip select high time

Data input valid time

Data strobe input valid time

Data strobe input hold time

Data strobe output valid time

3×t(CK)

3×t(CK) tsr(DQ),tsf(DQ)

Data input setup time

Voltage ranges 0/1

Voltage range 2 thr(DQ),thf(DQ)

Data input hold time

Voltage ranges 0/1

Voltage range 2 tvr(OUT), tvf(OUT) thr(OUT), thf(OUT)

Data output valid time

Data output hold time

DHQC=

Voltage ranges 0/1

Voltage range 2

DHQC=0

DHQC=

Pres=1,

2…

DHQC=

Voltage ranges 0/1

DHQC=

Pres=1,

2…

Voltage range 2

DHQC=0

-0.75

-2.25

3.75

4.75

3.25

Tpclk/4

-0.25

6.5

5.75

Tpclk/4

+0.75

t(CK)/2

-5.75

(4) t(CK)/2

-8