STMicroelectronics TDA7569BLV Datasheet

TDA7569BLV

'!0'03

Flexiwatt27 (Horiz.)

'!0'03

Flexiwatt27 (Vert.)

Features

 Multipower BCD technology

 MOSFET output power stage

 DMOS power output

 Class SB high efficiency

 High output power capability 4x28 W/4 Ω @

14.4 V, 1 kHz, 10% THD, 4 x 45 W max power

 Max power 4 x 72 W / 2 

 Full I

2

C bus driving:

– Standby

– Independent front/rear soft play/mute

– Selectable gain 26 dB /16 dB (for low noise line output function)

– High efficiency enable/disable

– I

2

C bus digital diagnostics (including DC bus AC load detection)

 Full fault protection

 DC offset detection

 Four independent short circuit protection

 Clipping detector pin with selectable threshold

(2 %/10 %)

 Standby/mute pin

 Linear thermal shutdown with multiple thermal warning

 ESD protection

4 x 50 W power amplifier with full I

2

C diagnostics,

high efficiency and low voltage operation

Datasheet

-

production data

'!0'03

Flexiwatt27 (SMD)

 Very robust against misconnections

 Improved SVR suppression during battery transients

 Capable to operate down to 6 V (e.g. “Startstop”)

'!0'03

PowerSO36

Description

The TDA7569BLV is the most advanced BCD technology quad bridge car radio amplifier of his family, including a wide range of innovative features.

The TDA7569BLV is equipped with the most complete diagnostics array that communicates the status of each speaker through the I 2 C bus.

The dissipated output power under average listening condition is significantly reduced when compared to the conventional class AB solutions, thanks to the patented solution. Moreover it has been designed to be very robust against several kinds of misconnections.

It is moreover compliant to the most recent OEM specifications for low voltage operation (so called

'start-stop' battery profile during engine stop and re-start), helping car manufacturers to reduce the overall emissions and thus contributing to environment protection.

Figure 1. Device summary

Order code Package Packing

TDA7569BLVSM

TDA7569BLVSMTR

Flexiwatt27

(SMD)

Tube

Tape and reel

TDA7569BLV

TDA7569BLVH

Flexiwatt27

(vertical)

Flexiwatt27

(horizontal)

Tube

Tube

TDA7569BLVPD

TDA7569BLVPDTR

PowerSO36

Tube

Tape and reel

September 2014

This is information on a product in full production.

DocID023498 Rev 9

1/41

www.st.com

1

2

3

Contents

Contents

4

5

6

7

8

9

TDA7569BLV

Block diagram and application circuits . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

Permanent diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3

Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4

AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1

Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1

Fast muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Battery transitions management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1

Low voltage operation (“start stop”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2

Advanced battery management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Application suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1

Inputs impedance matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.2

High efficiency introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

I

2

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.1

I 2

C programming/reading sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.2

Address selection and I

2

C disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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12

TDA7569BLV Contents

9.3

I

2

C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.3.1

9.3.2

9.3.3

9.3.4

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

13

Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DocID023498 Rev 9

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3

List of tables

List of tables

TDA7569BLV

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Pin list description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Double fault table for turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DB1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 9.

DB2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10.

DB3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11.

DB4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12.

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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DocID023498 Rev 9

TDA7569BLV

List of figures

List of figures

Figure 1.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4.

Application circuit (TDA7569BLVPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5.

Pin connection diagram of the Flexiwatt27 (top of view). . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6.

Pin connection diagram of the PowerSO36 slug up (top of view). . . . . . . . . . . . . . . . . . . . . 8

Figure 7.

Quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

Output power vs. supply voltage (4 Ω ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9.

Distortion vs. output power (4 Ω , STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.

Distortion vs. output power (4 Ω ,

Figure 11.

Distortion vs. output power (2 Ω ,

Figure 12.

Distortion vs. output power (2 Ω ,

Figure 13.

Distortion vs. frequency (2 Ω ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 14.

Distortion vs. output power V s

= 6 V (4 Ω , STD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15.

Distortion vs. frequency (4 Ω ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 16.

Crosstalk vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 17.

Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18.

Power dissipation vs. average output power (audio program simulation, 2 Ω ). . . . . . . . . . 15

Figure 19.

Power dissipation vs. average output power (audio program simulation, 4 Ω ). . . . . . . . . . 16

Figure 20.

Total power dissipation and efficiency vs. output power (4 Ω , HI-EFF, Sine). . . . . . . . . . . 16

Figure 21.

Total power dissipation and efficiency vs. output power (4 Ω , STD, Sine) . . . . . . . . . . . . . 16

Figure 22.

ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 16

Figure 23.

Turn-on diagnostic: working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 24.

SVR and output behavior (Case 1: without turn-on diagnostic) . . . . . . . . . . . . . . . . . . . . . 17

Figure 25.

SVR and output pin behavior (Case 2: with turn-on diagnostic) . . . . . . . . . . . . . . . . . . . . . 18

Figure 26.

Short circuit detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 27.

Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 28.

Load detection threshold - low gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 29.

Restart timing without diagnostic enable (permanent) - Each 1 mS time, a sampling of the fault is done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 30.

Restart timing with diagnostic enable (permanent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 31.

Current detection high: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . 21

Figure 32.

Current detection low: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . . 21

Figure 33.

Thermal foldback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 34.

Worst case battery cranking curve sample 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 35.

Worst case battery cranking curve sample 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 36.

Upwards fast battery transitions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 37.

Inputs impedance matching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 38.

High efficiency - basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 39.

Data validity on the I

2

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 40.

Timing diagram on the I

2

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 41.

Acknowledge on the I

2

C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 42.

Flexiwatt27 (horizontal) mechanical data and package dimensions. . . . . . . . . . . . . . . . . . 36

Figure 43.

Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 37

Figure 44.

Flexiwatt27 (SMD) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . 38

Figure 45.

PowerSO36 (slug up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 39

DocID023498 Rev 9

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5

Block diagram and application circuits

1 Block diagram and application circuits

TDA7569BLV

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6/41

DocID023498 Rev 9

TDA7569BLV Block diagram and application circuits

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DocID023498 Rev 9

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40

Pin description TDA7569BLV

8/41

For channel name reference: CH1 = LF, CH2 = LR, CH3 = RF and CH4 = RR.

Figure 5. Pin connection diagram of the Flexiwatt27 (top of view)

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DocID023498 Rev 9

TDA7569BLV Pin description

Table 1. Pin list description

Pin #

(PowerSo36)

Pin #

(Flexiwatt27)

29

30

31

32

25

26

27

28

33

34

35

36

21

22

23

24

17

18

19

20

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

14

15

16

17

12

-

13

-

18

19

-

20

9

10

-

11

8

7

6

-

-

5

3

-

27

4

2

21

26

24

-

-

1

22

23

25

Pin name Function

TAB

OUT4+

CK

-

I

Channel 4, + output

2

C bus clock/HE selector

PWGND4 Channel 4 output power ground

NC

VCC4

DATA

OUT4-

ADSEL

OUT2-

STBY

VCC2

I

Not connected

Supply voltage pin4

2

C bus data pin/gain selector

Channel 4, - output

Address selector pin/ I

Channel 2, - output

Standby pin

Supply voltage pin2

2

C bus disable (legacy select)

PWGND2 Channel 2 output power ground

NC

NC

CD

OUT2+

Not connected

Not connected

Clip detector output pin

Channel 2, + output

NC

OUT1-

Not connected

Channel 1, - output

VCC1 Supply voltage pin1

PWGND1 Channel 1 output power ground

OUT1+

NC

SVR

IN1

Channel 1, + output

Not connected

SVR pin

Input pin, channel 1

NC

IN2

NC

SGND

Not connected

Input pin, channel 2

Not connected

Signal ground pin

IN4

IN3

Input pin, channel 4

Input pin, channel 3

AC GND AC ground

OUT3+ Channel 3, + output

PWGND3 Channel 3 output power ground

VCC3 Supply voltage pin3

OUT3Channel 3, - output

DocID023498 Rev 9

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40

Electrical specifications TDA7569BLV

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

Symbol

V op

V

S

V peak

GNDmax

DC supply voltage

Peak supply voltage (for t max

= 50 ms)

Ground pins voltage

Parameter

Operating supply voltage

(1)

Value

18

28

50

-0.3 to 0.3

Unit

V

V

V

V

V

CK,

V

DATA

V

V cd stby

CK and DATA pin voltage

Clip detector voltage

STBY pin voltage

-0.3 to 6

-0.3 to V op

-0.3 to V op

8

I

O

P tot

T stg

, T j

T amb

Output peak current (not repetitive t max

= 100ms)

Output peak current (repetitive f > 10 kHz)

Power dissipation T case

= 70°C

Storage and junction temperature

Operative temperature range

(2)

(3)

6

85

-55 to 150

-40 to 105

1. For R

L

= 2 Ω the output current limit is reached for V might be triggered.

OP

> 16 V; at this supply level internal protections

2. This is maximum theoretical value; for power dissipation in real application conditions, please refer to

curves reported in Section 3.4: Electrical characteristics curves

.

3. A suitable dissipation system should be used to keep Tj inside the specified limits.

V

V

V

A

W

°C

°C

Symbol

R th j-case

Table 3. Thermal data

Parameter

Thermal resistance junction-to-case Max.

PowerSO Flexiwatt Unit

1 1 °C/W

Symbol

Refer to the test circuit, V

S otherwise specified.

= 14.4 V; R

L

= 4 Ω ; f = 1 kHz; G

V

= 26 dB; T amb

= 25 °C; unless

Tested at T amb

= 25 °C and T hot

= 105 °C; functionality guaranteed for T j

= -40 °C to 150 °C.

Parameter

General characteristics

Table 4. Electrical characteristics

Test condition Min.

Typ.

Max.

Unit

V

S

Supply voltage range

R

L

= 4 ohm

R

L

= 2 ohm

6

6 -

18

16

(1)

V

10/41

DocID023498 Rev 9

TDA7569BLV Electrical specifications

Symbol

I

R

V

V

V

I d

IN

AM

OS dth

SB

SVR

Parameter

Total quiescent drain current

Input impedance

Min. supply mute threshold

Offset voltage

Dump threshold

Standby current

Table 4. Electrical characteristics (continued)

Supply voltage rejection

Test condition

-

-

IB1(D7) = 1;

Signal attenuation -6 dB

IB1(D7) = 0 (default);

(2)

Signal attenuation -6 dB

Mute & play

-

V standby

= 0 f = 100 Hz to 10 kHz; V r

R g

= 600 Ω

= 1 Vpk;

T

T

ON

OFF

TH

WARN1

TH

WARN2

TH

WARN3

Turn on timing (Mute play transition)

Turn off timing (Play mute transition)

Average junction temperature for

TH warning 1

Average junction temperature for

TH warning 2

Average junction temperature for

TH warning 3

Audio performances

D2/D1 (IB1) 0 to 1

D2/D1 (IB1) 1 to 0

DB1 (D7) = 1

DB4 (D7) = 1

DB4 (D6) = 1

Min.

-

45

7

5

-80

18.5

-

60

-

-

-

-

-

P

O

THD

C

T

G

V1

 G

V1

G

V2

 G

V2

E

IN1

E

IN2

Output power

Total harmonic distortion

Cross talk

Voltage gain 1

Voltage gain match 1

Voltage gain 2

Voltage gain match 2

Output noise voltage 1

Output noise voltage 2

Max. power

(3)

V s

= 14.4 V, R

L

= 4 Ω

THD = 10 %, R

L

THD = 1 %, R

L

= 4 Ω

= 4 Ω

R

L

R

L

R

L

= 2 Ω ; THD 10 %

= 2 Ω ; THD 1 %

= 2 Ω ; Max. power

(3)

V s

= 14.4 V

Max power@ V s

= 6 V, R

L

= 4 Ω

P

O

= 1 W to 10 W; STD mode

HE MODE; P

O

HE MODE; P

O

= 1.5 W

= 8 W

P

O

= 1-10 W, f = 10 kHz;

STD mode

-

G

V

V

O

= 16 dB; STD mode

= 0.1 to 5 V RMS

f = 1 kHz to 10 kHz, R g

= 600 Ω

-

-

R g

= 600 Ω 20 Hz to 22 kHz

R g

= 600 Ω ; GV = 16d B

20 Hz to 22 kHz

-

25

20

40

32

60

-

-

-

-

-

50

25

-1

15

-1

-

25

25

160

145

125

Typ.

165

60

-

-

-

19.5

1

70

-

-

50

50

-

W

W

W

W

W

W

W

%

%

%

%

% dB dB dB dB dB

μ V

μ V

45

28

22

50

40

75

6

0.015

0.05

0.1

0.15

0.02

65

26

-

16

-

45

20

-

-

-

0.05

-

27

1

17

1

60

30

-

0.1

0.1

0.5

0.5

5.8

80

20.5

5

-

Max.

Unit

250

70 mA k Ω

8

V mV

V

μ A dB ms ms

°C

DocID023498 Rev 9

11/41

40

Electrical specifications TDA7569BLV

Symbol

Δ V

OITU

Parameter

BW Power bandwidth

CMRR Input CMRR

Table 4. Electrical characteristics (continued)

ITU Pop filter output voltage

Test condition

-

V cm

= 1 Vpk-pk, R g

= 0 Ω

Standby to Mute and

Mute to Standby transition

T amb

= 25 °C,

ITU-R 2K, C svr

= 10 μ F

V s

= 14.4 V

Mute to Play transition

T amb

= 25 °C,

ITU-R 2K, V s

= 14.4 V

(4)

Play to Mute transition

T amb

= 25 °C,

ITU-R 2K, V s

= 14.4 V

(5)

Min.

100

-

-7.5

-7.5

-7.5

Clip detector

CD

LK

CD

SAT

Clip det. high leakage current

Clip det sat. voltage

CD

THD

Clip det THD level

CD off / V

CD

= 6 V

CD on; I

CD

= 1 mA

D0 (IB1) = 1

D0 (IB1) = 0

5

1

-

-

Control pin characteristics

V

SBY

V

MU

V

OP

Standby/mute pin for standby

Standby/mute pin for mute

-

-

I

MU

A

SB

A

M

Standby/mute pin for operating -

Standby/mute pin current

Standby attenuation

Mute attenuation -

-

V st-by/mute

= 4.5 V

V st-by/mute

< 1.2 V

Turn on diagnostics 1 (Power amplifier mode)

Pgnd

Pvs

Short to GND det. (below this limit, the Output is considered in short circuit to GND)

Short to Vs det. (above this limit, the output is considered in short circuit to Vs)

Pnop

Normal operation thresholds.

(Within these limits, the output is considered without faults).

Shorted load det.

Lsc

Lop Open load det.

Lnop Normal load det.

Power amplifier in standby

Power amplifier in standby

Turn on diagnostics 2 (Line driver mode)

Pgnd

Short to GND det. (below this limit, the output is considered in short circuit to GND)

Power amplifier in standby

-

85

1.5

-

-

Vs -1.2

1.8

0

2.9

4.5

-

-

90

80

Typ.

-

70

-

-

-

-

-

-

-

0

-

10

2

-

-

-

-

1

-

-

0

110

100

Max.

Unit

-

kHz dB

+7.5

+7.5

+7.5

1.2

3.5

18

5

5

-

-

5

300

15

3

1.2

-

0.5

-

45

V

V

V

μ A

μ A dB dB

Ω

Ω

Ω

μ A mV

%

%

Vs -1.8

V

1.2

mV mV mV

V

V

V

12/41

DocID023498 Rev 9

TDA7569BLV Electrical specifications

Symbol

Table 4. Electrical characteristics (continued)

Parameter

Pvs

Short to Vs det. (above this limit, the output is considered in short circuit to Vs)

Pnop

Normal operation thresholds.

(Within these limits, the output is considered without faults).

Shorted load det.

Lsc

Lop Open load det.

Lnop Normal load det.

-

-

-

-

-

Test condition Min.

Vs -1.2

1.8

-

330

7

Typ.

-

-

Max.

Unit

V

Vs -1.8

V

-

-

1.5

-

180

Permanent diagnostics 2 (Power amplifier mode or line driver mode)

Pgnd

Pvs

Pnop

L

V

SC

O

Short to GND det. (below this limit, the Output is considered in short circuit to GND)

Short to Vs det. (above this limit, the output is considered in short circuit to Vs)

Normal operation thresholds.

(Within these limits, the output is considered without faults).

Power amplifier in mute or play, one or more short circuits protection activated

Shorted load det.

Offset detection

Power amplifier mode

Line driver mode

Power amplifier in play,

AC input signals = 0

I

NLH

I

OLH

I

NLL

I

OLL

Normal load current detection

Open load current detection

Normal load current detection

Open load current detection

I

2

C bus interface

V

V

O

O

< (V

< (V

S

S

-5)pk, IB2 (D7) = 0

-5)pk, IB2 (D7) = 1

-

Vs -1.2

1.8

-

-

±1.5

500

-

250

-

±2

-

-

-

-

-

-

-

-

1.2

Vs -1.8

0.5

1.5

±2.5

-

-

250

-

125

V

V

V

Ω

Ω

V

S

CL

V

IL

V

IH

Clock frequency

Input low voltage

Input high voltage

-

-

-

-

-

2.3

1. When V

S

> 16 V the output current limit is reached (triggering embedded internal protections).

2. In legacy mode only low threshold option is available.

-

-

-

400

1.5

-

3. Saturated square wave output.

4. Voltage ramp on STBY pin: from 3.3 V to 4.2 V in t ≥ 40 ms.

In case of I 2 C mode command IB1(D1) = 1 (Mute → Unmute rear channels) and/or IB1(D2) = 1 (Mute channels) must be transmitted before to start the voltage ramp on STBY pin.

→ Unmute front

5. Voltage ramp on STBY pin: from 4.05 V to 3.55 V in t ≥ 40 ms.

In case of I

2

C mode command IB1(D1) = 0 Unmute → Mute rear channels) and/or IB1(D2) = 0 (Unmute channels) must be NOT transmitted before to start the voltage ramp on STBY pin.

→ Mute front kHz

V

V mA mA mA mA

Ω

Ω

Ω

DocID023498 Rev 9

13/41

40

Electrical specifications TDA7569BLV

3.4 Electrical characteristics curves

Figure 7. Quiescent current vs. supply voltage Figure 8. Output power vs. supply voltage (4 Ω )

0O 7

2, 7

FK(Z 0OMAX

4($

4($

!'V

'!0'03

Figure 9. Distortion vs. output power (4 Ω , STD)

4($

34!.$!2$-/$%

6S6

7

6S6

'!0'03

Figure 10. Distortion vs. output power

(4 HI-EFF)

4($

()%&&-/$%

6S6

2,

FK(Z

FK(Z

FK(Z FK(Z

0O 7

'!0'03

Figure 11. Distortion vs. output power

(2 STD)

4($

34!.$!2$-/$%

6S6

2, 7

FK(Z

FK(Z

0O 7

Figure 12.

Distortion vs. output power

(

2 Ω ,

HI-EFF)

4($

'!0'03

()%&&-/$%

6S6

2, 7

FK(Z

FK(Z

0O 7

14/41

0O 7

'!0'03

DocID023498 Rev 9

'!0'03

TDA7569BLV Electrical specifications

Figure 13. Distortion vs. frequency (2 Ω )

4($

34!.$!2$-/$%

6S6

2, 7

0O7

Figure 14. Distortion vs. output power V s

(4 Ω , STD)

= 6 V

4($

34!.$!2$-/$%

6S6

2, 7

FK(Z

FK(Z

F(Z

'!0'03

Figure 15. Distortion vs. frequency (4 Ω )

4($

34!.$!2$-/$%

6S6

2, 7

0O 7

0O 7

Figure 16. Crosstalk vs. frequency

'!0'03

#2/334! ,+D"

34! .$!2$-/$%

2, 7

0O 7

2G 7

F(Z

'!0'03

Figure 17. Supply voltage rejection vs. frequency

362D"

F(Z

'!0'03

Figure 18. Power dissipation vs. average output power (audio program simulation, 2 Ω )

0TOT7

34$(%-/$%

2G 7

6RIPPLE6RMS

6S6

2,X/HM

'!533)!../)3%

34$-/$%

#,)0

34!24

()%&&-/$%

0O7

F(Z '!0'03 '!0'03

DocID023498 Rev 9

15/41

40

Electrical specifications TDA7569BLV

Figure 19. Power dissipation vs. average output power (audio program simulation, 4 Ω )

0TOT7

Figure 20. Total power dissipation and efficiency vs. output power (4 Ω , HI-EFF, Sine)

0TOT7 H

34$-/$%

6S6

2,X/HM

'!533)!../)3%

6S

2, 7

F+(Z

()%&& MODE

H

#,)0

34! 24

()%&&-/$%

0TOT

0O7

'!0'03

Figure 21. Total power dissipation and efficiency vs. output power (4 Ω , STD, Sine)

0TOT7 H

0O7

'!0'03

Figure 22. ITU R-ARM frequency response, weighting filter for transient pop

/UTPUTATTENUATIOND"

H

6S6

2, 7

FK(Z

0TOT

0O7 (Z

'!0'03 '!0'03

16/41

DocID023498 Rev 9

TDA7569BLV

4

Diagnostics functional description

Diagnostics functional description

It is strongly recommended to activate this function at turn on (standby out) through I

2

C bus request. Detectable output faults are:

 SHORT TO GND

 SHORT TO Vs

 SHORT ACROSS THE SPEAKER

 OPEN SPEAKER

To verify if any of the above misconnections are in place, a subsonic (inaudible) current

pulse ( Figure

) is internally generated, sent through the speaker(s) and sunk back.The

Turn On diagnostic status is internally stored until a successive diagnostic pulse is requested (after a I

2

C reading).

If the "standby out" and "diag. enable" commands are both given through a single programming step, the pulse takes place first (during the pulse the power stage stays 'off', showing high impedance at the outputs).

Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The previous Turn On state is kept until a short appears at the outputs.

Figure 23. Turn-on diagnostic: working principle

9Va9

,VRXUFH

,P$

,VRXUFH

,VLQN

,VLQN aPV

0HDVXUHWLPH

WPV

'!0'03

Figure

and

25 show SVR and OUTPUT waveforms at the turn-on (stand-by out) with and

without turn-on diagnostic.

Figure 24. SVR and output behavior (Case 1: without turn-on diagnostic)

6SVR

/UT

0ERMANENTDIAGNOSTIC

ACQUISITIONTIMEMS4YP

)#"$!4!

"IASPOWER AMPT URNON

$IAGNOSTIC %NABLE

0ERMANENT

&!5,4

EVENT

0ERMANENT$IAGNOSTICSDATAOUPUT

PERMITTEDTIME

2EAD$ATA

DocID023498 Rev 9

T

'!0'03

17/41

40

Diagnostics functional description TDA7569BLV

Figure 25. SVR and output pin behavior (Case 2: with turn-on diagnostic)

6SVR

/UT 4U RNOND IAGNOSTIC

ACQU ISI TIONTIM EMS 4YP

0ERMANENTDIAGN OST IC

ACQUI SIT IONTIMEMS 4YP

18/41

T

$IAGNOST IC%NABLE

4UR NON

4URNON $IAGN OST ICS DATAOUT PU T

PER MITT EDTI ME

$IAGN OST IC% NABLE

0ERMAN ENT

&!5,4

EVENT

"IASPOWERAMP TURNON

PERMITTE DT IME

2EAD$ATA

0ERMANENT$IAGNO ST ICS DAT AOUT PUT

PERMITTE DTIME

)#"$!4!

'!0'03

The information related to the outputs status is read and memorized at the end of the current pulse plateau. The acquisition time is 100 ms (typ.). No audible noise is generated in the process. As for SHORT TO GND / Vs the fault-detection thresholds remain unchanged from 26 dB to 16 dB gain setting. They are as follows:

Figure 26. Short circuit detection thresholds

3#TO'.$ X .ORMAL/PERATION X 3#TO6S

6 6 6 6

3

6 6

3

6 6

3

'!0'03

Concerning SHORT ACROSS THE SPEAKER / OPEN SPEAKER, the threshold varies from 26 dB to 16 dB gain setting, since different loads are expected (either normal speaker's impedance or high impedance). The values in case of 26 dB gain are as follows:

Figure 27. Load detection thresholds - high gain setting

3#ACROSS,OAD X .ORMAL/PERATION X /PEN,OAD

6 7 7 7 7 )NFINITE

'!0'03

If the Line-Driver mode (Gv= 16 dB and Line Driver Mode diagnostic = 1) is selected, the same thresholds will change as follows:

Figure 28. Load detection threshold - low gain setting

3#ACROSS,OAD X .ORMAL/PERATION X /PEN,OAD

7 7 7 7 7 INFINITE

'!0'03

DocID023498 Rev 9

TDA7569BLV Diagnostics functional description

Detectable conventional faults are:

– Short to GND

– Short to Vs

– Short across the speaker

The following additional feature is provided:

– Output offset detection

The TDA7569BLV has 2 operating status:

1.

RESTART mode. The diagnostic is not enabled. Each audio channel operates independently of each other. If any of the a.m. faults occurs, only the channel(s) interested is shut down. A check of the output status is made every 1 ms (

Figure

Restart takes place when the overload is removed.

29 ).

mode. is via C bus and it self activates if an output overload

(such as to cause the intervention of the short-circuit protection) occurs to the speakers outputs. Once activated, the diagnostics procedure develops as follows (

Figure 30

):

– To avoid momentary re-circulation spikes from giving erroneous diagnostics, a check of the output status is made after 1ms: if normal situation (no overloads) is detected, the diagnostic is not performed and the channel returns active.

– Instead, if an overload is detected during the check after 1 ms, then a diagnostic cycle having a duration of about 100 ms is started.

– After a diagnostic cycle, the audio channel interested by the fault is switched to

RESTART mode. The relevant data are stored inside the device and can be read by the microprocessor. When one cycle has terminated, the next one is activated by an I 2 C reading. This is to ensure continuous diagnostics throughout the carradio operating time.

– To check the status of the device a sampling system is needed. The timing is chosen at microprocessor level (over half a second is recommended).

Figure 29. Restart timing without diagnostic enable (permanent) - Each 1 mS time, a sampling of the fault is done

/UT

M3

M3

M3 M3 M3

/VERCUR RENTAND SHOR T

CIRCUIT PROTECT IONI NTERVENT ION

IESHOR TCIRCUI TT O'.$

T

3HOR TCIRCUI TREMOVED

Figure 30. Restart timing with diagnostic enable (permanent)

M3 M3 M3 M3

/VERCURRENT ANDSHORT

CIRCUITPROTECTI ON IN TERVENTI ON

IES HORTC IRCUI TTO'.$

DocID023498 Rev 9

'!0'03

T

3HO RTCIRCUIT REMOVED

'!0'03

19/41

40

Diagnostics functional description

4.3 Output DC offset detection

TDA7569BLV

Any DC output offset exceeding ±2 V is signalled out. This inconvenient might occur as a consequence of initially defective or aged and worn-out input capacitors feeding a DC component to the inputs, so putting the speakers at risk of overheating.

This diagnostic has to be performed with low-level output AC signal (or Vin = 0).

The test is run with selectable time duration by microprocessor (from a "start" to a "stop" command):

– START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1

– STOP = Actual reading operation

Excess offset it is signalled out if persistent for all the assigned testing time. This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process.

20/41

This function is design to detect accidental disconnection of tweeters in 2-way speaker and, more in general, presence of capacitive (AC) coupled loads.

This diagnostic is based on the notion that the overall speaker's impedance (woofer + parallel tweeter) will tend to increase towards high frequencies if the tweeter gets disconnected, because the remaining speaker (woofer) would be out of its operating range

(high impedance). The diagnostic decision is made according to peak output current thresholds, and it is enabled by setting (IB2-D2) = 1. Two different detection levels are available:

– High current threshold IB2 (D7) = 0

Iout > 500 mApk = normal status

Iout < 250 mApk = open tweeter

– Low current threshold IB2 (D7) = 1

Iout > 250 mApk = normal status

Iout < 125 mApk = open tweeter

To correctly implement this feature, it is necessary to briefly provide a signal tone (with the amplifier in "play") whose frequency and magnitude are such as to determine an output current higher than 500 mApk with IB2(D7) = 0 (higher than 250 mApk with IB2(D7) = 1) in normal conditions and lower than 250 mApk with IB2(D7) = 0 (lower than 125 mApk with

IB2(D7)=1) should the parallel tweeter be missing.

The test has to last for a minimum number of 3 sine cycles starting from the activation of the

AC diagnostic function IB2<D2>) up to the I 2 C reading of the results (measuring period). To confirm presence of tweeter, it is necessary to find at least 3 current pulses over the above threadless over all the measuring period, else an "open tweeter" message will be issued.

The frequency / magnitude setting of the test tone depends on the impedance characteristics of each specific speaker being used, with or without the tweeter connected

(to be calculated case by case). High-frequency tones (> 10 kHz) or even ultrasonic signals are recommended for their negligible acoustic impact and also to maximize the impedance module's ratio between with tweeter-on and tweeter-off.

Figure and 32 shows the load impedance as a function of the peak output voltage and

the relevant diagnostic fields.

DocID023498 Rev 9

TDA7569BLV Diagnostics functional description

It is recommended to keep output voltage always below 8 V (high threshold) or 4 V (low threshold) to avoid the circuit to saturate (causing wrong detection cases).

This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process.

Figure 31. Current detection high: load impedance |Z| vs. output peak voltage

,O AD\Z\/HM

,OWCURRENTDETECTIONAREA

/PENLOAD

$OFTHE$"XBYRES

)OUTPEAK M!

)OUTPEAK M!

)"$

(IGHCURRENTDETECTIONAREA

.ORMALLOAD

$OFTHE$"XBYTES

6OUT 0EAK

Figure 32. Current detection low: load impedance |Z| vs. output peak voltage

,OAD\Z\/HM

,OWCURRENTDETECTIONAREA

/PENLOAD

$OFTHE$"XBYRES

)OUTPEAK M!

)OUTPEAK M!

'!0'03

)"$

(IGHCURRENTDETECTIONAREA

.ORMALLOAD

$OFTHE$"XBYTES

6OUT0EAK

'!0'03

DocID023498 Rev 9

21/41

40

Multiple faults TDA7569BLV

When more misconnections are applied simultaneously at the audio outputs, it is guaranteed that at least one of them is initially read out. The others are notified after successive cycles of I 2 C reading and faults removal, provided that the diagnostic is enabled.

This is true for both kinds of diagnostic (Turn on and Permanent).

The table below shows all the couples of double-fault possible. It should be taken into account that a short circuit with the 4 ohm speaker unconnected is considered as double fault.

S. GND

S. Vs

S. Across L.

Open L.

Table 5. Double fault table for turn-on diagnostic

S. GND

S. GND

/

/

/

S. Vs

S. Vs + S. GND

S. Vs

/

/

S. Across L.

S. GND

S. Vs

S. Across L.

/

Open L.

S. GND

S. Vs

N.A.

Open L. (*)

In Permanent Diagnostic the table is the same, with only a difference concerning Open

Load (*) , which is not among the recognizable faults. Should an Open Load be present during the device's normal working, it would be detected at a subsequent Turn on

Diagnostic cycle (i.e. at the successive Car Radio Turn on).

All the results coming from I

2

C bus, by read operations, are the consequence of measurements inside a defined period of time. If the fault is stable throughout the whole period, it will be sent out.

To guarantee always resident functions, every kind of diagnostic cycles (Turn on,

Permanent, Offset) will be reactivate after any I

2

C reading operation. So, when the micro reads the I

2

C, a new cycle will be able to start, but the read data will come from the previous diag. cycle (i.e. The device is in Turn On state, with a short to Gnd, then the short is removed and micro reads I

2

C. The short to Gnd is still present in bytes, because it is the result of the previous cycle. If another I

2

C reading operation occurs, the bytes do not show the short). In general to observe a change in Diagnostic bytes, two I

2

C reading operations are necessary.

22/41

DocID023498 Rev 9

TDA7569BLV Thermal protection

Thermal protection is implemented through thermal foldback ( Figure

).

Thermal foldback begins limiting the audio input to the amplifier stage as the junction temperatures rise above the normal operating range. This effectively limits the output power capability of the device thus reducing the temperature to acceptable levels without totally interrupting the operation of the device.

The output power will decrease to the point at which thermal equilibrium is reached.

Thermal equilibrium will be reached when the reduction in output power reduces the dissipated power such that the die temperature falls below the thermal foldback threshold.

Should the device cool, the audio level will increase until a new thermal equilibrium is reached or the amplifier reaches full power. Thermal foldback will reduce the audio output level in a linear manner.

Three thermal warning are available through the I 2 C bus data. After thermal shut down threshold is reached, the CD could toggle (as shown in

Figure ) or stay low, depending on

signal level.

Figure 33. Thermal foldback diagram

6OUT

4( 7! 2.

/.

/.

/.

6OUT

4(3(

34!24

4(3(

%.$

4J #

4

3$ 3$

WITHSAMEINPUT

SIGNAL

4J #

#$OUT

4J #

'!0'03

The muting time can be shortened to less than 1.5ms by setting (IB2) D5 = 1. This option can be useful in transient battery situations (i.e. during car engine cranking) to quickly turnoff the amplifier to avoid any audible effects caused by noise/transients being injected by preamp stages. The bit must be set back to “0” shortly after the mute transition.

DocID023498 Rev 9

23/41

40

Battery transitions management

7 Battery transitions management

7.1

TDA7569BLV

Low voltage operation (“start stop”)

The most recent OEM specifications are requiring automatic stop of car engine at traffic light, in order to reduce emissions of polluting substances. The TDA7569BLV, thanks to its innovating design, allows a continuous operation when battery falls down to 6/7V during such conditions, without producing pop noise. The maximum system power will be reduced accordingly.

Worst case battery cranking curves are shown below, indicating the shape and durations of allowed battery transitions.

Figure 34. Worst case battery cranking curve sample 1

9

EDWW

9

9

9

9

9

W W

W

W

W

W W

WV

V1 = 12 V; V2 = 6 V; V3 = 7 V; V4 = 8 V t1 = 2 ms; t2 = 50 ms; t3 = 5 ms; t4 = 300 ms; t5 =10 ms; t6 = 1 s; t7 = 2 ms

Figure 35. Worst case battery cranking curve sample 2

9

EDWW

9

9

*$3*36

24/41

9

9

W

W

W

W

V1 = 12 V; V2 = 6 V; V3 = 7 V t1 = 2 ms; t2 = 5 ms; t3 = 15 ms; t5 = 1 s; t6 = 50 ms

W

DocID023498 Rev 9

WV

*$3*36

TDA7569BLV

7.2

Battery transitions management

Advanced battery management

In addition to compatibility with low V batt

, the TDA7569BLV is able to sustain upwards fast battery transitions (like the one showed in

Figure ) without causing unwanted audible

effect, thanks to the innovative circuit topology.

Figure 36. Upwards fast battery transitions diagram

'!0'03

DocID023498 Rev 9

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40

Application suggestion TDA7569BLV

8.1 Inputs impedance matching

Figure 37. Inputs impedance matching circuit

)N

!#'.$

K 7

6

).

0LAY

6

!#'.$

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0-

K 7

362CHARGE

CIRCUIT

362

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The above is a simplified input stage where it is visible that the AC-GND impedance (60 k Ω ) is the same as the input one.

During battery variations the SVR voltage is moved and V

IN the two R-C networks.

and V

AC-GND

tracks it through

Any differences of this two time constants can produce a differential input voltage, which can produce a noise.

Consequently, any additional passive components at the inputs (other than the input capacitors) such as series resistance or R dividers must be compensated for at AC-GND level by connecting the same equivalent resistance in series to C

AC-GND

.

A good 1:1 matching (Z

AC-GND

= Z

IN

) is therefore recommended to minimize pop. This rule applies to both "4-CH operation" and "2-CH operation", as any unused input has be ACgrounded (through the same C

IN

value).

26/41

DocID023498 Rev 9

TDA7569BLV

8.2

Application suggestion

High efficiency introduction

Thanks to its operating principle, the TDA7569BLV obtains a substantial reduction of power dissipation from traditional class-AB amplifiers without being affected by the massive radiation effects and complex circuitry normally associated with class-D solutions.

The high efficiency operating principle is based on the use of bridge structures which are connected by means of a power switch. In particular, as shown in

Figure 2 , Ch1 is linked to

Ch2, while Ch3 to Ch4. The switch, controlled by a logic circuit which senses the input signals, is closed at low volumes (output power steadily lower than 2.5 W) and the system acts like a "single bridge" with double load. In this case, the total power dissipation is a quarter of a double bridge.

Due to its structure, the highest efficiency level can be reached when symmetrical loads are applied on channels sharing the same switch.

Figure 38. High efficiency - basic structure

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)?& )?2

&RONT

2EAR

6IN& 6IN2 n

&20

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&CHANNEL

(IGH

IMPEDANCE

2CHANNEL

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When the power demand increases to more than 2.5 W, the system behavior is switched back to a standard double bridge in order to guarantee the maximum output power, while in the 6 V start-stop devices the High Efficiency mode is automatically disabled at low V

CC

(7.3

V ± 0.3 V). No need to re-program it when V

CC

goes back to normal levels.

The results show (

Figure ) that in the range 2-4 W (@ V

CC

= 14.4 V, R

L

= 4 Ω ), with the

High Efficiency mode, the dissipated power gets up to 50 % less than the value obtained with the standard mode.

DocID023498 Rev 9

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40

I 2 C bus

9 I

2

C bus

TDA7569BLV

9.1 I

2

C programming/reading sequences

A correct turn on/off sequence with respect to the diagnostic timings and producing no audible noises could be as follows (after battery connection):

– TURN-ON: PIN2 > 4.5V --- 10 ms --- (STAND-BY OUT + DIAG ENABLE) --- 1 s

(min) --- MUTING OUT

– TURN-OFF: MUTING IN - wait for 50 ms - HW ST-BY IN (ST-BY pin ≤ 1.2 V)

– Car Radio Installation: PIN2 > 4.5 V --- 10ms DIAG ENABLE (write) --- 200 ms ---

I

2

C read (repeat until All faults disappear).

– OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30 ms - I

2

C reading (repeat I

2

C reading until high-offset message disappears).

9.2 Address selection and I

2

C disable

When the ADSEL/I2CDIS pin is left open the I

2

C bus is disabled and the device can be controlled by the STBY/MUTE pin.

In this status (no - I

2

C bus) the CK pin enables the HIGH-EFFICIENCY MODE (0 = STD

MODE; 1 = HE MODE) and the DATA pin sets the gain (0 = 26 dB; 1 = 16 dB).

When the ADSEL/I2CDIS pin is connected to GND the I

2

C bus is active with address

<1101100-x>.

To select the other I

2

C address a resistor must be connected to ADSEL/I2CDIS pin as following:

0 < R < 1 k Ω : I 2 C bus active with address <1101100x>

11 k Ω < R < 21 k Ω : I 2 C bus active with address <1101101x>

40 k Ω < R < 70 k Ω : I 2 C bus active with address <1101110x>

R > 120 k Ω : Legacy mode

(x: read/write bit sector)

9.3 I

2

C bus interface

Data transmission from microprocessor to the TDA7569BLV and viceversa takes place through the 2 wires I

2

C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).

As shown by

Figure , the data on the SDA line must be stable during the high period of

the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

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DocID023498 Rev 9

TDA7569BLV

9.3.2

I 2 C bus

Start and stop conditions

As shown by

Figure a start condition is a HIGH to LOW transition of the SDA line while

SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is

HIGH.

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

9.3.4 Acknowledge

The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see

Figure ). The receiver** has to pull-down (LOW) the SDA line during the

acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.

* Transmitter

– master ( μ P) when it writes an address to the TDA7569BLV

– slave (TDA7569BLV) when the μ P reads a data byte from TDA7569BLV

** Receiver

– slave (TDA7569BLV) when the μ P writes an address to the TDA7569BLV

– master ( μ P) when it reads a data byte from TDA7569BLV

Figure 39. Data validity on the I

2

C bus

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Figure 40. Timing diagram on the I 2 C bus

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Figure 41. Acknowledge on the I 2 C bus

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DocID023498 Rev 9

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40

Software specifications TDA7569BLV

All the functions of the TDA7569BLV are activated by I 2 C interface.

The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from μ P to

TDA7569BLV) or read instruction (from TDA7569BLV to μ P).

Chip address

D7

1 1 0 1 1 (*) (*)

X = 0 Write to device

X = 1 Read from device

If R/W = 0, the  P sends 2 "Instruction Bytes": IB1 and IB2.

(*) address selector bit, please refer to address selection description on Chapter

.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Table 6. IB1

Instruction decoding bit

Supply transition mute threshold high (D7 = 1)

Supply transition mute threshold low (D7 = 0)

Diagnostic enable (D6 = 1)

Diagnostic defeat (D6 = 0)

Offset Detection enable (D5 = 1)

Offset Detection defeat (D5 = 0)

Front Channel (CH1, CH3)

Gain = 26 dB (D4 = 0)

Gain = 16 dB (D4 = 1)

Rear Channel (CH2, CH4)

Gain = 26 dB (D3 = 0)

Gain = 16 dB (D3 = 1)

Mute front channels (D2 = 0)

Unmute front channels (D2 = 1)

Mute rear channels (D1 = 0)

Unmute rear channels (D1 = 1)

CD 2% (D0 = 0)

CD 10% (D0 = 1)

D0

X D8 Hex

30/41

DocID023498 Rev 9

TDA7569BLV Software specifications

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Table 7. IB2

Instruction decoding bit

Current detection threshold

High th (D7 = 0)

Low th (D7 =1)

0

Normal muting time (D5 = 0)

Fast muting time (D5 = 1)

Stand-by on - Amplifier not working - (D4 = 0)

Stand-by off - Amplifier working - (D4 = 1)

Power amplifier mode diagnostic (D3 = 0)

Line driver mode diagnostic (D3 = 1)

Current Detection Diagnostic Enabled (D2 =1)

Current Detection Diagnostic Defeat (D2 =0)

Right Channel Power amplifier working in standard mode (D1 = 0)

Power amplifier working in high efficiency mode (D1 = 1)

Left Channel Power amplifier working in standard mode (D0 = 0)

Power amplifier working in high efficiency mode (D0 = 1)

If R/W = 1, the TDA7569BLV sends 4 "Diagnostics Bytes" to  P: DB1, DB2, DB3 and DB4.

Bit

Table 8. DB1

Instruction decoding bit

D7 Thermal warning 1 active (D7 = 1), T j

=160 °C

D6

Diag. cycle not activated or not terminated (D6 = 0)

Diag. cycle terminated (D6 = 1)

D5

D4

Channel LF (CH1)

Current detection IB2 (D7) = 0

Output peak current < 250 mA - Open load (D5 = 1)

Output peak current > 500 mA - Normal load (D5 = 0)

Channel LF (CH1)

Turn-on diagnostic (D4 = 0)

Permanent diagnostic (D4 = 1)

D3

D2

Channel LF (CH1)

Normal load (D3 = 0)

Short load (D3 = 1)

Channel LF (CH1)

Turn-on diag.: No open load (D2 = 0)

Open load detection (D2 = 1)

Offset diag.: No output offset (D2 = 0)

Output offset detection (D2 = 1)

-

-

-

-

-

Channel LF (CH1)

Current detection IB2 (D7) = 1

Output peak current < 125 mA - Open load (D5 = 1)

Output peak current > 250 mA - Normal load (D5 = 0)

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40

Software specifications TDA7569BLV

Bit

Table 8. DB1 (continued)

Instruction decoding bit

D1

D0

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Channel LF (CH1)

No short to Vcc (D1 = 0)

Short to Vcc (D1 = 1)

Channel LF (CH1)

No short to GND (D1 = 0)

Short to GND (D1 = 1)

-

-

Table 9. DB2

Instruction decoding bit

Offset detection not activated (D7 = 0)

Offset detection activated (D7 = 1)

-

X

-

-

Channel LR (CH2)

Current detection IB2 (D7) = 0

Output peak current < 250 mA - Open load (D5 = 1)

Output peak current > 500 mA - Normal load (D5 = 0)

Channel LR (CH2)

Current detection IB2 (D7) = 1

Output peak current < 125 mA - Open load (D5 = 1)

Output peak current > 250 mA - Normal load (D5 = 0)

Channel LR (CH2)

Turn-on diagnostic (D4 = 0)

Permanent diagnostic (D4 = 1)

Channel LR (CH2)

Normal load (D3 = 0)

Short load (D3 = 1)

Channel LR (CH2)

Turn-on diag.: No open load (D2 = 0)

Open load detection (D2 = 1)

Permanent diag.: No output offset (D2 = 0)

Output offset detection (D2 = 1)

Channel LR (CH2)

No short to Vcc (D1 = 0)

Short to Vcc (D1 = 1)

Channel LR (CH2)

No short to GND (D1 = 0)

Short to GND (D1 = 1)

-

-

-

-

32/41

DocID023498 Rev 9

TDA7569BLV Software specifications

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Table 10. DB3

Instruction decoding bit

Standby status (= IB2 - D4)

Diagnostic status (= IB1 - D6) -

-

Channel RF (CH3)

Current detection IB2 (D7) = 0

Output peak current < 250 mA - Open load (D5 = 1)

Output peak current > 500 mA - Normal load (D5 = 0)

Channel RF (CH3)

Current detection IB2 (D7) = 1

Output peak current < 125 mA - Open load (D5 = 1)

Output peak current > 250 mA - Normal load (D5 = 0)

Channel RF (CH3)

Turn-on diagnostic (D4 = 0)

Permanent diagnostic (D4 = 1)

Channel RF (CH3)

Normal load (D3 = 0)

Short load (D3 = 1)

Channel RF (CH3)

Turn-on diag.: No open load (D2 = 0)

Open load detection (D2 = 1)

Permanent diag.: No output offset (D2 = 0)

Output offset detection (D2 = 1)

Channel RF (CH3)

No short to Vcc (D1 = 0)

Short to Vcc (D1 = 1)

Channel RF (CH3)

No short to GND (D1 = 0)

Short to GND (D1 = 1)

-

-

-

-

-

DocID023498 Rev 9

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40

Software specifications TDA7569BLV

Bit

Table 11. DB4

Instruction decoding bit

D7 Thermal warning 2 active (D7 = 1), T j

= 145 °C

D6 Thermal warning 3 active (D6 = 1) T j

= 125 °C

D5

Channel RR (CH4)

Current detection IB2 (D7) = 0

Output peak current < 250 mA - Open load (D5 = 1)

Output peak current > 500 mA - Normal load (D5 = 0)

D4

D3

Channel RR (CH4)

Turn-on diagnostic (D4 = 0)

Permanent diagnostic (D4 = 1)

Channel R (CH4)

R Normal load (D3 = 0)

Short load (D3 = 1)

D2

D1

D0

Channel RR (CH4)

Turn-on diag.: No open load (D2 = 0)

Open load detection (D2 = 1)

Permanent diag.: No output offset (D2 = 0)

Output offset detection (D2 = 1)

Channel RR (CH4)

No short to Vcc (D1 = 0)

Short to Vcc (D1 = 1)

Channel RR (CH4)

No short to GND (D1 = 0)

Short to GND (D1 = 1)

-

-

-

-

-

-

-

Channel RR (CH4)

Current detection IB2 (D7) = 1

Output peak current < 125 mA - Open load (D5 = 1)

Output peak current > 250 mA - Normal load (D5 = 0)

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TDA7569BLV

11 Examples of bytes sequence

Examples of bytes sequence

1 - Turn-On diagnostic - Write operation

Start Address byte with D0 = 0 ACK

2 - Turn-On diagnostic - Read operation

IB1 with D6 = 1 ACK IB2 ACK STOP

Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP

The delay from 1 to 2 can be selected by software, starting from 1ms

3a - Turn-On of the power amplifier with 26dB gain, mute on, diagnostic defeat, CD = 2%

.

Start Address byte with D0 = 0 ACK IB1

X0000000

ACK IB2

XXX1XX11

ACK STOP

3b - Turn-Off of the power amplifier

Start Address byte with D0 = 0 ACK IB1

X0XXXXXX

ACK IB2

XXX0XXXX

ACK STOP

4 - Offset detection procedure enable

Start Address byte with D0 = 0 ACK IB1

XX1XX11X

ACK IB2

XXX1XXXX

ACK STOP

5 - Offset detection procedure stop and reading operation (the results are valid only for the offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4)

.

Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP

 The purpose of this test is to check if a D.C. offset (2 V typ.) is present on the outputs, produced by input capacitor with anomalous leakage current or humidity between pins.

 The delay from 4 to 5 can be selected by software, starting from 1ms

DocID023498 Rev 9

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40

Package information TDA7569BLV

36/41

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

Figure 42. Flexiwatt27 (horizontal) mechanical data and package dimensions

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DocID023498 Rev 9

TDA7569BLV Package information

Figure 43. Flexiwatt27 (vertical) mechanical data and package dimensions

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DocID023498 Rev 9

37/41

40

Package information TDA7569BLV

Figure 44. Flexiwatt27 (SMD) mechanical data and package dimensions

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38/41

DocID023498 Rev 9

TDA7569BLV Package information

Figure 45. PowerSO36 (slug up) mechanical data and package dimensions

$)-

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39/41

40

Revision history TDA7569BLV

Date

30-Jul-2012

13-Sep-2012

11-Dec-2012

25-Jan-2013

18-Sep-2013

10-Feb-2014

10-Mar-2014

28-Apr-2014

18-Sep-2014

Table 12. Document revision history

Revision Changes

1

2

3

4

5

6

7

8

Initial release.

Document status promoted from preliminary data to datasheet.

Updated

Table 4: Electrical characteristics on page .

Updated

Section Package .

Corrected typeset error of the "a1" dimension on the Figure

PowerSO36 (slug up) mechanical data and package dimensions on page

.

Updated

Section 8.2: High efficiency introduction on page .

Updated Disclaimer.

Updated Table Electrical and

Section programming/reading sequences .

Updated

Figure 3 and

4 note (*);

Table Electrical characteristics (

Δ V

OITU parameter on page 12).

Updated

Section 9.2: Address selection and I

2

C disable on

9

Updated

Section I

2

C programming/reading sequences on page .

40/41

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TDA7569BLV

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2014 STMicroelectronics – All rights reserved

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