STMicroelectronics STGAP1BS Datasheet

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STGAP1BS

Product label

STGAP1BS

Datasheet

Automotive galvanically isolated advanced single gate driver

Features

• AEC-Q100 qualified

• High voltage rail up to 1500 V

• Driver current capability: 5 A sink/source current at 25 °C

• dV/dt transient immunity ±50 V/ns in full temperature range

• Overall input/output propagation delay: 100 ns

• Separate sink and source for easy gate driving configuration

• Negative gate drive ability

• Active Miller clamp

• Desaturation detection

• SENSE input

• V

CE

active clamping

• Output 2-level turn-off

• Diagnostic status output

• UVLO and OVLO functions

• Programmable input deglitch filter

• Asynchronous stop command

• Programmable deadtime, with violation error

• SPI interface for parameters programming

• Temperature warning and shutdown protection

• Self-diagnostic routines for protection features

• Full effective fault protection

Applications

• 600/1200 V inverters

• Inverters for EV/HEV

• EV charging stations

• Industrial drives

• UPS equipment

• DC/DC converters

• Solar inverters

Description

The STGAP1BS is a galvanically isolated single gate driver for N-channel MOSFETs and IGBTs with advanced protection, configuration and diagnostic features. The architecture of the STGAP1BS isolates the channel from the control and the low voltage interface circuitry through true galvanic isolation.

The gate driver is characterized by 5 A capability, making the device also suitable for high power inverter applications such as motor drivers in hybrid and electric vehicles and in industrial drives. The output driver section provides a rail-to-rail output with the possibility to use a negative gate driver supply.

DS11974 - Rev 4 - October 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

STGAP1BS

The input to output propagation delay remains below 100 ns, providing high PWM control accuracy.

Protection functions such as the Miller clamp, desaturation detection, dedicated sense pin for overcurrent detection, output 2-level turn-off, V

CE

overvoltage protection, UVLO and OVLO are included to easily design high reliability systems.

Open drain diagnostic outputs are included and detailed device conditions can be monitored through the SPI.

Each function parameter can be programmed via the SPI, making the device very flexible and allowing it to fit in a wide range of applications.

Separate sink and source outputs provide high flexibility and bill of material reduction for external components.

DS11974 - Rev 4 page 2/59

1

Block diagram

Figure 1. Block diagram

STGAP1BS

Block diagram

DS11974 - Rev 4 page 3/59

2

STGAP1BS

Pin connection

Pin connection

Figure 2. Pin connection (top view)

GND

SDO

SDI

CS

CK

VREG

VDD

IN-/DIAG2

IN+

DIAG1

SD

GND

5

6

7

8

1

2

3

4

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

ASC

VL

CLAMP

GOFF

GON

VCECLAMP

DESAT

VH

SENSE

VREGISO

VL

GNDISO

Table 1. Pin description

22

14, 23

13

16

24

19

18

15

17

20

21

5

3

2

10

1, 12

4

7

6

11

9

8

Pin no.

Pin name Type Function

VCECLAMP

DESAT

VREGISO

VH

GON

GOFF

CLAMP

VL

GNDISO

SENSE

ASC

VDD

VREG

SD

Power supply

Power supply

Logic input

Power supply for low voltage section and internal 3.3 V regulator

Internal 3.3 V regulator output and supply pin

Shutdown input (active low)

IN+ Logic input Gate command input

IN-/DIAG2 Logic input/open drain output Gate command input /open drain diagnostic output

DIAG1

GND

CS

CK

SDI

SDO

Open drain output

Ground

Logic input

Logic input

Logic input

Logic output

Open drain diagnostic output

Low voltage section ground

SPI chip select (active low)

SPI clock

SPI serial data input

Analog input

Analog input/output

Power supply

Power supply

Analog output

Analog output

Analog output

Power supply

Ground

Analog input

Analog input

SPI serial data output

V

CE

active clamping protection

Desaturation protection

Internal regulator output pin for decoupling

Positive power supply for high voltage section

Gate source output

Gate sink output

Miller clamp

Negative power supply or ground for high voltage section

High voltage section (isolated) ground

Sense input for overcurrent protection

Asynchronous stop command

DS11974 - Rev 4 page 4/59

STGAP1BS

Electrical data

3

Electrical data

3.1

3.2

Absolute maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Test condition Min.

dV

ISO

/dt Common mode transient immunity

VDD Low voltage section power supply voltage vs. GND -

V

CM

= 1500 V

VREG

Low voltage section internal regulator voltage vs.

GND

-

-

-0.30

-0.30

VREGISO

High voltage section internal regulator voltage vs.

GNDISO

V

LOGIC

Logic pins voltage vs. GND

VHL

VH

VL

Differential supply voltage (VH vs. VL)

Positive supply voltage (VH vs. GNDISO)

V

OUT

Negative supply voltage (VL vs. GNDISO)

Voltage on gate driver outputs (GON, GOFF, CLAMP vs. VL)

-

-

-

-

-

-

V

DESAT

V

SENSE

Voltage on DESAT pin vs. GNDISO

Voltage on SENSE pin vs. GNDISO

V

CECLAMP

Voltage on VCECLAMP pin vs. VL

V

ASC

I

DIAGx

Voltage on ASC pin vs. GNDISO

Open drain DC output current

V

DIAGx

T

J

T

S

T

A

P

Din

Open drain output voltage

Junction temperature

Storage temperature

Ambient temperature

Power dissipation input chip

-

-

-

-

-

-

-

-

-

V

DIAGx

< 0.8 V

-0.30

-0.30

-0.30

-0.30

-15

VL - 0.30

-0.30

-2

VL - 0.30

-0.30

-

-

-0.30

-40

-50

-40

P

Dout dH/dt

ESD

Power dissipation output chip

Magnetic field immunity

Human body model

-

-

-

-

-

Max.

50

6.50

3.60

3.60

VDD + 0.30

40

40

0.30

VH + 0.30

VH + 0.30

(VH + 0.30, 20)

VH + 0.30

VH + 0.30

20

6.50

150

150 min

125

65

(T

J,max

- T

A

P

Din

)/R th(JA)

-

100

2

V

V

V

W

A/(m·s) kV

V

V

V

V

Unit

V/ns

V

V

°C

°C

°C mW

V

V

V

V mA

Thermal data

Table 3. Thermal data

Symbol

R th(JA)

Parameter

Thermal resistance junction to ambient (1)

1. The STGAP1BS mounted on the EVALSTGAP1BS rev 2.0 board (two-layer FR4 PCB).

Value

65

Unit

°C/W

DS11974 - Rev 4 page 5/59

3.3

STGAP1BS

Recommended operating conditions

Recommended operating conditions

Table 4. Recommended operating conditions

Symbol

VH

VL

VHL

VREG

V

VDD

LOGIC

Pin

17

Parameter

Positive supply voltage (VH vs. GNDISO)

14, 23 Negative supply voltage (VL vs. GNDISO)

-

7

6

Differential supply voltage (VH vs. VL)

Low voltage section power supply voltage vs.

GND

Low voltage section internal regulator voltage vs. GND

2, 3, 4, 5, 8, 9,

11

Logic pins voltage vs. GND

ASC

V

DESATth f

SW

24

18

-

ASC pin voltage

Desaturation protection threshold

Maximum switching frequency (4)

1. When UVLO is enabled, this value is VH on,max

2. When UVLO is enabled, this value is VL on,min

3. When VDD is connected to the VREG pin (refer to

Section 6 ).

4. Actual limit depends on power dissipation constraints.

(3)

Test condition

-

-

-

Min.

Max.

4.50

(1)

36

GNDISO - 10 GNDISO (2)

36

Unit

V

V

V

-

-

-

DESAT enabled

-

4.50

GNDISO

-

-

-

3.3 ±5%

5.50

(VDD, 5) min

(VH, 15) min

VH - 1.50

150

V

V

V

V

V kHz

DS11974 - Rev 4 page 6/59

STGAP1BS

Electrical characteristics

4

Electrical characteristics

4.1

AC operation

Table 5. AC operation electrical characteristics

(T j

= -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO)

Symbol Pin Parameter Test condition t deglitch t

INmin

8, 9, 11

Input deglitch time

INfilter = '11'

INfilter = '01'

INfilter = '10'

INfilter = '00' and (2LTO_EN = '1' or

2LTOtime = 0x0) t

Don t

Doff

8, 9, 11, 20

8, 9, 11, 21

Minimum propagated input pulse

Input to output propagation delay ON

Input to output propagation delay OFF

Deglitch filter and 2LTO disabled

Deglitch filter and 2LTO disabled t r t f

PWD 8, 9, 11, 20, 21

Pulse width distortion |t

Don

t

Doff

|

DT

20

21

GON rise time

GOFF rise time

8, 9, 20, 21 Deadtime

VL = 0 V;

C

L

= 2 nF, 10% ÷ 90%

VL = 0V

C

L

= 2 nF, 90% ÷ 10% t

IN

> 100 ns

Deglitch filter and 2LTO disabled

DTset = '01'

DTset = '10'

DTset = '11' t release

11 Minimum flag release time SD = '0', SD_FLAG = '1'

4.2

DC operation

Table 6. DC operation electrical characteristics

(T j

= -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO)

Symbol Pin Parameter Test condition

V ol

V oh

I

INh

I

INl

I

SDh

I

SDl

R in_pd

R in_pu

2

8, 9

11

SDO logic “0” output voltage

SDO logic “1” output voltage

INx logic “1” input bias current

INx logic “0” input bias current

SD logic “1” input bias current

SD logic “0” input bias current

8, 9, 11 Input pull-down resistors

4 CS input pull-up resistor

Logic inputs/output

I = 4 mA

I = 4 mA

V

IN

= 5 V

(pin 8 used as IN-)

V

IN

= 0 V

(pin 8 used as IN-)

V

SD

= 5 V

V

SD

= 0 V

V

IN

= 5 V

(pin 8 used as IN-)

CS = GND

Min.

-

4.85

55

-

55

-

35

35

Typ.

85

-

85

-

60

55

-

-

Min. Typ. Max. Unit

50 70 90 ns

100 160 220 ns

420 500 580 ns

20 ns

90 100 130 ns

90 100 130 ns

25 ns

25 ns

4 10 ns

205 250 295

650 800 945

985 1200 1415

ns

105 μs

Max.

Unit

0.15

-

145

0.10

145

0.10

85

80

μA

μA

μA

μA kΩ kΩ

V

V

DS11974 - Rev 4 page 7/59

I

REG

VDD on

VDD off

VDD hys

OV

VDDon

OV

VDDoff

OV

VDDhys

Symbol

V

V

I

I

I

V il

V ih

GON

GOFF

GOFFL

GONH

SafeClp

QDD

VH

VH

VH

VL

VL on off hyst on off

Pin

3, 4, 5, 8,

9, 11

20

21

21

20

Parameter

Low logic level voltage

High logic level voltage

20, 21, 22 GOFF active clamp

6

7

7

17

14, 23

Source short-circuit current

Sink short-circuit current

GOFF output low level voltage

GON output high level voltage

VREG short-circuit current

(see Section 7.3

)

VDD UVLO turn-on threshold

VDD UVLO turn-off threshold

VDD UVLO hysteresis

VDD OVLO turn-on threshold

VDD OVLO turn-off threshold

VDD OVLO hysteresis

VDD quiescent supply current

VH UVLO turn-on threshold

VH UVLO turn-off threshold

VH UVLO hysteresis

VL UVLO turn-on threshold

VL UVLO turn-off threshold

-

-

-

-

VDD = 5 V;

SD = 5 V; INx = GND; f = 0 Hz

VDD = 5 V;

SD = 5 V; f

SW

= f

SW,max

VHONth = '01'

VHONth = '10'

VHONth = '11'

VHONth = '01'

VHONth = '10'

VHONth = '11'

-

VLONth = '01'

VLONth = '10'

VLONth = '11'

VLONth = '01'

VLONth = '10'

Test condition

-

-

Driver buffer section

T pulse

< 5 µs, DC = 1%

T j

= 25 °C

T j

= -40 - +125 °C

T pulse

< 5 µs, DC = 1%

T j

= 25 °C

T j

= -40 - +125 °C

I

GOFF

= 0.1 A

I

GOFF

= 1 A

I

GON

= 0.1 A

I

GON

= 1 A

I

GOFF

= 0.2 A;

VH floating;

GON = GOFF = CLAMP

Supply voltage

0.1 V < VREG < 3.0 V

VREG < 0.1 V

-

-

STGAP1BS

DC operation

Min.

Typ.

Max.

Unit

0.29 · VDD 0.33 · VDD 0.37 · VDD V

0.62 · VDD 0.66 · VDD 0.79 · VDD V

5 A

2.50

(1)

7

5

2.50

(1)

VL + 0.03

VL + 0.50

VH - 0.18

VH - 2.10

VL + 0.09

VL + 1

VH - 0.10

VH - 1.30

6

VL + 0.15

VL + 1.80

VH - 0.05

VH - 0.50

A

V

V

3 V

-

-

3.95

3.65

0.15

5.30

5.40

100

5.20

60

15

4.10

3.80

-

5.50

5.70

200

6.50

120

35

4.30

4

-

5.90

6.10

300

7.50

mA

V

V

V

V

V mV mA

6.00

0.70

-3.15

-5.25

-7.35

-2.15

-4.25

9.40

11.30

13.15

8.45

10.35

12.25

8.50

-5

-7

1

-3

-2

-4

10

12

14

9

11

13

9.50

1.30

-2.80

-4.70

-6.55

-1.90

-3.80

10.50

12.60

14.70

9.45

11.55

13.65

mA

V

V

V

V

V

DS11974 - Rev 4 page 8/59

STGAP1BS

DC operation

Symbol

VL off

VL hys

OV

VHoff

OV

VHon

OV

VHhys

OV

VLoff

OV

VLon

OV

VLhyst

I

QH

V t

I t

I

I

QL

DESATth

DESfilter

DESAT

DESoff t

BLK

DESAT

V

SENSEth

Pin

14, 23

17

14, 23

17

14, 23

18

18

16

Parameter

VL UVLO turn-off threshold

VL UVLO hysteresis

VH OVLO turn-off threshold

VH OVLO turn-on threshold

VH OVLO hysteresis

Test condition

-

VLONth = '11'

OVLO_EN = '1'

OVLO_EN = '1'

OVLO_EN = '1'

VL OVLO turn-off threshold

VL OVLO turn-on threshold

OVLO_EN = '1'

OVLO_EN = '1'

VL OVLO hysteresis

VH quiescent supply current

VL quiescent supply current

OVLO_EN = '1'

SD = 5 V;

IN+ = 5 V; IN- = GND

VL = -5 V;

SD = 5 V;

IN+ = IN- = GND

Desaturation protection

DESATth = '000';

DESATth = '001'

DESATth = '010'

DESATth = '011'

Desaturation threshold

SENSE protection threshold

DESATth = '100'

DESATth = '101'

DESATth = '110'

DESATth = '111'

DESAT pin deglitch filter

DESAT blanking charge current

DESATth = '100'

(2)

DESATcur = '00';

V

DESAT

= 0 V

DESATcur = '01';

V

DESAT

= 0 V

DESATcur = '10';

V

DESAT

= 0 V

DESATcur = '11';

V

DESAT

= 0 V

DESAT blanking discharge current

DESAT protection fixed blanking time

V

DESAT

= 8 V

-

DESAT protection intervention time

V

DESAT

= V

DESAth

to GOFF 90%

C

LOAD

= 10 nF

2LTO disabled

SENSE overcurrent function

SENSEth = '000'

SENSEth = '001'

SENSEth = '010'

SENSEth = '011'

6.50

7.40

8.30

9.30

10

2.60

3.60

4.60

5.50

Min.

-6.35

0.70

17.80

16.90

0.60

-10.50

-9.45

0.70

5

300

Typ.

-6

1

19

18

1

-10

-9

1

6.70

420

Max.

-5.70

1.20

20

18.90

1.30

-9.40

-8.55

1.30

7.50

Unit

V

V

V

V

V

V

V

V mA

550 µA

220

440

660

885

50

160

80

88

110

135

158

3.10

4.20

5.30

6.30

7.40

8.40

9.40

10.50

30

265

V ns

525

800

μA

1050

90

340 mA ns

220 ns

9

10

7

8

20

3

4

5

6

250

500

750

1000

70

250

150

100

125

150

175

112

140

165

192 mV

DS11974 - Rev 4 page 9/59

STGAP1BS

DC operation

V

SENSEth t

Symbol t

V

SENSE

2LTOth

2LTOtime

Pin

16

21

21

Parameter

SENSE protection threshold

SENSE protection intervention time

2LTO threshold

2LTO time

Test condition

SENSEth = '100'

SENSEth = '101'

SENSEth = '110'

SENSEth = '111'

SENSEth = '111'

0→1 V step on V

SENSE

to GOFF

90%;

C

LOAD

= 10 nF

2LTO disabled

2-level turn-off function

2LTOth = '0000'

2LTOth = '0001'

2LTOth = '0010'

2LTOth = '0011'

2LTOth = '0100'

2LTOth = '0101'

2LTOth = '0110'

2LTOth = '0111'

2LTOth = '1000'

2LTOth = '1001'

2LTOth = '1010'

2LTOth = '1011'

2LTOth = '1100'

2LTOth = '1101'

2LTOth = '1110'

2LTOth = '1111'

2LTOtime = '0001'

2LTOtime = '0010'

2LTOtime = '0011'

2LTOtime = '0100'

2LTOtime = '0101'

2LTOtime = '0110'

2LTOtime = '0111'

2LTOtime = '1000'

2LTOtime = '1001'

2LTOtime = '1010'

2LTOtime = '1011'

2LTOtime = '1100'

2LTOtime = '1101'

2LTOtime = '1110'

2LTOtime = '1111'

Min.

185

235

285

380

-

Typ.

200

250

300

400

95

Max.

215

268

315

420

120

Unit mV ns

0.75

1.00

1.50

2.00

2.50

12.50

13.00

13.50

14.00

14.50

7.00

7.50

8.00

8.50

9.00

9.50

10.00

10.50

11.00

11.50

12.00

4.50

4.75

5.00

5.25

5.50

3.00

3.50

3.75

4.00

4.25

0.64

0.89

1.36

1.83

2.30

11.87

12.35

12.82

13.30

13.77

6.65

7.12

7.60

8.07

8.55

9.02

9.50

9.97

10.45

10.92

11.40

4.18

4.42

4.66

4.90

5.12

2.77

3.25

3.47

3.71

3.94

0.89

1.15

1.65

2.18

2.70

13.13

13.65

14.18

14.70

15.23

7.35

7.88

8.40

8.93

9.45

9.98

10.50

11.03

11.55

12.08

12.60

4.82

5.08

5.34

5.63

5.95

3.23

3.75

4.03

4.29

4.56

V

μs

DS11974 - Rev 4 page 10/59

V

VCECLth

V

VCECLhy st t

VCECLoff t

VCECL

V

ASCl

V

ASCh

I

ASCh

I

ASCl

R

ASC t

ASC t

Gchk

V

Gchk t

Rchk

I

GOFFchk

I

SENSERc hk t

SENSEchk t

DESATchk

Symbol

V t

R

I

I

I

DIAG1,2

DIAG1

DIAG2

DIAG1,2

CLAMPth

CLAMP

V

CLAMP_L

T

T

T

WN

SD hys

-

-

-

Pin

8, 10

22

19

19

24

20, 21

20

16

21

16

18

Parameter Test condition

Diagnostic outputs

Fault event to DIAGx Low delay Fault event to DIAGx 90%

DIAG1 low level sink current

DIAG2 low level sink current

DIAGx pull-down resistor

V

DIAG1

= 0.4 V

V

DIAG2

= 0.4 V

-

Clamp Miller function

CLAMP voltage threshold CLAMP vs. GNDISO

Clamp short-circuit current

T pulse

< 5 µs, DC = 1%

T j

= 25 °C

T j

= -40 ÷ +125 °C

Clamp low level output voltage I

CLAMP

= 1 A

VCE active clamping protection

V

CE

clamping threshold -

V

CE

clamping threshold hysteresis

V

CE

clamping time-out

V

CE

clamping intervention time

(2)

-

-

-

ASC function

Low logic level voltage -

High logic level voltage

ASC logic “1” input bias current

ASC logic “0” input bias current

ASC pull-down resistors

ASC intervention time

-

V

ASC

= 5 V

V

ASC

= 0 V

V

ASC

= 5 V

V

ASC

= 5 V

Functionality checks

Gate path check time (GON/

GOFF) (3)

Gate path check voltage (GON)

-

SENSE resistor check time

GOFF path check current -

-

-

SENSE resistor check current V

SENSE

< 1 V

SENSE comparator check time -

DESAT comparator check time -

Overtemperature protection

Warning temperature

(2)

Shutdown temperature (2)

Temperature hysteresis (2)

-

-

STGAP1BS

DC operation

Min.

-

10

10

300

Typ.

5

18

18

550

Max.

-

30

30

800

Unit

1.70

2 2.30

V

2.50

(1)

VL + 0.50

5

VL + 1

A

6

VL + 1.80

V

μs mA mA kΩ

VL + 1.20

VL + 1.60

0.30

2

-

0.50

2.30

20

VL + 2

0.60

2.60

-

V

V

μs ns

0.80

1.80

55

-

35

100

1.10

2.20

100

-

50

-

1.40

2.40

145

0.10

70

250

V

V

μA

μA kΩ ns

30 μs

0.7 x VH 0.76 x VH 0.84 x VH V

15 μs

-420 -350 -280 μA

8 10 12 μA

-

-

-

15

15

μs

μs

125

155

-

-

-

20

-

-

-

°C

°C

°C

DS11974 - Rev 4 page 11/59

STGAP1BS

DC operation

I

Symbol

STBY_VD t t rCK

t fCK t hCK

t lCK t

D t sleep t awake

CKmax t setCS t holCS desCS

Pin

7

-

-

5

4

Parameter

VDD standby current

Test condition

Standby

VDD = 5 V

Standby time

SD = '0', measured from CS rise

Logic wake-up time (2)

SD = '1'

SPI (characterization data, not tested in production)

Maximum SPI clock frequency -

SPI clock rise and fall time

SPI clock high and low time

CS setup time

CS hold time

CS deselect time (4)

CL = 30 pF

-

-

-

Local register read

Remote register read

Start configuration

Stop configuration

Min.

0.40

500

5

5

-

75

350

10

800

30

22

5

Reset status register 50 t setSDI t holSDI t enSDO t disSDO t vSDO t holSDO t

SDLCSL t

CSHSDH

3

2

4, 11

4, 11

SDI setup time

SDI hold time

SDO enable time

SDO disable time

SDO valid time

SDO hold time

SD falling to CS falling

CS rising to SD rising

1. Guaranteed by correlation.

2. Characterization data, not tested in production.

3. The actual waiting time depends on the gate charge size.

4. See

Table 22

and Section 9.1.3

.

Any other command

-

-

-

-

-

-

-

-

700

25

20

-

37

350

350

-

-

Typ.

0.80

700

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Max.

Unit

1

900

mA ns

μs

-

57

-

-

-

-

38

47

25

-

-

-

-

-

-

-

-

-

-

-

MH z ns ns ns ns ns

μs ns ns ns ns ns ns ns ns ns

DS11974 - Rev 4 page 12/59

5

STGAP1BS

Isolation

Isolation

Table 7. Isolation and safety-related specifications

Parameter

Clearance

(minimum external air gap)

Creepage

(minimum external tracking)

Comparative tracking index (tracking resistance)

Isolation group

Symbol Value Unit

CLR

CPG

CTI

-

8

8

≥ 400

II mm mm

-

-

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body

Conditions

DIN IEC 112/VDE 0303 Part 1

Material group (DIN VDE 0110, 1/89, Table 1)

Table 8. IEC 60747-5-2 isolation characteristics

Parameter

Installation classification (EN 60664-1, Table 1

(1)

)

For rated mains voltage ≤ 150 V rms

For rated mains voltage ≤ 300 V rms

For rated mains voltage ≤ 600 V rms

Pollution degree (EN 60664-1)

Maximum working isolation voltage

Symbol

-

-

V

IORM

Test conditions

-

-

-

Input to output test voltage as per IEC 60747-5-2 V

PR

Method a, type test

V

PR

= V

IORM

× 1.6, t m

= 10 s

Partial discharge < 5 pC

Method b1, 100 % production test

V

PR

= V

IORM

× 1.875, t m

= 1 s

Partial discharge < 5 pC

Transient overvoltage as per IEC 60747-5-2 (highest allowable overvoltage)

V

IOTM t ini

= 60 s; type test

Maximum surge isolation voltage

Isolation resistance

V

IOSM

R

IO

Type test

V

IO

= 500 V at T

S

; type test

1. For three-phase systems the values in the table refer to the line-to-neutral voltage.

Characteristic Unit

I - IV

I - III

I - II

2

1500

2400

2815

4000

4000

>10 9

V

V

V

V

V

-

-

PEAK

PEAK

PEAK

PEAK

PEAK

Ω

Table 9. UL 1577 isolation voltage ratings

Description

Isolation withstand voltage, 1 min. (type test)

Isolation withstand test, 1 sec. (100% production)

Symbol

V

ISO

V

ISOtest

Characteristic

2500\3536

3000\4245

Unit

V rms

\V

PEAK

V rms

\V

PEAK

DS11974 - Rev 4 page 13/59

STGAP1BS

Logic supply management

6

Logic supply management

6.1

Low voltage section voltage regulator

The device integrates in the low voltage section a linear voltage regulator that can be used to obtain the 3.3 V logic core supply voltage from an external 5 V supply voltage. If an external 3.3 V supply voltage is available,

the VDD and VREG must be shorted as shown in Figure 3 . The logic IOs are referred to the VDD voltage (see

Table 6

for details).

4.7 µF

Figure 3. Low voltage section 3.3 V voltage regulator

VDD from +5 V power supply VDD from +3.3 V power supply

+5V +3.3V

VDD

VDD

100 nF

LDO

Reg

LDO

Reg

VREG VREG

100 nF 4.7 µF 100 nF

Undervoltage protection is available on the VDD supply pin (disabled by default).

When the VDD voltage goes below the VDD off

threshold the device and its outputs goes in “safe state” (see

Section 6.3 ) and the UVLOD status flag is forced low. Once the protection is triggered, the UVLOD flag is

latched and the device remains in “safe state” until the UVLOD flag is not released. See

Section 7.11

for indication on how the failure flags can be released.

This protection can be enabled writing the UVLOD_EN bit of the CFG1 register (disabled by default).

Overvoltage protection is available on the VDD supply pin.

When the VDD voltage goes over the OV

VDDoff

threshold, the device and its outputs go in “safe state” and the OVLOD status flag is set. The device remains in “safe state” and the OVLOD flag is latched, see

Section 7.11

for indication on how the failure flags can be released.

DS11974 - Rev 4 page 14/59

6.2

6.3

6.4

STGAP1BS

High voltage section voltage regulator

High voltage section voltage regulator

The device integrates in the high voltage section a linear voltage regulator that generates the 3.3 V logic core supply voltage from an external supply voltage connected to the VH pin.

Figure 4. High voltage section 3.3 V voltage regulator

VH

VH

100 nF

LDO

Reg

VREGISO

4.7 µF 100 nF

If the voltage at the VREGISO pin goes below the minimum operating threshold which causes the logic reset, the

REGERRR bit in the STATUS2 register is set high.

•

•

•

•

Power-up, power-down and “safe state”

The following conditions define the device's “safe state”:

GOFF = ON state

GON = high impedance

CLAMP = ON state (if CLAMP < 'GNDISO + V

CLAMPth

')

DESAT = GNDISO (internal switch on and current generator off)

Such conditions are guaranteed at power-up of the isolated side (also for VH < VH on

and VL > VL on

) and during the whole device power-down phase (also for VH < VH off

and VL > VL off

), whatever the value of the input pins.

The device integrates a structure which clamps the driver output to a voltage smaller than SafeClp when the VH voltage is not high enough to actively turn the GOFF N-channel MOSFET on.

If the VH positive supply pin is floating the GOFF pin is clamped to a voltage smaller than SafeClp.

After power-up of the isolated side the REGERRR status flag is latched and the device is forced in “safe state”.

See

Section 7.11 for indication on how the failure flags can be released.

After power-up of the low voltage side the REGERRL and UVLOD status flags are latched and the device is

forced in “safe state”. See Section 7.11

for indication on how the failure flags can be released.

The UVLOH flag is also forced high at the power-up of the low voltage side, but its value is set to zero as soon as the isolated side power-up is completed.

Standby function

The device can be put in standby mode to reduce the power consumption on VDD via the SPI command “ Sleep ”

(refer to

Section 9.1.5 ).

The proper sequence is:

1.

Pull-down the SD pin: the driver section will be put in “safe state”

2.

Send a Sleep command

3.

After a t sleep

time, the device can be considered in sleep mode.

To exit from the sleep mode, it is necessary to set the SD high for at least t awake

while keeping IN+ low.

After a t awake

time the device can accept new commands and the REGERRR bit is set to indicate that the device needs to be reprogrammed.

If the SD pin is raised while t sleep

is still not expired, the device returns to the operation mode within a t awake

time.

DS11974 - Rev 4 page 15/59

STGAP1BS

Functional description

7

Functional description

7.1

7.2

Inputs and outputs

•

•

The device is controlled through following logic inputs:

• SD: active low shutdown input

•

IN+: driver input

CS: active low chip select (SPI)

SDI: serial data input (SPI)

• CK: serial clock (SPI)

And following logic outputs:

• SDO: serial logic output (SPI)

• DIAG1: diagnostic signal (open drain)

And following IO pin:

• IN-/DIAG2: driver input or diagnostic open drain output.

Logic input thresholds and output ranges vary according to VDD voltage. In particular, the device is designed to work with VDD supply voltages of 5 V or 3.3 V.

The operation of the driver IOs can be programmed through DIAG_EN bits as described in Table 10

.

Table 10. Inputs true table (device NOT in “safe state”)

Bit in CFG1 register

DIAG_EN

X

0

0

1

0

0

1

SD

0

1

1

1

1

1

1

Input pins

IN+

X

0

1

0

0

1

1

0

1

X

(1)

X

(1)

IN-

X

0

1

1. The IN-/DIAG2 pin is used as the open drain output for diagnostic signaling (refer to

Section 7.11

OFF

ON

OFF

OFF

GON

Output pins

GOFF

OFF

OFF

ON

ON

ON

OFF

ON

ON

ON OFF

A deglitch filter is applied to device inputs (SD, IN+, IN-). Each input pulse, positive and negative, shorter than the programmed t deglitch

value is neglected by internal logic. Deglitch time can be programmed as listed in

Table 30 .

When the deglitch filter is disabled (INfilter = '00') and the 2-level turn-off function is disabled (2LTOtime = 0x0) or enabled only after a fault event (2LTO_EN = '1'), a minimum input pulse t

INmin

is required to change the device output status. The minimum input pulse timing filters out both positive and negative pulses at the IN+, IN- and SD pins.

Deadtime and interlocking

When single gate drivers are used in half-bridge configuration, they usually do not allow preventing cross conduction in case of wrong input signals coming from the controller device. This limitation is due to the fact that each driver does not have the possibility to know the status of the input signal of the other companion driver in the same leg. Thanks to the availability of two input pins with opposite polarity the STGAP1BS allows implementing hardware interlocking that prevents cross conduction even in case of wrong input signals generated by the control unit. This functionality can be achieved by implementing the connection shown in

Figure 5

and by configuring the IN-/DIAG2 pin as input (which is its default configuration).

DS11974 - Rev 4 page 16/59

STGAP1BS

Deadtime and interlocking

Figure 5. HW cross conduction prevention in half-bridge configuration with two single gate drivers

IN+

IN-

STGAP1BS HS

μC

HIN

LIN

IN+

IN-

STGAP1BS LS

When such configuration is used, it is also possible to enable the STGAP1BS programmable deadtime feature, which guarantees that at least a DT time passes between the turn-off of one driver's output and the turn-on of the other driver. The deadtime value DT can be programmed through the SPI interface as shown in

Table 29 .

If the deadtime feature is enabled, a counter is started when the input status changes from < IN- = '1' and IN+ =

'0' > to a different combination, which means that the other driver in the same leg is at the beginning of a turn-off

(refer to

Figure 6

).

Once the counter is started it keeps counting regardless of any input variation until a DT time has passed, and during this time the driver prevents the turn-on of its output even if the controller tries to force the turn-on (inputs set to < IN- = '0' and IN+ = '1' >).

Once the programmed DT counter is expired, the driver immediately turns the output on as soon as a turn-on command is present at the input pins, and no extra delay is added.

Figure 6. Transitions causing the DT generation

IN- = 1

IN+ = 0

paired

Driver ON

DS11974 - Rev 4

ALL OFF

IN- = 0

IN+ = 0

IN- = 0

IN+ = 1

this

Driver ON

IN- = 1

IN+ = 1

ALL OFF

Transitions causing the DT generation

Some examples of the device behavior when the deadtime feature is enabled are shown from

Figure 7

to

Figure 10 .

page 17/59

7.3

7.4

STGAP1BS

Hardware RESET

Figure 7. Synchronous control signal edges

IN-

SYNCHRONOUS

CONTROL SIGNALS EDGES;

DEAD TIME

IN+

GON-GOFF

DT

Figure 8. Control edges signal overlapped, example 1

IN-

CONTROL SIGNALS EDGES

OVERLAPPED;

DEAD TIME

IN+

GON-G OFF

DT DT

Figure 9. Control edges signal overlapped, example 2

CONTROL SIGNALS EDGES

NOT OVERLAPPED,

BUT INSIDE THE DEAD TIME:

DEAD TIME

IN-

IN+

GON-GOFF

DT

DT

DT

DT

Figure 10. Control edges signal not overlapped and outside DT (direct control)

CONTROL SIGNALS EDGES

NOT OVERLAPPED,

OUTSIDE THE DEAD TIME:

DIRECT DRIVING

IN-

IN+

GON-GOFF

DT DT

When the deadtime function is enabled, the STGAP1BS returns a “deadtime violation” fault when the control unit tries to turn on any of the drivers in one leg during the counting of the programmed DT time. If such event occurs the DT_ERR flag is set high and latched.

Hardware RESET

The device can be reset by forcing the VREG pin to ground through an external switch. The internal regulator is designed to stand this condition.

The maximum current required to force the VREG pin to ground is indicated by the parameter I

REG

.

Power supply UVLO and OVLO

Undervoltage protection is available on both VH and VL supply pins.

The turn-on threshold can be programmed through the SPI writing the CFG4 register. A fixed 1 V hysteresis will set the respective turn-off threshold.

Both UVLO protections can be independently disabled by setting the proper value in the CFG4 register.

DS11974 - Rev 4 page 18/59

7.5

7.6

STGAP1BS

Thermal warning and shutdown protection

When VH voltage goes below the VH off

threshold, the output buffer goes in “safe state” and the UVLOH status flag is forced high. If the UVLOlatch bit in the CFG4 register is set low (default), the UVLOH status flag is released when VH voltage reaches the VH on

threshold and the device returns to normal operation.

Otherwise, the UVLOH flag is latched and the device remains in “safe state” until the VH voltage reaches the

VH on

threshold and the flag is released. See Section 7.11 for indication on how the failure flags can be

released.

When VL voltage goes over the VL off

threshold, the output buffer goes in “safe state” and the UVLOL status flag is forced high. If the UVLOlatch bit in the CFG4 register is set low (default), the UVLOL status flag is released when

VL voltage goes below the VLon threshold and the device returns to normal operation.

Otherwise. the UVLOL flag is latched and the device remains in “safe state” until the VL voltage goes below the

VL on

threshold and the flag is released. See Section 7.11 for indication on how the failure flags can be released.

Overvoltage protection is available on both VH and VL supply pins. Both OVLO protections can be disabled by setting the proper value in the CFG4 register.

When the VH voltage goes over the OV

VHoff

threshold, the output buffer goes in “safe state” and the OVLOH status flag is forced high. The OVLOH flag is latched and the device remains in “safe state” until VH voltage goes

below the overvoltage threshold and the flag is released. See Section 7.11

for indication on how the failure flags can be released.

When VL voltage goes over the OV

VLoff

threshold, the output buffer goes in “safe state” and the OVLOL status flag is forced high. The OVLOL flag is latched and the device remains in “safe state” until VH voltage goes below the overvoltage threshold and the flag is released. See

Section 7.11

for indication on how the failure flags can be released.

Thermal warning and shutdown protection

The device provides a thermal warning and a thermal shutdown protection.

When junction temperature reaches the T

WN

temperature threshold the TWN flag in the STATUS1 register is forced high. The TWN flag is released as soon as the junction temperature is lower than T

WN

- T hys

.

When junction temperature reaches the T

SD

temperature threshold, the device is forced in “safe state” and the

TSD flag in the STATUS1 register is forced high. The device operation is restored and the TSD flag is released as soon as the junction temperature is lower than T

SD

- Thys.

Desaturation protection

This feature allows implementing an overload protection for the IGBT. The DESAT pin monitors the V

CE

voltage of the IGBT while it is on, and if the protection threshold is reached, the IGBT is turned off.

DS11974 - Rev 4 page 19/59

DS11974 - Rev 4

A

T

I

O

L

I

S

O

N

STGAP1BS

Desaturation protection

Figure 11. Example of desaturation protection connection

LOGIC

+

DESATcurr

(programmable)

DESATth

(programmable)

Discharge switch

VH

DESAT

Cblank

Rg_on

GON

GOFF

I

C

VL

GNDISO

When the IGBT is off (GOFF output is activated) the DESAT pin is kept low internally and the external blanking capacitor connected to the DESAT pin is discharged (the internal current generator is fully switched off and the switch between DESAT and GNDISO pins is turned on).

When the GON output is activated the switch between DESAT and GNDISO pins is turned off and an internal programmable current generator (I

DESAT

) starts charging the external blanking capacitor after a fixed blanking time t

BLK

.

If a desaturation event occurs the V

CE

voltage increases and the voltage at the DESAT pin reaches the desaturation threshold V

DESATth

: the DESAT comparator output is set, the device is forced in “safe state” and the DESAT flag is forced high and latched.

The DESAT comparator is not active when the external IGBT is off or after desaturation detection (see Figure 12

).

Both the V

DESATth

threshold and the I

DESAT

blanking current are programmable through the SPI.

page 20/59

7.7

STGAP1BS

VCE active clamping protection

Figure 12. DESAT protection timing diagram

IN+

Comparator Disabled Comparator Enabled Comparator Disabled

t

DESAT

VH level

GON-GOFF

V

DESATth

DESAT

VL level

Blanking time

t

BLK t

DIAGx

DiagX

A deglitch filter is applied to the DESAT pin. Each pulse exceeding the V

DESATth

for a time shorter than t value shall not trigger the protection.

DESfilter

V

CE

active clamping protection

This protection is used to actively clamp the drain/collector overvoltage spikes during the MOSFET/IGBT turn-off.

This feature allows using low turn-off resistor values leading lower turn-off losses, thus increasing efficiency, while limiting the maximum turn-off spike on the collector (or drain) within safe limits.

The direct feedback of the collector voltage to the device can for example be made via an element with avalanche characteristics such as a TVS. If the V

CE

voltage exceeds the breakdown voltage of the TVS, the V

VCECLth threshold voltage on the VCECLAMP is reached and the IC actively slows down the power switch turn-off to keep a safe condition.

The active limiting of the driver's turn-off current strongly reduces the current flowing through the TVS, thus preventing it from operating in overstressing conditions.

DS11974 - Rev 4 page 21/59

STGAP1BS

SENSE overcurrent protection

Figure 13. Example of V

CE

active clamping protection connection

VCECLAMP

7.8

Floating

Section

Control

Logic

Level

Shifter

VH

GON

GOFF

CLAMP

VL

VLVLVL

GNDISO

+

CLAMPth

When the VCECLAMP is activated during the turn-off phase a watchdog timer starts inside the driver. This timer allows the VCECLAMP pin to act on the driver's output status for a t

VCECLoff

time maximum. After that time has expired, the driver continues the normal turn- off ignoring the VCECLAMP pin status. This assures that the protection is only acting to clamp inductive V

CE

spikes during the turn-off.

The timer is reset and the VCECLAMP protection is enabled again at the beginning of the following turn-off sequence.

Figure 14. VCECLAMP timing diagram

GON\GOFF

VCECLAMP

VCEcounter

stopped ready counting t

VCECLof stopped ready

The VCECLAMP pin is masked and has no effect on the driver's outputs status when the external MOSFET/IGBT is on.

The V

CE

active clamping protection can be disabled connecting the VCECLAMP pin to VL.

SENSE overcurrent protection

This function is suitable in applications in which it is possible to measure the load current through the use of a shunt resistor, or in applications that use IGBTs with the current sense pin available. The load current (or a fraction of it in case SenseFETs are used) is converted to voltage by an external shunt resistor and is fed to the

SENSE pin (comparator input).

DS11974 - Rev 4 page 22/59

STGAP1BS

Miller clamp function

When an overcurrent event occurs the sense voltage reaches the V

SENSEth

threshold, the device is forced in “safe state” and the SENSE status flag is forced high and latched.

The V

SENSEth

threshold is programmable through the SPI (refer to Section 9.2.2

).

Figure 15. Example of SENSE overcurrent protection connection

I

C

VH

Rg_on

GON

GOFF

A

T

I

O

N

I

S

O

L

LOGIC

VL

SENSE

Vref

(programmable)

GNDISO

Rsense

7.9

7.10

Miller clamp function

The Miller clamp function allows the control of the Miller current during the power stage switching in half-bridge configurations. When the external power transistor is in the OFF state, the driver operates to avoid the induced turn-on phenomenon that may occur when the other switch in the same leg is being turned on, due to the C gc capacitance.

During the turn-off period the gate of the external switch is monitored through the CLAMP pin.

The CLAMP switch is activated when gate voltage goes below the voltage threshold V

CLAMPth

, thus creating a low impedance path between the switch gate and the VL pin.

This function can be disabled setting low the CLAMP_EN bit in the CFG5 register (high by default).

2-level turn-off function

If an overcurrent event happens, a large voltage overshoot exceeding V

CE

absolute ratings may occur across the power switch during the turn-off, due to the parasitic stray inductances.

The 2-level turn-off function (2LTO) allows the reduction of the stressing overvoltage experienced by the power component in overcurrent condition by switching off the external power in two phases.

In the first phase, the GOFF voltage is actively forced to a programmable value V

2LTOth

; after a programmable delay t

2LTOtime

the GOFF is forced to VL to complete the gate turn-off.

This allows to slow down the critical part of the turn-off transient, that may induce the overvoltage spikes.

The voltage level V

2LTOth

and duration t

2LTOtime

of the intermediate off-level are programmable through the SPI.

It is possible to program when this feature takes place, refer to the following paragraphs.

DS11974 - Rev 4 page 23/59

STGAP1BS

2-level turn-off function

7.10.1

2-level turn-off function - Always

The 2LTO is performed at each turn-off transition (2LTO_EN = '0').

When 2LTO is used, at each transition the minimum on or off pulse width is determined by 2LTO time. Some sample waveforms are given in

Figure 16 and Figure 17 , where IN

AND

represents the condition: < IN+ = 'H' and

IN- = 'L' >.

If a turn-on pulse is shorter than t

2LTOtime

it shall be ignored; turn-on pulses longer than t

2LTOtime

will determine a delay in the turn-on equal to t

2LTOtime

(see

Figure 16 ).

Figure 16. Example of short turn-on pulses when 2LTO occurs at each cycle

ON

time

ON

time

IN

AND

GON-GOFF

t

2LTOtime

ON-time < t

2LTOtime t

2LTOtime t

2LTOtime t

Doff

ON

time t

Don t

2LTOtime

ON-time < t

2LTOtime

ON-time > t

2LTOtime t

2LTOtime t

Don

ON-time > t

2LTOtime t

Doff

ON

time t

2LTOtime

When a turn-off pulse is detected the turn-off procedure starts immediately by forcing the V

2LTOth

voltage on the

GOFF pin. If the duration of the turn-off pulse is shorter than t

2LTOtime

GOFF in high impedance and turning GON on again (see

Figure 17 ).

the turn-off sequence is aborted by setting

Figure 17. Example of short turn-off pulse when 2LTO occurs at each cycle

IN

AND t

Dof t

Dof t

Don t

Dof

7.10.2

GON-GOFF

t

2LTOtime t

2LTOtime t

2LTOtime

OFF-time > t

2LTOtime

OFF-time < t

2LTOtime

OFF-time > t

2LTOtime

When the 2LTO is used at each cycle, any event that forces the device to enter in “safe state” generates a driver switch off performing a 2LTO sequence.

2-level turn-off function - Fault

The 2LTO is performed only after a desaturation or overcurrent event (2LTO_EN = '1'). In such cases the device

enters in “safe state” until the failure flag is released. See Section 7.11 for indication on how the failure flags can

be released.

This configuration overrides some drawbacks of using the 2LTO at each turn-off, such as the minimum pulse width equal to t

2LTOtime

and the turn-on delay needed to avoid duty cycle distortion.

With this configuration the turn-off is only slowed down in case of desaturation or overcurrent events.

DS11974 - Rev 4 page 24/59

STGAP1BS

Failure management

7.10.3

7.11

Figure 18. Example of operation with 2LTO in “Fault” mode

IN

AND

V

DESATth

DESAT

GON-GOFF

t

Dof t

Don t

Dof t

Don t

DESAT t

2LTOtime

2-level turn-off function - Never

The 2LTO function is disabled (2LTOtime = 0x0). In this case a standard turn-off sequence is used (directly lowering the gate voltage from VH to VL) also in case of desaturation or sense overcurrent events.

•

•

Failure management

The device provides advanced diagnostic through open drain outputs (DIAG1/DIAG2) and internal status

registers. The DIAG2 output shares the same pin of the IN- input (see Figure 1 ); the diagnostic signal through the

pin is enabled through the DIAG_EN bit as described in

Section 7.1

.

Status registers (STATUS1, STATUS2 and STATUS3) provide failures and status information as listed in respective paragraphs.

DIAG1 and DIAG2 pins can be programmed through the dedicated registers (DIAG1CFG and DIAG2CFG) to signal one or more failure conditions. The output value is the result of the NOR of the selected status bits: if one of the selected bits is high, the output is forced low.

Some of the failure conditions reported by the status registers are latched, i.e.: the flag is kept high even if the triggering condition is expired.

Different methods can be used to clear the failure flags contained in the status registers:

• Using the ResetStatus command

The SD must be set low before giving this command and must remain low until the end of the command’s execution time.

This is the recommended method, because guarantees that status registers are only cleared by direct intervention of the MCU.

All flags in the StatusRegisters are released after a t desCS

time following the rise of the SPI CS.

Forcing low the SD pin for at least t release

All the flags are released at the rising edge of the SD. This mode is enabled at device’s power-on, but it can be disabled by setting the SD_FLAG configuration bit low during the configuration phase, and by doing this any possibility to clear a FLAG without direct intervention of the MCU is prevented. Even if the

SD_FLAG is set high, status registers are not cleared after the rising edge of the SD if a configuration sequence is executed ( StartConfig , StopConfig ). This is done to avoid clearing errors that may have been generated during the configuration procedure.

Using HW reset

(see Section 7.3

)

In this case the device behaves as after power-up sequence.

In any of the above cases, if the failure condition is still present, the respective flag is not released.

Selected failures force the device in “safe state”; the device remains in this state until the relative status flags are released. Refer to

Table 49 ,

Table 51 and Table 53 for details.

The possibility to clear status registers by setting the SD low allows operating the device also without using the SPI interface. In order to avoid an unintended clear of fault conditions it is recommended to disable this functionality by setting the SD_FLAG = '0'.

DS11974 - Rev 4 page 25/59

STGAP1BS

Asynchronous stop command

7.12

7.13

7.14

7.14.1

Asynchronous stop command

The ASC pin allows to turn-on the GON output acting directly on the isolated driver logic and regardless of the status of the input pins IN+, IN- and SD. This pin is active high.

The status of this pin is mirrored in the ASC bit present in the STATUS2 register.

The power supply of the isolated section must be present (VH > VH on

).

In case UVLO on VH is not enabled, ASC function works for VH values within the recommended operating values.

This function works even if the VDD voltage is not available or is in UVLO condition.

The priority of such command is lower than that of DESAT and SENSE pins, so the ASC command is ignored in case of a desaturation or overcurrent fault. After such events the gate can be turned on again with a low-to-high

transition of the ASC pin, or by clearing the fault condition (see Section 7.11 ).

Watchdog and echo

The isolated side provides a watchdog function in order to identify when it is no more able to communicate with the LV side. In this case the driver is automatically forced in “safe state” and the REGERRR flag is set.

When the LV side is in the standby mode, turned off or in hardware reset condition, the isolated side watchdog is still operative and the REGERRR flag is set.

The low voltage side provides a watchdog function in order to identify when it is no more able to communicate with the isolated side. In this case the REGERRL flag is set and the device is forced in “safe state”.

An echo function is implemented in order to check that input commands toward the gate are correctly propagated to the driver's output. In case something should prevent the correct propagation of the command, the driver is able to detect this condition and will start a new communication (echo) in order to set the desired output state.

This process has typical duration of 4 μs.

•

Security check functions

•

•

•

•

•

The device allows verifying the gate and sense resistor connections and the functionality of SENSE and DESAT.

This can be achieved through the following security checks:

Logic inputs to isolated driver path

GON to gate path

GOFF to gate path

SENSE comparator

SENSE resistor

DESAT comparator

The check modes are enabled through a dedicated configuration register TEST1 (refer to

Section 9.2.9 ) and

thus require entering in configuration mode.

Only one check mode at a time must be enabled. At the end of security check procedure, the TEST1 register must be set to 0x00 before running the device in normal mode.

It is recommended to clear the status register with the ResetStatus command before and after each check.

To prevent the SD from clearing the STATUS flags, set the SD_FLAG = '0' as described in Section 7.11

.

Logic inputs to isolated driver path

The purpose of this security check is to verify the path integrity including the input buffer.

The check uses bit #[0] of the STATUS2 register, which contains information about the gate status request that the gate driver stage received from the logic inputs and reported. Please note that this value may differ from the actual GON and GOFF status, for example if some condition is forcing the device in “safe state”.

To perform this test, the following procedure has to be followed:

• Set SD = high, IN- = low and IN+ = low

• Set IN+ = high

• Wait at least t

Gchk

DS11974 - Rev 4 page 26/59

STGAP1BS

Security check functions

7.14.2

7.14.3

• Read GATE bit in the STATUS2 register

– GATE = '1' → OK

– GATE = '0' → FAIL

Set IN+ = low •

During all the duration of the check the logic inputs have to follow the levels indicated by the procedure and must not be otherwise modified.

Please note that when IN+ is set high during the check, the gate may be forced high (GON turned on). The user test routine has to take into account this behavior.

•

•

GON to gate path check

•

•

The purpose of this security check is to verify the path integrity including the driver's GON output, the GON

(turn-on) gate resistor, the power switch gate and the CLAMP pin (see

Figure 19 ).

To perform this test, the following procedure has to be followed:

• Set SD = low

• Send StartConfig

Set GONCHK = '1'

command

Send StopConfig command

Wait at least t

Gchk

Read TSD flag

– TSD = '0' → OK (V

CLAMP

> V

Gchk

)

– TSD = '1' → FAIL (V

CLAMP

< V

Gchk

)

Please note that during all the time the check is enabled the gate will be forced high (GON turned on) regardless the SD pin level. The user test routine has to take into account this behavior.

In any case, when GONCHK = '1', the protections SENSE and DESAT, if enabled, will continue to operate protecting the power switch regardless the SD pin.

•

•

•

•

•

•

GOFF to gate path check

The purpose of this security check is to verify the path integrity, including the driver's GOFF output, the GOFF

(turn-off) gate resistor, the power switch gate, and the CLAMP pin (see Figure 19

).

To perform this test, the following procedure has to be followed:

Set SD = low

Send StartConfig command

Set GOFFCHK = '1'

Send StopConfig command

Wait at least t

Gchk

+ t

GATE_GOFFchk

Read DESAT flag

– DESAT = '0' → OK (V

CLAMP

< V

CLAMPth

)

– DESAT = '1' → FAIL (V

CLAMP

> V

CLAMPth

)

During the check, a small current I

GOFFchk

will be sourced from the CLAMP pin while GOFF is on, keeping the gate low through the turn-off gate resistor.

To ensure the check result, some applicative conditions have to be verified:

• The bleeding resistor, sometimes present between the gate and source in the power switch, shall be higher than 8.2 kΩ.

• During the test, the power switch gate shall have the time to be charged up to V

CLAMPth

by I

GOFFchk

. In case no bleeding resistor is present, this time can be roughly computed as: t

GATE_GOFFchk

≈ C

GATE

* (V

CLAMPth

- VL) / I

GOFFchk

If a bleeding resistor is present or an additional push-pull circuit has been added, the time has to be computed with the adequate corrective factors.

If the check fails due to the lack of the GOFF resistor, the power switch gate will gradually rise up to VH with no protections of SENSE nor DESAT. The user test routine shall consider this behavior.

DS11974 - Rev 4 page 27/59

STGAP1BS

Security check functions

Figure 19. Gate paths check circuitry

SD

CS

CK

SDI

SDO

Control

Logic

SPI

T

I

O

N

I

S

O

L

A

Floating

Section

Control

Logic

Level

Shifter

+

V CLAMPth

I

GOFFchk

VH test control

Floating ground

VH

GON

GOFF

CLAMP

VL

GNDISO

7.14.4

SENSE comparator check

The purpose of this security check is to verify the functionality of the sense comparator.

To enable this check, it is necessary to set SNSCHK = '1' and SENSE_EN = '1'.

When this check is enabled the switch in series to the SENSE pin is open (see

Figure 20 ); a SENSE

fault (STATUS1 register) should be reported within t

SENSEchk

, otherwise the SENSE comparator operation is compromised.

•

•

V

SENSEcomp

> V

SENSEth

→ comparator OK → SENSE = '1'

V

SENSEcomp

< V

SENSEth

→ comparator FAIL → SENSE = '0'

The SENSE fault generated by this test is latched and shall be cleared accordingly.

DS11974 - Rev 4 page 28/59

STGAP1BS

Security check functions

SD

CS

CK

SDI

SDO

Control

Logic

A

T

I

O

I

S

O

L

N

Figure 20. SENSE comparator and resistor check circuitry

Floating

Section

Control

Logic

Level

Shifter

VH

GON

GOFF

CLAMP

VL

I

SENSERchk

VH

+

SENSEcomp

V SENSEth test control test control

SENSE

R test SPI

Floating ground GNDISO

R

SENSE

7.14.5

7.14.6

•

•

•

•

SENSE resistor check

The purpose of this security check is to verify the connection between the device and the sense shunt resistor and to verify the optional sense resistor filter network is not open.

To perform this test, the following procedure has to be followed:

• Set SD = low

•

•

Send StartConfig

Set SENSE_EN = '1'

command

Set RCHK= '1'

Send StopConfig command

Wait t

Rchk

+ t

SENSERchk

Read SENSE flag

– SENSE = '0' → OK (V

SENSE

< V

SENSEth

)

– SENSE = '1' → FAIL (V

SENSE

> V

SENSEth

)

During the check a small current I

SENSERchk

is sourced from the SENSE pin (see

Figure 20 ). If the sense resistor

is not present or floating, SENSE pin voltage will rise and once V

SENSEth

is exceeded, a SENSE fault will be reported in the STATUS1 register within t

Rchk

.

To ensure the check result, the following condition has to be verified:

• The SENSE flag read has to be delayed of t to reach V

SENSEth

by the I

SENSERchk

current.

SENSERchk

, which is the time the customer filtering network takes

DESAT comparator check

•

•

The purpose of this security check is to verify the functionality of the desaturation comparator.

To perform this test, the following procedure has to be followed:

Set SD = low

Send StartConfig command

DS11974 - Rev 4 page 29/59

STGAP1BS

Register corruption protection

•

•

•

•

•

•

•

Set DESAT_EN = '1'

Set DESCHK = '1'

Send StopConfig command

Set SD = high

Wait 3 μs

Apply at the inputs a gate turn on pulse longer than 500 ns

Read DESAT flag

– DESAT = '1' → OK (V

DESATcomp

> V

DESATth

)

– DESAT = '0' → FAIL (V

DESATcomp

< V

DESATth

)

During this test GON is first turned on and then turned off as soon the test succeeds. In case the test should fail, the output remains on as long as the input signal remains high.

At the end of the check the DESAT fault remains set (it is latched), and it has to be cleared.

Figure 21. DESAT comparator check circuitry

CS

CK

SDI

SDO

SD

IN+

INControl

Logic

O

N

T

I

I

S

O

L

A

Floating

Section

Control

Logic

SPI

+

I

DESAT

VH test control test control

V

DESATth

DESAT

C blank

Level

Shifter

Floating ground

VH

GON

GOFF

CLAMP

VL

GNDISO

1k

7.15

Register corruption protection

All the configuration registers are protected against content corruption.

If the value of a local register is changed without a proper command is received ( WriteReg or GlobalReset ), the REGERRL flag is set high and the device is forced in “safe state”.

If the value of a remote register is changed without a proper command is received ( WriteReg or GlobalReset ), the REGERRR flag is set high and the device is forced in “safe state”.

DS11974 - Rev 4 page 30/59

8

STGAP1BS

SPI interface

SPI interface

•

•

The IC communicates with an external MCU through a 16-bit SPI. This interface is used to set the device parameters and for advanced diagnostic.

SPI commands are executed after the rising edge of the CS, and adequate wait time must be respected before a new command is started by setting the CS low again. Refer to the t desCS

parameter in

Table 6

for required wait time after each command.

The SPI I/O pins are:

• CS: chip select (active low)

• CK: serial clock

SDI: serial data input (MOSI)

SDO: serial data output (MISO).

The interface is compliant with the SPI standard CPHA = 1 and CPOL = 0 (serial data is sampled on CK falling edge and it is updated on CK rising edge, at the CS falling edge the CK signal must be low) as shown in

Figure 22 .

Figure 22. SPI timings

SD

(Not required for

NOP and read operations) t

SDLCSL

CS t setCS t fCK t lCK t rCK t hCK t

CSHSDH t desCS

CK

SDI

SDO

HiZ t enSDO t setSDI t holSDI

MSB t holSDO

MSB

N-1 t vSDO

N-2

N-1 N-2 t holCS

LSB

LSB t disSDO

MSB

The SPI interface can work up to 5 Mbps and provides the daisy chain feature.

In order to guarantee a safe operation and robustness to electrical noise, the number of rising edges within a CS negative pulse must be multiple of 16, otherwise the communication cycle is ignored and a communication failure is indicated forcing high the SPI_ERR flag.

Any number of the STGAP1BS can be connected in daisy chain, and only 4 lines for the SPI and one for the

SD are required in order to guarantee access to status and configuration registers of each device. An example of daisy chain configuration is shown in

Figure 23 .

In case that several STGAP1BS devices are connected in the SPI link, each of them can be configured in a different way by simply writing the desired data in each configuration and diagnostic register. This allows for example differentiating the configuration for high-side and low-side drivers.

DS11974 - Rev 4 page 31/59

STGAP1BS

CRC protection

Figure 23. SPI daisy chain connection example

Device 1 Device 2 Device N

SD

CS

CK

SDI

SDO

I

S

O

L

A

T

I

O

N

SD

CS

CK

SDI

SDO

O

L

A

T

I

O

I

S

N

SD

CS

CK

SDI

SDO

O

L

A

T

I

O

I

S

N

μC

SD

MOSI

CS

CK

MISO

In case a bootstrap capacitor and a diode are used to generate the VH supply voltage for the high-side drivers, it is recommended to have one dedicated SD line for all of the high- side drivers and another dedicated SD line for all of the low-side drivers. An example of such topology is shown in

Figure 24 .

Figure 24. SPI daisy chain connection example when bootstrap technique is used for high-side drivers

VH

_HS1

VH

VH

_HS2

VH

SD SD

CS

CK

SDI

SDO

L

A

T

I

S

O

I

O

N

C boot _HS1

VL

GNDISO

CS

CK

SDI

SDO

T

I

O

N

O

L

I

S

A C boot

_HS2

VL

GNDISO

VH

_LS

VH

VH

_LS

VH

μC

SD_HS

MOSI

CS

CK

MISO

SD_LS

SD

CS

CK

SDI

SDO

A

T

I

O

N

I

S

O

L

VL

GNDISO

GNDisoGNDiso

SD

CS

CK

SDI

SDO

O

N

T

I

L

A

I

S

O

VL

GNDISO

8.1

CRC protection

All the command and data bytes have to be followed by a CRC code. If the CRC_SPI bit is set high, this code is used to check the data byte is correct, otherwise the CRC byte is ignored. In this case the CRC byte must be transmitted by the host, but its value is unimportant.

A failure on the CRC check causes the respective data byte is ignored and the SPI_ERR flag is set high.

The polynomial generator of the CRC code is X 8 + X 2

+ X + 1 corresponding to the block diagram in Figure 25

.

DS11974 - Rev 4 page 32/59

DS11974 - Rev 4

STGAP1BS

CRC protection

Figure 25. Block diagram of the CRC generator

Message

(from MSb to LSb)

X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0

The host must transmit to the device the inverted CRC code computed using the following procedure:

•

•

•

Initialize CRC to all 1

Start the calculation from the most significant bit of the message

Invert the CRC result

In case of a WriteReg command, the CRC of the data byte (i.e.: the new register value) must be calculated initializing the computation system to the CRC of the command byte (i.e., the CRC is calculated on a 16-bit message composed by the command + data byte). This way a data byte cannot be accepted as a command byte

and vice-versa. Some examples are listed in Table 11

.

The device always transmits a response byte followed by a CRC computed using the same polynomial generator

(X 8 + X 2 + X + 1). The CRC byte transmitted by the device is not inverted.

If no response is required, the word returned by the device has no meaning and it should be discarded. Some

examples are listed in Table 12

.

Command

StopConfig

WriteReg(CFG1, 0x20)

WriteReg(CFG5, 0x06)

ResetStatus

ReadReg(CFG3)

Table 11. CRC byte examples (from host to device)

Command byte

0x3A

0x8C

0x99

0xD0

0xBE

Command CRC

0xAA

0xA1

0xCA

0x32

0x3F

Data byte

N.A.

0x20

0x06

N.A.

N.A.

Data CRC

N.A.

0x82

0x66

N.A.

N.A.

Table 12. CRC byte examples (from device to host)

Data byte

0x00

0xEA

0xF5

0x2A

Data CRC

0xF3

0x6B

0x36

0x25 page 33/59

STGAP1BS

Programming manual

9

Programming manual

9.1

9.1.1

SPI commands

Table 13. SPI commands

Command mnemonic

StartConfig

Command value Action

0 0 1 0 1 0 1 0 Device configuration start

StopConfig

NOP

WriteReg

0 0 1 1 1 0 1 0 Device configuration/check completed

0 0 0 0 0 0 0 0 No operation

1 0 0 A A A A A Write AAAAA register

-

Notes

Enter CFG mode SD low only

Leave CFG mode SD low only

CFG mode only

ReadReg

ResetStatus

GlobalReset

Sleep

1 0 1 A A A A A Read AAAAA register

1 1 0 1 0 0 0 0 Reset all the status registers

1 1 1 0 1 0 1 0 Global reset

1 1 1 1 0 1 0 1 Device enters in standby mode

-

SD low only

CFG mode only

SD low only

StartConfig and StopConfig commands

Table 14. StartConfig command synopsis

Byte

To device

1

0010 1010

1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

2

1101 1010

(1)

Table 15. StopConfig command synopsis

Byte

To device

1

0011 1010

1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

2

1010 1010

(1)

Device parameters are configured by writing configuration values in configuration registers (CFGx and

DIAGxCFG), which is only possible by entering in configuration mode.

To switch the device to the configuration mode the StartConfig command must be sent. This command is accepted when the SD line is low only. If the command has been correctly received and interpreted, the IC registers writing is enabled.

The SD pin must be kept low during the whole configuration procedure, which is terminated by the StopConfig command. If the SD pin is raised during the configuration procedure the device immediately quits the configuration mode causing a fault error indicated by the REGERRL and REGERRR bits. In this case all the changes operated on device configuration are undone and the previous configuration is restored.

At the end of the device setup, the StopConfig command has to be sent in order to quit the configuration mode and make all changes effective.

Configuration sequence must be repeated every time the power supply on either side (VDD or VH) is removed and then restored.

•

•

VDD falling below critical value will result in the REGERRL flag being set in status registers after that the proper VDD level is restored.

VH falling below critical value will result in the REGERRR flag being set in status registers.

DS11974 - Rev 4 page 34/59

STGAP1BS

SPI commands

After that all supply voltages are supplied and stable, the configuration process can be executed. The flow chart shown in

Figure 26 is recommended for the configuration. In this way it will be possible to check that the desired

configuration has been correctly stored in the device at the end of the configuration sequence.

Figure 26. STGAP1BS recommended configuration flow

Power ON

VDD, VH, (VL) stabilization

Set SD low

Reset status

Clear STATUS registers through

“Reset Status” SPI command

9.1.2

SD must be low with no glitch/bounces during this phase

Read CFG1-2-3-4-5. DIAG1-2 through appropriate read masks

N

Y

Read status

Read STATUS1-2-3 registers through appropriate read masks

Status OK

Y

N

CONFIGURATION

Set SD high

End of inizialization

WriteReg command

Table 16. WriteReg command synopsis

Byte

To device

1

100A AAAA (1)

2

CCCC CCCC (2)

3

DDDD DDDD

(3)

1. The command byte where AAAAA is the address of the target register.

2. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

3. Data to be written into the target register.

4. The CRC byte of the command and data, if the CRC check is disabled this byte is ignored.

4

KKKK KKKK (4)

The device register can be written through the WriteReg command when the device is set in the configuration mode only (refer to

Section 9.1.1 ), otherwise the write command is ignored and the SPI_ERR flag is forced low.

DS11974 - Rev 4 page 35/59

9.1.3

9.1.4

STGAP1BS

SPI commands

The WriteReg command is followed by the data to be written into the target register. The CRC code following the data is based on both command and data bytes. In this way, in case of communication error, a data byte cannot be decoded as a command and vice-versa (refer to

Section 8.1 ).

ReadReg command

Table 17. ReadReg command synopsis

Byte

To device

From device

1

101A AAAA

0000 0000

(2)

2

CCCC CCCC

0000 0000

(3)

1. Proper time have to be waited in order to allow the device to prepare the data.

2. The command byte where AAAAA is the address of the target register.

3. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

4. The CRC byte of the NOP command.

5. Data read from the target register.

6. The CRC byte of the data.

3

(1)

0000 0000

DDDD DDDD

(5)

4

CCCC CCCC (4)

KKKK KKKK

(6)

All the registers of the device can be read anytime, and this requires two accesses (CS must be asserted LOW and HIGH twice). In the first access the SPI host issues the ReadReg command (including the register address) and the CRC of the first byte, which will be ignored if SPI CRC is not enabled. After the command is received and decoded by the device, the register value and the respective CRC code is prepared for the transmission. The

CRC polynomial used by the device during the transmission is different from the one used by the host, but the

CRC code is not inverted before transmission (refer to Section 8.1

).

The time required to obtain the reading result changes according to the side where the register is located. The reading of a local register (low voltage side) is available in 800 ns. The reading of a remote register (isolated side), if no communication error occurs between the two sides of the device, is available in 30 μs.

After the read result is ready it is stored in the SPI output buffer, and the host MCU will receive it as soon as it will send a new SPI command. Any command can be used for this purpose, including a NOP or the ReadReg command for the next register to be read.

Some status and configuration registers contain a reserved bit whose content is not predictable. In order to clearly identify the content of relevant information, the value read from each register should be masked with the

appropriate masking code (see “Mask code” in Table 23

).

ResetStatus and GlobalReset commands

Table 18. ResetStatus command synopsis

Byte

To device

1

1101 0000

1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

2

0011 0010 (1)

The ResetStatus command is a specific reset command which acts on all status registers releasing all the latched flags. The command is executed only when the SD input is low, otherwise the SPI_ERR flag is forced low.

Table 19. GlobalReset command synopsis

Byte

To device

1

1110 1010

1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

2

1001 0100

(1)

DS11974 - Rev 4 page 36/59

9.1.5

9.1.6

9.2

STGAP1BS

Register and flag descriptions

The GlobalReset command reset all the registers to the default and releases all the failure flag (if latched).

It can be sent when the device is in the configuration mode only, otherwise the command is ignored and the

SPI_ERR flag is forced low.

Sleep command

Table 20. Sleep command synopsis

Byte

To device

1

1111 0101

1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

2

1100 1001

(1)

The CRC byte of the command, if the CRC check is disabled this byte is ignored.

The command forces the device to switch in standby mode within a t sleep

period. The command is executed only when the SD pin in low, if the SD pin is high the command is ignored and the SPI_ERR flag is forced low.

Refer to

Section 6.4

for the description of the standby mode.

NOP command

Table 21. NOP command synopsis

Byte

To device

1

0000 0000

1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.

The command does not modify the device status and does not generate any answer.

2

0000 1100

(1)

Register and flag descriptions

All device features can be configured through a set of 8-bit long registers. There are three different types of registers:

1.

Local registers are located on the low voltage side

2.

Remote registers are located on the isolated side

3.

Shared registers are located both on the low voltage and isolated side and the value of the two copies is kept synchronized.

Name

-

CFG1

CFG2

CFG3

CFG4

CFG5

STATUS1

STATUS2

STATUS3

TEST1

Table 22. Register map

L

L

L

R

R

R

Side (1)

-

L

R

R

Structure

[7] [6] [5] [4]

CRC_SPI UVLOD_EN SD_FLAG DIAG_EN

SENSEth

2LTOth

DESATcur

[3]

-

-

OVLOH

-

-

-

-

-

OVLOL

-

-

-

OVLO_EN UVLOlatch

-

DESAT

-

-

-

-

SENSE

-

UVLOH

-

DTset

VLONth

[2] [1]

DESATth

2LTOtime

INfilter

[0]

2LTO_EN CLAMP_EN DESAT_EN SENSE_EN

GOFFCHK GONCHK

UVLOL

REGERRR

DT_ERR SPI_ERR REGERRL

DESCHK

VHONth

TSD

ASC

OVLOD

SNSCHK

TWN

GATE

UVLOD

RCHK

DS11974 - Rev 4 page 37/59

9.2.1

STGAP1BS

Register and flag descriptions

Name

DIAG1CFG

DIAG2CFG

Side (1)

L

L

1. R: remote (isolated side), L: local (low voltage side).

Structure

DIAG1_7 DIAG1_6 DIAG1_5 DIAG1_4 DIAG1_3 DIAG1_2

DIAG2_7 DIAG2_6 DIAG2_5 DIAG2_4 DIAG2_3 DIAG2_2

DIAG1_1

DIAG2_1

DIAG1_0

DIAG2_0

Name

CFG1

CFG2

CFG3

CFG4

CFG5

STATUS1

STATUS2

STATUS3

TEST1

DIAG1CFG

DIAG2CFG

CFG1 register (low voltage side)

The CFG1 register has the structure of

Table 24 .

Table 23. Registers access

0x02

0x01

0x0A

0x11

0x05

0x06

Address

0x0C

0x1D

0x1E

0x1F

0x19

Mask code

0xFF

0xFF

0xFF

0x3F

0x0F

0xFF

0x07

0x1F

0x1F

0xFF

0xFF

-

-

Default/reset

Bit 7

CRC_SPI

0

Table 24. CFG1 register

Bit 6

UVLOD_EN

0

Bit 5

SD_FLAG

1

Bit 4

DIAG_EN

0

The CRC_SPI bit enables the CRC check on the SPI communication protocol.

Bit 3 Bit 2

DTset

00

Bit 1 Bit 0

INfilter

00

CRC_SPI

0

1

Table 25. CRC enable

SPI communication protocol CRC enable

Disabled

Enabled

The UVLOD_EN bit enables the UVLO protection on VDD supply voltage.

UVLOD_EN

0

1

Table 26. VDD supply voltage UVLO enable

Supply voltage UVLOD enable

Disabled

Enabled

DS11974 - Rev 4 page 38/59

9.2.2

STGAP1BS

Register and flag descriptions

The SD_FLAG bit sets the SD pin functionality according to

Table 27 . When the reset of the failure flags through

the SD pin is enabled, keeping low the SD pin for at least t release

causes all the latched flags of the status registers to be released at the next SD rising edge.

SD_FLAG

0

1

Table 27. SD pin FAULT management

SD pin functionality

SD pin do not reset STATUS registers

SD pin reset STATUS registers

The DIAG_EN bit sets if the IN-/DIAG2 pin works as the input or open drain output according to

Table 28 . Refer to

Section 7.1 for details.

DIAG_EN

0

1

The DTset bits set the deadtime value.

Table 28. IN-/DIAG2 pin functionality

IN-/DIAG2 pin functionality

The IN-/DIAG2 pin work as input

The IN-/DIAG2 pin work as open drain output

DTset [1 ... 0]

0

0

1

1

Table 29. Deadtime

Deadtime value [ns]

0

1

0

1

The INfilter bits set the input deglitch time t deglitch

for the SD, IN- and IN+ pins.

-

Disabled

250

800

1200

1

1

0

0

INfilter [1 ... 0]

0

1

0

1

Table 30. Input deglitch time

Input deglitch time value [ns]

Disabled

160

500

70

CFG2 register (isolated side)

The CFG2 register has the structure of

Table 31 .

-

-

Default/reset

Bit 7

Table 31. CFG2 register

Bit 6

SENSEth

000

Bit 5 Bit 4 Bit 3

DESATcur

00

Bit 2 Bit 1

DESATth

100

Bit 0

The SENSEth bits set the SENSE comparator threshold according to

Table 32 . Refer to

Section 7.8 for details.

DS11974 - Rev 4 page 39/59

9.2.3

STGAP1BS

Register and flag descriptions

0

0

1

1

0

0

1

1

SENSEth [2 ... 0]

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Table 32. SENSE threshold

SENSE threshold value [mV]

100

125

150

175

200

250

300

400

The DESATcurr parameter sets the current sourced by the DESAT pin according to

Table 33 and the DESATth parameter sets the DESAT comparator threshold according to Table 34 . Refer to

Section 7.6 for details.

DESATcur [1 ... 0]

0

0

1

1

Table 33. DESAT current

0

1

0

1

DESAT current value [μA]

250

500

750

1000

0

0

1

0

0

1

1

1

DESATth [2 ... 0]

0

0

1

1

0

0

1

1

0

1

0

0

1

1

0

1

CFG3 register (isolated side)

The CFG3 register has the structure of

Table 35 .

Table 34. DESAT threshold

DESAT threshold value [V]

3

4

5

6

7

8

9

10

-

-

Default/reset

Bit 7

Table 35. CFG3 register

Bit 6

2LTOth

0000

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

2LTOtime

0000

Bit 0

The 2LTOth parameter sets the voltage value which is actively forced during the 2-level turn- off sequence (refer to

Section 7.10

for details).

DS11974 - Rev 4 page 40/59

9.2.4

STGAP1BS

Register and flag descriptions

1

1

1

0

0

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

1

1

1

1

2LTOth [3 ... 0]

0 0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

Table 36. 2LTOth

2LTO threshold value [V]

7.00

7.50

8.00

8.50

9.00

9.50

10.00

10.50

11.00

11.50

12.00

12.50

13.00

13.50

14.00

14.50

The 2LTOtime parameter sets the duration of the 2-level turn-off sequence (refer to Section 7.10

for details). If the 2LTOtime is set to zero, the 2-level turn-off feature is disabled.

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

0

1

1

0

0

0

0

1

1

1

1

2LTOtime [3 ... 0]

0 0

0

0

0

1

1

0

0

1

1

0

1

1

0

1

0

0

1

CFG4 register (isolated side)

The CFG4 register has the structure of

Table 38 .

0

1

0

0

1

0

1

0

1

0

1

1

0

1

0

1

Table 37. 2-level turn-off time value

2-level turn-off time value [μs]

Disabled

0.75

1.00

1.50

2.00

2.50

3.00

3.50

3.75

4.00

4.25

4.50

4.75

5.00

5.25

5.50

DS11974 - Rev 4 page 41/59

9.2.5

STGAP1BS

Register and flag descriptions

-

-

Default/reset

Bit 7

-

-

Bit 6

-

-

Table 38. CFG4 register

Bit 5

OVLO_EN

0

Bit 4

UVLOlatch

0

Bit 3 Bit 2

VLONth

00

Bit 1 Bit 0

VHONth

00

The OVLO_EN bit enables the OVLO protection on the VH and VL power supply according to Table 39

.

OVLO_EN

0

1

Table 39. VH and VL supply voltages OVLO enable

OVLO supply voltage enable

Disabled

Enabled

The UVLOlatch bit sets if the UVLO is latched or not (refer to

Section 7.4 for details).

UVLOlatch

0

1

Table 40. UVLO protection management

UVLO protection management

UVLO protection is not latched

UVLO protection is latched

The VLONth bits set the UVLO threshold on the negative power supply according to Table 41

.

Setting the parameter to zero disables the UVLO protection of the VL supply.

1

1

0

0

VLONth [1 ... 0]

0

1

0

1

Table 41. VL negative supply voltage UVLO threshold

Negative supply voltage UVLO threshold [V]

Disabled

-3

-5

-7

The VHONth bits set the UVLO threshold on the positive power supply according to Table 42

.

Setting the parameter to zero disables the UVLO protection of the VH supply.

0

1

1

0

VHONth [1 ... 0]

0

1

0

1

Table 42. VH positive supply voltage UVLO threshold

Positive supply voltage UVLO threshold [V]

Disabled

10

12

14

CFG5 register (isolated side)

The CFG5 register has the structure of

Table 43 .

DS11974 - Rev 4 page 42/59

9.2.6

STGAP1BS

Register and flag descriptions

-

-

Default/reset

Bit 7 Bit 6

-

-

Table 43. CFG5 register

Bit 5 Bit 4

-

-

Bit 3

2LTO_EN

0

Bit 2

CLAMP_EN

1

Bit 1

DESAT_EN

1

Bit 0

SENSE_EN

0

The 2LTO_EN bit sets when the feature takes place according to

Table 44 . Refer to

Section 7.10

for details.

2LTO_EN

0

1

Table 44. 2LTO mode

2LTO mode

2LTO always active

2LTO active only after a fault event

The 2LTOth bit sets the 2-level turn-off threshold according to

Table 36 and the 2-level turn-off time according to

Table 37 .

The SENSE_EN bit sets if the sense overcurrent function is enabled or not (refer to

Section 7.8

for details).

SENSE_EN

0

1

Table 45. SENSE comparator enabling

SENSE comparator status

SENSE comparator disabled

SENSE comparator enabled

The DESAT_EN bit sets if the desaturation protection is enabled or not (refer to Section 7.6 Section 7.6

for details).

DESAT_EN

0

1

Table 46. DESAT comparator enabling

DESAT comparator status

DESAT comparator disabled

DESAT comparator enabled

Set the CLAMP_EN bit to enable the Miller clamp feature (refer to Section 7.9

for details).

CLAMP_EN

0

1

Table 47. Miller clamp feature enabling

Miller clamp feature status

Miller clamp feature disabled

Miller clamp feature enabled

STATUS1 register (low voltage side)

The STATUS1 is a read only register that reports some device failure flags.

All flags are active high (the high value indicates a failure condition). The STATUS1 register has the structure of

Table 48 .

DS11974 - Rev 4 page 43/59

9.2.7

STGAP1BS

Register and flag descriptions

Table 48. STATUS1 register

-

-

Default (1)

Reset

Bit 7

OVLOH

0

0

Bit 6

OVLOL

0

0

Bit 5

DESAT

0

0

Bit 4

SENSE

0

0

Bit 3

UVLOH

1

0

Bit 2

UVLOL

0

0

Bit 1

TSD

0

0

Bit 0

TWN

0

0

1. Default value of the local copy of the register. The value will be updated according to the actual information from the isolated side. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no failures).

A description of the STATUS1 register bits is provided in Table 49 .

Table 49. STATUS1 register description

Name Bit Fault

OVLOH 7

OVLOL 6

DESAT 5

SENSE 4

VH overvoltage flag.

It is forced high when VH is over OV

VHoff

threshold.

VL overvoltage flag.

It is forced high when VL is over OV

VLoff

threshold.

Desaturation flag.

It is forced high when DESAT pin voltage reaches

V

DESATth

threshold.

Sense flag.

It is forced high when SENSE pin voltage reaches

V

SENSEth

threshold.

UVLOH 3

VH undervoltage flag.

It is forced high when VH is below VHoff threshold.

Latched

Always

Always

Always

Always

When UVLOlatch is high only

Force

“safe state”

Yes

Yes

Yes

Yes

UVLOL 2

VL undervoltage flag.

It is forced high when VL is over VLoff threshold.

TSD 1

TWN 0

Thermal shutdown protection flag.

It is forced high when overtemperature shutdown threshold is reached.

Thermal warning flag.

It is forced high when overtemperature shutdown threshold is reached.

When

UVLOlatchis high only

No (hysteresis)

No (hysteresis)

Yes

No

Note

-

-

-

-

-

-

Yes

Yes

If not latched

(UVLOlatch low)

UVLOH returns low when VH is over VH on threshold.

If not latched

(UVLOlatch low)

UVLOL returns low when VL is below VL on threshold.

STATUS2 register (low voltage side)

The STATUS2 is a read only register. The STATUS2 register has the structure of

Table 50 .

-

-

Default (1)

Bit 7

x

Bit 6

x

Table 50. STATUS2 register

Bit 5

x

Bit 4

x

Bit 3

x

Bit 2

REGERRR

1

Bit 1

ASC

0

Bit 0

GATE

0

DS11974 - Rev 4 page 44/59

9.2.8

STGAP1BS

Register and flag descriptions

-

Reset

Bit 7 x

Bit 6 x

Bit 5 x

Bit 4 x

Bit 3 x

Bit 2

0

Bit 1

0

Bit 0

0

1. Default value of the local copy of the register. The value will be updated according to the actual information from the isolated side. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no failures).

A description of the STATUS2 register bits is provided in Table 51 .

Table 51. STATUS2 register description

Name Bit Fault Latched

Force

“safe state”

REGERRR 2

ASC 1

•

•

•

Register or communication error on isolated side. It is forced high when:

Programming procedure is not correctly performed.

Isolated interface communication fails.

An unexpected register value change occurs in one of the remote registers.

It is also latched at power-up/reset and from Sleep state.

ASC pin status.

When ASC pin is high, the flag reports '1', otherwise it is '0'.

GATE 0

Gate command flag.

Flag is '1' when the requested output status from logic inputs is “ON” and '0' when requested output status is “OFF”.

Always

No

No

Yes

No

No

Note

-

See details in

Section 7.12

This bit is not indicated for real-time feedback of external gate status

(

Section 7.14 )

STATUS3 register (low voltage side)

The STATUS3 is a read only register. The STATUS3 register has the structure of

Table 52 .

Table 52. STATUS3 register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

Default (1)

Reset

x x

x x

x x

DT_ERR

0

0

SPI_ERR

0

0

REGERRL

1

0

OVLOD

0

0

1. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no failures).

UVLOD

1

0

A description of the STATUS3 register bits is provided in Table 53 .

Name Bit

Table 53. STATUS3 register description

Fault

DT_ERR 4

Deadtime error flag.

This bit is forced high when a violation of internal DT is detected.

SPI_ERR 3 SPI communication error flag.

Latched

Force

“safe state”

Always

Always

No

No

Note

See details in

Section 7.2

-

DS11974 - Rev 4 page 45/59

STGAP1BS

Register and flag descriptions

9.2.9

9.2.10

Name Bit Fault

REGERRL 2

OVLOD 1

UVLOD 0

•

•

•

•

It is forced high when the SPI communication fails cause:

Wrong CRC check.

Wrong number of CK rising edges.

Attempt to execute a not-allowed command.

Attempt to read, write or reset at a not- available address.

Register or communication error on low voltage side.

•

•

•

It is forced high when:

Programming procedure is not correctly performed.

Isolated interface communication fails.

An unexpected register value change occurs in one of the remote registers.

It is latched at power-up/reset also.

VDD overvoltage flag.

It is forced high when VDD is over OVVDDoff threshold.

VDD undervoltage flag.

It is forced high when VDD is below VDDon threshold.

It is latched at power-up/reset as well.

TEST1 register (isolated side)

The TEST1 register has the structure of

Table 54 .

Latched

Force

“safe state”

Always Yes

Always Yes

Always Yes

-

-

Default/reset

Bit 7

x

Bit 6

x

Bit 5

x

Table 54. TEST1 register

Bit 4

GOFFCHK

0

Bit 3

GONCHK

0

Setting an one check bit of the register enables the respective check mode.

Bit 2

DESCHK

0

Note

-

-

-

Bit 1

SNSCHK

0

Bit 0

RCHK

0

Bit

RCHK

SNSCHK

DESCHK

GONCHK

GOFFCHK

Table 55. Check mode

Check mode

SENSE resistor

SENSE comparator

DESAT comparator

GON to gate path

GOFF to gate path

DIAG1CFG and DIAG2CFG registers (low voltage side)

The DIAG1CFG register has the structure of

Table 56 .

-

Bit 7

DIAG1_7

Bit 6

DIAG1_6

Table 56. DIAG1CFG register

Bit 5

DIAG1_5

Bit 4

DIAG1_4

Bit 3

DIAG1_3

Bit 2

DIAG1_2

Bit 1

DIAG1_1

Bit 0

DIAG1_0

DS11974 - Rev 4 page 46/59

DS11974 - Rev 4

STGAP1BS

Register and flag descriptions

-

Default/reset

Bit 7

1

Bit 6

1

Bit 5

0

The DIAG2CFG register has the structure of

Table 57 .

Bit 4

1

Bit 3

1

Bit 2

0

Bit 1

1

Bit 0

0

-

-

Default/reset

Bit 7

DIAG2_7

0

Bit 6

DIAG2_6

0

Table 57. DIAG2CFG register

Bit 5

DIAG2_5

0

Bit 4

DIAG2_4

0

Bit 3

DIAG2_3

0

Bit 2

DIAG2_2

0

Bit 1

DIAG2_1

0

Bit 0

DIAG2_0

0

If a bit in the DIAG1CFG register is high, the corresponding fault events turn on the open drain connected to the

DIAG1 pin forcing the output low.

If a bit in the DIAG2CFG register is high and the DIAG_EN bit is high, the corresponding fault events turn on the open drain connected to the DIAG2 pin forcing the output low.

The relationship between the DIAG1CFG and DIAG2CFG register bits and failure events is described in

Table 58 .

DIAGxCFG bit

0

1

2

3

6

7

4

5

Table 58. Relation between DIAGxCFG bits and failure conditions

Failure

Thermal warning

Thermal shutdown

ASC feedback

Desaturation and sense detection

Overvoltage failure

Undervoltage failure

VDD power supply failure

SPI communication error or register failure

Status registers bit

TWN

TSD

ASC, DT_ERR

DESAT, SENSE

OVLOH, OVLOL

UVLOH, UVLOL

UVLOD, OVLOD

SPI_ERR, REGERRL, REGERRR page 47/59

10

STGAP1BS

Typical application diagram

Typical application diagram

Figure 27. Typical application diagram in half-bridge configuration

DS11974 - Rev 4

Refer to

Figure 13 in the dedicated

Section 7.7

for the connection of the VCECLAMP pin.

page 48/59

11

11.1

STGAP1BS

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

SO24W package information

Figure 28. SO24W package outline

D hx45°

B

24 13

SEATING

PLANE

1 12 L e

Table 59. SO24W package mechanical data

Symbol

Dimensions (mm)

-

-

-

1.27

Typ.

-

-

-

-

-

-

-

-

Max.

2.65

0.30

0.51

0.32

15.60

7.60

-

10.65

0.75

1.27

8

0.10

Notes e

H

D

E h

L

K ddd

A

A1

B

C

Min.

2.35

0.10

0.33

0.23

15.20

7.40

0.25

0.40

0

-

-

10.00

-

-

-

-

-

Degrees

-

-

-

-

-

(1)

1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15 mm per side.

DS11974 - Rev 4 page 49/59

Figure 29. SO24W suggested land pattern

STGAP1BS

SO24W package information

DS11974 - Rev 4 page 50/59

STGAP1BS

Ordering information

12

Ordering information

Order code

STGAP1BS

STGAP1BSTR

Table 60. Device summary

Package

SO24W

SO24W

Packing

Tube

Tape and reel

DS11974 - Rev 4 page 51/59

Revision history

Date

06-Oct-2021

Table 61. Document revision history

Version

4

Changes

Cover package updated

STGAP1BS

DS11974 - Rev 4 page 52/59

STGAP1BS

Contents

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1

Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.3

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.1

AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.2

DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6 Logic supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.1

Low voltage section voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2

High voltage section voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.3

Power-up, power-down and “safe state”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.4

Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

7.1

Inputs and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.2

Deadtime and interlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.3

Hardware RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.4

Power supply UVLO and OVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.5

Thermal warning and shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.6

Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.7

V

CE

active clamping protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.8

SENSE overcurrent protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.9

Miller clamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.10

2-level turn-off function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.10.1

2-level turn-off function - Always . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.10.2

2-level turn-off function - Fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.10.3

2-level turn-off function - Never . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DS11974 - Rev 4 page 53/59

STGAP1BS

Contents

7.11

Failure management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.12

Asynchronous stop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.13

Watchdog and echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.14

Security check functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.14.1

Logic inputs to isolated driver path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.14.2

GON to gate path check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.14.3

GOFF to gate path check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.14.4

SENSE comparator check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.14.5

SENSE resistor check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.14.6

DESAT comparator check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.15

Register corruption protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8 SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

8.1

CRC protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

9.1

SPI commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

StartConfig and StopConfig commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

WriteReg command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

ReadReg command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

ResetStatus and GlobalReset commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Sleep command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

NOP command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.2

Register and flag descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

CFG1 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CFG2 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

CFG3 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

CFG4 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

CFG5 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

STATUS1 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.2.7

9.2.8

STATUS2 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

STATUS3 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2.9

TEST1 register (isolated side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2.10

DIAG1CFG and DIAG2CFG registers (low voltage side). . . . . . . . . . . . . . . . . . . . . . . . . . 46

DS11974 - Rev 4 page 54/59

STGAP1BS

Contents

10 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

11 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

11.1

SO24W package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

DS11974 - Rev 4 page 55/59

STGAP1BS

List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Low voltage section 3.3 V voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. High voltage section 3.3 V voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. HW cross conduction prevention in half-bridge configuration with two single gate drivers . . . . . . . . . . . . . . . . 17

Figure 6. Transitions causing the DT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Synchronous control signal edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Control edges signal overlapped, example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Control edges signal overlapped, example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Control edges signal not overlapped and outside DT (direct control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. Example of desaturation protection connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. DESAT protection timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Example of V

CE

active clamping protection connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14. VCECLAMP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 15. Example of SENSE overcurrent protection connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 16. Example of short turn-on pulses when 2LTO occurs at each cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17. Example of short turn-off pulse when 2LTO occurs at each cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 18. Example of operation with 2LTO in “Fault” mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 19. Gate paths check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 20. SENSE comparator and resistor check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 21. DESAT comparator check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 22. SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 23. SPI daisy chain connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 24. SPI daisy chain connection example when bootstrap technique is used for high-side drivers. . . . . . . . . . . . . . 32

Figure 25. Block diagram of the CRC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 26. STGAP1BS recommended configuration flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 27. Typical application diagram in half-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 28. SO24W package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 29. SO24W suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DS11974 - Rev 4 page 56/59

STGAP1BS

List of tables

List of tables

Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 4. Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 5. AC operation electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 6. DC operation electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 7. Isolation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. IEC 60747-5-2 isolation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 9. UL 1577 isolation voltage ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 10. Inputs true table (device NOT in “safe state”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. CRC byte examples (from host to device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 12. CRC byte examples (from device to host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 13. SPI commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. StartConfig command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15. StopConfig command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. WriteReg command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17. ReadReg command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 18. ResetStatus command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 19. GlobalReset command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 20. Sleep command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 21. NOP command synopsis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 22. Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 23. Registers access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 24. CFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 25. CRC enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 26. VDD supply voltage UVLO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 27. SD pin FAULT management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 28. IN-/DIAG2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 29. Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 30. Input deglitch time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 31. CFG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 32. SENSE threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 33. DESAT current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 34. DESAT threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 35. CFG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 36. 2LTOth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 37. 2-level turn-off time value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 38. CFG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 39. VH and VL supply voltages OVLO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 40. UVLO protection management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 41. VL negative supply voltage UVLO threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 42. VH positive supply voltage UVLO threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 43. CFG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 44. 2LTO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 45. SENSE comparator enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 46. DESAT comparator enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 47. Miller clamp feature enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 48. STATUS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 49. STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 50. STATUS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 51. STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 52. STATUS3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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List of tables

Table 53. STATUS3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 54. TEST1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 55. Check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 56. DIAG1CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 57. DIAG2CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 58. Relation between DIAGxCFG bits and failure conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 59. SO24W package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 60. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 61. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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DS11974 - Rev 4 page 59/59