STD150NH02L-1
STD150NH02L
N-channel 24V - 0.003
Ω
- 150A - ClipPAK™ - IPAK
STripFET™ IlI Power MOSFET
General features
Type
STD150NH02L
STD150NH02L-1
V
DSSS
24V
24V
R
DS(on)
<0.0035
Ω
<0.0035
Ω
■
■
■
■
R
DS(on)
* Qg industry’s benchmark
Conduction losses reduced
Switching losses reduced
Low threshold device
I
D
150A
150A
Description
The STD150NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This novel 0.6
µ process utilizes also unique metallization techniques that couple to a
"bondless" assembly technique result in outstanding performance with standard DPAK outline. It is therefore ideal in high performance
DC-DC converter applications where efficiency it to be achieved at very high out currents.
Applications
■ Switching application
1
3
ClipPAK
TM
IPAK
Internal schematic diagram
1
2
3
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Order codes
Part number
STD150NH02LT4
STD150NH02L-1
Marking
D150NH02L
D150NH02L
Package
ClipPAK™
IPAK
Packaging
Tape & reel
Tube
December 2006 Rev 9 1/16 www.st.com
16
5
6
3
4
1
2
Contents
Contents
STD150NH02L
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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STD150NH02L Electrical ratings
Table 1.
Absolute maximum ratings
Symbol Parameter
V spike
(1)
Drain-source voltage rating
V
DS
V
DGR
Drain-source voltage (V
Drain-gate voltage (R
Drain-source voltage
GS
GS
= 0)
= 20K Ω )
V
GS
I
D
I
I
D
DM
(2)
P
TOT
Drain current (continuous) at T
C
= 25°C
Drain current (continuous) at T
C
=100°C
Drain current (pulsed)
Total dissipation at T
C
= 25°C
Derating factor
E
AS
(3)
T stg
Single pulse avalanche energy
Storage temperature
T
J
Max. operating junction temperature
1.
Garanted when external Rg = 4.7
Ω and t f
< t fmax
.
2.
Pulse width limited by safe operating area
3.
Starting T
J
= 25 o
C, I
D
= 75A, V
DD
= 10V
Table 2.
Symbol
R thJC
R thJA
T l
Thermal data
Parameter
Thermal resistance junction-case Max
Thermal resistance junction-ambient Max
Maximum lead temperature for soldering purpose
Value
30
24
24
± 20
150
107
600
125
0.83
500
-55 to 175
Value
1.2
100
275
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Unit
°C/W
°C/W
°C
Unit
A
A
V
A
W
V
V
V
W/°C mJ
°C
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Electrical characteristics STD150NH02L
(T
CASE
=25°C unless otherwise specified)
Table 3.
Symbol
On
(1)
/off states
Parameter Test conditions
V
(BR)DSS
Drain-source breakdown voltage
I
D
= 25mA, V
GS
= 0
I
DSS
Zero gate voltage drain current (V
GS
= 0)
V
DS
= 20V
V
DS
= 20V, T
C
= 125°C
I
GSS
Gate body leakage current
(V
DS
= 0)
V
GS
= ±20V
V
GS(th)
Gate threshold voltage V
DS
= V
GS
, I
D
= 250µA
R
DS(on)
Static drain-source on resistance
V
GS
= 10V, I
D
= 75A
V
GS
= 5V, I
D
= 37.5A
1.
Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Min.
Typ.
Max.
Unit
24
1
10
V
µA
µA
1
±100 nA
1.8
0.003
0.004
0.0035
0.0065
V
Ω
Ω
Table 4.
Symbol
Dynamic
Parameter Test conditions Min.
Typ.
Max.
Unit g fs
(1)
C iss
C oss
C rss
Forward transconductance V
DS
= 10 V
,
I
D
= 75A
Input capacitance
Output capacitance
Reverse transfer capacitance
V
V
DS
GS
= 15V, f = 1 MHz,
= 0
60
4450
1126
141 pF pF pF
Q g
Q gs
Q gd
Q oss
(2)
Q gls
(3)
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 16V, I
D
= 150A
V
GS
= 10V
Output charge V
DS
= 16V, V
GS
= 0V
Third-quadrant gate charge V
DS
< 0V, V
GS
= 10V
69
13
9
27
64
93 nC nC nC nC nC f = 1MHz gate DC Bias = 0
R
G
1.6
Gate input resistance Test signal level = 20mV
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Ω
1.
Pulsed: pulse duration=300µs, duty cycle 1.5%
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3.
Gate charge for synchronous operation
S
4/16
STD150NH02L Electrical characteristics
Table 5.
Symbol t d(on) t r t d(off) t f
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
= 10V, I
D
= 75A,
R
G
= 4.7
Ω, V
GS
= 10V
Figure 13 on page 8
Min.
Typ.
Max.
Unit
14
224
69
40 54 ns ns ns ns
Table 6.
Symbol
Source drain diode
Parameter Test conditions
I
SD
I
SDM
V
SD
(1)
Source-drain current
Source-drain current (pulsed)
I t
Q rr rr
RRM
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 75A, V
GS
= 0
I
SD
= 150A, di/dt = 100A/µs,
V
DD
= 15V, T
J
= 150°C
Figure 15 on page 8
1.
Pulsed: pulse duration=300µs, duty cycle 1.5%
Min Typ.
Max Unit
150
600
1.15
A
A
V
47
58
2.5
ns
µC
A
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Electrical characteristics
Figure 1.
Safe operating area Figure 2.
Thermal impedance
STD150NH02L
Figure 3.
Output characterisics Figure 4.
Transfer characteristics
Figure 5.
Transconductance Figure 6.
Static drain-source on resistance
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STD150NH02L Electrical characteristics
Figure 7.
Gate charge vs gate-source voltage Figure 8.
Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized breakdown voltage vs temperature
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Test circuit
3 Test circuit
Figure 13. Switching times test circuit for resistive load
Figure 14. Gate charge test circuit
STD150NH02L
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped Inductive load test circuit
Figure 17. Unclamped inductive waveform
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STD150NH02L
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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Package mechanical data STD150NH02L
DIM.
G
H
L
L1
L2
C
C2
D
E
B
B2
B3
B5
B6
A
A1
A3
0.45
0.48
6
6.4
4.4
15.9
9
0.8
MIN.
2.2
0.9
0.7
0.64
5.2
TO-251 (IPAK) MECHANICAL DATA
mm
TYP.
0.3
0.8
0.95
0.6
0.6
6.2
6.6
4.6
16.3
9.4
1.2
1
MAX.
2.4
MIN.
0.086
1.1
0.035
1.3 0.027
0.9
5.4
0.85
0.025
0.204
0.017
0.019
0.236
0.252
0.173
0.626
0.354
0.031
inch
TYP.
0.012
0.031
H
0.037
0.023
0.023
0.244
0.260
0.181
0.641
0.370
0.047
0.039
MAX.
0.094
0.043
0.051
0.031
0.212
0.033
D
L
L2
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L1
0068771-E
10/16
STD150NH02L Package mechanical data
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Packaging mechanical data
5 Packaging mechanical data
DPAK FOOTPRINT
STD150NH02L
12/16
All dimensions are in millimeters
TAPE MECHANICAL DATA mm inch
DIM.
MIN.
MAX.
MIN.
MAX.
P1
P2
R
W
A0 6.8
7 0.267 0.275
B0 10.4
10.6
0.409 0.417
B1 12.1
0.476
D
D1
1.5
1.5
1.6
0.059 0.063
0.059
E
F
1.65
1.85
0.065 0.073
7.6
0.291 0.299
K0 2.55
2.75
0.100 0.108
3.9
7.9
4.1
0.153 0.161
8.1
0.311
0.319
1.9
2.1
0.075 0.082
40 1.574
15.7
16.3
0.618
0.641
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA mm inch
DIM.
MIN.
MAX.
MIN.
MAX.
A
B
N
T
C
D
G
330 12.992
1.5
0.059
12.8
13.2
0.504
0.520
20.2
0.795
16.4
18.4
0.645
0.724
50 1.968
22.4
0.881
BASE QTY
2500
BULK QTY
2500
STD150NH02L Buck converter - power losses estimation
Appendix A Buck converter - power losses estimation
Figure 18.
Buck converter: power losses estimation
●
●
●
●
●
●
●
●
●
The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature.
The low side (SW2) device requires:
Very low R
DS(on)
to reduce conduction losses
Small Qgls to reduce the gate charge losses
Small Coss to reduce losses due to output capacitance
Small Qrr to reduce losses on SW1 during its turn-on
The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon;
The high side (SW1) device requires:
Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate
Small Qg to have a faster commutation and to reduce gate charge losses ●
● Low R
DS(on)
to reduce the conduction losses.
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Buck converter - power losses estimation STD150NH02L
Table 7.
Power losses calculation
High side switching (SW1) Low side switch (SW2)
Pconduction R
DS(on)SW1
* I 2
L
*
δ
Pswitching
Recovery
(1)
Pdiode
Conductio n
V in
* (Q gsth(SW1)
+
Q gd(SW1)
) * f *
I
L
I g
Not applicable
Not applicable
R
DS(on)SW2
* I 2
L
* ( 1
− δ
)
Zero Voltage Switching
V in
* Q rr(SW2)
* f
V f(SW2)
* I
L
* t deadtime
* f
Pgate(Q
G
) Q g(SW1)
* V gg
* f Q gls(SW2)
* V gg
* f
P
Qoss
1.
Dissipated by SW1 during turn-on
V in
* Q oss(SW1)
2
* f V in
* Q oss(SW2)
2
* f
Table 8.
Paramiters meaning
Parameter Meaning d
Q gsth
Q gls
Pconduction
Pswitching
Pdiode
Duty-cycle
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Pgate
P
Qoss
Gate drive losses
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STD150NH02L
Table 9.
Date
Revision history
Revision
09-Sep-2004
21-Jun-2005
28-Jul-2006
20-Dec-2006
6
7
8
9
Changes
Preliminary data
Complete version with curves
The document has been reformatted
Typo mistake on Table 3.
Revision history
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STD150NH02L
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