STMicroelectronics STNRG012 Datasheet
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STNRG012
Datasheet
Digital combo multi-mode PFC and time-shift LLC resonant controller for AC and
DC input line
Product status link
STNRG012
Product label
Features
• Digital combo multi-mode PFC + time-shift LLC resonant half-bridge controller
• Management of both AC and DC input
• Input voltage range up to 305 VAC
• On-board 800 V start-up circuit, line sense
• Enhanced fixed-on-time multi-mode TM PFC controller with input voltage feedforward, new thd optimizer and frequency limitation
• Complete set of PFC protections
• Time-shift control of resonant half-bridge
• Brownout protection
• Complete set of half-bridge protections
• S020 package
Application
• Street lighting
• Home lighting
• Industrial
Description
The STNRG012 embodies a multi-mode (Transition-Mode and DCM) PFC controller, a high-voltage double-ended controller for LLC resonant half-bridge, an 800 V-rated start-up generator and a sophisticated digital engine that manage optimal operation of three blocks.
The STNRG012 manages both input line AC or DC.
The device comes in a 20-pin SO package and offers an advanced solution for power-factor-corrected high-efficiency converters supposed to comply with the most stringent energy saving regulations.
The power system and the control algorithms are managed by an 8 bit core with dedicated fast peripherals (SMED). Optimized digital algorithms together with HW analog IPs are implemented to guarantee very high performance, BOM optimization and robustness.
The digital algorithms are stored in an internal ROM memory and all key application parameters can be stored into a device’s NVM memory during production phase, allowing wide configurability and calibration.
The device can also externally communicate through a 2-pin UART, allowing monitor function, black box storing into an external flash and software patch upload from the external flash.
DS13643 - Rev 1 - February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Block diagram
Figure 1. Block Diagram
STNRG012
Block diagram
DS13643 - Rev 1 page 2/34
2
Pin connection
Figure 2. Pin connection (top view)
STNRG012
Pin connection
DS13643 - Rev 1 page 3/34
3
STNRG012
Absolute maximum ratings and thermal data
Absolute maximum ratings and thermal data
V
LVG
V
VCORE
I
PFC_CS
,
I
LLC_CS
,
I
PFC_ZCD
,
V
PFC_CS
,
V
LLC_CS
,
V
PFC_ZCD
V
PFC_FB
,
V
LLC_FB
V
RX
V
TX
Symbol
V
AC
V
BOOT
V
FGND d
VFGND /dt
V
HVG
V
VCC
Pin
VAC
BOOT
FGND
FGND
HVG
VCC
LVG,
PFC_GD
VCORE
PFC_CS,
LLC_CS,
PFC_ZCD
Table 1. Absolute maximum ratings
Parameter
Voltage range
Floating supply voltage, referred to GND
Half-bridge node voltage
Floating ground max. slew rate
HVG voltage
IC supply voltage
Voltage range
Voltage range
Clamped source current
(pin voltage: < 0V, self-limited)
Value
-1 to 800
-0.3 to 600 + VCC
-3 up to a value included in the range
BOOT - VCC and BOOT +0.3
50
FGND -0.3 to BOOT +0.3
-0.3 to 19
-0.3 to VCC
-0.3 to 5.5
2
PFC_CS,
LLC_CS,
PFC_ZCD
PFC_FB.
LLC_FB
RX
TX
Positive voltage range
Voltage range
Voltage range
Voltage range
VCORE+0.3
-0.3 to VCORE+0.3
-0.3 to VCORE+0.3
-0.3Vto VCORE+0.3
Unit
V
V
V
V/ns
V
V
V
V mA
V
V
V
V
Symbol
Rth j-amb
Jedec 1s0p
Rth j-amb
Jedec 2s2p
Tj
Tstg
Table 2. Thermal data
Parameter
Max. thermal resistance, junction-to-ambient,
Jedec 1s0p
Max. thermal resistance, junction-to-ambient,
Jedec 2s2p
Junction temperature operating range
Storage temperature
Value
120
Unit
°C/W
65
-40 to 150
-55 to 150
°C/W
°C
°C
DS13643 - Rev 1 page 4/34
STNRG012
Absolute maximum ratings and thermal data
Figure 3. Dynamic thermal resistance, junction-to-ambient
DS13643 - Rev 1 page 5/34
4
Detailed block diagram
Figure 4. Detailed block diagram
STNRG012
Detailed block diagram
DS13643 - Rev 1 page 6/34
5
STNRG012
Pin function
Pin function
16
17
13
14
15
5
6
7
8
N.
1
2
3
4
9
10
11
12
Name
BOOT
HVG
FGND
N.C.
LVG
TX
RX
LLC_CS
LLC_AUX
LLC_FB
PFC_ZCD
PFC_CS
PFC_FB
VCORE
SGND
PGND
PFC_GD
Table 3. Pin function detailed description
Function
High-side gate-drive floating supply voltage.
The bootstrap capacitor is connected between this pin and FGND.
A fast diode has to be connected from this pin and VCC to guarantee recharge of the bootstrap capacitor.
High-side gate-drive output.
The driver is capable of 0.5 A source and 0.75 A sink peak current (minimum values) to drive the upper MOSFET of the half-bridge leg.
A resistor internally connected to FGND ensures that the pin is never floating.
High-side gate-drive floating ground.
It is the return path for the high-side gate-drive current.
Lay out carefully the connection of this pin to avoid too large spikes below ground.
High-voltage spacer.
The pin is not internally connected to isolate the high-voltage section and ease compliance with safety regulations (creepage distance) on the PCB.
Low-side gate-drive output.
The driver is capable of 0.5 A source and 0.75 A sink peak current (minimum values) to drive the lower MOSFET of the half-bridge leg.
The pin is actively pulled to GND during UVLO.
TX pin for UART/I2C interface
RX pin for UART/I2C interface
LLC tank current sensing input. A voltage proportional to the tank current (usually obtained with a capacitive divider) has to be applied to this pin.
The information is used for zero-crossing detection (required by time-shift algorithm), the first and second level OCP.
LLC_AUX is connected to a divider sensing the auxiliary voltage from the LLC transformer. The
LLC OVP detection is active on this pin.
The voltage from this pin is used as the LLC feedback voltage. It has to be connected to the feedback phototransistor collector and a pull-up resistor to VCORE.
PFC ZCD input, connected to the PFC AUX winding through a resistor divider detecting the PFC inductor demagnetization.
Current sense input for PFC.
The current flowing in the MOSFET is sensed through a resistor, and the resulting voltage is applied to this pin.
After GD turns on, a first voltage threshold cross allows enhanced COT control implementation. A second level can be detected for overcurrent protection.
Input for PFC output voltage. It is used for closing the PFC loop and OVP protection. It has to be connected with a voltage divider to the bulk capacitor.
Internal VCORE bypass capacitor connection.
Signal ground. Reference ground for analog signals.
Power ground. Current return for the PFC gate-driver and the low-side gate-driver of the halfbridge. Keep the PCB trace that goes from this pin to the sources of the PFC and the low-side
MOSFETs separate from the trace that collects the grounding of the bias components.
PFC gate-driver output.
DS13643 - Rev 1 page 7/34
N.
18
19
20
STNRG012
Pin function
Name
VCC
N.C.
VAC
Function
The output stage is able to drive power MOSFETs, it is capable of 0.7 A source current and 0.8 A sink current (minimum values).
Supply voltage of both the signal part of the IC and the gate-drivers. A bypass capacitor to GND is necessary to sustain the IC during startup and low power modes.
The voltage on the pin is internally clamped to protect the internal circuits from temporary excessive supply voltages.
The pin is not internally connected to isolate the high-voltage section and ease compliance with safety regulations (creepage distance) on the PCB.
High-voltage startup generator input.
The pin has to be connected directly to the mains voltage through two dedicated diodes. If the voltage on the pin is higher than 40 V, an internal current source charges the capacitor connected between the pin VCC and GND until the voltage on the VCC pin reaches the startup threshold.
Normally, the generator is re-enabled when the voltage on the VCC pin falls below the UVLO threshold.
The pin is also used as the line voltage sensing input.
This pin is internally connected to a 20 MΩ resistor divider. It is used for all line sense related functions: the brownout, input voltage feed-forward, line synchronization.
DS13643 - Rev 1 page 8/34
6
STNRG012
Electrical characteristics
Electrical characteristics
(T j
= -40°C to +125°C,Vcc = V
BOOT
= 15 V,C
HVG
= C
LVG
= C
GD_PFC
= 1 nF; unless otherwise specified)
Table 4. Electrical characteristics
Min.
Symbol
SUPPLY VOLTAGE
Vccz
Vcc
Vcc
On
Parameter
V cc clamp
Operating range
Processing turnon threshold
V
Vcc
Vcc ccOff
H ys
CoreOn
CoreOff
Processing turnoff threshold
Hysteresis
VCC threshold for
VCore turn-on
VCC threshold for
VCore turn-off
Test Condition
After turn-on
Voltage falling
Voltage falling
VCore Operating range
SUPPLY CURRENT
I
VCCS
Quiescent current during sleep (BM)
I
I
VAC_on vcc_charge
ON-state input current
ON-state VCC charge current
I source
0 to 1 mA
T 25°C
I vCCQ
Operating supply current @ f sw
=
50 kHz, C = 1 nF,
VCC = 12 V
PFC and LLC off
PFC driver only (during pfc ss)
All drivers
HIGH-VOLTAGE START-UP GENERATOR
V
AC_BR
Breakdown voltage
I
HV
< 50 µA
VCC > VCC
On
V
VAC
> 40 V
Vcc < 0.8 V
V
VAC
> 40 V
0.8 V < Vcc < Vcc
CoreOn
V
VAC
> 100 V
Vcc
CoreOn
< Vcc < 14 V
V
VAC
> 100 V
14 V < Vcc < Vcc
_on
40 V < V
VAC
< 100 V
Vcc
CoreOn
< Vcc < 14 V
40 V < V
VAC
< 100 V
14 V < Vcc < Vcc on
V
VAC
> 40 V
Vcc < 0.8 V
V
VAC
> 40 V
0.8 V < Vcc < Vcc
CoreOn
19
9.5
16
7.9
-
-
-
4.75
-
-
-
-
800
-
-
-
-
-
-
-0.5
-3.5
Typ.
-
1
6
6
4
20
10
-0.75
-5
0.5
18
20
22
8.7
8.3
8
-
-
17
7
-
Max.
Unit
-
-
-
-
-
-
9.4
-
-
-
19
18
-
5.25
-
-
-
-
-
-1.3
-8 mA
V
V
V
V
V
V
V mA mA
V mA
DS13643 - Rev 1 page 9/34
DS13643 - Rev 1
I
Symbol vcc_charge
Parameter
ON-state VCC charge current
Test Condition
V
VAC
> 100 V
Vcc
CoreOn
< Vcc < 14 V
V
VAC
> 100 V
14 V < Vcc < Vcc on
40 V < V
VAC
< 100 V
Vcc
CoreOn
< Vcc < 14 V
40 V < V
VAC
< 100 V
14 V < Vcc < Vcc on
I
I
VAC_off
VAC_HV_SINK
OFF-state VAC input current
VAC reading improvement current
V
VAC
= 400 V, Vcc > Vcc
V
VAC
= 100 V on
PFC - GATE DRIVER
V
OL
Output low voltage
I sink
= 100 mA
V
OH
Output high voltage
I source
= -10 mA
VCC = 10 V,
VCC = 18 V
I srcpk
Peak source current
Cgate = 4.7 nF
I snkpk t f t r
Peak sink current
Voltage fall time
Voltage rise time
Cgate = 4.7 nF
PFC
_uvlo
UVLO saturation
Vcc = 0 to Vcc on mA
, I sink
= 1
LOW-SIDE GATE DRIVER (voltages referred to GND)
V
OL
Output low voltage
I sink
= 100 mA
V
OH
Output high voltage
I source
= 10 mA
Vcc = 10 V
I srcpk
Peak source current
Cgate = 4.7 nF
I snkpk t f t r
Peak sink current
Voltage fall time
Voltage rise time
LVG
_uvlo
UVLO saturation
Vcc = 0 to Vcc on
, I sink
= 1 mA
HIGH-SIDE GATE DRIVER (voltages referred to FGND)
V
OL
Output low voltage
I
Vcc = 18 V sink
= 100 mA
V
OH
Output high voltage
I source
= 10 mA
VBOOT = 10 V,
VBOOT = 18 V
Min.
-
-
-
-
-
-
-
9.85
17.9
-
-
9.85
17.85
-
9.85
17.85
-0.7
0.8
-
-
-0.5
0.75
-
-
-
-
9.9
17.9
-0.8
1.2
25
40
0.9
-
9.95
17.95
-1.1
1.3
25
30
0.9
-
9.9
17.9
-18
-8
20
100
Typ.
-5
-3.5
STNRG012
Electrical characteristics
-
40
-
Max.
-
Unit
mA
-
µA
µA
0.7
-
-
-
-
1.15
-
-
V
V
A
A ns ns
V
0.7
-
-
-
-
1.15
-
-
V
V
A
A ns ns
V
0.7
-
-
V
V page 10/34
DS13643 - Rev 1
Symbol
I srcpk
Parameter
Peak source current
Peak sink current I snkpk t f t r
Voltage fall time
Voltage rise time
HSGD
I
_pdw
FGND
HSGD-COMM pull-down
Current from
VBOOT to FGND
BROWN IN/OUT
BI
TH
BO
BIBO_H
BO
_mask
H yst
Brownout time
Overtemperature (by design)
OTP_TH TH
OTP_H H yst
CK
F ck
ADC
ADC
_res
FSR
F
DNL ck_adc
Ck run mode
Resolution
Conversion range
Differential non linearity
Clock frequency
T s
T c
Sampling time
Total conversion time (sampling included)
COMPARATORS
PFC_CS
RECOT
TH RISE (DAC
6bit)
PFC_CS OC1
PFC_CS OC2
HYST
TH RISE
TH FALL
TH RISE
TH FALL
TH FALLING
(TH_F)
HYST (TH_R)
PFC_FB OVP
LLC_FB
BURST
TH RISING
HSYR
TH RISING
HYST
Test Condition
V
V in
V in
V
V
V in in in boot
= 200 V
Vline rising
Vline falling
T rising
T rising
ADC > 50 mv
ADC > 50 mv
ADC > 50 mv
ADC > 50 mv
ADC > 50 mv
Input pin PFC_CS
Input pin PFC_CS
Input pin PFC_CS
Input pin PFC_ZCD
Input pin PFC_FB
Input pin LLC_FB
Min.
-0.5
0.75
-
-
-
-
130
57
-
-
-
0
-
-
112
5.25
60
10
-
±1.5
15
7
18
114
108
6
77
140
-30
Typ.
-0.8
1.2
25
40
25
1.5
FSR = 125
STEP = 1.95
5
500
450
900
850
0/50/100/200
210/110
/310/
TH_F +10
2.33
75
0.75/1/1.25
5/10
STNRG012
Electrical characteristics
Max.
-
-
-
-
-
-
Unit
A
A ns ns kΩ
µA
116
6.75
V
V
V ms
150 C
C
63.7
MHz
-
-
-
2.5
-
bit
V lsb
MHz
Adc Ck cycles
Adc Ck cycles mV
V mV
V mV mV mV mV page 11/34
Symbol
LLC_FB
SHUTDOWN
LLC_AUX OVP
LLC_AUX Ext
BM.
LINE SURGE
Parameter
TH RISING
TH FALLING
TH RISE
TH FALL
TH RISING
TH FALLING
TH RISING
TH FALLING
Test Condition
Input pin LLC_FB
Input pin LLC_AUX
Input pin LLC_AUX
Input pin VAC
Min.
LLC_OC1
TH RISING (DAC
5bit)
Input pin LLC_CS
LLC_OCP2
HYST
TH RISING
TH FALLING
Input pin LLC_CS
1. Parameters tracking each other.
2. Guaranteed by design, not production tested.
3. Thresholds referred only to AC input line.
4. Thresholds and hysteresis are programmed by the software in use.
5. The selection for TH_R = 110 mV is not allowed if TH_F = 200 mV.
Typ.
145
125
2.5
2.4
0.9
0.8
430
410
FSR = 500
STEP = 15.6
20
700
650
STNRG012
Electrical characteristics
Max.
Unit mV
V
V
V mV mV
DS13643 - Rev 1 page 12/34
7
Typical application schematic
Figure 5. Typical application schematic (part 1)
STNRG012
Typical application schematic
DS13643 - Rev 1 page 13/34
Figure 6. Typical application schematic (part 2)
STNRG012
Typical application schematic
DS13643 - Rev 1 page 14/34
8
STNRG012
Architecture
Architecture
The PFC and LLC external MOSFETs gates are managed by the “State Machine Event Driven” (SMEDs): 2 for
PFC (PFC SMEDs) and 2 for LLC (LLC SMEDs).
The SMEDs are programmable state machine driven by events:
1.
External events
2.
Analog comparators outputs
3.
Power manager generated events (protections)
4.
Internal events
•
•
5.
Timers events
PFC SMEDs
Inputs events: PFC RECOT, PFC OC1, PFC ZCD
Outputs: PFC_GD
LLC SMEDs
• Inputs events: LLC ZCD
• Outputs: LVG, HVG
•
•
•
•
The μP subsystem manages dynamically the control loop.
• Analog comparators thresholds setting
SMED configuration
SMED timers
ADC scheduler
Interrupt management
The multichannel ADC is controlled by a programmable event driven scheduler: sampling sequence can be configured and every sample can be triggered by a specific SMED state occurrence and an internal timer value.
Different priorities can be programmed to allow fast sampling for real time control and slow sampling for state control.
The scheduler can be programmed to generate interrupts after completion of selectable conversions.
A dedicated AC line monitor easily follows the AC line providing system triggers.
The uP reads data from the ADC and performs the loop calculation with the support of a dedicated 16-b x 16-b multiplier and a 32-b accumulator unit.
A Power management and burst-mode machine manages the system power state in order to have very low idle consumption and fast activity restart during the burst-mode operation.
Hard protections are managed with a very low propagation delay; the protection enable and the latched/not latched response are programmable. If not specified, the duration of autorestart timer for not latched response is configurable by one NVM parameter.
The power manager controls also the brown-in/out, VCC charge/discharge and AC monitor.
A Watchdog resets the system in case of missed µP signal for a long time.
•
•
A communication peripheral allows serial communication at startup and during the normal operation for:
• External memory communication for
•
– Black box external recording
– Patch SW upload
Monitoring
Internal memory R/W and NVM management
Test mode
DS13643 - Rev 1 page 15/34
9
9.1
9.2
9.2.1
STNRG012
Functional description
Functional description
The main functions are:
•
•
•
•
•
•
•
HV startup and VCC management
Line monitor and protection
Drivers
PFC control and fault management
Resonant HB control and fault management
Power management
Communication and configuration
HV startup and VCC management
The VAC pin voltage can be both:
• a rectified sine wave at 100 Hz/120 Hz
• a DC voltage
The VAC pin is the device supply at the startup.
At the VAC pin a HV DMOS is internally connected to charge the capacitor connected to the VCC pin.
From the VCC pin an internal LDO provides the 5 V VCore for analog and digital circuitry; the digital section is supplied by the internal LDO from the VCORE pin.
At startup, from the HV DMOS the capacitor connected to the VCC pin is charged to provide the power supply to the whole device; then the HV DMOS is turned off.
The VCC pin starts sourcing current to the connected capacitor after about 15 V VAC pin voltage.
The VCC capacitor charge current is limited to 0.75 mA (typ.) during the first charge phase to limit the temperature increase in case the VCC pin is short-circuited at startup. After the VCC pin voltage is above 0.8 V, the charging current rises to 5 mA (typ.).
VCORE pin voltage rises when the VCC pin crosses 8 V (Vcc
CoreOn
). There is a VCORE overload protection that limits the VCC charging current below 1.3 mA in case the VCORE pin is short-circuited at startup. Then the VCC capacitor charge continues with an average current higher than 6 mA: the current is increased during the time the
VAC pin voltage is below 100 V (see Electrical characteristics table, parameter I vcc_charge
).
Once the VCC pin crosses the 17 V, Vcc
On
rising threshold the HV DMOS turns off and the whole device starts working: the uP boots.
If the VCC pin goes below the 8.7 V, Vcc
Off
DMOS turns on again.
falling threshold (UVLO threshold) the uP stops working and the HV
If the VCC pin falls below 7 V (Vcc
CoreOff
) the device stops working and the capacitor connected to the VCORE pin discharges. The VCC pin can rise again only after the voltage on the VCORE pin falls below 1 V.
The worst case average charging current from the 0.8 V to the Vcc on
threshold is estimated in 4.6 mA (in case the mains voltage is 115 Vac - 60 Hz) and 4.1 mA (in case the mains voltage is 230 Vac - 50 Hz).
AC line monitor and protection
•
•
A HV voltage divider is internally connected to the VAC pin to generate Vline_sense for the input line monitoring and protection:
•
Brown-in/out
Line synchronization
Line monitor for PFC control
Brown in/out
Brown-in and brownout functions are implemented based on the Vline_sense information.
DS13643 - Rev 1 page 16/34
9.2.2
9.2.3
9.2.4
9.3
9.4
9.4.1
STNRG012
Gate drivers
The peak, in case of VAC voltage, or its value, in case of VDC voltage, is monitored to enable and disable the
PFC. The PFC is enabled when the input pin voltage crosses the brown-in threshold. The PFC is disabled after
77 ms (typ.) the VAC pin has gone below the brownout threshold.
Please consider that the brownout threshold and hysteresis values are guaranteed for AC input only.
In order to improve AC line reading and avoid false brown-in, the HV DMOS is turned on sinking IXCD current for 3 ms in case of brownout. In case the device turns off for brownout, only after 100 ms are the turning-on conditions checked again.
This function can be enabled / disabled through the dedicated NVM bit.
Line synchronization
A dedicated digital peripheral manages the PFC synchronization with the AC line sine wave.
In order to improve AC line reading and synchronization, the HV DMOS is turned on sinking IVAC_HV_SINK current at startup. This function can be enabled / disabled through the dedicated NVM bit.
In case the input line switches from AC to DC the device simulates the line synchronization maintaining the AC input line frequency.
In case the input line is DC voltage at the startup, the device emulates the line synchronization as 60 Hz input line
(i.e. half period of about 8.3 ms).
Line monitor for PFC control
A 20 MΩ voltage divider for the AC line monitor is internally connected from the VAC pin to GND.
Vline surge stop
A surge can be detected on the VAC pin (430 V).
During the surge the PFC activity is stopped for one half-cycle.
If a line surge is detected during the PFC soft-start, the system shuts down with a not latched fault.
The surge protection can be enabled / disabled through the dedicated NVM bit.
Gate drivers
The HVG and LVG are matched drivers. Deadtimes are programmable by the user.
During the burst-mode sleep phase, the HS BOOT capacitor discharges. The burst packets always start with an
LVG pulse to recharge the bootstrap capacitor. A fast external bootstrap diode is necessary.
PFC control and fault management
PFC resources
Pin name
Table 5. PFC related pins
Description
PFC_CS PFC MOSFET current sense
Level
0-125 mV
500 mV
900 mV
Function
6-bit ramp enhanced
COT feature
OCP1
OCP2 Fault
PFC_ZCD
PFC_FB
VAC
PFC_GD
PFC auxiliary connection for ZCD detection
Reading for PFC Vout estimation
Mains line voltage reading
PFC MOSFET gate driver
ADC, 10 bit
ADC, 10 bit
DS13643 - Rev 1 page 17/34
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.5
STNRG012
PFC algorithm
Vin reading
Input line voltage peak (Vin) reading on the VAC pin by the ADC at the AC line peak.
In case a DC is applied, the Vin is read each 8.3 ms if the device starts with a DC input. Otherwise, the sampling period depends on the last AC applied before switching to DC.
PFC output voltage feedback reading
PFC output voltage reading on the PFC_FB pin by the ADC.
PFC OVP comparator
The PFC OVP comparator sets the limit for the PFC output voltage.
It monitors the PFC_FB pin with respect to a fixed 2.33 V threshold.
PFC RECOT comparator
The PFC RECOT comparator implements the TON adjustment for the ramp enhanced constant on-time (RECOT) control.
It monitors the PFC_CS pin with respect to a programmable threshold. Its output communicates to the PFC
SMED.
The new THD optimizer is based on this comparator.
PFC OC1 comparator
The PFC OC1 comparator sets the limit for the operational maximum allowed peak current into the PFC
MOSFET. If the OC1 threshold is hit the PFC_GD is turned off. This protection works cycle by cycle. It monitors the PFC_CS pin with respect to a fixed 500 mV threshold. Its output communicates to the PFC SMED.
PFC OC2 comparator
The PFC OC2 comparator sets a HW limit for the current flowing into the PFC MOSFET: it triggers the OCP fault.
It monitors the PFC_CS pin with respect to a fixed 900 mV threshold.
PFC ZCD
The PFC ZCD comparator performs the zero cross detection to implement the soft switching of the PFC
MOSFET.
It monitors the PFC_ZCD pin with respect to two programmable rising and falling thresholds.
Its output communicates to the PFC SMED.
Please consider that the PFC ZCD feedback disconnection is not implemented.
PFC state machine event driven (SMED)
The PFC high frequency operations are managed by a programmable 8-state ”State Machine Event Driven” (2 coupled 4-state SMEDs).
The SMED controls the PFC MOSFET based on the PFC comparators output and internally controlled counters.
It generates also the comparators' enable signals. It works at 60 MHz.
PFC algorithm
The PFC operates based on a multi-mode scheme.
A constant on-time (COT) control is implemented; TON is calculated from the PFC feedback and the measured
Vin (the peak in case of a VAC, its value in case of a VDC).
T
ON
is calculated and updated at the line cycle valley in case of VAC input, otherwise the system executes the
TON calculation each 8.3 ms (in case the device starts with DC input).
Based on the working PFC's operating state variables, the working mode is changed to optimize the overall efficiency.
DS13643 - Rev 1 page 18/34
9.5.1
9.5.2
STNRG012
PFC protections
The device includes an automatic bulk voltage drop management: during running operation, in case the PFC_FB pin is below 31 LSB with respect to the target, the device boosts the PFC output changing automatically the control loop parameters (only during the management of the drop).
Ramp enhanced COT improved (patented)
The PFC control is based on the constant on-time scheme, with a proprietary improved algorithm: the calculated
TON is applied only after the PFC RECOT comparator is triggered to balance the recovery diode energy and the
EMI capacitor current.
The PFC RECOT comparator threshold is adjusted by the core with a 6-bit DAC and allows to apply the programmed base and ramp (defined by user into NVM).
This feature allows improving the total harmonic distortion (THD) and the power factor (PF) of the application.
New THD optimizer (patented)
The device implements the new THD optimizer algorithm that can be enabled/disabled by the NVM. This new
(patented) algorithm is based on the enhanced COT:
The PFC RECOT comparator threshold is adjusted by the core with a 6-bit DAC but, instead of constant threshold, the DAC value depends on both the phase of the AC input line and on the mode of the PFC.
Figure 7. New THD optimizer algorithm example
9.5.3
9.6
9.6.1
The user can fine tune the algorithms by the related NVM parameters.
Operating modes
•
•
The PFC manager changes the operating modes by dynamically reconfiguring the SMEDs, obtaining optimal performances in terms of both efficiency and THD/PF.
•
Transition mode (TM mode)
Valley skipping
Discontinuous mode (DCM)
PFC protections
PFC OVP
The device includes two different PFC OVP protections: hardware (based on PFC_OVP comparator) and software (based on ADC PFC_FB sampling). In both cases, if the PFC OVP protection is triggered during the running state of the PFC, the device turns off the PFC until the next line valley. The HW OVP threshold is fixed, the SW OVP threshold is an NVM parameter.
Please see the PFC_CS disconnection paragraph for information about PFC_OVP and PFC_CS disconnection.
•
•
The device shuts down for PFC_OVP only if all the following three conditions are triggered:
• the PFC_OVP HW comparator is triggered during the PFC startup the feedback disconnection faults are enabled
PFC_CS comparator is not triggered during PFC start-up phase
DS13643 - Rev 1 page 19/34
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
STNRG012
PFC protections
Please consider that in all other cases the device does not enter fault state so the half-bridge input voltage could be higher than the PFC_OVP HW threshold with the output still in regulation.
PFC OCP2
If the PFC OC2 comparator is triggered, the PFC gate is truncated and remains off until the beginning of a new line half cycle. In case the PFC OC2 comparator is triggered for more than a programmable number of consecutive half line cycles, the device enters the OCP2 fault and it is turned off.
The OCP2 fault can be programmed as latched or not latched.
PFC soft-start timeout
If the PFC soft-start is not finished after 1 s the system enters the PFC soft-start timeout fault state and it is turned off. The fault is not latched.
PFC UVP
If the PFC_FB pin is below a programmable threshold for more than about 600 us, the device enters the PFC
UVP fault and it shuts down. The PFC UVP fault is a not latched fault.
In case the LLC is in running state and the PFC UVP is triggered, the not latched timer depends on the related
NVM parameter and could be set to either:
• 100 ms or
• Programmable autorestart timer for not latched fault
In case the PFC UVP is triggered and the LLC is not in running state (i.e. soft-start or ACP management state), the duration of not latched timer is set to the programmable autorestart timer for not latched fault.
PFC_FB disconnection
It could be enabled/disabled by NVM parameter.
If the PFC_FB is stuck low the system enters the PFC_FB disconnection fault state (latched) and it is turned off.
PFC_CS disconnection
It could be enabled/disabled by NVM parameter. If enabled, the PFC_CS disconnection fault protection is latched.
In case the PFC_CS is stuck high during the operative mode, the device enters the PFC_CS disconnection protection and it is turned off.
In case the PFC_CS pin is stuck low (or high) during the PFC start-up phase, the device enters the PFC_CS disconnection protection and it is turned off.
In particular, during the start-up phase if the disconnection faults detection is enabled and the PFC_OVP is triggered, the device behavior depends on the following cases:
• If the voltage of PFC_FB pin is between PFC_FB target and HW PFC_OVP threshold:
– AC CASE: as long as the PFC_CS is not triggered, after the 45° input line phase, the system turns on the PFC gate for a few pulses about every 0.6 ms.
– DC CASE: if the PFC_CS is not triggered the system turns on the PFC gate for a few pulses before entering the soft-start phase.
in both cases, if the PFC_CS comparator is not triggered during the start-up phase and the feedback disconnections are enabled, the device turns off entering PFC_CS disconnection fault protection.
• If the voltage of PFC_FB pin is above the HW PFC_OVP threshold:
– in case the PFC_CS is not triggered the device turns off entering PFC_OVP fault protection (not latched).
DS13643 - Rev 1 page 20/34
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
9.7.7
STNRG012
LLC control and protection
LLC control and protection
LLC related resources
Pin name
LLC_CS
LLC_AUX
LLC_FB
HVG
LVG
Table 6. LLC related pins
Description
Low-side current sense
LLC auxiliary winding voltage sense
LLC OPTO feedback sense, burst comparator and SHUTDOWN comparator
Level
0-500 mV
700 mV
0.9 V
2.5 V
ADC, 10 bit
Programmable
125 mV
High-side gate driving
Low-side gate driving
Function
5 bit OLP
OCP2 fault
External burst mode
LLC output OVP
Feedback sense
Burst comparator
Shutdown comparator
LLC OC1 comparator
The LLC OC1 comparator implements the overload protection (OLP). It monitors the LLC_CS pin with respect to a programmable threshold. If the LLC_CS pin goes every cycle over the OC1 threshold for a programmable time, the IC shuts down and enters the OLP fault.
Both threshold and duration are programmable trough NVM parameters.
LLC OC2 comparator
The LLC OC2 comparator sets a HW limit for the current flowing into the LLC resonant tank: it triggers the OCP2 fault.
It monitors the LLC_CS pin with respect to a fixed 700 mV threshold. If this threshold is triggered for a programmable consecutive number of cycles, the OCP2 fault is triggered and the system shuts down.
LLC ZCD comparator
The LLC ZCD comparator detects the LLC current zero-crossing during the normal operation to implement the time-shift control and the anti-capacitive protection.
Its output communicates to the LLC SMED.
The comparator’s hysteresis is programmable by NVM choosing between the available values 5 mV or 10 mV. It is recommended to use the 10 mV hysteresis.
LLC_FB voltage reading: OPTO feedback loop error
The LLC_FB pin is connected to the optocoupler and its voltage is the error signal of the LLC loop.
The LLC_FB voltage is sampled by the ADC to calculate the time-shift.
Shutdown feature
If the LLC_FB pin is forced below 125 mV, the device shuts down. If the voltage returns over such threshold the system restarts performing the soft-start.
This feature can be enabled / disabled using an NVM bit.
SMEDs
HVG and LVG are driven by an event driven 60 MHz state machine (2 coupled 4-state SMEDs).
Driving events are the ZCD event and the elapsing of the programmable time which sets the high-side and low-side time-shift values and drivers deadtime.
DS13643 - Rev 1 page 21/34
9.7.8
9.7.9
9.8
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.8.7
STNRG012
LLC protections
Algorithm
The LLC operation is based on “Symmetric Time-Shift Control” (STSC), an improved version of time-shift control that guarantees 50% of the HB duty cycle. The time-shift value is calculated from the LLC_FB pin.
Time-shift (patented)
The TSC methodology consists in controlling the amount of time elapsing from a zero crossing of the tank current to the switch-off of the MOSFET currently on.
Conceptually, with TSC an inner loop is closed and the outer loop that regulates the output voltage provides the reference for the inner loop. This inner loop is completely managed by SMEDs using the zero current detection information.
LLC protections
Anti-capacitive protection
Anti-capacitive control is applied at the SMEDs level using ZCD time events.
The IC monitors the phase relationship between the LLC tank current sensed on the LLC_CS pin and the voltage at the HVG and LVG, checking the time between the gate rising edge and the tank current zero cross detection.
If this time is below a programmable threshold, which is indicative of impending capacitive-mode operation, the monitoring circuit activates the “Soft” ACP procedure: the time-shift is reduced (and therefore the switching frequency is increased) in order to keep the converter away from that dangerous condition.
If the time reaches “zero” the device is stopped immediately. This is called “Hard” ACP.
Both hard and soft ACP can be enabled and disabled through NVM.
LLC OLP
If the LLC OC1 comparator is triggered the system could enter the overload protection (OLP). During this phase the system regulates the output and checks for a programmable time if the OCP1 event is still present, in this case the device is shut down entering the OLP fault state that can be programmed as latched or not latched.
LLC OCP2
If the LLC OC2 comparator is triggered for a number of times greater than a threshold set by the user, the device sets the OCP2 fault and it is shut down. The OCP2 fault can be programmed as latched or not latched.
LLC soft-start timeout
If the LLC output voltage cannot reach the regulation value within 100 ms, the device enters the LLC soft-start timeout fault and it is shut down. The fault can be programmed as latched or not latched.
LLC OVP
If the LLC_AUX pin voltage is higher than the LLC OVP comparator threshold (2.5 V) the system enters the LLC
OVP fault state and it is turned off. The fault can be programmed as latched or not latched and can be disabled.
The autorestart timer is set to about 34 ms in case not latched chosen.
LLC_CS disconnection
If the LLC_CS pin is stuck at 0 V or 5 V during the soft-start the system enters the LLC_CS disconnection fault
(not latched) and it is shut down if the disconnection faults detection is enabled in NVM.
LLC_AUX disconnection
If the pure external burst-mode is enabled and the LLC_AUX pin is stuck at 0 V during the burst and the
LLC_FB pin is higher than the burst comparator threshold, after 32 burst packets the system enters LLC_AUX disconnection protection (latched) and it is shut down if the disconnection faults detection is enabled in NVM.
DS13643 - Rev 1 page 22/34
STNRG012
ADC
9.9
9.10
9.10.1
9.10.2
ADC
•
•
The system ADC is an 8-channel 15-MHz SAR 10-bit A/D converter.
It needs 7 cycles (470 ns) for sampling and 11 cycles (740 ns) to convert the data.
It is controlled by an SW programmable scheduler allowing flexible system signals reading:
Fixed time sequence conversion
Event driven sequence conversion
Signal
Input line voltage
PFC feedback voltage
LLC feedback voltage
Table 7. ADC input signals
VAC
PFC_FB
LLC_FB
Pin Internal voltage divider
Internal voltage divider
Direct reading
Direct reading
FST
484.5 V
2.5 V
2.5 V
Burst-mode
Specific resources
Burst comparator on LLC_FB pin
The LLC BURST comparator at the LLC_FB pin is used to wake up the system, in order to perform a burst sequence.
The comparator is alive also during sleep and the wake-up threshold is programmable (0.75 V, 1 V, 1.25 V).
External burst-mode comparator on LLC_AUX pin
The external burst-mode comparator with the 0.9 V threshold on the LLC_AUX pin is used to enter / exit the burst-mode using an external digital signal. The external burst-mode operation can be enabled / disabled using a
NVM bit.
30-kHz system oscillator
A 30-kHz oscillator (always on) keeps the system alive.
•
Algorithm
•
•
The system can manage the deep sleep state with very low VCC current consumption (500 µA).
The system in deep sleep
•
Monitors the AC line for brownout condition
Monitors the burst comparator to detect wake condition
Monitors the VCC for data integrity
Maintains all RAM data
The device implements two different burst-mode algorithms: the LLC_FB burst or external burst. The first one is based on just the LLC_FB pin voltage, the second one is based on the external BM comparator on the LLC_AUX pin that can be driven sensing the output current.
The burst-mode can be programmed to depend either on the LLC_FB pin only, or LLC_AUX pin only, or both. This third possibility is called hybrid external burst.
In case of the LLC_FB burst-mode, the device enters sleep mode if the LLC_FB pin voltage goes below a programmable threshold. The burst switching activity is enabled after the burst comparator is triggered.
The normal switching activity is restored if the time between two bursts is lower than a programmable threshold.
This time defines a precise power level at which the controller exits the burst-mode. In order to have a faster response to the big load transient the system exits burst-mode also if the LLC_FB pin voltage is still above the burst comparator threshold after one burst packet.
In case of the LLC_AUX pin driven burst-mode, two types of external burst mode could be defined:
• Pure external burst-mode: only the external BM comparator manages the burst-mode entering / exiting;
DS13643 - Rev 1 page 23/34
9.11
9.11.1
9.11.2
9.11.3
STNRG012
Communication and configuration
• Hybrid external burst-mode: if the external BM comparator is high, the system stays out of burst-mode while if the external BM comparator is low, burst-mode entering / exiting is managed by the LLC_FB pin settings.
In both external burst-mode cases, the burst switching activity is anyway managed by the LLC_FB pin and the burst comparator.
The PFC and LLC switching activities during the burst-mode are synchronized.
The LLC can perform a burst without the PFC, depending on the system conditions.
Communication and configuration
•
•
•
•
•
The device communicates with an external digital device through a serial interface.
The serial interface uses two dedicated pins with a standard UART protocol. It implements also an I 2 C protocol for external E 2 PROM writing and reading.
The serial interface allows the user
• To write the NVM to configure the device in a specific application: 24 bytes are available
To write into the RAM for test and SW patch purposes
To read the NVM content
To read the RAM content
To read registers content
To configure the device for specific tests
Based on a specific code into the NVM the serial interface functionality can be reduced for security reasons.
Monitor
Some internal data can be provided to an external digital device through the UART interface for monitoring purposes.
Black box
Black box data are written into the external E 2 PROM (if present) during the normal operation.
Patches
SW patches (if necessary) are uploaded by the device from the external E
2
PROM at the startup. It can be enabled/disabled using a NVM bit for security reasons.
DS13643 - Rev 1 page 24/34
10
10.1
STNRG012
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
SO20 package information
Figure 8. SO20 package outline
DS13643 - Rev 1
Symbol
A
A1
B
C
Min.
2.35
0.10
0.33
0.23
Table 8. SO20 package mechanical data
Dimension mm
Typ.
-
-
-
-
Max
2.65
0.30
0.51
0.32
Min.
0.093
0.004
0.013
0.090
Inch
Typ.
-
-
-
-
Max.
0.104
0.012
0.020
0.013
page 25/34
Symbol e
H
D
E h
L
K
STNRG012
SO20 package information
Min.
12.60
7.40
-
10.00
0.25
0.40
1.27
-
-
mm
Typ.
-
-
Dimension
Max
13.00
7.60
-
Min.
0.496
0.291
-
10.65
0.75
1.27
0.394
0.010
0.016
0° (min.), 8° (max.)
Inch
Typ.
-
-
0.050
-
-
-
Max.
0.512
0.299
-
0.419
0.030
0.050
DS13643 - Rev 1 page 26/34
STNRG012
Ordering information
11
Ordering information
Part number
STNRG012
STNRG012TR
Table 9. Order codes
Package
SO20
SO20
Packing
Tube
Tape and reel
DS13643 - Rev 1 page 27/34
Revision history
Date
23-Feb-2021
Version
1
Table 10. Document revision history
Changes
Initial release.
STNRG012
DS13643 - Rev 1 page 28/34
STNRG012
Contents
Contents
DS13643 - Rev 1 page 29/34
STNRG012
Contents
DS13643 - Rev 1 page 30/34
STNRG012
Contents
DS13643 - Rev 1 page 31/34
STNRG012
List of tables
List of tables
DS13643 - Rev 1 page 32/34
STNRG012
List of figures
List of figures
DS13643 - Rev 1 page 33/34
STNRG012
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DS13643 - Rev 1 page 34/34
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