STMicroelectronics L5965 Datasheet

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Dokument

L5965

Datasheet

Power management for automotive vision and radar systems

Features

VFQFPN-48 (7x7 mm)

Product status link

L5965

Product summary

Order code Package Packing

L5965SQ-V0Y

L5965SQ-V0T

VFQFPN-48

Tray

Tape and reel

GAPGPS03203

• AEC-Q100 qualified

• Pre SMPS BUCK1 regulator controller, adjustable via OTP to 0.8 V, 1.0 V, 1.1 V,

1.2 V, 1.8 V, 3.3 V, 3.8 V, 5.0 V @ 0.4 MHz

• Pre SMPS BUCK2 regulator, adjustable via OTP to 1.0 V, 1.1 V, 1.2 V, 1.35 V,

1.5 V, 3.3 V, 3.6 V, 5.0 V @ 1.35/2.6 A min peak current limit, 0.4/2.4 MHz

• Post SMPS BUCK3 regulator, adjustable via OTP to 1.0 V, 1.2 V, 1.35 V, 1.8 V,

2.0 V, 2.3 V, 2.5 V, 3.3 V @ 1.4 A min peak current limit, 2.4 MHz

• Post SMPS BUCK4 regulator, adjustable via OTP to 1.1 V, 1.12 V, 1.2 V, 1.25 V,

1.3 V, 1.35 V, 1.8 V, 3.3 V @ 1 A min peak current limit, 2.4 MHz

• Post SMPS BOOST regulator, adjustable via OTP to 5.0 V @ 0.3 A max load current, 7.0 V @ 0.2 A max load current, 2.4 MHz

• Post Linear regulator LDO, adjustable via OTP to 1.2 V, 1.25 V, 1.3 V, 1.8 V,

2.5 V, 2.8 V, 3.3 V, 5.0 V @ 300/600 mA max load current

• Precise Voltage reference, adjustable via OTP to 1.8 V, 2.5 V, 3.3 V,

4.1 V @ 20 mA max load current

• SPI interface with CRC

• Programmable slew rate/soft start

• Voltage supervisors

• Spread frequency spectrum

• Reset and reset activation list

• Adjustable window watchdog supervisors

• Power up phase programmable via OTP

• Short circuit protected outputs and Fault detection pin to Microcontroller

• Low external components number

• Thermal shutdown junction temperature 175 °C

Description

L5965 is a multiple voltage regulator composed by two battery compatible BUCK preregulators (one of which is a controller), two BUCK post regulators with internal compensation, one BOOST, one LDO and a precise voltage reference regulator. All the regulators, except the BUCK1 pre-regulator, have internal power switches.

OTP (One Time Programmable) cells are used for the main device parameters programming (output voltages and currents, switching frequencies) and to configure power up sequence.

An SPI interface can be used to enable or disable the single voltage regulators, for diagnostic information and to program internal blocks parameters (monitor and

Power Good thresholds, slew rate, etc.).

The device offers a set of features to support applications that need to fulfill functional safety requirements as defined by Automotive Safety Integrity Level (ASIL) A-B-C-D.

DS12567 - Rev 2 - May 2019

For further information contact your local STMicroelectronics sales office.

www.st.com

1.1

L5965

Overview

Overview

L5965 is a multichannel voltage regulator able to offer flexibility and ease to use, together with a set of features that make it compliant to car passenger applications that require a certain level of safety. The product includes input and output monitors, independent band-gaps, ground loss monitors, internal compensation networks, that also help reduce the BOM, digital and analog BIST, fault pin.

In this product, there are 7 different regulators. A first battery-compatible regulator, a controller that can supply several current flow thanks to the use of external MOSs. A second regulator with integrated MOS that can be used as a pre-regulator for currents up to about 2.6 A. Two bucks, post regulators, one boost that can be used to supply, for example, a CAN bus, one LDO and a 1% accurate reference voltage for the microcontroller.

All output voltages can be selected via memory cells (OTP) that can be programmed before using the PMIC. This guarantees precision and safety, since output voltages are not susceptible to variations due to the external environment. It also contributes to reducing the number of external components. Through the OTP it is also possible to decide the switching frequency of some regulators, the current limitation, select the main buck and the system power-on sequence.

Programming can also be done at customer’s production line.

There is also an SPI bus, used to program the PMIC and to communicate with the microcontroller. Through this bus it is possible to set overvoltage and undervoltage thresholds, enable the spread spectrum, select the soft start time and many other things. The SPI is also used to communicate the status of the bucks in case of fault, overtemperature or other events.

The maximum free run switching frequency of the bucks is 2.4 MHz, modifiable through external synchronization signals.

The PMIC can manage watchdog and reset signals.

Simplified block diagram

WKUP

VBAT INDEPENDENT SUPPLIES

Figure 1. Simplified block diagram

Voltage references

Pre-BUCK1 controller

Buck pre/post regulator compatible to battery V

5-3.8-3.3-1.8-1.2-1.1-1.0-0.8 V @ 0.4 MHz

FAULT

RESETB

SPI

SYNC_IN

SYNC_OUT

Safety management

Watchdog &

Reset

SPI

OTP

Diagnostics

Oscillator

Pre-BUCK2

BUCK3

Internal compensation

BUCK4

Internal compensation

BOOST

Supervisors

LDO

Supervisors

VREF

Supervisors

Buck pre/post regulator compatible to battery V

5.0-3.6-3.3-1.5-1.35-1.2-1.1-1.0 V @ 1.35-2.6 A ● 0.4-2.4 MHz

Buck post regulator compatible to 5.5 V max

3.3-2.5-2.3-2.0-1.8-1.35-1.2-1.0 V @ 1.4 A ● 2.4 MHz

Buck post regulator compatible to 5.5 V max

3.3-1.8-1.35-1.3-1.25-1.2-1.12-1.1 V @ 1 A ● 2.4 MHz

Boost post regulator compatible to 5.5 V max

7 V @ 0.2 A, 5 V @ 0.3 A ● 2.4 MHz

Linear post regulator compatible to 5.5 V max

5-3.3-2.8-2.5-1.8-1.3-1.25-1.2 V @ 300-600 mA

Internally connected to the battery

4.1 - 3.3 - 2.5 - 1.8 V @ 20 mA

Note: Buck min peak currents .

GAPG1005181515PS

DS12567 - Rev 2 page 2/85

L5965

Functional block diagram

1.2

Functional block diagram

Figure 2. Functional block diagram

Application example with BUCK2 as main buck.

VBAT 1

REF

VSLDO

LDO

VBUCK2

MCU

VBUCK2

MCU

VBAT 1

VBUCK2

MCU

VBAT 1

SGND

AGND

DGND

REFERENCE bandgap1

Frequency processor

SYNCIN

SYNCOUT

REF

VSLDO

LDO bandgap3

VREF

LDO

FAULT

Safety management bandgap 2 monitors

TJ clusters

VBAT 1

ADC

WDI

RESET_B

Watchdog & reset

WKUP

Debug

Input control

CSN

CLK

SPI

EXTSUP

4.6 V

VREG

BUCK1

BST1

GH1

3.3 V

BUCK2

3.3 V

BUCK3

Output

/loop control

Output

/loop control

PH1

GL 1

PGND1 sensep sensen

VREG1_S

COMP1

VBAT 2

BST2

PH2

PGND2

VREG2_S

COMP2

VIN 3

BST3

PH3

PGND3

VREG3_S

3.3 V

BUCK4

Output

/loop control

VIN 4

BST4

PH4

PGND4

VREG4_S

3.3 V

BOOST

PH5

PGND5

Output/ control

VBOOST_ S

EXTSUP

VBAT 1

VBUCK2

VBUCK3

VBUCK2

VBUCK4

VBUCK2

VBOOST

VBUCK1

GADG1005181537PS

DS12567 - Rev 2 page 3/85

L5965

Pins description

Pins description

Figure 3. Pin out (top view)

REF

VBAT1

EXTSUP

VREG

BST1

GH1

PH1

GL1

PGND1 sensep sensen

COMP1

SYNCOUT

SYNCIN

BST2

VBAT2

PH2

PGND2

VREG2_S

COMP2

VBOOST_S

PGND5

PH5

WKUP

DS12567 - Rev 2

Pin name

REF

VBAT1

EXTSUP

VREG

BST1

GH1

PH1

GL1

PGND1 sensep sensen

COMP1

VREG1_S

Debug

No.

Table 1. Pin description and functions

Pin type

I/O

Description

Accurate reference voltage output

VBAT1 for inner reference and supply for pre-BUCK1 external HS MOS

Optional LV input for BUCK1, BUCK3, BUCK4 gate driver supply

Internal regulator for BUCK1, BUCK3, BUCK4 gate driver supply (decoupling)

Boot-strap capacitor to supply BUCK1 high-side MOS gate-driver circuitry

Gate driver of external high-side MOS

Switching node BUCK1

Gate driver of external low-side MOS

Ground for external low-side MOS driver circuitry

Positive differential current sense input for BUCK1

Negative differential current sense input for BUCK1

BUCK1 Error Amplifier compensation network

BUCK1 regulated voltage output (to internal voltage monitors)

Device debug. Keep floating or connect to ground when not used

GAPG2206151609PS page 4/85

DS12567 - Rev 2

L5965

Pins description

No.

27 PGND5

28 VBOOST_S

29 COMP2

VREG2_S

PGND2

PH2

VBAT2

BST2

SYNCIN

SYNCOUT

WDI

CSN

CLK

RESET_B

Pin name

BST3

VIN3

PH3

PGND3

VREG3_S

VREG4_S

PGND4

PH4

VIN4

BST4

WKUP

PH5

FAULT

DGND

SGND

AGND

LDO

VSLDO

I/O

Pin type

I/O

Description

Boot-strap capacitor to supply BUCK3 high-side MOS gate-driver circuitry

Input voltage supply for BUCK3

Switching node BUCK3

BUCK3 Power ground

BUCK3 regulated voltage output (to internal voltage monitors)

BUCK4 regulated voltage output (to internal voltage monitors)

BUCK4 Power ground

Switching node BUCK4 input voltage supply for BUCK4

Boot-strap capacitor to supply BUCK4 high-side MOS gate-driver circuitry

Wake up input. Internal 200 kΩ pull-down

BOOST switching node

BOOST Power ground

BOOST regulated voltage output (to internal voltage monitors)

BUCK2 Error Amplifier compensation network

BUCK2 regulated voltage output (to internal voltage monitors)

BUCK2 Power ground

Switching node BUCK2

Input voltage supply for BUCK2

Boot-strap capacitor to supply BUCK2 high-side MOS gate-driver circuitry

PWM input frequency for synchronization purpose. Internal current pull-down

PWM output frequency of inner 2.4M oscillator, or SYNCIN if used

Watchdog input. WDI is trigger input from MCU. Internal current pull-down

SPI: chip select input. Active low. Internal current pull-up

SPI: serial data input. Internal current pull-down

SPI: serial clock input. Internal current pull-down

SPI: serial data output

Reset

Fault pin detection to MCU

Digital GND

Signal ground for low noise circuitry

Analog GND

Linear regulated output

Input voltage supply for LDO page 5/85

3.1

L5965

Electrical specifications

Electrical specifications

Pin name

FAULT

SYNCOUT

SYNCIN

EXTSUP

VREG

BST1

GH1

PH1

GL1

VBAT1

SGND

AGND

DGND

REF

VSLDO

LDO

WKUP

RESET_B

WDI

CSN

CLK sensep sensen

VREG1_S

PGND1

VBAT2

BST2

PH2

VREG2_S

PGND2

Absolute maximum ratings & operating voltage

Table 2. Absolute maximum ratings & operating voltage

Absolute maximum rating

-0.3

PH1-0.3

-1

PGND1-0.3

-0.3

sensen-2

-0.3

PH2-0.3

-1

-0.3

Min

-0.3

6.5

4.6

6.5

PH1+10

PGND1+10

6.5

sensen+2

6.5

0.3

PH2+4.6

6.5

0.3

6.5

Max

0.3

6.5

Unit

-0.3

PH1-0.3

-1

PGND1-0.3

-0.3

sensen-2

-0.3

PH2-0.3

-1

-0.3

Min

-0.3

Operating voltage

5.5

3.6

5.5

6.6

PH1+8

PGND1+8

5.5

sensen+2

5.5

0.3

PH2+3.6

5.5

0.3

5.5

Max

5.5

Unit

DS12567 - Rev 2 page 6/85

L5965

Thermal data

3.2

3.2.1

3.2.2

Pin name

VIN3

BST3

PH3

VREG3_S

PGND3

VIN4

BST4

PH4

VREG4_S

PGND4

PH5

VBOOST_S

PGND5

Debug

COMP1

COMP2

Thermal data

Thermal resistance

Min

Absolute maximum rating

Max

-0.3

PH3-0.3

-1

-0.3

PH4-0.3

-1

-0.3

6.5

PH3+4.6

6.5

4.6

0.3

6.5

PH4+4.6

6.5

4.6

0.3

4.6

0.3

Unit

Min

-0.3

PH3-0.3

-1

-0.5

-0.3

PH4-0.3

-1

-0.5

-0.3

Operating voltage

Max

5.5

PH3+3.6

5.5

3.6

0.3

5.5

PH4+3.6

5.5

3.6

0.3

3.6

0.3

7.5

Symbol

R th j-a-2s

R th j-a-2s2p

R th j-a-2s2pv

R th j-case

Parameter

Table 3. Operation junction temperature

Thermal resistance junction-to-ambient

Board

2s2p

2s2p+vias

Thermal resistance junction-to-case

Thermal warning and protection

Symbol

SD_TH

SD_hys

OT_THx (x=1-7)

OT_hysx (x=1-7)

SD_filter

T j

T stg

Parameter

Thermal Shutdown

Table 4. Temperature thresholds

Over temperature warning

Thermal Filter time

Junction temperature

Storage temperature

Test condition

–

Hysteresis

–

Hysteresis

–

T j

T stg

Value unit

2.2

Min.

160

0.5

140

–

-40

Typ.

175

155

Max.

190

170

–

150

Unit

°C

µs

°C

Unit

°C/W

Unit

DS12567 - Rev 2 page 7/85

L5965

Electrical characteristics

3.3

According to the below formula and considering T

SD_TH maximum suggested power dissipation is:

thermal shutdown minimum threshold at 160 °C, the

DISS_suggested

= (T

SHD

-T

AMB

) / R

THJ-A

Symbol

R th j-a-2s

R th j-a-2s2p

R th j-a-2s2pvias

Table 5. Maximum suggested power

T amb

125 ° C

0.53 W

1.1 W

1.35 W

T amb

105 ° C

0.9 W

1.8 W

2.3 W

T amb

80 ° C

1.2 W

2.6 W

3.2 W

Electrical characteristics

BAT1

supplies pre-BUCK1 circuitry the inner reference circuit (band-gap and oscillator) and VREF.

BAT2

supplies BUCK2, VSLDO supplies the LDO, VIN3 supplies BUCK3 and VIN4 supplies BUCK4.

BAT1,2

= 14 V, T amb

= –40 °C to 125 °C, unless otherwise specified.

Symbol

General characteristics

BAT1

BAT2

STANDBY1

STANDBY2

ACTIVE

ACTIVE_ALL

Table 6. Electrical characteristics

Parameter Test condition

Operating range

STANDBY mode total current consumption on VBAT1

STANDBY mode total current consumption on VBAT2

ACTIVE mode total current consumption

–

All regulators off, V

BAT1

= 14 V, nonsupply inputs floating, current consumption from the supplies

All regulators off, V

BAT2

= 14 V, nonsupply inputs floating, current consumption from the supplies

Main BUCK only, V

BAT1-2

= 14 V,

EXTSUP = 0 V

All regulators ON, V

BAT1-2

= 14 V,

Rising slope < 0.1V*ms,

EXTSUP=0 V

Supply monitors

UV_HYS

OK_HYS

OV_HYS t

UVOV_filter

RESETB

FAULT

Under-voltage threshold for V

BAT1

and

BAT2

Under-voltage hysteresis

OK threshold for VBAT1 or VBAT2, depending on which is the main regulator

OK-voltage hysteresis

Supply decreasing

–

Supply increasing

Over-voltage threshold for V

BAT1

and V

BAT2

Over-voltage hysteresis

Supply increasing

–

Over/under voltage filter time

RESETB pin low output voltage

RESETB pulse duration

FAULT pin low output voltage

–

RESET

= 1 mA

–

FAULT

= 1 mA

Min.

Typ.

Max.

Unit

–

5.3

–

5.5

–

5.8

0.2

0.1

–

6.3

0.4

6.5

0.4

2.4

–

0.25

µA

µA mA mA

µs

DS12567 - Rev 2 page 8/85

L5965

Electrical characteristics

Symbol

Power on reset

POR_R

POR_F

Oscillator f osc f

SYNC

VREG

VREG

EXTSUP_TH

EXTSUP_HYS

DROP_VREG

LIM_REG

VREG

REG_OK

BUCK1

IN_BUCK1

OUT_BUCK1

Vsense

SW_BUCK1

F spread_BUCK1

BAT1

threshold

BAT1

threshold

Parameter

Oscillator frequency

Input frequency at SYNCIN pin

SYNCIN high threshold

SYNCIN low threshold

–

Test condition

BAT1

rising

BAT1

falling

Min.

2.8

Typ.

3.4

3.2

Max.

3.8

3.6

Unit

4.08

4.8

1.8

–

2.1

–

5.52

MHz

2.76

MHz

–

BUCK1 gate driver inner regulated supply

Switch over threshold

Switch over hysteresis

Drop out voltage at VREG

VREG current limitation

Capacitive load

VREG under voltage threshold

VREG

= 0 mA~50 mA, EXTSUP =

6.3~12 V

VREG

= 5 mA~50 mA, EXTSUP rising, in ACTIVE mode

–

I load

= 50 mA, supplied by VBAT1

I load

= 50 mA, supplied by EXTSUP

Supplied by VBAT1/EXTSUP

–

VREG rising

Hysteresis

5.8

6.0

6.2

–

4.7

0.2

–

2.2

0.26

–

0.25

0.4

µF

V mA

Input voltage range

Output voltage

(> 200 mA, static)

Cycle by cycle current limitation sense voltage

Switching frequency

Spread spectrum range

–

OTP = 000

OTP = 001

OTP = 010

OTP = 011

OTP = 100

OTP = 101

OTP = 110

OTP = 111

–

Fsw = 400 kHz

-2.5%

–

1.8

1.2

1.1

1.0

0.8

–

5.0

3.8

3.3

340

-20

+2.5

–

400 460

– 20

V mV kHz

DS12567 - Rev 2 page 9/85

L5965

Electrical characteristics t

Symbol programming_dead_BUCK1

Ron LS1

CLAMP_VGS_HS

CLAMP_VGS_LS

Parameter

Dead time (Blanktime: non-overlap time plus programming time)

Test condition

SPI = 000 default

SPI = 001

SPI = 010

SPI = 011

SPI = 100

SPI = 101

SPI = 110

SPI = 111

– t on_min

BUCK1 GATE Driver

Ron HS1 t

SOFTSTART_BUCK1

–

Ron @ Buck1_curr_max

SPI = '0' (1.0 A)

SPI = '1' (2.0 A)

SPI = '0' (1.0 A)

SPI = '1' (2.0 A)

Clamp protection for Vgs of external transistor

–

Soft start time when start up, Vref from 0 V to 1 V

SPI = 00

SPI = 01

SPI = 10

BUCK2

IN_BUCK2

Input voltage range

OUT_BUCK2 t on_min

Min T on

internal FET

Free running frequency

∆V

BUCK2

(2)

Undershoot &overshoot

∆V

LINER-LOADR_VBUCK2

Static line + load regulation

LIMIT

Ron

Output voltage (no load, static)

Peak switching current limitation

High side switch on resistance

–

Min.

Typ.

Max.

Unit

– 50 – ns

–

– ns ns ns ns

100

200

208

1.75

0.85

3.20

1.60

–

9 – 11

0.3

0.42

0.55

0.7

1.6

1.3

2.4

V ms ms ms

Ω

V ns ns ns ns

–

OTP = 000

OTP = 001

OTP = 010

OTP = 011

OTP = 100

OTP = 101

OTP = 110

OTP = 111

–

OTP = 0

OTP = 1

Load = 0.3 A to 1.8 A, ∆t = 10 µs,

= 5 V

= 6 V to 32 V, V

OUT

= 5 V

Load

= 0.3 A to 1.8 A

OTP = 0

OTP = 1

–

3.3

-2.5%

–

5.0

3.6

3.3

1.5

1.35

1.2

1.1

1.0

– 100

0.34

0.4

2.04

2.4

-5 –

+2.5

– ns

0.46

MHz

2.76

MHz

5 %

– -0.45

–

1.35

1.8

2.6

3.4

–

2.3

4.2

120 190

A mΩ

DS12567 - Rev 2 page 10/85

L5965

Electrical characteristics

ƞ (2)

SOFTSTART_BUCK2

F t

Symbol

Ron

LS spread_BUCK2

Phi

BUCK2

SR_PH2

(2)

Parameter

Low side switch on resistance

Efficiency

Soft start time when start up, Vref from 0 V to 1 V

Spread spectrum range

Phase shift to BUCK1

Output stage slew rate when F kHz

= 400

Test condition

–

FSW =400 kHz, V

V/3.3 V,

=14 V, V

OUT

= 5

I load

= 2 A

= 2.4 MHz, V

= 5 V, V

OUT

3.3 V, I load

= 1 A

SPI = 00 default

SPI = 01

SPI = 10

Fsw=400 kHz

Fsw=2.4 MHz

–

= 14 V, I load

= 1.8 A, V

OUT

3.3 V

SPI = 00

SPI = 01

Output stage slew rate when F

MHz

= 2.4

= 5 V, I load

= 1 A, V

OUT

= 3.3 V

Min.

Typ.

Max.

Unit

– 110 190 mΩ

–

0.35

0.45

0.8

1.8

-20

-4

–

1.1

2.2

–

180

–

0.5

1.4

2.6

–

% ms ms ms

% deg ns ns ns

BUCK3

IN_BUCK3

Input voltage range

OUT_BUCK3 t on_min

∆V

BUCK3

(2)

Output voltage

(no load, static)

–

Undershoot

∆V

LINEAR-LOADR_VBUCK3

LIMIT

Ron

F sw_BUCK3

Static line + load regulation

Peak switching current limitation

High side switch on resistance

Low side switch on resistance

Free-run switching frequency

ƞ (2)

Efficiency

–

OTP = 000

IN_BUCK3

> 4.5 V

OTP = 001

OTP = 010

OTP = 011

OTP = 100

OTP = 101

OTP = 110

OTP = 111

–

Load = 0.3 A to 0.8 A ∆t = 10 µs,

= 3.3 V

Load = 0.3 A to 0.8 A

–

FSW = 2.4 MHz, V

= 3.3 V, V

OUT

1. 2 V, I load

= 0.7 A

3.0

-2.5%

–

-5

–

3.3

2.5

2.3

2.0

1.8

1.35

1.2

1.0

–

+2.5

–

1.4

–

– 110

2.04

2.4

0.1

–

1.8

2.3

150 250

200

A mΩ mΩ

2.76

MHz

5.5

–

V ns

DS12567 - Rev 2 page 11/85

L5965

Electrical characteristics t

Symbol

SOFTSTART_BUCK3

I spread_BUCK3 t

Phi

BUCK3

SR_PH3

(2)

BOOST

BOOST_limit

Parameter

Soft start time when start up, Vref from 0 V to 1 V

Spread spectrum range

Phase shift to BUCK1

Ouptut stage slew rate, F

=2.4 MHz

Test condition

SPI = 00

SPI = 01

SPI = 10

Fsw=2.4 MHz

–

= 3.3 V, I load

= 0.8 A, V

OUT

= 1.2

Min.

Typ.

Max.

Unit

0.35

0.45

0.55

0.8

1.8

1.1

2.2

1.4

2.6

ms ms

-4

– 90

–

% deg

– 10 – ns

BUCK4 t

VIN_BUCK4

VOUT_BUCK4 t on_min

∆V

BUCK4

(2)

∆V

LINER-LOADR_VBUCK4

LIMIT

Ron

(2)

SOFTSTART_BUCK4

F spread_BUCK4

F t

Phi

BUCK4 sw_BUCK4

SR_PH4

(2)

Input voltage range

Output voltage

(no load, static)

–

Undershoot

Static line + load regulation

Peak switching current limitation

High side switch on resistance

Low side switch on resistance

Efficiency

Soft start time when start up, Vref from 0 V to 1 V

Spread spectrum range

Phase shift to BUCK1

Free-run switching frequency

Output stage slew rate when f

MHz

= 2.4

–

OTP = 000

IN_BUCK4

> 4.5 V

OTP = 001

OTP = 010

OTP = 011

OTP = 100

OTP = 101

OTP = 110

OTP = 111

–

Load = 0.3 A to 0.6 A ∆t = 10 µs, V

= 3.3 V

Load = 0.3 A to 0.6 A

–

3.0

-2.5%

–

-5

–

= 2.4 MHz, V

= 3.3 V, V

OUT

1.8 V, I load

= 0.6 A

SPI = 00

SPI = 01

SPI = 10

Fsw=2.4 MHz

–

= 3.3 V, I load

= 0.6 A, V

OUT

= 1.8

mΩ mΩ

0.35

0.45

0.55

0.8

1.1

1.4

1.8

2.2

2.6

-4% – 4%

– 270

2.04

2.4

– deg

2.76

MHz ms ms ms

–

3.3

1.8

1.35

1.3

1.25

1.2

1.12

1.1

–

0.1

1.35

150

120

5.5

+2.5

–

1.9

250

220

–

V ns

% ns

BOOST

IN_BOOST

Input voltage range

Output voltage

Switch current limitation

–

OTP = 0

OTP = 1

–

3.0

-2.5%

500

–

5.5

+2.5

1200 mA

DS12567 - Rev 2 page 12/85

L5965

Electrical characteristics

Symbol

SW_BOOST

PhS

BOOST

F spread_BOOST t

SS_BOOST

LDO

RDS

ON_BOOST ƞ

BOOST

(2)

VSLDO

LDO

LS RDS

Efficiency

Parameter

Switching frequency

Phase shift to BUCK1

Spread spectrum range

Soft start time

Input voltage range

Output voltage

VREF

I load

V drop

C load

ESR

REF

I load

REF_TOT

VREF

ESR

Toc_filter

SYNC IN/OUT

SYNCOUTL

SYNCOUTH

SYNCOUT

Load current range

I out

= 600 mA

–

REF Output voltage, I

VREF

= 5 mA

Load current range

Reference voltage current limit

VREF load capacitor

Load capacitor ESR

Filter for over current flag of VREF

Output low level

Output high level

Pin capacitance inside silicon

Load capacitor at application level

–

OTP = 000

OTP = 001

OTP = 010

OTP = 011

OTP = 100

OTP = 101

OTP = 110

OTP = 111

OTP = 0

OTP = 1

Test condition

–

= 2.4 MHz

SPI = 00 default

SPI = 01

SPI = 10

–

= 2.4 MHz, V

5 V, Load = 200 mA

= 3.3 V, V

OUT

-4%

0.4

0.9

1.8

–

Min.

Typ.

Max.

Unit

2.04

2.4

2.76

MHz

– 270 – deg

–

0.5

1.2

2.4

400 700

4% *f

0.6

1.5

3 ms ms mΩ

– 87 – %

1.8

-2.5%

–

5.0

3.3

2.8

2.5

1.8

1.3

1.25

1.2

–

300

600

0.6

–

100

+2.5

µF mΩ

V mA mA

–

OTP = 00

OTP = 01

OTP = 10

OTP = 11

–

SYNCOUT

= -1 mA

SYNCOUT

= 200 μA

(1)

(2)

1.78

1.8

2.47

2.5

3.27

3.3

4.06

4.1

0.22

–

3.0

–

0.2

3.3

200 mA

µF mΩ ms

V mA

–

1.82

2.53

3.33

4.14

V pF pF

DS12567 - Rev 2 page 13/85

L5965

Electrical characteristics

WKUP

WAKE_OFF

LEAK_WKUP t

WAKE_filter

Symbol

SYNCOUT

T delay_ SYNC_in-out

SYNCIN

T det

WAKE_ON

PD_WAKE

Twk_rec

Parameter

SYNCOUT cycles/seconds

Delay between SYNCIN rising edge and

SYNCOUT rising edge

Duty cycle of SYNCIN

SYNCIN rising edge detection time

–

Leakage current

–

Internal pull-down resistor

WKUP high duration in REC

range

Test condition

Aligned with SYNCIN frequency

No load on SYNCOUT pin

SYNCIN frequency >1.6 MHz.

–

WKUP

= 5 V, active mode

–

SPI = 00 default

SPI = 01

SPI = 10

SPI = 11

GND loss comparator

GL_TH

GND loss threshold t

GL_filter

GND loss filter

Power output UV/OV monitor

VUV_L_ BUCKx, BOOST,

LDO, V ref

Under voltage threshold at falling edge of output (as % of output). Referred to the output relative value

VUV_HYS_ BUCKx,

BOOST, LDO, V ref

Hysteresis of UV

VOV_H_BUCK2

VOV_H_BOOST, LDO

VOV_H_VREF, BUCK

1/3/4

Over voltage threshold at rising edge of output (as % of output). Referred to the output relative value

VOV_H_BUCK2

VOV_H_BOOST, LDO

VOV_H_VREF, BUCK

1/3/4

Over voltage threshold at rising edge of output (as % of output). Referred to the output relative value

VOV_HYS_ BUCKx,

BOOST, LDO, V ref

Hysteresis of OV t

UV_filter_BUCK3,4

, BOOST,

LDO, V ref

Under voltage threshold filter time t

OV_filter_BUCK3,4

, BOOST,

LDO, V ref

Over voltage threshold filter time t

UV_filter_BUCK1 t

UV_filter_BUCK2 t

OV_filter_BUCK1 t

OV_filter_BUCK2

Power Good

Under voltage threshold filter time

Over voltage threshold filter time

SGND to PGNDx

–

SPI = 0 default

SPI = 1

–

SPI = 0 (default)

SPI = 1

–

Min.

Typ.

Max.

Unit

– 370 ns

–

30%

–

70%

18 ns

µs

–

200

–

µA

µs

V kΩ ms ms ms ms

0.18

0.27

0.34

– 16 –

µs

86 -

– 2 3

-3.5

107

108

107.5

112

113

112.5

+3.5

– 2 3

– 16 – µs

– 40 – µs

DS12567 - Rev 2 page 14/85

Symbol

TH_PGx (x=1,2,3,4)

Parameter

PGx Threshold as output voltage percentage. Referred to the output relative value t

GLITCH_PG

Watchdog trigger time

WDI

Glitch Filter Time for PG

WDI pin threshold high

WDI pin threshold low

EFW1

LFW1

Long open window

Early Failure

Window 1

Late Failure

Window 1

SW1

Safe Window 1

EFW2

LFW2

Early Failure

Window 2

Late Failure

Window 2

SW2

Safe Window 2

EFW3

LFW3

Early Failure

Window 3

Late Failure

Window 3

SW3

Safe Window 3

EFW4

LFW4

Early Failure

Window 4

Late Failure

Window 4

SW4

Safe Window 4

1. Guaranteed by design

2. Guaranteed by bench tests

–

SPI = 00

SPI = 01

SPI = 10

SPI = 11

Test condition

SPI = 0 default

SPI = 1

–

L5965

Electrical characteristics

Min.

Typ.

Max.

Unit

95 99 %

–

µs

2.3

–

160

–

200 240

– 6.4

V ms ms

15.6

7.8

–

12.7

ms ms ms

31.1

15.6

–

25.5

ms ms

25.5

62.2

31.1

–

50.9

ms ms

50.9

124.4

62.2

–

– ms

101.8

DS12567 - Rev 2 page 15/85

L5965

Electrical characteristics

3.3.1

Electrical characteristic curves

Figure 4. Efficiency of Buck2 with Vin = 14 V and

Vout = 3.3 V

100

η [%]

Buck2 @ 400 kHz

Buck2 @ 2.4 MHz

0.5

1 1.5

I (A)

2 2.5

Figure 5. Efficiency of Buck3 with Vin = 3.3 V and

GADG0609180940PS

100

η [%]

Buck3 @ 2.4 MHz

0.2

0.4

Vout = 2 V

0.6

I (A)

0.8

1 1.2

1.4

GADG0609180948PS

100

η [%]

Figure 6. Efficiency of Buck4 with Vin = 3.3 V and

Vout = 1.8 V

Boost @ 2.4 MHz

0.2

0.4

0.6

I (A)

0.8

Figure 7. Efficiency of Boost with Vin = 3.3 V and

Vout = 5 V

1.2

1.4

GADG0609181051PS

100

η [%]

Buck5 @ 2.4 MHz

0.05

0.1

0.15

0.2

0.25

I (A)

0.3

0.35

0.4

0.45

0.5

GADG0609181118PS

DS12567 - Rev 2 page 16/85

L5965

Functional description

4.1

4.2

4.2.1

Functional description

Programming by OTP

•

OTP cells are used to program all regulators output voltages and running frequencies, together with additional device features. Programmable values are:

• BUCK1 output values : 5.0 V, 3.8 V, 3.3 V, 1.8 V, 1.2 V, 1.1 V, 1.0 V or 0.8 V (3 bits)

BUCK2 output values : 5.0 V, 3.6 V, 3.3 V, 1.5 V, 1.35 V, 1.2 V, 1.1 V or 1.0 V (3 bits)

BUCK2 current limit value: 1.35 A or 2.6 A (1 bit)

BUCK2 free running frequency: 0.4 or 2.4 MHz (1 bit)

BUCK3 output values : 3.3 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.35 V, 1.2 V, or 1.0 V (3 bits)

BUCK4 output values : 3.3 V, 1.8 V, 1.35 V, 1.3 V, 1.25 V, 1.2 V, 1.12 V or 1.1 V (3 bits)

LDO output values : 5.0 V, 3.3 V, 2.8 V, 2.5 V, 1.8 V, 1.3 V, 1.25 V or 1.2V (3 bits)

•

LDO output current limitation: 300 or 600 mA (1 bit)

BOOST output voltage: 7.0 V or 5.0 V (1 bit)

VREF output voltage: 4.1 V, 3.3 V, 2.5 V or 1.8 V (2 bits)

Watchdog selection: by WDI pin or through SPI (2 bits)

– if OTP "WD_cfg" bits is "00" or "01": Use Watch Dog;

– if OTP "WD_cfg" bits is "10" : No watch dog;

– if OTP "WD_cfg" bits is "11": Use SPI as Watch Dog;

Effect of WD failure on FSM. If SPI_WD_REC_en=0 and OTP_WD_REC_en=0, a WD failure asserts

RESET_B but not FSM: the device keeps active state with regulators running. If one of these bits is “1”,

RESET_B is asserted and FSM goes to REC state.

Main BUCK selection: BUCK1 or BUCK2 (3 bit)

Other regulators turning on order: from the second to the seventh one (3 bits per each regulator)

Regulators turning on delay after Power Good of the previous regulator: 0, 2, 5 or 10 ms (2 bits)

Reset activation after Power Good signal of a specific regulator (3 bits), with the possibility to add a delay from 0 (no delay) to 10 ms (2 bits)

Reset activation by the over-voltage of regulators in reset activation list (1 bit)

•

The approach used in L5965 device is the following:

• L5965 OTP cells must be programmed before first device turning on:

– No default status is present for OTP programmed parameters

– Customer can program OTP by itself

If all OTP cells are not written, the device automatically moves to OTP program mode.

OTP programming can be done only one time:

– It is not possible additional writing procedure after the first one:

◦ 3 bits stored inside OTP means OTP written (USR Area Protection)

– If OTP programming procedure fails or it is wrong, device is discarded

If a regulator is not used (disabled), it is recommended to set to “0” its enable and SeqId (post regulator activation) bits. PGNDx, VREGx_S and VBOOST_S pins should be connected to ground, while other pins can be left floating. If the internal VREG is not used, EXSUP pin should be connected to ground.

Voltage regulators and features description

VREG

VREG is an internal regulator used to supply Buck1, Buck3 and Buck4. Its output (6.0 V typical) is available at

VREG pin and decoupled by using a ceramic capacitor (2.2 µF suggested). The regulator has an internal current limitation protection.

DS12567 - Rev 2 page 17/85

L5965

Voltage regulators and features description

4.2.2

An external supply can be provided at EXTSUP pin, in parallel to VBAT1. In ACTIVE mode, if EXTSUP is higher than a fixed threshold (typically 4.6 V), VREG supply is automatically switched to EXTSUP. It helps to improve efficiency and save power dissipation when VBAT1 is higher than EXTSUP.

In case of over-temperature detection on VREG, the PMIC enters REC mode.

When the PMIC is in RAMPUP MAIN or SECUP mode, in case of fail of “vreg ok" on VREG, the IC enters REC mode.

When the PMIC is in other modes, in case of fail of “vreg ok" on VREG, the IC provides a "vreg not ok" status via

SPI bit and asserts the FAULT pin.

VREG output value influences the PMIC power-up phase when BUCK2 is configured as main buck.

The minimum value of VBAT1 required to switch-on the IC can be calculated as Vth(VREG_OK)_rising + VREG drop.

In RAMPUP MAIN and SECUP modes, if VBAT1 has not reached the minimum required value and VREG is not ok, then FSM moves to REC state.

In ACTIVE mode, if VBAT1 has not reached the minimum required value and VREG is not ok, all related analog blocks (buck1, buck3, buck4) are active, but the SPI bit and FAULT pin are asserted. To make sure that BUCK1,

BUCK3 and BUCK4 fully work, VREG should be higher than 3.5 V.

If this regulator is disabled and not used, EXSUP pin should be connected to ground.

Figure 8. VREG influence on PMIC behavior

VBAT1(min)

Vreg=6V

Vth(vreg_ok)_rise+vreg drop

Vth(vreg_ok)_rise

Vth(vreg_ok)_fall

Vth(POR)_rise

VBAT1

VREG

Vreg_ok

Vreg_drop

FSM

SHUTDOWN …...

RAMPUP …...

ACTIVE

FAULT pin

…...

GADG2711180930PS

Pre regulator BUCK1

BUCK1 controller operates using constant frequency peak current mode control. According to OTP selection, it can work as Main BUCK pre-regulator (enabled by WKUP pin signal) or as post-regulator. The input voltage

(VBAT1) is compatible to battery level and the overvoltage detection of VBAT1 (typ 32 V, available via SPI and enabled by default) can be disabled via SPI (enabled by default). The switching frequency is set to 400 kHz with the possibility to have Spread Spectrum (enabled by default and disabled via SPI). Driving stage maximum output current is programmable via SPI to 1 A or 2 A. Output voltage is programmable via OTP to 8 possible values

(5.0 V, 3.8 V, 3.3 V, 1.8 V, 1.2 V, 1.1 V, 1.0 V or 0.8 V). The inductor current is monitored by a Sense Amplifier, sensing the drop on an external resistor, then the current limit value depends on the resistor value. Output power stage dead time (to avoid Cross Conduction) is programmable via SPI on 8 different levels. Soft Start time is programmable via SPI. Compensation network is external.

DS12567 - Rev 2 page 18/85

VREG

BST1

Figure 9. Pre regulator BUCK1

L5965

Voltage regulators and features description

VBAT1

GH1

DS12567 - Rev 2

VREG

PH1

COMP1

Sensen/p

GL1

Rsense VBUCK1

PGND1

GAPG2206151644PS

•

In dropout operation the external high-side MOSFET is kept always on; every fourth clock cycle it has to be turned off for 180ns to recharge bootstrap capacitor. This allows a maximum duty cycle of 98%.

BUCK1 controller provides the following diagnostic:

• Monitor of the output voltage is monitored by an independent circuit for UV/OV detection: thresholds are set via SPI.

• Monitor of the Power Good thresholds: are set via SPI (at 5/10% of VBUCK1) and the status is provided via

SPI bit.

Over Current Protection via current sense amplifier.

Over Temperature detection by a local thermal sensor.

PGND1 loss detection.

If BUCK1 is set as Main BUCK pre-regulator:

• If a UV/OV fault occurs, then Fault pin is asserted and the corresponding fault bit is set inside the SPI register, where can be read and cleared. RESET_B is always asserted in case of UV. In case of OV, it is possible to enable or disable the reset for all regulators together by OTP. The reset moves the device to

REC state.

• If OT occurs, the power stage is switched OFF with a 16 µs filter time. The output decreases until UV is detected. The regulator goes in REC state and can restart only when OT flag is reset. The corresponding

SPI bit is set and FAULT pin is asserted.

•

Over current limitation is a cycle by cycle protection: when a fault happens for 7 consequent cycles, the

FAULT pin is asserted and the corresponding fault bit is set inside SPI register.

If PGND1 ground loss occurs, all regulators are turned OFF, FAULT and RESET_B pins are asserted and device goes back to REC state. Until the fault is present, any tentative of turning on the regulator is ignored.

If BUCK1 is set as BUCK post-regulator we have the same behavior as above, except that:

• In case of UV fault, RESET_B is asserted according to OTP reset activation and power up sequence. If

PGND1 ground loss occurs, the regulator is turned OFF and the FAULT pin is asserted. RESET_B is page 19/85

L5965

Voltage regulators and features description

4.2.3

4.2.4

asserted according to OTP reset activation and power up sequence. Until the fault is present and stored any tentative of turning on the regulator is ignored. BUCK1 can be turned on again after the fault removal and a

Read & Clear cycle.

If this regulator is disabled and not used, VREG1_S and PGND1 pins should be connected to ground.

•

Pre regulator BUCK2

•

BUCK2 regulator operates using constant frequency peak current mode control. According to OTP selection about Main BUCK, it can work as Main BUCK pre-regulator (enabled by WKUP pin signal) or as post-regulator.

The input voltage (VBAT2) is compatible to battery level (up to 32 V) and the overvoltage detection of VBAT2 (typ

32 V, available via SPI and enabled by default) can be disabled via SPI (enable by default condition). The switching frequency is set via OTP to 0.4/2.4 MHz with the possibility to have Spread Spectrum (enabled by default and disabled via SPI); a phase shift of 180° versus BUCK1 is internally generated. Output voltage is programmable with internal OTP cells to 8 possible values (5.0 V, 3.6 V, 3.3 V, 1.5 V, 1.35 V, 1.2 V, 1.1 V or 1.0

V). Over current protection can be set via OTP to 1.5 A or to 3 A. Soft start time and power stage driver slew rates

(change in T rise

and T fall

) can be independently set via SPI. Compensation network is external.

BUCK2 regulator provides the following diagnostic:

• Monitor of the output voltage by an independent circuit for UV/OV detection: thresholds are set via SPI.

• Monitor of the Power Good thresholds is set via SPI (at 5/10% of VBUCK2) but the information is not available on the bus in active mode.

Over Current Protection (with 2 selectable values by OTP) on High Side FET.

Over Temperature detection by a local thermal sensor.

PGND2 loss detection. An external schottky diode is necessary to protect the power stage in case of ground loss.

If BUCK2 is set as Main BUCK pre-regulator:

• If a UV/OV fault occurs then Fault pin is asserted and the corresponding fault bit is set inside the SPI register, where it can be read and cleared. RESET_B is always asserted in case of UV. In case of OV, it is possible to enable or disable the reset for all regulators together by OTP. The reset moves the device to

REC state.

•

If OT occurs, the power stage is switched OFF with a 16 µs filter time. The output decreases until UV is detected. The regulator goes in REC state and can restart only when OT flag is reset. The corresponding

SPI bit is set and FAULT pin is asserted.

The over current limitation is a cycle by cycle protection: when a fault happens for 7 consequent cycles, the

FAULT pin is asserted and the corresponding fault bit is set inside the SPI register.

If PGND2 ground loss occurs, all regulators are turned OFF, FAULT and RESET_B pins are asserted and the device goes back to REC state. Until the fault is present any tentative of turning on the regulator is ignored.

If BUCK2 is set as BUCK post-regulator we have the same behavior as above, except that:

•

In case of UV fault, RESET_B is asserted according to OTP reset activation and power up sequence.

If PGND2 ground loss occurs, the regulator is turned OFF and Fault pin is asserted. RESET_B is asserted according to OTP reset activation and power up sequence. Until the fault is present and stored any tentative of turning on the regulator is ignored. BUCK2 can be turned on again after the fault removal, Read & Clear cycle.

If this regulator is disabled and not used, VREG2_S and PGND2 pins should be connected to ground.

Post regulator BUCK3

BUCK3 regulator operates using constant frequency peak current mode control. The input voltage (VIN3) is compatible to the Main regulator output (up to 5.5 V). The switching frequency is 2.4 MHz with the possibility to have Spread Spectrum (enabled by default and disabled via SPI); a phase shift of 90 ° versus BUCK1 is internally generated. Output voltage is programmable via OTP cells to 8 possible values (3.3 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V,

1.35 V, 1.2 V, or 1.0 V). The soft start time can be set via SPI. Compensation network is internal.

BUCK3 regulator provides the following diagnostic:

• Monitor of the output voltage by an independent circuit for UV/OV detection: thresholds are set via SPI.

• Monitor of the Power Good thresholds: are set via SPI (at 5/10% of VBUCK3) and the status is provided via

SPI bit.

DS12567 - Rev 2 page 20/85

L5965

Voltage regulators and features description

4.2.5

4.2.6

•

Over Current Protection on High Side FET.

Over Temperature detection by a local thermal sensor.

PGND3 loss detection.

BUCK3 fault management:

• If a UV/OV fault occurs then the FAULT pin is asserted and the corresponding fault bit is set inside the SPI register, where it can be read and cleared. RESET_B is asserted in case of UV, according to OTP reset activation and power up sequence. In case of OV, it is possible to enable or disable the reset for all regulators together by OTP. The reset moves the device to REC state.

•

If OT occurs, the power stage is switched OFF with a 16us filter time. The output decreases until UV is detected. The regulator goes in REC state and can restart only when OT flag is reset. The corresponding

SPI bit is set and FAULT pin is asserted.

The over current limitation is a cycle by cycle protection: if a fault happens for 7 consequent cycles, the

FAULT pin is asserted and the corresponding fault bit is set in the SPI register.

• If PGND3 ground loss occurs, the regulator is turned OFF and the FAULT pin is asserted. RESET_B is asserted according to OTP reset activation and power up sequence. The device moves to REC state. Until the fault is present and stored any tentative of turning on the regulator is ignored. BUCK3 can be turned on again after the fault removal and a Read & Clear cycle.

If this regulator is disabled and not used, VREG3_S and PGND3 pins should be connected to ground.

Post regulator BUCK4

BUCK4 regulator operates using constant frequency peak current mode control. The input voltage (VIN4) is compatible to the Main regulator output up to 5.5 V. The switching frequency is 2.4 MHz with the possibility to have Spread Spectrum (enabled by default and disabled via SPI); a phase shift of 270 ° versus BUCK1 is internally generated. Output voltage is programmable with internal OTP cells to 8 possible values (3.3 V, 1.8 V,

1.35 V, 1.3 V, 1.25 V, 1.2 V, 1.12 V or 1.1 V). The soft start time can be set via SPI. Compensation network is internal.

•

BUCK4 regulator provides the following diagnostic:

• Monitor of the output voltage by an independent circuit for UV/OV detection: thresholds are set via SPI.

•

Monitor of the Power Good thresholds: are set via SPI (at 5/10% of VBUCK4) and the status is provided via

SPI bit.

Over Current Protection on High Side FET.

Over Temperature detection by a local Thermal sensor.

PGND4 loss detection.

BUCK4 Fault management:

• If a UV/OV fault occurs then the FAULT pin is asserted and the corresponding fault bit is set inside the SPI register, where can be read and cleared. RESET_B is asserted in case of UV, according to OTP reset activation and power up sequence. In case of OV, it is possible to enable or disable the reset for all regulators together by OTP. The reset moves the device to REC state.

•

SPI bit is set and FAULT pin is asserted.

Over current limitation is a cycle by cycle protection: if a fault happens for 7 consequent cycles the FAULT pin is asserted and the corresponding fault bit is set in the SPI register.

If PGND4 ground loss occurs, the regulator is turned OFF and the FAULT pin is asserted. RESET_B is asserted according to OTP reset activation and power up sequence. The device moves to REC state. Until the fault is present and stored any tentative of turning on the regulator is ignored. BUCK4 can be turned on again after the fault removal, Read & Clear cycle.

If this regulator is disabled and not used, VREG4_S and PGND4 pins should be connected to ground.

BOOST

BOOST regulator is a converter running at 2.4 MHz that provides a nominal voltage of 5 V/7 V (selectable via

OTP). Spread Spectrum on PWM is enabled by default and disabled via SPI; a phase shift of 270° versus BUCK1 is internally generated. Soft start time is programmed via SPI. Compensation network is internal.

BOOST regulator provides the following diagnostic:

DS12567 - Rev 2 page 21/85

L5965

Voltage regulators and features description

4.2.7

4.2.8

4.2.9

•

Monitor of the output voltage by an independent circuit for UV/OV detection.

Monitor of the Power Good: thresholds status provided via SPI bit.

Over Current Protection.

Over Temperature detection by a local thermal sensor.

PGND5 loss detection.

BOOST Fault management:

• If a UV/OV fault occurs the FAULT pin is asserted and the fault bit is set in the SPI register, where it can be read and cleared.

•

SPI bit is set and FAULT pin is asserted.

Over current limitation is a cycle by cycle protection: if the fault happens for 7 consequent cycles, the FAULT pin is asserted and the corresponding fault bit is set in the SPI register.

If PGND5 ground loss occurs, the BOOST is turned OFF and FAULT pin is asserted. Until the fault is present and stored any tentative of turning on the regulator is ignored. BOOST can be turned on again after the fault removal, and a Read & Clear cycle.

If this regulator is disabled and not used, VBOOST_S and PGND5 pins should be connected to ground.

LDO

LDO is a low drop out linear regulator with 8 programmable output voltages (5.0 V, 3.3 V, 2.8 V, 2.5 V, 1.8 V, 1.3 V,

1.25 V or 1.2 V) through OTP cell. The input voltage (VSLDO) is compatible to main regulator output (up to 5.5 V).

•

LDO regulator provides the following diagnostic:

• Programmable Over Current limitation in case of over-load or short to ground. Programmable.

Monitor of the output voltage is monitored by an independent circuit for UV/OV detection.

Over Temperature detection by a local thermal sensor.

LDO Fault management:

• In case of OV, the power stage is turned off, the fault SPI bit is set and the FAULT pin is asserted. The power stage is turned on again after a Read & Clear cycle. RESET_B is asserted if enabled by OTP, and it moves the device to REC state.

•

In case of UV, the SPI bit is set and the FAULT pin is asserted. RESET_B is asserted, according to OTP reset activation and power up sequence, and moves the device to REC state.

If OT occurs, the LDO is switched OFF with a 16 µs filter time. The output decreases until UV is detected.

The regulator goes in REC state and can restart only when OT flag is reset. The corresponding SPI bit is set and FAULT pin is asserted.

•

VREF

L5965 includes a 1% precise voltage reference output to supply a system ADC. Output voltage can be selected via OTP cell (4.1 V, 3.3 V, 2.5 V or 1.8 V).

VREF provides the following diagnostic:

Over Current limitation in case of over-load or short to ground.

Monitor of the output voltage by an independent circuit for UV/OV detection.

VREF Fault management:

• In case of OV, the power stage is turned off, the fault SPI bit is set and the FAULT pin is asserted. The power stage is turned on again after a Read & Clear cycle.

• In case of UV, the fault SPI bit is set and the FAULT pin is asserted.

• In case of OC on VREF for 4 ms, the SPI register fault bit is set and VREF turns off. The FAULT pin is asserted. VREF turns on again when OC is removed.

ADC

L5965 includes an Analog to Digital converter (10 bit SAR) to provide via SPI a digital information on internal local thermal sensors (divided in Thermal Clusters THCL) VBAT1 and VBAT2. The voltages are provided sequentially by an analog multiplexer and converted with a t con available every t con

*9.

conversion time: therefore, an update of the ADC value is

DS12567 - Rev 2 page 22/85

L5965

Voltage regulators and features description

4.2.10

4.2.11

The ADC works only in ACTIVE mode. Out of active mode, ADC value of thermal sensors is 10'b1, ADC value of

VBAT1/VBAT2 is 10'b0.

Figure 10. ADC circuit

VBAT1

1000k

VBAT2

3.3V

100k 10pF

TH1

TH2

TH3

TH4

TH5

TH6

TH7

9 Channel

Mux

SPI Register

VREF=2 V

10 Bit

SAR

GAPG2206151659PS

The Thermal Clusters are seven: six are dedicated to every regulators (TH1 → VREG, TH2 → BUCK1, TH3 →

BUCK2, TH4 → BUCK3, TH5 → BUCK4 and BOOST, TH6 → LDO) and one at the center of the die, TH7.

In case of OT, the FAULT pin is asserted.

Wake up pin (WKUP)

The WKUP pin has an internal pulldown resistance. The maximum voltage this pin can sustain is limited to 40 V.

A higher voltage compliance level in the application can be achieved by applying an external series resistor between the WKUP pin and the external wake-up signal.

•

When the device is in STANDBY mode, it can be activated by a voltage above V

WAKE_ON

threshold, with a minimum duration of t

WAKE_FILTER

The device can be moved to STANDBY mode, applying a voltage below V

WAKE_OFF minimum pulse width of t

WAKE_FILTER

threshold, with a

Synchronizing pin (SYNC in/out)

The user can provide an external clock on SYNCIN pin (higher than 1.8 MHz) in order to change the switching frequency of the internal regulators (Buck1,Buck2, Buck3, Buck4 and Boost).

In case an external clock is not provided, SYNCIN can be left floating (with inner pull-down resistor). All regulators work at their default switching frequency or, for Buck2, the frequency selected by OTP.

When a clock at f syncin

frequency is provided on SYNCIN pin:

• Buck1 works at f syncin

/6 if f syncin

>1.8 MHz or 400 kHz (default switching frequency) if f syncin

<1.2 MHz.

•

Buck3, Buck4 and Boost work at f syncin

if f syncin

>1.8 MHz or 2.4 MHz (default switching frequency) if f syncin

<1.2 MHz.

When the frequency of Buck2 is set to 2.4 MHz by OTP, Buck2 works at f syncin

(default switching frequency) if f syncin

<1.2 MHz.

if f syncin

>1.8 MHz or 2.4 MHz

When frequency of Buck2 is set to 400 kHz by OTP, Buck2 works at f syncin

/6 if f syncin

>1.8 MHz or 400 kHz

(default switching frequency) if f syncin

<1.2 MHz.

DS12567 - Rev 2 page 23/85

DS12567 - Rev 2

L5965

Voltage regulators and features description

SYNCIN pin

Figure 11. SYNC IN/OUT in Active mode

IC

in PLL out

Oscillator

2.4 MHz

MUX

Frequency processors

Control logic

Clock for buck & boost

Buffer SYNCOUT pin

Smitter

Frequency detection

Reference frequency

SYNCIN/OUT function in ACTIVE mode

GADG1105180837PS

Figure 12. SYNCOUT output buffer

IC

3.3V inner supply

SYNCOUT

DGND

SYNCOUT output buffer

GADG1105180841PS page 24/85

L5965

Voltage regulators and features description

4.2.12

Reset and Fault

In ACTIVE mode, a reset signal is generated by L5965 at RESET_B pin in case of UV, OV if enabled by OTP, PG loss on Main regulator and Watchdog failure (wrong trigger of WD). Every regulator that can issue a reset, moves

the device to REC state. Reset behavior at Power Up phase is fully described in Section 6 Device operating mode .

Figure 13. Reset circuit diagram in ACTIVE mode

RESET_B pin

Buck1/2_mon_uv

(post)

Buck1/2_mon_uv/ov

(post)

Buck1/2_pg_loss

(post)

Buck3_mon_uv/ov

Buck3_pg_loss

Buck4_mon_uv/ov

Buck4_pg_loss

Ldo_mon_uv/ov

OTP user setup &

SPI control bits

MUX

Buck1/2_mon_uv

(main)

Buck1/2_pg_loss

(main)

Watchdog failure

≥ 1

GAPG2306150942PS

A loss of ground (PGLOSS) asserts RESET_B with the following rules:

if the regulator is disabled by OTP, PGLOSS cannot assert RESET_B;

if the regulator is enabled by OTP, but it is not in the Reset Activation list, PGLOSS cannot assert RESET_B;

if the regulator is enabled by OTP and it is in the Reset Activation list, no matter if it is disabled by SPI,

PGLOSS can assert RESET_B.

•

The undervoltage (UV) asserts RESET_B with the following rules:

• if the regulator is disabled by OTP, UV cannot assert RESET_B; if the regulator is enabled by OTP, but it is not in the Reset Activation list, UV cannot assert RESET_B; it the regulator is enabled by OTP and it is in the Reset Activation list, but it is disabled by SPI, UV cannot assert RESET_B;

• if the regulator is enabled by OTP, it is in the Reset Activation list and it is not disabled by SPI, UV can assert

RESET_B.

The overvoltage (OV) asserts RESET_B in a similar way as the undervoltage, with this additional condition:

• if OvRst_EN is set to 0 through OTP, the OV cannot assert RESET_B.

A FAULT signal is generated in active mode in case of a fault, as shown in Figure 14

• "SPI_parity_fail" refers SPI_PAR_FAIL, Bit2 of SPI fault STAT

• "PowerUp fault" is an error generated by regulators during power-up phase:

– each regulator should complete its own power-up phase up to the power good signal within 20 ms

• "Digital_Bist_err" is an error generated by one of the following checks:

– Buck clock generation

– Logic diagnostics circuit

– Main State Machine

DS12567 - Rev 2 page 25/85

L5965

Voltage regulators and features description

Figure 14. Fault function in active mode

4.2.13

Buck1/2_uv/ov/oc/ot/pg_loss

Boost_uv/ov/oc/ot/pg_pg_loss

Ldo_uv/ov/ot

Vref_uv/ov/oc

Vreg_ot

Centre_ot

Vreg_nok

VBAT1/VBAT2_uv/ov

(read&clear)

All_buck_fault

(read&clear)

Watchdog_fail

(read&clear)

SPI_parity_fail

(read&clear)

PowerUp_fault

Digital_Bist_err

NOR

FAULT pin

‘1’: no fault

‘0’: with fault

GADG1105180907PS

In order to avoid triggering RESET and FAULT during the soft start time, the UV is masked when regulators

(BUCK1/2/3/4, BOOST, LDO and VREF) are going to be enabled. The masking time is given by the following table.

Regulator

BUCK1

BUCK2

BUCK3

BUCK4

BOOST

VREF

LDO

VREG

Table 7. UV masking time

Masking time (ms typ.)

0.5

Configurable watchdog and reset

During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle. When the device is in ACTIVE mode, which means the power up phase has been correctly performed and RESET_B signal has been released, the watchdog is started with a timeout (long open window TLW ) to allow the microcontroller to run its own setup and then to start the window watchdog by setting an inner signal TRIG = 1.

Subsequently, the micro controller has to serve the watchdog by providing the watchdog trigger bit TRIG within the safe trigger area TSW. The trigger time is configurable by SPI. A correct watchdog trigger signal immediately starts the next cycle. A wrong watchdog trigger causes a watchdog failure.

WDI signal can be ignored (by setting OTP bit) and SPI can be used as watchdog: in this case, a specific SPI register must be accessed and toggled by SPI within the watchdog window. If the register is not refreshed at the right time, a watchdog failure happens. In case of a watchdog failure, a RESET_B is always asserted, and the device goes to REC mode or keeps in ACTIVE mode depending on WD_REC_en OTP configuration.

If OTP_WD_REC_en = 1 the device goes to REC mode in case of WD failure, and WD is not more active until the

ACTIVE mode is reached.

If OTP_WD_REC_en = 0, the device keeps in ACTIVE mode in case of WD failure, and WD is inactive for 280 ns

(1 system clock cycle, not significant), then active again in Long open window, and RESET_B asserts a small pulse (typ 8 µs). Moving SPI_WD_REC_en = 1, the device behavior is the same as OTP_WD_REC_en = 1.

Configuration with OTP_WD_REC_en = 0 is useful if voltages should be immediately active in order to initialize the system, regardless of the WD signal.

DS12567 - Rev 2 page 26/85

DS12567 - Rev 2

L5965

Voltage regulators and features description

The following picture illustrates the watchdog behavior.

Long open window

Figure 15. Watchdog behavior

WD is working

WD is stop

Trig=1 WD off Shutdown mode

Window mode

Proper trigger in window mode

WD is stop

WD is working when in ACTIVE mode and OTP bit is enabled

GAPG2306150737PS

The watchdog trigger time is configured by setting SPI. The change of this time is not limited to the Long Open

Window. It can be changed also in "Window mode" state. However, it is suggested to write these bits only during the long window, in order to avoid watchdog failures. Besides, the first trigger time should be < TLW (160 ms), after that, next trigger should happen between (previous _Trigger_ time + TSW_min) and (previous _Trigger_ time

+ TSW_max).

Figure 16. Watchdog timing if WD_REC_en = 1

Normal startup operation and timeout failures

= correct trigger timing

= early trigger timing

= missing trigger

EFW

WDtrigger

EFW

Trigger signal

Time / ms

RESET-B

RSTA

0 Normal operation Missing trigger early write

Time / ms

GADG1105181220PS page 27/85

DS12567 - Rev 2

L5965

Voltage regulators and features description

Figure 17. Watchdog timing if WD_REC_en = 0

Normal startup operation and timeout failures

= correct trigger timing

= early trigger timing

= missing trigger

EFW

WDtrigger

EFW

Trigger signal

Time / ms

RESET-B

RSTT

0 Normal operation Missing trigger early write

Time / ms

GADG1405181212PS

Figure 18. Watchdog Early, Safe and Late window diagram

TSWn = Safe window #1..4

TEFWn = Early Failure window #1..4

TLFWn = Late failure window #1..4

TLFWn_min

TSWn_max

TSWn_min

TEFWn_max

Earl

Watchdog

Failure undefined safe trigger area

GAPG1502160942PS undefined

Late

Watchdog

Failure tim page 28/85

L5965

Voltage regulators and features description

4.2.14

•

Under-Voltage, Over-Voltage and Power-Good

All regulators are monitored, and Power-Good, Over-Voltage and Under-Voltage information is provided through

SPI.

One SPI bit allows to select between two threshold options:

UV/PG/OV of 91%, 95%, 108%

UV/PG/OV of 86%, 90%, 113%

Over-voltage and Power-Good are checked when the signal is rising, the Under-Voltage is valid when the signal is falling.

The next figure shows the relationships among these monitors.

Figure 19. Output voltage and monitors

Falling signal

Rising

signal thresholds

thresholds TYP

Over-Voltage

OV with Hysteresis

Power-Good

PG with Hysteresis

UV with Hysteresis

Under-Voltage

V th th

OV max

OV typ

V OV min

V th

PG max

PG typ

V PG min

V th

OV max

V th th

OV typ + hyst

OV min

VOUT (100%)

V th th

PG max

PG typ+ hyst

PG min

V th

V UV max

UV typ + hyst

V UV min

V th th

V th

UV max

UV typ

UV min

4.2.15

GADG0407181523PS

Temperature control and VBATx voltage through internal ADC

In order to provide an advanced on-chip temperature control, power outputs are grouped in 7clusters with dedicated thermal sensors. The sensors are suitably located on the device. In case the temperature of a cluster reaches the thermal shutdown threshold, the outputs assigned to this cluster are shut down (all other outputs remain active). The central cluster only asserts the FAULT pin. Each output cluster has a dedicated temperature warning and shutdown flag and the cluster temperature can be read out by SPI.

Next table shows voltages referred to ground and currents are assumed positive when the current flows into the pin. T j

= -40 °C to 130 °C.

Table 8. Temperature diode characteristics

Symbol Parameter

TROOM1-7

SENSE

output voltage at 25 °C

Test condition

T = 25 °C

TSENSE1-7

Temperature coefficient for T

SENSE

output voltage T = 25 °C; T = 130 °C;

Min. Typ. Max. Unit

1.335

-4 mV/K

DS12567 - Rev 2 page 29/85

DS12567 - Rev 2

L5965

Voltage regulators and features description

Figure 20. VTSENSE vs. temperature

1.3

1.2

1.1

1.0

1.7

1.6

1.5

1.4

0.9

0.8

0.7

0.6

-40 -20 0

V(TSENSE), MAX.

V(TSENSE), MIN.

V(TSENSE), TYP.

20 40 60 80 100

Temperature (°C)

120 140 160 180

GADG1405181318PS

Cluster temperatures information is available in SPI registers and can be calculated from the binary coded register value using the following formula:

Decimal = VTSENSE ×

1024

VREFADC

− 1

Starting from the following values:

VTSENSE = VTROOM + Tj − 25 × TCTSENSE

Decimal =

358.26 − Tj

0.488

Tj = 358.26 − Decimal × 0.488

We can get this information:

T = -40 °C → decimal code is 816 (0x330, read out from SPI register)

T = 25 °C → decimal code is 683 (0x2AB, read out from SPI register)

Read out SPI register 0x330, means the decimal is 816 → T = -40 °C

Read out SPI register 0x2AB, means the decimal is 683 → T = 25 °C

Also VBATx can be read from 0 to 22 V (above 22 V the ADC output doesn't change):

Decimal = 46.55 × VBATx x = 1,2 − 1

VBATx = decimal + 1

46.55

Example:

BAT1

= 14 V→ decimal code is 651 (0x28B, read out from SPI register)

Read out SPI register 0x28B, means the decimal is 65 → V

BAT1

= 14 V

(1)

(2)

(3)

(4)

(5)

(6) page 30/85

L5965

Voltage regulators and features description

4.2.16

4.2.17

Maximum Duty Cycle and Refresh Mode for Buck

The high-side N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor current reaches its peak value as set by the regulation loop. Once the high side power is turned OFF, and after a small delay (shoot-through delay), the lower N-channel MOSFET is turned on until the start of the next clock cycle.

In dropout operation the high-side MOSFET can stay on 100%. To ensure the bootstrap capacitor is recharged, the buck low-side power is forced off time (140ns) per 4 cycles. It is called “refresh mode”. This forced OFF time limits the maximum duty cycle of the buck to:

Dmax = 1 − fsw ⋅ tOFF ⋅ 0.25

The actual maximum duty cycle varies with the switching frequency.

(7)

Figure 21. Refresh mode in bucks f

SW_buck

PH_buck t

OFF_refresh

4 cycles

GADG0509181611PS

Frequency-Hopping Spread Spectrum

L5965 features a pseudo-random spectrum for 2.4 MHz switching frequency, and a triangular spread architecture for 400 kHz switching frequency. The frequency shifts only by one step at each cycle to avoid large jumps in bucks and boost switching frequencies.

DS12567 - Rev 2 page 31/85

L5965

SPI format and register mapping

Note:

SPI format and register mapping

A 32-bit SPI bus is used for bi-directional communication with the microcontroller, for functional and test purpose.

A write operation leads to a modification of the addressed data by the payload if a write access is allowed (e.g.

control register, valid data). A read operation (based on previous communication request) shifts out the data present in the addressed register (out of frame data exchange protocol).

A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared are defined first by payload bits set to 0. The SPI word is represented in the below figure.

Figure 22. SPI word representation

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DI RW ADDRESS

RSV

CNT DATA WRITE CRC

SPI

ERR

IERR ADDRESS FBACK DATA READ CRC

GAPG2306150958PS

•

DI Stream:

•

Bit 31: R/W flag. To select read (0) or write (1) operation

Bit 30-23: SPI register address

Bit 22: Test Mode flag

Bit 21: Frame counter (0/1). After Power-on reset, this bit must be ‘0’. The bit must be toggled according to the previous SPI CNT bit.

Bit 20-5: Data to be written at selected address

Bit 4-0: CRC code

DO Stream:

•

• Bit 31: Previous SPI communication Error (CRC error, Too long frame, Too short frame, frame count error,

SPI error, CSN low time out) (*)

Bit 30:RSTB (*)

Bit 29: FAULT (*)

Bit 28:21: SPI register address (related to the previous transmission)

Bit 20-5: Data read at selected address (related to previous transmission)

Bit 4-0: CRC code

(*) bit 29 and bit 30 reflect the current status of RSTB pin and FAULT pin. Every time the relevant SPI register is accessed, an internal register will sample the current status of RSTB and FAULT pins, store them, then shift them out on SPI DO frame at next SPI access. If RSTB and Fault bits in ACTIVE mode are `1' , it means there's no reset and no fault.

DS12567 - Rev 2 page 32/85

DS12567 - Rev 2

L5965

SPI format and register mapping

Figure 23. SPI diagram data updated

CSN

CLK

DI data shifted out shift sample

GAPG2306151214PS

•

DO is sampled by the microcontroller on CLK falling edge, DI is sampled by L5965 on CLK falling edge. In case of writing operation selected, internal register is updated at CSN rising edge.

In the below figure SPI protocol is shown:

1 st Frame: Write Access on RW Register X → Register X is updated at the end of the frame.

After the update of register X, the data out shift register is updated too.

2 nd Frame: Read Access → Register X with data Y is shifted out on MISO.

The data out shift register is updated with the same data.

Figure 24. SPI protocol diagram

Data out to be shifted out updated

Write register X, data Y Register X shifted out (data Y)

R/W = 1 R/W = 0 register X updated with data Y

GAPG2306151521PS

To detect frame losses/non-refreshment, Bit21 of DI frame must have opposite values in sequential frames. If a static fault (stuck-at) or cross-talk occurs, the communication data received would not pass the CRC check and will be discarded: FAULT pin is asserted.

If SPI communication has some errors (no matter to which register), the write in data is discarded. In the next SPI communication, DO will automatically read out 0x1D register address and data-in order to give details on SPI error.

Symbol

CSNLOW

CSNHIGH

CSNHYS

CSNPU

Parameter

Input voltage low level

Input voltage high level

CSNHIGH

- V

CSNLOW

Internal pull up resistor

Table 9. Input CSN

Test condition

Normal mode

Min.

–

2.3

0.2

–

Typ.

–

0.4

800

Max.

–

Unit

V kΩ page 33/85

DS12567 - Rev 2

L5965

SPI format and register mapping

Symbol

V in L

V in H

V in Hyst

I in

C in f

CLK

Parameter

Input low level

Input high level

Input hysteresis

Pull down current at input

Input capacitance at input pins CSN, CLK, DI

SPI input frequency at CLK

Table 10. Input CLK, DI

Test condition

–

V in

= 1.5 V

Guaranteed by design

–

Min.

Typ.

Max.

Unit

– – 1 V

2.3

0.2

–

0.4

–

µ A

–

1 pF

MHz

Table 11. DI, CLK and CSN timing

Symbol t

CLK t

CLKH t

CLKL t set CSN t set CLK t set DI t hold DI t t r in f in

Parameter

Clock period

Clock high time

Clock low time

CSN setup time, CSN low before rising edge of CLK

CLK setup time, CLK high before rising edge of CSN

DI setup time

DI hold time

Rise time of input signal

DI, CLK, CSN

Fall time of input signal

DI, CLK, CSN

–

Test condition

500

Min.

Typ.

Max.

Unit

1000

400

–

– ns ns ns

–

– ns ns ns ns

–

25 ns ns

Symbol

DOL

DOLK

Output low level

Parameter

Open Drain leakage current

Open Drain input capacitance

Table 12. Output DO

Test condition

= -4 mA

When DO output=high

Guaranteed by design

Symbol t

CSN_HI,min t

CSNfail

Parameter

Minimum CSN high time

Active mode

CSN low timeout

Table 13. CSN timing

Test condition

Transfer of SPI-command to Input Register

–

Min.

–

-5

–

Typ.

–

Max.

0.3

Unit

µA pF

Min.

Typ.

Max.

Unit

6 – – µs

20 35 50 ms page 34/85

5.1

L5965

SPI frame CRC generator

The SPI protocol is defined by frames of 32 bits with 5 bits of CRC (Cyclic Redundancy Check) in both input and output directions. The polynomial calculation implemented is: g(x)= x^5 + x^2 + 1 the structure of CRC generator is shown in

Figure 25. Structure of CRC generator .

Here are the rules:

For DI, CNT=DI[21] is ignored when calculating CRC, it means only {DI[31:22],DI[20:5]} is used to calculate

CRC. For example, if DI[31:5]=27‘b1000_0010_1011_1111_1111_1111_111, the CRC[4:0]= 5‘b0_0011

For DO, DO[21] is ignored when calculating CRC, it means only {DO[31:22],DO[20:5]} is used to calculate

CRC.

The initial value of CRC generator is 5'b1_1111.

MSB (DI[31]) is shift in CRC generator at first.

Figure 25. Structure of CRC generator

MOSI

XOR BIT4 BIT3 BIT2 XOR BIT1 BIT0

GAPG2402160858PS

5.2

SPI registers mapping

When registers are not written, their default state is the one shown in the respective map.

SPI REG BUCK1

5.2.1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

R/W

Address 0x00

BUCK1_CUR_MAX: Driver max output current (see BUCK1 GATE Driver )

BUCK1_XTH: OV/UV/PG threshold setting (see Power output UV/OV monitor

Power Good )

BUCK1_SPREAD_EN: Spread spectrum enable

BUCK1_BLANKTIME: Output power stage blanking time (see

tprogramming_dead_BUCK1 )

BUCK1_SSCLK_SEL: SoftStart time selection (see tSOFTSTART_BUCK1 )

DS12567 - Rev 2 page 35/85

L5965

SPI registers mapping

5.2.2

SPI REG BUCK2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RESERVED

R/W

Address 0x01

5.2.3

BUCK2_XTH: OV/UV/PG threshold setting (see Power output UV/OV monitor

Power Good )

BUCK2_SPREAD_EN: Spread spectrum enable

BUCK2_OUTPUT_SR: Output stage slew rate (see tSR_PH2

)

BUCK2_SSCLK_SEL: SoftStart time selection (see tSOFTSTART_BUCK2 )

SPI REG WD_REC_EN

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RESERVED

0 0

R/W

Address 0x02

SPI_WD_REC_EN: In case OTP_WD_REC_EN=1, WD failure asserts RESET_B and makes FSM go to REC state.

DS12567 - Rev 2 page 36/85

L5965

SPI registers mapping

5.2.4

SPI REG BUCK4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RESERVED

R/W

Address 0x03

5.2.5

BUCK4_XTH: OV/UV/PG threshold setting (see Power output UV/OV monitor

Power Good )

BUCK4_SPREAD_EN: Spread spectrum enable

BUCK3_SSCLK_SEL: SoftStart time selection (see tSOFTSTART_BUCK4 )

SPI REG BOOST VREF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RESERVED

R/W

Address 0x04

VREF_XTH: OV/UV/PG threshold setting (see Power output UV/OV monitor

Power Good )

BOOST_XTH: OV/UV/PG threshold (see

Power output UV/OV monitor , Power Good )

BOOST_SPREAD_EN: Boost spread spectrum enable

LDO_XTH: OV/UV/PG threshold setting (see Power output UV/OV monitor

Power Good )

BOOST_SSCLK_SEL: Boost SoftStart time selection (see tSS_BOOST )

DS12567 - Rev 2 page 37/85

L5965

SPI registers mapping

5.2.6

SPI REG BUCK EN

15 14 13 12 11 10

R/W

RESERVED

8 7 6 5 4 3 2 1 0

R/W

Address 0x05

5.2.7

VBAT1/2_EN: VBAT UV/OV detection Enable

(Others)_EN SPI Regulators Enable/Disable (only in ACTIVE Mode)

SPI REG WD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

R/W

Address 0x06

WD_TWIN: WatchDog Window timer selection (see Watchdog trigger time

)

TWK_REC: WKUP high duration timer selection (see

WKUP )

INF_RETRIAL_EN: 0: finite restart trials

1: infinite restart trials (default)

FAULT_TOGGLE: fault pin toggle test bits

101: set fault pin 'low';

110: set fault pin 'high'; others: keep fault pin as original fault output.

SPI_WDI: If SPI bit is used as WatchDog Input, SPI need to toggle this bit in WatchDog time windows. This bit has default value 0.

DS12567 - Rev 2 page 38/85

L5965

SPI registers mapping

5.2.8

SPI REG BUCK STAT1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address 0x10

5.2.9

[15:0] '0' means no fault present: read&clear bits

SPI REG BUCK STAT2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address 0x11

[15:0] 0: means no fault present: read & clear bits

DS12567 - Rev 2 page 39/85

L5965

SPI registers mapping

5.2.10

SPI REG Fault Table PWUP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address 0x12

XX_POWERUP_FAULT: 1: means Power-on failed

0: means Power-on succeeded or regulator disabled by OTP

VREG_NOK_STAT: Vreg not ok state; read and clear.

0: vreg ok;

1: vreg not ok

REC_CNT: the counter of times that FSM into REC; will be cleared in STANDBY. If inf_retrail_en=1, REC_CNT is always 0.

RESERVED (Bit11): this bit is reporting the internal PLL locking status. When "1", the output frequency of the PLL is locked and stable. When "0", the PLL is not yet stable or off.

WD_FAIL: watchdog fail flag, read and clear; Include normal WDI WD or SPI WD.

0: no fail

1: fail

ABIST_ERR: ABist fail flag, read only.

0: no fail

1: fail

SAF_CRC_FAILED: read only.

0: no fail

1: fail

LBIST_ERR: read only.

0: no fail

1: fail

DS12567 - Rev 2 page 40/85

L5965

SPI registers mapping

5.2.11

SPI REG ADC TH1

14 13 12

RESERVED

R R

0 0

5 4

ADC_TH1

R R

1 1

Address 0x13

5.2.12

ADC_TH1: ADC bits output for TH1 cluster (VREG); read only

SPI REG ADC TH2

14 13 12

RESERVED

5 4

ADC_TH2

Address 0x14

5.2.13

ADC_TH2: ADC bits output for TH2 cluster (BUCK1); read only

SPI REG ADC TH3

14 13 12

RESERVED

5 4

ADC_TH3

Address 0x15

5.2.14

ADC_TH3: ADC bits output for TH3 cluster (BUCK2); read only

SPI REG ADC TH4

14 13 12

RESERVED

R R

0 0

5 4

ADC_TH4

R R

1 1

DS12567 - Rev 2 page 41/85

L5965

SPI registers mapping

Address 0x16

5.2.15

ADC_TH4 ADC bits output for TH4 cluster (BUCK3); read only

SPI REG ADC TH5

13 12

RESERVED

5 4

ADC_TH5

3 2

Address 0x17

5.2.16

ADC_TH5: ADC bits output for TH5 cluster (BUCK4 and BOOST); read only

SPI REG ADC TH6

13 12

RESERVED

5 4

ADC_TH6

3 2

Address 0x18

5.2.17

ADC_TH6: ADC bits output for TH6 cluster (LDO); read only

SPI REG ADC TH7

14 13 12

RESERVED

R R

0 0

5 4

ADC_TH7

R R

1 1

Address 0x19

ADC_TH7: ADC bits output for TH7 cluster (Center of the DIE); read only

DS12567 - Rev 2 page 42/85

L5965

SPI registers mapping

5.2.18

SPI REG ADC VBAT1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ADC_VBAT1

Address 0x1A

5.2.19

ADC_VBAT1: ADC output for VBAT1 voltage (see

Figure 10. ADC circuit

); read only

VBAT1_OV_STAT: VBAT1 status; read & clear

VBAT1_UV_STAT: VBAT1 status; read & clear

SPI REG ADC VBAT2

8 7

15 14 13

RESERVED

12 11 10

VBAT2

_UV_S

TAT

VBAT2

_OV_

STAT

0 0

5 4

ADC_VBAT2

2 1 0

Address 0x1B

ADC_VBAT2: ADC output for VBAT2 voltage (see

Figure 10. ADC circuit

); read only

VBAT2_OV_STAT: VBAT2 status; read&clear

VBAT2_UV_STAT: VBAT2 status; read&clear

DS12567 - Rev 2 page 43/85

L5965

SPI registers mapping

5.2.20

SPI REG OT Warning

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

R R R R R R R R R

0 0 0 0 0 0 0 0 0

Address 0x1C

5.2.21

[6:0] Thermal warning from all the Thermal Clusters; read & clear

SPI Fault STAT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

Address 0x1D

SPI_FRAME_LONG: SPI frame length error; read & clear

SPI_FRAME_SHORT: SPI frame length error; read & clear

SPI_PAR_FAIL: SPI frame CRC fail; read & clear

SPI_FRAME_CNT_FAULT: SPI frame error on Count bit; read & clear

SPI_ADDRESS_ERR: SPI frame address error; read & clear

CSN_LOW_TIMEOUT_FAIL: 0: Csn right;

1: Csn low time longer than 35 ms; read & clear

DS12567 - Rev 2 page 44/85

L5965

SPI registers mapping

5.2.22

SPI Silicon Version

15 14 13

FSM_STATUS

R R

0 0

11 10

FSM2REC

7 6 5

TOREC_REASON_FLAG

R R R

0 0 0

2 1

SILVERSION

R R

0 0

Address 0x20

SILVERSION: read only ("0000" means 'AA' version)

FSM_STATUS: read only

0001: Shutdown

0010: StandBy

0011: INIT

0100: RampUP_Main

0101: Secup

0110: Active

0111: Rec

1000: Test

1001: OTP_Prog

FSM2REC: read & clear. State machine status before going into REC mode.

000: default value after reset release or R&C;

001: INIT, means the state machine moved from INIT mode to REC mode;

010: RAMPUP MAIN, means the state machine moved from RAMPUP MAIN mode to REC mode;

011: SECUP, means the state machine moved from SECUP mode to REC mode;

100: ACTIVE, means the state machine moved from ACTIVE mode to REC mode;

TOREC_REASON_FLAG: read & clear. The reason that make state machine jump to REC.

When FSM2REC is INIT:

Bit4 = 1: lbist_fail flag makes state machine from INIT to REC.

Bit5 = 1: abist_fail flag makes state machine from INIT to REC.

Bit6 = 1: mbuck_pgndloss flag makes state machine from INIT to REC.

Bit7 = 1: saf_crc_fail flag makes state machine from INIT to REC.

When FSM2REC is RAMPUP MAIN:

Bit4 = 1: lbist_fail flag makes state machine from RAMPUP MAIN to REC.

Bit5 = 1: main_buck_fail flag (main PG=0 & timer expired) makes state machine fromRAMPUP MAIN to REC.

Bit6 = 1: main_buck_pg_loss makes state machine from RAMPUP MAIN to REC.

When FSM2REC is SECUP:

Bit4 = 1: lbist_fail flag makes state machine from SECUP to REC.

Bit5 = 1: mbuck_PG=0 flag makes state machine from SECUP to REC.

Bit6 = 1: mbuck_pgndloss flag makes state machine from SECUP to REC.

Bit7 = 1: vreg_ot flag makes state machine from SECUP to REC.

DS12567 - Rev 2 page 45/85

L5965

SPI registers mapping

5.2.23

When FSM2REC is ACTIVE:

Bit4 = 1: lbist_fail flag makes state machine from ACTIVE to REC.

Bit5 = 1: mbuck_PG=0 or vreg_ot flag makes state machine from ACTIVE to REC.

Bit6= ’1’ => mbuck_pgndloss flag makes state machine from ACTIVE to REC.

Bit7 = 1: SECUP fail=3 flag makes state machine from ACTIVE to REC.

Bit8 = 1: Rstb fail.

SPI Device Identification

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED OTP_DEVICE_IDENTIFICATION

Address 0x21

OTP DEVICE IDENTIFICATION: Digital circuit auto download the information from OTP to this register when chip power up. Read only.

The default value will be all 0 if OTP is not configured.

OTP_WD_REC_EN: Digital circuit auto download the information from OTP to this register when chip power up. Read only.

The default value will be all 0 if OTP is not configured.

DS12567 - Rev 2 page 46/85

L5965

Device operating mode

Device operating mode

L5965 can work in different operative modes according to input/SPI signals, OTP/SPI settings, fault management and regulators status.

Figure 26. State machine

Power on

SHUTDOWN

VBAT 1<Vpor

VBAT 1>Vpor

& OTP_PrimID!=000

& OTP_DL_END=1

VBAT 1>Vpor

& OTP_PrimID=000

& OTP_DL_END=1 STANDBY

OTP programming

WKUP pin high

WKUP pin low

WKUP high >Twk_rec

& REC_CNT* inv(inf_retrial_en)<3

WKUP pin low

INIT nok

INIT

INIT ok & main VBAT > Vok

Timer

WKUP pin low

REC Main fail

(main PG=0 & timer expired) main PGND loss

RAMPUP

MAIN

Main ok

(main PG = 1 before timer expired)

Main fail

(main PG=0

Or main PGND loss)

Main fail

(main PG=0

Or main PGND loss)

SECUP fail=3

WD_RST &

WD_REC_en=1

SEC

Sec up end

RST fail

(except WD_RST)

SECUP fail<3

ACTIVE

WD fail &

WD_REC_en=0(default)

GADG1405181520PS

DS12567 - Rev 2 page 47/85

L5965

Shutdown mode

6.1

6.2

6.3

6.4

6.5

Shutdown mode

In Shutdown Mode supply batteries (VBAT1/VBAT2/VINx) are not present and all regulators are OFF.

A rising edge on VBAT1 line (higher than Power On Reset threshold) moves L5965 to STANDBY Mode.

Standby mode

In Standby mode, all the regulators are OFF, RESET_B is asserted and current consumption is very low. A low to high transition on WKUP pin moves the IC to INIT Mode. If VBAT1 falls below POR threshold, the device goes back to Shutdown Mode.

INIT mode

•

In INIT mode all the functional checks on analog and digital circuitry are performed:

• OTP program checksum: data integrity is verified and OTP WR bit is checked

•

Analog BIST on Voltage monitors (UV/OV)

Analog BIST on Temperature monitors

RESET_B assertion and path is checked

Digital BIST

Check if main VBAT is ok

Main regulator GND LOSS comparator is active.

DBIST is always active, not only in INIT mode. In INIT mode, in case of issues during DBIST, the IC moves to

REC mode. Outside INIT mode, in case of issues during DBIST, the FAULT pin is asserted.

Besides, DBIST includes:

Buck clock generation check;

Logic diagnostics;

Main State Machine check.

If all the checks are completed without any fail, L5965 moves to RAMPUP mode. In case of fail, the device moves from INIT to REC state and the FAULT pin is asserted. A transition (High to Low) on WKUP moves the state machine back to STBY, where the FAULT pin is de-asserted.

REC mode

L5965 goes to REC mode (recovery state) in case the Main Regulator or a regulator associated with the reset activation fails. When the IC moves from active to stand-by state, the power down phase is activated. When the

IC moves from the active to REC state, all regulators switch off at the same time.

In this state, the FAULT pin is asserted and RESET_B is kept low. There are 2 ways to move the device out of

REC:

A transition High to Low on WKUP pin moves the IC back to STANDBY, where the FAULT pin is de-asserted.

If WKUP pin is kept High for a time longer than Twk_rec and the IC goes in REC mode less than a number of times (3 times if inf_retrial_en = 0, infinite times if inf_retrial_en = 1), then the device moves from REC to

INIT and restarts again.

When the chip enters the REC mode, the IC is switched off. The outputs of the SMPS decrease slowly in order to be ready for next power up phase. The outputs of the SMPS are pulled down to 0 V by an inner pull-down current.

The pull-down current of each regulator is typically 12 mA.

RAMPUP MAIN and SEC_UP

In RAMPUP MAIN status, the main regulator (selected by OTP bit) is turned on: when this phase ends, the state machine moves to SEC_UP status where all secondary regulators are turned ON following the Power Up sequence programmed by OTP. When the last regulator has finished its power up phase, device moves to

ACTIVE Mode, where SPI communication is allowed: all regulators that have to be turned on by SPI command can now be enabled.

WKUP pin is not monitored in these transition phases.

Reset signal release is programmed via OTP: three OTP bits associate the reset signal to a regulator.

DS12567 - Rev 2 page 48/85

L5965

RAMPUP MAIN and SEC_UP

A regulator is a “reset associated regulator” if it can issue a reset signal. This is decided by OTP. RESET_B deasserts only when the Power Good signals of all the “reset associated regulators” are high.

When a regulator starts the power up phase, a dedicated timer, whose duration is typically of 20ms, is started: if the Power Good signal goes high before the time expires, then the state machine moves to the next regulator in the sequence (after the OTP programmed delay). If the time expires and the Power Good is still low, then the correspondent regulator power up phase is considered failed.

We can have two possible scenarios, depending on the regulator type (Main, or reset associated, or Post):

• Main BUCK power up phase fails: the FAULT pin is asserted, RESET_B is kept low and the device goes to a safe state (called REC state) waiting for a WKUP falling down transition to go back to STANDBY.

• Reset associated regulator or Post regulator power up phase fails: the FAULT pin is asserted, RESET_B signal is kept low and SEC_UP phase is completed for the other regulators. Once the device has moved to the ACTIVE state, it immediately goes back to SEC_UP state to retry to turn on the failed regulator. The retry phase is done three times: if the fail is still present, then the device moves to REC state.

DS12567 - Rev 2 page 49/85

DS12567 - Rev 2

Figure 27. State machine for SEC UP

RAMPUP

MAIN

SECUP

SECUP fail <3

2 nd REG

2 nd reg ok

(2 nd

PG = 1 before timer expired) or time expired

3 rd REG

3 rd reg ok

(3 rd PG = 1 before timer expired) or time expired

4 th REG

L5965

RAMPUP MAIN and SEC_UP last REG last reg ok

(last PG = 1 before timer expired) or time expired

Active

GADG1405181539PS page 50/85

6.6

6.7

L5965

ACTIVE mode

In ACTIVE Mode the regulators are ON and the device is controlled by SPI: SPI communication is active only in this state. All the regulators, except the Main regulator and the ones disabled via OTP (ENx = 0), can be turned on and off via SPI; if the device goes out from ACTIVE mode, OTP power up phase is recovered.

If a fault occurs, the device can stay in ACTIVE Mode or move to REC, depending on the regulator involved and the kind of fault.

• A fault that asserts RESET_B moves the IC to the REC phase. WD failure asserting RESET_B depends on

OTP bit WD_REC_en: if WD_REC_en=1, L5965 moves to REC phase;

• if WD_REC_en=0, L5965 keeps in ACTIVE mode.

WKUP pin is continuously monitored: if the signal goes low after a filtering time, then L5965 goes back to

STANDBY state after proper Power Down phase.

When the IC is switched on for the first time, supplying VBAT1 and/or VBAT2, a fault is asserted by VBAT1_uv or

VBAT2_uv. That’s not a real fault, and it can be cleared by an SPI read&clear command.

OTP program mode

L5965 needs a programming phase of OTP (One Time Programmable) cells before starting any operation: this is allowed by providing battery line higher than 17 V (~20 V) at VBAT1 pin, together with a dedicated SPI word.

DS12567 - Rev 2 page 51/85

L5965

OTP program mode

Figure 28. OTP program flow chart

SAF_BCD8SAUTO_DTI

Program start

Burn a row of OTP

Read this row of OTP

Discard Die

Read

OK?

All rows of

OTP are burned?

DS12567 - Rev 2

SAF_BCD8SAUTO_DTI

Program end

GADG1505180834PS

After power-on release, the SAF (Antifuse cell) FSM (Finite State Machine) starts to download all SAF rows to internal DFFs. When the auto download has finished, if Prim Id (bit15~13, ROW9) are “000”, the FSM will go to

OTP program mode for customer usage.

In this mode, the user could program/burn SAF rows:

• Write data to SAF_REG_DI via SPI

• Set SAF parameter in SAF_REG_CFG via SPI

The program/burn command should be sent to SAF_REG_OP via SPI, then the data in SAF_REG_DI will be burned in SAF cells.

USR_ Area _PROTECTION (bit15~13 of ROW12) is used to protect SAF rows from re-burning; when the bits are

“111”, the burning command for USR SAF rows can’t be executed. So the Row12 must be the last one to be burned in the USR Area.

In OTP program mode, the saf_addr should be from 8~12; otherwise the saf_opration_error flag will be set.

page 52/85

L5965

OTP program mode

Table 14. OTP row programming shows the detailed instructions on how to program an OTP row.

Table 14. OTP row programming

Step

Enter

OTP prog mode

Description

Power on device. If OTP has not been burned yet, the device goes to OTP program mode

Power on device.

Action

Burn

OTP

In this step, selected words

(indicated as data1) must be written to a selected row of

OTP (address indicated as row_addr)

SPI Frame

Write register SAF_REG_DI = “data1” via SPI.

Note: bit15~13 of this register is crc of data1, it is auto calculated by digital circuit.

Write register SAF_REG_CFG=“0x7000” via SPI; note: saf_hv_en_force_decoding (bit14~bit12 of this register) should be set to "111", otherwise the burn operation is forbidden.

Send burn command and address of selected row of OTP.

Write register SAF_REG_OP=“0x001[row_addr]” via SPI

Wait end of write procedure, then read register

SAF_REG_STAT via SPI. For first reading, don’t care DO frame.

DI frame:

Bit31=’1’, bit30~23 =“0x32”,

Bit22=’1’, bit21=’0’, bit20~5=data1, bit4~0=CRC.

DI frame:

Bit31=’1’, bit30~23 =“0x31”,

Bit22=’1’, bit21=’1’, bit20~5=“0x7000”, bit4~0=CRC.

DI frame:

Bit31=’1’, bit30~23 =“0x30”,

Bit22=’1’, bit21=’0’, bit20~11=“0x000”,

Bit10~9=”01”,

Bit8~5=”row_addr”, bit4~0=CRC.

DI frame:

Bit31=’0’, bit30~23 =“0x34”,

Bit22=’1’, bit21=’1’, bit20~5=”--”, bit4~0=CRC.

Read register SAF_REG_STAT via SPI again.

Saf_busy (bit4 of this register)=’1’ indicates burn operation is not finished, then wait a moment and read this register again.

Saf_busy =’0’ indicates burn operation is finished.

Saf_opration_error (bit6 of this register) =’0’ indicates the burn operation is valid, otherwise invalid.

DI frame:

Bit31=’0’, bit30~23 =“0x34”,

Bit22=’1’, bit21=’0’, bit20~5=”--”, bit4~0=CRC.

DO frame:

Check if bit28~21=“0x34”,

If bit9=’0’, if bit11=’0’.

DS12567 - Rev 2 page 53/85

L5965

OTP bit mapping and register configuration

Step

Read

OTP

6.8

Description

In this step, read the selected row of OTP

Action

Write register SAF_REG_CFG=“0xXXXX” via SPI;

This is not necessary, you can skip it if you keep saf_r_code default.

SPI Frame

Send read command and address of selected row of OTP.

Write register SAF_REG_OP=“0x002[row_addr]” via SPI

DI frame:

Bit31=’1’, bit30~23 =“0x30”,

Bit22=’1’, bit21=’1’, bit20~11=“0x000”,

Bit10~9=”10”,

Bit8~5=”row_addr”, bit4~0=CRC.

Read register SAF_REG_STAT via SPI. For first reading, don’t care DO frame.

Get read back data on next DO frame, and then check if reading operation is finished (saf_busy=0) and crc of OTP is ok (saf_crc_ok=1/ status_crc_glb=1).

Read register SAF_REG_DO_Bit_Ts via SPI again, then get the read back data of this register on DO frame.

DI frame:

Bit31=’0’, bit30~23 =“0x34”,

Bit22=’1’, bit21=’0’, bit20~5=”--”, bit4~0=CRC.

DI frame:

Bit31=’0’, bit30~23 =“0x33”,

Bit22=’1’, bit21=’1’, bit20~5=”--”, bit4~0=CRC.

Read register SAF_REG_DO_Bit_Ts via SPI. For first reading, don’t care DO frame.

DO frame (read back data of

SAF_REG_STAT):

Check if bit28~21=“0x34”,

If bit9=’0’, if bit8=’1’, if bit7=’1’.

DI frame:

Bit31=’0’, bit30~23 =“0x33”,

Bit22=’1’, bit21=’0’, bit20~5=”--”, bit4~0=CRC.

Note: bit15~13 of this register is crc of data1, it needs to be checked.

DO frame:

Check if bit28~21=“0x33”,

If bit20~5=”“data1”.

OTP bit mapping and register configuration

Figure 29. OTP bit mapping

15 14 13 12 11 10

Reset activation

Prim Id

SeqId BUCK4

SeqId LDO

USR Area Protection

9 8 7 6

Device identification

Non Prim SeqId

SeqId BUCK3

SeqId BOOST

BUCK2 CFG

BUCK4 CFG OvRst EN

EnLDO EnBOOST

OTP_WD_REC_en

LDO CFG

SeqId VREF PowrOn Delay EnVREF WDG CFG

5 4 3

BUCK1 CFG

EnBUCK4 EnBUCK3

BUCK3 CFG

BOOST CFG

VREF CFG

2 1 0

CRC

GADG1505180950PS

DS12567 - Rev 2 page 54/85

L5965

OTP bit mapping and register configuration

Figure 30. Programmed configuration

15 14 13 12 11 10

Reset activation

Prim Id

SeqId BUCK4

SeqId LDO

USR Area Protection

9 8 7 6

Device identification

Non Prim SeqId

SeqId BUCK3 BUCK4 CFG

OTP_WD_REC_en

BUCK2 CFG

OvRst EN

SeqId BOOST

SeqId VREF

EnLDO EnBOOST

PowrOn Delay EnVREF

LDO CFG

WDG CFG

5 4 3

BUCK1 CFG

EnBUCK4 EnBUCK3

BUCK3 CFG

BOOST CFG

VREF CFG

2 1 0

CRC

GADG1505180950PS

Table 15. Reset activation OTP

Bit Nb Name

Row 8

Bit15:13 Reset_activation<2:0>

(1)

Description

Reset release

000: Reset release after PGOOD of Main BUCK with a delay set by PowrOn Delay

001: Reset release after PGOOD of the 2nd regulator with a delay set by PowrOn Delay

010: Reset release after PGOOD of the 3rd regulator with a delay set by PowrOn Delay

011: Reset release after PGOOD of the 4th regulator with a delay set by PowrOn Delay

100: Reset release after PGOOD of the 5th regulator with a delay set by PowrOn Delay

101: Reset release after PGOOD of the 6th regulator with a delay set by PowrOn Delay

110: Reset release after PGOOD of the last regulator with a delay set by PowrOn Delay

111: Reset release when ACTIVE state is reached (unconditional Reset release)

1. All regulators switched on before the Reset is released are considered part of the "Reset activation list"

Bit Nb

Row 8

Bit12:7

Name

Device_id<5:0>

Table 16. Device identification OTP

Description

Custom information. It can be read out by SPI.

Table 17. WD_REC_en OTP

Bit Nb Name Description

Row 8

Bit6

OTP_WD_REC_en<0>

When OTP bit = 0, SPI bit = 0 make a WD failure to assert RESET_B but not affect the FSM.

All regulators keep running in active mode. If the SPI bit = 1 WD failure asserts RESET_B and makes FSM go to REC state.

When OTP bit = 1, a WD failure asserts RESET_B and makes FSM go to REC state.

DS12567 - Rev 2 page 55/85

DS12567 - Rev 2

L5965

OTP bit mapping and register configuration

Bit num

Row 8

Bit5:3

Name vsel<2:0>

Table 18. Buck1 CFG

Output Voltage selection

000: 5.0 V

001: 3.8 V

010: 3.3 V

011: 1.8 V

100: 1.2 V

101: 1.1 V

110: 1.0 V

111: 0.8 V

Description

Table 19. Primary activation OTP

PrimId

"101"

"110"

“110”

"001"

"010"

"000 | 011 | 100 |

111"

Non Prim SeqId

[001:110]

"111"

“000”

[001:110]

“111”

“000” any any

EnBuck1 EnBuck2 Note

FSM=ON SPI=CH

FSM=OFF SPI=CH

FSM=ON, SPI=CH Buck1 is primary, Buck2 is enabled by FSM

FSM=OFF,

SPI=CH

Buck1 is primary, Buck2 can be enabled by

SPI

Error

Buck2 is primary, Buck1 can be enabled by

FSM

Buck2 is primary, Buck1 can be enabled by

SPI

Error

Buck2 is primary, Buck1 is disabled

Buck1 is primary, Buck2 is disabled any 0 0 Error

Bit num

Row 9

Bit9

Row 9

Bit8

Row 9

Bit7:5

Name freqsel<0> cursel<0> vsel<2:0>

Table 20. Buck2 CFG

Description

Free Running Frequency selection

0: 0.4 MHz

1: 2.4 MHz

Max current selection

0: 1.5 A

1: 3.0 A

Output Voltage selection

000: 5.0 V

001: 3.6 V

010: 3.3 V

011: 1.5 V

100: 1.35 V

101: 1.2 V

110: 1.1 V

111: 1.0 V page 56/85

DS12567 - Rev 2

L5965

OTP bit mapping and register configuration

EnBuck4 enable of buck4

0: disable

1: enable

EnBuck3 enable of buck3

0: disable

1: enable

Table 21. Enables

EnLDO enable of LDO

0: disable

1: enable

EnBoost enable of Boost

0: disable

1: enable

EnVREF enable of VREF

0: disable

1: enable

Bit Nb

–

Name

Table 22. SeqId Buck4, Buck3, LDO, Boost, Vref OTP

SeqID_x<2:0>

(x=buck4, buck3, ldo, boost, vref)

Description

000: regulator is turned on only by SPI enable signal

001: regulator is turned on after Main regulator (second regulator)

010: regulator is turned on as third one

011: regulator is turned on as fourth one

100: regulator is turned on as fifth one

101: regulator is turned on as sixth one

110: regulator is turned on as seventh one

111: regulator is turned on only by SPI enable signal

Bit num

Row 10

Bit9:7

Name vsel<2:0>

Table 23. Buck4 CFG

Output voltage selection

000: 3.3 V

001: 1.8 V

010: 1.35 V

011: 1.3 V

100: 1.25 V

101: 1.2 V

110: 1.12 V

111: 1.1 V

Description

Bit num

Row 10

Bit6

Name

OvRst_EN<0>

Table 24. OvRst_EN

Description

OV assert RESET_B enable for all regulators except BOOST and VREF

0: no OV of regulator can assert RESET_B;

1: the OV of regulator that is in the reset activation list can assert RESET_B.

page 57/85

DS12567 - Rev 2

L5965

OTP bit mapping and register configuration

Bit num

Row 10

Bit5:3

<1:0>

Name vsel<2:0>

Table 25. Buck3 CFG

Output voltage selection

000: 3.3 V

001: 2.5 V

010: 2.3 V

011: 2.0 V

100: 1.8 V

101: 1.35 V

110: 1.2 V

111: 1.0 V

Description

Bit num

Row 11

Bit7

Row 11

Bit6:4

Bit num

Row 11

Bit3

Name cursel<0> vsel<2:0>

Table 26. LDO CFG OTP

Maximum current selection

0: 0.299 A

1: 0.599 A

Output Voltage selection

000: 5.0 V

001: 3.3 V

010: 2.8 V

011: 2.5 V

100: 1.8 V

101: 1.3 V

110: 1.25 V

111: 1.2 V

Description

Name vsel<0>

Table 27. Boost CFG OTP

Output Voltage selection

0: 5.0 V

1: 7.0 V

Description

Bit num

Row 12

Bit15:13

Name

Table 28. USR Area Protection OTP

Usr_area_protection<2:0>

Description

Rewrite protection.

111: the User SAF rows couldn’t be burned or simulated;

Others: the User SAF rows could be burned or simulated

Table 29. PowrOn Delay OTP time (ms)

2 (min 1.49, max 2.3) page 58/85

DS12567 - Rev 2

L5965

OTP bit mapping and register configuration

<1:0>

11 time (ms)

5 (min 4.04 max 5.75)

10 (min 8.29 max 11.5)

Bit num

Row 12

Bit6:5

Bit num

Row 12

Bit4:3

Name

Wd_cfg<1:0>

Table 30. WDG CFG OTP

Description

Output Voltage selection

00, 01: use hardware watchdog (WDI pin)

10: no watchdog

11: use SPI as watchdog

Name vsel<1:0>

Table 31. VREF CFG OTP

Output Voltage selection

00: 1.8 V

01: 2.5 V

10: 3.3 V

11: 4.1 V

Description

Figure 31. OTP start-up state check

Power on

SHUTDOWN

VBAT1 > Vpor

&OTP_PrimID!=000

VBAT 1< Vpor

VBAT1 > Vpor

&OTP_PrimID=000

&OTP_DL_END=1

&OTP_DL_END=1 STANDBY

OTP programming

WKUP pin low

REC

GAPG2302160823PS page 59/85

L5965

OTP (SAF) registers

6.9

6.9.1

OTP (SAF) registers

SAF_REG_OP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RESERVED SAF_CMD SAF_ADDR

R/W

Address 0x30

[3:0] SAF_ADDR: SAF row address

[5:4] SAF_CMD: SAF opt command

01: burn / write

10: read

11: simulation

[11:6] RESERVED

[12] SAF_AUTO_DL_FORCE: SAF auto download bit. When auto download is finished, this bit will be cleared to '0'. This register is only accessible in TM and OTP Program mode.

Note: In OTP program mode, 8/9/10/11/12 (USR ROWs) are valid for SAF_ADDR;

Writing operation to this register generates SAF_TRIG pulse (if SAF_CMD is valid op);

The auto download has higher priority.

DS12567 - Rev 2 page 60/85

L5965

OTP (SAF) registers

6.9.2

SAF_REG_CFG

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RESERVED

R/W

Address 0x31

[1:0] SAF_R_CODE: SAF reading time;

[3:2] SAF_T_WR: SAF programming time;

[7:4] RESERVED

[9:8] SAF_HV_MAN: SAF burning configuration;

[10:11] RESERVED

[12] SAF_HV_EN_FORCE_DECODING: When the bits are set to "111", the SAF write/burn operation is activated. This register is only accessible in OTP program mode (High voltage connection for burning operation is implemented).

[13:15] RESERVED

DS12567 - Rev 2 page 61/85

L5965

OTP (SAF) registers

6.9.3

SAF_REG_DI

15 14

CRC CODE

12 11 10 9

R/W

6 5

SAF_DIN

R/W R/W

0 0

4 3 2 1 0

R/W

Address 0x32

6.9.4

[15:13] CRC_CODE: the CRC checksum for SAF din. These bits can be set to '000' in SAF_REG_DI word, since they are read only.

[12:0 SAF_DIN: SAF writing data; (for burning).

Note: The CRC_CODE is only readable and is generated automatically by HW; This register is only accessible in OTP program mode.

SAF_REG_D0_Bit_Ts

15 14

CRC CODE

12 11

7 6

SAF_BIT_TS

Address 0x33

[15:13] CRC CODE: CRC checksum for SAF din.

[12:0] SAF_BIT_TS: read data from SAF bit_ts port, 3 state bus.

Note: The register will return the data from SAF_BIT_TS bus after the SAF read command.

DS12567 - Rev 2 page 62/85

L5965

Power down phase

6.9.5

SAF_REG_STAT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

Address 0x34

6.10

[0] SAF_USR_PROTECT_STAT: SAF protection status for usr region; '1' means the SAF rows in user region can't be burned or simulated;

[1] SAF_TRIM_PROTECT_STAT: SAF protection status for usr region; '1' means the SAF rows in trim region can't be burned or simulated;

[2] SAF_BUSY: SAF is busy for reading/program or CRC checking;

[3] SAF_AUOT_DL_END: '1' means saf auto download is ended;

[4] CRC_STATUS_GLB: CRC checksum status for all rows;

[5] CRC_OK: CRC checksum status for current SAF row reading operation;

[6] SAF_OPERATION_ERROR: Invalid SAF operation in OTP programing mode;

[7] CRC_BUSY: CRC busy flag;

[15:8] RESERVED

Note: This register is only accessible in OTP program mode.

Power down phase

When WKUP signal goes low, the device moves from any state to STANDBY status turning off all the regulators: at first all the active regulators are switched off, then, after a delay time (T delay

), the internal VREG is switched off too.

DS12567 - Rev 2 page 63/85

L5965

Power up programming

6.11

Power up programming

According to the data written in OTP cells, we can have different power up phases. The meaning of OTP bits code is the following:

• Main BUCK selection : main regulator, BUCK1 (OTP = 101) or BUCK2 (OTP = 110), is turned on only by

WKUP signal

• Other regulators (BUCK1 or BUCK2, BUCK3, BUCK4, BOOST, LDO and VREF) turning on order, from second to the seventh one:

– 000 = regulator is never turned on

– 001 = regulator is turned on after Main regulator (second regulator)

– 010 = regulator is turned on as third one

– 011 = regulator is turned on as fourth one

– 100 = regulator is turned on as fifth one

– 101 = regulator is turned on as sixth one

– 110 = regulator is turned on as seventh one

– 111 = regulator is turned on only by SPI enable signal

•

Two regulators with the same order number is not allowed, except for 000 or 111 code. Enable bit in OTP cells

(EnBuck3/4, EnLDO, EnBoost and EnVref) must be set to '1' too, to have the regulator ON in ACTIVE phase. All the regulators with 111 code can be turned on in ACTIVE mode, when the SPI is available.

Regulators turning on delay after Power Good: the delay is the same for all the regulators.

• 00 = no delay

01 = 2 ms after PGOOD of previous regulator

10 = 5 ms after PGOOD of previous regulator

11 = 10 ms after PGOOD of previous regulator

• Reset activation related to the right regulator Power Good (3 bits)

– 000 = Reset release after PGOOD of Main BUCK with a delay from 0 (no delay) to 10 ms (2bits)

– 001 = Reset release after PGOOD of the second regulator with a delay from 0 (no delay) to 10 ms

(2bits)

– …

– 110 = Reset release after PGOOD of the last regulator with a delay from 0 (no delay) to 10 ms (2bits ）

– 111 = Reset release when ACTIVE state is reached (unconditional Reset release)

Figure 32. Power up sequence

INIT

RAMPUP

MAIN

SEC UP

VREG_OK

VREG

Main BUCK

PG_MAINBUCK

T < texp

GAPG1002161613PS

DS12567 - Rev 2 page 64/85

Figure 33. Power down sequence

Modes ACTIVE STANDBY

WKUP

VREG

MAIN_BUCK

V_BUCK

BUCK3/BUCK4/

BOOST/LDO/VREF tdelay

L5965

Power up programming

GAPG2306151452PS

DS12567 - Rev 2 page 65/85

7.1

7.2

L5965

Functional safety requirements

Functional safety requirements

The device has been designed taking into account the following Top Level Safety Requirements:

Table 32. Top level safety requirements

ID Description

TLSR1

All regulators output voltages must remain within programmed range when RESET_B and FAULT pins are not asserted

TLSR2

Operation of the voltage regulators is allowed till over temperature limit

Safe State

REC state with RESET_B and FAULT pin asserted

REC state with RESET_B and FAULT pin asserted; all regulators OFF

Functions and safety mechanism related to safety requirements

Table 33. Functions and safety mechanism

Description

Two independent voltage references (VBG1-VBG2) for voltage monitor comparators

Ground loss comparators

Built In Self Test (Analog BIST) of Under/Over voltage and overtemperature comparators at INIT status

Built In Self Test (Digital BIST) on internal logic block at INIT status

OTP integrity Check at INIT status

Over temperature monitoring (via 7 different sensors) at ACTIVE state

Thermal sensors value readable via SPI

Built In Self Test on Thermal Comparators

System safety mechanism

Table 34. System safety mechanism

Description

Window Watchdog (via WDI pin or SPI communication)

Failure Status pin FAULT (open drain) indicating a generic failure on the device

SPI command to read device diagnosis via SPI fault registers

SPI communication check via CRC and CNT bit

TLSR

TLSR1

TLSR2

DS12567 - Rev 2 page 66/85

L5965

Application information

Application information

8.1

8.1.1

8.1.1.1

8.1.1.2

Note:

8.1.1.3

External components calculation

BUCK1 controller

SENSE

An external resistor senses the current through the inductor. R

SENSE

must be chosen so that the maximum forward peak current in the inductor generates a voltage (V

SENSE

) across the sense pins. The typical value of

SENSE

is 75 mV.

RSENSE =

VSENSE

IPEAK_LIM

(8)

BUCK1 output inductor

The value of the output inductor is usually calculated to satisfy the peak-to-peak ripple current requirement. For the best compromise of cost, size and performance, it is suggested to keep the inductor current ripple between

20% and 40% of maximum load current.

For example, if ∆I

= I

Ripple

= 0.3xI

OUT(max)

Where, I

OUT(max)

is the maximum output current.

Then, the inductor value can be estimated by the following equation:

L >

1 fSW × ΔIL

× VOUT × 1 −

VOUT

VIN(max)

Where, f

is the switching frequency, V

IN(max)

is the maximum input voltage.

The peak current flowing in Inductor is:

(9)

IL PEAK = IOUT max +

ΔIL

If the Inductor value decreases, the peak current increases. The peak current has to be lower than the current limit of the device.

The inductor should have a saturation current higher than the device current limit.

(10) in order to meet slope compensation, L needs to meet the following equation:

L > 12 ×

VOUT

Islope

Islope = 30µA × fSW

(11)

(12)

BUCK1 output capacitor

Output capacitors are selected to support load transients and output ripple current, as well as loop stability.

The amount of the voltage ripple can be calculated by the output ripple current flowing in the inductor:

∆ VOUT RIPPLE = ∆ IL ESR +

8 × fSW × COUT

(13)

Usually the first term is dominant. However, if the ceramic capacitor (which is recommended) is adopted, the first term on the above equation can be neglected, as the ESR value is very low.

COUT min =

ΔIL

8 × fSW × VOUT RIPPLE − ΔIL × ESR

(14)

For example, in case V

OUT

= 3.3 V, V

= 14 V, f

= 250 kHz, ∆I

= 0.3 x 3.5 A = 1.05 A, in order to have a

∆V

OUT

= 5% x V

OUT

= 0.165 V, a 4.7 µF ceramic capacitor is needed. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value.

In the above example, if a 100 µF with ESR = 100 mΩ electrolytic capacitor is chosen, the voltage drop on ESR dominates and the voltage ripple 1.05 A × 100 mΩ = 105 mV

DS12567 - Rev 2 page 67/85

L5965

External components calculation

8.1.1.4

8.1.1.5

The output capacitor is also important to sustain the output voltage during a load transient. In general, minimizing the ESR value and increasing the output capacitance results in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel, or by using higher quality capacitors.

The minimum output capacitance needed is determined by the maximum energy stored in the inductor when a high current to low current transition occurs. The capacitance must be sufficient to absorb the change in inductor current.

COUT min =

2 ×

Iout max 2 − Iout min 2

Vout × ΔVout

(15)

Where:

OUT(max)

, I

OUT(min) voltage.

refer to the worst case load step in the system and ∆V

OUT

is the tolerance of regulated output

BUCK1 bootstrap capacitor

The bootstrap capacitor is put between PH1 and BS1, and is 100 nF. The voltage rating of the capacitor is at least 9 V. The bootstrap capacitor should be a high-quality ceramic type with good temperature stability.

BUCK1 compensation network

The compensation network has to assure stability and good dynamic performance. The loop of the device is based on the peak current mode control, compatible with external RC compensation network. The error amplifier is a trans-conductance amplifier with large bandwidth, which is much larger than the closed-loop one.

Figure 34. Basic control loop block diagram

Current sense

Pulse-width modulator

OUT

LOAD

ESR

OUT

COMP

gm

+

–

0.9 V

GADG2409181446PS

The above figure shows the closed loop system with a RC compensation network. The basic regulator loop is modeled as a power modulator, an output feedback divider and an error amplifier. The loop transfer function is:

L s =

VREF

VOUT

× GMOD s × GEA s (16)

Where: s is the angular frequency.

DS12567 - Rev 2 page 68/85

L5965

External components calculation

REF

is the internal reference voltage, 0.8 V.

OUT

is the output voltage of the converter.

MOD

(s) is the transfer function of the error amplifier with RC compensation network.

MOD

(s) forms a pole and a zero by R equation:

LOAD

, the output capacitor (C

OUT

), and its ESR as expressed in the below

GMOD s = gmMOD × RLOAD × 1 + sESR × COUT

1 + sRLOAD × COUT g mMOD

= 1/(10 x R sense

)

RLOAD =

VOUT

IOUT, MAX

The dominant pole is: fpMOD =

2π × COUT × RLOAD × ESR

The zero is: fzMOD =

2π × COUT × ESR

GEA(s) is the transfer function of the buck converter from control to output. It forms two poles and a zero as expressed in the below equation:

(17)

(18)

(19)

(20)

GEA s ≈ gmEA × ro 1 + sRC × CC

1 + srO × CC 1 + sRC × CF

Where: g mEA

is the trans-conductance of the error amplifier, 1 mS.

is the output resistance of the error amplifier.

The zero is: fzEA =

2π × CC × RC

The optional pole is: fpEA =

2π × CF × RC

(21)

(22)

(23)

Figure 35. Simplified gain plot

DS12567 - Rev 2

The zero f zEA

set by C

and R

cancels the pole f pMOD

set by R

LOAD

and C

OUT

page 69/85

L5965

External components calculation

8.1.2

8.1.2.1

Note:

8.1.2.2

The optional pole f pEA

is set by C

and R

in order to cancel the output capacitor ESR zero if it occurs near the crossover frequency f

, where the loop gain equals 1 (0 dB).

The power modulator has a DC gain set by g mMOD

x R

LOAD

g mMOD

is trans-conductance of modulator, it is about 3.6 S. The following equations allow to approximate the value for the gain of the power modulator GAIN

MOD(DC)

GAINMOD fC = gmMOD × RLOAD (24)

The total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error-amplifier gain at f

should be equal to 1.

Then:

GAINMOD fC = GAINMOD DC × fpMOD fC

The guidelines for calculating the external network are the following ones.

(25)

Choose a value for f

, usually between f

/5 and f

/10 .

Choose resistor divider R

and R

that set the required V

OUT

Calculate the value of RC as follows:

RC =

VOUT gmEA × VFB × GAINMOD fC

(26)

Set the error-amplifier compensation zero formed by R

and C

(f zEA

) at the f pMOD

. Calculate the value of

as follows:

CC =

2π × fpMOD × RC

(27)

If f zMOD

is less than 5f

, add a second capacitor, C

, from COMP to GND and set the compensation pole formed by R

and C

(f pEA

) at the f zMOD

. Calculate the value of C

as follows:

CF =

2π × fzMOD × RC

(28)

BUCK2 controller

BUCK2 output inductor

20% and 40% of maximum load current.

For example, if ∆I

= I

Ripple

= 0.3xI

OUT(max)

Where, I

OUT(max)

is the maximum output current.

Then, the inductor value can be estimated by the following equation:

L >

1 fSW × ΔIL

× VOUT × 1 −

VOUT

VIN(max)

Where, f

is the switching frequency, V

IN(max)

is the maximum input voltage.

The peak current flowing in the Inductor is:

(29)

IL PEAK = IOUT max +

ΔIL

If the Inductor value decreases, the peak current increases. The peak current has to be lower than the current limit of the device.

The inductor should have a saturation current higher than the device current limit.

(30) in order to meet slope compensation, L needs to meet the following equation:

L > 12 ×

VOUT

Islope

Islope = 45µA × fSW

(31)

(32)

BUCK2 output capacitor

Refer to

BUCK1 output capacitor

for BUCK2 output capacitor selection.

DS12567 - Rev 2 page 70/85

L5965

External components calculation

8.1.2.3

BUCK2 compensation network

Figure 36. Basic control loop block diagram

Current sense

Pulse-width modulator

OUT

LOAD

ESR

OUT

COMP

gm

+

–

0.9 V

GADG2409181446PS

L s =

VREF

VOUT

× GMOD s × GEA s

Where: s is the angular frequency.

REF

is the internal reference voltage, 1 V.

OUT

is the output voltage of the converter.

(33)

MOD

(s) is the transfer function of the error amplifier with RC compensation network.

MOD

(s) forms a pole and a zero by R equation:

LOAD

, the output capacitor (C

OUT

), and its ESR as expressed in the below

GMOD s = gmMOD × RLOAD × 1 + sESR × COUT

1 + sRLOAD × COUT

(34) g mMOD

= 2.2 S

RLOAD =

VOUT

IOUT, MAX

(35)

The dominant pole is: fpMOD =

2π × COUT × RLOAD × ESR

(36)

The zero is:

DS12567 - Rev 2 page 71/85

L5965

External components calculation fzMOD =

2π × COUT × ESR

GEA(s) is the transfer function of the buck converter from control to output. It forms two poles and a zero as expressed in the below equation:

GEA s ≈ gmEA × ro 1 + sRC × CC

1 + srO × CC 1 + sRC × CF

Where: g mEA

is the trans-conductance of the error amplifier, 1 mS.

is the output resistance of the error amplifier.

The zero is: fzEA =

2π × CC × RC

The optional pole is: fpEA =

2π × CF × RC

(37)

(38)

(39)

(40)

Figure 37. Simplified gain plot

DS12567 - Rev 2

The zero f zEA

set by C

and R

cancels the pole f pMOD

set by R

LOAD

and C

OUT

The optional pole f pEA crossover frequency f

is set by C

and R

in order to cancel the output capacitor ESR zero if it occurs near the

, where the loop gain equals 1 (0 dB).

The power modulator has a DC gain set by g mMOD

x R

LOAD

g mMOD

is trans-conductance of modulator, it is about 3.6 S. The following equations allow to approximate the value for the gain of the power modulator GAIN

MOD(DC)

GAINMOD fC = gmMOD × RLOAD (41)

The total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error-amplifier gain at f

should be equal to 1.

Then:

GAINMOD fC = GAINMOD DC × fpMOD fC

The guidelines for calculating the external network are the following ones.

Choose a value for f

, usually between f

/5 and f

/10 .

Choose resistor divider R

and R

that set the required V

OUT

Calculate the value of RC as follows:

(42) page 72/85

L5965

External components calculation

RC =

VOUT gmEA × VFB × GAINMOD fC

(43)

Set the error-amplifier compensation zero formed by R

and C

(f zEA

) at the f pMOD

. Calculate the value of

as follows:

CC =

2π × fpMOD × RC

(44)

If f zMOD

is less than 5f

, add a second capacitor, C

, from COMP to GND and set the compensation pole formed by RC and CF (f pEA

) at the f zMOD

. Calculate the value of CF as follows:

CF =

2π × fzMOD × RC

(45)

DS12567 - Rev 2 page 73/85

L5965

External components calculation

8.1.3

8.1.3.1

8.1.3.2

8.1.3.3

BUCK3, BUCK4

Output inductor and capacitor

Buck3 and BUCK4 have an inner compensation. Here below are the recommendations for selecting the external inductor and capacitor:

• When output voltage >1.2 V, the L recommended value is 2.2 µH; when output voltage ≤ 1.2 V, the L recommended value is 1.5 µF.

• The output capacitor is recommended to be 4.7 µF~20 µF.

To select output inductor and capacitor, please refer to

BUCK1 output inductor and BUCK1 output capacitor

explanation.

Bootstrap capacitor for BUCK3 and BUCK4

A bootstrap capacitor must be connected between the BSx and PHASEx pins to provide a floating gate drive to the high-side MOSFET. For most applications 47 nF is sufficient. This should be a ceramic capacitor with a voltage rating of at least 6 V.

Input capacitor

Because of their nature, the buck converter has a pulsating input current. The device requires a low-ESR input capacitor to prevent large voltage transients that can cause misbehavior of the device or interference with other circuits in the system. An input capacitor of 4.7 µF~10 μF is sufficient for BUCK3 and BUCK4.

DS12567 - Rev 2 page 74/85

L5965

External components calculation

8.1.4

8.1.4.1

8.1.4.2

8.1.4.3

8.1.4.4

8.1.4.5

BOOST

BOOST output inductor

The inductor value depends on the allowed ripple current in the coil, related to VIN, VOUT and FSW.

The peak to peak ripple could be selected to be 30%, for instance. In this case:

ILRIPPLE max = 0.3 ×

IOUT MAX

1 − DMIN

LMIN ≈

VINmax

IRIPPLEmax

× DMIN ×

1 fSW

The maximum inductor value (L) acceptable by the Boost is limited by RHP, as explained later.

The output inductor is recommended to be 4.7 µH.

(46)

(47)

BOOST output capacitor

Output capacitors should be selected to meet the required output ripple and transient specifications for

OUT(ripple)

. Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage.

COUT = 8 ×

IOUT × D

VOUT ripple

(48)

Because BOOST employs inner compensation, which is fixed, the maximum acceptable output capacitor needs to be selected based on compensation, bandwidth and phase margin.

BOOST compensation network

The BOOST works in current mode, then the compensation principle can refer to the compensation of the buck, as explained before. The RHP (Right-Half-Plane) zero limits the cross frequency.

fZ, RHP =

RLOAD ×

VIN

VOUT

2π × L

The inner compensation of BOOST is, R

COMP error amplifier, which has MΩ of magnitude.

= 42 kΩ, C

COMP

=240 pF, C f

= 1 pF. REA is the output resistor of

(49)

If a different output capacitor is needed, the cross over frequency f

C f

× f

. When a bigger output inductor is required, the f needs to be selected in order to have f

< f

Z, RHP

Z,RHP

needs to be checked in order to assure that

should be decreased and the inductance

Output diode for the BOOST converter

The selected diode must have a reverse voltage rating >1.25 V

OUT

of the boost.

The peak current rating of the diode must be greater than the maximum inductor current.

To reduce the power losses, the diode is usually a schottky diode. The power dissipation of the diode is estimated as below:

PDmax ≈ VFD × IOUT where V

is the forward drop voltage of the diode.

(50)

Input capacitor selection

The input capacitor is chosen based on VIN(RIPPLE), and can be calculated as below:

CIN >

IRIPPLE

4 × VIN RIPPLE × fSW

ESR <

VIN RIPPLE

2 × IIN RIPPLE

(51)

(52)

DS12567 - Rev 2 page 75/85

8.2

PCB Layout example (BUCK1 as main regulator)

Figure 38. PCB Layout example

LDO output voltage

LDO supply voltage

Analog ground

L5965

PCB Layout example (BUCK1 as main regulator)

Reference output voltage

Input supply voltage

REF 1

VBAT1 2

Option LV supply voltage EXTSUP 3

VREG 4

BST1 5

GH1 6

PH1 7

GL1 8

PGND1 9 sensep 10 sensen 11

COMP1

Buck1 output voltage

Analog ground

SYNCOUT

35 SYNCIN

34 BST2

33 VBAT2

32 PH2

31 PGND2

30 VREG2_S

29 COMP2

28 VBOOST_S

27 PGND5

26 PH5

25 WKUP

Analog ground

Boost output voltage

Analog ground

GAPG2306151622PS

DS12567 - Rev 2 page 76/85

9.1

L5965

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

VFQFPN-48 (7x7x1.0 mm - opt. D) package information

Figure 39. VFQFPN-48 (7x7x1.0 mm - opt. D) package outline

INDEX AREA

R0.125

C0.35

Ref

0.10 C

48X ddd C

DETAIL A

Terminal Length

0.5±0.05

0.05 Ref

DETAIL A

NOTE :

1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES.

2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

COPLANARITY SHALL NOT EXCEED 0.08 mm.

3. WARPAGE SHALL NOT EXCEED 0.10 mm.

4. REFER JEDEC MO-220.

7446345_G_V0 (Opt. C)

24 e

0.20 Ref

Terminal Thickness

48X b

0.18 Ref.

0.30 Ref.

0.48 Ref.

GAPGPS03449

Table 35. VFQFPN-48 (7x7x1.0 - opt. D) package mechanical data

Min.

0.85

Dimensions (mm)

Typ.

0.95

0.75

Max.

1.05

0.05

DS12567 - Rev 2 page 77/85

L5965

VFQFPN-48 (7x7x1.0) marking information

9.2

Ref

E2 e

L ddd

A3 b

Min.

6.85

5.15

0.45

0.15

6.80

5.15

VFQFPN-48 (7x7x1.0) marking information

Dimensions (mm)

Typ.

0.200

0.25

7.00

5.30

7.00

5.30

0.50

Figure 40. VFQFPN-48 (7x7x1.0) marking information

Marking area

Max.

7.15

5.45

0.55

0.08

0.35

7.15

5.45

Last two digits

ES: Engineering sample

<blank>: Commercial sample

GAPG2203161040PS

Parts marked as 'ES' are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

DS12567 - Rev 2 page 78/85

L5965

Revision history

Date

04-Dec-2018

09-May2019

Revision

Table 36. Document revision history

Changes

Initial release.

Updated:

Features ;

Section 4 Functional description

;

Electrical characteristics

;

Table 32. Top level safety requirements and Table 33. Functions and safety mechanism ;

INIT mode ,

OTP bit mapping and register configuration

;

From

SPI REG ADC TH1

SPI REG ADC TH7

DS12567 - Rev 2 page 79/85

L5965

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.1

Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.1

Absolute maximum ratings & operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2.1

3.2.2

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal warning and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3.1

Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.1

Programming by OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

Voltage regulators and features description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.2.7

VREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Pre regulator BUCK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pre regulator BUCK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Post regulator BUCK3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Post regulator BUCK4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

BOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2.8

4.2.9

VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2.10

Wake up pin (WKUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.11

Synchronizing pin (SYNC in/out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.12

Reset and Fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.13

Configurable watchdog and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2.14

Under-Voltage, Over-Voltage and Power-Good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.15

Temperature control and VBATx voltage through internal ADC . . . . . . . . . . . . . . . . . . . . . 29

4.2.16

Maximum Duty Cycle and Refresh Mode for Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DS12567 - Rev 2 page 80/85

L5965

Contents

4.2.17

Frequency-Hopping Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5 SPI format and register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.1

SPI frame CRC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.2

SPI registers mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

SPI REG BUCK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SPI REG BUCK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SPI REG WD_REC_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SPI REG BUCK4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SPI REG BOOST VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2.6

5.2.7

5.2.8

5.2.9

SPI REG BUCK EN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SPI REG WD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SPI REG BUCK STAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SPI REG BUCK STAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.2.10

SPI REG Fault Table PWUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2.11

SPI REG ADC TH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2.12

SPI REG ADC TH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2.13

SPI REG ADC TH3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2.14

SPI REG ADC TH4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2.15

SPI REG ADC TH5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.16

SPI REG ADC TH6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.17

SPI REG ADC TH7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2.18

SPI REG ADC VBAT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.19

SPI REG ADC VBAT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.20

SPI REG OT Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2.21

SPI Fault STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2.22

SPI Silicon Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2.23

SPI Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6 Device operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

6.1

Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.3

INIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.4

REC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DS12567 - Rev 2 page 81/85

L5965

Contents

6.5

RAMPUP MAIN and SEC_UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.6

ACTIVE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.7

OTP program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.8

OTP bit mapping and register configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.9

OTP (SAF) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.9.1

6.9.2

6.9.3

6.9.4

6.9.5

SAF_REG_OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SAF_REG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

SAF_REG_DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SAF_REG_D0_Bit_Ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SAF_REG_STAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.10

Power down phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.11

Power up programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7 Functional safety requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

7.1

Functions and safety mechanism related to safety requirements . . . . . . . . . . . . . . . . . . . . . . 66

7.2

System safety mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

8.1

External components calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.1.1

8.1.2

8.1.3

8.1.4

BUCK1 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

BUCK2 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

BUCK3, BUCK4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

BOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2

PCB Layout example (BUCK1 as main regulator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

9.1

VFQFPN-48 (7x7x1.0 mm - opt. D) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.2

VFQFPN-48 (7x7x1.0) marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

DS12567 - Rev 2 page 82/85

L5965

List of tables

Table 1. Pin description and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Absolute maximum ratings & operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Operation junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Maximum suggested power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. UV masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8. Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Input CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Input CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. DI, CLK and CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. Output DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. OTP row programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 15. Reset activation OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 16. Device identification OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 17. WD_REC_en OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 18. Buck1 CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 19. Primary activation OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 20. Buck2 CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 21. Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 22. SeqId Buck4, Buck3, LDO, Boost, Vref OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 23. Buck4 CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 24. OvRst_EN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 25. Buck3 CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 26. LDO CFG OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 27. Boost CFG OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 28. USR Area Protection OTP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 29. PowrOn Delay OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 30. WDG CFG OTP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 31. VREF CFG OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 32. Top level safety requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 33. Functions and safety mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 34. System safety mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 35. VFQFPN-48 (7x7x1.0 - opt. D) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

DS12567 - Rev 2 page 83/85

L5965

List of figures

Figure 1. Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3. Pin out (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Efficiency of Buck2 with Vin = 14 V and Vout = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. Efficiency of Buck3 with Vin = 3.3 V and Vout = 2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Efficiency of Buck4 with Vin = 3.3 V and Vout = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Efficiency of Boost with Vin = 3.3 V and Vout = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. VREG influence on PMIC behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Pre regulator BUCK1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. ADC circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. SYNC IN/OUT in Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 12. SYNCOUT output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. Reset circuit diagram in ACTIVE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. Fault function in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15. Watchdog behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16. Watchdog timing if WD_REC_en = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 17. Watchdog timing if WD_REC_en = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 18. Watchdog Early, Safe and Late window diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 19. Output voltage and monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 20. VTSENSE vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 21. Refresh mode in bucks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 22. SPI word representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 23. SPI diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 24. SPI protocol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 25. Structure of CRC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 26. State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 27. State machine for SEC UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 28. OTP program flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 29. OTP bit mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 30. Programmed configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 31. OTP start-up state check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 32. Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 33. Power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 34. Basic control loop block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 35. Simplified gain plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 36. Basic control loop block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 37. Simplified gain plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 38. PCB Layout example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 39. VFQFPN-48 (7x7x1.0 mm - opt. D) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 40. VFQFPN-48 (7x7x1.0) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DS12567 - Rev 2 page 84/85

L5965

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of

Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DS12567 - Rev 2 page 85/85

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Datasheet

Power management for automotive vision and radar systems

Overview

Simplified block diagram

Pins description

Electrical specifications

Thermal resistance

Thermal warning and protection

Electrical characteristic curves

Functional description

VREG

Pre regulator BUCK1

Pre regulator BUCK2

Post regulator BUCK3

Post regulator BUCK4

BOOST

LDO

VREF

ADC

Wake up pin (WKUP)

Synchronizing pin (SYNC in/out)

IC

IC

Reset and Fault

Configurable watchdog and reset

Under-Voltage, Over-Voltage and Power-Good

Temperature control and VBATx voltage through internal ADC

Maximum Duty Cycle and Refresh Mode for Buck

Frequency-Hopping Spread Spectrum

SPI format and register mapping

SPI REG BUCK1

SPI REG BUCK2

SPI REG WD_REC_EN

SPI REG BUCK4

SPI REG BOOST VREF

SPI REG BUCK EN

SPI REG WD

SPI REG BUCK STAT1

SPI REG BUCK STAT2

SPI REG Fault Table PWUP

SPI REG ADC TH1

SPI REG ADC TH2

SPI REG ADC TH3

SPI REG ADC TH4

SPI REG ADC TH5

SPI REG ADC TH6

SPI REG ADC TH7

SPI REG ADC VBAT1

SPI REG ADC VBAT2

SPI REG OT Warning

SPI Fault STAT

SPI Silicon Version

SPI Device Identification

Device operating mode

SAF_REG_OP

SAF_REG_CFG

SAF_REG_DI

SAF_REG_D0_Bit_Ts

SAF_REG_STAT

Functional safety requirements

Application information

BUCK1 controller

Pulse-width modulator

gm

+

–

BUCK2 controller

Pulse-width modulator

gm

+

–

BUCK3, BUCK4

BOOST

Package information

VFQFPN-48 (7x7x1.0 mm - opt. D) package information

Verwandt

Infineon KIT_PSC3_DB1 Evaluation Board Quick Start Guide

ST L5965 evaluation board User Manual

STMicroelectronics UM3229 Evaluation Board User Manual

EVAL-L5965 User Manual - STMicroelectronics