STMicroelectronics LIS3DHH Datasheet
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LIS3DHH
Ceramic cavity LGA-16
(5x5x1.7 mm)
Features
3-axis, ±2 .5 g full-scale
Ultra-low noise performance: 45 μ g / √ Hz
Excellent stability over temperature
(<0.4 m g /°C) and time
16-bit data output
SPI 4-wire digital output interface
Embedded temperature sensor
12-bit temperature data output
Embedded FIFO (depth 32 levels)
High shock survivability
Extended operating temperature range
(-40 °C to +85 °C)
ECOPACK ® , RoHS and “Green” compliant
MEMS motion sensor:
three-axis digital output accelerometer
Datasheet
-
production data
Applications
Precision inclinometer
Platform and antenna stabilization
Leveling instruments
Description
The LIS3DHH is an ultra-high-resolution and lownoise three-axis linear accelerometer.
The LIS3DHH has a full scale of 2.5 g and is capable of providing the measured accelerations to the application through an SPI 4-wire digital interface.
The sensing element is manufactured using a dedicated micromachining process developed by
STMicroelectronics to produce inertial sensors and actuators on silicon wafers.
The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
The LIS3DHH is available in a high-performance
(low-stress) ceramic cavity land grid array (CC
LGA) package and can operate within a temperature range of -40 °C to +85 °C.
Order codes
LIS3DHHTR
Table 1. Device summary
Temperature range [ C] Package
-40 to +85 CC LGA-16 (5x5x1.7 mm)
Packaging
Tape and reel
October 2017
This is information on a product in full production.
DocID030220 Rev 3 1/29 www.st.com
Contents
Contents
LIS3DHH
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . 11
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OUT_TEMP_L (25h), OUT_TEMP_H (26h) . . . . . . . . . . . . . . . . . . . . . . . 24
2/29 DocID030220 Rev 3
LIS3DHH
Contents
LGA-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID030220 Rev 3 3/29
29
List of tables
List of tables
LIS3DHH
4/29 DocID030220 Rev 3
LIS3DHH
List of figures
List of figures
External asynchronous trigger to FIFO for Continuous-to-FIFO mode . . . . . . . . . . . . . . . . 18
External asynchronous trigger to FIFO for Bypass-to-Continuous mode . . . . . . . . . . . . . . 19
DocID030220 Rev 3 5/29
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Pin description LIS3DHH
Figure 1. Pin connections
6/29
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8
12
13
14
15
16
9
10
11
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Name
SPC
SDI
SDO
CS
INT2
INT1
Vdd_IO
Vdd
GND
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2. Pin description
Function
Clock line for SPI 4-wire interface (SPC)
Serial data input (SDI) line for SPI 4-wire interface
Serial data output (SDO) line for SPI 4-wire interface
SPI chip-select line (CS)
Programmable interrupt 2 generated according to a configurable FIFO threshold in a dedicated register
Programmable interrupt 1 generated according to a configurable FIFO threshold in a dedicated register
Power supply for I/O pins
Recommended power supply decoupling capacitor (100 nF)
Power supply
Recommended power supply decoupling capacitors (100 nF ceramic in parallel with 10 μ F aluminum)
0 V power supply
Connect to GND
Connect to GND
Connect to GND
Connect to GND
Connect to GND or leave unconnected
Connect to GND or leave unconnected
Connect to GND or leave unconnected
DocID030220 Rev 3
LIS3DHH
2
Mechanical and electrical specifications
Mechanical and electrical specifications
@ Vdd = 2.8 V, T = 25 °C unless otherwise noted.
Symbol
FS
So
Parameter
Measurement range
(2)
Sensitivity (3)
Table 3. Mechanical characteristics
Test condition Min. Typ.
(1)
TCSo
Off
TCOff
NL
Zgn
ODR
Bw
StartT
ST
Sensitivity change vs. temperature
Zerog level offset accuracy
(4)
Zerog level change vs. temperature
(5)
Non linearity
Zerog noise density
Digital output data rate
From -40 °C to +85 °C, delta from 25°C
From -40 °C to +85 °C, delta from 25 °C
Best-fit straight line
FS = ±2.5 g
Bandwidth
Startup time
Self-test positive difference
(6)
For both FIR and IIR filters
For cold start condition
X, Y-axis
Z-axis
Top
Operating temperature range
-0.4
75
75
-40
±2.5
0.076
0.7
±20
45
1.1
235 or
440
Max.
0.4
2
65
150
650
1400
+85
Unit g m g /digit
% m g m g /°C
% FS ug Hz kHz
Hz ms m g
°C
1. Typical specifications are not guaranteed.
2. Sensor is designed with larger dynamic to avoid variation of FS limits in the operative bandwidth. Consequently to trim operations at factory final test.
3. Sensitivity range after MSL3 preconditioning.
4. Typical zerog level offset value after MSL3 preconditioning.
5. Min/max at 3 sigma. Based on characterization data for a limited number of samples, not measured during final test for production.
6. Self-test positive difference is defined as:
OUTPUT[m g ](
ST2, ST1 bits = 01
) - OUTPUT[m g ](
) in steady state.
DocID030220 Rev 3 7/29
29
Mechanical and electrical specifications LIS3DHH
@ Vdd = 2.8 V, T = 25 °C unless otherwise noted.
Symbol Parameter
Table 4. Electrical characteristics
Test condition Min.
Typ.
(1)
Max.
Unit
Vdd Supply voltage
Vdd_IO I/O pins supply voltage
Idd Supply current
V
IH
V
IL
V
OH
V
OL
Top
Digital high-level input voltage
Digital low-level input voltage
High-level output voltage
Low-level output voltage
Twait
Operating temperature range
SPI_Fr SPI frequency
Trise Time for power supply rising
(3)
Time delay between Vdd_IO and Vdd
(3)
I
I
OH
OL
= 4 mA
= 4 mA
(2)
4-wire interface
1.71
1.71
0.7*Vdd_IO
Vdd_IO - 0.2
-40
0.01
0
2.8
2.5
5
3.6
Vdd+0.1
5
0.3*Vdd_IO
0.2
+85
10
100
10 ms
1. Typical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
3. Please refer to Section 2.2.1: Recommended power-up sequence for more details.
V
V
V
V
V
V mA
°C
MHz ms
8/29 DocID030220 Rev 3
LIS3DHH
2.2.1
Mechanical and electrical specifications
Recommended power-up sequence
For the power-up sequence please refer to the following figure, where:
Trise is the time for the power supply to rise from 10% to 90% of its final value
Twait is the time delay between the end of the Vdd_IO ramp (90% of its final value) and the start of the Vdd ramp
In the power-down sequence Vdd and Vdd_IO can come down in any order.
Figure 2. Recommended power-up sequence
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9GGB,2 9
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9GG
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2.3 Temperature sensor characteristics
@ Vdd = 2.8 V, T = 25 °C unless otherwise noted.
Symbol
Table 5. Temperature sensor characteristics
Parameter Test condition
TSDr
Tn
Temperature sensor output change vs. temperature
Temperature sensor noise ( RMS )
Temperature accuracy Ta
TODR Temperature refresh rate equal to ODR/16
TNL Temperature nonlinearity Best-fit straight line
Top
Operating temperature range
1. Typical specifications are not guaranteed.
Min.
-15
62.5
-40
Typ.
(1)
16
5
Max.
Unit digit/°C
0.1
+15
+85
°C
°C
Hz
% Top
°C
DocID030220 Rev 3 9/29
29
Absolute maximum ratings
3 Absolute maximum ratings
Note:
LIS3DHH
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Table 6. Absolute maximum ratings
Ratings
Vdd and
Vdd_IO
Supply voltage
T
STG
Sg
Storage temperature range
Acceleration g for 0.2 ms
ESD Electrostatic discharge protection (HBM)
Vin
Input voltage on any control pin
(including CS, SPC, SDI, SDO)
Maximum value
-0.3 to 4.8
-40 to +85
10,000
2
-0.3 to Vdd_IO +0.3
Unit
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
V
°C g kV
V
10/29 DocID030220 Rev 3
LIS3DHH
4
Communication interface characteristics
Communication interface characteristics
4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 7. SPI slave timing values
Value
(1)
Symbol Parameter Unit
Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
5
20
5
15
5
10
50
50
1. Values are guaranteed at 10 MHz clock frequency for SPI 4 wires, based on characterization results, not tested in production ns
MHz ns
Figure 3. SPI slave timing diagram
Note:
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
The SPI state machine is reset each time the CS signal is de-asserted.
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Communication interface characteristics
4.2 SPI bus interface
LIS3DHH
The LIS3DHH SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface interacts with the application using 4 wires: CS , SPC , SDI and SDO .
Figure 4. Read and write protocol
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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. These lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the
CTRL_REG1 (20h) (IF_ADD_INC) bit is ‘0’ the address used to read/write data remains the
same for every block. When
CTRL_REG1 (20h) (IF_ADD_INC) bit is ‘1’ the address used to
read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
12/29 DocID030220 Rev 3
LIS3DHH Communication interface characteristics
Figure 5. SPI read protocol
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The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 6. Multiple byte SPI read protocol (2-byte example)
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DocID030220 Rev 3 13/29
29
Communication interface characteristics
Figure 7. SPI write protocol
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LIS3DHH
The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1 -7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 8. Multiple byte SPI write protocol (2-byte example)
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14/29 DocID030220 Rev 3
LIS3DHH
5 FIFO
FIFO
The LIS3DHH embeds 32 slots of 16-bit data FIFO for each of the accelerometer’s three output channels, X, Y and Z. This allows consistent power saving for the system since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to five different modes: Bypass mode, FIFO mode, Continuous mode,
Continuous-to-FIFO mode and Bypass-to-Continuous mode. Each mode is selected by the
FMODE [2:0] bits in the
register. Programmable FIFO threshold status,
FIFO overrun events and the number of unread samples stored are available in the
register and can be set to generate dedicated interrupts on the INT1 and
INT2 pins using the
and
registers.
(FTH) goes to '1' when the number of unread samples (
(FSS5:0)) is greater than or equal to FTH [4:0] in
FIFO_CTRL (2Eh) . If FIFO_CTRL (2Eh)
(FTH[4:0]) is equal to 0,
FIFO_SRC (2Fh) (FTH) goes to ‘0’.
(OVRN) is equal to '1' if a FIFO slot is overwritten.
FIFO_SRC (2Fh) (FSS [5:0]) contains stored data levels of unread samples. When FSS [5:0]
is equal to ‘000000’, FIFO is empty. When FSS [5:0] is equal to ‘100000’, FIFO is full and the unread samples are 32.
The FIFO feature is enabled by writing '1' in CTRL_REG4 (23h)
(FIFO_EN).
To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded.
In Bypass mode (
FIFO_CTRL (2Eh) (FMODE [2:0]= 000), the FIFO is not operational, no
data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers.
Bypass mode is also used to reset the FIFO when in FIFO mode.
As described in Figure 9 , for each channel only the first address is used. When new data is
available the old data is overwritten.
Figure 9. Bypass mode x i
,y i
,z i x
0 y
0 z
0 empty x
1 x
2 y
1 y
2 z
1 z
2 x
31 y
31 z
31
DocID030220 Rev 3 15/29
29
FIFO LIS3DHH
In FIFO mode (
(FMODE [2:0] = 001) data from the output channels are stored in the FIFO memory until it is full, when 32 unread samples are stored in memory, data collecting is stopped.
To reset FIFO content, Bypass mode should be selected by writing
(FMODE [2:0]) to '000'. After this reset command, it is possible to restart FIFO mode, writing
FIFO_CTRL (2Eh) (FMODE [2:0]) to '001'.
A FIFO threshold interrupt can be enabled (INT1_OVR bit in
or
INT2_OVR bit in
INT2_CTRL (22h) ) in order to be raised when the FIFO is filled to the level
specified by the FTH[4:0] bits of FIFO_CTRL (2Eh) .
Figure 10. FIFO mode
[
L
\
L
]
L
[
[
[
\
\
\
]
]
]
[ \ ]
16/29 DocID030220 Rev 3
LIS3DHH FIFO
Continuous mode ( FIFO_CTRL (2Eh)
(FMODE[2:0] = 110) provides a continuous FIFO update: when 32 unread samples are stored in memory, as new data arrives the oldest data is discarded and overwritten by the newer.
A FIFO threshold flag
(FTH) is asserted when the number of unread samples in FIFO is greater than or equal to
It is possible to route
FIFO_SRC (2Fh) (FTH) to the INT1 pin by writing the INT1_FTH bit to
A full-flag interrupt can be enabled (
INT1_CTRL (21h) (INT_ FSS5)= '1' or INT2_CTRL
(INT_ FSS5)= '1') when the FIFO becomes saturated and in order to read the contents all at once. If an overrun occurs, the oldest sample in FIFO is overwritten and the OVRN flag in
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in
Figure 11. Continuous mode x i
,y i
,z i x
0 x
1 x
2 x
30 x
31 y
0 y
1 y
2 y
30 y
31 z
0 z
1 z
2 z
30 z
31
DocID030220 Rev 3 17/29
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FIFO LIS3DHH
In Continuous-to-FIFO mode ( FIFO_CTRL (2Eh) (FMODE [2:0] = 011), FIFO operates in
Continuous mode and FIFO mode starts on the INT1 edge trigger event. When the FIFO is full, data collecting is stopped.
Figure 12. Continuous-to-FIFO mode x i
,y i
,z i x i
,y i
,z i x
0 x
1 x
2 x
30 x
31 y
0 y
1 y
2 y
30 y
31 z
0 z
1 z
2 z
30 z
31 x
0 x
1 x
2 y
0 y
1 y
2 z
0 z
1 z
2 x
31 y
31 z
31
Continuous Mode
Trigger event
FIFO Mode
Figure 13. External asynchronous trigger to FIFO for Continuous-to-FIFO mode
18/29 DocID030220 Rev 3
LIS3DHH FIFO
In Bypass-to-Continuous mode ( FIFO_CTRL (2Eh) (FMODE[2:0] = '100'), data
measurement storage inside FIFO starts in Continuous mode on the INT1 edge trigger event, then the sample that follows the trigger is available in FIFO.
Figure 14. Bypass-to-Continuous mode x i
,y i
,z i x i
,y i
,z i empty x
0 x
1 x
2 y
0 y
1 y
2 z
0 z
1 z
2 x
0 x
1 x
2 x
30 x
31 y
0 y
1 y
2 y
30 y
31 z
0 z
1 z
2 z
30 z
31 x
31 y
31 z
31
Bypass Mode Continuous Mode
Trigger event
Figure 15. External asynchronous trigger to FIFO for Bypass-to-Continuous mode
DocID030220 Rev 3 19/29
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Register mapping LIS3DHH
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.
Name
Reserved
WHO_AM_I
Reserved
CTRL_REG1
INT1_CTRL
INT2_CTRL
CTRL_REG4
CTRL_REG5
OUT_TEMP_L
OUT_TEMP_H
STATUS
OUT_X_L_XL
OUT_X_H_XL
OUT_Y_L_XL
OUT_Y_H_XL
OUT_Z_L_XL
OUT_Z_H_XL
FIFO_CTRL
FIFO_SRC
Reserved r r r r r r r r r r/w r
-r/w r/w r/w r/w
-r
-r/w
Type
Table 8. Register mapping
Register address
Hex
29
2A
2B
2C
25
26
27
28
21
22
23
24
00-0E
0F
10-1F
20
2D
2E
2F
30-32
Binary
--
00001111
--
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
--
Default output output output output output output output output
--
00010001
--
00000000
00000000
00000000
00000000
00000000 output
00000000 output
--
Note
Reserved
Reserved
Reserved
Registers marked as Reserved must not be changed. Writing to those registers may affect the correct behavior of the device.
Their content is automatically restored when the device is powered up.
20/29 DocID030220 Rev 3
LIS3DHH Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration and temperature data. The register addresses, consisting of 7 bits, are used to identify them and to write the data through the serial interface.
Device identification register.
0 0 0
Table 9. WHO_AM_I register
1 0 0 0 1
Control register 1.
Table 10. CTRL_REG1 register
NORM_
MOD_EN
IF_ADD_
INC
0
(1)
0
(1)
BOOT SW_RESET
1. These bits must be set to ‘0’ for the correct operation of the device.
DRDY_
PULSE
BDU
NORM_-
MOD_EN
IF_ADD_INC
BOOT
Table 11. CTRL_REG1 register description
Normal mode enable. Default value: 0
(0: power down; 1: enabled)
Register address automatically incremented during a multiple byte access with
SPI serial interface. Default value: 1
(0: disabled; 1: enabled)
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content
(1)
)
SW_RESET
DRDY_PULSE
BDU
Software reset. Default value: 0
With SW_RESET the values in the writable CTRL registers are changed to the default values.
(0: normal mode; 1: reset device)
This bit is cleared by hardware at the end of the operation.
Data ready on INT1 pin. Default value: 0
(0: DRDY latched; 1: DRDY pulsed, pulse duration is 1/4 ODR)
Block Data Update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB read)
1. Boot request is executed as soon as the internal oscillator is turned on. It is possible to set the bit while in power-down mode, in this case it will be served at the next normal mode.
DocID030220 Rev 3 21/29
29
Register description LIS3DHH
INT1 pin control register.
INT1_
DRDY
INT1_
BOOT
INT1_
OVR
Table 12. INT1_CTRL register
INT1_
FSS5
INT1_FTH INT1_ EXT
1. These bits must be set to ‘0’ for the correct operation of the device.
0
(1)
0
(1)
INT1_DRDY
INT1_ BOOT
INT1_OVR
INT1_ FSS5
INT1_FTH
INT1_ EXT
Table 13. INT1_CTRL register description
Accelerometer data ready on INT1 pin. Default value: 0
(0: disabled; 1: enabled)
Boot status available on INT1 pin. Default value: 0
(0: disabled; 1: enabled)
Overrun flag on INT1 pin. Default value: 0
(0: disabled; 1: enabled)
FSS5 full FIFO flag on INT1 pin. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold flag on INT1 pin. Default value: 0
(0: disabled; 1: enabled)
INT1 pin configuration. Default value: 0
It configures the INT1 pad as output for FIFO flags or as external asynchronous input trigger to FIFO.
INT2 pad is always available as output for FIFO flags.
(0: INT1 as output interrupt; 1: INT1 as input channel)
22/29
INT2 pin control register.
Table 14. INT2_CTRL register
INT2_DRDY INT2_BOOT INT2_OVR INT2_ FSS5 INT2_FTH 0
(1)
1. These bits must be set to ‘0’ for the correct operation of the device.
INT2_DRDY
INT2_ BOOT
INT2_OVR
INT2_ FSS5
INT2_FTH
Table 15. INT2_CTRL register description
Accelerometer data ready on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
Boot status available on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
Overrun flag on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
FSS5 full FIFO flag on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold flag on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
0
(1)
DocID030220 Rev 3
0
(1)
LIS3DHH Register description
Control register 4.
0
1
ST2
0
1
DSP_LP_
TYPE
DSP_BW_
SEL
Table 16. CTRL_REG4 register
ST2 ST1
PP_OD_
INT2
1. This bit must be set to ‘1’ for correct operation of the device.
PP_OD_
INT1
DSP_LP_TYPE
DSP_BW_SEL
ST [2:1]
PP_OD_INT2
PP_OD_INT1
FIFO_EN
FIFO_EN
Table 17. CTRL_REG4 register description
Digital filtering selection. Default value: 0
(0: FIR Linear Phase; 1: IIR Nonlinear Phase)
User-selectable bandwidth. Default value: 0
(0: 440 Hz typ.; 1: 235 Hz typ.)
Self-test enable. Default value: 00
(00: Self-test disabled; Other: See Table 18 )
Push-pull/open drain selection on INT2 pin. Default value: 0
(0: push-pull mode; 1: open drain mode)
Push-pull/open drain selection on INT1 pin. Default value: 0
(0: push-pull mode; 1: open drain mode)
FIFO memory enable. Default value: 0
(0: disabled; 1: enabled)
1
0
ST1
0
1
Table 18. Self-test mode selection
Self-test mode
Normal mode
Positive sign self-test
Negative sign self-test
Not allowed
1
(1)
Control register 5.
0
(1)
0
(1)
0
(1)
Table 19. CTRL_REG5 register
0
(1)
0
(1)
1. These bits must be set to ‘0’ for correct operation of the device.
0
(1)
0
(1)
FIFO_SPI_HS_ON
FIFO_SPI_HS_ON
Table 20. CTRL_REG5 register description
Enables the SPI high speed configuration for the FIFO block that is used to guarantee a minimum duration of the window in which writing operation of
RAM output is blocked. This bit is recommended for SPI clock frequencies higher than 6 MHz. Default value: 0.
(0: not enabled; 1: enabled)
DocID030220 Rev 3 23/29
29
Register description
7.7 OUT_TEMP_L (25h), OUT_TEMP_H (26h)
LIS3DHH
Temperature data output register. L and H registers together express a 16-bit word in two’s complement left-justified.
Temp3
Temp11
Temp [11:0]
Temp2 Temp1
Table 21. OUT_TEMP_L register
Temp0 0 0
Temp10 Temp9
Table 22. OUT_TEMP_H register
Temp8 Temp7 Temp6
0
Table 23. OUT_TEMP register description
Temperature sensor output data.
The value is expressed as two’s complement sign.
0 LSB represents T=25 °C ambient.
Temp5
0
Temp4
Status register (r)
ZYXOR ZOR YOR
Table 24. Status register
XOR ZYXDA ZDA YDA XDA
Table 25. Status register description
ZYXOR Logic OR of the single X-, Y- and Z-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new set of data has overwritten the previous set)
ZOR
YOR
XOR X-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data)
ZYXDA Logic AND of the single X-, Y- and Z-axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
ZDA Z-axis new data available. Default value: 0
(0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available)
YDA
Z-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data)
Y-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data)
XDA
Y-axis new data available. Default value: 0
(0: new data for the Y-axis is not yet available; 1: new data for the Y-axis is available)
X-axis new data available. Default value: 0
(0: new data for the X-axis is not yet available; 1: new data for the X-axis is available)
24/29 DocID030220 Rev 3
LIS3DHH
7.9
Register description
OUT_X (28h - 29h)
Linear acceleration sensor X-axis output register. The value is expressed as a 16-bit word in two’s complement.
7.10 OUT_Y (2Ah - 2Bh)
Linear acceleration sensor Y-axis output register. The value is expressed as a 16-bit word in two’s complement.
7.11 OUT_Z (2Ch - 2Dh)
Linear acceleration sensor Z-axis output register. The value is expressed as a 16-bit word in two’s complement.
FIFO control register.
Table 26. FIFO_CTRL register
FMODE2 FMODE1 FMODE0 FTH4 FTH3 FTH2 FTH1 FTH0
FMODE [2:0]
FTH [4:0]
Table 27. FIFO_CTRL register description
FIFO mode selection bits. Default value: 000
For further details refer to
FIFO threshold level setting. Default value: 0 0000
1
1
0
1
0
0
0
1
Table 28. FIFO mode selection
FMODE2 FMODE1 FMODE0 Mode
0
1
1
0
0
0
1
1
1
0
1
0
0
1
0
1
Bypass mode. FIFO turned off
FIFO mode. Stops collecting data when FIFO is full.
Reserved
Continuous mode until trigger is asserted, then FIFO mode.
Bypass mode until trigger is asserted, then Continuous mode.
Reserved
Continuous mode. If the FIFO is full, the new sample overwrites the older sample.
Reserved
DocID030220 Rev 3 25/29
29
Register description LIS3DHH
FIFO status register.
FTH OVRN FSS5
Table 29. FIFO_SRC register
FSS4 FSS3 FSS2 FSS1 FSS0
FTH
OVRN
FSS [5:0]
Table 30. FIFO_SRC register description
FIFO threshold status.
(0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level
FIFO overrun status.
(0: FIFO is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten) For further details refer to
Number of unread samples stored in FIFO.
(000000: FIFO empty; 100000: FIFO full, 32 unread samples)
For further details refer to
.
0
--
(1)
...
--
(1)
0
(1)
0
1
0
0
1
1
0
0
Table 31. FIFO_SRC example: OVR/FSS details
FTH OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Description
FIFO empty
1 unread sample
32 unread samples
At least one sample has been overwritten
1. When the number of unread samples in FIFO is equal to or greater than the threshold level set in register
, the FTH value is ‘1’.
The FSS is the FIFO stored data level of the unread samples. When it is equal to FTH, all data available in FIFO are read without additional read operations.
The INT output is high when the number of samples to read is equal to or greater than FTH.
Figure 16. Continuous mode: FTH/FSS details
26/29 DocID030220 Rev 3
LIS3DHH Package information
8.1
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
LGA-16 package information
Figure 17. Ceramic cavity LGA-16: package outline and mechanical data
)
-
Note:
3LQ
LQGLFDWRU
Note:
Top and bottom view: dimensions are expressed in mm
ITEM
Length [L]
Width [W]
Height [H]
Pad size
Table 32. Outer dimensions
Dimension [mm]
5
5
1.7 typ
0.7 x 0.5
General tolerance is ±0.1 mm unless otherwise specified
Tolerance [mm]
±0.15
±0.15
±0.15
±0.15
B$
DocID030220 Rev 3 27/29
29
Revision history LIS3DHH
Date
23-Mar-2017
09-May-2017
11-Oct-2017
Revision
Table 33. Document revision history
Changes
1
2
3
Initial release
Updated V
IH
, V
IL
and added V
OH characteristics
, V
OL to Table 4: Electrical
Updated
Table 3: Mechanical characteristics
Updated
Table 4: Electrical characteristics
Updated
Figure 2: Recommended power-up sequence
Updated
Table 7: SPI slave timing values
Updated
Figure 6: Multiple byte SPI read protocol (2-byte example)
and Figure 8: Multiple byte SPI write protocol (2-byte example)
Added
Updated bit 0 in CTRL_REG4 (23h)
28/29 DocID030220 Rev 3
LIS3DHH
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
DocID030220 Rev 3 29/29
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