STMicroelectronics LD49100 Datasheet
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LD49100
Datasheet
Automotive-grade, 1 A, low quiescent current, low-noise regulator with soft-start
DFN6 (3x3)
Wettable Flanks
Maturity status link
LD49100
Features
• AEC-Q100 qualified
• Temperature range: -40 °C to 125 °C
• Input voltage from 1.5 to 5.5 V
• Ultra low-dropout voltage (200 mV typ. at 1 A load)
• Very low quiescent current (20 µA typ. at no load, 200 µA typ. at 1 A load, 1 µA max. in off mode)
• Very low-noise with no bypass capacitor (30 µV
RMS
at V
OUT
= 0.8 V)
• Output voltage tolerance: ± 2.0% at 25 °C
• 1 A guaranteed output current
• Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 V
• Logic-controlled electronic shutdown
• Power Good function
• Stable with ceramic capacitors C
OUT
= 1 µF
• Internal current and thermal limit
• DFN6 (3x3 mm) package with wettable flanks
Applications
• Infotainment and cluster
• ADAS
• Telematics
• Body electronics
Description
The LD49100 provides 1 A maximum current with an input voltage range from 1.5 V to 5.5 V and a typical dropout voltage of 200 mV. The device is stable with ceramic capacitors on the input and output.
The ultra low-dropout voltage, low quiescent current and low-noise features make it suitable for a wide range of automotive applications. Power supply rejection is 70 dB at low frequency and starts to roll off at 10 kHz. Enable logic control function puts the
LD49100 in shutdown mode, allowing a total current consumption lower than 1 μA.
The device features a precise Power Good indicator, useful to monitor and sequence functions. Internal 1 ms soft-start circuit allows the reduction of inrush current.
The device includes the short-circuit constant current limiting and thermal protection.
The LD49100 is available in AEC-Q100 grade 1 qualified version, in a small 6-pin
DFN6 (3x3 mm) with wettable flank package.
DS13115 - Rev 4 - February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Circuit schematics
Figure 1. LD49100 schematic diagram (adjustable version)
IN
Power-good signal
PG
BandGap reference
OUT protection
ADJ
EN
IN
GND
Figure 2. LD49100 schematic diagram (fixed version)
Power-good signal
IN
PG
LD49100
Circuit schematics
EN
OUT
R
2
R
1
V
SENSE
GND
DS13115 - Rev 4 page 2/28
2
LD49100
Pin configuration
Pin configuration
Figure 3. Pin connection (top view)
EN 1
GND 2
PG 3
6 V
IN
5 V
SENSE
4 V
OUT
LD49100 (fixed version)
EN
GND
PG
1
2
3
6 V
IN
5 ADJ
4 V
OUT
LD49100 (adjustable version)
Symbol
EN
GND
PG
V
OUT
ADJ/V
SENSE
V
IN
GND
Table 1. Pin description
Pin
LD49100
(adjustable version)
LD49100
(fixed version)
1
2
3
4
5
6
Exposed pad
1
2
3
4
5
6
Function
Enable input: set VEN = high to turn on the device
VEN = low to turn off the device
Don't leave this pin floating
Common ground
Power Good
Output voltage
ADJ: adjust pin on the adjustable version. Connect to resistor divider to set the output voltage.
V
SENSE
: output voltage sensing pin on fixed versions. Connect to V
OUT
.
Allows remote sensing
LDO input voltage
Exposed pad has to be connected to GND
DS13115 - Rev 4 page 3/28
3
Note:
LD49100
Absolute maximum ratings
Absolute maximum ratings
Stressing the device above the rating listed in Table 2. Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Symbol
V
IN
V
OUT
/V
SENSE
EN
PG
ADJ
I
OUT
P
D
T
STG
T
OP
T
J-MAX
Table 2. Absolute maximum ratings
Parameter
DC input voltage
DC output voltage, output voltage sense pin
Enable pin
Power Good pin
Adjust pin
Output current
Power dissipation
Storage temperature range
Operating junction temperature range
Maximum junction temperature range
Value
-0.3 to 7
-0.3 to V
IN
+ 0.3
(7 V max.)
-0.3 to 7
-0.3 to 7
4
Internally limited
Internally limited
- 65 to 150
- 40 to 125
150
Unit
V
V
V
V
V
°C
°C
°C
Symbol
R thJA
R thJC
Table 3. Thermal data
Parameter
Thermal resistance junction-ambient
Thermal resistance junction-case
R thJA
for DFN6 based on a 4-layer JEDEC PCB (2S2P) test board with 2 thermal vias.
Value
55
10
Symbol
ESD
Parameter
ESD protection voltage
Table 4. ESD performance
Test conditions
HBM
CDM
CDM corner pins
Value
2
500
750
Unit
°C/W
°C/W
Unit kV
V
DS13115 - Rev 4 page 4/28
4
LD49100
Electrical characteristics
Electrical characteristics
Table 5. LD49100 electrical characteristics (adjustable version) T
J
= 25 °C, V
IN
= 1.8 V, C
IN
= C
OUT
= 1 µF,
I
OUT
= 100 mA, V
EN
= V
IN
, unless otherwise specified.
Symbol
V
IN
V
ADJ
I
ADJ
∆V
OUT
∆V
OUT
∆V
OUT
∆V
OUT
V
DROP e
N
SVR
I
Q
Parameter
Operating input voltage
Test conditions
V
ADJ
accuracy
I
OUT
= 10 mA, T
J
= 25 °C
I
OUT
= 10 mA
-40 °C < T
J
< 125 °C
Adjust pin current
Static line regulation
Transient line regulation
V
OUT
+ 1 V ≤ V
IN
≤ 5.5 V
I
OUT
= 100 mA
∆V
IN
= 500 mV
I
OUT
= 100 mA, t
R
= 5 µs
∆V
IN
= 500 mV
I
OUT
= 100 mA, t
F
= 5 µs
Static load regulation
Transient load regulation
Dropout voltage
Supply voltage rejection
V
O
= 0.8 V
Output noise voltage
Quiescent current
I
OUT
= 10 mA to 1 A
I
OUT
= 10 mA to 1 A t
R
= 5 µs
I
OUT
= 1 A to 10 mA, t
F
= 5 µs
I
OUT
= 1 A V
O
fixed to 1.5 V
-40 °C < T
J
< 125 °C
10 Hz to 100 kHz
I
OUT
= 100 mA
V
OUT
= 0.8 V
V
IN
= 1.8 V+/-V
RIPPLE
V
RIPPLE
= 0.25 V frequency = 1 kHz, I
OUT
= 10 mA
V
IN
= 1.8 V+/-V
RIPPLE
V
RIPPLE
= 0.25 V
V
RIPPLE
= 0.25 V frequency = 10 kHz, I
OUT
= 100 mA
I
OUT
= 0 mA
I
OUT
= 0 mA
-40 °C < T
J
< 125 °C
I
OUT
= 0 to 1 A
I
OUT
= 0 to 1 A
-40 °C < T
J
< 125 °C
V
IN
input current in off mode:
V
EN
Min.
1.5
784
776
Typ.
800
800
0.01
10
10
0.001
40
40
200
30
70
65
20
200
0.001
Max.
5.5
816
824
1
400
50
300
1
Unit
V mV
µA
%/V mVpp
%/mA mVpp mV
µV
RMS dB
µA
DS13115 - Rev 4 page 5/28
DS13115 - Rev 4
LD49100
Electrical characteristics
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
V
PG_ON
V
PG_OFF
Power Good output threshold, rising
Power Good output threshold, falling
-40 °C < T
-40 °C < T
J
J
< 125 °C
< 125 °C
93
99
95
%V
OUT
V
PG_MIN
Minimum Power Good threshold
-40 °C < T
J
< 125 °C 91
%V
OUT_
NOM
V
PG_L
Power Good output voltage low
I sink
= 6 mA open drain output 0.4
V
T
I
V t
SC
EN
I
EN
SS
SHDN
Short-circuit current
Enable input logic low
Enable input logic high
Enable pin input current
Soft-start time
Thermal shutdown
Hysteresis
Output capacitor
R
L
= 0
V
IN
= 1.5 V to 5.5 V
-40 °C < T
J
< 125 °C
V
EN
= V
IN
From enable to 95% of V
OUT(NOM)
0.9
0.5
2.5
0.1
1
160
20
0.4
100
1.5
A
V
V nA ms
°C
C
OUT
Capacitance (see
1 µF
1. Guaranteed by design, not tested in production.
2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply to output voltages below 1.5 V.
3. PG pin floating.
4. Power good is measured as a percentage of the real output voltage value - which includes temperature and process variation - not the nominal one.
5. 91% or V
PG_MIN
wichever is higher.
page 6/28
DS13115 - Rev 4
LD49100
Electrical characteristics
Symbol
V
I
V
OUT
Table 6. LD49100 electrical characteristics (fixed version) T
C
IN
= C
OUT
= 1 µF, I
OUT
= 100 mA, V
EN
= V
J
= 25 °C, V
IN
= V
OUT(NOM)
+ 1 V,
IN
, unless otherwise specified.
Parameter
Operating input voltage
V
OUT
accuracy
Test conditions
I
OUT
= 10 mA, T
J
= 25 °C
I
OUT
= 10 mA
-40 °C < T
J
< 125 °C
Min.
1.5
-2.0
-3.0
Typ.
Max.
5.5
2.0
3.0
I
SENSE
I
SENSE
sense pin current 2
∆V
OUT
∆V
OUT
∆V
OUT
∆V
OUT
V
DROP e
N
SVR
I
Q
Static line regulation
Static load regulation
Output noise voltage
Supply voltage rejection
V
OUT
= 1.5 V
Quiescent current
V
OUT
+ 1 V ≤ V
IN
≤ 5.5 V
I
OUT
= 100 mA
∆V
IN
= 500 mV
I
OUT
= 100 mA, t
R
= 5 µs
∆V
IN
= 500 mV
I
OUT
= 100 mA, t
F
= 5 µs
I
OUT
= 10 mA to 1 A
I
OUT
= 10 mA to 1 A, t
R
= 5 µs
I
OUT
= 1 A to 10 mA, t
F
= 5 µs
I
OUT
= 1 A, V
OUT
> 1.5 V
-40 °C < T
J
< 125 °C
10 Hz to 100 kHz
I
OUT
= 100 mA, V
OUT
= 2.5 V
V
IN
= V
OUT(NOM)
+0.5 V+/-V
RIPPLE
V
RIPPLE
= 0.1 V frequency = 1 kHz, I
OUT
= 10 mA
V
IN
= V
OUT(NOM)
+0.5 V+/-V
RIPPLE
V
RIPPLE
= 0.1 V frequency = 10 kHz, I
OUT
= 100 mA
I
OUT
= 0 mA
I
OUT
= 0 mA, -40 °C < T
J
< 125 °C
I
OUT
= 0 to 1 A
I
OUT
= 0 to 1 A
-40 °C < T
J
< 125 °C
V
IN
input current in OFF mode:
V
EN
0.01
10
10
0.001
40
40
200
85
65
62
20
200
0.001
400
50
300
1
Unit
V
%
μA
%/V mVpp
%/mA mVpp mV
µV
RMS dB
µA
V
PG_ON
V
PG_OFF
V
PG_MIN
V
PG_L
Power Good output threshold, rising
Power Good output threshold, falling
Minimum Power Good threshold
Power Good output voltage low
-40 °C < T
J
< 125 °C
-40 °C < T
J
< 125 °C
-40 °C < T
J
< 125 °C
I sink
= 6 mA open drain output
93
91
91
99
95
0.4
%V
OUT
%V
OUT_
NOM
V page 7/28
LD49100
Electrical characteristics
Symbol
T
I
V t
SC
EN
I
EN
SS
SHDN
Parameter
Short-circuit current
Enable input logic low
Enable input logic high
Enable pin input current
Thermal shutdown
Hysteresis
V
EN
= V
IN
Test conditions
R
L
= 0
V
IN
= 1.5 V to 5.5 V
-40 °C < T
J
< 125 °C
From enable to 95% of V
OUT(NOM)
Min.
0.9
0.5
Typ.
2.5
0.1
1
160
20
Max.
0.4
100
1.5
Unit
A
V
V nA ms
°C
C
OUT
Output capacitor
) 1 µF
1. Guaranteed by design, not tested in production.
2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply to output voltages below 1.5 V.
3. PG pin floating.
4. Power good is measured as a percentage of the real output voltage value - which includes temperature and process variation - not the nominal one.
5. 91% or V
PG_MIN
wichever is higher.
DS13115 - Rev 4 page 8/28
LD49100
Typical performance characteristics
5
Typical performance characteristics
C
IN
= C
OUT
= 1 µF
Figure 4. V
ADJ
accuracy
V
IN
= 1.8 V, V
EN
= I
OUT
= 10 mA
Figure 5. V
OUT
accuracy
T [°C ]
Figure 6. Dropout voltage vs. temperature
(V
OUT
= 2.5 V)
Figure 7. Dropout voltage vs. temperature
(V
OUT
= 1.5 V)
400
350
300
250
200
150
100
50
0
-50
V
EN
= V
IN
, I
OUT
= 1 A
-25 0 25 50
T [°C ]
75 100 125 150
Figure 8. Dropout voltage vs. output current
0.25
0.2
0.15
0.1
0.05
0
0 200 400 600
I
OUT
[mA]
800 1000 1200
Figure 9. Short-circuit current vs. drop voltage
3.5
3
2.5
2
1.5
1
V
IN
from 0 to 5.5 V, V
EN
to V
IN
, V
OUT
shorted to GND
0.5
0
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5 5.5
6
Vdrop [V]
DS13115 - Rev 4 page 9/28
DS13115 - Rev 4
LD49100
Typical performance characteristics
Figure 10. Output voltage vs. input voltage
(V
OUT
= 0.8 V)
1.2
1
0.8
0.6
0.4
0.2
0
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5 5.5
6
V
IN
[V]
Figure 11. Output voltage vs. input voltage
(V
OUT
= 2.5 V)
3
2.5
2
1.5
1
0.5
0
0 0.5
1 1.5
2 2.5
3 3.5
4 4.5
5 5.5
6
Figure 12. Quiescent current vs. temperature
200
180
160
140
120
100
80
60
40
20
0
-50
V
IN
= V
EN
=2.5, Vout = ADJ
-30 -10 10 30 50
T
A
[°C]
70
Iout=1A
No load
90 110 130
Figure 13. V
IN
input current in off mode vs.
temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50
T [°C]
75 100 125 150
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-50 -25
Figure 14. Load regulation
0 25 50
T [°C]
75 100 125 150
Figure 15. Line regulation V
OUT
= 0.8 V
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-50 -25 0 25 50
T [°C]
75 100 125 150 page 10/28
DS13115 - Rev 4
LD49100
Typical performance characteristics
Figure 16. Line regulation V
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-50 -25 0 25 50
T [°C]
75
OUT
= 2.5 V
100 125 150
Figure 17. Supply voltage rejection vs. temperature
(V
OUT
= 0.8 V)
100
80
60
40
20
0
-50 -25 0 25 50
T [°C]
75 100 125 150
Figure 18. Supply voltage rejection vs. temperature
(V
OUT
= 2.5 V)
100
80
60
40
20
0
-50 -25 0 25 50
T [°C]
75 100 125 150
Figure 19. Supply voltage rejection vs. frequency
(V
OUT
= 0.8 V)
100
80
60
40
20
0
0
I I
I I
10 20 30 40 50 60 70 80 90 100 110
Freq [kHz]
Figure 20. Supply voltage rejection vs. frequency
(V
OUT
= 2.5 V)
I I
I I
10 20 30 40 50 60 70 80 90 100 110
Freq [kHz]
Figure 21. Output noise voltage vs. frequency
2.5
2.0
1.5
AP - IOUT = 100mA
AP - IOUT = 10mA
AP - IOUT = 1mA
AP - IOUT = 0A
1.0
0.5
0.0
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 f [Hz]
V
IN
= 1.8 V, V
OUT
= 0.8 V, V
EN
= V
IN page 11/28
DS13115 - Rev 4
LD49100
Typical performance characteristics
Figure 23. Line transient Figure 22. Enable voltage vs. temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0
V
IN
= 5.5 V I
OUT
= 100 mA, V
OUT
= 0 8 V
25 50
T [°C]
75 100 125 150
Figure 24. Load transient Figure 25. Load transient
Figure 26. Load transient Figure 27. Load transient page 12/28
Figure 28. Enable transient
LD49100
Typical performance characteristics
DS13115 - Rev 4 page 13/28
6
LD49100
Application information
Application information
The LD49100 is an ultra low-dropout linear regulator. It provides up to 1 A with a low 200 mV dropout. The input voltage range is from 1.5 V to 5.5 V. The device is available both in fixed and adjustable output versions.
The regulator is equipped with internal protection circuitry, such as short-circuit current limiting and thermal protection.
Figure 29 and Figure 30 illustrate the typical application schematics:
Figure 29. Typical application circuit for fixed output version
V
I N
6
V
I N
P G
3
V
O U T
C
O F F O N
1
E N
LD49100
2
G N D
V
O U T
4
V
SENSE
5
C
O U T
Figure 30. Typical application circuit for adjustable version
V
I N
6
V
I N
C
I N
OFF ON
1
E N
LD49100
GND
2
P G
V
OUT
4
3
A DJ
5
R
1
C
V
OUT
R
2
DS13115 - Rev 4
Regarding to the adjustable version, the output voltage can be fixed from 0.8 V up to the input voltage, minus the voltage drop across the pass element (dropout voltage), by connecting a resistor divider between ADJ pin and the output, thus allowing remote voltage sensing.
page 14/28
6.1
6.1.1
6.1.2
6.2
6.3
LD49100
External capacitors
The resistor divider should be selected as follows:
VOUT = VADJ 1 + R1/R2 (1) with
VADJ = 0.8V typ.
Resistors should be used with values in the range from 10 kΩ to 50 kΩ. Lower values can also be suitable, but they increase the current consumption.
(2)
External capacitors
The LD49100 voltage regulator requires external low ESR capacitors to assure control loop stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance defined in the following sections.
Input and output capacitors should be located as close as possible to the relevant pins.
Input capacitor
An input capacitor with a minimum value of 1 μF must be located as close as possible to the input pin of the device and returned to a clean analog ground. A good quality, low-ESR ceramic capacitor is suggested. It helps to ensure stability of the control loop, reduces the effects of inductive sources and improves ripple rejection.
A value above 1 µF may be chosen when the application involves fast load transients.
Output capacitor
The LD49100 requires a low-ESR capacitor connected on its output to keep the control loop stable and reduce the risk of ringing and oscillations. The control loop is designed to be stable with any good quality ceramic capacitor (such as X5R/X7R types) with a minimum value of 1 µF and equivalent series resistance in the 0 to 150 mΩ range.
It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the full operating temperature, load and input voltage ranges to assure stability. Therefore, capacitance and
ESR variations must be taken into account in the design phase to ensure the device works in the expected stability region.
If the conditions above are met, there is no maximum limit to the output capacitance.
Output voltage sense pin
In the fixed output voltage version, on pin 5, a V
SENSE
connection is available. This pin must not be left floating, since it is necessary for a correct sensing of the output voltage. It can be either connected to the load in a remote sensing configuration, or directly shorted to the V
OUT
pin (pin 4, refer to
Figure 29. Typical application circuit for fixed output version .
Power dissipation
An internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 160
°C. This feature protects the device from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without the risk of damaging the device.
A good PC layout should be used to maximize power dissipation. The thermal path for the heat generated by the device is from the die to the copper lead frame, through the package leads and exposed pad, to the PCB copper layer. The PCB copper layer works as a heatsink. The footprint copper pads should be as wide as possible to spread and dissipate the heat to the surrounding ambient. Feed-through vias to the inner or backside copper layers are also useful to improve the overall thermal performance of the device.
The device power dissipation depends on the input voltage, output voltage and output current, and is given by:
PD = VIN − VOUT IOUT
Junction temperature of the device is:
(3)
TJ_MAX = TA + RtℎJA × PD (4)
DS13115 - Rev 4 page 15/28
6.4
6.5
LD49100
Enable function where:
T
J_MAX
is the maximum junction of the die,125 °C
T
A
is the ambient temperature
R thJA
is the thermal resistance junction-to-ambient
Figure 31. Power dissipation vs. ambient temperature
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -30 -10 10 70 90 30
T
A
[°C]
50 110 130
Enable function
The LD49100 features the enable function. When EN voltage is higher than 0.9 V, the device is ON, and if it is lower than 0.4 V, the device is OFF. In shutdown mode, consumption is lower than 1 μA.
An internal soft-startup circuit helps reducing the in-rush current at turn-on, by providing a typical output voltage rise-time of 1 ms.
EN pin has not an internal pull-up, so it cannot be left floating if it is not used.
Power Good function
Some applications require a flag showing that the output voltage is in the correct range.
Power Good threshold depends on the output voltage. When it is higher than V
PG-ON to high impedance. If it is below V
PG-OFF
, Power Good (PG) pin goes
PG pin goes to low impedance. If the device works well, Power Good pin is at high impedance.
If the device is disabled (EN pin low) the PG signal is set to high impedance. This is done intentionally to avoid pull-down current by the PG pin in disabled mode.
Power Good function requires an external pull-up resistor, which has to be connected between PG pin and V
IN
or
V
OUT
. PG pin typical current capability is up to 6 mA. A pull-up resistor for PG should be in the range from 100 kΩ to 1 MΩ. If Power Good function is not used, PG pin has to remain floating.
DS13115 - Rev 4 page 16/28
7
LD49100
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS13115 - Rev 4 page 17/28
7.1
LD49100
DFN6 (3x3 mm) automotive-grade package information
DFN6 (3x3 mm) automotive-grade package information
Figure 32. DFN6 (3x3 mm) automotive-grade package outline
Bottom view
Detail A
Detail A
DS13115 - Rev 4
Top view
DM00169862_1 page 18/28
LD49100
DFN6 (3x3 mm) automotive-grade package information
Dim.
A
A1 b
D
D2 e
E
E2
L
Table 7. DFN6 (3x3 mm) automotive-grade mechanical data
Min.
0.80
0.0
0.20
2.95
2.30
2.95
1.50
0.30
mm
Typ.
0.85
0.25
3.00
2.40
0.95
3.00
1.60
0.40
Figure 33. DFN6 (3x3 mm) automotive-grade recommended footprint
Max.
0.90
0.05
0.30
3.05
2.50
3.05
1.70
0.50
DS13115 - Rev 4 page 19/28
7.2
DFN6 (3x3 mm) packing information
Figure 34. DFN6 (3x3) tape outline
LD49100
DFN6 (3x3 mm) packing information
DS13115 - Rev 4
7875978_N page 20/28
DS13115 - Rev 4
Figure 35. DFN6 (3x3 mm) tape oriented
LD49100
DFN6 (3x3 mm) packing information
Figure 36. DFN6 (3x3 mm) reel outline
7875978_N page 21/28
Dim.
A0
B0
K0
LD49100
DFN6 (3x3 mm) packing information
Table 8. DFN6 (3x3) tape and reel mechanical data
Min.
3.20
3.20
1 mm
Typ.
3.30
3.30
1.10
Max.
3.40
3.40
1.20
DS13115 - Rev 4 page 22/28
8
Ordering information
Order codes
LD49100PURY
LD49100PU10RY
LD49100PU12RY
LD49100PU15RY
LD49100PU18RY
LD49100PU25RY
LD49100PU30RY
LD49100PU33RY
Table 9. Order code
Output voltages
Adjustable
1.0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
3.3 V
LD49100
Ordering information
DS13115 - Rev 4 page 23/28
LD49100
Revision history
Date
26-Aug-2020
01-Sep-2020
11-Sep-2020
18-Feb-2021
Table 10. Document revision history
Revision
1
2
3
4
Changes
Initial release.
Change maturity status.
Load transient characteristics update in Section 5 Typical performance characteristics.
Added new order codes LD49100PU10RY and LD49100PU15RY in
DS13115 - Rev 4 page 24/28
LD49100
Contents
Contents
DS13115 - Rev 4 page 25/28
LD49100
List of tables
List of tables
Table 5. LD49100 electrical characteristics (adjustable version) T
Table 6. LD49100 electrical characteristics (fixed version) T
DS13115 - Rev 4 page 26/28
LD49100
List of figures
List of figures
Figure 6. Dropout voltage vs. temperature (V
= 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Dropout voltage vs. temperature (V
= 1.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Output voltage vs. input voltage (V
= 0.8 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11. Output voltage vs. input voltage (V
= 2.5 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 17. Supply voltage rejection vs. temperature (V
= 0.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 18. Supply voltage rejection vs. temperature (V
= 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 19. Supply voltage rejection vs. frequency (V
= 0.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 20. Supply voltage rejection vs. frequency (V
= 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DS13115 - Rev 4 page 27/28
LD49100
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DS13115 - Rev 4 page 28/28
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