STMicroelectronics STM32L4, STM32L4+ Series Microcontroller User manual

UM2305

User manual

STM32L4 and STM32L4+ Series safety manual

Introduction

This document must be read along with the technical documentation such as reference manual(s) and datasheets for the

STM32L4 and STM32L4+ Series microcontroller devices, available on www.st.com

.

It describes how to use the devices in the context of a safety-related system, specifying the user's responsibilities for installation and operation in order to reach the targeted safety integrity level. It also pertains to the X-CUBE-STL software product.

It provides the essential information pertaining to the applicable functional safety standards, which allows system designers to avoid going into unnecessary details.

The document is written in compliance with IEC 61508, and it provides information relative to other functional safety standards.

The safety analysis in this manual takes into account the device variation in terms of memory size, available peripherals, and package.

UM2305 - Rev 10 - June 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

1

1.1

Note:

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About this document

About this document

Purpose and scope

This document describes how to use Arm ® Cortex ® ‑ M4 -based STM32L4 and STM32L4+ Series

microcontroller unit (MCU)

devices (further also referred to as Device (s)) in the context of a safety ‑ related system, specifying the user's responsibilities for installation and operation, in order to reach the desired safety integrity level.

It is useful to system designers willing to evaluate the safety of their solution embedding one or more Device(s) .

For terms used, refer to the glossary at the end of the document.

Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

1.2

Normative references

•

•

This document is written in compliance with the IEC 61508 international norm for functional safety of electrical, electronic and programmable electronic safety-related systems, version IEC 61508:1-7 © IEC:2010.

The other functional safety standards considered in this manual are:

• ISO 13849-1:2015, ISO13849-2:2012

IEC 62061:2005+AMD1:2012+AMD2:2015

IEC 61800-5-2:2016

The following table maps the document content with respect to the IEC 61508-2 Annex D requirements.

Table 1. Document sections versus IEC 61508-2 Annex D safety requirements

Safety requirement

D2.1 a) a functional specification of the functions capable of being performed

D2.1 b) identification of the hardware and/or software configuration of the Compliant item

D2.1 c) constraints on the use of Compliant item or assumptions on which analysis of the behavior or failure rates of the item are based

D2.2 a) the failure modes of Compliant item due to random hardware failures, that result in a failure of the function and that are not detected by diagnostics internal to Compliant item ;

D2.2 b) for every failure mode in a), an estimated failure rate;

D2.2 c) the failure modes of Compliant item due to random hardware failures, that result in a failure of the function and that are detected by diagnostics internal to Compliant item ;

D2.2 d) the failure modes of the diagnostics, internal to Compliant item due to random hardware failures, that result in a failure of the diagnostics to detect failures of the function;

D2.2 e) for every failure mode in c) and d), the estimated failure rate;

D2.2 f) for every failure mode in c) that is detected by diagnostics internal to Compliant item , the diagnostic test interval;

D2.2 g) for every failure mode in c) the outputs of Compliant item initiated by the internal diagnostics;

D2.2 h) any periodic proof test and/or maintenance requirements;

D2.2 i) for those failure modes, in respect of a specified function, that are capable of being detected by external diagnostics, sufficient information must be provided to facilitate the development of an external diagnostics capability.

D2.2 j) the hardware fault tolerance;

D2.2 k) the classification as type A or type B of that part of Compliant item that provides the function (see

7.4.4.1.2 and 7.4.4.1.3);

Section number

3

3.2

3.2

3.7

3.2.2

3.6

3.7

3

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1.3

Reference documents

[1]

[2]

AN5112: Results of FMEA on STM32L4 and STM32L4+ Series microcontrollers.

AN5111: FMEDA snapshots for STM32L4 and STM32L4+ Series microcontrollers.

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Reference documents

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2

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Device development process

Device development process

STM32 series product development process (see

Figure 1

), compliant with the IATF 16949 standard, is a set of interrelated activities dedicated to transform customer specification and market or industry domain requirements into a semiconductor device and all its associated elements (package, module, sub-system, hardware, software, and documentation), qualified with ST internal procedures and fitting ST internal or subcontracted manufacturing technologies.

Figure 1. STMicroelectronics product development process

1 Conception

2 Design and validation

3 Qualification

· Key characteristics and requirements related to future uses of the device

· Industry domain(s), specific customer requirements and definition of controls and tests needed for compliance

· Product target specification and strategy

· Project manager appointment to drive product development

· Evaluation of the technologies, design tools and IPs to be used

· Design objective specification and product validation strategy

· Design for quality techniques (DFD, DFT, DFR,

DFM, …) definition

· Architecture and positioning to make sure the software and hardware system solutions meet the target specification

· Product approval strategy and project plan

· Semiconductor design development

· Hardware development

· Software development

· Analysis of new product specification to forecast reliability performance

· Reliability plan, reliability design rules, prediction of failure rates for operating life test using Arrhenius’s law and other applicable models

· Use of tools and methodologies such as

APQP, DFM, DFT, DFMEA

· Detection of potential reliability issues and solution to overcome them

· Assessment of Engineering

Samples (ES) to identify the main potential failure mechanisms

· Statistical analysis of electrical parameter drifts for early warning in case of fast parametric degradation (such as retention tests)

· Failure analysis on failed parts to clarify failure modes and mechanisms and identify the root causes

· Physical destructive analysis on good parts after reliability tests when required

· Electrostatic discharge

(ESD) and latch-up sensitivity measurement

· Successful completion of the product qualification plan

· Secure product deliveries on advanced technologies using stress methodologies to detect potential weak parts

· Successful completion of electrical characterization

· Global evaluation of new product performance to guarantee reliability of customer manufacturing process and final application of use (mission profile)

· Final disposition for product test, control and monitoring

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3

3.1

3.2

3.2.1

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Reference safety architecture

Reference safety architecture

This section reports details of the STM32L4 and STM32L4+ Series safety architecture.

Safety architecture introduction

Device (s) analyzed in this document can be used as Compliant item (s) within different safety applications.

The aim of this section is to identify such Compliant item (s), that is, to define the context of the analysis with respect to a reference concept definition. The concept definition contains reference safety requirements, including design aspects external to the defined Compliant item .

As a consequence of Compliant item approach, the goal is to list the system-related information considered during the analysis, rather than to provide an exhaustive hazard and risk analysis of the system around

Device . Such information includes, among others, application-related assumptions for danger factors, frequency of failures and diagnostic coverage already guaranteed by the application.

Compliant item

This section defines the Compliant item term and provides information on its usage in different safety architecture schemes.

Definition of Compliant item

According to IEC 61508:1 clause 8.2.12, Compliant item is any item (for example an element) on which a claim is being made with respect to the clauses of IEC 61508 series. Any mature Compliant item must be described in a safety manual available to End user .

In this document, Compliant item

is defined as a system including one or two STM32 devices (see Figure 2 ). The

communication bus is directly or indirectly connected to sensors and actuators.

Figure 2. STM32 as Compliant item

Actuator

Sensor

S

S

Remote controller

Remote controller

Processing element

STM32 device(s)

Compliant item

Remote controller

Remote controller

A

A

3.2.2

Other components might be related to Compliant item , like the external HW components needed to guarantee either the functionality of Device (external memory, clock quartz and so on) or its safety (for example, the external watchdog or voltage supervisors).

A defined Compliant item can be classified as element according to IEC61508-4, 3.4.5.

Safety functions performed by Compliant item

In essence, Compliant item architecture encompasses the following processes performing the safety function or a part of it:

• input processing elements (PEi) reading safety related data from the remote controller connected to the sensor(s) and transferring them to the following computation elements

• computation processing elements (PEc) performing the algorithm required by the safety function and transferring the results to the following output elements

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3.2.3

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Compliant item

•

•

•

• output processing elements (PEo) transferring safety related data to the remote controller connected to the actuator in 1oo2 architecture, potentially a further voting processing element (PEv) the computation processing elements can be involved (to the extent depending to the target safety integrity) in the implementation of local software-based diagnostic functions; this is represented by the block PEd processes external to Compliant item ensuring safety integrity, such as watchdog (WDTe) and voltage monitors (VMONe)

The role of the PEv process is clarified in Section 3.2.4 Reference safety architectures - 1oo2

. The role of the

WDTe and VMONe external processes is clarified under Section 3.6 Hardware and software diagnostics

:

•

WDTe: refer to

CPU_SM_1,

External watchdog – CPU_SM_5 and

Control flow monitoring in Application software –

• VMONe: refer to

Supply voltage internal monitoring (PVD)

– VSUP_SM_1 and System-level power supply management - VSUP_SM_5.

•

•

In summary, Devices support the implementation of End user safety functions consisting of three operations:

• safe acquisition of safety-related data from input peripheral(s) safe execution of Application software program and safe computation of related data safe transfer of results or decisions to output peripheral(s)

Claims on Compliant item and computation of safety metrics are done with respect to these three basic operations.

According to the definition for implemented safety functions, Compliant item (element) can be regarded as type B

(as per IEC61508-2, 7.4.4.1.3 definition). Despite accurate, exhaustive and detailed failure analysis, Device has to be considered as intrinsically complex. This implies its type B classification.

Two main safety architectures are identified: 1oo1 (using one Device ) and 1oo2 (using two Devices ).

Reference safety architectures - 1oo1

1oo1 reference architecture ( Figure 3 ) ensures safety integrity of

Compliant item through combining Device internal processes (implemented safety mechanisms) with external processes WDTe and VMONe.

1oo1 reference architecture targets

safety integrity level (SIL)

SIL2 .

Figure 3. 1oo1 reference architecture

VMONe WDTe

Sensors

PEi PEc

PEd

PEo

Actuators

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3.2.4

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Compliant item

Reference safety architectures - 1oo2

1oo2 reference architecture ( Figure 4 ) contains two separate channels, either implemented as 1oo1

reference architecture ensuring safety integrity of Compliant item through combining Device internal processes

(implemented safety mechanisms) with external processes WDTe and VMONe. The overall safety integrity is then

ensured by the external voter PEv, which allows claiming hardware fault tolerance (HFT)

equal to 1. Achievement of higher safety integrity levels as per IEC61508-2 Table 3 is therefore possible. Appropriate separation between the two channels (including power supply separation) should be implemented in order to avoid huge impact of

common-cause failures (refer to Section 4.2 Analysis of dependent failures

). However, β and βD parameters computation is required.

1oo2 reference architecture targets SIL3 .

Figure 4. 1oo2 reference architecture

VMONe WDTe

PEi PEc

PEd

PEo

Sensors PEv Actuators

PEi PEc

PEd

PEo

VMONe WDTe

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Safety analysis assumptions

3.3

3.3.1

Caution:

Note:

Safety analysis assumptions

This section collects all assumptions made during the safety analysis of Devices .

Safety requirement assumptions

The safety concept specification, the overall safety requirement specification and the consequent allocation determine the requirements for Compliant item as further listed. ASR stands for assumed safety requirement.

It is End user ’s responsibility to check the compliance of the final application with these assumptions.

•

•

ASR1: Compliant item can be used to implement four kinds of safety function modes of operation according to

IEC61508-4,3.5.16:

• a a a

continuous mode (CM) low-demand (LD)

CM or HD SIL2

SIL

or high-demand (HD)

3 safety function (

safety function ( CM2

LD3

), or

SIL3

), or

safety function ( CM3 ), or

• a LD SIL2 safety function ( LD2 ).

ASR2: Compliant item is used to implement safety function(s) allowing a specific worst-case time budget (see note below) for the STM32 MCU to detect and react to a failure. That time corresponds to the portion of the

process safety time (PST)

allocated to Device ( STM32xx Series duty

in Figure 5 ) in error reaction chain at system

level.

The computation for time budget mainly depends on the execution speed for periodic tests implemented by software. Such duration might depends on the actual amount of hardware resources (RAM memory,

Flash memory, peripherals) actually declared as safety-related. Further constraints and requirements from

IEC61508-2, 7.4.5.3 must be considered.

Figure 5. Allocation and target for STM32 PST

STM32xx Series duty

MCU detection FW reaction SW reaction

End user duty

….

Actuator reaction

System-level PST

Note:

ASR3: Compliant item is used to implement safety function(s) that can be continuously powered on for a period over eight hours. It is assumed to not require any proof test, and the lifetime of the product is considered to be no less than 10 years.

ASR4: It is assumed that only one safety function is performed or if many, all functions are classified with the same SIL and therefore they are not distinguishable in terms of their safety requirements.

ASR5: In case of multiple safety function implementations, it is assumed that End user is responsible to duly ensure their mutual independence.

ASR6: It is assumed that there are no non-safety-related functions implemented in Application software , coexisting with safety functions.

ASR7: It is assumed that the implemented safety function(s) does (do) not depend on transition of Device to and from a low-power state.

ASR8: The local safe state of Compliant item is the one in which either:

• SS1: Application software is possible.

is informed by the presence of a fault and a reaction by Application software itself

• SS2: Application software cannot be informed by the presence of a fault or Application software is not able to execute a reaction.

End user must take into account that random hardware failures affecting Device can compromise its operation

(for example failure modes affecting the program counter prevent the correct execution of software).

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Note:

3.4

3.5

3.6

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Electrical specifications and environment limits

The following table provides details on the SS1 and SS2 safe states.

Table 2. SS1 and SS2 safe state details

Safe state

SS1

SS2

Condition

Compliant item action

Application software is informed by the presence of a fault and a reaction by Application software itself is possible.

Application software cannot be informed by the presence of a fault or Application software is not able to execute a reaction.

Fault reporting to Application software

Reset signal issued by WDTe

System transition to safe state – 1oo1 architecture

Application software drives the overall system in its safe state

WDTe drives the overall system in its safe state (“safe shut-down”)

(1)

1. Safe state achievement intended here is compliant to Note on IEC 61508-2, 7.4.8.1

System transition to safe state – 1oo2 architecture

Application software in one of the two channels drives the overall system in its safe state

PEv drives the overall system in its safe state

ASR9: It is assumed that the safe state defined at system level by End user is compatible with the assumed local safe state (SS1, SS2) for Compliant item .

ASR10: Compliant item is assumed to be analyzed according to routes 1H and 1S of IEC 61508-2.

Refer to

Section 3.5 Systematic safety integrity and Section 3.6 Hardware and software diagnostics .

ASR11: Compliant item is assumed to be regarded as type B, as per IEC 61508:2, 7.4.4.1.2.

ASR12: It is assumed that dual-bank Flash memory mass erase and reprogramming features are used during maintenance state of the final system, and not for the implementation of the safety function.

Electrical specifications and environment limits

•

•

To ensure safety integrity, the user must operate Device (s) within its (their) specified:

• absolute maximum rating capacity operating conditions

For electrical specifications and environmental limits of Device (s), refer to its (their) technical documentation such as datasheet(s) and reference manual(s) available on www.st.com

.

Systematic safety integrity

According to the requirements of IEC 61508 -2, 7.4.2.2, the Route 1S is considered in the safety analysis of

Device (s). As clearly authorized by IEC61508-2, 7.4.6.1, STM32 MCU products can be considered as standard, mass-produced electronic integrated devices, for which stringent development procedures, rigorous testing and extensive experience of use minimize the likelihood of design faults. However, ST internally assesses the compliance of the Device development flow, through techniques and measures suggested in the IEC 61508-2

Annex F. A safety case database

(see Section 5 List of evidences

) keeps evidences of the current compliance level to the norm.

Hardware and software diagnostics

This section lists all the safety mechanisms (hardware, software and application-level) considered in the

Device safety analysis. It is expected that users are familiar with the architecture of Device , and that this document is used in conjunction with the related Device datasheet, user manual and reference information. To avoid inconsistency and redundancy, this document does not report device functional details. In the following descriptions, the words safety mechanism , method , and requirement are used as synonyms.

As the document provides information relative to the superset of peripherals available on the devices it covers

(not all devices have all peripherals), users are supposed to disregard any recommendations not applicable to their Device part number of interest.

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3.6.1

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Hardware and software diagnostics

Information provided for a function or peripheral applies to all instances of such function or peripheral on Device .

Refer to its reference manual or/and datasheet for related information.

The implementation guidelines reported in the following section are for reference only. The safety verification executed by ST during the Device safety analysis and related diagnostic coverage figures reported in this manual

(or related documents) are based on such guidelines. For clarity, safety mechanisms are grouped by Device function.

Information is organized in form of tables, one per safety mechanism, with the following fields:

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on

Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Unique safety mechanism code/identifier used also in FMEA document. Identifiers use the scheme mmm_SM_x where mmm is a 3- or 4-letter module (function, peripheral) short name, and x is a number. It is possible that the numbering is not sequential (although usually incremental) and/or that the module short name is different from that used in other documents.

Short mnemonic description

ST: method is available on silicon.

End user : method must be implemented by End user through Application software modification, hardware solutions, or both.

Detailed implementation sometimes including notes about the safety concept behind the introduction of the safety mechanism.

Describes how the fault detection is reported to Application software .

Time that the safety mechanism needs to detect the hardware failure.

•

•

Reports fault model(s) addressed by the diagnostic (permanent, transient, or both), and other information:

If ranked for Fault avoidance : method contributes to lower the probability of occurrence of a failure

If ranked for Systematic : method is conceived to mitigate systematic errors (bugs) in

Application software design

Reports if safety mechanism implementation or characteristics change among different Device part numbers.

Specific operation to be executed to activate the contribution of the safety mechanism

Continuous : safety mechanism is active in continuous mode.

Periodic: safety mechanism is executed periodically

(1) .

On-demand: safety mechanism is activated in correspondence to a specified event (for instance, reception of a data message).

Startup: safety mechanism is supposed to be executed only at power-up or during off-line maintenance periods.

Reports specific procedure (if any and recommended) to allow on-line tests of safety mechanism efficiency. If no specific procedure applies (as for the majority of safety mechanisms), the field indicates Not applicable .

Reports the safety mechanism(s) associated in order to correctly manage a multiple-fault scenario

(refer to

Section 4.1.3 Notes on multiple-fault scenario

).

Additional recommendations or limitations (if any) not reported in other fields.

1. In CM systems, safety mechanism can be accounted for diagnostic coverage contribution only if it is executed at least once per PST. For LD and HD systems, constraints from IEC61508-2, 7.4.5.3 must be applied.

Arm ® Cortex ® -M4 CPU

SM CODE

Description

Table 3. CPU_SM_0

CPU_SM_0

Periodic core self-test software for Arm ® Cortex ® -M4 CPU .

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Hardware and software diagnostics

SM CODE

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

CPU_SM_0

End user or ST

The software test is built around well-known techniques already addressed by IEC 61508:7,

A.3.2 (Self-test by software: walking bit one-channel). To reach the required values of coverage, the self-test software is specified by means of a detailed analysis of all the CPU failure modes and related failure modes distribution.

Depends on implementation

Depends on implementation

Permanent

None

None

Periodic

Self-diagnostic capabilities can be embedded in the software, according to the test implementation design strategy chosen. The adoption of checksum protection on results variables and defensive programming are recommended.

CPU_SM_5: External watchdog

This method is the main asset in STM32L4 and STM32L4+ Series safety concept. Hardware integrity of the CPU is a key factor, given that the defined diagnostics for MCU peripherals are to major part software-based.

Startup execution of this safety mechanism is recommended for multiple fault mitigations refer to

Section 4.1.3 Notes on multiple-fault scenario

for details.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Table 4. CPU_SM_1

CPU_SM_1

Control flow monitoring in Application software

End user

A significant part of the failure distribution of CPU core for permanent faults is related to failure modes directly related to program counter loss of control or hang-up. Due to their intrinsic nature, such failure modes are not addressed by a standard software test method like

SM_CPU_0. Therefore, it is necessary to implement a run-time control of Application software flow in order to monitor and detect deviation from the expected behavior due to such faults.

Linking this mechanism to watchdog firing assures that severe loss of control (or, in the worst case, a program counter hang-up) is detected.

•

•

•

•

•

The guidelines for the implementation of the method are the following:

Different internal states of Application software are well documented and described (the use of a dynamic state transition graph is encouraged).

Monitoring of the correctness of each transition between different states of Application software is implemented.

Transition through all expected states during the normal Application software program loop is checked.

A function in charge of triggering the system watchdog is implemented in order to constrain the triggering (preventing the issue of CPU reset by watchdog) also to the correct execution of the above-described method for program flow monitoring. The use of window feature available on internal window watchdog (WWDG) is recommended.

The use of the independent watchdog (IWDG), or an external one, helps to implement a more robust control flow mechanism fed by a different clock source.

In any case, safety metrics do not depend on the kind of watchdog in use (the adoption of independent or external watchdog contributes to the mitigation of dependent failures, see

Section 4.2.2 Clock ).

Depends on implementation

Depends on implementation. Higher value is fixed by watchdog timeout interval.

Permanent/transient

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Hardware and software diagnostics

SM CODE

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

CPU_SM_1

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

None

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 5. CPU_SM_2

CPU_SM_2

Double computation in Application software

End user

A timing redundancy for safety-related computation is considered to detect transient faults affecting the Arm ® Cortex access.

® -M4 CPU subparts devoted to mathematical computations and data

•

•

•

The guidelines for the implementation of the method are the following:

The requirement needs be applied only to safety-relevant computation, which in case of wrong result could interfere with the system safety functions. Such computation must be therefore carefully identified in the original Application software source code

Both mathematical operation and comparison are intended as computation.

The redundant computation for mathematical computation is implemented by using copies of the original data for second computation, and by using an equivalent formula if possible

Depends on implementation

Depends on implementation

Transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

End user is responsible to carefully avoid that the intervention of optimization features of the used compiler removes timing redundancies introduced according to this condition of use.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Table 6. CPU_SM_3

CPU_SM_3

Arm ® Cortex ® -M4 HardFault exceptions

ST

HardFault exception raise is an intrinsic safety mechanism implemented in Arm ® Cortex ® -M4 core, mainly dedicated to intercept systematic faults due to software limitations or error in software design (causing for example execution of undefined operations, unaligned address access). This safety mechanism is also able to detect hardware random faults inside the CPU bringing to such described abnormal operations.

High-priority interrupt event

Depends on implementation. Refer to functional documentation.

Permanent/transient

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Hardware and software diagnostics

SM CODE

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

CPU_SM_3

None

None

Continuous

It is possible to write a test procedure to verify the generation of the HardFault exception; anyway, given the expected minor contribution in terms of hardware random-failure detection, such implementation is optional.

CPU_SM_0: Periodic core self-test software

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 7. CPU_SM_4

CPU_SM_4

Stack hardening for Application software

End user

The stack hardening method is required to address faults (mainly transient) affecting CPU register bank. This method is based on source code modification, introducing information redundancy in register-passed information to called functions.

•

•

•

The guidelines for the implementation of the method are the following:

To pass also a redundant copy of the passed parameters values (possibly inverted) and to execute a coherence check in the function.

To pass also a redundant copy of the passed pointers and to execute a coherence check in the function.

For parameters that are not protected by redundancy, to implement defensive programming techniques (plausibility check of passed values). For example enumerated fields are to be checked for consistency.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

This method partially overlaps with defensive programming techniques required by IEC61508 for software development. Therefore in presence of Application software qualified for safety integrity greater or equal to SC2, optimizations are possible.

SM CODE

Description

Ownership

Detailed implementation

Table 8. CPU_SM_5

CPU_SM_5

External watchdog

End user

Using an external watchdog linked to control flow monitoring method (refer to CPU_SM_1) addresses failure mode of program counter or control structures of CPU .

External watchdog can be designed to be able to generate the combination of signals needed on the final system to achieve the safe state. It is recommended to carefully check the assumed requirements about system safe state reported in

Section 3.3.1 Safety requirement assumptions .

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Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device

Initialization

Periodicity

configuration

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

CPU_SM_5

It also contributes to dramatically reduce potential common cause failures, because the external watchdog is clocked and supplied independently of Device .

Depends on implementation

Depends on implementation (watchdog timeout interval)

Permanent/transient

None

Depends on implementation

Continuous

To be defined at system level (outside the scope of Compliant item analysis).

CPU_SM_1: Control flow monitoring in Application software

In case of usage of windowed watchdog, End user must consider possible tolerance in

Application software execution to avoid false error reports (affecting system availability).

It is worth noting that the use of an external watchdog could be needed anyway when Device is used to trigger final elements, in order to comply at system level with requirements from

IEC61508-2:2010 Table A.1/Table A.14.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 9. CPU_SM_6

CPU_SM_6

Independent watchdog

ST

Using the IDWG watchdog linked to control flow monitoring method (refer to CPU_SM_1) addresses failure mode of program counter or control structures of CPU .

Reset signal generation

Depends on implementation (watchdog timeout interval)

Permanent

None

IWDG activation. It is recommended to use hardware watchdog in option byte settings (IWDG is automatically enabled after reset).

Continuous

WDG_SM_1: Software test for watchdog at startup

CPU_SM_1: Control flow monitoring in Application software

WDG_SM_0: Periodic read-back of configuration registers

The IWDG intervention is able to achieve a potentially “incomplete” local safe state because it can only guarantee that CPU is reset. No guarantee that Application software can be still executed to generate combinations of output signals that might be needed by the external system to achieve the final safe state. If this limitation turn out in a blocking point, End user must adopt CPU_SM_5.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Table 10. CPU_SM_7

CPU_SM_7

Memory protection unit ( MPU ).

ST

The CPU memory protection unit is able to detect illegal access to protected memory areas, according to criteria set by End user .

Exception raise (MemManage).

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Hardware and software diagnostics

SM CODE

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

CPU_SM_7

Refer to functional documentation

Systematic (software errors)

Permanent/transient (only program counter and memory access failures)

None

MPU registers must be programmed at start-up.

On line

MPU_SM_1: MPU software test

MPU_SM_0: Periodic read-back of MPU configuration registers

•

•

•

The use of memory partitioning and protection by MPU functions is highly recommended when multiple safety functions are implemented in Application software . The MPU can be indeed used to enforce privilege rules separate processes enforce access rules

Hardware random-failure detection capability for MPU is restricted to well-selected failure modes, mainly affecting program counter and memory access CPU functions. The associated diagnostic coverage is therefore not expected to be relevant for the safety concept of Device .

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 11. CPU_SM_8

CPU_SM_8

AMBA firewall

ST

The Firewall can protect a specific part of code or data in the non-volatile memory, and/or it can protect volatile data in the SRAM 1 from interferences by the code executed outside the protected area.

Illegal AMBA bus accesses are blocked through bus snooping.

DMA accesses to restricted area are blocked.

Reset generation

Refer to functional documentation

Systematic

None

Firewall protection must be enabled/disabled at run time.

On demand (Firewall open/close)

Not required

Not required

This diagnostic feature has been designed mainly to implement information security schemes on STM32L4 and STM32L4+ Series MCUs. Anyway, it also contributes to the systematic capability increase for Application software , being able to detect illegal accesses caused by software design faults. In the framework of STM32L4 and STM32L4+ Series safety concept, it could help to mitigate potential common cause failures related to DMA malfunctions.

SM CODE

Description

Ownership

Table 12. MPU_SM_0

MPU_SM_0

Periodic read-back of MPU configuration registers

End user

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

MPU_SM_0

This method must be applied to MPU configuration registers (also unused by End userApplication software ).

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 13. MPU_SM_1

MPU_SM_1

MPU software test

End user

This method tests MPU capability to detect and report memory accesses violating the policy enforcement implemented by the MPU itself.

The implementation is based on intentionally performing read and write accesses outside the memory areas allowed by the MPU region programming, and collecting and verifying related generated error exceptions.

Test can be executed with the final MPU region programming or with a dedicated one.

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

Startup execution of this safety mechanism is recommended for multiple fault mitigations refer to

Section 4.1.3 Notes on multiple-fault scenario

.

3.6.2

System bus architecture/BusMatrix

Description

Ownership

SM CODE

Table 14. BUS_SM_0

BUS_SM_0

Periodic software test for interconnections

End user

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

BUS_SM_0

The intra-chip connection resources (Bus Matrix, AHB or APB bridges) needs to be periodically tested for permanent faults detection. Note that STM32L4 and STM32L4+

Series devices have no hardware safety mechanism to protect these structures. The test executes a connectivity test of these shared resources, including the testing of the arbitration mechanisms between peripherals.

According to IEC 61508:2 Table A.8, A.7.4 the method is considered able to achieve high levels of coverage.

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

Implementation can be considered in large part as overlapping with the widely used Periodic read-back of configuration registers required for several peripherals.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 15. BUS_SM_1

BUS_SM_1

Information redundancy in intra-chip data exchanges

End user

This method requires to add some kind of redundancy (for example a CRC checksum at packet level) to each data message exchanged inside Device .

Message integrity is verified using the checksum by Application software , before consuming data.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

Implementation can be in large part overlapping with other safety mechanisms requiring information redundancy on data messages for communication peripherals. Optimizations are therefore possible.

3.6.3

Embedded SRAM

SM CODE

Description

Ownership

Table 16. RAM_SM_0

RAM_SM_0

Periodic software test for static random access memory (SRAM)

End user or ST

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

RAM_SM_0

To enhance the coverage on SRAM data cells and to ensure adequate coverage for permanent faults affecting the address decoder it is required to execute a periodic software test on the system RAM memory. The selection of the algorithm must ensure the target SFF coverage for both the RAM cells and the address decoder. Evidences of the effectiveness of the coverage of the selected method must be also collected

Depends on implementation

Depends on implementation

Permanent

RAM size can change according to the part number.

Depends on implementation

Periodic

Self-diagnostic capabilities can be embedded in the software, according to the test implementation design strategy chosen.

CPU_SM_0: Periodic core self-test software

Usage of a March test C- is recommended.

Because the nature of this test can be destructive, RAM contents restore must be implemented. Possible interferences with interrupt-serving routines fired during test execution must be also considered (such routines can access to RAM invalid contents).

Startup execution of this safety mechanism is recommended for multiple fault mitigations refer to

Section 4.1.3 Notes on multiple-fault scenario

.

Unused RAM section can be excluded by the testing, under End user responsibility on actual

RAM usage by final Application software .

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 17. RAM_SM_1

RAM_SM_1

Parity on SRAM2

ST

Internal SRAM2 is protected by additional parity bits (1 bit per byte). The parity bits are computed and stored when writing into the SRAM.

Error flag SYSCFG_CFGR2 set

NMI raised

Parity bits are checked during a reading.

Permanent/transient

None

End user must enable the parity check using the option bit SYSCFG_CFGR2, after the boot.

Continuous

Direct test procedure for SRAM2 parity function is not available. SRAM2 parity-related runtime hardware failures leading to disabling such protection fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

DIAG_SM_0: Periodic read-back of hardware diagnostics configuration registers.

RAM_SM_0: Periodic software test for static random access memory (SRAM).

It is advised to initialize by software the whole SRAM2 memory at Application software startup, to avoid getting parity errors when reading non-initialized locations.

As parity protection is restricted to SRAM2, End user is encouraged to store all safety-related data in SRAM2 (if possible), in order to get benefit of such additional hardware-based fast diagnostic.

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 18. RAM_SM_2

RAM_SM_2

Stack hardening for Application software

End user

The stack hardening method is used to enhance Application software robustness to SRAM faults that affect the address decoder. The method is based on source code modification, introducing information redundancy in the stack-passed information to the called functions.

Method contribution is relevant in case the combination between the final Application software structure and the compiler settings requires a significant use of the stack for passing function parameters.

Implementation is the same as method CPU_SM_4.

Refer to CPU_SM_4

Refer to CPU_SM_4

Refer to CPU_SM_4

Refer to CPU_SM_4

Refer to CPU_SM_4

Refer to CPU_SM_4

Refer to CPU_SM_4

Refer to CPU_SM_4

Refer to CPU_SM_4

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Table 19. RAM_SM_3

RAM_SM_3

Information redundancy for safety-related variables in Application software

End user

To address transient faults affecting SRAM controller, it is required to implement information redundancy on the safety-related system variables stored in the RAM.

•

•

•

•

•

The guidelines for the implementation of this method are the following:

The system variables that are safety-related (in the sense that a wrong value due to a failure in reading on the RAM affects the safety functions) are well-identified and documented.

The arithmetic computation or decision based on such variables are executed twice and the two final results are compared.

Safety-related variables are stored and updated in two redundant locations, and comparison is checked before consuming data.

Enumerated fields must use non-trivial values, checked for coherence with the same

frequency as for periodically executed diagnostics (see (1) in

Section 3.6 Hardware and software diagnostics

).

Data vectors stored in SRAM must be protected by a encoding checksum (such as

CRC ).

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

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SM CODE

Recommendations and known limitations

RAM_SM_3

Implementation of this safety method shows a partial overlap with an already foreseen method for Arm ® Cortex ® -M4 (CPU_SM_1); optimizations in implementing both methods are therefore possible.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 20. RAM_SM_4

RAM_SM_4

Control flow monitoring in Application software

End user

In case End user Application software is executed from SRAM, permanent and transient faults affecting the memory (cells and address decoder) can interfere with the program execution.

The implementation of this method is required to address such failures.

For more details on the implementation, refer to CPU_SM_1 description.

Depends on implementation

Depends on implementation. Higher value is fixed by watchdog timeout interval.

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

Needed only in case of Application software execution from SRAM.

CPU_SM_1 correct implementation supersedes this requirement.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 21. RAM_SM_5

RAM_SM_5

Periodic integrity test for Application software in RAM

End user

In case Application software or diagnostic libraries are executed in RAM, it is needed to protect the integrity of the code itself against soft-error corruptions and related code mutations. This method must check the integrity of the stored code by checksum computation techniques, on a periodic basis. For implementation details, refer to similar method

FLASH_SM_0.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Periodic

Self-diagnostic capabilities can be embedded in the software, according to the test implementation design strategy chosen.

CPU_SM_0: Periodic core self-test software

CPU_SM_1: Control flow monitoring in Application software

This method must only be implemented if Application software or diagnostic libraries are executed from RAM.

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 22. RAM_SM_6

RAM_SM_6

Read protection (RDP) and write protection (WRP)

ST

SRAM2 can be protected against illegal reads or erase/write by using these protection features. The combination of these techniques and the related different protection level allows

End user to build an effective access protection policy.

Refer to functional documentation - in some cases a HardFault error is generated.

Refer to functional documentation

Systematic

SRAM2 size may vary depending on part number.

Not required

Continuous

Not applicable

Not required

Hardware random-failure detection capability for SRAM2 access policy is restricted to wellselected marginal failure modes, mainly affecting program counter and SRAM2 interface functions. The associated diagnostic coverage is therefore expected to be irrelevant in the framework of STM32L4 and STM32L4+ Series safety concept.

3.6.4

Embedded Flash memory

Description

Ownership

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 23. FLASH_SM_0

Periodic software test for Flash memory

FLASH_SM_0

End user or ST

Permanent faults affecting the system Flash memory interface address decoder are addressed through a dedicated software test that checks the memory cells contents versus the expected value, using signature-based techniques. According to IEC 61508:2 Table A.5, the effective diagnostic coverage of such techniques depends on the width of the signature in relation to the block length of the information to be protected - therefore the signature computation method is to be carefully selected. Note that the simple signature method

(IEC 61508:7 - A.4.2 Modified checksum) is inadequate as it only achieves a low value of coverage.

The information block does not need to be addressed with this test as it is not used during normal operation (no data nor program fetch).

Depends on implementation

Depends on implementation

Permanent

Flash memory size changes according to the part number.

Memory signatures must be stored in Flash memory as well.

Periodic

Self-diagnostic capabilities can be embedded in the software, according to the test implementation design strategy chosen.

CPU_SM_0: Periodic core self-test software

CPU_SM_1: Control flow monitoring in Application software

This test is expected to have a relevant time duration – test integration must therefore consider the impact on Application software execution.

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Hardware and software diagnostics

Description

Ownership

SM CODE

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

FLASH_SM_0

The use of internal cyclic redundancy check (CRC) module is recommended. In principle direct memory access (DMA)

feature for data transfer can be used.

Unused Flash memory sections can be excluded from testing.

Table 24. FLASH_SM_1

FLASH_SM_1

Control flow monitoring in Application software

End user

Permanent and transient faults affecting the system Flash memory, memory cells and address decoder, can interfere with the access operation by the CPU , leading to wrong data or instruction fetches.

Such failures can be detected by control flow monitoring techniques implemented in

Application software loaded from Flash memory.

For more details on the implementation, refer to description CPU_SM_1.

Depends on implementation

Depends on implementation. Higher value is fixed by watchdog timeout interval.

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

CPU_SM_1 correct implementation supersedes this requirement.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 25. FLASH_SM_2

FLASH_SM_2

Arm ® Cortex ® -M4 HardFault exceptions

ST

Hardware random faults (both permanent and transient) affecting system Flash memory

(memory cells, address decoder) can lead to wrong instruction codes fetches, and eventually to the intervention of the Arm ® Cortex ® -M4 HardFault exceptions. Refer to CPU_SM_3 for detailed description.

Refer to CPU_SM_3

Refer to CPU_SM_3

Permanent/transient

None

Refer to CPU_SM_3

Continuous

Refer to CPU_SM_3

Refer to CPU_SM_3

Refer to CPU_SM_3

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 26. FLASH_SM_3

FLASH_SM_3

Option byte write protection

ST

This safety mechanism prevents unintended writes on the option byte. The use of this method is encouraged to enhance end application robustness for systematic faults.

Write protection exception

Not applicable

None (systematic only)

None

None (always enabled)

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

This method addresses systematic faults in software application and it have zero efficiency in addressing hardware random faults affecting the option byte value during running time. No DC value is therefore associated.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Table 27. FLASH_SM_4

FLASH_SM_4

Static data encapsulation

End user

If static data are stored in Flash memory, encapsulation by a checksum field with encoding capability (such as CRC ) must be implemented.

Checksum validity is checked by Application software before static data consuming.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

None

Table 28. FLASH_SM_5

FLASH_SM_5

Option byte redundancy with load verification

ST

During option byte loading after each power-on reset, the bit-wise complementarity of the option byte and its corresponding complemented option byte is verified. Mismatches are reported as an error.

Option byte error (OPTVERR) generation

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Hardware and software diagnostics

SM CODE

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

FLASH_SM_5

Not applicable

Permanent

None

None (always enabled)

Startup

Not applicable

CPU_SM_0: Periodic core self-test software

None

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Table 29. FLASH_SM_6

FLASH_SM_6

Flash memory unused area filling code

End user

Used Flash memory area must be filled with deterministic data. This way in case that the program counter jumps outside the application program area due to a transient fault affecting

CPU , the system evolves in a deterministic way.

Not applicable

Not applicable

None (fault avoidance)

None

Not applicable

Not applicable

Not applicable

Not applicable

Filling code can be made of NOP instructions, or an illegal code that leads to a HardFault exception raise.

Table 30. FLASH_SM_7

FLASH_SM_7

ECC on Flash memory

ST

•

•

Internal Flash memory is protected by ECC (Error Correction Code) redundancy,implementing a protection feature at double-word (64 bit) level: one-bit fault: correction two-bit fault: detection

•

•

Correction:

ECCC flag (ECC correction) is set in the FLASH_ECCR register.

Interrupt is generated.

•

•

•

Detection:

ECCD flag (ECC detection) is set in the FLASH_ECCR register.

NMI is generated.

The address of the failing double word and its associated bank are saved in the

ADDR_ECC[20:0] and BK_ECC bitfields of the FLASH_ECCR register.

ECC bits are checked during a memory reading.

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Hardware and software diagnostics

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

SM CODE

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

FLASH_SM_7

Permanent/transient

None

None

Continuous

Direct test procedure for ECC efficiency is not available. ECC run-time hardware failures leading to disabling such protection, or leading to wrong corrections, fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

Also refer to the Recommendations and known limitations field.

FLASH_SM_0: Periodic software test for Flash memory

DIAG_SM_0: Periodic read-back of hardware diagnostics configuration registers

CPU_SM_3: Arm ® Cortex ® -M4 HardFault exceptions

According to Flash interface specifications, when the ECCC flag is set, a further two errors detection is not able to generate the NMI. It is therefore highly recommended to clear the

ECCC flag as soon as a correction is operated, to preserve the ECC error detection capability.

Accordingly, the correction interrupt handling and related ECCC flag clear must be considered as integral part of the ECCC protection implementation, and it must be implemented to claim

FLASH_SM_7 diagnostic coverage contribution.

Note: As a result of above exposed limitation, Flash locations occupied by the code implementing correction interrupt management routine are exposed to potential lack of protection against dual errors until the code part where the ECCC flag is cleared. The End users needing to fully address failure modes of those memory locations may execute a periodical CRC check on that Flash section

(see FLASH_SM_0 for general guidance). The frequency of test execution must consider the recommendation of note 1

(1)

.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 31. FLASH_SM_8

FLASH_SM_8

Read protection (RDP), write protection (WRP), and proprietary code readout protection

(PCROP)

ST

Flash memory can be protected against illegal read or erase/write accesses by using these protection features. The combination of these techniques and the related different protection levels allows End user to build an effective access protection policy.

Refer to functional documentation.

In some cases, a HardFault error is generated.

Refer to functional documentation.

Systematic

None

Not required

Continuous

Not applicable

Not required

Hardware random-failure detection capability for Flash memory access policy is restricted to well-selected marginal failure modes, mainly affecting program counter and Flash memory interface functions. The associated diagnostic coverage is therefore expected to be irrelevant in the framework of STM32L4 and STM32L4+ Series safety concept.

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

3.6.5

Firewall (FW)

Table 32. FLASH_SM_9

FLASH_SM_9

Periodic test by software for Flash memory address decoder

End user

Permanent faults affecting the system Flash memory interface address decoder are addressed through a dedicated software test that checks the memory cells contents versus the expected value.

Depends on implementation

Depends on implementation

Permanent

Flash memory size depends on part number.

Not required

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

Overlaps with FLASH_SM_0 implementation are possible.

Description

Ownership

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

3.6.6

Power controller (PWR)

Table 33. FWR_SM_0

FWR_SM_0

Periodic read-back of Firewall configuration registers

End user

This method must be applied to Firewall configuration registers (also unused by End userApplication software ).

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Table 34. VSUP_SM_0

VSUP_SM_0

Periodic read-back of configuration registers

End user

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

VSUP_SM_0

This method must be applied to configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 35. VSUP_SM_1

VSUP_SM_1

Supply voltage internal monitoring (PVD)

ST

The device features an embedded programmable voltage detector (PVD) that monitors the

V

DD

V

DD

power supply and compares it to the V

drops below the V

PVD

threshold. An interrupt can be generated when

PVD

threshold or when V

DD

is higher than the V

PVD

threshold.

Interrupt event generation

Depends on threshold programming. Refer to functional documentation.

Permanent/transient

None

Protection enable by the PVDE bit and the threshold setting in the Power control register

(PWR_CR)

Continuous

Direct test procedure for PVD efficiency is not available. PVD run-time hardware failures leading to disabling such protection fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

DIAG_SM_0: Periodic read-back of hardware diagnostics configuration registers

Internal monitoring PVD has limited capability to address failures affecting STM32L4 and

STM32L4+ Series internal voltage regulator. Refer to [1] for details.

Internal monitoring PVD has limited capability to address failures affecting the internal voltage regulator. Refer to Device FMEA for details.

SM CODE

Description

Ownership

Detailed implementation

Table 36. VSUP_SM_2

VSUP_SM_2

Independent watchdog

ST

Failures in the power supplies for digital logic (core or peripherals) may lead to alteration of

Application software timing, which can be detected by IWDG as safety mechanism introduced to monitor Application software control flow. Refer to CPU_SM_1 and CPU_SM_6 for further information.

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UM2305

Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

VSUP_SM_2

Reset signal generation

Depends on implementation (watchdog timeout interval)

Permanent

None

IWDG activation. It is recommended to use Hardware watchdog in Option byte settings (IWDG is automatically enabled after reset).

Continuous

Refer to CPU_SM_6.

CPU_SM_1: Control flow monitoring in Application software

In specific part numbers, IWDG can be fed by a power supply independent from the one used for CPU core and main peripherals. Such diversity helps to increase the protection guaranteed by IWDG from main power supply anomalies.

The adoption of an external watchdog (refer to CPU_SM_5) adds further diversity.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 37. VSUP_SM_3

VSUP_SM_3

Internal temperature sensor check

End user

The internal temperature sensor must be periodically tested in order to detect abnormal increase of the die temperature – hardware faults in supply voltage system may cause excessive power consumption and consequent temperature rise.

Depends on implementation

Depends on implementation

Permanent

None

None

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

This method also mitigates the probability of common-cause failure due to excessive temperature, affecting Device .

Refer to the Device datasheet to set the threshold temperature.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Table 38. VSUP_SM_4

VSUP_SM_4

Peripheral voltage monitoring (PVM)

ST

The device features an embedded programmable voltage detector (PVM) that monitors and compares the three independent power supplies to thresholds. An interrupt can be generated when an independent power supply drops below the threshold or when it is higher than the threshold.

Interrupt generation on specific EXTI lines

Depends on threshold programming. Refer to functional documentation.

Permanent/transient

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Hardware and software diagnostics

SM CODE

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

VSUP_SM_4

None

Protection enable and threshold programming on selected power rails in Power control register

Continuous

Not applicable

CPU_SM_5: External watchdog

This method can be used in conjunction with VSUP_SM_0 to implement a complete supervision of VDD value

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 39. VSUP_SM_5

VSUP_SM_5

System-level power supply management

End user

•

•

•

This method is implemented at system level in order to guarantee the stability of power supply value over time. It can include a combination of different overlapped solutions, some listed here below (but not limited to): additional voltage monitoring by external components passive electronics devices able to mitigate overvoltage specific design of power regulator in order to avoid power supply disturbance in presence of a single failure

Depends on implementation

Fault avoidance

None

None

Depends on implementation

Continuous

Not applicable

Not applicable

Usually, this method is already required/implemented to guarantee the stability of each component of the final electronic board.

3.6.7

Reset and clock controller (RCC)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Table 40. CLK_SM_0

CLK_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to configuration registers for clock and reset system (refer to

RCC register map).

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

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Hardware and software diagnostics

SM CODE

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

CLK_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 41. CLK_SM_1

CLK_SM_1

Clock security system (CSS)

ST

•

•

•

The clock security system (CSS) detects the loss of high-speed external (HSE) oscillator clock activity and executes the corresponding recovery action, such as: switch-off HSE commutation on the HIS generation of related NMI

NMI

Depends on implementation (clock frequency value)

Permanent/transient

None

CSS protection must be enabled through Clock interrupt register (RCC_CIR) after boot.

Continuous

CLK_SM_0: Periodic read-back of configuration registers

CPU_SM_5: External watchdog

It is recommended to carefully read reference manual instruction on NMI generation, in order to correctly managing the faulty situation by Application software .

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Table 42. CLK_SM_2

CLK_SM_2

Independent watchdog

ST

The independent watchdog IWDG is able to detect failures in internal main MCU clock (lower frequency).

Reset signal generation

Depends on implementation (watchdog timeout interval)

Permanent

None

IWDG activation. It is recommended to use the hardware watchdog in Option byte settings

(IWDG is automatically enabled after reset).

Continuous

Refer to CPU_SM_6.

CPU_SM_1: Control flow monitoring in Application software

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Hardware and software diagnostics

SM CODE

Recommendations and known limitations

CLK_SM_2

The adoption of an external watchdog (refer to CPU_SM_5) adds further diversity.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 43. CLK_SM_3

CLK_SM_3

Internal clock cross-measurement

End user

This method is implemented using TIM15/TIM16/TIM17 capabilities to be fed by the 32 KHz

RTC clock or an external clock source (if available). TIM15/TIM16/TIM17 counter progresses are compared with another counter (fed by internal clock). Abnormal values of oscillator frequency can therefore be detected.

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

Periodic

Not applicable

CPU_SM_1: Control flow monitoring in Application software

CPU_SM_5: External watchdog

Efficiency versus transient faults is negligible. It provides only medium efficiency in permanent clock-related failure mode coverage.

3.6.8

General-purpose input/output (GPIO)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 44. GPIO_SM_0

GPIO_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to GPIO configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

GPIO availability can differ according to part number

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 45. GPIO_SM_1

GPIO_SM_1

1oo2 for input GPIO lines

End user

This method addresses GPIO lines used as inputs. Implementation is done by connecting the external safety-related signal to two independent GPIO lines. Comparison between the two GPIO values is executed by Application software each time the signal is used to affect

Application software behavior.

Depends on implementation

Depends on implementation

Permanent/transient

None

Permanent/transient

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

•

•

•

To reduce the potential impact of common cause failure, it is recommended to use GPIO lines: belonging to different I/O ports (for instance port A and B) with different bit port number (for instance PA1 and PB5) mapped to non-adjacent pins on the device package

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 46. GPIO_SM_2

GPIO_SM_2

Loopback scheme for output GPIO lines

End user

This method addresses GPIO lines used as outputs. Implementation is done by a loopback scheme, connecting the output to a different GPIO line programmed as input and by using the input line to check the expected value on output port. Comparison is executed by Application software periodically and each time output is updated.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

•

•

•

To reduce the potential impact of common cause failure, it is recommended to use GPIO lines: belonging to different I/O ports (for instance port A and B) with different bit port number (for instance PA1 and PB5) mapped to non-adjacent pins on the device package

Efficiency versus transient failures is linked to final application characteristics. We define as

Tm the minimum duration of GPIO output wrong signal permanence required to violate the related safety function(s). Efficiency is maximized when execution test frequency is higher than 1/Tm.

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 47. GPIO_SM_3

GPIO_SM_3

GPIO port configuration lock register

ST

This safety mechanism prevents configuration changes for GPIO registers; it addresses therefore systematic faults in software application.

The use of this method is encouraged to enhance the end-application robustness for systematic faults.

Depends on implementation

Depends on implementation

None (Systematic only)

None

Application software must apply a correct write sequence to LCKK bit (bit 16 of the

GPIOx_LCKR register) after writing the final GPIO configuration.

Continuous

Not applicable

Not required

This method does not address transient faults (soft errors) that can possibly cause bit-flips on

GPIO registers at running time.

3.6.9

Debug system or peripheral control

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 48. DBG_SM_0

DBG_SM_0

Watchdog protection

ST

The debug unintentional activation due to hardware random fault results in the massive disturbance of CPU operations, leading to an intervention of the independent watchdog or, alternatively, the other system watchdog WWDG or the external one (CPU_SM_5).

Reset signal generation

Depends on implementation (watchdog timeout interval).

Permanent/transient

None

Depends on implementation

Continuous

Refer to CPU_SM_6.

CPU_SM_1: Control flow monitoring in Application software

None

SM CODE

Description

Ownership

Table 49. LOCK_SM_0

LOCK_SM_0

Lock mechanism for configuration options

ST

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

LOCK_SM_0

The STM32L4 and STM32L4+ Series devices feature spread protection to prevent unintended configuration changes for some peripherals and system registers (for example PVD_LOCK, timers); the spread protection detects systematic faults in software application. The use of this method is encouraged to enhance the end application robustness to systematic faults.

Not generated (when locked, register overwrites are simply ignored).

Not applicable

None (systematic only)

None

Depends on implementation

Continuous

Not applicable

Not required

No DC associated because this test addresses systematic faults.

3.6.10

System configuration controller (SYSCFG)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 50. SYSCFG_SM_0

SYSCFG_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to system configuration controller configuration registers.

This method is strongly recommended to protect registers related to hardware diagnostics activation and error reporting chain related features.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

This method is mainly overlapped by several other configuration register read-backs required for other MCU peripherals. It is reported here for the sake of completeness.

SM CODE

Description

Ownership

Detailed implementation

Table 51. DIAG_SM_0

DIAG_SM_0

Periodic read-back of hardware diagnostics configuration registers

End user

•

In STM32L4 and STM32L4+ Series, several hardware-based safety mechanisms are available (those with the Ownership field set to ST). This method must be applied to any configuration register related to diagnostic measure operations, including error reporting. End user must therefore individuate configuration registers related to: hardware diagnostic enable

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Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

•

Refer to NVIC_SM_0

DIAG_SM_0 interrupt/NMI enable (if used for diagnostic error management)

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

3.6.11

Direct memory access controller (DMA/ DMA2D/ DMAMUX))

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 52. DMA_SM_0

DMA_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to DMA configuration register and channel address register.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Table 53. DMA_SM_1

DMA_SM_1

Information redundancy on data packet transferred via DMA

End user

This method is implemented by adding, to data packets transferred by DMA , a redundancy check (such as CRC check or similar one) with encoding capability. Full data packet redundancy would be an overkill.

The checksum encoding capability must be robust enough to guarantee at least 90% probability of detection for a single bit flip in the data packet.

Consistency of data packet must be checked by Application software before consuming data.

Depends on implementation

Depends on implementation

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Hardware and software diagnostics

SM CODE

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

DMA_SM_1

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

To give an example about checksum encoding capability, using just a bit-by-bit addition is inappropriate.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 54. DMA_SM_2

DMA_SM_2

Information redundancy by including sender or receiver identifier on data packet transferred via DMA

End user

This method helps to identify inside the MCU the source and the originator of the message exchanged by DMA .

•

•

•

Implementation is realized by adding an additional field to protected message, with a coding convention for message type identification fixed at Device level. Guidelines for the identification fields are:

Identification field value must be different for each possible couple of sender or receiver on DMA transactions.

Values chosen must be enumerated and non-trivial.

Coherence between the identification field value and the message type is checked by

Application software before consuming data.

This method, when implemented in combination with DMA_SM_4, makes available a kind of virtual channel between source and destinations entities.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

None

SM CODE

Description

Ownership

Detailed implementation

Table 55. DMA_SM_3

DMA_SM_3

Periodic software test for DMA

End user

•

This method requires the periodical testing of the DMA basic functionality, implemented through a deterministic transfer of a data packet from one source to another (for example from memory to memory) and the checking of the correct transfer of the message on the target. Data packets are composed by non-trivial patterns (avoid the use of 0x0000, 0xFFFF values) and organized in order to allow the detection during the check of the following failures: incomplete packed transfer

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Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

•

•

DMA_SM_3 errors in single transferred word wrong order in packed transmitted data

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

None

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 56. DMA_SM_4

DMA_SM_4

DMA transaction awareness

End user

DMA transactions are non-deterministic by nature, because typically driven by external events like communication messages reception. Anyway, well-designed safety systems should keep much control as possible of events – refer for instance to IEC61508:3 Table 2 item 13 requirements for software architecture.

This method is based on system knowledge of frequency and type of expected DMA transaction. For instance, an externally connected sensor supposed to send periodically some messages to a STM32 peripheral. Monitoring DMA transaction by a dedicated state machine allows to detect missing or unexpected DMA activities.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

Because DMA transaction termination is often linked to an interrupt generation, implementation of this method can be merged with the safety mechanism NVIC_SM_1:

Expected and unexpected interrupt check.

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Hardware and software diagnostics

3.6.12

Chrom-Art Accelerator controller (DMA2D)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 57. DMA2D_SM_0

DMA2D_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to DMA2D configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 58. DMA2D_SM_1

DMA2D_SM_1

Periodic software test for DMA2D functions

End user

This method requires the periodical testing of the DMA2D basic functionality, implemented through a deterministic transfer and processing of a set of test images from memory to memory and the checking of the correct execution (output image must be generated as per specifications). Output image correctness can be performed by fast methods like CRC fingerprint computation.

•

•

•

•

•

Test definition must be able to cover following DMA2D basic functions: full image copy image filling with a specific color copy of part of the image pixel format conversion blending of two different images

Achieved diagnostic coverage on the module depends on the quantity and variance of tests performed.

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

Periodicity

Not applicable

CPU_SM_0: Periodic core self-test software

In principle, DMA2D basic functions not used in the safety application can be excluded from this test suite implementation.

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UM2305

Hardware and software diagnostics

Description

Ownership

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Note:

3.6.13

SM CODE

Detailed implementation

Table 59. DMA2D_SM_2

DMA2D_SM_2

DMA processing and interrupt awareness

End user

This method is based on system knowledge of frequency and type of DMA2D transaction expected. In general, image processing systems are based on a deterministic timing for image framing arrival and processing.

Therefore, this method requires to monitor the expected execution of image processing and, in case interrupt generation is used, their correct timing and sequence.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

Implementation of this method can be merged with the safety mechanism NVIC_SM_1:

Expected and unexpected interrupt check

If image processing performed by DMA2D is used for the implementation of a safety function, system level considerations (as consistency checks on objects recognition results) may guarantee additional diagnostic coverage. Similarly, system level data redundancy schemes (as for instance algorithms based on processing for sequences of multiple image frames) may result in a relevant de rating for transient failure rate.

Chrom-GRC™ (GFXMMU)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 60. GFX_SM_0

GFX_SM_0

Periodic read-back of GFXMMU configuration registers

End user

This method must be applied to DSI Host configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

UM2305 - Rev 10 page 39/110

UM2305

Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 61. GFX_SM_1

GFX_SM_1

Periodic LUT read-back

End user

This test is implemented by executing a periodical read-back of the LUT programmed memory cells versus their expected value. LUT reference values are usually stored in the Flash memory, allowing the implementation of the check feature.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

Alternative solutions (such as reading LUT values and computing CRC seed to be checked versus its expected value) are allowed. End user must carefully check the MMU performance impact loss due to read operations related to this method.

3.6.14

Extended interrupt and events controller (EXTI)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Table 62. NVIC_SM_0

NVIC_SM_0

Periodic read-back of configuration registers

End user

This test is implemented by executing a periodic check of the configuration registers for a system peripheral against its expected value. Expected values are previously stored in

RAM and adequately updated after each configuration change. The method mainly addresses transient faults affecting the configuration registers, by detecting bit flips in the registers contents. It addresses also permanent faults on registers because it is executed at least once per PST

(or another timing constraint; refer to (1)

diagnostics ) after an update of the peripheral.

in

Section 3.6 Hardware and software

Method must be implemented to any configuration register whose contents are able to interfere with NVIC or EXTI behavior in case of incorrect settings. Check includes NVIC vector table.

According to the state-of-the-art automotive safety standard ISO26262, this method can achieve high levels of

diagnostic coverage (DC)

(refer to ISO26262-5:2018, Table D.4).

•

•

•

An alternative valid implementation requiring less space in SRAM can be realized on the basis of signature concept:

Peripheral registers to be checked are read in a row, computing a of hardware CRC is encouraged).

CRC checksum (use

Obtained signature is compared with the golden value (computed in the same way after each register update, and stored in SRAM).

Coherence between signatures is checked by Application software – signature mismatch is considered as failure detection.

Depends on implementation

Depends on implementation

Permanent/transient

None

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Hardware and software diagnostics

SM CODE

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

NVIC_SM_0

Values of configuration registers must be read after the boot before executing the first check.

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

This method addresses only failures affecting configuration registers, and not peripheral core logic or external interface.

Attention must be paid to registers containing mixed combination of configuration and status bits. Mask must be used before saving register contents affecting signature, and related checks done, to avoid false positive detections.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 63. NVIC_SM_1

NVIC_SM_1

Expected and unexpected interrupt check

End user

According to IEC 61508:2 Table A.1 recommendations, a diagnostic measure for continuous, absence or cross-over of interrupt must be implemented. The method of expected and unexpected interrupt check is implemented at Application software level.

•

•

•

•

•

The guidelines for the implementation of the method are the following:

The interrupts implemented on the MCU are well documented, also reporting, when possible, the expected frequency of each request (for example, the interrupts related to

ADC conversion completion that come on a regular basis).

Individual counters are maintained for each interrupt request served, in order to detect in a given time frame the cases of a) no interrupt at all b) too many interrupt requests

(“babbling idiot” interrupt source). The control of the time frame duration must be regulated according to the individual interrupt expected frequency.

Interrupt vectors related to unused interrupt source point to a default handler that reports, in case of triggering, a faulty condition (unexpected interrupt).

In case an interrupt service routine is shared between different sources, a plausibility check on the caller identity is implemented.

Interrupt requests related to non-safety-related peripherals are handled with the same method here described, despite their originator safety classification.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

In order to decrease the complexity of method implementation, it is suggested to use polling technique (when possible) instead of interrupt for end system implementation.

3.6.15

Cyclic redundancy-check calculation unit (CRC)

Table 64. CRC_SM_0

SM CODE

Description CRC self-coverage

CRC_SM_0

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Hardware and software diagnostics

SM CODE

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

CRC_SM_0

ST

The CRC algorithm implemented in this module (CRC-32 Ethernet polynomial: 0x4C11DB7) offers excellent features in terms of error detection in the message. Therefore permanent and transient faults affecting CRC computations are easily detected by any operations using the module to recompute an expected signature.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

None

3.6.16

Flexible static memory controller (FSMC)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 65. FSMC_SM_0

FSMC_SM_0

Control flow monitoring in Application software

End user

If FSMC is used to connect an external memory containing software code to be executed by the CPU, permanent and transient faults affecting the FSMC memory controller are able to interfere with the access operation by the CPU, leading to wrong data or instruction fetches. A strong control flow mechanism linked to a system watchdog is able to detect such failures, in case they interfere with the expected flow of Application software .

The implementation of this method is identical to the one reported for CPU_SM_1, refer there for details.

Depends on implementation

Depends on implementation. Higher value is fixed by watchdog timeout interval.

Permanent/transient

FSMC interface is available only on selected part numbers.

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

This mechanism must only be used if FSMC external memory is used to store executable programs.

SM CODE

Description

Ownership

Table 66. FSMC_SM_1

FSMC_SM_1

Information redundancy on external memory connected to FSMC

End user

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device

Periodicity

configuration

Initialization

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

FSMC_SM_1

•

•

If FSMC interface is used to connect an external memory where safety-relevant data are stored, information redundancy techniques for stored data are able to address faults affecting the FSMC interface. The possible techniques are: using redundant copies of safety-relevant data and performing coherence check before consuming organizing data in arrays and computing the checksum field to check before use

Depends on implementation

Depends on implementation

Permanent/transient

FSMC interface is available only on selected part numbers.

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

This mechanism must be used just if FSMC external memory is used to store safety-related data.

This safety mechanism can overlap with information redundancy techniques implemented at system level to address failure of physical device connected to FSMC port.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SM CODE

Description

Ownership

Detailed implementation

Table 67. FSMC_SM_2

FSMC_SM_2

Periodic read-back of FSMC configuration registers

End user

This method must be applied to FSMC configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

FSMC interface is available only on selected part numbers.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Table 68. FSMC_SM_3

FSMC_SM_3

ECC engine on NAND interface in FSMC module

ST

The FMC NAND Card controller includes two error correction code computation hardware blocks, one per memory bank. They reduce the host CPU workload when processing the ECC by software.

ECC mechanism protects data integrity on the external memory connected to NAND port.

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Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

3.6.17

Note:

FSMC_SM_3

Refer to functional documentation

ECC bits are checked during memory reading.

Permanent/transient

FSMC interface is available only on selected part numbers.

None

Continuous

Not applicable

FSMC_SM_2: Periodic read-back of FSMC configuration registers

This method has negligible efficiency in detecting hardware random failures affecting the

FSMC interface. It can be part of End user safety concept because addressing memories outside STM32L4 and STM32L4+ Series MCU.

Quad-SPI interface and Octo-SPI interface (QUADSPI/OCTOSPI)

For this document's scope, Octo-SPI interface includes the OCTOSPIM.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 69. QSPI_SM_0

QSPI_SM_0

Periodic read-back of OCTOSPI configuration registers

End user

This method must be applied to OCTOSPI configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Table 70. QSPI_SM_1

QSPI_SM_1

Protocol error signals including hardware CRC

ST

OCTOSPI communication module embeds protocol error checks (like overrun, underrun, timeout etc.), conceived to detect communication-related abnormal conditions. These mechanisms are able anyway to detect a percentage of hardware random failures affecting the module itself.

Error flag raise and optional interrupt event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

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Hardware and software diagnostics

SM CODE

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

QSPI_SM_1

Permanent/transient

None

Depends on implementation

Continuous

Direct test procedure for CRC efficiency is not available. CRC run-time hardware failures leading to disabling such protection fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

QSPI_SM_2: Information redundancy techniques on messages

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 71. QSPI_SM_2

QSPI_SM_2

Information redundancy techniques on messages

End user

This method is implemented adding to data packets (not commands) transferred by OCTOSPI interface a redundancy check (like a CRC check, or similar one) with encoding capability. The checksum encoding capability must be robust enough to guarantee at least 90% probability of detection for a single bit flip in the data packet.

Consistency of data packet must be checked by Application software before consuming data.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

To give an example on checksum encoding capability, using just a bit-by-bit addition is unappropriated.

This safety mechanism can overlap with information redundancy techniques implemented at system level to address failure of physical device connected to OCTOSPI port.

3.6.18

Analog-to-digital converter (ADC)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Table 72. ADC_SM_0

ADC_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to ADC configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

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Hardware and software diagnostics

SM CODE

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

ADC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 73. ADC_SM_1

ADC_SM_1

Multiple acquisition by Application software

End user

This method implements a timing information redundancy by executing multiple acquisitions on the same input signal. Multiple acquisition data are then combined by a filter algorithm to determine the signal correct value.

Depends on implementation

Depends on implementation

Depends on implementation

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

It is highly probable that this recommendation is satisfied by design by End userApplication software . Usage of multiple acquisitions followed by average operations is a common technique in industrial applications exposed to electromagnetic interference on sensor lines.

Table 74. ADC_SM_2

ADC_SM_2

Range check by Application software

End user

•

•

•

The guidelines for the implementation of the method are the following:

The expected range of the data to be acquired are investigated and adequately documented. Note that in a well-designed application it is improbable that during normal operation an input signal has a very near or over the upper and lower rail limit

(saturation in signal acquisition).

If Application software is aware of the state of the system, this information is to be used in the range check implementation. For example, if the ADC value is the measurement of a current through a power load, reading an abnormal value such as a current flowing in opposite direction versus the load supply may indicate a fault in the acquisition module.

As the ADC module is shared between different possible external sources, the combination of plausibility checks on the different signals acquired can help to cover the whole input range in a very efficient way.

Depends on implementation

Depends on implementation

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Hardware and software diagnostics

SM CODE

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

ADC_SM_2

Depends on implementation

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

The implementation and the related diagnostic efficiency of this safety mechanism are strongly application-dependent.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 75. ADC_SM_3

ADC_SM_3

Periodic software test for ADC

End user

•

•

The method is implemented acquiring multiple signals and comparing the read value with the expected one, supposed to be know. Method can be implemented with different level of complexity:

Basic complexity: acquisition and check of upper or lower rails (VDD or VSS) and internal reference voltage

High complexity: in addition to basic complexity tests, acquisition of a DAC output connected to ADC input and checking all voltage excursion and linearity

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

Combination of two methods with different complexity can be used to better optimize test frequency in high-demand safety functions.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Table 76. ADC_SM_4

ADC_SM_4

1oo2 scheme for ADC inputs

End user

This safety mechanism is implemented using two different SAR ADC channels belonging to separate ADC modules to acquire the same input signal. Application software checks the coherence between the two readings.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

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Hardware and software diagnostics

SM CODE

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

ADC_SM_4

Not applicable

ADC_SM_0: Periodic read-back of configuration registers

This method can be used in conjunction with ADC_SM_0 / ADC_SM_2 / ADC_SM_3 to achieve highest level of ADC module diagnostic coverage.

3.6.19

Digital-to-analog converter (DAC)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 77. DAC_SM_0

DAC_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to DAC configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 78. DAC_SM_1

DAC_SM_1

DAC output loopback on ADC channel

End user

Route the active DAC output to one ADC channel, and check the output current value against the expected one.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous or on demand

Not applicable

CPU_SM_0: Periodic core self-test software

Efficiency versus transient failures is linked to final application characteristics. We define as

Tm the minimum duration of DAC wrong signal permanence required to violate the related safety function(s). Efficiency is maximized when execution test frequency is higher than 1/Tm.

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Hardware and software diagnostics

3.6.20

Voltage reference buffer (VREFBUF)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 79. VREF_SM_0

VREF_SM_0

Periodic read-back of VREFBUF system configuration registers

End user

This method must be applied to VREFBUF configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

CPU_SM_0: Periodic core self-test software

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 80. VREF_SM_1

VREF_SM_1

VREF cross-check by ADC reading

End user

This method is based on ADC acquisition for VREF generated signal, to crosscheck with the expected value.

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

Overlaps with ADC_SM_3 are possible.

3.6.21

Comparator (COMP)

SM CODE

Description

Ownership

Detailed implementation

Table 81. COMP_SM_0

COMP_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to COMP configuration registers.

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Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

COMP_SM_0

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 82. COMP_SM_1

COMP_SM_1

1oo2 scheme for comparator

End user

This safety mechanism is implemented using the two internal comparators to take the same decision. It requires that the comparator voting is handled accordingly.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

This method is not compatible with window comparator feature.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Table 83. COMP_SM_2

COMP_SM_2

Plausibility check on inputs

End user

This method is used to redundantly acquire on dedicated ADC channels the analog inputs that are subjected to comparator function, and to periodically check the coherence of the comparator output on the measured values.

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

Periodic

Not applicable

UM2305 - Rev 10 page 50/110

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Hardware and software diagnostics

SM CODE

Multiple-fault protection

Recommendations and known limitations

COMP_SM_2

CPU_SM_0: Periodic core self-test software

None

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 84. COMP_SM_3

COMP_SM_3

Multiple acquisition by Application software

End user

This method requires that Application software takes a decision not on the basis of a comparator single-shot transition, but after multiple events or after the permanence of comparator trigger conditions for a certain amount of time.

Depends on implementation

Depends on implementation

Transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

It is highly probable that this recommendation is satisfied by design on End user application

- multiple acquisition is a common technique in industrial applications facing electromagnetic interference on sensor lines.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 85. COMP_SM_4

COMP_SM_4

Comparator lock mechanism

ST

This safety mechanism prevents configuration changes for comparator control and status registers; it addresses therefore systematic faults in the software application.

Not applicable

Not applicable

None (Fault avoidance)

None

Lock protection must be enabled through the COMPxLOCK bits of the COMP_CSR register.

Continuous

Not applicable

Not applicable

This method does not addresses comparator configuration changes due to soft errors.

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Hardware and software diagnostics

3.6.22

Operational amplifiers (OPAMP)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Note:

3.6.23

Table 86. AMP_SM_0

AMP_SM_0

Periodic read-back of OPAMP configuration registers

End user

This method must be applied to OPAMP configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Because OPAMP modules are expected to be used in signal conditioning/amplification, their use in safetyrelated functions lead to an application level scenario. End user is therefore responsible for the mitigation of failure modes affecting the analog section of used OPAMP module(s).

Digital filter for sigma delta modulators (DFSDM)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 87. DFS_SM_0

DFS_SM_0

Periodic read-back of DFSDM configuration registers

End user

This method must be applied to DFSDM configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

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UM2305

Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 88. DFS_SM_1

DFS_SM_1

Multiple acquisition by Application software

End user

This method implements a timing information redundancy by executing multiple acquisitions on the same input signal. Multiple acquisition data are then combined by a filter algorithm to determine the signal correct value.

Depends on implementation

Depends on implementation

Transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

It is highly probable that this recommendation is satisfied by design by End userApplication software . Usage of multiple acquisitions followed by average operations is a common technique in industrial applications where it is needed to survive with spurious EMI disturbs on sensor lines.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 89. DFS_SM_2

DFS_SM_2

Range check by Application software

End user

This method is implemented as described in ADC_SM_2: Range check by Application software .

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Not applicable

Not applicable

CPU_SM_0: Periodic core self-test software

The implementation of this safety mechanism is strongly application-dependent.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Table 90. DFS_SM_3

DFS_SM_3

1oo2 scheme for DFSM inputs

End user

This safety mechanism is implemented using two different DFSM modules to acquire the same input signal. Application software checks the coherence between the two readings.

Depends on implementation

Depends on implementation

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Hardware and software diagnostics

SM CODE

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

DFS_SM_3

Permanent/transient

None

Depends on implementation

On demand

Not applicable

DFS_SM_0: Periodic read-back of DFSDM configuration registers

This method can be used in conjunction with DFS_SM_0 to achieve highest level of DFSM module diagnostic coverage (in alternative to DFS_SM_1 and DFS_SM_2).

3.6.24

Digital camera interface (DCMI)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 91. DCMI_SM_0

DCMI_SM_0

Periodic read-back of DCMI configuration registers

End user

This method must be applied to DCMI configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

DCMI interface is available only on selected part numbers.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Table 92. DCMI_SM_1

DCMI_SM_1

DCMI video input data synchronization

ST

According to the nature of video data stream received, DCMI module implements synchronization controls, from the simplest one (hardware synchronization) to the most complex (e.g. embedded data synchronization mode). DCMI internal failures leading to the incapability of correcting synchronizing the data stream can be therefore detected.

No explicit error signal/message generation is provided (*).

Depends on implementation

Permanent

DCMI interface is available only on selected part numbers.

Depends on implementation

Continuous

Not applicable

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Hardware and software diagnostics

SM CODE

Multiple-fault protection

Recommendations and known limitations

3.6.25

DCMI_SM_1

DCMI_SM_0: Periodic read-back of DCMI configuration registers

(*) For its nature, the detection of an actual hardware failure by this safety mechanism can be confused with functional-related scenarios (e.g. camera device disconnected or powered-off).

It is responsibility of Application software to discriminate, as far as it is technically possible, among different events.

LCD-TFT display controller (LTDC)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 93. LCD_SM_0

LCD_SM_0

Periodic read-back of LTDC configuration registers and buffer memory

End user

This method must be applied to LTDC configuration registers and to the buffer memory.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 94. LCD_SM_1

LCD_SM_1

LTDC acquisition by ADC channel

End user

Correct generation of LTDC driving signals is checked by ADC reading versus expected values

Depends on implementation

Depends on implementation

Permanent

None

None

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

This method is conceived to mainly detect permanent failures affecting analog parts and therefore the execution on periodic way is acceptable. Diagnostic coverage achievable depends on the quantity of LTDC signals checked

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Note:

3.6.26

The above-described safety mechanism addresses the LTDC interface included in STM32 MCUs. Because actual capability of correct image generation on LTDC is not addressed by this safety mechanism, in case such feature is considered safety relevant, End user is warned to evaluate the adoption of adequate system-level measures.

DSI Host (DSI)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 95. DSI_SM_0

DSI_SM_0

Periodic read-back of DSI configuration registers

End user

This method must be applied to DSI configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 96. DSI_SM_1

DSI_SM_1

Protocol error signals and information redundancy including hardware checksums

ST

DSI communication/command protocol is based on a packet handling concept, including

(where applicable) ECC and checksum capabilities. This mechanism, mainly implemented to manage on field communication disturbance, is able to achieve a relevant diagnostic coverage on several DSI module failure modes.

Error conditions are reported by flag bits in related registers.

Depends on peripheral configuration and the type of violation detected. Refer to functional documentation.

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

DSI_SM_0: Periodic read-back of DSI configuration registers

None

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Note: The above-described safety mechanisms addresses the DSI interface included in STM32 MCUs, including PHY.

Because actual capability of correct physical signal generation to drive the connected monitor is not addressed by these safety mechanisms, in case such feature is considered safety relevant, End user is warned to evaluate the adoption of adequate system-level measures.

Touch sensing controller (TSC) 3.6.27

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 97. TSC_SM_0

TSC_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to TSC configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 98. TSC_SM_1

TSC_SM_1

Multiple acquisition by Application software

End user

This method implements a timing information redundancy by executing multiple acquisitions on TSC input data. Multiple acquisition data are then used to determine the acquisition correct state.

This method overlaps on the native features of the TSC module of counting events to ensure a stable acquisition against external noise.

Depends on implementation

Depends on implementation

Transient

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

None

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SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 99. TSC_SM_2

TSC_SM_2

Application-level detection of permanent failures of TSC acquisition

End user

This method must detect TSC module permanent failure leading to wrong or missing acquisition of touch sensing events.

Depends on implementation

Depends on implementation

Permanent

None

Depends on implementation

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

Due to the strictly application-dependent nature of this solution, no detailed guidelines for its implementation are given here. As a solution fully based on microcontroller resources is impossible, it is necessary to leverage on the contribution from other components of the final system.

3.6.28

HASH processor (HASH)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 100. HASH_SM_0

HASH_SM_0

Periodic read-back of HASH configuration registers

End user

This method must be applied to HASH configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

HASH module available only on specific part numbers

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Table 101. HASH_SM_1

HASH processing collateral detection

ST

HASH_SM_1

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SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

HASH_SM_1

Message digest computation performed by HASH module is composed by several data manipulations and checks. A major part of the hardware random failures affecting HASH module leads to algorithm violations/errors, and so to decoding errors on the receiver side.

Several error condition can happens, check functional documentation.

Depends on implementation

Permanent/transient

HASH module available only on specific part numbers

Depends on implementation

Continuous

Direct test procedure for HASH efficiency is not available. HASH run-time hardware failures leading to disabling related collateral protection fall into multiple-fault scenario, from

IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection.

HASH_SM_0: Periodic read-back of HASH configuration registersCPU_SM_0: Periodic core self-test software

This detection capability can be used to implement software-based tests (by processing a predefined message and further checking the expected results) which can be executed periodically to early detect HASH failures before its use by application software.

Note:

3.6.29

Hardware random failures consequences on potential security features violations are not analyzed in this manual.

True random number generator (RNG)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 102. RNG_SM_0

RNG_SM_0

Periodic read-back of RNG configuration register

End user

This method must be applied to RNG configuration register RNG_CR.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

RNG module available only on specific part numbers

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Table 103. RNG_SM_1

SM CODE

Description

Ownership

RNG module entropy on-line tests

ST and End user

RNG_SM_1

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SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

RNG_SM_1

RNG module include an internal diagnostic for the analog source entropy that can be used to detect failures on the module itself. Furthermore, the required test on generated random number difference between the previous one (as required by FIPS PUB 140-2) can be exploited as well.

•

•

Implementation:

Check for RNG error conditions.

Check the difference between generated random number and the previous one.

CEIS, SEIS error bits of the RNG status register (RNG_SR)

Application software error for FIPS PUB 140-2 test fail

Depends on implementation

Permanent/transient

RNG module available only on specific part numbers

Permanent/transient

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

None

3.6.30

Advanced encryption standard hardware accelerator (AES)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 104. AES_SM_0

AES_SM_0

Periodic read-back of AES configuration registers

End user

This method must be applied to AES configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

AES module available only on specific part numbers

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Table 105. AES_SM_1

Encryption/decryption collateral detection

ST

AES_SM_1

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SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device

Periodicity

configuration

Initialization

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

AES_SM_1

Encryption and decryption operations performed by AES module are composed by several data manipulations and checks, with different level of complexity according to the selected chaining algorithm. A major part of the hardware random failures affecting AES module leads to algorithm violations/errors. Leading to decoding errors on the receiver side.

Several error conditions can happen, check functional documentation.

Dependency on Device configuration

Permanent/transient

AES module available only on specific part numbers

Dependency on Device configuration

Continuous

Direct test procedure for AES efficiency is not available. AES run-time hardware failures leading to disabling such protection fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

AES_SM_2: Information redundancy techniques on messages, including end-to-end protection

This detection capability can be used to implement software-based tests (by processing a predefined message and further checking the expected results) which can be executed periodically to early detect AES failures before its use by application software.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 106. AES_SM_2

AES_SM_2

Information redundancy techniques on messages, including end-to-end protection

End user

This method aim to protect the communication between a peripheral and his external counterpart. It is used in AES local safety concept to address failures not detected by the encryption/decryption features.

Refer to UART_SM_3 description for detailed information.

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

AES module available only on specific part numbers

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Important note: it is assumed that the remote counterpart has an equivalent capability of performing the checks described.

Refer to UART_SM_3 for further notice.

Important:

Hardware random failure consequences on potential violations of Device security feature are not detailed in this manual.

3.6.31

Advanced, general, and low-power timer (TIM1/2/3/4/5/8/15/16/17 LPTIM1/2)

As the timers have multiple mutually independent channels possibly used for different functions, the safety mechanism is selected individually for each channel.

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 107. ATIM_SM_0

ATIM_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to advanced, general-purpose and low-power timer configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 108. ATIM_SM_1

ATIM_SM_1

1oo2 for counting timers

End user

This method implements via software a 1oo2 scheme between two counting resources.

•

•

•

The guidelines for the implementation of the method are the following:

Two timers are programmed with same time base or frequency.

In case of timer use as a time base: use in Application software one of the timer as time base source, and the other one just for check. Coherence check for the 1oo2 is done at application level, comparing two counter values each time the timer value is used to affect safety function.

In case of interrupt generation: use the first timer as main interrupt source for the service routines, and the second timer as a “reference” to be checked at the initial of interrupt routine.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

Tolerance implementation in timer checks is recommended to avoid false positive outcomes of the diagnostic.

This method applies to timer channels merely used as elapsed time counters.

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 109. ATIM_SM_2

ATIM_SM_2

1oo2 for input capture timers

End user

This method is conceived to protect timers used for acquisition and measurement of external signals (input capture, encoder reading). The implementation consists in connecting the external signals also to a redundant timer, and checking the coherence of the measured data at application level.

Coherence check between timers is executed each time the reading is used by Application software .

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

To reduce the potential effect of common cause failures, it is suggested to use for redundant check a channel belonging to a different timer module and mapped to non-adjacent pin on the device package.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Table 110. ATIM_SM_3

ATIM_SM_3

Loopback scheme for pulse width modulation (PWM) outputs

End user

This method is implemented by connecting the PWM to a separate timer channel to acquire the generated waveform characteristics.

•

•

The guidelines are the following:

Both PWM frequency and duty cycle are measured and checked versus the expected value.

To reduce the potential effect of common cause failure, it is suggested to use for the loopback check a channel belonging to a different timer module and mapped to non-adjacent pins on the device package.

This measure can be replaced under the end-user responsibility by different loopback schemes already in place in the final application and rated as equivalent. For example if the PWM is used to drive an external power load, the reading of the on-line current value can be used instead of the PWM duty cycle measurement.

Depends on implementation

Depends on implementation

Depends on implementation

None

Depends on implementation

Continuous

Not applicable

CPU_SM_0: Periodic core self-test software

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Hardware and software diagnostics

SM CODE

Recommendations and known limitations

ATIM_SM_3

Efficiency versus transient failures is linked to final application characteristics. We define as

Tm the minimum duration of PWM wrong signal permanence (wrong frequency, wrong duty, or both) required to violate the related safety function(s). Efficiency is maximized when execution test frequency is higher than 1/Tm.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 111. ATIM_SM_4

ATIM_SM_4

Lock bit protection for timers

ST

This safety mechanism allows End user to lock down specified configuration options, thus avoiding unintended modifications by Application software . Therefore, it addresses software development systematic faults.

Not applicable

Not applicable

None (Fault avoidance)

None

Lock protection must be enabled using LOCK bits in the TIMx_BDTR register.

Continuous

Not applicable

Not applicable

This method does not address timer configuration changes due to soft errors.

Note:

3.6.32

IRTIM is not individually mentioned here as its implementation is mostly based on general-purpose timer functions. Refer to related prescriptions.

Basic timers (TIM6/7)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 112. GTIM_SM_0

GTIM_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to basic timer configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

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Hardware and software diagnostics

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 113. GTIM_SM_1

GTIM_SM_1

1oo2 for counting timers

End user

This method implements via software a 1oo2 scheme between two counting resources.

•

•

•

The guidelines for the implementation of the method are the following:

Two timers are programmed with same time base or frequency.

In case of timer use as a time base: use in Application software one of the timer as time base source, and the other one just for check. Coherence check for the 1oo2 is done at application level, comparing two counters values each time the timer value is used to affect safety function.

In case of interrupt generation usage: use the first timer as main interrupt source for the service routines, and use the second timer as a “reference” to be checked at the initial of interrupt routine.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

Tolerance implementation in timer checks is recommended to avoid false positive outcomes of the diagnostic.

3.6.33

Real-time clock module (RTC)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 114. RTC_SM_0

RTC_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to RTC configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

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SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 115. RTC_SM_1

RTC_SM_1

Application check of running RTC

End user

Application software implements some plausibility check on RTC calendar or timing data, mainly after a power-up and further date reading by RTC.

•

•

•

•

The guidelines for the implementation of the method are the following:

RTC backup registers are used to store coded information in order to detect the absence of VBAT during power-off period.

RTC backup registers are used to periodically store compressed information on current date or time

Application software executes minimal consistence checks for date reading after poweron (detecting “past” date or time retrieve).

Application software periodically checks that RTC is actually running, by reading RTC timestamp progress and comparing with an elapsed time measurement based on

STM32 internal clock or timers.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Periodic

Not applicable

CPU_SM_0: Periodic core self-test software

This method provides a limited diagnostic coverage for RTC failure modes. In case of End user application where RTC timestamps accuracy can affect in severe way the safety function

(for example, medical data storage devices), it is strongly recommended to adopt more efficient system-level measures.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 116. RTC_SM_2

RTC_SM_2

Information redundancy on backup registers

End user

Data stored in RTC backup registers must be protected by a checksum with encoding capability (for instance, CRC). Checksum must be checked by application software before consuming stored data.

This method guarantees data versus erases due to backup battery failures.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Periodic/On demand

Not applicable

CPU_SM_0: Periodic core self-test software

None

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SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 117. RTC_SM_3

RTC_SM_3

Application-level measures to detect failures in timestamps/event capture

End user

This method must detect failures affecting the RTC capability to correct execute the timestamps/event capture functions. Due to the nature strictly application-dependent of this solution, no detailed guidelines for its implementation are given here.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

Periodic/On demand

Not applicable

CPU_SM_0: Periodic core self-test software

This method must be used only if the timestamps/event capture function is used in the safety function implementation. It is worth noting that the use of timestamp / event capture in safety-related applications with the MCU in Sleep or Stop mode is prevented by the assumed requirement ASR7 (refer to

Section 3.3.1 Safety requirement assumptions

).

3.6.34

Inter-integrated circuit (I2C)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 118. IIC_SM_0

IIC_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to I2C configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Table 119. IIC_SM_1

SM CODE

Description

Ownership

Protocol error signals

ST

IIC_SM_1

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SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

IIC_SM_1

I2C communication module embeds protocol error checks (like overrun, underrun, packet error etc.) conceived to detect network-related abnormal conditions. These mechanisms are able anyway to detect a marginal percentage of hardware random failures affecting the module itself.

Error flag raise and optional interrupt event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

IIC_SM_2: Information redundancy techniques on messages

Adoption of SMBus option grants the activation of more efficient protocol-level hardware checks such as CRC-8 packet protection.

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 120. IIC_SM_2

IIC_SM_2

Information redundancy techniques on messages

End user

This method is implemented adding to data packets transferred by I2C a redundancy check

(such as a CRC check, or similar one) with encoding capability. The checksum encoding capability must be robust enough to guarantee at least 90% probability of detection for a single bit flip in the data packet.

Consistency of data packet must be checked by Application software before consuming data.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

It is assumed that the remote I2C counterpart has an equivalent capability of performing the check described.

To give an example on checksum encoding capability, using just a bit-by-bit addition is unappropriated.

This method is superseded by IIC_SM_3 if hardware handled CRC insertion is possible.

Table 121. IIC_SM_3

SM CODE

Description

Ownership

CRC packet-level

ST

IIC_SM_3

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

IIC_SM_3

I2C communication module allows to activate for specific mode of operation (SMBus) the automatic insertion (and check) of CRC checksums to packet data.

Error flag raise and optional Interrupt Event generation

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous

Direct test procedure for CRC efficiency is not available. CRC run-time hardware failures leading to disabling such protection fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

IIC_SM_2: Information redundancy techniques on messages

This method can be part of the implementation for IIC_SM_2 or IIC_SM_4. In that case, because of the warning issued in the Test for the diagnostic field, this mechanism can not be the only one to guarantee message integrity.

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 122. IIC_SM_4

IIC_SM_4

Information redundancy techniques on messages, including end-to-end protection

End user

This method aims to protect the communication between a I2C peripheral and his external counterpart.

Refer to UART_SM_3 description for detailed information.

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

It is assumed that the remote I2C counterpart has an equivalent capability of performing the checks described.

Refer to UART_SM_3 for further notice.

3.6.35

Universal synchronous/asynchronous receiver/transmitter and low power universal asychronous receiver/transmitter (USART1/2/3/4/5/6/7/8 and LPUART)

SM CODE

Description

Ownership

Table 123. UART_SM_0

UART_SM_0

Periodic read-back of configuration registers

End user

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

UART_SM_0

This method must be applied to USART1/2/3/4/5/6/7/8 and LPUART configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 124. UART_SM_1

UART_SM_1

Protocol error signals

ST

USART1/2/3/4/5/6/7/8 and LPUART communication module embeds protocol error checks

(like additional parity bit check, overrun, frame error) conceived to detect network-related abnormal conditions. These mechanisms are able anyway to detect a marginal percentage of hardware random failures affecting the module itself.

Error signals connected to these checkers are normally handled in a standard communication software, so the overhead is reduced.

Error flag raise and optional interrupt event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

UART_SM_2: Information redundancy techniques on messages

USART1/2/3/4/5/6/7/8 and LPUART communication module allows several different configurations. The actual composition of communication error checks depends on the selected configuration.

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Table 125. UART_SM_2

UART_SM_2

Information redundancy techniques on messages

End user

This method is implemented by adding to data packets transferred by USART1/2/3/4/5/6/7/8 and LPUART a redundancy check (such as a CRC check, or similar one) with encoding capability. The checksum encoding capability must be robust enough to guarantee at least

90% probability of detection for a single bit flip in the data packet.

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Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

UART_SM_2

Consistency of data packet must be checked by Application software before consuming data.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

It is assumed that the remote USART1/2/3/4/5/6/7/8 and LPUART counterpart has an equivalent capability of performing the check described.

To give an example on checksum encoding capability, using just a bit-by-bit addition is unappropriated.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 126. UART_SM_3

UART_SM_3

Information redundancy techniques on messages, including end-to-end protection

End user

This method aims to protect the communication between a peripheral and his external counterpart establishing a kind of “protected” channel. The aim is to specifically address communication failure modes as reported in IEC61508:2, 7.4.11.1.

•

•

•

•

Implementation guidelines are as follows:

Data packet must be protected (encapsulated) by an information redundancy check, like for instance a CRC checksum computed over the packet and added to payload.

Checksum encoding capability must be robust enough to guarantee at least 90% probability of detection for a single-bit flip in the data packet.

Additional field added in payload reporting an unique identification of sender or receiver and an unique increasing sequence packet number.

Timing monitoring of the message exchange (for example check the message arrival within the expected time window), detecting therefore missed message arrival conditions.

Application software must verify before consuming data packet its consistency (CRC check), its legitimacy (sender or receiver) and the sequence correctness (sequence number check, no packets lost).

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

A major overlap between the requirements of this method and the implementation of complex communication software protocols can exists. Due to large adoption of these protocols in industrial applications, optimizations can be possible.

It is assumed that the remote counterpart has an equivalent capability of performing the checks described.

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Hardware and software diagnostics

3.6.36

Serial peripheral interface (SPI)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 127. SPI_SM_0

SPI_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to SPI configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 128. SPI_SM_1

SPI_SM_1

Protocol error signals

ST

SPI communication module embeds protocol error checks (like overrun, underrun, timeout and so on) conceived to detect network-related abnormal conditions. These mechanisms are able anyway to detect a marginal percentage of hardware random failures affecting the module itself.

Error flag raise and optional interrupt event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

SPI_SM_2: Information redundancy techniques on messages

None

SM CODE

Description

Ownership

Table 129. SPI_SM_2

SPI_SM_2

Information redundancy techniques on messages

End user

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device

Initialization

Periodicity

configuration

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SPI_SM_2

This method is implemented adding to data packets transferred by SPI a redundancy check

(such as a CRC check, or similar one) with encoding capability. The checksum encoding capability must be robust enough to guarantee at least 90% probability of detection for a single bit flip in the data packet.

Consistency of data packet must be checked by Application software before consuming data.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

It is assumed that the remote SPI counterpart has an equivalent capability of performing the check described.

To give an example on checksum encoding capability, using just a bit-by-bit addition is unappropriated.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 130. SPI_SM_3

SPI_SM_3

CRC packet-level

ST

SPI communication module allows to activate automatic insertion (and check) of CRC-8 or

CRC-18 checksums to packet data.

Error flag raise and optional Interrupt Event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

Permanent/transient

None

Depends on implementation

Continuous

Direct test procedure for CRC efficiency is not available. CRC run-time hardware failures leading to disabling such protection fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

SPI_SM_2: Information redundancy techniques on messages

This method can be part of the implementation for SPI_SM_2 or SPI_SM_4. In that case, because of the warning issued in the Test for the diagnostic field, this mechanism can not be the only one to guarantee message integrity.

SM CODE

Description

Ownership

Table 131. SPI_SM_4

SPI_SM_4

Information redundancy techniques on messages, including end-to-end protection

End user

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Hardware and software diagnostics

SM CODE

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device

Periodicity

configuration

Initialization

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SPI_SM_4

This method aims to protect the communication between SPI peripheral and his external counterpart.

Refer to UART_SM_3 description for detailed information.

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3 for further notice.

It is assumed that the remote SPI counterpart has an equivalent capability of performing the checks described.

3.6.37

Serial audio interface (SAI)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 132. SAI_SM_0

SAI_SM_0

Periodic read-back of SAI configuration registers

End user

This method must be applied to SAI configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Table 133. SAI_SM_1

SAI_SM_1

SAI output loopback scheme

End user

This method uses a loopback scheme to detect permanent and transient faults on the output channel used for serial audio frame generation. It is implemented by connecting the second serial audio interface as input for primary output generation. Application software is able therefore to identify wrong or missing audio frame generation.

Depends on implementation

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Hardware and software diagnostics

SM CODE

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SAI_SM_1

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous/ On demand

Not applicable

CPU_SM_0: Periodic core self-test software

Efficiency versus transient failures is linked to final application characteristics. We define as

Tm the minimum duration of serial audio wrong signal permanence required to violate the related safety function(s). Efficiency is maximized when execution test frequency is higher than 1/Tm.

Method to be used when SAI interface safety-related use is audio stream generation .

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 134. SAI_SM_2

SAI_SM_2

1oo2 scheme for SAI module

End user

This safety mechanism is implemented using the two SAI interfaces to decode/receive the same input stream audio. Application software checks the coherence between the received data.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

The MCU performance overload and the implementation complexity associated to this method can be relevant.

Method to be used when SAI interface safety-related use is audio stream receive .

3.6.38

Single Wire Protocol Master Interface (SWPMI)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Table 135. SWPMI_SM_0

SWPMI_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to SWPMI configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

UM2305 - Rev 10 page 75/110

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Hardware and software diagnostics

SM CODE

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SWPMI_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 136. SWPMI_SM_1

SWPMI_SM_1

Protocol error signals and information redundancy including hardware CRC

ST

SWPMI communication is based on a frame handling concept, composed by a combination of hardware synchronization signals, frame structure composition, hardware-computed CRC filed. This mechanism, mainly implemented to manage on-field communication disturbance, is able to achieve a relevant diagnostic coverage on several SWMPI module failure modes.

Error conditions are reported by flag bits in related registers.

Depends on implementation

Permanent/transient

None

Depends on implementation

Continuous

Direct test procedure for CRC efficiency is not available. CRC run-time hardware failures leading to disabling such protection fall into multiple-fault scenario, from IEC61508 perspective. Related failures are adequately mitigated by the combination of safety mechanisms reported in this table, field Multiple-fault protection .

SWPMI_SM_0: Periodic read-back of configuration registers

SWPMI_SM_2: SWMPI loopback test

This method is unable to address all IEC 61508 failure modes related to time handshake between parties (e.g. resequencing, repetition), leading to the introduction of SWPMI_SM_3.

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Table 137. SWPMI_SM_2

SWPMI_SM_2

SWMPI loopback test

End user

By using the SWPMI module loopback function, it is possible to emulate the sending of SWPI frames and cross-checking the expected result in reception.

Error conditions are reported by flag bits in related registers

Depends on implementation

Permanent

None

Loopback mode must be enabled.

UM2305 - Rev 10 page 76/110

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Hardware and software diagnostics

SM CODE

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SWPMI_SM_2

Periodic

Not applicable

-

SWPMI_SM_0: Periodic read-back of configuration registers

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 138. SWPMI_SM_3

SWPMI_SM_3

Information redundancy techniques on messages to implement full end-to-end operation

End user

This method aims to protect the communication between a peripheral and its external counterpart establishing a kind of “protected” channel. The aim is to specifically address communication failure modes as reported in IEC 61508:2, 7.4.11.1.

•

•

•

Implementation guidelines are the following:

Additional field added in payload reporting an unique identification of sender/receiver and an unique increasing sequence packet number

Timing monitoring of the message exchange (for example check the message arrival within the expected time window), detecting therefore missed message arrival conditions

Application software must verify before consuming data packet its consistency (CRC check), its legitimacy (sender/receiver) and the correctness of sequence (sequence number check, no packets lost)

Depends on implementation

Depends on implementation

Depends on implementation

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

It is assumed that the remote SWMPI counterpart has an equivalent capability of performing the checks described. This method is simplified by the existence of SWPMI_SM_1.

A major overlap between the requirements of this method and the implementation of security protection on the transaction is possible.

3.6.39

SD/SDIO/MMC card host interface (SDMMC)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Table 139. SDIO_SM_0

SDIO_SM_0

Periodic read-back of SDIO/SMMC configuration registers

End user

This method must be applied to SDIO/SMMC configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

UM2305 - Rev 10 page 77/110

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Hardware and software diagnostics

SM CODE

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SDIO_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 140. SDIO_SM_1

SDIO_SM_1

Protocol error signals including hardware CRC

ST

SDIO/SMMC communication module embeds protocol error checks (like overrun, underrun, timeout etc.) and CRC-packet checks as well, conceived to detect network-related abnormal conditions. These mechanisms are able anyway to detect a percentage of hardware random failures affecting the module itself

Error flag raise and optional interrupt event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

SDIO_SM_2: Information redundancy techniques on messages

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Table 141. SDIO_SM_2

SDIO_SM_2

Information redundancy techniques on messages

End user

This method is implemented adding to data packets transferred by SDIO/SMMC a redundancy check (like a CRC check, or similar one) with encoding capability. The checksum encoding capability must be robust enough to guarantee at least 90% probability of detection for a single bit flip in the data packet.

Consistency of data packet must be checked by Application software before consuming data.

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

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Hardware and software diagnostics

SM CODE

Multiple-fault protection

Recommendations and known limitations

SDIO_SM_2

CPU_SM_0: Periodic core self-test software

To give an example on checksum encoding capability, using just a bit-by-bit addition is unappropriated.

This safety mechanism can overlap with information redundancy techniques implemented at system level to address failure of physical device connected to SDIO/SMMMC port.

Note:

3.6.40

The safety mechanisms mentioned above are addressing the SDIO/SMMC interface included in STM32 MCUs.

No claims are done in this Safety Manual about the mitigation of hardware random faults affecting the external memory connected to SDIO/SMMC port.

Controller area network (bxCAN)

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 142. CAN_SM_0

CAN_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to bxCAN configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Table 143. CAN_SM_1

CAN_SM_1

Protocol error signals

ST

CAN communication module embeds protocol error checks (like error counters) conceived to detect network-related abnormal conditions. These mechanisms are able anyway to detect a marginal percentage of hardware random failures affecting the module itself.

Error signals connected to these checkers are normally handled in a standard communication software, so the overhead is reduced.

Several error condition are reported by flag bits in related CAN registers.

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

Permanent/transient

None

Depends on implementation

Continuous

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Hardware and software diagnostics

SM CODE

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

CAN_SM_1

Not applicable

CAN_SM_2: Information redundancy techniques on messages, including end-to-end protection.

Enabling related interrupt generation on the detection of errors is highly recommended.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 144. CAN_SM_2

CAN_SM_2

Information redundancy techniques on messages, including end-to-end protection.

End user

This method aims to protect the communication between a peripheral and his external counterpart establishing a kind of “protected” channel. The aim is to specifically address communication failure modes as reported in IEC61508:2, 7.4.11.1.

•

•

•

•

Implementation guidelines are as follows:

Data packet must be protected (encapsulated) by an information redundancy check, like for instance a CRC checksum computed over the packet and added to payload.

Checksum encoding capability must be robust enough to guarantee at least 90% probability of detection for a single-bit flip in the data packet.

Additional field added in payload reporting an unique identification of sender or receiver and an unique increasing sequence packet number.

Timing monitoring of the message exchange (for example check the message arrival within the expected time window), detecting therefore missed message arrival conditions.

Application software must verify before consuming data packet its consistency (CRC check), its legitimacy (sender or receiver) and the sequence correctness (sequence number check, no packets lost).

Depends on implementation

Depends on implementation

Permanent/transient

None

Depends on implementation

On demand

Not applicable

CPU_SM_0: Periodic core self-test software

A major overlap between the requirements of this method and the implementation of complex communication software protocols can exists. Due to large adoption of these protocols in industrial applications, optimizations can be possible.

It is assumed that the remote counterpart has an equivalent capability of performing the checks described.

3.6.41

Universal serial bus full-speed device interface (OTG_FS)

SM CODE

Description

Ownership

Detailed implementation

Table 145. USB_SM_0

USB_SM_0

Periodic read-back of configuration registers

End user

This method must be applied to USB configuration registers.

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

UM2305 - Rev 10 page 80/110

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Hardware and software diagnostics

SM CODE

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

USB_SM_0

Table 146. USB_SM_1

USB_SM_1

Protocol error signals

ST

USB communication module embeds protocol error checks (like overrun, underrun, NRZI, bit stuffing etc.) conceived to detect network-related abnormal conditions. These mechanisms are able anyway to detect a marginal percentage of hardware random failures affecting the module itself

Error flag raise and optional interrupt event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation

Permanent/transient

None

Depends on implementation

Continuous

Not applicable

USB_SM_2: Information redundancy techniques on messages

Enabling related interrupt generation on the detection of errors is highly recommended.

Table 147. USB_SM_2

USB_SM_2

Information redundancy techniques on messages

End user or ST

The implementation of required information redundancy on messages, USB communication module is fitted by hardware capability. It basically allows to activate the automatic insertion

(and check) of CRC checksums to packet data.

Error flag raise and optional interrupt event generation

Depends on peripheral configuration (for example baud rate). Refer to functional documentation.

Permanent/transient

None

Error reporting configuration, if interrupt events are planned

Continuous

UM2305 - Rev 10 page 81/110

UM2305

Hardware and software diagnostics

SM CODE

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

USB_SM_2

Not applicable

CPU_SM_0: Periodic core self-test software

None

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

3.6.42

Table 148. USB_SM_3

USB_SM_3

Information redundancy techniques on messages, including end-to-end protection.

End user

This method aims to protect the communication between the USB OTG_FS peripheral and its external counterpart.

Refer to UART_SM_3 description for detailed information.

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

Refer to UART_SM_3

This method applies in case USB bulk or isochronous transfers are used. For other transfers modes the USB hardware protocol already implements several features of this requirement.

Refer to UART_SM_3 for further notice.

Part separation (no interference)

This section reports safety mechanisms that address peripherals not used by the safety application, or not used at all.

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Table 149. FFI_SM_0

FFI_SM_0

Disable of unused peripherals

End user

This method contributes to the reduction of the probability of cross-interferences caused by peripherals not used by the software application, in case a hardware failure causes an unintentional activation.

•

•

After the system boot, Application software must disable all unused peripherals with this procedure:

Enable reset flag on AHB and APB peripheral reset register.

Disable clock distribution on AHB and APB peripheral clock enable register.

Not applicable

Not applicable

Not applicable

None

Not applicable

UM2305 - Rev 10 page 82/110

UM2305

Conditions of use

SM CODE

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

FFI_SM_0

Startup

Not applicable

FFI_SM_1: Periodic read-back of interference avoidance registers

None

SM CODE

Description

Ownership

Detailed implementation

Error reporting

Fault detection time

Addressed fault model

Dependency on Device configuration

Initialization

Periodicity

Test for the diagnostic

Multiple-fault protection

Recommendations and known limitations

Table 150. FFI_SM_1

FFI_SM_1

Periodic read-back of interference avoidance registers

End user

•

•

This method contributes to the reduction of the probability of cross-interferences between peripherals that can potentially conflict on the same input/output pins, including for instance unused peripherals. This diagnostic measure must be applied to following registers: clock enable and disable registers alternate function programming registers

Detailed information on the implementation of this method can be found in

Section 3.6.14 Extended interrupt and events controller (EXTI)

.

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

Refer to NVIC_SM_0

3.7

Conditions of use

The table below provides a summary of the safety concept recommendations reported in

Section 3.6 Hardware and software diagnostics

. The conditions of use to be applied to STM32L4 and STM32L4+ Series devices are reported in form of safety mechanism requirements. Exception is represented by some conditions of use introduced by FMEA analysis in order to correctly address specific failure modes. These conditions of use are reported at the end of the table presented in this section.

Rank column reports how related safety mechanism has been considered during the analysis, with following meaning:

M

++

+ o

The safety mechanism is always active during normal operation, with no possibility for End user to deactivate it.

The safety mechanism is highly recommended as common practice. It is considered in this document for the computation of safety metrics to allow the use of Device in systems implementing safety functions up to SIL 2 with a single MCU or up to SIL 3 with two MCU s in 1oo2 scheme.

The safety mechanism is recommended as additional safety measure, but not considered in this document for the computation of safety metrics. STM32L4 and STM32L4+ Series users can skip the implementation in case it is in contradiction with functional requirements or overlapped by another mechanism ranked ++ .

The safety mechanism is optional. It is not strictly required for the implementation of safety functions up to SIL 2, or it is related to a specific MCU configuration.

UM2305 - Rev 10 page 83/110

UM2305

Conditions of use

The X marker in the Perm and Trans table columns indicates that the related safety mechanism is effective for such fault model.

Diagnostic

CPU_SM_0

CPU_SM_1

CPU_SM_2

CPU_SM_3

CPU_SM_4

CPU_SM_5

CPU_SM_6

CPU_SM_7

CPU_SM_8

MPU_SM_0

MPU_SM_1

BUS_SM_0

BUS_SM_1

RAM_SM_0

RAM_SM_1

RAM_SM_2

RAM_SM_3

RAM_SM_4

RAM_SM_5

RAM_SM_6

FLASH_SM_0

FLASH_SM_1

FLASH_SM_2

FLASH_SM_3

FLASH_SM_4

FLASH_SM_5

FLASH_SM_6

FLASH_SM_7

FLASH_SM_8

Table 151. List of safety recommendations

Description

Arm ® Cortex ® -M4

Periodic core self-test software for Arm ® Cortex ® -

M4 CPU .

Control flow monitoring in Application software

Double computation in Application software

Arm ® Cortex ® -M4 HardFault exceptions

Stack hardening for Application software

External watchdog

Independent watchdog

Memory protection unit ( MPU ).

AMBA firewall

Periodic read-back of MPU configuration registers

MPU software test

System bus architecture/BusMatrix

Periodic software test for interconnections

Information redundancy in intra-chip data exchanges

Embedded SRAM

Periodic software test for static random access memory

(SRAM)

Parity on SRAM2

Stack hardening for Application software

Information redundancy for safety-related variables in

Application software

Control flow monitoring in Application software

Periodic integrity test for Application software in RAM

Read protection (RDP) and write protection (WRP)

Embedded Flash memory

Periodic software test for Flash memory

Control flow monitoring in Application software

Arm ® Cortex ® -M4 HardFault exceptions

Option byte write protection

Static data encapsulation

Option byte redundancy with load verification

Flash memory unused area filling code

ECC on Flash memory

Read protection (RDP), write protection (WRP), and proprietary code readout protection (PCROP)

Rank

++

++

++

++

++

+

++

o (3) o (3)

+

+

+

++

M

M

+

M

+

++

++

++

M

+

++

(1)

++

(1)

++

(2)

+

++

(2)

o

Perm

X

X

X

X

-

X

X

X

-

X

X

X

X

X

X

X

X

-

X

X

X

X

-

X

-

X

-

X

X

Trans

-

X

X

X

X

X

-

-

X

X

X

-

X

-

X

-

-

X

-

X

X

X

X

X

X

X

-

X

-

UM2305 - Rev 10 page 84/110

Diagnostic

FLASH_SM_9

FWR_SM_0

VSUP_SM_0

VSUP_SM_1

VSUP_SM_2

VSUP_SM_3

VSUP_SM_4

VSUP_SM_5

CLK_SM_0

CLK_SM_1

CLK_SM_2

CLK_SM_3

GPIO_SM_0

GPIO_SM_1

GPIO_SM_2

GPIO_SM_3

DBG_SM_0

LOCK_SM_0

SYSCFG_SM_0

DIAG_SM_0

DMA_SM_0

DMA_SM_1

DMA_SM_2

DMA_SM_3

DMA_SM_4

DMA2D_SM_0

DMA2D_SM_1

DMA2D_SM_2

GFX_SM_0

Description Rank

Periodic test by software for Flash memory address decoder

Firewall (FW)

Periodic read-back of Firewall configuration registers

Power controller (PWR)

Periodic read-back of configuration registers

Supply voltage internal monitoring (PVD)

Independent watchdog

Internal temperature sensor check

Peripheral voltage monitoring (PVM)

System-level power supply management

Reset and clock controller (RCC)

Periodic read-back of configuration registers

Clock security system (CSS)

Independent watchdog

Internal clock cross-measurement

General-purpose input/output (GPIO)

++ o

Periodic read-back of configuration registers

1oo2 for input GPIO lines

Loopback scheme for output GPIO lines

GPIO port configuration lock register

Debug system or peripheral control

Watchdog protection

Lock mechanism for configuration options

System configuration controller (SYSCFG)

Periodic read-back of configuration registers

++

+

++

Periodic read-back of hardware diagnostics configuration registers

++

Direct memory access controller (DMA/ DMA2D/ DMAMUX))

++ Periodic read-back of configuration registers

Information redundancy on data packet transferred via

DMA

++

Information redundancy by including sender or receiver identifier on data packet transferred via DMA

Periodic software test for DMA

DMA transaction awareness

Chrom-Art Accelerator controller (DMA2D)

++

++

++

Periodic read-back of configuration registers

Periodic software test for DMA2D functions

DMA processing and interrupt awareness

Chrom-GRC™ (GFXMMU)

Periodic read-back of GFXMMU configuration registers

++

++

++

++

++

++

++

+

++

++

++

+

++

++

++ o

+

+

UM2305

Conditions of use

Trans

X

X

X

X

-

X

-

-

-

X

-

-

-

-

X

-

X

X

X

-

X

-

X

X

X

-

X

X

X

Perm

X

X

X

X

-

X

X

X

X

X

X

-

X

-

X

X

X

X

X

-

X

X

X

X

X

X

X

X

X

UM2305 - Rev 10 page 85/110

Diagnostic

GFX_SM_1

NVIC_SM_0

NVIC_SM_1

CRC_SM_0

FSMC_SM_0

FSMC_SM_1

FSMC_SM_2

FSMC_SM_3

QSPI_SM_0

QSPI_SM_1

QSPI_SM_2

ADC_SM_0

ADC_SM_1

ADC_SM_2

ADC_SM_3

ADC_SM_4

DAC_SM_0

DAC_SM_1

VREF_SM_0

VREF_SM_1

COMP_SM_0

COMP_SM_1

COMP_SM_2

COMP_SM_3

COMP_SM_4

AMP_SM_0

DFS_SM_0

DFS_SM_1

DFS_SM_2

DFS_SM_3

Description Rank

Periodic LUT read-back

Extended interrupt and events controller (EXTI)

Periodic read-back of configuration registers

Expected and unexpected interrupt check

Cyclic redundancy-check calculation unit (CRC)

CRC self-coverage

Flexible static memory controller (FSMC)

++

++

++

++

Control flow monitoring in Application software

Information redundancy on external memory connected to FSMC

Periodic read-back of FSMC configuration registers

ECC engine on NAND interface in FSMC module

Information redundancy techniques on messages

Analog-to-digital converter (ADC)

++

++

++

++

Quad-SPI interface and Octo-SPI interface (QUADSPI/OCTOSPI)

Periodic read-back of OCTOSPI configuration registers

Protocol error signals including hardware CRC

++

++

++

Periodic read-back of configuration registers

Multiple acquisition by Application software

Range check by Application software

Periodic software test for ADC

1oo2 scheme for ADC inputs

++

++

++

++

+

Digital-to-analog converter (DAC)

Periodic read-back of configuration registers

DAC output loopback on ADC channel

Voltage reference buffer (VREFBUF)

Periodic read-back of VREFBUF system configuration registers

VREF cross-check by ADC reading

Comparator (COMP)

Periodic read-back of configuration registers

1oo2 scheme for comparator

Plausibility check on inputs

Multiple acquisition by Application software

Comparator lock mechanism

Operational amplifiers (OPAMP)

Periodic read-back of OPAMP configuration registers

Digital filter for sigma delta modulators (DFSDM)

Periodic read-back of DFSDM configuration registers

Multiple acquisition by Application software

Range check by Application software

1oo2 scheme for DFSM inputs

++

++

++

+

++

++

++

++

+

+

+

+

++

++

UM2305

Conditions of use

X

X

X

X

X

Trans

X

X

X

X

X

X

-

X

X

X

X

X

X

X

-

-

X

-

X

X

X

X

X

X

X

X

X

X

X

-

Perm

X

X

X

X

-

X

X

X

X

X

X

X

X

X

X

X

-

-

X

X

X

X

X

X

-

UM2305 - Rev 10 page 86/110

Diagnostic

DCMI_SM_0

DCMI_SM_1

LCD_SM_0

LCD_SM_1

DSI_SM_0

DSI_SM_1

JPEG_SM_0

JPEG_SM_1

JPEG_SM_2

TSC_SM_0

TSC_SM_1

TSC_SM_2

RNG_SM_0

RNG_SM_1

AES_SM_0

AES_SM_1

AES_SM_2

HASH_SM_0

HASH_SM_1

ATIM_SM_0

ATIM_SM_1

ATIM_SM_2

ATIM_SM_3

ATIM_SM_4

GTIM_SM_0

GTIM_SM_1

Description Rank

Digital camera interface (DCMI)

Periodic read-back of DCMI configuration registers

DCMI video input data synchronization

LCD-TFT display controller (LTDC)

Periodic read-back of LTDC configuration registers and buffer memory

Periodic read-back of configuration registers

1oo2 for counting timers

1oo2 for input capture timers

Loopback scheme for pulse width modulation (PWM) outputs

Lock bit protection for timers

Basic timers (TIM6/7)

Periodic read-back of configuration registers

1oo2 for counting timers

++

++

++

LTDC acquisition by ADC channel

DSI Host (DSI)

Periodic read-back of DSI configuration registers

Protocol error signals and information redundancy including hardware checksums

JPEG codec (JPEG)

Periodic read-back of JPEG codec configuration registers

++

++

++

Periodic test for JPEG encoding/decoding functions

Application-level detection of failures affecting JPEG coding/encoding

Touch sensing controller (TSC)

Periodic read-back of configuration registers

++

++

++

Multiple acquisition by Application software

Application-level detection of permanent failures of TSC acquisition

True random number generator (RNG)

++

++

+

Periodic read-back of RNG configuration register

RNG module entropy on-line tests

++

++

Advanced encryption standard hardware accelerator (AES)

Periodic read-back of AES configuration registers ++

++ Encryption/decryption collateral detection

Information redundancy techniques on messages, including end-to-end protection

++

HASH processor (HASH)

Periodic read-back of HASH configuration registers ++

HASH processing collateral detection ++

Advanced, general, and low-power timer (TIM1/2/3/4/5/8/15/16/17 LPTIM1/2)

++

++

++

++

+

++

++

Perm

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

-

X

X

X

X

X

-

X

X

X

UM2305

Conditions of use

X

X

X

-

X

-

X

Trans

X

X

X

X

X

X

-

X

X

-

X

-

X

X

X

X

X

X

X

UM2305 - Rev 10 page 87/110

UM2305

Conditions of use

Diagnostic Description Rank Perm Trans

RTC_SM_0

RTC_SM_1

RTC_SM_2

RTC_SM_3

IIC_SM_0

IIC_SM_1

IIC_SM_2

IIC_SM_3

IIC_SM_4

Real-time clock module (RTC)

Periodic read-back of configuration registers

Application check of running RTC

Information redundancy on backup registers

Application-level measures to detect failures in timestamps/event capture

Inter-integrated circuit (I2C)

Periodic read-back of configuration registers

Protocol error signals

Information redundancy techniques on messages

CRC packet-level

Information redundancy techniques on messages, including end-to-end protection

++

++ o o

++

++

++

+

+

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Universal synchronous/asynchronous receiver/transmitter and low power universal asychronous receiver/transmitter

(USART1/2/3/4/5/6/7/8 and LPUART)

UART_SM_0 Periodic read-back of configuration registers ++ X X

UART_SM_1

UART_SM_2

Protocol error signals

Information redundancy techniques on messages

++

++

X

X

X

X

UART_SM_3

SPI_SM_0

SPI_SM_1

SPI_SM_2

SPI_SM_3

SPI_SM_4

Information redundancy techniques on messages, including end-to-end protection

Serial peripheral interface (SPI)

Periodic read-back of configuration registers

Protocol error signals

Information redundancy techniques on messages

CRC packet-level

Information redundancy techniques on messages, including end-to-end protection

++

++

++

++

+

+

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

SAI_SM_0

SAI_SM_1

SAI_SM_2

SWPMI_SM_0

SWPMI_SM_1

SWPMI_SM_2

SWPMI_SM_3

SDIO_SM_0

SDIO_SM_1

SDIO_SM_2

Serial audio interface (SAI)

Periodic read-back of SAI configuration registers

SAI output loopback scheme

1oo2 scheme for SAI module

Single Wire Protocol Master Interface (SWPMI)

Periodic read-back of configuration registers

Protocol error signals and information redundancy including hardware CRC

SWMPI loopback test

Information redundancy techniques on messages to implement full end-to-end operation

SD/SDIO/MMC card host interface (SDMMC)

Periodic read-back of SDIO/SMMC configuration registers

Protocol error signals including hardware CRC

Information redundancy techniques on messages

++

++

++

++

++

+

++

++

++

++

X

X

X

X

X

X

X

X

X

X

X

X

-

X

X

X

X

X

X

X

UM2305 - Rev 10 page 88/110

Diagnostic

CAN_SM_0

CAN_SM_1

CAN_SM_2

USB_SM_0

USB_SM_1

USB_SM_2

USB_SM_3

FFI_SM_0

FFI_SM_1

CoU_1

CoU_2

CoU_3

CoU_4

CoU_5

CoU_6

CoU_7

CoU_8

Description Rank

Controller area network (bxCAN)

Periodic read-back of configuration registers

Protocol error signals

Information redundancy techniques on messages, including end-to-end protection.

++

++

++

Universal serial bus full-speed device interface (OTG_FS)

Periodic read-back of configuration registers ++

Protocol error signals

Information redundancy techniques on messages

Information redundancy techniques on messages, including end-to-end protection.

Part separation (no interference)

Disable of unused peripherals

Periodic read-back of interference avoidance registers

Arm ® Cortex ® -M4 CPU

++

++

+

++

++

The reset condition of Arm ® Cortex ® - M4 CPU must be compatible as valid safe state at system level

Debug

Device debug features must not be used in safety function(s) implementation.

++

++

Arm ® Cortex ® -M4 / Supply system

Low-power mode state must not be used in safety function(s) implementation.

Device peripherals

End user must implement the required combination of safety mechanism/CoUs for each STM32 peripheral used in implementation of safety function(s).

Flash memory subsystem

During Flash memory bank mass erase and reprogramming there must not be safety functions(s) executed by Device .

On ‑ field Application software live update by dual ‑ bank

Flash memory system must include the execution of code/data integrity check through methods such as

FLASH_SM_0

CPU subsystem

In case of multiple safety functions implementations, methods to guarantee their mutual independence must include use.

Clock recovery system (CRS)

CRS features must not be used in safety function(s) implementation.

Device

Cross-check between two STM32 MCUs

++

++

++

++

++

++ o DUAL_SM_0

1. To achieve on the single MCU local safety metrics compatible with SIL2 target , method CPU_SM_6 could be sufficient. Anyway, to understand the rationale behind "++" classification for both methods, refer to the

“Recommendations” row of related description in Section 3.6 Hardware and software diagnostics for more

details.

Perm

-

-

-

-

-

X

X

-

-

-

X

X

X

X

X

X

X

X

UM2305

Conditions of use

X

X

X

X

-

-

Trans

X

X

X

-

X

-

X

-

-

-

-

X

UM2305 - Rev 10 page 89/110

UM2305

Conditions of use

2. Can be considered ranked as “+” if only one safety function is implemented and the presence of non-safetyrelated software is excluded.

3. Must be considered ranked as “++” if Application software is executed on RAM.

The above-described safety mechanism or conditions of use are conceived with different levels of abstraction depending on their nature: the more a safety mechanism is implemented as application-independent, the wider is its possible use on a large range of End user applications.

The safety analysis highlights two major partitions inside the MCU :

• System-critical MCU modules

•

Every End user application is affected, from safety point of view, by a failure on these modules. Because they are used by every End user application, related methods or safety mechanism are mainly conceived to be application-independent. The system-critical modules on Device are: CPU, RCC, PWR, bus matrix and interconnect, and Flash memory and RAM (including their interfaces).

Peripheral modules

Such modules could be not used by the end-user application, or they could be used for non-safety related tasks. Related safety methods are therefore implemented mainly at application level, as Application software solutions or architectural solutions.

UM2305 - Rev 10 page 90/110

4

4.1

Note:

4.1.1

UM2305

Safety results

Safety results

This section reports the results of the safety analysis of the STM32L4 and STM32L4+ Series devices, according to IEC 61508 and to ST methodology flow, related to the hardware random and dependent failures.

Random hardware failure safety results

•

•

The analysis for random hardware failures of STM32L4 and STM32L4+ Series devices reported in this safety manual is executed according to STMicroelectronics methodology flow for safety analysis of semiconductor devices in compliance with IEC61508. The accuracy of results obtained are guaranteed by three factors:

STMicroelectronics methodology flow strict adherence to IEC61508 requirements and prescriptions the use, during the analysis, of detailed and reliable information on microcontroller design

• the use of state-of-the-art fault injection methods and tools for safety metrics verification

The Device safety analysis explored the overall and exhaustive list of Device failure modes, to individuate for each of them an adequate mitigation measure (safety mechanism). The overall list of Device failure modes is maintained in the related FMEA document

[1] , provided on demand by local STMicroelectronics sales office.

In summary, with the adoption of the safety mechanisms and conditions of use reported in

Section 3.7 Conditions of use , it is possible to achieve the integrity levels summarized in the following table.

Table 152. Overall achievable safety integrity levels

Number of

Devices used

Safety architecture

Target Safety analysis result

1

2

1oo1/1oo1D

1oo2

SIL 2 LD Achievable

SIL 2 HD / CM Achievable with potential performance impact

(1)

SIL 3 LD Achievable

SIL 3 HD / CM Achievable with potential performance impact

1. Note that the potential performance impact related to some above-reported target achievements is mainly related to the need of execution of periodical software-based diagnostics (refer to safety mechanism description for details). The impact

is therefore strictly related to how much “aggressive” the system level PST is (see Section 3.3.1 Safety requirement assumptions

).

•

•

The resulting relative safety metrics ( diagnostic coverage (DC) and safe failure fraction (SFF)

) and absolute

safety metrics ( probability of failure per hour (PFH)

,

probability of dangerous failure on demand (PFD)

) are not reported in this section but in the

failure mode effect diagnostic analysis (FMEDA) snapshot

[2] , due to:

• a large number of different STM32L4 and STM32L4+ Series parts, a possibility to declare non-safety-relevant unused peripherals, and a possibility to enable or not the different available safety mechanisms.

The FMEDA

snapshot [2]

is a static document reporting the safety metrics computed at different detail levels (at microcontroller level and for microcontroller basic functions) for a given combination of safety mechanisms and for a given part number. If FMEDA computation sheet is needed, early contact the local STMicroelectronics sales representative, in order to receive information on expected delivery dates for specific Device target part number.

Safety metrics computations are restricted to STM32L4 and STM32L4+ Series boundary, hence they do not

include the WDTe, PEv, and VMONe processes described in Section 3.3.1 Safety requirement assumptions

).

Safety analysis result customization

The safety analysis executed for STM32L4 and STM32L4+ Series devices documented in this safety manual considers all microcontroller modules to be safety-related, thus able to interfere with the safety function, with no exclusion. This is in line with the conservative approach to be followed during the analysis of a general-purpose microcontroller, in order to be agnostic versus the final application. This means that no microcontroller module has been declared safe as per IEC61508-4, 3.6.8. Therefore, all microcontroller modules are included in SFF computations.

UM2305 - Rev 10 page 91/110

Note:

4.1.2

UM2305

Random hardware failure safety results

•

•

In actual End user applications, not all the STM32L4 and STM32L4+ Series parts or modules implement a safety function. That happens if:

The part is not used at all (disabled), or

The part implements functions that are not safety-related (for example, a GPIO line driving a power-on signaling light on an electronic board).

Implementation of non-safety-related functions is in principle forbidden by the assumed safety requirement

ASR6 (see

Section 3.3.1 Safety requirement assumptions

), hence under End user's entire responsibility. As any other derogation from safety requirements included in this manual, it is End user's responsibility to provide consistent rationales and evidences that the function does not bring additional risks, by following the procedure described in this section. Therefore, it is strongly recommended to reserve such derogation to very simple functions (as the one provided in the example).

•

•

Implementing safety mechanisms on such parts would be a useless effort for End user . The safety analysis results can therefore be customized.

End user can define a STM32L4 and STM32L4+ Series part as non-safety-related based on:

•

Collecting rationales and evidences that the part does not contribute to safety function.

Collecting rationales and evidences that the part does not interfere with the safety function during normal operation, due to final system design decisions. Mitigation of unused modules is exhaustively addressed in

Section 4.1.2 General requirements for freedom from interferences (FFI) .

Fulfilling the general condition for the mitigation of intraMCU interferences (see

Section 4.1.2 General requirements for freedom from interferences (FFI) ).

For a non-safety-related part, End user is allowed to:

• Exclude the part from computing metrics to report in FMEDA , and

•

Not implement safety mechanisms as listed in Table 151. List of safety recommendations

.

With regard to SFF computation, this section complies with the no part / no effect definition as per IEC 61508 ‑ 4,

3.6.13 / 3.6.14.

General requirements for freedom from interferences (FFI)

A dedicated analysis has highlighted a list of general requirements to be followed in order to mitigate potential interferences between Device internal modules in case of internal failures (freedom from interferences, FFI).

These precautions are integral part of the Device safety concept and they can play a relevant role when multiple microcontroller modules are declared as non-safety-related by End user

as per Section 4.1.1 Safety analysis result customization

.

End user must implement the safety mechanisms listed in

Table 153 (implementation details in

Section 3.6 Hardware and software diagnostics

) regardless any evaluation of their contribution to safety metrics.

Table 153. List of general requirements for FFI

Diagnostic

BUS_SM_0 Periodic software test for interconnections

GPIO_SM_0 Periodic read-back of configuration registers

DMA_SM_0 Periodic read-back of configuration registers

Description

DMA_SM_2 Information redundancy by including sender or receiver identifier on data packet transferred via

DMA (1)

DMA_SM_4 DMA transaction awareness

(1)

NVIC_SM_0 Periodic read-back of configuration registers

NVIC_SM_1 Expected and unexpected interrupt check

FFI_SM_0

FFI_SM_1

Disable of unused peripherals

Periodic read-back of interference avoidance registers

1. To be implemented only if DMA is actually used.

UM2305 - Rev 10 page 92/110

4.1.3

4.2

4.2.1

4.2.2

UM2305

Analysis of dependent failures

Notes on multiple-fault scenario

According to the requirements of IEC61508, the safety analysis for STM32L4 and STM32L4+ Series devices considered multiple-fault scenarios. Furthermore, following the spirit of ISO26262 (the reference and state-of-theart standard norm for integrated circuit safety analysis), the analysis investigated possible causes preventing the implemented safety mechanisms from being effective, in order to determine appropriate counter-measures.

In the Multiple-fault protection

field, the tables in Section 3.6 Hardware and software diagnostics

report the safety mechanisms required to properly manage a multiple-fault scenario, including mitigation measures against failures making safety mechanisms ineffective. It is strongly recommended that the safety concept includes such mitigation measures, and in particular for systems operating during long periods, as they tend to accumulate errors. Indeed, fault accumulation issue has been taken into account during STM32L4 and STM32L4+ Series devices safety analysis.

Another potential source of multiple error condition is the accumulation of permanent failures during power-off periods. Indeed, if the end system is not powered, no safety mechanism are active and so able to early detect the insurgence of such failures. To mitigate this potential issue, it is strongly recommended to execute all periodic safety mechanism at each system power-up; this measure guarantees a fresh system start with a fault-free hardware. This recommendation is given for periodic safety mechanisms rated as "++" (highly recommended) in the Device safety concept, and mainly for the most relevant ones in term of failure distribution: CPU_SM_0,

FLASH_SM_0, RAM_SM_0. This startup execution is strongly recommended regardless the safety functions mode of operations and/or the value of PST.

Analysis of dependent failures

The analysis of dependent failures is important for microcontroller and microprocessor devices. The main subclasses of dependent failures are CCFs . Their analysis is ruled by IEC 61508:2 annex E, which lists the design requirements to be verified to allow the use of on-chip redundancy for integrated circuits with one common semiconductor substrate.

As there is no on-chip redundancy on STM32L4 and STM32L4+ Series devices, the CCF quantification through the βIC computation method - as required by Annex E.1, item i - is not required. Note that, in the case of 1oo2 safety architecture implementation, End user is required to evaluate the β and βD parameters (used in PFH computation) that reflect the common cause factors between the two channels.

The Device architecture and structures can be potential sources of dependent failures. These are analyzed in the following sections. The safety mechanisms referred to are described in

Section 3.6 Hardware and software diagnostics

.

Power supply

•

•

Power supply is a potential source of dependent failures, because any alteration can simultaneously affect many modules, leading to not-independent failures. The following safety mechanisms address and mitigate those dependent failures:

VSUP_SM_1: detection of abnormal value of supply voltage;

VSUP_SM_2: the independent watchdog is different from the digital core of the MCU , and this diversity helps to mitigate dependent failures related to the main supply alterations. As reported in VSUP_SM_2 description, separate power supply for IWDG or/and the adoption of an external watchdog (CPU_SM_5) increase such diversity.

The adoption of such safety mechanisms is therefore highly recommended despite their minor contribution to the safety metrics to reach the required safety integrity level. Refer to

Section 3.6.6 Power controller (PWR) for the

detailed safety mechanism descriptions.

Clock

System clocks are a potential source of dependent failures, because alterations in the clock characteristics

(frequency, jitter) can affect many parts, leading to not-independent failures. The following safety mechanisms address and mitigate such dependent failures:

• CLK_SM_1: the clock security system is able to detect hard alterations (stop) of system clock and activate the adequate recovery actions.

• CLK_SM_2: the independent watchdog has a dedicated clock source. The frequency alteration of the system clock leads to the watchdog window violations by the triggering routine on Application software , leading to the MCU reset by watchdog.

UM2305 - Rev 10 page 93/110

4.2.3

Note:

4.2.4

UM2305

Analysis of dependent failures

The adoption of such safety mechanism is therefore highly recommended despite their minor contribution to the safety metrics to reach the required safety integrity level. Refer to

Section 3.6.7 Reset and clock controller

(RCC)

for detailed safety mechanisms description.

•

DMA

•

•

The DMA function can be involved in data transfers operated by most of the peripherals. Failures of DMA can interfere with the behavior of the system peripherals or Application software , leading to dependent failures. The adoption of the following safety mechanisms is therefore highly recommended (refer to

Section 3.6.11 Direct memory access controller (DMA/ DMA2D/ DMAMUX))

for description):

DMA_SM_0

DMA_SM_1

DMA_SM_2

Only DMA_SM_0 must be implemented if DMA is not used for data transfer.

Internal temperature

The abnormal increase of the internal temperature is a potential source of dependent failures, as it can affect many MCU

parts. The following safety mechanism mitigates this potential effect (refer to Section 3.6.6 Power controller (PWR) for description):

VSUP_SM_3: the internal temperature read and check allows the user to quickly detect potential risky conditions before they lead to a series of internal failures.

UM2305 - Rev 10 page 94/110

5

UM2305

List of evidences

List of evidences

A safety case database stores all the information related to the safety analysis performed to derive the results and conclusions reported in this safety manual.

The safety case database is composed of the following:

• safety case with the full list of all safety-analysis-related documents

•

•

•

STMicroelectronics' internal FMEDA tool database for the computation of safety metrics, including estimated and measured values safety report, a document that describes in detail the safety analysis executed on STM32L4 and STM32L4+

Series devices and the clause-by-clause compliance to IEC 61508

STMicroelectronics' internal fault injection campaign database including tool configuration and settings, fault injection logs and results

As these materials contain STMicroelectronics' confidential information, they are only available for the purpose of audit and inspection by authorized bodies, without being published, which conforms to Note 2 of IEC 61508:2,

7.4.9.7.

UM2305 - Rev 10 page 95/110

6

6.1

6.1.1

UM2305

Change impact analysis for other safety standards

Change impact analysis for other safety standards

The safety analysis reported in this safety manual is executed according to the IEC 61508 safety norm. This section reports the outcome of a change impact analysis with respect to different safety standards. For each new safety standard addressed, the following items are considered:

•

•

Differences in the suggested hardware architecture (architectural categories), and how to map to safety architectures of IEC 61508.

Differences in the safety integrity level definitions and metrics computation methods, and how to recompute and judge the safety performances of the devices according to the new standard.

The safety standards examined within this change impact analysis are:

• ISO 13849-1:2015, ISO13849-2:2012 – Safety of machinery and Safety-related parts of control systems ,

•

•

IEC 62061:2005+AMD1:2012+AMD2:2015 – Safety of machinery and Functional safety of safety-related electrical, electronic and programmable electronic control systems ,

IEC 61800-5-2:2016 – Adjustable speed electrical power drive systems – Part 5-2: Safety requirements –

Functional

ISO 13849-1:2015, ISO 13849-2:2012

ISO 13849-1 is a type B1 standard. It provides a guideline for the development of

Safety-related parts of machinery control systems (SRP/CS) including programmable electronics, hardware and software.

ISO 13849 architectural categories

ISO 13849-1:2015 reports in section 4.4, Figure 4 a typical safety function diagrammatic presentation. Under the assumption that Compliant item as defined in section is used to implement the b (logic), the equivalence of the

ISO 13849 representation with the one in

Section 3.2.1

is evident. The mapping of ISO 13849 architectures with

the one described in Section 3 is possible.

ISO 13849-1:2015 in section §6 defines in details five different categories. The following table lists for each category the possible implementation by one of the IEC 61508 compliant architectures described in this manual

in Section 3 . It is worth to note that for each category, the achievable

PL is decided by the specific values of

diagnostic coverage (DC)

avg

and

mean time to dangerous failure (MTTFd) (refer to

Section 6.1.2 for details on

computations).

UM2305 - Rev 10 page 96/110

UM2305

ISO 13849-1:2015, ISO 13849-2:2012

Table 154. ISO 13849 architectural categories

ISO13849-1:2015

Category Clause

Link to IEC61508-compliant safety architectures

Notes/constraints

B

1

2

3

6.2.3

6.2.4

6.2.5

6.2.6

Possible with 1oo1 architecture

Not recommended

Possible with 1oo1 architecture (external

WDT is mandatory)

Possible with 1oo2 architecture +

DUAL_SM_0

No requirements for MTTFd and DC avg are given for category B, anyway it is recommended to follow safety manual recommendation.

Category not recommended because of the

NOTE1 in IEC13849-1, section §6.2.4.

The adoption of external WDT (CPU_SM_5) acting as TE is mandatory.

Constraints on DC avg

and MTTFd can be satisfied but computations are needed

(1) .

Constraints on CCF

are satisfied (2)

.

Constraints on DC avg

and MTTFd can be satisfied but computations are needed

(1)

Constraints on CCF

are satisfied (2)

.

4 6.2.7

Possible with 1oo2 architecture +

DUAL_SM_0

Implementation of DUAL_SM_0 scheme is mandatory to mitigate fault accumulation.

Constraints on DC avg

and MTTFd can be satisfied but computations are needed

(1)

Constraints on CCF

are satisfied (2)

.

1. Computations related to DC avg

and MTTFd can involve also other components than Device because used in the safety function implementation (sensors, actuators, etc). The figures need therefore to be evaluated at system level – refer to

Section 6.1.2 for the correct interpretation of Device data in such a computation.

2. CCF additional requirements expressed in ISO13849-1, Annex F table F.1 are basically enforcing the system implementation and therefore outside the scope of this manual. It is worth to note that the complete safety analysis resulting as output of the IEC61508 compliance activity (this manual) helps to claim the score for item #4 in Table F.1.

6.1.2

Note:

ISO 13849 safety metrics computation

Appendix C of ISO 13849 presents tables of standardized MTTFd for the various electric or electronics components. However, table C.3 in ISO 13849 points to ICs manufacturer’s data while attempting to classify

MTTFd for programmable ICs. As a consequence, safety analysis results of this Safety Manual can be re-mapped in ISO 13849 domain, because even computed for IEC 61508 they are definitely more and more accurate in the definition of dangerous failures identification.

When for a certain component PFH << 1 it can be assumed that MTTFd = 1 / PFH .

It is worth to note that according ST methodology, FMEDA data includes failure rate related to transient faults without any assumption about their potential partial safeness. Because of this assumption, PFH values in Device

FMEDA leads to very conservative values for computed MTTFd .

In ISO 13849-1 the DC for each single component has the same meaning of the IEC 61508 metric; results of this safety manual and related FMEA/FMEDA can therefore be reused. However, this standard defines the concept of DC avg

applicable to the whole SRP/CS in the form of the equation defined in Annex E, formula E.1, where the contribution of each part of the control system is weighted with respect to MTTFd of the various subsystems of the channel. End user is therefore responsible for the computations of the overall DC avg

.

The standard denies any possibility of fault exclusion while calculating DC avg

(ISO13849-2 Tab.D.21 no exclusion allowed), which is also the assumption of Device analysis documented in this safety manual.

Each architectural solution analyzed in this safety manual results in PFH values producing high MTTFd.

UM2305 - Rev 10 page 97/110

6.2

6.2.1

6.2.2

UM2305

IEC 62061:2005+AMD1:2012+AMD2:2015

IEC 62061:2005+AMD1:2012+AMD2:2015

This standard is applicable in the specification, design and verification or validation of

safety-related electrical control systems (SRECS) of machines.

SRECS is the electrical or electronics control system of the machine which failure could lead to reduction or loss of safety. SRECS implements a

safety-related control function (SRCF)

to prevent any increase of the risk.

Because STM32xx has been classified as Type B according IEC61508 (refer to Section 3.2.2

), it must be considered as a “complex component” in IEC62061 definition.

IEC 62061 architectural categories

IEC 62061 defines a set of basic system architectures to be used for the design of safety-related electrical control systems ( SRECS ) implementing their SRCF s. The following table lists for each system architecture the possible implementation/mapping by/to one of the IEC 61508 compliant architectures described in this manual in

Section 3

.

Safety metrics related to STM32xx MCU can be reused from IEC61508 analysis (refer to Device FMEDA), while their combination with the ones related to other devices included in the system is full responsibility of End user .

Table 155. IEC 62061 architectural categories

IEC 62061

Architecture Clause

A

B

Link to IEC61508-compliant safety architectures

6.7.8.2.2

6.7.8.2.3

Equivalent of 1oo1, with HFT = 0, no diagnostic function(s) implemented.

Equivalent to 1oo2 with HFT = 1, a single failure does not lead to the loss of SRCF .

No diagnostic function(s) implemented.

C

D

6.7.8.2.4

Equivalent of 1oo1 architecture.

6.7.8.2.5

Equivalent of 1oo2 architecture.

Notes/constraints

-

-

All requirements related to 1oo1 architecture must be implemented.

All requirements related to 1oo2 architecture must be implemented.

IEC 62061 safety metrics computation

The failure rate (λ) in T is the smaller proof test interval or the life time of the subsystem.

As seen in ISO 13849, the approximation §6.7.8.2.1 NOTE2 is still considered valid, hence

λ = 1 / MTTFd , where it is assumed that 1 >> λ x T.

So, as PFH

D

= λ

D

x 1h, so PFD = 1 / MTTFd .

Safety analysis executed for STM32L4 and STM32L4+ Series devices according to IEC 61508 is more and more accurate for the definition of dangerous failure identifications that can be re-mapped in IEC 62061 domain. Thus, values of λ, PFH and SFF that are reported in the FMEDA

(refer to Section 4 Safety results ), are still valid and

can be reused.

For evaluation of CCF in basic architectures with HFT = 1, End user can rely to what reported in

Section 4.2 Analysis of dependent failures , and to the guidelines included in IEC 61508:2010-6 Annex D.

Alternatively, End user can apply the simplified approach from the standard (refer to Annex F) to calculate the β factor value to be used in formulas for PFD .

UM2305 - Rev 10 page 98/110

6.3

6.3.1

6.3.2

UM2305

IEC 61800-5-2:2016

IEC 61800-5-2:2016

The scope of this standard is the functional safety of adjustable speed electric drive systems.

IEC 61800 architectural categories

Because IEC 61800 definitions for HFT and for architectures are equivalent to the ones of IEC61508, the remapping is straightforward.

The STM32xx MCU is considered as Type B for the consideration reported in

Section 3.2.2 .

IEC 61800 safety metrics computation

The PFH of a safety function performed by PDS(SR) is evaluated by the application of IEC 61508-2. The strong link with the norm IEC 61508 is reflected also by the adoption in IEC 61800-5-2 of the same relevant metrics

PFH , and SFF. So, results of this safety manual (and related FMEA and FMEDA ) can be re-mapped in IEC 61800 domain.

UM2305 - Rev 10 page 99/110

UM2305

Revision history

Date

02-Nov-2017

13-Nov-2017

24-Apr-2018

08-Aug-2018

11-Oct-2018

13-Nov-2018

24-Jun-2019

22-Jul-2020

Revision

1

2

3

4

5

6

7

8

Table 156. Document revision history

Changes

Initial release.

•

•

•

•

Updated:

Section: Advanced, general and low-power timers TIM1/2/3/4/5/8/15/16/17

LPTIM1/2.

Table : ATIM_SM_0.

Table: List of safety mechanisms.

Table: IEC 60730 required safety mechanism for Class B/C compliance.

•

•

•

•

•

•

Updated:

Reference of “IEC 13849” is updated to “ISO 13549” in the whole document.

Section: Reference normative.

Section Appendix A: Change impact analysis for other safety standards.

Name of Section A.2: IEC 62061:2005/AMD1:2012.

Section A.2.2: Safety metrics computation.

Figure: SRECS high-level diagram.

•

Deleted:

Section A.4: IEC 60730-1:2010.

Updated Section: Terms and abbrevations.

•

•

•

•

•

•

•

Updated:

Document scope to include STM32L4+ Series information.

Title of Section: Direct memory access controller (DMA/DMA2D/DMAMUX).

Section: RTC_SM_2.

Title of Section: Quad-SPI interface (QUADSPI) and Octo-SPI interface

(OCTOSPI).

Title of Section: LCD-TFT display controller (LTDC).

Section: Conditions of use.

Section: Change impact analysis for other safety standards and its subsections.

•

•

•

•

Added:

Section: DSI Host (DSIHOST).

Section: Chrom-GRC TM (GFXMMU).

Section: Voltage reference buffer (VREFBUF).

Section Inter-processor communication controller (IPCC).

•

•

Updated:

Section: Voltage reference buffer (VREFBUF).

Section: List of safety mechanisms.

•

Deleted:

Section: Inter-processor communication controller (IPCC).

•

•

•

Updated:

Section: Functional safety documentation framework.

Section: Reference normative.

Section: Change impact analysis for other safety standards.

•

Deleted:

Section A.4 ISO 26262:2010.

General update.

Former appendix changed into

Section 6 Change impact analysis for other safety standards , with the removal of

ISO 13849 work products , IEC 62061 work products , and

IEC 61800 work products subsections.

UM2305 - Rev 10 page 100/110

UM2305

Date

17-Dec-2020

23-Jun-2021

Revision

9

10

Changes

•

•

•

•

•

•

Updated:

Section 3.6.1 Arm® Cortex®-M4 CPU CPU_SM_0.

Section 3.6.4 Embedded Flash memory

FLASH_SM_7.

Section 3.6.28 HASH processor (HASH)

AES_SM_1.

HASH_SM_1.

Section 3.6.30 Advanced encryption standard hardware accelerator (AES)

Section 3.6.33 Real-time clock module (RTC) RTC_SM_2.

Section 3.7 Conditions of use .

Updated

Section 3.7 Conditions of use

CoU_1.

UM2305 - Rev 10 page 101/110

UM2305

Glossary

Glossary

Application software within the software executed by

Device , the part that ensures functionality of End user 's application and integrates safety functions

CCF common cause failure

CM continuous mode

Compliant item any item subject to claim with respect to the clauses of IEC 61508 series of standards

COTS commercial off-the-shelf

CoU conditions of use

CPU central processing unit

CRC cyclic redundancy check

DC diagnostic coverage

Device depending on context, any single or all of the silicon products

DMA direct memory access

DTI diagnostic test interval

ECM engine control module

ECU electronic control unit

End user individual person or company who integrates Device in their application, such as an electronic control board

EUC equipment under control

FIT failure in time

FMEA failure mode effect analysis

FMEDA failure mode effect diagnostic analysis

HD high-demand

HFT hardware fault tolerance

HW hardware

ITRS international technology roadmap for semiconductors

LD low-demand

MCU microcontroller unit

MPU memory protection unit

MTBF mean time between failures

MTTFd mean time to dangerous failure

PDS(SR) safety-related power drive system

PEc programmable electronics - core

PEd programmable electronics - diagnostic

PFD probability of dangerous failure on demand

PFH probability of failure per hour

PL performance level

PST process safety time

SFF safe failure fraction

SIL safety integrity level

SILCL safety integrity level claim limit

SRCF safety-related control function

SRECS safety-related electrical control systems

SRP/CS safety-related parts of machinery control systems

UM2305 - Rev 10 page 102/110

UM2305

Contents

Contents

1 About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.1

Purpose and scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2

Normative references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3

Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Device development process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Reference safety architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1

Safety architecture introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2

Compliant item. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2.1

3.2.2

3.2.3

3.2.4

Definition of Compliant item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Safety functions performed by Compliant item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Reference safety architectures - 1oo1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Reference safety architectures - 1oo2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3

Safety analysis assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3.1

Safety requirement assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4

Electrical specifications and environment limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.5

Systematic safety integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6

Hardware and software diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6.1

3.6.2

3.6.3

3.6.4

3.6.5

3.6.6

3.6.7

Arm ® Cortex ® -M4 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

System bus architecture/BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Firewall (FW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power controller (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.6.8

3.6.9

General-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Debug system or peripheral control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.6.10

System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.6.11

Direct memory access controller (DMA/ DMA2D/ DMAMUX)). . . . . . . . . . . . . . . . . . . . . . 35

3.6.12

Chrom-Art Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.6.13

Chrom-GRC™ (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

UM2305 - Rev 10 page 103/110

UM2305

Contents

3.6.14

Extended interrupt and events controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.6.15

Cyclic redundancy-check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.6.16

Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.6.17

Quad-SPI interface and Octo-SPI interface (QUADSPI/OCTOSPI). . . . . . . . . . . . . . . . . . 44

3.6.18

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6.19

Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.6.20

Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.6.21

Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.6.22

Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.6.23

Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.6.24

Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.6.25

LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.6.26

DSI Host (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.6.27

Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.6.28

HASH processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.6.29

True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.6.30

Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . 60

3.6.31

Advanced, general, and low-power timer (TIM1/2/3/4/5/8/15/16/17 LPTIM1/2) . . . . . . . . . 61

3.6.32

Basic timers (TIM6/7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.6.33

Real-time clock module (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.6.34

Inter-integrated circuit (I2C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.6.35

Universal synchronous/asynchronous receiver/transmitter and low power universal asychronous receiver/transmitter (USART1/2/3/4/5/6/7/8 and LPUART). . . . . . . . . . . . . . 69

3.6.36

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.6.37

Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.6.38

Single Wire Protocol Master Interface (SWPMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.6.39

SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.6.40

Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.6.41

Universal serial bus full-speed device interface (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . 80

3.6.42

Part separation (no interference). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.7

Conditions of use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4 Safety results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

4.1

Random hardware failure safety results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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UM2305

Contents

4.1.1

4.1.2

4.1.3

Safety analysis result customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

General requirements for freedom from interferences (FFI) . . . . . . . . . . . . . . . . . . . . . . . 92

Notes on multiple-fault scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.2

Analysis of dependent failures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.2.1

4.2.2

4.2.3

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.2.4

Internal temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5 List of evidences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

6 Change impact analysis for other safety standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

6.1

ISO 13849-1:2015, ISO 13849-2:2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.1.1

6.1.2

ISO 13849 architectural categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

ISO 13849 safety metrics computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.2

IEC 62061:2005+AMD1:2012+AMD2:2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.2.1

6.2.2

IEC 62061 architectural categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

IEC 62061 safety metrics computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.3

IEC 61800-5-2:2016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.3.1

6.3.2

IEC 61800 architectural categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

IEC 61800 safety metrics computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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List of tables

List of tables

Table 1. Document sections versus IEC 61508-2 Annex D safety requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. SS1 and SS2 safe state details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. CPU_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. CPU_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. CPU_SM_2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. CPU_SM_3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. CPU_SM_4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. CPU_SM_5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 9. CPU_SM_6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 10. CPU_SM_7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 11. CPU_SM_8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12. MPU_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 13. MPU_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14. BUS_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15. BUS_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 16. RAM_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 17. RAM_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 18. RAM_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 19. RAM_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 20. RAM_SM_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 21. RAM_SM_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 22. RAM_SM_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 23. FLASH_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 24. FLASH_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 25. FLASH_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 26. FLASH_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 27. FLASH_SM_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 28. FLASH_SM_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 29. FLASH_SM_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 30. FLASH_SM_7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 31. FLASH_SM_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 32. FLASH_SM_9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 33. FWR_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 34. VSUP_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 35. VSUP_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 36. VSUP_SM_2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 37. VSUP_SM_3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 38. VSUP_SM_4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 39. VSUP_SM_5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 40. CLK_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 41. CLK_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 42. CLK_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 43. CLK_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 44. GPIO_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 45. GPIO_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 46. GPIO_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 47. GPIO_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 48. DBG_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 49. LOCK_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 50. SYSCFG_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 51. DIAG_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 52. DMA_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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List of tables

Table 53. DMA_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 54. DMA_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 55. DMA_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 56. DMA_SM_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 57. DMA2D_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 58. DMA2D_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 59. DMA2D_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 60. GFX_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 61. GFX_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 62. NVIC_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 63. NVIC_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 64. CRC_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 65. FSMC_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 66. FSMC_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 67. FSMC_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 68. FSMC_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 69. QSPI_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 70. QSPI_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 71. QSPI_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 72. ADC_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 73. ADC_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 74. ADC_SM_2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 75. ADC_SM_3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 76. ADC_SM_4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 77. DAC_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 78. DAC_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 79. VREF_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 80. VREF_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 81. COMP_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 82. COMP_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 83. COMP_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 84. COMP_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 85. COMP_SM_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 86. AMP_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 87. DFS_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 88. DFS_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 89. DFS_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 90. DFS_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 91. DCMI_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 92. DCMI_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 93. LCD_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 94. LCD_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 95. DSI_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 96. DSI_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 97. TSC_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 98. TSC_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 99. TSC_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 100. HASH_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 101. HASH_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 102. RNG_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 103. RNG_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 104. AES_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 105. AES_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 106. AES_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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UM2305

List of tables

Table 107. ATIM_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 108. ATIM_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 109. ATIM_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 110. ATIM_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 111. ATIM_SM_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 112. GTIM_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 113. GTIM_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 114. RTC_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 115. RTC_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 116. RTC_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 117. RTC_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 118. IIC_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 119. IIC_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 120. IIC_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 121. IIC_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 122. IIC_SM_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 123. UART_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 124. UART_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 125. UART_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 126. UART_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 127. SPI_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 128. SPI_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 129. SPI_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 130. SPI_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 131. SPI_SM_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 132. SAI_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 133. SAI_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 134. SAI_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 135. SWPMI_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 136. SWPMI_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 137. SWPMI_SM_2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 138. SWPMI_SM_3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 139. SDIO_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 140. SDIO_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 141. SDIO_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 142. CAN_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 143. CAN_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 144. CAN_SM_2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 145. USB_SM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 146. USB_SM_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 147. USB_SM_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 148. USB_SM_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 149. FFI_SM_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 150. FFI_SM_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 151. List of safety recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 152. Overall achievable safety integrity levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 153. List of general requirements for FFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 154. ISO 13849 architectural categories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 155. IEC 62061 architectural categories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 156. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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UM2305

List of figures

List of figures

Figure 1. STMicroelectronics product development process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. STM32 as Compliant item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. 1oo1 reference architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. 1oo2 reference architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Allocation and target for STM32 PST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

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UM2305

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