The STM32F411xC/xE datasheet should be read in conjunction with RM0383 reference manual which is available from the STMicroelectronics website www.st.com

. It includes all information concerning Flash memory programming.

For information on the Cortex

-M4 core, please refer to the Cortex

-M4 programming manual (PM0214) available from www.st.com

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2 Description

Description

The STM32F411 X C/ X E devices are based on the high-performance Arm ® Cortex ® -M4 32bit RISC core operating at a frequency of up to 100 MHz. The Cortex ® -M4 core features a

Floating point unit (FPU) single precision which supports all Arm single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F411xC/xE belongs to the STM32 Dynamic Efficiency

™

product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching.

The STM32F411xC/xE incorporate high-speed embedded memories (up to 512 Kbytes of

Flash memory, 128 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB bus and a 32-bit multi-AHB bus matrix.

All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers including one PWM timer for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces.

• Up to three I

• Five SPIs

• Five I

Ss out of which two are full duplex. To achieve audio class accuracy, the I

S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.

• Three USARTs

• SDIO interface

• USB 2.0 OTG full speed interface

The STM32F411xC/xE operate in the - 40 to + 125 °C temperature range from a 1.7 (PDR

OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

These features make the STM32F411xC/xE microcontrollers suitable for a wide range of applications:

• Motor drive and application control

• Medical equipment

• Industrial applications: PLC, inverters, circuit breakers

• Printers, and scanners

• Alarm systems, video intercom, and HVAC

• Home audio appliances

• Mobile phone sensor hub

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Description STM32F411xC STM32F411xE

Package

Table 2. STM32F411xC/xE features and peripheral counts

Peripherals STM32F411xC STM32F411xE

256 512 Flash memory in Kbytes

SRAM in Kbytes System

Timers

Generalpurpose

Advancedcontrol

SPI/ I

Communication interfaces

USART

SDIO

USB OTG FS

GPIOs

12-bit ADC

Number of channels

Maximum CPU frequency

Operating voltage

Operating temperatures

128

36 50 81 36 50 81

10 16 10

100 MHz

1.7 to 3.6 V

Ambient temperatures: - 40 to +85 °C / - 40 to + 105 °C/ - 40 to + 125 °C

WLCSP49

UFQFPN48

5/5 (2 full duplex)

Junction temperature: – 40 to + 130 °C

LQFP64

UFBGA100

LQFP100

WLCSP49

UFQFPN48

LQFP64

UFBGA100

LQFP100

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STM32F411xC STM32F411xE

2.1 Compatibility with STM32F4 Series

Description

The STM32F411xC/xE are fully software and feature compatible with the STM32F4 series

(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)

The STM32F411xC/xE can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board.

Figure 1. Compatible board design for LQFP100 package

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Description STM32F411xC STM32F411xE

Figure 2. Compatible board design for LQFP64 package

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DocID026289 Rev 7

STM32F411xC STM32F411xE

Figure 3. STM32F411xC/xE block diagram

Description

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1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 100 MHz.

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15/149

Functional overview STM32F411xC STM32F411xE

3.1 Arm

®

Cortex

SRAM

®

-M4 with FPU core with embedded Flash and

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

Note:

The STM32F411xC/xE devices are compatible with all Arm tools and software.

Figure 3 shows the general block diagram of the STM32F411xC/xE.

Cortex

-M4 with FPU is binary compatible with Cortex

-M3.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm ® Cortex advantage of the Arm

-M4 with FPU processors. It balances the inherent performance

Cortex

-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor full 105 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the -bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 100 MHz.

3.3 Batch Acquisition mode (BAM)

The Batch acquisition mode allows enhanced power efficiency during data batching. It enables data acquisition through any communication peripherals directly to memory using the DMA in reduced power consumption as well as data processing while the rest of the system is in low-power mode (including the flash and ART). For example in an audio system, a smart combination of PDM audio sample acquisition and processing from the I2S directly to RAM (flash and ART

™

stopped) with the DMA using BAM followed by some very short processing from flash allows to drastically reduce the power consumption of the application. A dedicated application note (AN4515) describes how to implement the BAM to allow the best power efficiency.

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3.4 Memory protection unit

Functional overview

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5 Embedded Flash memory

The devices embed up to 512 Kbytes of Flash memory available for storing programs and data.

To optimize the power consumption the Flash memory can also be switched off in Run or in

Sleep mode (see Section 3.18: Low-power modes ). Two modes are available: Flash in Stop

mode or in DeepSleep mode (trade off between power saving and startup time, see

Table 34: Low-power mode wakeup timings (1)

). Before disabling the Flash memory, the code must be executed from the internal RAM.

One-time programmable bytes

A one-time programmable area is available with 16 OTP blocks of 32 bytes. Each block can be individually locked.

(Additional information can be found in the product reference manual.)

3.6 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

All devices embed:

• 128 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states

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Functional overview STM32F411xC STM32F411xE

3.8 Multi-AHB matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 4. Multi-AHB matrix

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DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

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STM32F411xC STM32F411xE

The DMA can be used with the main peripherals:

• SPI and I

• I 2 C

• USART

• General-purpose, basic and advanced-control timers TIMx

• SD/SDIO/MMC/eMMC host interface

• ADC

Functional overview

3.10 Nested vectored interrupt controller (NVIC)

and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M4 with FPU.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

The external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected to the 16 external interrupt lines.

3.12 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

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Functional overview STM32F411xC STM32F411xE buses is 100 MHz while the maximum frequency of the high-speed APB domains is

100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I 2 S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

At startup, boot pins are used to select one out of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by using USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12) through

DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),

SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).

For more detailed information on the bootloader, refer to Application Note: AN2606, STM32 microcontroller system memory boot mode .

• VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor

(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and NRST pins.

• V

SSA

, V

DDA

= 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. V

DDA

and V decoupling technique.

SSA

must be connected to V

and V

, respectively, with

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

Refer to Figure 17: Power supply scheme for more details.

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STM32F411xC STM32F411xE Functional overview

This feature is available for V

operating voltage range 1.8 V to 3.6 V.

The internal power supply supervisor is enabled by holding PDR_ON high.

The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes.

The devices remain in reset mode when V

BOR

is below a specified threshold, V

, without the need for an external reset circuit.

POR/PDR

The devices also feature an embedded programmable voltage detector (PVD) that monitors the V

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V higher than the V

PVD

DDA

drops below the V

PVD

threshold and/or when V

DDA

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to low.

An external power supply supervisor should monitor V

DD mode when V

and should set the device in reset

is below 1.7 V. NRST should be connected to this external power supply

supervisor. Refer to Figure 5: Power supply supervisor interconnection with internal reset

OFF .

Figure 5. Power supply supervisor interconnection with internal reset OFF (1)

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1. The PRD_ON pin is only available on the WLCSP49 and UFBGA100 packages.

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Functional overview STM32F411xC STM32F411xE

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no longer supported:

• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.

• The brownout reset (BOR) circuitry must be disabled.

• The embedded programmable voltage detector (PVD) is disabled.

• V

BAT

functionality is no more available and VBAT pin should be connected to V

The regulator has four operating modes:

• Regulator ON

– Main regulator mode (MR)

– Low power regulator (LPR)

– Power-down

• Regulator OFF

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.

There are three power modes configured by software when the regulator is ON:

• MR is used in the nominal regulation mode (With different voltage scaling in Run)

In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.

• LPR is used in the Stop modes

The LP regulator mode is configured by software when entering Stop mode.

• Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost.

Depending on the package, one or two external ceramic capacitors should be connected on the V

CAP_1 and V

CAP_2 pins. The V

CAP_2

pin is only available for the LQFP100 and

UFBGA100 packages.

All packages have the regulator ON feature.

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The Regulator OFF is available only on the UFBGA100, which features the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through V

CAP_1

and V

CAP_2

pins.

Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to

Table 14: General operating conditions

The two 2.2 µF V

CAP ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to

Figure 17: Power supply scheme

DocID026289 Rev 7

STM32F411xC STM32F411xE Functional overview

When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain.

In regulator OFF mode, the following features are no more supported:

• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin.

• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.

Figure 6. Regulator OFF

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The following conditions must be respected:

• V

should always be higher than V between power domains.

CAP_1

and V

CAP_2 to avoid current injection

• If the time for V

CAP_1

and V and V

CAP_2 reach V

CAP_2 to reach V

12 minimum value is faster than the time for

to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V

CAP_1 minimum value and until V

reaches 1.7 V (see Figure 7

• Otherwise, if the time for V

CAP_1 than the time for V

Figure 8 ).

and V

CAP_2 to reach V

12 minimum value is slower

to reach 1.7 V, then PA0 could be asserted low externally (see

• If V

CAP_1

and V

CAP_2

go below V

12 minimum value and V reset must be asserted on PA0 pin.

is higher than 1.7 V, then a

The minimum value of V

12 depends on the maximum frequency targeted in the application

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Functional overview STM32F411xC STM32F411xE

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CAP_1

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CAP_2 stabilization

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STM32F411xC STM32F411xE Functional overview

3.16.3 Regulator ON/OFF and internal power supply supervisor availability

Table 3. Regulator ON/OFF and internal power supply supervisor availability

Package Regulator ON Regulator OFF

Power supply supervisor ON

Power supply supervisor OFF

UFQFPN48 Yes No Yes

WLCSP49 Yes No

Yes

PDR_ON set to VDD

LQFP64

LQFP100

UFBGA100

Yes No

Yes

BYPASS_REG set to

VSS

Yes

BYPASS_REG set to

VDD

Yes

PDR_ON set to VDD

1. Refer to Section 3.15: Power supply supervisor

Yes

PDR_ON external control

(1)

Yes

PDR_ON external control (1)

The backup domain includes:

• The real-time clock (RTC)

• 20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC features a reference clock detection, a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from

Stop and Standby modes. The sub-seconds value is also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power

RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The backup registers are 32-bit registers used to store 80 bytes of user application data when V

power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see

Section 3.18: Low-power modes ).

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

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Functional overview STM32F411xC STM32F411xE

The RTC and backup registers are supplied through a switch that is powered either from the

supply when present or from the V

BAT

pin.

The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

To further reduce the power consumption, the Flash memory can be switched off before entering in Sleep mode. Note that this requires a code execution from the RAM.

• Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The devices can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/ tamper/ time stamp events).

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the backup domain when selected.

The devices exit the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm/ wakeup/ tamper/time stamp event occurs.

Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

3.19 V

BAT

operation

The VBAT pin allows to power the device V

BAT super-capacitor, or from V present.

domain from an external battery, an external when no external battery and an external super-capacitor are

Note:

BAT

operation is activated when V

is not present.

The VBAT pin supplies the RTC and the backup registers.

When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from V

BAT

Reset OFF), the V

BAT to V

operation. When PDR_ON pin is not connected to V

(internal

functionality is no more available and VBAT pin should be connected

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STM32F411xC STM32F411xE Functional overview

3.20 Timers and watchdogs

The devices embed one advanced-control timer, seven general-purpose timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control and general-purpose timers.

Timer type

Advanced

-control

General purpose

Timer

Table 4. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max. interface clock

(MHz)

Max. timer clock

(MHz)

TIM1

TIM2,

TIM5

TIM3,

TIM4

TIM9

TIM10,

TIM11

16-bit

32-bit

16-bit

Up,

Down,

Up/down

Any integer between 1 and

65536

Up,

Down,

Up/down

Any integer between 1 and

65536

Up,

Down,

Up/down

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Yes

100

The advanced-control timer (TIM1) can be seen as three-phase PWM generators multiplexed on 4 independent channels. It has complementary PWM outputs with programmable inserted dead times. It can also be considered as a complete generalpurpose timer. Its 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge- or center-aligned modes)

• One-pulse mode output

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Functional overview STM32F411xC STM32F411xE

If configured as standard 16-bit timers, it has the same features as the general-purpose

TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability (0-

100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

TIM1 supports independent DMA request generation.

There are seven synchronizable general-purpose timers embedded in the

STM32F411xC/xE (see

Table 4

for differences).

• TIM2, TIM3, TIM4, TIM5

The STM32F411xC/xE devices are 4 full-featured general-purpose timers: TIM2, TIM5,

TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature four independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 15 input capture/output compare/PWMs.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timer TIM1 via the Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

• TIM9, TIM10 and TIM11

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

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This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

• A 24-bit downcounter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source.

circuit interface (I

2

C)

Up to three I 2 C bus interfaces can operate in multimaster and slave modes. They can support the standard (up to 100 kHz) and fast (up to 400 kHz) modes. The I2C bus frequency can be increased up to 1 MHz. For more details about the complete solution, please contact your local ST sales representative.They also support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

The devices also include programmable analog and digital noise filters (see

Table 5

Pulse width of suppressed spikes

Table 5. Comparison of I2C analog and digital filters

Analog filter Digital filter

≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks

(USART)

The devices embed three universal synchronous/asynchronous receiver transmitters

(USART1, USART2 and USART6).

These three interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 12.5 Mbit/s. The USART2 interface communicates at up to

6.25 bit/s.

USART1 and USART2 also provide hardware management of the CTS and RTS signals,

Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.

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Functional overview STM32F411xC STM32F411xE

USART name

Standard features

Modem

(RTS/CTS)

Table 6. USART feature comparison

LIN

SPI master irDA

Smartcard

(ISO 7816)

Max. baud rate in Mbit/s

(oversampling by 16)

Max. baud rate in Mbit/s

(oversampling by 8)

APB mapping

USART1

USART2

USART6

N.A

6.25

3.12

6.25

12.5

6.25

12.5

APB2

(max.

100 MHz)

APB1

(max.

50 MHz)

APB2

(max.

100 MHz)

3.23 Serial peripheral interface (SPI)

The devices feature five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and

SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the

DMA controller.

The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.

3.24 Inter-integrated sound (I

2

S)

Five standard I 2 S interfaces (multiplexed with SPI1 to SPI5) are available.They can be operated in master or slave mode, in simplex communication modes and full duplex for I2S2 and I2S3 and can be configured to operate with a 16-/32-bit resolution as an input or output channel. All the I2Sx audio sampling frequencies from 8 kHz up to 192 kHz are supported.

When either or both of the I 2 S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

All I 2 Sx can be served by the DMA controller.

3.25 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I

S application. It allows to achieve error-free I

S sampling clock accuracy without compromising on the CPU performance.

The PLLI2S configuration can be modified to manage an I

S sample rate change without disabling the main PLL (PLL) used for the CPU.

The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz to 192 kHz.

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In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output).

3.26 Secure digital input/output interface (SDIO)

An SD/SDIO/MMC/eMMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

3.27 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• 4 bidirectional endpoints

• 8 host channels with periodic OUT support

• HNP/SNP/IP inside (no need for any external resistor)

• For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 100 MHz.

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Functional overview STM32F411xC STM32F411xE

3.29 Analog-to-digital converter (ADC)

One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4 or TIM5 timer.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value. Refer to the reference manual for additional information.

As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

3.31 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.32 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F411xC/xE through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using any high-speed channel available. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

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STM32F411xC STM32F411xE

4 Pinouts and pin description

Pinouts and pin description

Figure 9. STM32F411xC/xE WLCSP49 pinout

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DocID026289 Rev 7

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Pinouts and pin description STM32F411xC STM32F411xE

Figure 10. STM32F411xC/xE UFQFPN48 pinout

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STM32F411xC STM32F411xE Pinouts and pin description

Figure 11. STM32F411xC/xE LQFP64 pinout

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DocID026289 Rev 7

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Pinouts and pin description STM32F411xC STM32F411xE

Figure 12. STM32F411xC/xE LQFP100 pinout

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STM32F411xC STM32F411xE Pinouts and pin description

Figure 13. STM32F411xC/xE UFBGA100 pinout

)

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3( 3%

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DocID026289 Rev 7

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Pinouts and pin description STM32F411xC STM32F411xE

Name

Pin name

Pin type

I/O structure

Notes

Alternate functions

Additional functions

Table 7. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

NRST

Input/ output pin

5 V tolerant I/O

Standard 3.3 V I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Pin number

1 B2 PE2

2 A1 PE3

3 B1 PE4

Table 8. STM32F411xC/xE pin definitions

Pin name

(function after reset)

(1)

Alternate functions Additional functions

4 C2 PE5

I/O FT -

TRACECLK,

SPI4_SCK/I2S4_CK,

SPI5_SCK/I2S5_CK,

EVENTOUT

TRACED0,

EVENTOUT

TRACED1,

SPI4_NSS/I2S4_WS,

SPI5_NSS/I2S5_WS,

EVENTOUT

TRACED2,

TIM9_CH1,

SPI4_MISO,

SPI5_MISO,

EVENTOUT

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STM32F411xC STM32F411xE Pinouts and pin description

Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

5 D2 PE6 I/O FT -

VSS

VDD

S -

E2 VBAT

PC13-

ANTI_TAMP

PC14-

OSC32_IN

PC15-

OSC32_OUT

F2 VSS

I/O FT

(2)(3)

(4)

11 G2 VDD

D7 12 F1 PH0 - OSC_IN

S -

I/O FT -

13 G1

PH1 -

OSC_OUT

S -

I/O FT -

TRACED3,

TIM9_CH2,

SPI4_MOSI/I2S4_SD,

SPI5_MOSI/I2S5_SD,

EVENTOUT

RTC_AMP1,

RTC_OUT, RTC_TS

OSC32_IN

OSC32_OUT

OSC_IN

OSC_OUT

14 H2 NRST

15 H1 PC0

16 J2 PC1

17 J3 PC2

I/O FT EVENTOUT

I/O FT -

SPI2_MISO,

I2S2ext_SD,

EVENTOUT

ADC1_10

ADC1_11

ADC1_12

E6 20

PC3

VDD

VSSA

VREF-

VREF+

VDDA

I/O FT

S -

SPI2_MOSI/I2S2_SD,

EVENTOUT

ADC1_13

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Pinouts and pin description STM32F411xC STM32F411xE

Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

PA0-WKUP

PA1

PA2

PA3

I/O TC

I/O FT

(5)

TIM2_CH1/TIM2_ET,

TIM5_CH1,

USART2_CTS,

EVENTOUT

ADC1_0, WKUP1

TIM2_CH2,

TIM5_CH2,

SPI4_MOSI/I2S4_SD,

USART2_RTS,

EVENTOUT

ADC1_1

TIM2_CH3,

TIM5_CH3,

TIM9_CH1,

I2S2_CKIN,

USART2_TX,

EVENTOUT

TIM2_CH4,

TIM5_CH4,

TIM9_CH2,

I2S2_MCK,

USART2_RX,

EVENTOUT

ADC1_2

ADC1_3

VSS S -

E3 BYPASS_REG S -

VDD

PA4

PA5

I FT EVENTOUT

I/O FT -

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

USART2_CK,

EVENTOUT

I/O FT -

TIM2_CH1/TIM2_ET,

SPI1_SCK/I2S1_CK,

EVENTOUT

PA6

PA7

I/O FT

I/O FT -

ADC1_4

ADC1_5

TIM1_BKIN,

TIM3_CH1,

SPI1_MISO,

I2S2_MCK,

SDIO_CMD,

EVENTOUT

ADC1_6

TIM1_CH1N,

TIM3_CH2,

SPI1_MOSI/I2S1_SD,

EVENTOUT

ADC1_7

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Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

25 -

K5 PC4

L5 PC5

18 26 G5 35 M5 PB0

19 27 G4 36 M6 PB1

28 G3 37

PB2

PE7

PE8

PE9

PE10

42 M9 PE11

43 L9 PE12

44 M10 PE13

45 M11 PE14

46 M12 PE15

I/O FT EVENTOUT

I/O FT -

TIM1_CH2N,

TIM3_CH3,

SPI5_SCK/I2S5_CK,

EVENTOUT

I/O FT -

TIM1_CH3N,

TIM3_CH4,

SPI5_NSS/I2S5_WS,

EVENTOUT

I/O FT EVENTOUT

ADC1_14

ADC1_15

ADC1_8

ADC1_9

BOOT1

I/O FT

I/O FT -

TIM1_ETR,

EVENTOUT

TIM1_CH1N,

EVENTOUT

TIM1_CH1,

EVENTOUT

TIM1_CH2N,

EVENTOUT

I/O FT

I/O FT -

TIM1_CH2,

SPI4_NSS/I2S4_WS,

SPI5_NSS/I2S5_WS,

EVENTOUT

TIM1_CH3N,

SPI4_SCK/I2S4_CK,

SPI5_SCK/I2S5_CK,

EVENTOUT

TIM1_CH3,

SPI4_MISO,

SPI5_MISO,

EVENTOUT

TIM1_CH4,

SPI4_MOSI/I2S4_SD,

SPI5_MOSI/I2S5_SD,

EVENTOUT

TIM1_BKIN,

EVENTOUT

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Pinouts and pin description STM32F411xC STM32F411xE

Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

21 29 E3 47 L10 PB10

K9 PB11

30 G2 48 L11 VCAP_1

31 D3 49 F12 VSS

32 F2 50 G12 VDD

25 33 E2 51 L12 PB12

26 34 G1 52 K12 PB13

27 35 F1 53 K11 PB14

28 36 E1 54 K10 PB15

55 PD8

56 K8 PD9

57 J12 PD10

58 J11 PD11

59 J10 PD12

I/O FT -

S -

I/O FT -

I/O FT

I/O FT -

I/O FT

I/O FT -

TIM2_CH3,

I2C2_SCL,

SPI2_SCK/I2S2_CK,

I2S3_MCK, SDIO_D7,

EVENTOUT

TIM2_CH4,

I2C2_SDA,

I2S2_CKIN,

EVENTOUT

TIM1_BKIN,

I2C2_SMBA,

SPI2_NSS/I2S2_WS,

SPI4_NSS/I2S4_WS,

SPI3_SCK/I2S3_CK,

EVENTOUT

TIM1_CH1N,

SPI2_SCK/I2S2_CK,

SPI4_SCK/I2S4_CK,

EVENTOUT

TIM1_CH2N,

SPI2_MISO,

I2S2ext_SD,

SDIO_D6,

EVENTOUT

RTC_50Hz,

TIM1_CH3N,

SPI2_MOSI/I2S2_SD,

SDIO_CK,

EVENTOUT

TIM4_CH1,

EVENTOUT

RTC_REFIN

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Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

60 H12 PD13

61 H11 PD14

62 H10 PD15

37 63 E12 PC6

38 64 E11 PC7

39 65 E10 PC8

40 66 D12 PC9

29 41 D1 67 D11 PA8

30 42 D2 68 D10 PA9

I/O FT -

TIM4_CH2,

EVENTOUT

TIM4_CH3,

EVENTOUT

TIM4_CH4,

EVENTOUT

TIM3_CH1,

I2S2_MCK,

USART6_TX,

SDIO_D6,

EVENTOUT

TIM3_CH2,

SPI2_SCK/I2S2_CK,

I2S3_MCK,

USART6_RX,

SDIO_D7,

EVENTOUT

TIM3_CH3,

USART6_CK,

SDIO_D0,

EVENTOUT

MCO_2, TIM3_CH4,

I2C3_SDA,

I2S2_CKIN,

SDIO_D1,

EVENTOUT

MCO_1, TIM1_CH1,

I2C3_SCL,

USART1_CK,

USB_FS_SOF,

SDIO_D1,

EVENTOUT

TIM1_CH2,

I2C3_SMBA,

USART1_TX,

USB_FS_VBUS,

SDIO_D2,

EVENTOUT

OTG_FS_VBUS

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Pinouts and pin description STM32F411xC STM32F411xE

Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

C12 PA10

B12 PA11

A12 PA12

72 A11 PA13

73 C11 VCAP_2

74 F11 VSS

75 G11 VDD

76 A10 PA14

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A9 PA15

B11 PC10

C10 PC11

B10 PC12

I/O FT -

I/O FT

S -

I/O FT

I/O FT -

TIM1_CH3,

SPI5_MOSI/I2S5_SD,

USART1_RX,

USB_FS_ID,

EVENTOUT

TIM1_CH4,

SPI4_MISO,

USART1_CTS,

USART6_TX,

USB_FS_DM,

EVENTOUT

TIM1_ETR,

SPI5_MISO,

USART1_RTS,

USART6_RX,

USB_FS_DP,

EVENTOUT

JTMS-SWDIO,

EVENTOUT

JTCK-SWCLK,

EVENTOUT

JTDI,

TIM2_CH1/TIM2_ETR

SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS,

USART1_TX,

EVENTOUT

SPI3_SCK/I2S3_CK,

SDIO_D2,

EVENTOUT

I2S3ext_SD,

SPI3_MISO,

SDIO_D3,

EVENTOUT

SPI3_MOSI/I2S3_SD,

SDIO_CK,

EVENTOUT

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STM32F411xC STM32F411xE Pinouts and pin description

Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

81 C9 PD0

82 B9 PD1

83 C8 PD2

84 B8 PD3

85 B7 PD4

86 A6 PD5

87 B6 PD6

88 A5 PD7

39 55 A3 89 A8 PB3

40 56 A4 90 A7 PB4

41 57 B4 91 C5 PB5

42 58 C4 92 B5 PB6

I/O FT EVENTOUT

I/O FT -

TIM3_ETR,

SDIO_CMD,

EVENTOUT

I/O FT

I/O TC

I/O FT -

SPI2_SCK/I2S2_CK,

USART2_CTS,

EVENTOUT

USART2_RTS,

EVENTOUT

USART2_TX,

EVENTOUT

SPI3_MOSI/I2S3_SD,

USART2_RX,

EVENTOUT

USART2_CK,

EVENTOUT

JTDO-SWO,

TIM2_CH2,

SPI1_SCK/I2S1_CK,

SPI3_SCK/I2S3_CK,

USART1_RX,

I2C2_SDA,

EVENTOUT

JTRST, TIM3_CH1,

SPI1_MISO,

SPI3_MISO,

I2S3ext_SD,

I2C3_SDA, SDIO_D0,

EVENTOUT

TIM3_CH2,

I2C1_SMBA,

SPI1_MOSI/I2S1_SD,

SPI3_MOSI/I2S3_SD,

SDIO_D3,

EVENTOUT

TIM4_CH1,

I2C1_SCL,

USART1_TX,

EVENTOUT

DocID026289 Rev 7

45/149

Pinouts and pin description STM32F411xC STM32F411xE

Table 8. STM32F411xC/xE pin definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions Additional functions

A7 100

PB7

BOOT0

PB8

PB9

PE0

PE1

VSS

H3 PDR_ON

VDD

I/O FT -

TIM4_CH2,

I2C1_SDA,

USART1_RX,

SDIO_D0,

EVENTOUT

I B

I/O FT -

TIM4_CH3,

TIM10_CH1,

I2C1_SCL,

SPI5_MOSI/I2S5_SD,

I2C3_SDA, SDIO_D4,

EVENTOUT

I/O FT -

TIM4_CH4,

TIM11_CH1,

I2C1_SDA,

SPI2_NSS/I2S2_WS,

I2C2_SDA, SDIO_D5,

EVENTOUT

I/O FT -

TIM4_ETR,

EVENTOUT

I/O FT EVENTOUT

VPP

1. Function availability depends on the chosen device.

2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F411xx reference manual.

4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

5. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low)

46/149

DocID026289 Rev 7

Table 9. Alternate function mapping

AF04 AF05 AF06 AF07 AF08

Port

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

AF00

SYS_AF

TIM1/TIM2

TIM2_CH1/

TIM2_ETR

TIM2_CH2

TIM2_CH1/

TIM2_ETR

TIM3/

TIM4/ TIM5

TIM5_CH1

TIM5_CH2

TIM9/

TIM10/

TIM11

TIM2_CH3 TIM5_CH3 TIM9_CH1

TIM2_CH4 TIM5_CH4 TIM9_CH2

I2C1/I2C2/

I2C3

SPI1/I2S1S

PI2/

I2S2/SPI3/

I2S3

SPI2/I2S2/

SPI3/

I2S3/SPI4/

I2S4/SPI5/

I2S5

SPI3/I2S3/

USART1/

USART2

SPI4_MOSI

/I2S4_SD

I2S2_CKIN

I2S2_MCK -

SPI1_NSS/I

2S1_WS

SPI3_NSS/I2

S3_WS

SPI1_SCK/I

2S1_CK

USART2_

CTS

USART2_

RTS

USART2_

USART6

TIM1_BKIN TIM3_CH1 SPI1_MISO I2S2_MCK -

MCO_1

JTMS-

SWDIO

JTCK-

SWCLK

JTDI

AF01

TIM1_CH1N TIM3_CH2

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

TIM2_CH1/

TIM2_ETR

AF02

AF03

I2C3_

SCL

I2C3_

SMBA

SPI1_MOSI

/I2S1_SD

SPI5_MOSI/I

2S5_SD

SPI4_MISO

SPI5_MISO

USART1_

CTS

USART1_

RTS

USART6_

SPI1_NSS/I

2S1_WS

SPI3_NSS/I2

S3_WS

USART1_

AF09

I2C2/

I2C3

AF10

OTG1_FS

USB_FS_

SOF

USB_FS_

VBUS

USB_FS_

AF11 AF12 AF13 AF14 AF15

SDIO

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

SDIO_

CMD

SDIO_

AF03

Table 9. Alternate function mapping (continued)

AF04 AF05 AF06 AF07 AF08 AF09 AF00 AF01 AF02 AF10

Port

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB10

PB11

SYS_AF

JTDO-

SWO

JTRST

TIM1/TIM2

TIM3/

TIM4/ TIM5

TIM1_CH2N TIM3_CH3

TIM1_CH3N TIM3_CH4

TIM9/

TIM10/

TIM11

I2C1/I2C2/

I2C3

SPI1/I2S1S

PI2/

I2S2/SPI3/

I2S3

SPI2/I2S2/

SPI3/

I2S3/SPI4/

I2S4/SPI5/

I2S5

SPI5_SCK

/I2S5_CK

SPI5_NSS

/I2S5_WS

SPI3/I2S3/

USART1/

USART2

USART6

TIM2_CH2

TIM2_CH3

TIM3_CH1

TIM3_CH2

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM10_CH1

SPI1_SCK/I

2S1_CK

SPI3_SCK

/I2S3_CK

SPI1_MISO SPI3_MISO

USART1_

I2S3ext_S

I2C1_SMB

SPI1_MOSI

/I2S1_SD

SPI3_MOSI/

I2S3_SD

I2C1_SCL

I2C1_SDA -

USART1_

I2C1_SCL -

SPI5_MOSI/

I2S5_SD

TIM4_CH4 TIM11_CH1 I2C1_SDA

I2C2_SCL

SPI2_NSS/I

2S2_WS

SPI2_SCK/I

2S2_CK

I2S3_MCK -

TIM2_CH4 I2C2_SDA I2S2_CKIN -

I2C2/

I2C3

I2C2_SDA

I2C3_SDA

I2C2_SDA

OTG1_FS

PB12

PB13 -

TIM1_BKIN

TIM1_CH1N

PB14 TIM1_CH2N

PB15

RTC_50H z

TIM1_CH3N -

I2C2_SMB

SPI2_NSS/I

2S2_WS

SPI2_SCK/I

2S2_CK

SPI4_NSS

/I2S4_WS

SPI4_SCK/

I2S4_CK

SPI2_MISO I2S2ext_SD

SPI3_SCK

/I2S3_CK

SPI2_MOSI

/I2S2_SD

AF11 AF12 AF13 AF14 AF15

SDIO

SDIO_

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

PC3

PC4

PC5

PC6

PC0

PC1

PC2

PC10

PC11

PC12

PC13

PC14

PC15

PC7

PC8

PC9 MCO_2

AF00 AF01 AF02

SYS_AF TIM1/TIM2

TIM3/

TIM4/ TIM5

AF03

Table 9. Alternate function mapping (continued)

AF04 AF05 AF06 AF07 AF08 AF09

TIM9/

TIM10/

TIM11

I2C1/I2C2/

I2C3

SPI1/I2S1S

PI2/

I2S2/SPI3/

I2S3

SPI2/I2S2/

SPI3/

I2S3/SPI4/

I2S4/SPI5/

I2S5

SPI3/I2S3/

USART1/

USART2

USART6

I2C2/

I2C3

AF10

OTG1_FS

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM3_CH1

SPI2_MISO I2S2ext_SD

SPI2_MOSI

/I2S2_SD

I2S2_MCK -

SPI2_SCK/I

2S2_CK

I2S3_MCK

I2C3_SDA I2S2_CKIN

SPI3_SCK/I2

S3_CK

I2S3ext_SD SPI3_MISO

SPI3_MOSI/I

2S3_SD

USART6_

AF11 AF12 AF13 AF14 AF15

SDIO

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

SDIO_

Port

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PD3

PD4

PD5

PD6

PD0

PD1

PD2

AF00 AF01 AF02

SYS_AF TIM1/TIM2

TIM3/

TIM4/ TIM5

AF03

Table 9. Alternate function mapping (continued)

AF04 AF05 AF06 AF07 AF08 AF09

TIM9/

TIM10/

TIM11

I2C1/I2C2/

I2C3

SPI1/I2S1S

PI2/

I2S2/SPI3/

I2S3

SPI2/I2S2/

SPI3/

I2S3/SPI4/

I2S4/SPI5/

I2S5

SPI3/I2S3/

USART1/

USART2

USART6

I2C2/

I2C3

AF10

OTG1_FS

TIM4_CH1

TIM3_ETR

TIM4_CH2

TIM4_CH3

TIM4_CH4

SPI2_SCK/I

2S2_CK

SPI3_MOSI

/I2S3_SD

USART2_

CTS

USART2_

RTS

USART2_

AF11 AF12 AF13 AF14 AF15

SDIO

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

SDIO_

CMD

Port

PE10

PE11

PE12

PE0 -

PE1 -

PE2

TRACECL

PE3 TRACED0

PE4 TRACED1

PE5 TRACED2

PE6 TRACED3

PE7

PE8

PE9

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM4_ETR

TIM9_CH1

TIM9_CH2

PE13

PE14

PE15

AF00

SYS_AF TIM1/TIM2

TIM3/

TIM4/ TIM5

AF01

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

AF02

AF03

Table 9. Alternate function mapping (continued)

AF04 AF05 AF06 AF07 AF08 AF09

TIM9/

TIM10/

TIM11

I2C1/I2C2/

I2C3

SPI1/I2S1S

PI2/

I2S2/SPI3/

I2S3

SPI2/I2S2/

SPI3/

I2S3/SPI4/

I2S4/SPI5/

I2S5

SPI3/I2S3/

USART1/

USART2

USART6

I2C2/

I2C3

SPI4_SCK/I

2S4_CK

SPI5_SCK/I2

S5_CK

SPI4_NSS/I

2S4_WS

SPI5_NSS/I2

S5_WS

SPI4_MISO SPI5_MISO

SPI4_MOSI

/I2S4_SD

SPI5_MOSI/I

2S5_SD

SPI4_NSS/I

2S4_WS

SPI5_NSS/I2

S5_WS

SPI4_SCK/I

2S4_CK

SPI5_SCK/I2

S5_CK

SPI4_MISO SPI5_MISO

SPI4_MOSI

/I2S4_SD

SPI5_MOSI/I

2S5_SD

AF10

OTG1_FS

AF11 AF12 AF13 AF14 AF15

SDIO

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

H PH0

PH1

AF00 AF01 AF02

SYS_AF TIM1/TIM2

TIM3/

TIM4/ TIM5

AF03

Table 9. Alternate function mapping (continued)

AF04 AF05 AF06 AF07 AF08 AF09

TIM9/

TIM10/

TIM11

I2C1/I2C2/

I2C3

SPI1/I2S1S

PI2/

I2S2/SPI3/

I2S3

SPI2/I2S2/

SPI3/

I2S3/SPI4/

I2S4/SPI5/

I2S5

SPI3/I2S3/

USART1/

USART2

USART6

I2C2/

I2C3

AF10

OTG1_FS

AF11 AF12 AF13 AF14 AF15

SDIO

STM32F411xC STM32F411xE Memory mapping

The memory map is shown in

Figure 14

Figure 14. Memory map

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Bus

Cortex

-M4

Table 10. STM32F411xC/xE register boundary addresses

Boundary address

0xE010 0000 - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0x5004 0000 - 0xDFFF FFFF

Peripheral

Reserved

Cortex-M4 internal peripherals

Reserved

DocID026289 Rev 7

53/149

Memory mapping

Bus

AHB2

AHB1

STM32F411xC STM32F411xE

Table 10. STM32F411xC/xE register boundary addresses (continued)

Boundary address Peripheral

0x5000 0000 - 0x5003 FFFF

0x4002 6800 - 0x4FFF FFFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 5000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3400 - 0x4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2000 - 0x4002 2FFF

0x4002 1C00 - 0x4002 1FFF

0x4002 1400 - 0x4002 1BFF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

USB OTG FS

Reserved

DMA2

DMA1

Reserved

Flash interface register

RCC

Reserved

CRC

Reserved

GPIOH

Reserved

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

54/149

DocID026289 Rev 7

STM32F411xC STM32F411xE

Bus

APB2

Memory mapping

Table 10. STM32F411xC/xE register boundary addresses (continued)

Boundary address Peripheral

0x4001 5400- 0x4001 FFFF

0x4001 5000 - 0x4001 53FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2400 - 0x4001 2BFF

0x4001 2000 - 0x4001 23FF

0x4001 1800 - 0x4001 1FFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0400 - 0x4001 0FFF

0x4001 0000 - 0x4001 03FF

0x4000 7400 - 0x4000 FFFF

Reserved

SPI5/I2S5

TIM11

TIM10

TIM9

EXTI

SYSCFG

SPI4/I2S4

SPI1/I2S1

SDIO

Reserved

ADC1

Reserved

USART6

USART1

Reserved

TIM1

Reserved

DocID026289 Rev 7

55/149

Memory mapping

Bus

APB1

STM32F411xC STM32F411xE

Table 10. STM32F411xC/xE register boundary addresses (continued)

Boundary address Peripheral

0x4000 7000 - 0x4000 73FF

0x4000 6000 - 0x4000 6FFF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4800 - 0x4000 53FF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1000 - 0x4000 27FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

PWR

Reserved

I2C3

I2C2

I2C1

Reserved

USART2

I2S3ext

SPI3 / I2S3

SPI2 / I2S2

I2S2ext

IWDG

WWDG

RTC & BKP Registers

Reserved

TIM5

TIM4

TIM3

TIM2

56/149

DocID026289 Rev 7

STM32F411xC STM32F411xE Electrical characteristics

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

1.7 V ≤ tested.

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 15

Figure 15. Pin loading conditions

-#5PIN

#P&

-36

DocID026289 Rev 7

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123

Electrical characteristics

6.1.5 Pin input voltage

STM32F411xC STM32F411xE

The input voltage measurement on a pin of the device is described in Figure 16 .

Figure 16. Input voltage measurement

-#5PIN

6).

-36

58/149

DocID026289 Rev 7

STM32F411xC STM32F411xE

6.1.6 Power supply scheme

Figure 17. Power supply scheme

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1. To connect PDR_ON pin, refer to Section 3.15: Power supply supervisor

2. The 4.7 µF ceramic capacitor must be connected to one of the V

pin.

3. VCAP_2 pad is only available on LQFP100 and UFBGA100 packages.

4. V

DDA

and V

SSA

Caution: Each power supply pair (for example V

, V

DDA

SSA

) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.

This might cause incorrect operation of the device.

DocID026289 Rev 7

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123

Electrical characteristics STM32F411xC STM32F411xE

Figure 18. Current consumption measurement scheme

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Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 11: Voltage characteristics

Table 12: Current characteristics

, and

Table 13: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 11. Voltage characteristics

Ratings Min Max Unit

–V

SSX

| Δ V

DDx

− V

ESD(HBM)

External main supply voltage (including V

DDA

BAT

)

(1)

, V

and

Input voltage on FT and TC pins

(2)

Input voltage on any other pin

Input voltage for BOOT0

Variations between different V

power pins

| Variations between all the different ground pins

Electrostatic discharge voltage (human body model)

–0.3

4.0

–0.3

+4.0

–0.3

4.0

9.0

50 see

Section 6.3.14:

Absolute maximum ratings (electrical sensitivity)

1. All main power (V

, V

DDA

) and ground (V

SS supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

maximum value must always be respected. Refer to

Table 12

for the values of the maximum allowed injected current.

V mV

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DocID026289 Rev 7

STM32F411xC STM32F411xE Electrical characteristics

Symbol

Table 12. Current characteristics

Ratings Max.

Unit

Σ I

VDD

VSS

VDD

VSS

Total current into sum of all V

DD_x power lines (source)

(1)

Total current out of sum of all V

SS_x ground lines (sink)

(1)

Maximum current into each V

DD_x power line (source)

(1)

Maximum current out of each V

SS_x ground line (sink) (1)

Output current sunk by any I/O and control pin

160

-160

100

-100

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/O and control pins

(2)

Total output current sourced by sum of all I/Os and control pins

(2)

Injected current on FT and TC pins

(4)

-25

120

-120 mA

INJ(PIN)

(3) –5/+0

Σ I

INJ(PIN)

Injected current on NRST and B pins

(4)

Total injected current (sum of all I/O and control pins)

(5)

±25

1. All main power (V

DD permitted range.

, V

DDA

) and ground (V

, V

SSA

) pins must always be connected to the external power supply, in the

2. This current consumption must be correctly distributed over all I/Os and control pins.

3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the positive and

Symbol

Table 13. Thermal characteristics

Ratings Value Unit

STG

Storage temperature range

Maximum junction temperature

–65 to +150

130

LEAD

Maximum lead temperature during soldering

(WLCSP49, LQFP64/100, UFQFPN48,

UFBGA100) see note

(1)

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011).

°C

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Electrical characteristics STM32F411xC STM32F411xE

6.3.1 General operating conditions

Symbol Parameter

Table 14. General operating conditions

Conditions Min Typ Max Unit f

HCLK

Internal AHB clock frequency

Power Scale3: Regulator ON,

VOS[1:0] bits in PWR_CR register = 0x01

Power Scale2: Regulator ON,

VOS[1:0] bits in PWR_CR register = 0x10

Power Scale1: Regulator ON,

VOS[1:0] bits in PWR_CR register = 0x11 f

PCLK1 f

PCLK2

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(ADC limited to 1.2 M samples)

DDA

(2)(3)

Analog operating voltage

(ADC limited to 2.4 M samples)

Must be the same potential as V

(4)

BAT

Backup operating voltage

Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins

VOS[1:0] bits in PWR_CR register = 0x01

Max frequency 64 MHz

VOS[1:0] bits in PWR_CR register = 0x10

Max frequency 84 MHz

VOS[1:0] bits in PWR_CR register = 0x11

Max frequency 100 MHz

Regulator OFF: 1.2 V external voltage must be supplied on

VCAP_1/VCAP_2 pins

Max frequency 64 MHz

Max frequency 84 MHz

Max frequency 100 MHz

Input voltage on RST, FT and

TC pins

(6)

Input voltage on BOOT0 pin -

2 V ≤ V

≤ 3.6 V

≤ 2 V

UFQFPN48

WLCSP49

Power dissipation at

= 85°C (range 6) or

105 °C (range 7) (7)

LQFP64

LQFP100

UFBGA100

1.7

(1)

1.7

(1)

2.4

1.65

1.08

(5)

1.20

(5)

1.26

0 -

1.32

100

3.6

2.4

3.6

1.14 1.20

1.26 1.32

(5)

1.38

1.10

1.14

1.20

1.26

1.32

1.26

1.32

1.38

–0.3

5.5

–0.3

5.2

625

392

425

465

323

MHz

V mW

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STM32F411xC STM32F411xE Electrical characteristics

Symbol

Table 14. General operating conditions (continued)

Parameter Conditions Min Typ Max Unit

Power dissipation at

= 125 °C (range 3)

Ambient temperature for range 6

Ambient temperature for range 7

Ambient temperature for range 3

(7)

Junction temperature range

UFQFPN48

WLCSP49

LQFP64

LQFP100

UFBGA100

Maximum power dissipation

Low power dissipation

(8)

Maximum power dissipation

Low power dissipation

(8)

Maximum power dissipation

Low power dissipation

(8)

Range 6

Range 7

Range 3

- 40

- 40 -

- 40

1. V

DDA

minimum value of 1.7 V with the use of an external power supply supervisor (refer to

reset OFF

Section 3.15.2: Internal

2. When the ADC is used, refer to

Table 65: ADC characteristics

3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.

4. It is recommended to power V

DD and V

DDA from the same source. A maximum difference of 300 mV between V

DD and

DDA can be tolerated during power-up and power-down operation.

5. Guaranteed by test in production.

6. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled

7. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

8. In low power dissipation state, T

can be extended to this range as long as T

does not exceed T

Jmax

125

110

130

105

125

130

105

156

106

116 mW

°C

Operating power supply range

Table 15. Features depending on the operating power supply range

ADC operation

Maximum

Flash memory access frequency with no wait states

Flashmax

)

Maximum Flash memory access frequency with wait states

(1)(2)

I/O operation

Clock output frequency on

I/O pins

(3)

Possible

Flash memory operations

2.1 V

=1.7 to

(4)

= 2.1 to

2.4 V

Conversion time up to

1.2 Msps

Conversion time up to

1.2 Msps

16 MHz

(5)

18 MHz

100 MHz with 6 wait states

– No I/O compensation up to 30 MHz

100 MHz with 5 wait states

– No I/O compensation up to 30 MHz

8-bit erase and program operations only

16-bit erase and program operations

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Electrical characteristics STM32F411xC STM32F411xE

Table 15. Features depending on the operating power supply range (continued)

Operating power supply range

ADC operation

Maximum

Flash memory access frequency with no wait states

Flashmax

)

Maximum Flash memory access frequency with wait states

(1)(2)

I/O operation

Clock output frequency on

I/O pins

(3)

Possible

Flash memory operations

= 2.4 to

2.7 V

Conversion time up to

2.4 Msps

24 MHz

100 MHz with 4 wait states

– I/O compensation works up to 50 MHz

16-bit erase and program operations

= 2.7 to

3.6 V (6)

Conversion time up to

2.4 Msps

30 MHz

100 MHz with 3 wait states

– I/O compensation works

– up to

100 MHz when V

3.0 to 3.6 V

– up to

50 MHz when V

2.7 to 3.0 V

32-bit erase and program operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.

3. Refer to Table 55: I/O AC characteristics

for frequencies vs. external load.

4. V

DDA

minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF

5. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.

6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of

D- and D+ pins will be degraded between 2.7 and 3 V.

6.3.2 VCAP_1/VCAP_2 external capacitors

Stabilization for the main regulator is achieved by connecting the external capacitor C

EXT the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT

to capacitors are replaced by a single capacitor.

EXT

is specified in Table 16

Figure 19. External capacitor C

EXT

(65

/HDN

069

1. Legend: ESR is the equivalent series resistance.

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6.3.3

Electrical characteristics

Symbol

Table 16. VCAP_1/VCAP_2 operating conditions (1)

Parameter Conditions

CEXT

ESR

Capacitance of external capacitor with a single VCAP pin available

ESR of external capacitor with a single VCAP pin available

4.7 µF

< 1 Ω

1. When bypassing the voltage regulator, the two 2.2 µF V

CAP replaced by two 100 nF decoupling capacitors.

capacitors are not required and should be

Operating conditions at power-up/power-down (regulator ON)

Subject to general operating conditions for T

Table 17. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit t

VDD

rise time rate

fall time rate

∞

µs/V

Note:

Subject to general operating conditions for T

Table 18. Operating conditions at power-up / power-down (regulator OFF) (1)

Symbol Parameter Conditions Min Max Unit t t

VDD

VCAP

rise time rate

fall time rate

Power-up

Power-down

CAP_1

and V

CAP_2 rise time rate Power-up

CAP_1

and V

CAP_2

fall time rate Power-down

∞

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V

1.08 V.

reach below

µs/V

This feature is only available for UFBGA100 package.

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123

Electrical characteristics

6.3.5

STM32F411xC STM32F411xE

Embedded reset and power control block characteristics

The parameters given in

Table 19 are derived from tests performed under ambient

temperature and V

supply voltage @ 3.3V.

Symbol

Table 19. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

PVD

Programmable voltage detector level selection

PVDhyst

(2) PVD hysteresis

POR/PDR

Power-on/power-down reset threshold

PDRhyst

(2)

PDR hysteresis

BOR1

Brownout level 1 threshold

BOR2

Brownout level 2 threshold

BOR3

Brownout level 3 threshold

BORhyst

(2)

BOR hysteresis

POR reset timing -

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

2.09

2.14

2.19

1.98

2.04

2.08

2.23

2.30

2.37

2.13

2.19

2.25

2.39

2.45

2.51

2.29

2.35

2.39

2.54

2.60

2.65

2.44

2.51

2.56

2.70

2.76

2.82

2.59

2.66

2.71

2.86

2.93

2.99

2.77

2.82

2.89

2.96

3.03

3.10

2.85

2.93

2.99

3.07

3.14

3.21

2.95

3.03

3.09

100 -

1.60

(1) 1.68

1.76

1.64

1.72

1.80

40 -

2.13

2.19

2.24

2.23

2.29

2.33

2.44

2.50

2.56

2.53

2.59

2.63

2.75

2.83

2.88

2.85

2.92

2.97

100 -

0.5

1.5

3.0

V mV

V mV ms

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Electrical characteristics

Table 19. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

RUSH

(2)

RUSH

(2)

In-Rush current on voltage regulator poweron (POR or wakeup from

Standby)

In-Rush energy on voltage regulator poweron (POR or wakeup from

Standby)

= 1.7 V, T

= 125 °C,

RUSH

= 171 mA for 31 µs

160

200

5.4

µC

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design.

3. The reset timing is measured from the power-on (POR reset or wakeup from V

BAT instruction is fetched by the user application code.

) to the instant when first

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 18: Current consumption measurement scheme

All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at VDD or VSS (no load).

• All peripherals are disabled except if it is explicitly mentioned.

• The Flash memory access time is adjusted to both f

HCLK

frequency and VDD ranges

(refer to

Table 15: Features depending on the operating power supply range ).

• The voltage scaling is adjusted to f

HCLK

frequency as follows:

– Scale 3 for f

HCLK

≤ 64 MHz

– Scale 2 for 64 MHz < f

HCLK

≤ 84 MHz

– Scale 1 for 84 MHz < f

HCLK

≤ 100 MHz

• The system clock is HCLK, f

PCLK1

= f

HCLK

/2, and f

PCLK2

= f

HCLK

• External clock is 4 MHz and PLL is ON except if it is explicitly mentioned.

• The maximum values are obtained for V

DD temperature (T

= 3.6 V and a maximum ambient

), and the typical values for T

= 25 °C and V

= 3.3 V unless otherwise specified.

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Table 20. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

= 1.7 V

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) T

25 °C

85 °C

105 °C

125 °C

Unit

External clock,

PLL ON

(2)

, all peripherals enabled

(3)(4)

100

21.4

23.0

17.2

18.9

(5)

11.9

9.4

12.9

10.1

4.3

3.0

4.8

3.3

23.6

19.1

13.2

10.4

5.0

3.6

24.0

19.2

13.7

11.0

5.6

4.3

25.0

20.2

14.6

11.9

6.5

5.2

Supply current in Run mode

HSI, PLL off, all peripherals

enabled

(4)

External clock,

PLL on

(2)

)all

peripherals disabled

(3)

1 0.5

0.7

1.0

1.7

2.6

100

12.7

14.0

10.2

11.6

(5)

7.1

5.6

7.9

6.3

2.5

1.9

3.0

2.1

14.4

11.8

8.2

6.5

3.3

2.4

14.8

12.0

8.7

7.1

3.9

3.0

15.8

13.0

9.7

8.0

4.8

3.9

HSI, PLL off, all peripherals

disabled

(4)

1 0.4

0.5

0.9

1.6

2.5

1. Guaranteed by characterization results.

2. Refer to Table 41 and RM0383 for the possible PLL VCO setting

3. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered.

4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part.

5. Guaranteed by test in production.

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Table 21. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

= 3.6 V

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

Typ

25 °C

85 °C

105 °C

125 °C

Unit

External clock,

PLL ON

(2)

, all peripherals enabled

(3)(4)

100

21.7

17.5

12.2

9.6

4.5

3.0

23.3

19.2

(5)

13.2

10.4

5.0

3.3

23.9

19.4

13.5

10.7

5.3

3.6

24.3 25.3

19.5

20.5

14.0

11.2

14.9

12.1

5.9

6.8

4.3 5.2

Supply current in

Run mode

HSI, PLL OFF, all peripherals

enabled

(3)

External clock,

PLL OFF

(2)

all peripherals

disabled

(3)

100

0.5

13.0

10.5

7.4

5.9

2.8

1.9

0.7

14.6

6.6

3.3

2.1

1.0

14.6

12.1

8.8

6.8

3.5

2.4

1.7

14.9

12.2

8.9

7.3

4.2

3.1

2.6

16.0

13.2

9.9

8.2

5.1

4.0

HSI, PLL OFF, all peripherals

disabled

(3)

1 0.4

0.5

0.9

1.6

2.5

1. Guaranteed by characterization results.

2. Refer to Table 41 and RM0383 for the possible PLL VCO setting

3. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered.

4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part.

5. Guaranteed by test in production.

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Electrical characteristics STM32F411xC STM32F411xE

Table 22. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled except prefetch) running from Flash memory- V

= 1.7 V

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

Typ

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock, PLL

(2)

, all peripherals enabled

(3)(4)

HSI, PLL OFF

(2)

, all peripherals enabled

, all

peripherals disabled

(3)

External clock, PLL ON all peripherals disabled

(3)

(2)

(3)

100

20.4

16.5

11.4

9.0

4.6

2.9

0.7

11.2

9.1

6.4

5.1

2.6

1.8

0.6

21.8

17.6

12.3

9.7

5.0

3.2

0.8

12.2

9.9

7.0

5.6

3.0

2.0

0.7

22.1

17.8

12.5

10.0

5.3

3.6

1.3

12.4

10.1

7.3

5.9

3.3

2.4

1.2

22.8

18.6

13.1

10.6

6.0

4.3

1.9

13.2

10.9

7.9

6.6

4.0

3.0

1.9

1. Guaranteed by characterization results.

2. Refer to Table 41 and RM0383 for the possible PLL VCO setting

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

4. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part.

7.0

5.3

2.9

14.2

23.8

19.6

14.1

11.6

11.9

8.9

7.6

5.0

4.0

2.9

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Table 23. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled except prefetch) running from Flash memory - V

= 3.6 V

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

Typ

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock, PLL

(2)

, all peripherals enabled

(3)(4)

HSI, PLL OFF

(2)

, all peripherals enabled

, all

peripherals disabled

(3)

External clock, PLL ON all peripherals disabled

(3)

(2)

(3)

100

20.7

16.8

11.8

9.3

4.8

3.0

0.7

11.6

9.7

6.7

5.4

2.9

1.9

0.7

22.2

18.0

12.7

10.2

5.5

3.3

1.0

12.6

10.2

(5)

7.4

6.0

3.4

2.2

0.9

22.5

18.3

12.9

10.4

5.8

3.8

1.4

12.9

11.1

7.7

6.3

3.7

2.6

1.3

23.2

19.0

13.6

11.1

6.5

4.5

2.1

13.6

11.3

8.3

7.0

4.4

3.3

2.1

1. Guaranteed by characterization results.

2. Refer to Table 41 and RM0383 for the possible PLL VCO setting

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

4. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part.

5. Guaranteed by test in production.

7.4

5.4

3.0

14.8

24.4

20.1

14.6

12.0

12.5

9.4

8.0

5.4

4.3

3.1

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Electrical characteristics STM32F411xC STM32F411xE

Table 24. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator disabled) running from Flash memory - V

= 3.6 V

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

Typ

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock, PLL

(2)

, all peripherals enabled

(3)(4)

HSI, PLL OFF

(2)

, all peripherals enabled

, all

peripherals disabled

(3)

External clock, PLL ON all peripherals disabled

(3)

(2)

(3)

100

29.5

25.5

18.6

15.2

7.6

4.8

0.9

20.4

18.4

13.5

11.3

5.6

3.6

0.9

31.5

27.1

19.8

16.4

8.4

5.2

1.3

21.8

19.2

(5)

14.5

12.2

6.4

4.1

1.2

32.3

27.9

20.4

16.9

8.8

5.7

1.6

22.7

20.9

15.2

12.8

6.7

4.5

1.6

33.3

28.9

21.2

17.7

9.5

6.5

2.4

23.8

21.1

15.9

13.6

7.4

5.2

2.3

1. Guaranteed by characterization results.

2. Refer to Table 41 and RM0383 for the possible PLL VCO setting

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

4. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part.

5. Guaranteed by test in production.

10.5

7.5

3.4

25.1

34.7

30.2

22.4

18.7

22.4

17.2

14.7

8.5

6.3

3.4

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Table 25. Typical and maximum current consumption in run mode, code with data processing

(ART accelerator enabled with prefetch) running from Flash memory - V

= 3.6 V

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

Typ

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Run mode

External clock, PLL

(2)

, all peripherals enabled

(3)(4)

HSI, PLL OFF

(2)

, all peripherals enabled

, all

peripherals disabled

(3)

External clock, PLL ON all peripherals disabled

(3)

(2)

(3)

100

31.7

26.9

19.6

15.6

7.6

5.1

1.0

22.5

19.5

14.5

11.7

5.6

4.0

0.9

33.6

28.6

20.9

16.7

8.4

5.6

1.3

24.2

21.1

(5)

15.7

12.7

6.4

4.5

1.2

34.5

29.4

21.5

17.2

8.8

6.1

1.7

24.9

21.8

16.3

13.2

6.8

4.9

1.6

35.5

30.3

22.3

18.0

9.5

6.8

2.3

26.0

22.8

17.1

14.0

7.4

5.6

2.2

1. Guaranteed by characterization results.

2. Refer to Table 41 and RM0383 for the possible PLL VCO setting

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

4. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part.

5. Guaranteed by test in production.

10.6

7.9

3.4

27.3

37.0

31.6

23.5

19.1

24.1

18.3

15.1

8.5

6.7

3.3

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123

Electrical characteristics STM32F411xC STM32F411xE

Table 26. Typical and maximum current consumption in Sleep mode - V

= 3.6 V

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

Typ

25 °C

85 °C

105 °C

125 °C

Unit

Supply current in Sleep mode

External clock, PLL

(2)

, all peripherals enabled

(3)(4)

HSI, PLL OFF

(2)

, all peripherals enabled

, all

peripherals disabled

(3)

External clock, PLL ON all peripherals disabled

(3)

(2)

(3)

100

12.2

9.8

6.9

5.4

2.8

1.3

0.4

3.0

2.5

1.9

1.6

1.1

0.4

0.3

13.2

10.6

7.4

5.9

3.2

1.7

0.5

3.6

3.0

2.2

1.9

1.4

0.5

0.4

13.4

10.9

7.7

6.2

3.5

2.2

0.9

3.9

3.2

2.5

2.1

1.7

0.9

0.8

14.1

11.6

8.3

6.8

4.1

2.8

1.6

4.5

3.9

3.0

2.7

2.3

1.6

1.5

1. Guaranteed by characterization results.

2. Refer to Table 41 and RM0383 for the possible PLL VCO setting.

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

4. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part.

5.3

4.0

2.8

5.7

15.3

12.8

9.5

8.0

5.1

4.2

3.9

3.5

2.8

2.7

Symbol

Table 27. Typical and maximum current consumptions in Stop mode - V

= 1.7 V

Typ

(1)

Max

(1)

Conditions Parameter

25 °C

85 °C

105 °C

125 °C

112 142

(2)

400 710 1200

(2)

DD_STOP

Flash in Stop mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

Flash in Deep power down mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

Low power low voltage regulator usage

42.6

(2)

75 99

(2)

13.6

(2)

9 28

(2)

300

310

265

230

580 1044

(2)

580 993

(2)

550 1007

(2)

500 910

(2)

Unit

µA

1. Guaranteed by characterization results.

2. Guaranteed by test in production.

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STM32F411xC STM32F411xE Electrical characteristics

Symbol

Table 28. Typical and maximum current consumption in Stop mode - V

=3.6 V

Typ Max

(1)

Conditions Parameter

25 °C

85 °C

105 °C

125 °C

Flash in Stop mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

113.7 145

(2)

43.1

(2)

410 720 1217

(2)

310 600 1073

(2)

Unit

DD_STOP Flash in Deep power down mode, all oscillators OFF, no independent watchdog

Main regulator usage

Low power regulator usage

Low power low voltage regulator usage

76.2

105

320 600 1019

275 560 1025

235 510 928

µA

1. Guaranteed by characterization results.

2. Guaranteed by test in production.

Table 29. Typical and maximum current consumption in Standby mode - V

= 1.7 V

Typ

(1)

Max

(2)

Symbol Parameter Conditions

25 °C

85 °C

105 °C

125 °C

Unit

DD_STBY

Supply current in Standby mode

Low-speed oscillator (LSE) and RTC ON 2.4

RTC and LSE OFF 1.8

(3)

1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.

2. Guaranteed by characterization results.

3. Guaranteed by test in production.

(3)

µA

Table 30. Typical and maximum current consumption in Standby mode - V

= 3.6 V

Typ

(1)

Max

(2)

Symbol Parameter Conditions

25 °C

85 °C

105 °C

125 °C

Unit

DD_STBY

Supply current in Standby mode

Low-speed oscillator (LSE) and RTC ON

RTC and LSE OFF

2.8

2.1

(3)

13.5

1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.

2. Guaranteed by characterization results.

3. Guaranteed by test in production.

(3)

µA

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123

Electrical characteristics STM32F411xC STM32F411xE

Table 31. Typical and maximum current consumptions in V

BAT

mode

Typ Max

(2)

Symbol Parameter Conditions

(1)

= 25 °C

BAT

1.7 V

BAT

2.4 V

BAT

3.3 V

DD_VBAT

Backup domain supply current

Low-speed oscillator (LSE in lowdrive mode) and RTC ON

Low-speed oscillator (LSE in highdrive mode) and RTC ON

RTC and LSE OFF

0.7

1.5

0.8

1.6

0.1

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C

of 6 pF for typical values.

2. Guaranteed by characterization results.

1.0

1.9

0.1

85 °C

105 °C

125 °C Unit

3.8

BAT

= 3.6 V

5.8

6.8

8.6

5.8

µA

Figure 20. Typical V

BAT

current consumption (LSE in low-drive mode and RTC ON)

# # #

4EMPERATURE

-36

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STM32F411xC STM32F411xE Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 53: I/O static characteristics .

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 33: Peripheral current consumption ), the I/Os used by an application also contribute to the current consumption.

When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

=

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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Electrical characteristics STM32F411xC STM32F411xE

Table 32. Switching output I/O current consumption

Symbol Parameter Conditions

(1)

I/O toggling

frequency (f

)

Typ Unit

= 3.3 V

C = C

INT

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

C = C

INT

= 3.3 V

EXT

= 0 pF

+ C

EXT

+ C

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

IDDIO

I/O switching current

C = C

EXT

INT

= 3.3 V

=10 pF

+ C

EXT

+ C

8 MHz

25 MHz

50 MHz

60 MHz

0.65

1.85

2.45

4.70

84 MHz

90 MHz

2 MHz

8 MHz

8.80

10.47

0.25

1.00

= 3.3 V

C = C

EXT

INT

= 22 pF

+ C

EXT

+ C

25 MHz

50 MHz

3.45

7.15

60 MHz

2 MHz

11.55

0.32

= 3.3 V

EXT

= 33 pF

C = C

INT

+ C

EXT

+ C

8 MHz

25 MHz

1.27

3.88

50 MHz

1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).

12.34

2.40

3.55

4.23

0.20

0.10

0.35

1.05

2.20

0.05

0.15

0.45

0.85

1.00

1.40

1.67

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STM32F411xC STM32F411xE Electrical characteristics

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• At startup, all I/O pins are in analog input configuration.

• All peripherals are disabled unless otherwise mentioned.

• The ART accelerator is ON.

• Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.

• HCLK is the system clock at 84 MHz. f

PCLK1

= f

HCLK

/2, and f

PCLK2

= f

HCLK

The given value is calculated by measuring the difference of current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• Ambient operating temperature is 25 °C and V

=3.3 V.

AHB1

(up to 100 MHz)

APB1

(up to 50 MHz)

Table 33. Peripheral current consumption

Peripheral

GPIOA

(Typ)

1.55

TIM5

PWR

USART2

I2C1/2/3

SPI2 (3)

SPI3

(3)

I2S2

I2S3

WWDG

GPIOB

GPIOC

GPIOD

GPIOE

GPIOH

CRC

DMA1

(1)

DMA1

(2)

TIM2

TIM3

TIM4

3.10

2.62

2.86

1.90

1.67

0.71

11.19

8.57

8.33

11.19

0.71

3.33

1.55

0.36

14.96

1.54N+2.66

14.96

1.54N+2.66

Unit

µA/MHz

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123

Electrical characteristics STM32F411xC STM32F411xE

Table 33. Peripheral current consumption (continued)

Peripheral I

(Typ)

APB2

(up to 100 MHz)

TIM1

TIM9

TIM10

TIM11

OTG_FS

ADC1

(4)

SPI1

USART1

USART6

SDIO

SPI4

SYSCFG

5.71

2.86

1.79

2.02

23.93

2.98

1.19

3.10

2.86

5.95

1.31

0.71

Unit

µA/MHz

1. Valid if all the DMA streams are activated (please refer to the reference manual RM0383).

2. For N DMA streams activated (up to 8 activated streams, refer to the reference manual RM0383).

3. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral.

4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part.

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STM32F411xC STM32F411xE

6.3.7 Wakeup time from low-power modes

Electrical characteristics

The wakeup times given in Table 34

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep modes: the wakeup event is WFE.

• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

Figure 21. Low-power mode wakeup

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069

All timings are derived from tests performed under ambient temperature and V

=3.3 V.

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123

Electrical characteristics STM32F411xC STM32F411xE

Symbol

Table 34. Low-power mode wakeup timings (1)

Parameter Min

(1)

Typ

(1)

Max

(1) Unit t

WUSLEEP

(2) Wakeup from Sleep mode 4 6

CPU clock cycle t

WUSTOP

(2)

Wakeup from Stop mode, usage of main regulator

Wakeup from Stop mode, usage of main regulator, Flash memory in Deep power down mode

Wakeup from Stop mode, regulator in low power mode

Wakeup from Stop mode, regulator in low power mode,

Flash memory in Deep power down mode

13.5

105

113

14.5

111

130

µs t

WUSTDBY

(2)(3) Wakeup from Standby mode 314 407 µs t

WUFLASH

Wakeup of Flash from Flash_Stop mode

Wakeup of Flash from Flash Deep power down mode

100

µs

1. Guaranteed by characterization results.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

3. t

WUSTDBY maximum value is given at –40 °C.

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 53

. However, the recommended clock input

waveform is shown in Figure 22 .

The characteristics given in

Table 35 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 14 .

Symbol

Table 35. High-speed external user clock characteristics

Parameter f

HSE_ext

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

External user clock source frequency

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design.

(1)

Conditions

≤ V

Min

0.7V

Typ

Max

0.3V

Unit

MHz

V ns

±1 pF

µA

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STM32F411xC STM32F411xE Electrical characteristics

Figure 22. High-speed external clock source AC timing diagram

Z+6(+

+6(+

+6(/

U+6(

+6(

I+6(

Z+6(/

06Y9

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 53

. However, the recommended clock input

waveform is shown in Figure 23 .

The characteristics given in

Table 36 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 14 .

Symbol

Table 36. Low-speed external user clock characteristics

Parameter f

LSE_ext

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

LSEL t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current

1. Guaranteed by design.

Conditions

≤ V

Min

0.7V

450

Typ

32.768

Max

1000

0.3V

±1

Unit kHz

V ns pF

µA

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123

Electrical characteristics STM32F411xC STM32F411xE

Figure 23. Low-speed external clock source AC timing diagram

Note:

84/149

Z/6(+

/6(+

/6(/

U/6(

/6(

I/6( W

Z/6(/

06Y9

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 37

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 37. HSE 4-26 MHz oscillator characteristics

(1)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor

200

MHz k Ω

HSE current consumption

=3.3 V,

ESR= 30 Ω ,

=5 pF @25 MHz

=3.3 V,

ESR= 30 Ω ,

=10 pF @25 MHz

Startup

450

530 -

µA

G m_crit_max t

SU(HSE)

(2)

Maximum critical crystal g

Startup time m

is stabilized -

mA/V ms

1. Guaranteed by design.

2. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 24

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

DocID026289 Rev 7

STM32F411xC STM32F411xE Electrical characteristics

Figure 24. Typical application with an 8 MHz crystal

Note:

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0+]

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26&B28 7

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1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 38

The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption.

Symbol

Table 38. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit

Feedback resistor 18.4

LSE current consumption

Low-power mode

(default)

High-drive mode 3

G m

_crit_max

Maximum critical crystal g m

Startup, low-power mode

Startup, high-drive mode

0.56

1.50

SU(LSE)

(2) startup time V

is stabilized 2 -

1. Guaranteed by design.

2. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is guaranteed by characterization. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

M Ω

µA

µA/V s

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

For information about the LSE high-power mode, refer to the reference manual RM0383.

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123

Electrical characteristics

6.3.9

STM32F411xC STM32F411xE

Figure 25. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWK

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N+ ]

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26&B,1

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I/6(

670)

Internal clock source characteristics

The parameters given in

Table 39 and

Table 40 are derived from tests performed under

ambient temperature and V

supply voltage conditions summarized in

Table 14

High-speed internal (HSI) RC oscillator

Symbol

Table 39. HSI oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit

I t f

HSI

ACC

HSI su(HSI)

(2)

DD(HSI)

(2)

Frequency -

Accuracy of the HSI oscillator

User-trimmed with the RCC_CR register

(2)

Factorycalibrated

= - 40 to 125 °C

(3)

= - 40 to 105 °C

(3)

= - 10 to 85 °C

(3)

= 25 °C

(4)

HSI oscillator startup time

HSI oscillator power consumption

- 1

- 8

- 4

1. V

= 3.3 V, T

= - 40 to 125 °C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Factory calibrated non-soldered parts.

2.2

5.5

4.5

MHz

µs

µA

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STM32F411xC STM32F411xE Electrical characteristics

Figure 26. ACC

HSI

versus temperature

4! #

-IN

-AX

4YPICAL

-36

1. Guaranteed by characterization results.

Low-speed internal (LSI) RC oscillator

Symbol

Table 40. LSI oscillator characteristics

(1)

Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

LSI oscillator startup time

LSI oscillator power consumption

1. V

= 3 V, T

= –40 to 125 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Guaranteed by design.

Min

Typ

0.4

Max

0.6

Unit kHz

µs

µA

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123

Electrical characteristics STM32F411xC STM32F411xE

Figure 27. ACC

LSI

versus temperature

MAX

AVG

MIN

4EMPERAT URE #

-36

The parameters given in

Table 41 and

Table 42 are derived from tests performed under

temperature and V

supply voltage conditions summarized in

Table 14 .

Symbol f

PLL_IN f

PLL_OUT f

PLL48_OUT f

VCO_OUT t

LOCK

Jitter

(3)

Table 41. Main PLL characteristics

Parameter

PLL input clock

(1)

PLL multiplier output clock

48 MHz PLL multiplier output clock

PLL VCO output

Conditions Min

0.95

(2)

PLL lock time

Cycle-to-cycle jitter

Period Jitter

VCO freq = 100 MHz

VCO freq = 432 MHz

System clock

100 MHz

RMS peak to peak

100

Typ

± 150

± 200

Max

2.10

100

432

200

300

Unit

MHz

µs ps

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STM32F411xC STM32F411xE Electrical characteristics

Symbol

Table 41. Main PLL characteristics (continued)

Parameter Conditions Min Typ Max Unit

DD(PLL)

(4)

DDA(PLL)

(4)

PLL power consumption on VDD

PLL power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.30

0.55

0.40

0.75

0.40

0.85

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of two PLLs in parallel could degraded the Jitter up to +30%.

4. Guaranteed by characterization results.

Symbol

Table 42. PLLI2S (audio PLL) characteristics

Parameter

PLLI2S input clock

(1)

Conditions

Min

0.95

(2) f f t f

PLLI2S_IN

PLLI2S_OUT

VCO_OUT

LOCK

PLLI2S multiplier output clock

PLLI2S VCO output

PLLI2S lock time

VCO freq = 100 MHz

VCO freq = 432 MHz

100

Jitter

(3)

Master I2S clock jitter

WS I2S clock jitter

Cycle to cycle at

12.288 MHz on

48 kHz period,

N=432, R=5

Average frequency of

12.288 MHz

N = 432, R = 5 on 1000 samples

Cycle to cycle at 48 KHz on 1000 samples

RMS

peak to peak

DD(PLLI2S)

(4)

DDA(PLLI2S)

(4)

PLLI2S power consumption on

DDA

VCO freq = 100 MHz

VCO freq = 432 MHz

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

Typ

± 280

400

0.40

0.75

0.40

0.85

Max

2.10

216

432

200

300

Unit

MHz

µs ps mA

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Electrical characteristics STM32F411xC STM32F411xE

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 49: EMI characteristics for LQFP100

). It is available only on the main PLL.

Symbol f

Mod md

MODEPER * INCSTEP

1. Guaranteed by design.

Table 43. SSCG parameter constraints

Parameter Min

Modulation frequency

Peak modulation depth

(Modulation period) * (Increment Step)

0.25

Typ

Max

(1)

-1

Unit kHz

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER

= [

PLL_IN

⁄ ( 4 × f

Mod

) ] f

PLL_IN and f

Mod must be expressed in Hz.

As an example:

If f

PLL_IN

= 1 MHz, and f

MOD

= 1 kHz, the modulation depth (MODEPER) is given by equation 1:

MODEPER

= round 10

⁄ ( 4 × 10

) ]

250

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

INCSTEP

= round [ ( ( 2

–

1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] f

VCO_OUT must be expressed in MHz.

With a modulation depth (md) = ± 2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP

= round [ ( ( 2

–

1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] =

126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized

= ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2

–

1 ) × PLLN )

As a result: md quantized

= ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2

–

1 ) × 240 ) =

2.002%(peak)

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STM32F411xC STM32F411xE Electrical characteristics

Figure 28

and

Figure 29 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

PLL_OUT

nominal.

T mode

is the modulation period.

md is the modulation depth.

Figure 28. PLL output clock waveforms in center spread mode

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TMODE XTMODE

4IME

Figure 29. PLL output clock waveforms in down spread mode

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)

[PG

WPRGH [WPRGH

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DLE

Symbol

Flash memory

The characteristics are given at T

= - 40 to 125 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Parameter

Supply current

Table 44. Flash memory characteristics

Conditions Min

Write / Erase 8-bit mode, V

= 1.7 V

Write / Erase 16-bit mode, V

= 2.1 V

Write / Erase 32-bit mode, V

= 3.3 V -

Typ

Max

Unit mA

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Electrical characteristics STM32F411xC STM32F411xE

Symbol

Table 45. Flash memory programming

Parameter Conditions t t prog

ERASE16KB

Word programming time

Sector (16 KB) erase time

Program/erase parallelism

(PSIZE) = x 8/16/32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32 t

ERASE64KB

Sector (64 KB) erase time

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8 t

ERASE128KB

Sector (128 KB) erase time

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

V t

ME prog

Mass erase time

Programming voltage

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

32-bit program operation

16-bit program operation

8-bit program operation

1. Guaranteed by characterization results.

2. The maximum programming time is measured after 100K erase operations.

Min

(1)

2.7

2.1

1.7

Typ Max

(1)

Unit

16 100

(2)

400

300

250

1.3

5.5

800

600

500

1200 2400

700 1400

550 1100

2.6

3.6

µs ms ms s s

Symbol

Table 46. Flash memory programming with V

PP voltage

Parameter Conditions

Min

(1)

Typ Max

(1)

Double word programming 16 100

(2) t prog t

ERASE16KB t

ERASE64KB t

ERASE128KB t

Sector (16 KB) erase time

Sector (64 KB) erase time

Sector (128 KB) erase time

Mass erase time

= 0 to +40 °C

= 3.3 V

= 8.5 V

230

490

875

3.50

Unit

µs ms s

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Table 46. Flash memory programming with V

PP voltage (continued)

Symbol Parameter Conditions Min (1) Typ Max (1) t

V prog

VPP

(3)

Programming voltage

voltage range

Minimum current sunk on the V

Cumulative time during which V

PP is applied

1. Guaranteed by design.

2. The maximum programming time is measured after 100K erase operations.

3. V

should only be connected during programming/erasing.

2.7

3.6

Unit

V mA hour

Table 47. Flash memory endurance and data retention

Value

Symbol Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= - 40 to + 85 °C (temp. range 6)

= - 40 to + 105 °C (temp. range 7)

= - 40 to + 125 °C (temp. range 3)

1 kcycle (2) at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycle

(2)

at T

= 55 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Unit kcycles

Years

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in

Table 49

. They are based on the EMS levels and classes defined in application note AN1709.

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Electrical characteristics STM32F411xC STM32F411xE

Symbol

FESD

EFTB

Table 48. EMS characteristics for LQFP100 package

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V

SS pins to induce a functional disturbance

= 3.3 V, LQFP100, WLCSP49,

= +25 °C, f

HCLK

= 100 MHz, conforms to IEC 61000-4-2

= 3.3 V, LQFP100, WLCSP49,

= +25 °C, f

HCLK

= 100 MHz, conforms to IEC 61000-4-4

Level/

Class

When the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,

PA2, on LQFP100 packages and PDR_ON on WLCSP49.

As a consequence, it is recommended to add a serial resistor (1 k Ω maximum) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than

50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

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EMI

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Table 49. EMI characteristics for LQFP100

Symbol Parameter Conditions

Peak level

= 3.6 V, T

= 25 °C, conforming to

IEC61967-2

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

Max vs.

HSE

CPU

]

8/84 MHz

3.5

Unit dBµV

6.3.14 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol Ratings

Table 50. ESD absolute maximum ratings

Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

= +25 °C conforming to JESD22-A114 2 2000

ESD(CDM)

Electrostatic discharge voltage (charge device model)

UFBGA100,

UFQFPN48

= +25 °C conforming to

ANSI/ESD STM5.3.1

WLCSP49

LQPF64,

LQFP100

500

400

250

1. Guaranteed by characterization results.

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Electrical characteristics STM32F411xC STM32F411xE

Symbol

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

Parameter

Static latch-up class

Table 51. Electrical sensitivities

Conditions

= + 125 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Symbol

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins

(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in

Table 52

Table 52. I/O current injection susceptibility

(1)

Functional susceptibility

Description Unit

Negative injection

Positive injection

INJ

Injected current on BOOT0 pin

Injected current on NRST pin

Injected current on PB3, PB4, PB5, PB6, PB7,

PB8, PB9, PC13, PC14, PC15, PH1, PDR_ON,

PC0, PC1,PC2, PC3, PD1, PD5, PD6, PD7, PE0,

PE2, PE3, PE4, PE5, PE6

Injected current on any other FT pin

Injected current on any other pins

1. NA = not applicable .

–0

–5

+5 mA

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Note:

Electrical characteristics

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

General input/output characteristics

Unless otherwise specified, the parameters given in Table 53

are derived from tests

performed under the conditions summarized in Table 14

. All I/Os are CMOS and TTL compliant.

Symbol

Table 53. I/O static characteristics

Parameter

FT, TC and NRST I/O input low level voltage

Conditions

1.7 V ≤ V

≤ 3.6 V

Min

BOOT0 I/O input low level voltage

1.75 V ≤ V

≤ 3.6 V,

-40 °C ≤ T

≤ 125 °C

1.7 V ≤ V

0 °C ≤ T

≤

3.6 V,

125 °C

FT, TC and NRST I/O input high level voltage (5)

1.7 V ≤ V

≤ 3.6 V

0.7V

)

BOOT0 I/O input high level voltage

1.75 V ≤ V

≤ 3.6 V,

-40 °C ≤ T

≤ 125 °C

1.7 V ≤ V

0 °C ≤ T

≤

3.6 V,

125 °C

0.17V

+0.7

FT, TC and NRST I/O input hysteresis

1.7 V ≤ V

≤ 3.6 V

HYS

I lkg

BOOT0 I/O input hysteresis

I/O input leakage current

(4)

I/O FT/TC input leakage current

(5)

1.75 V ≤ V

≤ 3.6 V,

-40 °C ≤ T

≤ 125 °C

1.7 V ≤ V

0 °C ≤ T

≤

3.6 V,

125 °C

≤ V

= 5 V -

Typ Max

10% V

(3)

100

0.3V

(1)

0.1V

± 1

+0.1

Unit

V mV

µA

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Electrical characteristics STM32F411xC STM32F411xE

Symbol

Table 53. I/O static characteristics (continued)

Parameter Conditions Min Typ Max Unit

Weak pull-up equivalent resistor

(6)

All pins except for

PA10

(OTG_FS_ID)

= V

30 40 50

PA10

(OTG_FS_ID)

7 10 14 k Ω

Weak pull-down equivalent resistor

(7)

All pins except for

PA10

(OTG_FS_ID)

= V

30 40 50

PA10

(OTG_FS_ID)

7 10 14

(8)

I/O pin capacitance 5 -

1. Guaranteed by test in production.

2. Guaranteed by design.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 52: I/O current injection susceptibility

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 52: I/O current injection susceptibility

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order).

8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT and TC I/Os is shown in Figure 30

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Figure 30. FT/TC I/O input characteristics

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or source up to ± 20 mA (with a relaxed V

) except PC13, PC14 and PC15 which can sink or source up to ± 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

. In particular:

• The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

Σ I

VDD

(see

Table 12 ).

DD, plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

Σ I

VSS

(see

Table 12 ).

plus the maximum Run

cannot exceed the absolute maximum rating

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Electrical characteristics STM32F411xC STM32F411xE

Output voltage levels

Unless otherwise specified, the parameters given in Table 54

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 14 . All I/Os are CMOS and TTL compliant.

Symbol

Table 54. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= +8 mA

2.7 V ≤ V

≤

TTL port

(2)

=+8 mA

2.7 V ≤

3.6 V

–0.4

2.4

0.4

(1)

(3)

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

2.7 V

1.8 V

1.7 V

= +20 mA

≤

3.6 V

= +6 mA

≤

= +4 mA

≤

3.6 V

–1.3

(4)

–0.4

(4)

–0.4

(5)

1.3

0.4

(4)

(5)

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 12 .

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

current sourced by the device must always respect the absolute maximum rating specified in

Table 12 and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Guaranteed by characterization results.

5. Guaranteed by design.

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Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 31 and

Table 55 , respectively.

Unless otherwise specified, the parameters given in Table 55

are derived from tests performed under the ambient temperature and V

DD in

Table 14 .

supply voltage conditions summarized

Table 55. I/O AC characteristics (1)(2)

OSPEEDRy

[1:0] bit value (1)

Symbol Parameter Conditions Min Typ Max Unit

00 f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50 pF, V

≥ 2.70 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 50

3.6 V pF, V

= 1.7 V to

100

MHz ns

10 f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50 pF, V

≥ 2.70 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 50 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.70 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.70 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

(4)

100

(4)

12.5

MHz ns

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Electrical characteristics STM32F411xC STM32F411xE

Table 55. I/O AC characteristics (1)(2) (continued)

OSPEEDRy

[1:0] bit value

(1)

Symbol Parameter Conditions Min Typ Max Unit

F max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 30 pF, V

≥ 2.70 V

= 30 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.70 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.70 V

= 10 pF, V

≥ 1.7 V

100

(4)

2.5

MHz ns

EXTIpw

Pulse width of external signals detected by the EXTI controller

10 ns

1. Guaranteed by characterization results.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.

3. The maximum frequency is defined in

Figure 31

4. For maximum frequencies above 50 MHz and V

> 2.4 V, the compensation cell should be used.

Figure 31. I/O AC characteristics definition

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The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 53 ).

Unless otherwise specified, the parameters given in Table 56

are derived from tests performed under the ambient temperature and V

supply voltage conditions summarized in

Table 14 . Refer to

Table 53: I/O static characteristics for the values of VIH and VIL for

NRST pin.

Symbol Parameter

Table 56. NRST pin characteristics

Conditions Min Typ Max

F(NRST)

(2)

NF(NRST)

(2)

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse

NRST Input not filtered pulse

NRST_OUT

Generated reset pulse duration

= V

> 2.7 V

Internal Reset source

300

100

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)

2. Guaranteed by design.

Unit k Ω ns ns

µs

Figure 32. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 56 . Otherwise the reset is not taken into account by the device.

IL(NRST)

max level specified in

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Electrical characteristics STM32F411xC STM32F411xE

The parameters given in

Table 57 are guaranteed by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 57. TIMx characteristics

(1)(2)

Parameter Conditions

(3) Min Max Unit t res(TIM) f

EXT

Timer resolution time f

AHB/APBx prescaler=1 or 2 or 4, f

TIMxCLK

100 MHz

AHB/APBx prescaler>4,

TIMxCLK

= 100 MHz

Timer external clock frequency on CH1 to CH4 f

TIMxCLK

= 100 MHz

Timer resolution

11.9

0 f

TIMxCLK

/2 t t

TIMxCLK ns

MHz

Res

TIM

16/32 bit t

COUNTER

16-bit counter clock period when internal clock is selected f

TIMxCLK

= 100 MHz 0.0119

780 µs t

MAX_COUNT

Maximum possible count with 32-bit counter f

TIMxCLK

= 100 MHz -

65536 ×

65536

51.1

TIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise

TIMxCLK >= 4x PCLKx.

I

C interface characteristics

The I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD disabled, but is still present.

The I

C characteristics are described in

Table 58

. Refer also to

Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

The I 2 C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400 kHz). The I 2 C bus frequency can be increased up to 1 MHz. For more details about the complete solution, please contact your local ST sales representative.

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STM32F411xC STM32F411xE Electrical characteristics

Symbol Parameter

Table 58. I 2 C characteristics

Standard mode

(1)(2)

Min Max

Fast mode I

(1)(2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

3450

1000

300

(3)

1.3

0.6

100

900

(4)

300

µs ns t t t su(STA) su(STO) w(STO:STA) t

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Pulse width of the spikes that are suppressed by the analog filter for standard fast mode

4.0

4.7

4.0

4.7

0 50

(5)

0.6

0.6 -

0.6

1.3

0 50

(5)

µs

µs ns

C b

Capacitive load for each bus line

400 400 pF

1. Guaranteed by design.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I 2 achieve fast mode I clock.

C frequencies. It must be at least 4 MHz to

C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I

C fast mode

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

5. The minimum width of the spikes filtered by the analog filter is above t

(max)

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123

Electrical characteristics STM32F411xC STM32F411xE

Figure 33. I 2 C bus AC waveforms and measurement circuit

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1. R

= series protection resistor.

2. R

= external pull-up resistor.

3. V

DD_I2C

is the I2C bus power supply.

Table 59. SCL frequency (f

PCLK1

= 50 MHz, V

= V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

= 4.7 k Ω

400

300

200

100

0x8019

0x8021

0x8032

0x0096

50 0x012C

20 0x02EE

1. R

= External pull-up resistance, f

SCL

= I

C speed

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ± 5%. For other speed ranges, the tolerance on the achieved speed is ± 2%. These variations depend on the accuracy of the external components used to design the application.

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STM32F411xC STM32F411xE Electrical characteristics t w(SCKH) t w(SCKL) t su(NSS) t h(NSS) t su(MI) t su(SI) t h(MI) t h(SI)

Symbol f

SCK

1/t c(SCK)

Duty(SCK)

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 60

for the SPI interface are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

supply voltage conditions summarized in Table 14 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

Parameter

Table 60. SPI dynamic characteristics

(1)

Conditions

SPI clock frequency

Master full duplex/receiver mode,

2.7 V < V

< 3.6 V

SPI1/4/5

Master full duplex/receiver mode,

3.0 V < V

< 3.6 V

SPI1/4/5

Master transmitter mode

1.7 V < V

< 3.6 V

SPI1/4/5

Master mode

1.7 V < V

< 3.6 V

SPI1/2/3/4/5

Slave transmitter/full duplex mode

2.7 V < V

< 3.6 V

SPI1/4/5

Slave receiver mode,

1.8 V < V

< 3.6 V

SPI1/4/5

Slave mode,

1.8 V < V

< 3.6 V

SPI1/2/3/4/5

Duty cycle of SPI clock frequency

Slave mode

Min

Typ

Max

(2)

Unit

MHz

SCK high and low time Master mode, SPI presc = 2

NSS setup time

NSS hold time

Data input setup time

Data input hold time

Slave mode, SPI presc = 2

Master mode

Slave mode

Master mode

Slave mode

PCLK

− 1.5

PCLK

2.5

7.5

3.5

PCLK

+1.5

ns ns ns ns ns ns ns

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123

Electrical characteristics STM32F411xC STM32F411xE

Symbol

Table 60. SPI dynamic characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit t a(SO

) t dis(SO)

Data output access time Slave mode

Data output disable time Slave mode

12 ns ns t t v(SO) h(SO)

Data output valid time

Slave mode (after enable edge),

2.7 V < V

< 3.6 V

Slave mode (after enable edge),

1.7 V < V

< 3.6 V

Data output hold time

Slave mode (after enable edge),

1.7 V < V

< 3.6 V

Data output valid time Master mode (after enable edge)

18.5

ns ns ns t v(MO) t h(MO)

Data output hold time Master mode (after enable edge)

ns ns

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t v(SO)

and t su(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having t su(MI)

= 0 while Duty(SCK) = 50%

Figure 34. SPI timing diagram - slave mode and CPHA = 0

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STM32F411xC STM32F411xE Electrical characteristics

Figure 35. SPI timing diagram - slave mode and CPHA = 1 (1)

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Figure 36. SPI timing diagram - master mode (1)

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DocID026289 Rev 7

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123

Electrical characteristics STM32F411xC STM32F411xE

I

S interface characteristics

Unless otherwise specified, the parameters given in Table 61

for the I 2 S interface are derived from tests performed under the ambient temperature, f

PCLKx frequency and V

supply voltage conditions summarized in Table 14 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CK, SD, WS).

Symbol Parameter

Table 61. I

S dynamic characteristics

(1)

Conditions f

MCK f

CK t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

I2S Main clock output

I2S clock frequency

Master data: 32 bits

Slave data: 32 bits

I2S clock frequency duty cycle Slave receiver

WS valid time Master mode

WS hold time

WS setup time

WS hold time

Master mode

Slave mode

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency).

2.5

1.5

Min Max

256x8K 256xFs (2)

64xFs

2 -

Unit

MHz

% ns

Note: Refer to the I2S section of RM0383 reference manual for more details on the sampling frequency (F

). f

MCK

, f

, and D

values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. D

depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of

(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F

S maximum value is supported for each mode/condition.

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STM32F411xC STM32F411xE Electrical characteristics

Figure 37. I 2 S slave timing diagram (Philips protocol) (1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 38. I

S master timing diagram (Philips protocol)

(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

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123

Electrical characteristics

Note:

STM32F411xC STM32F411xE

USB OTG full speed (FS) characteristics

This interface is present in USB OTG FS controller.

Symbol

Table 62. USB OTG FS startup time

Parameter t

STARTUP

(1)

USB OTG FS transceiver startup time

1. Guaranteed by design.

Max

Unit

µs

Symbol

Table 63. USB OTG FS DC electrical characteristics

Parameter Conditions Min.

(1)

Typ. Max.

(1)

Unit

Input levels

USB OTG FS operating voltage

(3) Differential input sensitivity

(3)

Differential common mode range

I(USB_FS_DP/DM)

Includes V

DI range

3.0

(2)

0.2

0.8

3.6

2.5

(3)

Single ended receiver threshold

1.3

2.0

Output levels

Static output level low

Static output level high

of 1.5

k Ω to 3.6 V

(4)

of 15 k Ω to V

(4)

2.8

0.3

3.6

PA11, PA12

(USB_FS_DM/DP)

17 21 24

= V

PA9 (OTG_FS_VBUS) 0.65

1.1

2.0

PA11, PA12

(USB_FS_DM/DP)

= V

1.5

1.8

2.1

PA9 (OTG_FS_VBUS) V

= V

0.25

0.37

0.55

1. All the voltages are measured from the local ground potential.

2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V V

voltage range.

3. Guaranteed by design.

4. R

is the load connected on the USB OTG FS drivers.

V k Ω

When VBUS sensing feature is enabled, PA9 should be left at their default state (floating input), not as alternate function. A typical 200 µA current consumption of the embedded sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 when the feature is enabled.

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STM32F411xC STM32F411xE Electrical characteristics

Figure 39. USB OTG FS timings: definition of data signal rise and fall time

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Table 64. USB OTG FS electrical characteristics

(1)

Driver characteristics

Symbol

Rise time

(2)

Fall time

(2)

Parameter Conditions

= 50 pF

= 50 pF t r

/t f

Min Max t r t f t rfm

CRS

Rise/ fall time matching

Output signal crossover voltage

1.3

110

2.0

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

Unit ns ns

Unless otherwise specified, the parameters given in Table 65

are derived from tests performed under the ambient temperature, f

conditions summarized in Table 14

PCLK2 frequency and V

DDA

supply voltage

Symbol

DDA

REF+ f

ADC f

TRIG

(2)

AIN

(2)

Parameter

Power supply

Positive reference voltage

ADC clock frequency

External trigger frequency

Conversion voltage range

(3)

Table 65. ADC characteristics

Conditions

DDA

− V

REF+

< 1.2 V

DDA

= 1.7

(1)

to 2.4 V

DDA

= 2.4 to 3.6 V f

ADC

= 30 MHz,

12-bit resolution

Min

1.7

(1)

1.7

(1)

0.6

0 (V

SSA or V

REFtied to ground)

External input impedance

See Equation 1 for details

ADC

(2)(4)

Sampling switch resistance

ADC

(2)

Internal sample and hold capacitor

Typ

Max

3.6

DDA

1764

REF+

Unit

MHz

MHz kHz

1/f

ADC

V k Ω k Ω pF

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Electrical characteristics STM32F411xC STM32F411xE

I t

Symbol t t t t

CONV

f lat

latr

STAB

Parameter

Table 65. ADC characteristics (continued)

Conditions Min Typ Max

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time

Sampling rate

ADC

= 30 MHz, and t

= 3 ADC cycles) f f f

ADC

= 30 MHz

= 30 MHz f

ADC

= 30 MHz

12-bit resolution f

ADC

= 30 MHz

10-bit resolution

0.50

0.43

16.40

16.34

Total conversion time (including sampling time) f

ADC

= 30 MHz

8-bit resolution f

ADC

= 30 MHz

6-bit resolution

0.37

0.30

16.27

16.20

9 to 492 (t

for sampling +n-bit resolution for successive approximation)

12-bit resolution

Single ADC

12-bit resolution

Interleave Dual ADC mode

12-bit resolution

Interleave Triple ADC mode

0.100

3.75

0.100

(5)

0.067

(5)

480

ADC V

REF

DC current consumption in conversion mode

ADC V

DDA

DC current consumption in conversion mode

300

1.6

500

1.8

1. V

DDA

minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to

Section 3.15.2:

Internal reset OFF ).

2. Guaranteed by characterization results.

3. V

REF+

is internally connected to V

DDA

and V

REF-

is internally connected to V

SSA

4. R

ADC

maximum value is given for V

=1.7 V, and minimum value for V

=3.3 V.

5. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in Table 65 .

Unit

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

Msps

µA mA

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STM32F411xC STM32F411xE Electrical characteristics

Equation 1: R

AIN

max formula

AIN

=

ADC

(

C k 0.5

ADC

× ln

)

( 2

N +

)

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.

Symbol

Table 66. ADC accuracy at f

ADC

= 18 MHz (1)

Parameter Test conditions Typ Max

(2)

Unit

ET Total unadjusted error ±3 ±4

EO Offset error

EG Gain error

ED Differential linearity error

EL Integral linearity error

V f

ADC

DDA

REF

DDA

− V

=18 MHz

= 1.7 to 3.6 V

REF

< 1.2 V

±2

±1

±2

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization results.

±3

±2

±3

LSB

Symbol

Table 67. ADC accuracy at f

ADC

= 30 MHz (1)

Parameter Test conditions Typ Max

(2)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

AIN

REF

= 30 MHz,

< 10 k Ω ,

DDA

= 2.4 to 3.6 V,

= 1.7 to 3.6 V,

DDA

− V

REF

< 1.2 V

±2

±1.5

±1

±1.5

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization results.

±5

±2.5

±4

±2

±3

Unit

LSB

Symbol

Table 68. ADC accuracy at f

ADC

= 36 MHz (1)

Parameter Test conditions Typ Max

(2)

ET Total unadjusted error ±4 ±7

EO Offset error

EG Gain error

ED Differential linearity error

EL Integral linearity error f

ADC

DDA

=36 MHz,

DDA

= 2.4 to 3.6 V,

REF

= 1.7 to 3.6 V

− V

REF

< 1.2 V

±2

±3

±2

±3

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Guaranteed by characterization results.

±3

±6

±3

±6

Unit

LSB

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123

Electrical characteristics STM32F411xC STM32F411xE

Symbol

Table 69. ADC dynamic accuracy at f

ADC

= 18 MHz - limited test conditions (1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

Total harmonic distortion

1. Guaranteed by characterization results.

ADC

=18 MHz

DDA

= V

REF+

= 1.7 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.3

10.4

64 64.2

-72

-67

Symbol

Table 70. ADC dynamic accuracy at f

ADC

= 36 MHz - limited test conditions (1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to noise and distortion ratio

Signal-to noise ratio

Total harmonic distortion

1. Guaranteed by characterization results.

ADC

= 36 MHz

DDA

= V

REF+

= 3.3 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.6

10.8

-72

-70

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 6.3.16

does not affect the ADC accuracy.

and Σ I

INJ(PIN)

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STM32F411xC STM32F411xE Electrical characteristics

Figure 40. ADC accuracy characteristics

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6$$!

1. See also Table 67 .

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E

= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

Figure 41. Typical connection diagram using the ADC

AIC

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1. Refer to Table 65 for the values of R

AIN

, R

ADC

and C

ADC

2. C f parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5

ADC

should be reduced.

pF). A high C parasitic

value downgrades conversion accuracy. To remedy this,

DocID026289 Rev 7

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123

Electrical characteristics STM32F411xC STM32F411xE

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 42

Figure 43

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 42. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

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1. V

REF+

and V

REF-

REF- inputs are both available on UFBGA100. V

REF+ is also available on LQFP100. When are not available, they are internally connected to V

DDA and V

SSA

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STM32F411xC STM32F411xE Electrical characteristics

Figure 43. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

670)

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1. V

REF+

and V

REF-

REF- inputs are both available on UFBGA100. V

REF+ is also available on LQFP100. When are not available, they are internally connected to V

DDA and V

SSA

6.3.21 Temperature sensor characteristics

DLF

Table 71. Temperature sensor characteristics

Symbol Parameter Min Typ Max

(1)

Avg_Slope

(1)

START

(2)

S_temp

(2)

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature (1 °C accuracy)

1. Guaranteed by characterization results.

2. Guaranteed by design.

± 1

2.5

0.76

± 2

Unit

°C mV/°C

µs

Symbol

Table 72. Temperature sensor calibration values

Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V

DDA

= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D

TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V

DDA

= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

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123

Electrical characteristics STM32F411xC STM32F411xE

6.3.22 V

BAT

monitoring characteristics

Symbol

Table 73. V

BAT

monitoring characteristics

Parameter Min

(1)

S_vbat

(2)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1 mV accuracy

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

–1

Typ

Max

Unit

K Ω

µs

The parameters given in

Table 74 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Table 14 .

Symbol

Table 74. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

REFINT

S_vrefint

(1)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

- 40 °C < T

< + 125 °C

RERINT_s

(2)

Internal reference voltage spread over the temperature range

= 3V ± 10mV

Coeff

(2) t

START

(2)

Temperature coefficient

Startup time -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1.18

1.21

1.24

µs mV ppm/°C

µs

Symbol

REFIN_CAL

Table 75. Internal reference voltage calibration values

Parameter Memory address

Raw data acquired at temperature of

30 °C V

DDA

= 3.3 V

0x1FFF 7A2A - 0x1FFF 7A2B

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6.3.24 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 76

for the SDIO/MMC/eMMC interface are derived from tests performed under the ambient temperature, f

PCLK2 and V

frequency

supply voltage conditions summarized in Table 14

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF (for eMMC C = 20 pF)

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output

characteristics.

Figure 44. SDIO high-speed mode

Figure 45. SD default mode

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123

Electrical characteristics STM32F411xC STM32F411xE

Symbol

Table 76. Dynamic characteristics: SD / MMC characteristics (1)(2)

Parameter Conditions f

Clock frequency in data transfer mode

W(CKL) t

W(CKH)

SDIO_CK/fPCLK2 frequency ratio

Clock low time

Clock high time

fpp = 50 MHz fpp = 50 MHz

CMD, D inputs (referenced to CK) in MMC and SD HS mode

Min

10.5

8.5

Typ

2.5

t t

ISU

Input setup time HS

Input hold time HS fpp = 50 MHz fpp = 50 MHz

-40°C<T

< 125°C fpp = 50 MHz

-40°C<T

<+85°C

CMD, D outputs (referenced to CK) in MMC and SD HS mode t

OV t

Output valid time HS

Output hold time HS fpp = 50 MHz fpp = 50 MHz

CMD, D inputs (referenced to CK) in SD default mode t

ISUD t

IHD

Input setup time SD

Input hold time SD fpp = 25 MHz fpp = 25 MHz

CMD, D outputs (referenced to CK) in SD default mode t

OVD t

OHD

Output valid default time SD

Output hold default time SD

1. Guaranteed by characterization results.

2. V

= 2.7 to 3.6 V.

fpp =25 MHz fpp =25 MHz

2.5

4.5

3.5

Max

8/3

5.5

Unit

MHz

ns ns ns ns ns

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STM32F411xC STM32F411xE Electrical characteristics

Symbol

Table 77. Dynamic characteristics: eMMC characteristics V

= 1.7 V to 1.9 V

(1)(2)

Parameter Conditions Min Typ Max f

Clock frequency in data transfer mode

SDIO_CK/fPCLK2 frequency ratio t

W(CKL) t

W(CKH)

Clock low time

Clock high time

CMD, D inputs (referenced to CK) in eMMC mode

fpp = 50 MHz fpp = 50 MHz t

ISU t

Input setup time HS

Input hold time HS

CMD, D outputs (referenced to CK) in eMMC mode fpp = 50 MHz fpp = 50 MHz

10.5

9.5

8/3

OV t

Output valid time HS

Output hold time HS

1. Guaranteed by characterization results.

2. C load

= 20 pF fpp = 50 MHz fpp = 50 MHz

3.5

Unit

MHz

ns ns ns

Symbol

Table 78. RTC characteristics

Parameter Conditions f

PCLK1

/RTCCLK frequency ratio

Any read/write operation from/to an RTC register

Min

Max

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123

Package information STM32F411xC STM32F411xE

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Figure 46. WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale package outline

BBB :

!BALLLOCATION

$ETAIL!

E %

3IDEVIEW

"UMPSIDE

&RONTVIEW

"UMP

EEE :

124/149

!ORIENTATION

REFERENCE

AAA

7AFERBACKSIDE

1. Drawing is not to scale.

DocID026289 Rev 7

CCC : 8 9

DDD

.OTE

$ETAIL!

ROTATED

3EATINGPLANE

.OTE

!:6?-%?6

STM32F411xC STM32F411xE Package information

Table 79. WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e2

G aaa bbb ccc ddd eee e e1

(2) b

(3)

0.525

0.220

2.964

3.150

0.555

0.175

0.380

0.025

0.250

2.999

3.185

0.400

2.400

0.2995

0.3925

0.100

0.050

0.585

0.280

3.034

3.220

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0207

0.0087

0.1167

0.1240

0.0157

0.0945

0.0118

0.0155

0.0039

0.0020

0.0219

0.0069

0.0150

0.0010

0.0098

0.1181

0.1254

0.0230

0.0110

0.1194

0.1268

Figure 47. WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale recommended footprint

'SDG

'VP

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069

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141

Package information STM32F411xC STM32F411xE

Table 80. WLCSP49 recommended PCB design rules (0.4 mm pitch)

Dimension Recommended values

Pitch

Dpad

Dsm

PCB pad design

0.4 mm

260 µm max. (circular)

220 µm recommended

300 µm min. (for 260 µm diameter pad)

Non-solder mask defined via underbump allowed

Device marking for WLCSP49

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 48. WLCSP49 marking (package top view)

%DOO

LQGHQWLILHU

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(&(%

5HYLVLRQFRGH

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06Y9

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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7.2 UFQFPN48 package information

Package information

Figure 49. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

3LQLGHQWLILHU

ODVHUPDUNLQJDUHD

( (

H E

'HWDLO<

GGG

6HDWLQJ

SODQH

([SRVHGSDG

DUHD

SLQFRUQHU

'HWDLO=

5W\S

(

Symbol

$%B0(B9

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

Table 81. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Min.

0.500

0.000

6.900

5.500

Typ.

0.550

0.020

7.000

5.600

Max.

0.600

0.050

7.100

5.700

Min.

0.0197

0.0000

0.2717

0.2165

Typ.

0.0217

0.0008

0.2756

0.2205

Max.

0.0236

0.0020

0.2795

0.2244

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Package information STM32F411xC STM32F411xE

Table 81. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

T b e ddd

5.500

0.300

0.200

5.600

0.400

0.152

0.250

0.500

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.2165

0.0118

0.0079

Typ.

0.2205

0.0157

0.0060

0.0098

0.0197

Max.

0.2244

0.0197

0.0118

0.0031

Figure 50. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat recommended footprint

1. Dimensions are in millimeters.

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STM32F411xC STM32F411xE Package information

Device marking for UFQFPN48

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 51. UFQFPN48 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

670)

&(8

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< ::

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LQGHQWLILHU

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141

Package information

7.3 LQFP64 package information

STM32F411xC STM32F411xE

Figure 52. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

6($7,1*3/$1(

*$8*(3/$1(

FFF &

' /

130/149

3,1

,'(17,),&$7,21

:B0(B9

D1 b c

1. Drawing is not to scale.

Table 82. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

Typ

1.400

0.220

12.000

10.000

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

Min

0.0020

0.0531

0.0067

0.0035

Typ

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

Max

0.0630

0.0059

0.0571

0.0106

0.0079

DocID026289 Rev 7

STM32F411xC STM32F411xE Package information

Table 82. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 ccc

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

Max

7°

0.0295

0.0031

Figure 53. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint

AIC

1. Dimensions are expressed in millimeters.

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141

Package information STM32F411xC STM32F411xE

Device marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 54. LQFP64 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

5HYLVLRQFRGH

670)

5(7

'DWHFRGH

< ::

3LQ

LQGHQWLILHU

06Y9

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7.4 LQFP100 package information

Package information

Figure 55. LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package outline

3%!4).'0,!.%

'!5'%0,!.%

CCC #

, +

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

,?-%?6

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141

Package information STM32F411xC STM32F411xE

Table 83. LQPF100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

K ccc

D1 b c

0.050

1.350

0.170

0.090

15.800

13.800

15.800

13.800

0.450

0.0°

1.40

0.220

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.600

1.000

3.5°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

16.200

14.200

0.750

7.0°

1.60

0.150

1.450

0.270

0.200

16.200

14.200

0.622

0.5433

0.0177

0.0°

0.002

0.0531

0.0067

0.0035

0.622

0.5433

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

0.0031

0.0551

0.0087

0.6299

0.5512

0.6378

0.5591

0.0295

7.0°

0.063

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

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STM32F411xC STM32F411xE Package information

Figure 56. LQFP100 - 100-pin, 14 x 14 mm, 100-pin low-profile quad flat recommended footprint

AIC

1. Dimensions are in millimeters.

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141

Package information STM32F411xC STM32F411xE

Device marking for LQFP100

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 57. LQPF100 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

(6)

9(7$

'DWHFRGH

< ::

2SWLRQDOJDWHPDUN

5HYLVLRQFRGH

3LQ

LQGHQWLILHU

06Y9

1. Parts marked Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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7.5 UFBGA100 package information

Package information

Figure 58. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball

grid array package outline

= 6HDWLQJSODQH

$ $

(

)

GGG =

$ $

$EDOO

LGHQWLILHU

$EDOO

LQGH[DUHD

;

(

)

' '

%277209,(:

EEDOOV

HHH 0 = < ;

III 0 =

7239,(:

$&B0(B9

1. Drawing is not to scale.

Table 84. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043

A2 0.400 0.450 0.500 0.0157 0.0177 0.0197

A3 0.130 -

A4 0.270 0.320 0.370 0.0106 0.0126 0.0146

D1 5.450 5.500 5.550 0.2146 0.2165 0.2185

E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - -

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Package information STM32F411xC STM32F411xE

Table 84. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

ddd eee fff -

0.100

0.150

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0039

0.0059

0.0020

Figure 59. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint

'SDG

'VP

069

Pitch

Dpad

Dsm

Table 85. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)

Dimension Recommended values

Solder paste

0.5

0.27 mm

0.35 mm typ. (depends on the soldermask registration tolerance)

0.27 mm aperture diameter.

Non-solder mask defined (NSMD) pads are recommended.

2. 4 to 6 mils solder paste screen printing process.

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STM32F411xC STM32F411xE Package information

Device marking for UFBGA100

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 60. UFBGA100 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

(6)

9(,

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DocID026289 Rev 7

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141

Package information STM32F411xC STM32F411xE

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 14: General operating conditions on page 59 .

The maximum chip-junction temperature, T

J using the following equation:

max., in degrees Celsius, may be calculated

max = T

max + (PD max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

• PD max is the sum of P

INT

max and P

I/O max (PD max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 86. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

UFQFPN48

Thermal resistance junction-ambient

WLCSP49

Thermal resistance junction-ambient

LQFP64

Thermal resistance junction-ambient

LQFP100

Thermal resistance junction-ambient

UFBGA100

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

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STM32F411xC STM32F411xE Ordering information

Table 87. Ordering information scheme

Example: STM32 F 411 C E Y 6 TR

Device family

STM32 = Arm

-based 32-bit microcontroller

Product type

F = General-purpose

Device subfamily

411 = 411 family

Pin count

C = 48/49 pins

R = 64 pins

V = 100 pins

Flash memory size

C = 256 Kbytes of Flash memory

E = 512 Kbytes of Flash memory

Package

H = UFBGA

T = LQFP

U = UFQFPN

Y = WLCSP

Temperature range

6 = Industrial temperature range, - 40 to 85 °C

7 = Industrial temperature range, - 40 to 105 °C

3 = Industrial temperature range, - 40 to 125 °C

Packing

TR = tape and reel

No character = tray or tube

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141

Recommendations when using the internal reset OFF STM32F411xC STM32F411xE

Appendix A Recommendations when using the internal reset OFF

When the internal reset is OFF, the following integrated features are no longer supported:

• The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled.

• The brownout reset (BRO) circuitry must be disabled. By default BOR is OFF.

• The embedded programmable voltage detector (PVD) is disabled.

• V

BAT

functionality is no more available and VBAT pin should be connected to V

Table 88. Limitations depending on the operating power supply range

Operating power supply range

ADC operation

Maximum

Flash memory access frequency with no wait state

Flashmax

)

Maximum

Flash memory access frequency with no wait states

(1) (2)

I/O operation

Possible

Flash memory operations

2.1 V

= 1.7 to

(3)

Conversion time up to

1.2 Msps

20 MHz (4)

100 MHz with

6 wait states

No I/O compensation

8-bit erase and program operations only

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.

3. V

DDA

minimum value of 1.7 V, with the use of an external power supply supervisor (refer to

Section 3.15.1: Internal reset ON ).

4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.

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Appendix B Application block diagrams

Application block diagrams

B.1 USB OTG Full Speed (FS) interface solutions

Figure 61. USB controller configured as peripheral-only and used in Full-Speed mode

9WR9 ''

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UHJXODWRU

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26&B287

9%86

9 66

069

1. The external voltage regulator is only needed when building a V

BUS

powered device.

Figure 62. USB controller configured as host-only and used in Full-Speed mode

9 ''

*3,2

*3,2,54

670)[&[(

2YHUFXUUHQW

&XUUHQWOLPLWHU

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93RZHU

26&B,1

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9 66

26&B287

069

1. The current limiter is required only if the application has to support a V switch can be used if 5V are available on the application board.

BUS

powered device. A basic power

DocID026289 Rev 7

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146

Application block diagrams STM32F411xC STM32F411xE

Figure 63. USB controller configured in dual mode and used in Full-Speed mode

9 ''

*3,2

*3,2,54

670)[&[(

26&B,1

26&B287

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YROWDJH

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069

1. The external voltage regulator is only needed when building a V

BUS

powered device.

2. The current limiter is required only if the application has to support a V switch can be used if 5 V are available on the application board.

BUS powered device. A basic power

3. The ID pin is required in dual role only.

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STM32F411xC STM32F411xE Application block diagrams

B.2

[*3,2

*3,2

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-7$*

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Sensor Hub application example

Figure 64. Sensor Hub application example

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146

Application block diagrams STM32F411xC STM32F411xE

Data is transferred through the DMA from interfaces into the internal SRAM while the rest of the MCU is set in low power mode.

• Code execution from RAM before switching off the Flash.

• Flash is set in power down and flash interface (ART™ accelerator) clock is stopped.

• The clocks are enabled only for the required interfaces.

• MCU core is set in sleep mode (core clock stopped waiting for interrupt).

• Only the needed DMA channels are enabled and running.

Figure 65. Batch Acquisition Mode (BAM) example

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069

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Revision history

Revision history

Date

19-Jun-2014

Revision

10-Sep-2014

27-Nov-2014

04-Feb-2015

Table 89. Document revision history

Changes

Initial release.

Introduced the BAM feature in

Features ,

Section 2: Description ., and

Section 3.3: Batch

Acquisition mode (BAM) .

Updated

Section 3.5: Embedded Flash memory

Section 3.14: Power supply schemes

and Section 3.18: Low-power modes ,

Section 3.20.2: General-purpose timers (TIMx)

and Section 3.30: Temperature sensor .

Modified

Table 8: STM32F411xC/xE pin definitions ,

Table 9: Alternate function mapping

and APB2 in

Table 10: STM32F411xC/xE register boundary addresses .

Modified Table 34: Low-power mode wakeup timings

(1)

Table 20: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

= 1.7 V

Table 21: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - V

= 3.6 V ,

Table 25: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - V

= 3.6 V

Table 26: Typical and maximum current consumption in Sleep mode - V

3.6 V and

Table 58: I

C characteristics and

Figure 33: I

C bus AC waveforms and

measurement circuit

Added

Figure 21: Low-power mode wakeup ,

Section Appendix A: Recommendations when using the internal reset OFF

and Section Appendix B: Application block diagrams .

Changed datasheet status to Production Data.

Updated

Table 31: Typical and maximum current consumptions in V

BAT

mode .

Section : On-chip peripheral current consumption

: changed HCLK frequency and

updated DMA1 and DMA2 current consumption in Table 33: Peripheral current consumption .

Updated

Table 55: I/O AC characteristics .

Updated THD in Table 69: ADC dynamic accuracy at f

ADC

= 18 MHz - limited test conditions and Table 70: ADC dynamic accuracy at f

ADC conditions .

= 36 MHz - limited test

Updated

Table 55: I/O AC characteristics .

Updated

Figure 46: WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale package outline

and

Figure 48: WLCSP49 marking (package top view) .

Added

Figure 47: WLCSP49 - 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale recommended footprint

and Table 80: WLCSP49 recommended PCB design rules

(0.4 mm pitch)

Updated

Figure 51: UFQFPN48 marking example (package top view) ,

Figure 54:

LQFP64 marking example (package top view)

Figure 57: LQPF100 marking example

(package top view)

, and

Figure 84: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data .

Added VPP alternate function for BOOT0 in

Table 8: STM32F411xC/xE pin definitions

Added TC inputs in Table 11: Voltage characteristics ,

Table 12: Current characteristics ,

Table 14: General operating conditions

Table 53: I/O static characteristics and

Figure 30: FT/TC I/O input characteristics

Updated V

ESD(CDM) in

Table 50: ESD absolute maximum ratings

A3 minimum and maximum values removed in Table 83: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data .

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148

Revision history STM32F411xC STM32F411xE

Date

21-Nov-2016

05-Dec-2016

14-Dec-2017

Revision

Table 89. Document revision history

Changes

Updated:

–

Features

–

Figure 1: Compatible board design for LQFP100 package

–

Figure 2: Compatible board design for LQFP64 package

–

Figure 3: STM32F411xC/xE block diagram

–

Figure 22: High-speed external clock source AC timing diagram

–

Figure 23: Low-speed external clock source AC timing diagram

–

Figure 33: I

C bus AC waveforms and measurement circuit

–

Figure 58: UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline

–

Table 2: STM32F411xC/xE features and peripheral counts

–

Table 8: STM32F411xC/xE pin definitions

–

Table 13: Thermal characteristics

–

Table 14: General operating conditions

– From Table 20: Typical and maximum current consumption, code with data processing

(ART accelerator disabled) running from SRAM - V

maximum current consumptions in V

BAT

mode

= 1.7 V

Table 31: Typical and

–

Table 35: High-speed external user clock characteristics

–

Table 36: Low-speed external user clock characteristics

–

Table 39: HSI oscillator characteristics

–

Table 47: Flash memory endurance and data retention

–

Table 51: Electrical sensitivities

–

Table 53: I/O static characteristics

–

Table 76: Dynamic characteristics: SD / MMC characteristics

–

Table 87: Ordering information scheme

Added:

–

One-time programmable bytes

–

Table 86: Package thermal characteristics

Updated:

–

Table 27: Typical and maximum current consumptions in Stop mode - V

= 1.7 V

–

Table 28: Typical and maximum current consumption in Stop mode - V

=3.6 V

–

Table 29: Typical and maximum current consumption in Standby mode - V

= 1.7 V

–

Table 30: Typical and maximum current consumption in Standby mode - V

= 3.6 V

Updated:

–

Table 27: Typical and maximum current consumptions in Stop mode - V

= 1.7 V

–

Table 28: Typical and maximum current consumption in Stop mode - V

=3.6 V

–

Table 29: Typical and maximum current consumption in Standby mode - V

= 1.7 V

–

Table 30: Typical and maximum current consumption in Standby mode - V

= 3.6 V

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DocID026289 Rev 7

STM32F411xC STM32F411xE

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