STMicroelectronics STDVE001A Datasheet
विज्ञापन
विज्ञापन
STDVE001A
Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer
Features
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Compatible with the high-definition multimedia interface (HDMI) v1.3 digital interface
Conforms to the transition minimized differential signaling (TMDS) voltage standard on input and output channels
340 MHz maximum clock speed operation supports all video formats with deep color at maximum refresh rates
3.4 Gbps data rate per channel
Fully automatic adaptive equalizer for cables lengths up to 25 m
Single supply V
CC
: 3.135 to 3.465 V
ESD: > ± 5 KV HBM for all TMDS I/Os
Integrated open-drain I
2
C buffer for display data channel (DDC)
5.3 V tolerant DDC and HPD I/Os
Lock-up free operation of I
2
C bus
0 to 400 kHz clock frequency for I
2
C bus
Low capacitance of all the channels
Equalizer regenerates the incoming attenuated
TMDS signal
TQFP48 QFN48
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Buffer drives the TMDS outputs over long PCB track lengths
Low output skew and jitter
Tight input thresholds reduce bit error rates
On-chip selectable 50 Ω input termination
Low ground bounce
Data and control inputs provide undershoot clamp diode
Demonstration kit is available
Table 1.
Device summary
Order code Operating temperature Package Packaging
STDVE001ABTR -40 °C to 85 °C TQFP48 Tape and reel
STDVE001AQTR -40 °C to 85 °C QFN48 Tape and reel Obsolete Product(s) - Obsolete Product(s)
30 August 2011 Doc ID 14855 Rev 5 1/48 www.st.com
48
STDVE001A Contents
Contents
C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC electrical characteristics (I
2
C repeater) . . . . . . . . . . . . . . . . . . . . . . . 25
DC electrical characteristics (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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STDVE001A
Contents
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Contents STDVE001A
List of tables
DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs . . . . . . . 22
2
C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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STDVE001A
List of figures
List of figures
C bus repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SK(O)
SK(P)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SK(D)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Test circuit for AC measurements (I
C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2
C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2
C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Description
1 Description
STDVE001A
The STDVE001A integrates a 4-channel 3.4 Gbps TMDS equalizer. High-speed data paths and flow-through pinout minimize the internal device jitter and simplify the board layout.
The equalizer overcomes the intersymbol interference (ISI) jitter effects from lossy cables.
The buffer/driver on the output can drive the TMDS output signals over long distances. In addition to this, STDVE001A integrates the 50 Ω termination resistor on all the input channels to improve performance and reduce board space. The device can be placed in a low-power mode by disabling the output current drivers. The STDVE001A is ideal for advanced TV and STB applications supporting HDMI/DVI standard. The differential signal from the HDMI/DVI ports can be routed through the STDVE001A to guarantee good signal quality at the HDMI receiver. Designed for very low skew, jitter and low I/O capacitance, the switch preserves the signal integrity to pass the stringent HDMI compliance requirements.
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STDVE001A
Figure 1.
STDVE001A block diagram
Block diagram
4-$3
DIFFERENTIAL
INPUTS
3$!?%84
3#,?%84
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($0?%84
)NPUT
TERMINATION
SELECTABLE
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RECEIVER
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DRIVER
TRANSMITTER
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REPEATER
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DRIVER
#%#?)/
4-$3
DIFFERENTIAL
OUTPUTS
3$!?).4
3#,?).4
($0?).4
#%#?)/?).4
!-6
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Block diagram STDVE001A
Figure 2.
Equalizer functional diagram (one signal pair)
%1?"//34
/%? .
TERMINATION
SELECTABLE
0REAMP %QUALIZER
02%
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1UANTIZER
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DRIVER
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CONTROL
Figure 3.
DDC I
2
C bus repeater
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3#,?%84 9?$$#?3#,
Obsolete Product(s) - Obsolete Product(s)
!-6
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STDVE001A Application diagram
Figure 4.
STDVE001A in a digital TV
$6$ 2
460#"BOARD
"ACKPANEL
($-)?" ($-)?#
PORT($-)RECEIVER
34"
34$6%!
($-)?!
&RONTPANELOFAHIGHEND 46
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CONSOLE
!-6
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Pin configuration
Figure 5.
Pin configuration (TQFP48 package)
STDVE001A
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Pin configuration STDVE001A
Figure 6.
Pin configuration (QFN48 package)
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Pin configuration STDVE001A
Table 2.
Pin number
3
4
5
1
2
6
7
8
9
Pin description
Pin name Type Function
GND
VCC
Power Ground
Power 3.3 V ± 5% DC supply
CEC_IO I/O CEC signal to/from the connector end
CEC_IO_INT I/O CEC signal to/from TV end
GND
REXT
SDA_EXT
SCL_EXT
Power Ground
Analog
Connect to GND through a 4.7 K Ω ± 1% precision reference resistor. Sets the output current to generate the output voltage compliant with TMDS.
HPD_EXT Output
0 to 5.0 V (nominal) output signal. Hot plug detector output. Open-drain output.
Connect an external resistor according to the HDMI specification.
I/O DDC data I/O. Pulled-up by external termination to V
CC
.
I/O DDC clock I/O. Pulled-up by external termination to V
CC
.
TMDS output deemphasis adjustment
10
11
12
13
14
15
16
17
18
19
PRE Output deemphasis
PRE Input
0 V 0 dB
3.3 V 3 dB
VDD_EXT Power DC supply for DDC, HPD and CEC (can be 5 V or 3.3 V or unconnected).
GND Power Ground
OUT_D4+ Output
HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal with OUT_D4-.
OUT_D4Output
HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output signal with OUT_D4+.
VCC Power 3.3 V ± 10% DC supply
OUT_D3+ Output
HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal with OUT_D3-.
OUT_D3Output
HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output signal with OUT_D3+.
GND Power Ground
OUT_D2+ Output
HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2-.
HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output signal
20 OUT_D2Output
21 VCC with OUT_D2+.
Power 3.3 V ± 10% DC supply
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal
22 OUT_D1+ Output with OUT_D1-.
23 OUT_D1Output
HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output signal with OUT_D1+.
GND Power Ground 24
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STDVE001A Pin configuration
Pin description (continued) Table 2.
Pin number
Pin name Type Function
25
26
27
28
29
30
31
32
33
OE_N
VDD_INT
GND
SCL_INT
SDA_INT
HPD_INT
GND
DDC_EN
VCC
Active low enable signal.
OE_N N_D termination IOUT_D outputs
Input
1
0
High-Z
50 Ω
High-Z
Active
Power DC supply for DDC, HPD and CEC (can be 5 V or 3.3 V or unconnected).
Power Ground
I/O DDC Clock I/O. Pulled-up by external termination to V
CC
.
I/O DDC Data I/O. Pulled-up by external termination to V
CC
.
Input
Sink side, low-frequency, 0 V to 5 V (nominal) hot plug detector input signal.
Voltage high indicates “plugged” state; voltage low indicates “unplugged” state.
High: 5 V power signal asserted from source to sink and EDID is ready.
Low: No 5 V power signal is asserted from source to sink or EDID is not ready.
Power Ground
Input I
2
C repeater enable signal
DDC_EN I
2
C repeater
0 V
3.3 V
Power 3.3 V ± 10% DC supply
TMDS input equalization selector (control pin).
Disabled, high-Z
Enabled, active
EQ_BOOST2 EQ_BOOST1 Setting at 825 MHz
34-35
36
37
38
EQ_BOOST1,
EQ_BOOST2
GND
GND
IN_D1-
Input
1
1
0
0
0
1
0
1
11 dB
9 dB
4 dB
16 dB
Power Ground
Power Ground
Input HDMI 1.3 compliant TMDS input. IN_D1- makes a differential pair with IN_D1+.
39 IN_D1+ Input HDMI 1.3 compliant TMDS input. IN_D1+ makes a differential pair with IN_D1-.
40 VCC Power 3.3 V ± 10% DC supply Obsolete Product(s) - Obsolete Product(s)
41 IN_D2Input HDMI 1.3 compliant TMDS input. IN_D2- makes a differential pair with IN_D2+.
42 IN_D2+ Input HDMI 1.3 compliant TMDS input. IN_D2+ makes a differential pair with IN_D2-.
43 GND Power Ground
44
45
46
47
48
IN_D3-
IN_D3+
VCC
IN_D4-
IN_D4+
Input HDMI 1.3 compliant TMDS input. IN_D3- makes a differential pair with IN_D3+.
Input HDMI 1.3 compliant TMDS input. IN_D3+ makes a differential pair with IN_D3-.
Power 3.3 V ± 10% DC supply
Input HDMI 1.3 compliant TMDS input. IN_D4- makes a differential pair with IN_D4+.
Input HDMI 1.3 compliant TMDS input. IN_D4+ makes a differential pair with IN_D4-.
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Functional description STDVE001A
The STDVE001A routes physical layer signals for high bandwidth digital video and is compatible with low voltage differential signaling standard like TMDS. The device passes the differential inputs from a video source to a common display when it is in the active mode of operation. The device conforms to the TMDS standard on both inputs and outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE001A result in a very small propagation delay. Additionally, it supports the DDC, HPD and CEC signaling.
The I
2
C interface of the enabled input port is linked to the I
2
C interface of the output port, and the hot plug detector (HPD) of the enabled input port is output to HPD_EXT.
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation from long or lossy transmission media. The inputs present high impedance when the device is not active or when V
CC
is absent or 0 V. In all other cases, the 50 Ω termination resistors on input channels are present.
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the gain stage of the equalizer to compensate the signal degradation and then the signals are driven on to the output ports.
The equalizer is fully adaptive and automatic in function providing smaller gain at low frequencies and higher gain at high frequencies. The default setting of EQ = 00 is recommended on EQ pins for optimized operation.
Table 3.
Freq (MHz)
Adaptive equalizer gain with frequency
Gain in dB
(EQ = 00)
Gain in dB
(EQ = 01)
225
325
410
825
1650
3
5
6.5
11
16
2
3
4.5
9
14
Gain in dB
(EQ = 10)
0
1
1.5
4
8.5
Gain in dB
(EQ = 11)
6.5
8.5
11
16
21.5
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STDVE001A
Figure 7.
STDVE001A gain vs. frequency
Gain v/s Freq (STDVE001A)
25
20
15
10
5
0
225 325 410
Freq (MHz)
825 1650
Functional description
Gain (EQ=00)
Gain (EQ=01)
Gain (EQ=10)
Gain (EQ=11)
The equalizer of STDVE001A is fully adaptive and automatic in function. The default setting of EQ = 00 is recommended for optimal operation. The equalizer performance is optimized for all frequencies over the cable lengths from 1 m to 25 m at EQ = 00. If cable lengths greater than 25 m are desired in application, then EQ = 11 setting is recommended. The other two EQ settings of 01 and 10 are provided simply for fine-tuning purposes and can be used for very short external cables or PCB traces only if deemed necessary.
Input termination
The STDVE001A integrates precise 50 Ω ± 5% termination resistors, pulled up to V
CC
, on all its differential input channels. External terminations are not required. This gives better performance and also minimizes the PCB board space. These on-chip termination resistors should match the differential characteristic impedance of the transmission line. Since the output driver consists of current steering devices, an output voltage is not generated without a termination resistor. Output voltage levels are dependent on the value of the total termination resistance. The STDVE001A produces TMDS output levels for point-to-point links that are doubly terminated (100 Ω at each end). With the typical 10 mA output current, the STDVE001A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a termination line terminated at each end. The input terminations are selectable thus saving power for the unselected ports.
Output buffers
Each differential output of the STDVE001A drives external 50 Ω load (pull-up resistor) and conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential current-steering devices.
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OE_N = H or the device is not powered. The current steering architecture requires a resistive load to terminate the signal to complete the transmission loop from V
CC
to GND through the termination resistor. Because the device switches the direction of the current flow and not voltage levels, the output voltage swing is determined by V
CC
minus the voltage drop across the termination resistor. The output current drivers are controlled by the OE_N pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate internal current mirrors of a stable reference current which is generated by bandgap voltage across the R
EXT
. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.
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Functional description STDVE001A
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point communication over a tightly controlled impedance medium. The TMDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
Table 4.
OE_N operating modes
Input Output
Function
OE_N
L
L
H
H
L
X
L
H
X
H
L
Hi-Z
OUT-
L
H
Hi-Z
Active mode
Active mode
Low power mode
The OE_N input activates a hardware power down mode. When the power down mode is active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off and disabled.
Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a delay associated with turning on band-references and input/output buffer circuits.
Note that the OE_N pin is only used to disable the TMDS paths in the chip to same maximum amount of current. It does not affect the HPD, DDC and CEC portions. The DDC is controlled only by the DDC_EN pin whereas the HPD and CEC are always active as long as the supply to the chip is present.
The input pin HPD_INT is 5 V tolerant, allowing direct connection to 5 V signals. The output
HPD pin has open-drain structure so that the disabled HPD output is driven to GND whereas the enabled HPD port has the same polarity as the HPD_INT. Note that the HPD output should have an external pull-up resistor connected to +5 V from the HDMI source.
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The DDC channels are designed together with a bi-directional buffer so as to ensure the voltage levels on the I
2
C lines are met even after long capacitive cables. This feature eliminates the errors during EDID and HDCP reading.
5.5 I
2
C DDC line repeater
The device contains two identical bi-directional open-drain, non-inverting buffer circuits that enable I
2
C DDC bus lines to be extended without degradation in system performance. The
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STDVE001A Functional description
STDVE001A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I
2
C bus, while retaining all the operating modes and features of the I
2
C system. This enables two buses of 400 pF bus capacitance to be connected in an I
2
C application. These buffers are operational from a supply V of 3.0 V to 3.6 V.
The I
2
C bus capacitance limit of 400 pF restricts the number of devices and bus length. The
STDVE001A enables the system designer to isolate the two halves of a bus, accommodating more I
2
C devices or longer trace lengths. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other bus is required. The STDVE001A can be used to run the I
2
C bus at both 5 V and 3.3 V interface levels.
The DDC_EN acts as the enable for the DDC buffer. The DDC_EN line should not change state during an I
2
C operation, because disabling during bus operation hangs the bus and enabling port may through a bus cycle could confuse the I
2
C ports being enabled. The
DDC_EN input should change state only when the global bus and repeater port are in idle state, to prevent system failures.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lock-up condition from occurring when the input low condition is released.
As with the standard I
2
C system, pull up resistors are required to provide the logic high levels on the buffered bus. The STDVE001A has standard open collector configuration of the I
2
C bus. The size of the pull up resistors depends on the system, but each side of the repeater must have a pull up resistor.
This part is designed to work with standard mode and fast mode I
2
C devices. Standard mode I
2
C devices only specify 3 mA output drive, this limits the termination current to 3 mA in a generic I
2
C system where standard mode devices and multiple masters are possible.
Under certain conditions, higher termination currents can be used.
The OE_N pin can be used to disable the device. The OE_N is used to disable most of the internal circuitry of STDVE001A that puts the device in a low power mode of operation.
5.7 Bias
The bandgap reference voltage over the external R
EXT
reference resistor sets the internal bias reference current. This current and its factors (achieved by employing highly accurate
Obsolete Product(s) - Obsolete Product(s) several internal modules. The 10 mA current used by the transmitter block is also generated using this reference current. It is important to ensure that the R
EXT
value is within the ±1% tolerance range of its typical value.
Table 5.
Bias parameter
Parameter
Bandgap voltage
Min
−
Typ
1.2
Max
−
Unit
V
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Functional description STDVE001A
The output voltage swing depends on 3 components: supply voltage (V supply)
, termination resistor (R
T
) and current drive (I drive
). The supply voltage can vary from 3.3 V ± 5%, termination resistor can vary from 50 Ω ± 10%.
The voltage on the output is given by:
V supply
- I drive
x R
T
.
The variation on I drive
must be controlled to ensure that the voltage on HDMI output is within the HDMI specification under all conditions.
This is achieved when:
400 mV
≤
I drive
x R
T
600 mV with typical value centered at 500 mV.
5.8 Timing between HPD and DDC
It is important to ensure that the I
2
C DDC interface is ready by the time the HPD detection is complete.
As soon as the discovery is finished by the HPD detection, the configuration data is exchanged between a source and sink through the I
2
C DDC interface. The STDVE001A
DDC interface is ready for communication as soon as the power supply to the chip is present and stable. When the desired port is enabled and the chip is out of shutdown mode, the I
2
C DDC lines can be used for communication.
Thus, as soon as the HPD detection sequence is complete, the DDC interface can be readily used. There is no delay between the HPD detection and I
2
C DDC interface to be ready.
5.9 CEC
The CEC channel is a dedicated single pin bus and electrically translates to a bi-directional buffer used to ensure that the electrical specs of the CEC are met even with high capacitance on the single CEC line. The pull-up resistor of 26 K Ω is integrated on either sides of the buffer. The CEC is used for AV control of the electronic devices connected in a HDMI cluster. The drive of the buffer is set to meet the requirements of the CEC. This is optionally used for higher-level user functions such as automatic set-up tasks or tasks typically associated with infrared remote control usage.
The CEC line is continuously monitored during the power-on state and is not monitored during powered-off state. In powered off state, the CEC line should not be pulled low and it should not affect the CEC communication between other devices. The maximum capacitance on the CEC lines can be 7.2 nF.
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STDVE001A Maximum ratings
Stressing the device above the rating listed in
Table 6 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6.
Symbol
Absolute maximum ratings
Parameter
V
CC
V
I
I
O
T
STG
T
L
Table 7.
Supply voltage to ground
DC input voltage (TMDS ports)
OE_N, DDC_EN, PRE, EX_BOOST1, EX_BOOST2
SDA_INT, SCL_INT, SDA_EXT, SCL_EXT, HPD_INT, HPD_EXT
DC output current
Storage temperature
Lead temperature (10 sec.)
Thermal data
Value
-0.5 to +4.0
1.7 to +4.0
-0.5 to +4.0
-0.5 to +6.0
120
-65 to +150
300
Unit
V
V
V
V mA
°C
°C
Symbol
Θ
JA
Parameter
Thermal coefficient (junction-ambient)
TQFP48
QFN48
48
Unit
°C/W
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DC and AC characteristics
7
DC and AC characteristics
7.1 DC electrical characteristics
(a)
T
A
= -40 to +85 °C, V
CC
= 3.3 V ± 5%.
Power supply characteristics Table 8.
Symbol
V
CC
I
CC
Table 9.
Parameter Test condition
Supply voltage
Min
3.135
Supply current
All inputs/outputs are enabled.
Inputs are terminated with
50 Ω to V
CC
.
V
CC
= 3.465 V data rate =
3.4 Gbps
−
DC specifications for TMDS differential inputs
Symbol Parameter Test condition
V
TH
Min
−
V
TL
V
ID
V
CMR
C
IN
Differential input high threshold
(peak-to-peak)
Differential input low threshold
V
CC
= 3.465 V over the entire
V
CMR
V
CC
= 3.465 V over the entire
V
CMR
Differential input voltage
(peak-to-peak)
(1)
V
CC
= 3.465 V
Common mode voltage range
IN+ or IN- to
-150
150
V
CC
- 0.3
−
1.
Differential output voltage is defined as | (OUT+ - OUT-) |.
Differential input voltage is defined as | (IN+ - IN-) |.
Value
Typ
3.3
130
Value
Typ
0
0
−
−
3.5
Max
3.465
−
Max
150
−
STDVE001A
Unit
V mA
Unit mV mV
1560
V
CC
- 0.04
− mV
V pF a.
Typical parameters are measured at V
CC
= 3.3 V, T
A
= +25 °C.
20/48 Doc ID 14855 Rev 5
STDVE001A DC and AC characteristics
Table 10.
DC specifications for TMDS differential outputs
Value
Symbol Parameter Test condition
Min Typ Max
V
V
V swing
V
| I
C
I
I
OH
OL
OD
OH
OL
SC
OUT
|
Single-ended high level output voltage
Single-ended low level output voltage
Single ended output swing voltage
V
CC
= 3.3 V
R
TERM
= 50 Ω
Differential output voltage
(peak-to-peak)
(1)
Differential output high level current
V
CC
= 3.3 V
R
TERM
= 50 Ω
Differential output low level current
Output driver shortcircuit current
(continuous)
Output capacitance
OUT
±
= GND through a 50
Ω resistor.
OUT+ or OUT- to GND when tristate
F = 1 MHz
V
V
CC
CC
-10
-600
400
800
0
8
−
−
−
−
500
1000
−
10
−
5.5
V
V
CC
CC
+10
-400
600
1200
50
12
12
−
1.
Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |.
Unit mV mV mV mV
µA mA mA pF
Obsolete Product(s) - Obsolete Product(s)
Doc ID 14855 Rev 5 21/48
DC and AC characteristics STDVE001A
Table 11.
DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs
Value
Symbol Parameter Test condition
Min Typ Max
Unit
V
IH
V
IL
V
IK
I
IH
I
IL
C
IN
HIGH level input voltage
LOW level input voltage
Clamp diode voltage
Input high current
Input low current
Input capacitance
High level guaranteed
Low level guaranteed
V
CC
= 3.465 V
I
IN
= -18 mA
V
CC
= 3.465 V
V
IN
= V
CC
V
CC
= 3.465 V
V
IN
= GND
Pin to GND
F = 1 MHz
2.0
-0.5
-1.2
-5
-5
−
−
−
-0.8
−
−
3.5
−
0.8
−
+5
+5
−
V
V
V
µA
µA pF
Table 12.
Input termination resistor
Symbol Parameter Test condition
R
TERM
Differential input termination resistor on
IN ± channels relative to
V
CC
I
IN
= -10 mA 45
Value
50 55
Unit
Ω
Table 13.
External reference resistor
Symbol Parameter Test condition
R
EXT
Resistor for TMDS compliant voltage swing range
Tolerance for
R = ± 1%
Min
−
Value
Typ
4.7
Max
−
Unit
K Ω
Obsolete Product(s) - Obsolete Product(s)
22/48 Doc ID 14855 Rev 5
STDVE001A
Table 14.
DDC I/O pins
Symbol Parameter Test condition
Min
GND V
I(DDC)
Input voltage
I
I(leak)
C
I/O
Input leakage current
Input/output capacitance
V
CC
= 3.465 V input port= 5.3 V output port = 0.0 V switch is isolated
V
CC
= 3.465 V input port = 3.3 V output port = 0.0 V switch is isolated
V
I
= 0 V
F = 1 MHz switch disabled
V
I
= 0 V
F = 1 MHz switch enabled
Table 15.
Status pins (HPD_INT )
Symbol Parameter
V
IH
V
IL
I
I(leak)
High level input voltage
Low level input voltage
Input leakage current
−
−
−
−
Test condition
V
CC
= 3.3 V high level guaranteed
V
CC
= 3.3 V low level guaranteed
V
CC
= 3.465 V output = 5.3 V
V
CC
= 3.465 V output = 3.3 V
Min
2.0
GND
−
−
DC and AC characteristics
Value
Typ
−
−
5
9
Value
Typ
−
−
−
−
Max
5.3
6
2
−
−
Max
5.3
0.8
4
2
Unit
V
µA
µA pF pF
Unit
µA
µA
V
V
Obsolete Product(s) - Obsolete Product(s)
Doc ID 14855 Rev 5 23/48
DC and AC characteristics
Table 16.
Status pins ( HPD_EXT) (1)
Symbol Parameter Test condition
V Voltage
V
I
= 0 V
F = 1 MHz switch disabled
C
I/O
Input/output capacitance
V
I
= 0 V
F = 1 MHz switch enabled
V
OL
Output low voltage
(open-drain I/Os)
V
CC
= 3.3 V
I
OL
= 8 mA
1.
Typical parameters are measured at V
CC
= 3.3 V, T
A
= +25 °C.
STDVE001A
−
−
Min
GND
−
Value
Typ
−
5
Unit
Max
5.3 V
− pF
9
−
− pF
0.4
V
Obsolete Product(s) - Obsolete Product(s)
24/48 Doc ID 14855 Rev 5
STDVE001A DC and AC characteristics
7.2 DC electrical characteristics (I
2
C repeater)
(T
A
= -40 to +85 °C, V
CC
= 3.3 V ± 5%, GND = 0 V; unless otherwise specified).
Table 17.
Supplies
Value
Symbol Parameter Test condition
Min Typ Max
V
CC
DC supply voltage 3.135
3.3
3.465
Unit
V
Table 18.
Input/output SDA, SCL
Value
Symbol Parameter Test condition Unit
Min Typ Max
V
IH
V
IL
V
ILc
V
IK
I
IL
High level input voltage
Low level input voltage
(1)
Low level input voltage contention
(1)
Input clamp voltage
Input current low
(SDA, SCL)
I
I
= -18 mA
Input current low
(SDA, SCL)
0.7 V
CC
-0.5
-0.5
−
−
−
−
−
−
−
5.3
0.3 V
CC
0.4
-1.2
1
V
V
V
V
µA
I
IH
Input current high
(SDA, SCL)
V
I
= 3.465 V
(SDA, SCL)
V
I
= 5.3 V
(SDA, SCL)
−
−
−
−
10
10
µA
µA
V
OL
Low level output voltage
I
OL
= 3 mA
I
OL
= 6 mA
V
O
= 3.6 V; driver disabled
− −
0.4
0.65
10
V
V
µA
I
OH
Output high level leakage current
V
O
= 5.3 V; driver disabled
− −
10 µA
Input capacitance 6 7
(2) pF C
I
V
I
= 3 V or 0 V
−
1.
V
IL
specification is for the first low level seen by the SDA/SCL lines. V by the SDA/SCL lines.
2.
The SCL/SDA C
I
is about 200 pF when V
CC
ILc
is for the second and subsequent low levels seen
Obsolete Product(s) - Obsolete Product(s) secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
Doc ID 14855 Rev 5 25/48
DC and AC characteristics
7.3
STDVE001A
DC electrical characteristics (CEC)
(T
A
= -40 to +85 °C, V
CC
= 3.3 V ± 5%, GND = 0 V; unless otherwise specified).
Table 19.
DC electrical characteristics (CEC)
Value
Symbol Parameter Test condition
Min Typ Max Unit
V
CC
V
OL
V
OH
V
HL(th)
V
LH(th)
DC supply voltage
Logic 0 output
Logic 1 output
High to low input V treshold for logic ‘0’
Low to high input V treshold for logic ‘1’
Typical input hysteresis
(1)
3.135
0.0
2.5
−
−
3.3
−
−
V
CEC
(‘0’)
≤ 0.8
V
CEC
(‘1’)
≥ 2.0
0.4
3.465
0.6
3.63
−
−
V
V
V
V
V
I
V hys
R t t r f
PU
OFF
Maximum rise time
(10% to 90%)
Maximum fall time
(90% to 10%)
Internal pull-up resistor
(2)
CEC IO current in unpowered state
C
C
V
L
L
= 7.2 nF
= 7.2 nF
CC
= 0.0 V
−
−
−
23.4
−
−
−
26
−
−
250
50
28.6
1.8
V
µs
µs
K Ω
µA
1.
Input hysteresis is normally supplied by the microprocessor input circuit. In this case, additional hysteresis circuitry is not needed.
2.
The internal device pull-up should be disconnected from the line when the device is powered-off.
Obsolete Product(s) - Obsolete Product(s)
26/48 Doc ID 14855 Rev 5
STDVE001A DC and AC characteristics
7.4 Dynamic switching characteristics
(b)
(T
A
= -40 to +85 °C, V
CC
= 3.3 V ± 5%, R
TERM
= 50 Ω ± 5%, C
L
= 5 pF).
Typical values are at T
A
= +25 °C and V
CC
= 3.3 V.
Table 20.
Clock and data rate
Value
Symbol Parameter Test condition
Min Typ f
CK
D rate
Clock frequency
(1/10 th of the differential data rate)
Signaling rate
25
−
−
−
Table 21.
Differential output timings
Value
Symbol Parameter Test condition t r t f t
PLH t
PHL
Differential data and clock output rise/fall times
20% to 80% of V
OD
80% to 20% of V
OD
Differential low to high propagation delay
Differential high to low propagation delay
Alternating 1 and 0 pattern at slow and fast data rates
Measure at 50% V
OD
between input to output
Min
75
75
250
250
Typ
150
150
−
−
Table 22.
Skew times
Symbol t
SK(O) t
SK(P) t
SK(D) t
SK(CC)
Parameter Test condition
Inter-pair channel-tochannel output skew
Pulse skew
Intra-pair differential skew
| t
PLH
- t
PHL
|
Difference in propagation delay
(t
PLH
or t
PHL
) among all output channels
Min
−
−
−
−
Value
Typ
−
25
−
50
Max
340
3.4
Max
240
240
800
800
Max
100
80
44
125
Unit
MHz
Gbps
Unit ps ps ps ps
Unit ps ps ps ps b.
The timing values in this section are tested during characterization and are guaranteed by design and simulation. Not tested in production.
Doc ID 14855 Rev 5 27/48
DC and AC characteristics STDVE001A
Table 23.
Turn-on and turn-off times
Symbol Parameter Test condition
Min t
ON t
OFF
TMDS output enable time
TMDS output disable time
Time from
OE_N to OUT ± change from tristate to active
Time from
OE_N to OUT ± change from active to tristate
Table 24.
Status pins (HPD_INT, HPD_EXT, OE_N
)
−
−
Value
Typ
12
6
Max
20
10
Unit ns ns
Symbol Parameter Test condition
Min
Value
Typ Max
Unit t
PD(HPD) t
ON/OFF
Propagation delay
(from Y_HPD to the active port of HPD)
C
L
R
= 10 pF,
PU
= 1 K Ω
Switch time
(from port select to the latest valid status of
HPD)
C
L
= 10 pF
−
−
150
50
−
− ns ns
Table 25.
Jitter
Value
Symbol Parameter Test condition Unit
Min Typ Max t
JIT
Total jitter
(1)
PRBS pattern at 1.6 Gbps
(800 MHz)
−
35
− ps (p-p)
1.
Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. Input differential voltage = V
ID
= 500 mV, PRBS random pattern at 1.65 Gbps, t r
= t f
= 50 ps (20% to 80%).
Jitter parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
Obsolete Product(s) - Obsolete Product(s)
28/48 Doc ID 14855 Rev 5
STDVE001A DC and AC characteristics
7.5 Dynamic switching characteristics (I
2
C repeater)
(T
A
= -40 to +85 °C, V
CC
= 3.3 V ± 5%)
Typical values are at T
A
= +25 °C and V
CC
= 3.3 V.
.
Table 26.
I
2
C repeater
(1)
Symbol f
SCL t
LOW t
LOW
Parameter Test condition
Standard mode
I
2
C clock frequency
Fast mode
100 KHz
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
Low duration on SCL pin
400 KHz
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
Low duration on SCL pin
100 KHz
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
400 KHz
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
High duration on SCL
100 KHz
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
Value
Unit
Min Typ Max
− −
100 kHz
− −
400 kHz
4.7
1.3
4.7
1.3
4.0
−
−
−
−
−
−
−
−
−
−
µs
µs
µs
µs
µs t
HIGH
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
0.6
− −
µs
Doc ID 14855 Rev 5 29/48
DC and AC characteristics STDVE001A
Table 26.
I
2
C repeater
(1)
(continued)
Symbol t
HIGH t
PHL t
PLH t
PHL t
PLH t
PHL t
PLH t
PHL
Parameter
High duration on SCL pin
Propagation delay
Propagation delay
Propagation delay
Propagation delay
Propagation delay
Propagation delay
Propagation delay
Test condition
Value
Min Typ Max
Unit
100 KHz
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
400 KHz
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
Depends on input signal rise time. Includes the 20% time intervals on both transitions.
400 KHz waveform 1 (
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
400 KHz waveform 1 (
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
400 KHz waveform 1 (
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
400 KHz waveform 1 (
voltage on line = 3.3 V , Cmax = 400 pF, Rmax = 2 K Ω
100 KHz waveform 1 (
voltage on line = 5 V , Cmax = 400 pF, Rmax = 2 K Ω
100 KHz waveform 1 (
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K
Ω
100 KHz waveform 1 (
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
100 KHz waveform 1 (
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
4.0
0.6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
250
300
250
450
250
300
250
450
µs
µs
µs
µs ns ns ns ns ns ns
30/48 Doc ID 14855 Rev 5
STDVE001A DC and AC characteristics
Table 26.
I
2
C repeater
(1)
(continued)
Symbol Parameter Test condition
Value
Min Typ Max
Unit t t t t f f r r
Output fall time
Output fall time
Output rise time
Output rise time
400 KHz waveform 1 (
(2) voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
400 KHz waveform 1
(2) voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
100 KHz waveform 1 (
(2) voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K Ω
100 KHz waveform 1 (
(2) voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Ω
400 KHz waveform 1 (
(2)
, voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K Ω
400 KHz waveform 1 (
(2)
, voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
Ω
100 KHz waveform 1
(2)
Rmax = 2 K Ω
, voltage on line = 5 V, Cmax = 400 pF,
100 KHz waveform 1 (
(2)
, voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K Ω
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
300
300
300
300
300
300
1000
1000
1.
All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in production.
2.
The t r
transition time is specified with maximum load of 2 k
Ω
pull-up resistance and 400 pF load capacitance. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
ns ns ns ns ns ns ns ns
Table 27.
ESD performance
Symbol Parameter Test conditions Unit
TMDS I/Os
Other I/Os
Human body model
Human body model
Min
−
−
Typ
±
5
± 2
Max
−
− kV kV
Doc ID 14855 Rev 5 31/48
DC and AC characteristics
Figure 8.
Test circuit for electrical characteristics
6##
0ULSE
GENERATOR
24 24
6).
6).
#,
6/54
34$6%!
6/54
#,
STDVE001A
1.
C
L
= load capacitance: include jig and probe capacitance.
2.
R
T
= termination resistance; should be equal to Z
OUT
of the pulse generator.
Figure 9.
TMDS output driver
6##
24 24
:/24
4-$3
DRIVER :/24
4-$3
RECEIVER
!-6
#36
1.
Z
O
= characteristic impedance of the cable.
2.
R
T
= termination resistance: should be equal to Z
O
of the cable. Both are equal to 50
Ω
.
Obsolete Product(s) - Obsolete Product(s)
32/48 Doc ID 14855 Rev 5
STDVE001A
Figure 10.
Test circuit for HDMI receiver and driver
DC and AC characteristics
1.
R
T
= 50
Ω .
Figure 11.
Test circuit for turn-on and turn-off times
#,
6
6
6
34$6%!
6
6
#,
0ULSE
GENERATOR
Obsolete Product(s) - Obsolete Product(s)
!-6
1.
C
L
= 5 pF.
Doc ID 14855 Rev 5 33/48
DC and AC characteristics
Figure 12.
Test circuit for short-circuit output current
4-$3
DRIVER
)3#
6OR6
STDVE001A
#36
Figure 13.
Propagation delays
6!
6#-
6"
6)$
6)$
6)$PP
6#-
/UTPUT
T0,(
6/$/
6/$PP
T0(,
6##
6##n
6)$
TF
6
6
6
6DIFFERENTIAL
6/$5
!-
34/48 Doc ID 14855 Rev 5
STDVE001A
Figure 14.
Turn-on and turn-off times
3($.?.
6
T/&&
6/54 WHEN6)$ M6
6/54 WHEN6)$ M6
T/&&
6/54 WHEN6)$ M6
6/54 WHEN6)$ M6
DC and AC characteristics
6
T/.
T/.
6
6
6/(
6
6
6/,
!-
Obsolete Product(s) - Obsolete Product(s)
Doc ID 14855 Rev 5 35/48
STDVE001A DC and AC characteristics
Figure 15.
t
SK(O)
6
6
$ATA).
T0,(8
6
T0(,8
6
6/(
6
$ATA/54ATPORT
T3+/ T3+/
6/,
6/(
6
$ATA/54ATPORT
6/,
T0,(9 T0(,9
T3+/ \T0,(9nT0,(8\OR\T0(,9nT0(,8\
!-
Figure 16.
t
SK(P)
6
6
)NPUT
6
T0,( T0(,
Obsolete Product(s) - Obsolete Product(s) 6/(
6
/UTPUT
6/,
T3+0 \T0(,nT0,(\
!-
36/48 Doc ID 14855 Rev 5
DC and AC characteristics STDVE001A
Figure 17.
t
SK(D)
69
6/(
6:
6/,
T3+$
!-
Figure 18.
AC waveform 1 (I
2
C lines)
)NPUT
6 6
6
6
40(, 40,(
/UTPUT 6
6 6
6/,
T4(, T4,(
!-
Figure 19.
Test circuit for AC measurements (I
2
C lines)
6## 6##
2,
6).
$54
6/54
05,3%
'%.%2!4/2
24 #,
Obsolete Product(s) - Obsolete Product(s)
4ESTCIRCUITFOROPENDRAINOUTPUTS
!-
1.
R
L
= load resistor; 1.35 k
Ω .
2.
C
L
= load capacitance includes jig and probe capacitance; 7 pF.
3.
R
T
= termination resistance should be equal to Z
OUT
of pulse generator.
Doc ID 14855 Rev 5 37/48
DC and AC characteristics
Figure 20.
I
2
C bus timing
STDVE001A
Obsolete Product(s) - Obsolete Product(s)
38/48 Doc ID 14855 Rev 5
STDVE001A Application information
8.1
8.2
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to always apply V
CC before applying any signals to the input/output or control pins.
Power supply requirements
Bypass each of the V
CC pins with 0.1
μ
F and 1 nF capacitors in parallel as close to the device as possible, with the smaller-valued capacitor as close to the V
CC pin of the device as possible.
All V
CC pins can be tied to a single 3.3 V power source. A 0.01
μ
F capacitor is connected from each V
CC
pin directly to ground to filter supply nois e. The maximum power supply variation can only be ± 5% as per the HDMI specifications.
The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
The high-speed TMDS inputs are the most critical parts for the device. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device. a) Maintain Ω differential transmission line impedance into and out of the
STDVE001A.
b) Keep an uninterrupted ground plane below the high-speed I/Os.
c) Keep the ground-path vias to the device as close as possible to allow the shortest return current path.
d) Layout of the TMDS differential inputs should be with the shortest stubs from the connectors.
Output trace characteristics affect the performance of the STDVE001A. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. Run the differential traces close together to minimize the effects of the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to further prevent impedance discontinuities.
Obsolete Product(s) - Obsolete Product(s)
8.4 I C lines application information
A typical application is shown in the figure below. In the example, the system master is running on a 3.3 V I
2
C-bus while the slave is connected to a 5 V bus. Both buses run at
100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz.
Master devices can be placed on either bus.
Doc ID 14855 Rev 5 39/48
Application information
Figure 21.
Typical application of I
2
C bus system
6 6
STDVE001A
3$!
3#,
"USMASTER
K(Z
3$!
3#,
3$!
3#,
34$6%!
3$!
3#,
3LAVE
K(Z
"53 "53
!-6
The STDVE001A DDC lines are 5 V tolerant; so it does not require any extra circuitry to translate between the different bus voltages.
Obsolete Product(s) - Obsolete Product(s)
40/48 Doc ID 14855 Rev 5
STDVE001A
9 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 22.
TQFP48 (7 x 7 mm) package outline
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Package mechanical data
Table 28.
TQFP48 (7 x 7 mm) mechanical data
Millimeters
Symbol
Min a b b1
L
L1
T
T1 e ccc / ddd
D
D1
E
E1
A -
A1 0.05
A2 0.95
8.80
6.90
8.80
6.90
0°
0.17
0.17
−
−
0.45
−
0.70
0.10
Typ
0.15
0.13
−
0.22
0.20
0.500
0.08
-
0.10
1.00
9.00
7.00
9.00
7.00
0.60
1.00
STDVE001A
Max
1.20
0.15
1.05
9.20
7.10
9.20
7.10
0.75
−
0.20
1.15
7°
0.27
0.23
−
−
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STDVE001A
Figure 23.
TQFP48 (7 x 7 mm) footprint recommendation
Package mechanical data
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Package mechanical data
Figure 24.
TQFP48 (7 x 7 mm) tape and reel information
STDVE001A
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STDVE001A
Figure 25.
QFN48 (7 x 7 mm) package outline
Package mechanical data
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Package mechanical data
Table 29.
QFN48 (7 x 7 mm) package mechanical data
Millimeters
Symbol
Min Typ b
D
D2
E
A
A1
A2
A3
E2 e
L ddd
2.25
6.85
2.25
0.45
0.80
−
−
−
0.18
6.85
0.30
−
0.23
7.00
4.70
7.00
0.90
0.02
0.65
0.25
4.70
0.50
0.40
−
STDVE001A
Max
1.00
0.05
1.00
−
0.30
7.15
5.25
7.15
5.25
0.55
0.50
0.08
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STDVE001A Revision history
Table 30.
Document revision history
Date Revision
02-Jul-2008
21-Jul-2008
28-Jul-2009
06-Dec-2010
30-Aug-2011
1
2
3
4
5
Changes
Initial release.
Section 5: Functional description on page 14
Replaced ‘equation’ with ‘equalizer in the Features section.
Document status promoted from preliminary data to datasheet.
Updated: ESD values.
Document reformatted, updated
, title of
DD
by V
CC
,
, to
,
to
,
,
,
, removed Table 24 - DDC
I/O pins.
Changed the maximum value of parameter A to 1.20 in
.
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STDVE001A
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