(Flash memory up to 32 Kbyte and SRAM up to 4 Kbyte), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (one

I2C, one SPI, one I2S, and one USART), one 12-bit ADC, up to five general-purpose 16-bit timers, a 32-bit timer and an advanced-control PWM timer.

The STM32F050x4/6 family operates in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The STM32F050x4/6 family includes devices in four different packages ranging from 20 to

48 pins. Depending on the device chosen, different sets of peripherals are included. An overview of the complete range of peripherals proposed in this family is provided.

These features make the STM32F050x4/6 microcontroller family suitable for a wide range of applications such as control application and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,

PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

Table 2. STM32F050x4/6 device features and peripheral counts

Peripheral STM32F050Fx STM32F050Gx STM32F050Kx STM32F050Cx

SRAM (Kbyte)

Advanced control

Timers

General purpose

SPI (I2S)

(1)

Comm. interfaces

I2C

USART

16 32 16

4 4

1 (16-bit)

4 (16-bit)

1 (32-bit)

32 16 32

12-bit synchronized ADC

(number of channels)

GPIOs

Max. CPU frequency

Operating voltage

(9 ext. + 3 int.)

15 23

(10 ext. + 3 int.)

48 MHz

2.0 to 3.6 V

Operating temperature

Packages

Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C

Junction temperature: -40°C to 105°C / -40 °C to 125 °C

TSSOP20 UFQFPN28

The SPI interface can be used either in SPI mode or in I2S audio mode.

UFQFPN32 LQFP48

10/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

6:&/.

6:'$7

DV$)

3$>@

3%>@

3&>@

3)>@

026,6'

0,620&.

6&.&.

166:6DV$)

6HULDO:LUH

'HEXJ

&257(;0&38

I+&/. 0+]

19,&

*3'0$

FKDQQHOV

*3,2SRUW$

*3,2SRUW%

*3,2SRUW&

*3,2SRUW)

(;7,7

:.83

63,,6

6<6&)* ,)

7HPS VHQVRU

ELW$'& ,)

$'&B,1

''$

66$

/HJHQG

''$

6XSSOLHGE\9

''$

Description

Figure 1. Block diagram

$+%

$3%

)/$6+

ELWV

32:(5

92/7 5(*

97WR 9

65$0

5(6(7

&/2&.

&21752/

&5&

''$

5&+60+]

5&/6

3//

325

5HVHW

,QW

6833/<

683(59,6,21

325 3'5

39'

''$

;7$/ 26&

0+]

$+%3&/.

$3%3&/.

$'&&/.

&(&&/.

86$57&/.

+&/.

)&/.

,:'*

3RZHU

&RQWUROOHU

#96:

;7$/ N+]

57&

%DFNXS

UHJ

57& LQWHUIDFH

7,0(5

::'*

WR 9

1567

''$

26&,1 3)

26&287 3)

%$7

9 WR 9

26&B,1

26&B287

7$03(557&

$/$50 287

FKDQQHOV

FRPSO FKDQQHOV

%5. (75 LQSXW DV $)

FK (75 DV $)

FKDQQHO DV $)

FKDQQHO

FRPSO %5. DV $)

FKDQQHO

FRPSO %5. DV $)

,5B287DV$)

'%*0&8

86$57

5;7; &76 576

&. DV $)

6&/6'$60%DO

P$ IRU )0

DV $)

6XSSOLHGE\9

%$7

6XSSOLHGE\9

'' 069

DocID023683 Rev 2

11/101

Functional overview STM32F050x4 STM32F050x6

3.1 ARM

®

Cortex

®

-M0 core with embedded Flash and SRAM

The ARM

Cortex

-M0 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM

Cortex

-M0 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32F050x4/6 family has an embedded ARM core and is therefore compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

3.2 Memories

The device has the following features:

• 4 Kbyte of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications.

•

The non-volatile memory is divided into two arrays:

– 16 to 32 Kbyte of embedded Flash memory for programs and data

– Option bytes

The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (Cortex

-M0 serial wire) and boot in RAM selection disabled

At startup, the boot pin and boot selector option bit are used to select one of three boot options:

• Boot from User Flash

• Boot from System Memory

• Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1.

12/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Functional overview

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a CRC-32 (Ethernet) polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.5.1

3.5.2

Power supply schemes

•

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

DDA

= 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and

PLL (minimum voltage to be applied to V

DDA is 2.4 V when the ADC is used). The V

DDA voltage level must be always greater or equal to the V

DD provided first.

voltage level and must be

•

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold,

POR/PDR

, without the need for an external reset circuit.

• The POR monitors only the V

supply voltage. During the startup phase it is required that V

DDA

should arrive first and be greater than or equal to V

• The PDR monitors both the V

and V

DDA

supply voltages, however the V

DDA

power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V

DDA

is higher than or equal to V

The device features an embedded programmable voltage detector (PVD) that monitors the

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V

drops below the V

PVD

threshold and/or when V

is higher than the V

PVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

DocID023683 Rev 2

13/101

Functional overview STM32F050x4 STM32F050x6

The regulator has three operating modes: main (MR), low power (LPR) and power down.

•

MR is used in normal operating mode (Run)

• LPR can be used in Stop mode where the power demand is reduced

•

Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.

Note:

The STM32F050x4/6 family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines, the PVD output, RTC alarm, I2C1 or

USART1.

The I2C1 and the USART1 can be configured to enable the HSI RC oscillator for processing incoming data. If this is used, the voltage regulator should not be put in the low-power mode but kept in normal mode.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pins, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

14/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

3.6

Functional overview

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

Figure 2. Clock tree

&,)4&#,+

TO&LASHPROGRAMMINGINTERFACE

(3)

393#,+

TO)#

TO)3

-(Z

(3)2#

(3)

(#,+

0,,32#

0,,-5,

0,,

(3)

0,,#,+

(3%

#33

!("

PRESCALER

393#,+

!0"

PRESCALER

)F!0"PRESCALER

XELSEX

!$#

0RESCALER

TO!("BUSCORE

MEMORYAND$-!

TOCORTEX3YSTEMTIMER

&(#,+#ORTEXFREERUNNINGCLOCK

0#,+

TO!0"PERIPHERALS

TO4)-

/3#?/54

/3#?).

-(Z

(3%/3#

-(Z

(3)2#

(3)

TO!$#

-(ZMAX

/3#?).

0#,+

393#,+

(3)

,3%

TO53!24

/3#?/54

-#/

24##,+

,3%/3#

K(Z ,3%

24#3%,;=

,3)2#

K(Z

-AINCLOCK

OUTPUT

,3)

-#/

0,,#,+

(3)

(3%

393#,+

,3)

,3%

TO24#

TO)7$'

)7$'#,+

-36

DocID023683 Rev 2

15/101

Functional overview

3.7

STM32F050x4 STM32F050x6

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.8 Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except

TIM14) and ADC.

3.9 Interrupts events

3.9.1

3.9.2

Nested vectored interrupt controller (NVIC)

The STM32F050x4/6 family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex

-M0) and 4 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

Extended interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 39

GPIOs can be connected to the 16 external interrupt lines.

16/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Functional overview

3.10 Analog to digital converter (ADC)

The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The temperature sensor (TS) generates a voltage V

SENSE that varies linearly with temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C,

DDA

= 3.3 V

TS ADC raw data acquired at temperature of 110 °C

DDA

= 3.3 V

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

3.10.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

) provides a stable (bandgap) voltage output for the

ADC. V

REFINT

is internally connected to the ADC_IN17 input channel. The precise voltage of V

REFINT

is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 4. Temperature sensor calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at temperature of 30 °C

DDA

= 3.3 V

0x1FFF F7BA - 0x1FFF F7BB

DocID023683 Rev 2

17/101

Functional overview STM32F050x4 STM32F050x6

3.11 Timers and watchdogs

The STM32F050x4/6 family devices include up to six general-purpose timers, one basic timer and an advanced control timer.

Table 5 compares the features of the advanced-control, general-purpose and basic timers.

Timer type

General purpose

Timer

Counter resolution

Advanced control

TIM1

TIM3

TIM14

TIM16,

TIM17

16-bit

TIM2 32-bit

16-bit

Table 5. Timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

Up, down, up/down

Any integer between 1 and 65536

Yes

3.11.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

• Input capture

•

Output compare

• PWM generation (edge or center-aligned modes)

•

One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining.

18/101

There are six synchronizable general-purpose timers embedded in the STM32F050x4/6

devices (see Table 5 for differences). Each general-purpose timer can be used to generate

PWM outputs, or as simple time base.

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Functional overview

TIM2, TIM3

STM32F050x4/6 devices feature two synchronizable 4-channel general-purpose timers.

TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.

TIM2 and TIM3 both have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output.

Its counter can be frozen in debug mode.

TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output.

TIM16, and TIM17 have a complementary output with dead-time generation and independent DMA request generation

Their counters can be frozen in debug mode.

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode.

DocID023683 Rev 2

19/101

Functional overview STM32F050x4 STM32F050x6

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

•

A 24-bit down counter

• Auto reload capability

•

Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source (HCLK or HCLK/8)

The RTC and the 5 backup registers are supplied through a switch that takes power either on V

supply when present or through the V

BAT

pin. The backup registers are five 32-bit registers used to store 20 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, or when the device wakes up from Standby mode.

The RTC is an independent BCD timer/counter. Its main features are the following:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

•

Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.

• Programmable alarm with wake up from Stop and Standby mode capability.

•

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.

•

2 anti-tamper detection pins with programmable filter. The MCU can be woken up from

Stop and Standby modes on tamper event detection.

• Timestamp feature which can be used to save the calendar content. This function can triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

The RTC clock sources can be:

•

A 32.768 kHz external crystal

• A resonator or oscillator

•

The internal low-power RC oscillator (typical frequency of 40 kHz)

• The high-speed external clock divided by 32.

20/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Functional overview

circuit interface (I

2

C)

The I

C interface (I2C1) can operate in multimaster or slave mode. It can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive.

It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,

1 with configurable mask). It also includes programmable analog and digital noise filters.

Pulse width of suppressed spikes

Benefits

Drawbacks

Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter

≥ 50 ns

Available in Stop mode

Variations depending on temperature, voltage, process

Programmable length from 1 to 15

I2C peripheral clocks

1. Extra filtering capability vs. standard requirements.

2. Stable length

Wakeup from Stop on address match is not available when digital filter is enabled.

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

The I2C interface can be served by the DMA controller.

(USART)

The device embeds an universal synchronous/asynchronous receiver transmitters

(USART1), which communicates at speeds of up to 6 Mbit/s.

It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. It also supports SmartCard communication (ISO 7816), IrDA SIR

ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain independent from the CPU clock, allowing it to wake up the MCU from Stop mode.

The USART interface can be served by the DMA controller.

DocID023683 Rev 2

21/101

Functional overview STM32F050x4 STM32F050x6

3.15 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I

2

S)

The SPI (SPI1) is able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

One standard I

S interface (multiplexed with SPI1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.

3.16 Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

22/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

4 Pinouts and pin descriptions

Pinouts and pin descriptions

Figure 3. LQFP48 48-pin package pinout

9%$7

3&26&B,1

3&26&B287

3)26&B,1

3)26&B287

1567

966$

9''$

/4)3

Figure 4. UFQFPN32 32-pin package pinout

9''

3)26&B,1

3)26&B287

1567

9''$

966

966$

9''

069

DocID023683 Rev 2

23/101

Pinouts and pin descriptions STM32F050x4 STM32F050x6

Figure 5. UFQFPN28 28-pin package pinout

%227

3)26&B,1

3)26&B287

1567

9''$

9''

966

069

Figure 6. TSSOP20 20-pin package pinout

%227

3)26&B,1

3)26&B287

1567

9''$

3 $

9 ' '

966

3 %

069

24/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Pinouts and pin descriptions

Name

Table 7. Legend/abbreviations used in the pinout table

Abbreviation Definition

Pin name

Pin type

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I/O

FTf

Input only pin

Input / output pin

5 V tolerant I/O

5 V tolerant I/O, FM+ capable

I/O structure

Notes

TTa

RST

3.3 V tolerant I/O directly connected to ADC

Standard 3.3V I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate functions

Functions selected through GPIOx_AFR registers

Pin functions

Additional functions

Functions directly selected/enabled through peripheral registers

DocID023683 Rev 2

25/101

Pinouts and pin descriptions

Pin number

Table 8. Pin definitions

Pin name

(function after reset)

STM32F050x4 STM32F050x6

Pin functions

Notes

Alternate functions

Additional functions

2 -

15 11 11 11

VBAT

PC13

I/O

(1)(2)

Backup power supply

RTC_TAMP1,

RTC_TS,

RTC_OUT,

WKUP2

OSC32_IN 3

PC14/OSC32_IN

(PC14)

PC15/OSC32_OUT

(PC15)

PF0/OSC_IN

(PF0)

PF1/OSC_OUT

(PF1)

I/O

NRST

VSSA

VDDA

I/O RST

(1)(2)

PA0

PA1

PA2

PA3

PA4

PA5

I/O

TTa

TTa -

OSC32_OUT

OSC_IN

OSC_OUT

Device reset input / internal reset output

(active low)

Analog ground

Analog power supply

TIM2_CH1_ETR,

USART1_CTS

(3)

ADC_IN0,

RTC_TAMP2,

WKUP1

TIM2_CH2,

EVENTOUT,

USART1_RTS

(3)

ADC_IN1

TIM2_CH3,

USART1_TX

(3)

TIM2_CH4,

USART1_RX

(3)

SPI1_NSS,

I2S1_WS,

TIM14_CH1,

USART1_CK

(3)

SPI1_SCK,

I2S1_CK,

TIM2_CH1_ETR

ADC_IN2

ADC_IN3

ADC_IN4

ADC_IN5

26/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

Pin number

Pinouts and pin descriptions

Table 8. Pin definitions (continued)

Pin name

(function after reset)

Pin functions

Notes

Alternate functions

Additional functions

16 12 12 12

17 13 13 13

18 14 14 -

19 15 15 14

25 -

23 0 16 15

24 17 17 16

26 -

27 -

28 -

PA6

PA7

PB0

PB1

PB2

PB10

PB11

VSS

VDD

PB12

PB13

PB14

PB15

I/O TTa -

I/O

FTf -

I/O FTf

S -

I/O FT

SPI1_MISO,

I2S1_MCK,

TIM3_CH1,

TIM1_BKIN,

TIM16_CH1,

EVENTOUT

SPI1_MOSI,

I2S1_SD,

TIM3_CH2,

TIM14_CH1,

TIM1_CH1N,

TIM17_CH1,

EVENTOUT

TIM3_CH3,

TIM1_CH2N,

EVENTOUT

TIM3_CH4,

TIM14_CH1,

TIM1_CH3N

TIM1_BKIN,

EVENTOUT,

SPI1_NSS

(3)

TIM1_CH1N,

SPI1_SCK

(3)

TIM1_CH2N,

SPI1_MISO

(3)

TIM1_CH3N,

SPI1_MOSI

(3)

ADC_IN6

ADC_IN7

ADC_IN8

ADC_IN9

TIM2_CH3,

I2C1_SCL

(3)

TIM2_CH4,

EVENTOUT,

I2C1_SDA

(3)

Ground

Digital power supply

RTC_REFIN

DocID023683 Rev 2

27/101

Pinouts and pin descriptions

Pin number

STM32F050x4 STM32F050x6

Table 8. Pin definitions (continued)

Pin name

(function after reset)

Pin functions

Notes

Alternate functions

Additional functions

29 18 18 -

30 19 19 17

31 20 20 18

32 21 -

33 22 -

34 23 21 19

37 24 22 20

38 25 23 -

39 26 24 -

40 27 25 -

PA8

PA9

PA10

PA11

PA12

PA13

(SWDAT)

PF6

PF7

PA14

(SWCLK)

PA15

PB3

PB4

I/O FT -

I/O FTf -

I/O FT -

I/O

FTf

(4)

I/O FT -

USART1_CK,

TIM1_CH1,

EVENTOUT,

MCO

USART1_TX,

TIM1_CH2,

I2C1_SCL

(3)

USART1_RX,

TIM1_CH3,

TIM17_BKIN,

I2C1_SDA

(3)

USART1_CTS,

TIM1_CH4,

EVENTOUT

USART1_RTS,

TIM1_ETR,

EVENTOUT

IR_OUT,

SWDAT

I2C1_SCL

(3)

I2C1_SDA

(3)

SWCLK,

USART1_TX

(3)

SPI1_NSS,

I2S1_WS,

TIM2_CH_ETR,

EVENTOUT,

USART1_RX

(3)

SPI1_SCK,

I2S1_CK,

TIM2_CH2,

EVENTOUT

SPI1_MISO,

I2S1_MCK,

TIM3_CH1,

EVENTOUT

28/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

Pin number

Pinouts and pin descriptions

Table 8. Pin definitions (continued)

Pin name

(function after reset)

Pin functions

Notes

Alternate functions

Additional functions

28 -

PB5

PB6

PB7

I/O

FTf

FTf -

SPI1_MOSI,

I2S1_SD,

I2C1_SMBA,

TIM16_BKIN,

TIM3_CH2

I2C1_SCL,

USART1_TX,

TIM16_CH1N

I2C1_SDA,

USART1_RX,

TIM17_CH1N

BOOT0

PB8

PB9

VSS

VDD

I/O

FTf

Boot memory selection

I2C1_SCL,

TIM16_CH1

I2C1_SDA,

IR_OUT,

TIM17_CH1,

EVENTOUT

Ground 47

48 Digital power supply

PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- these GPIOs must not be used as a current sources (e.g. to drive an LED).

After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the STM32F05xx reference manual.

This alternate feature is available on standard dies only.

After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin and internal pull-down on SWCLK pin are activated.

DocID023683 Rev 2

29/101

Pin name

PA0

AF0

Table 9. Alternate functions selected through GPIOA_AFR registers for port A

AF1 AF2 AF3 AF4 AF5

USART1_CKS

(1)

PA1

PA2

PA3

EVENTOUT USART1_TX

(1)

USART1_RX

(1)

USART1_CTS

(1)

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

SPI1_NSS,

I2S1_WS

SPI1_SCK,

I2S1_CK

SPI1_MISO,

I2S1_MCK

SPI1_MOSI,

I2S1_SD

MCO

USART1_RTS

TIM3_CH1

TIM3_CH2

(1)

PA15

TIM17_BKIN

EVENTOUT

SWDAT

SWCLK

SPI1_NSS,

I2S1_WS

USART1_CK

USART1_TX

USART1_RX

USART1_CTS

USART1_RTS

IR_OUT

USART1_TX

USART1_RX

(1)

This alternate feature is available on standard dies only.

TIM2_CH1_

ETR

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_CH1_

ETR

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

TIM2_CH1_

ETR

EVENTOUT

TIM14_CH1

I2C1_SCL

(1)

I2C1_SDA

(1)

TIM16_CH1

TIM17_CH1

AF6

EVENTOUT

AF7

Pin name

Table 10. Alternate functions selected through GPIOB_AFR registers for port B

AF0

PB4

PB5

PB6

PB7

PB0

PB1

PB2

PB3

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

EVENTOUT

TIM14_CH1

SPI1_SCK, I2S1_CK

SPI1_MISO, I2S1_MCK

SPI1_MOSI, I2S1_SD

USART1_TX

USART1_RX

IR_OUT

EVENTOUT

SPI1_NSS

(1)

SPI1_SCK

(1)

SPI1_MISO

(1)

SPI1_MOSI

(1)

This alternate feature is available on standard dies only.

AF1

TIM3_CH3

TIM3_CH4

EVENTOUT

TIM3_CH1

TIM3_CH2

I2C1_SCL

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C1_SCL

(1)

I2C1_SDA

(1)

EVENTOUT

AF2

TIM1_CH2N

TIM1_CH3N

TIM2_CH2

EVENTOUT

TIM16_BKIN

TIM16_CH1N

TIM17_CH1N

TIM16_CH1

TIM17_CH1

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

AF3

I2C1_SMBA

EVENTOUT

Memory mapping STM32F050x4 STM32F050x6

X&&&&&&&&

#ORTEX-INTERNAL

PERIPHERALS

Figure 7. STM32F050x4/6 memory map

X&&

!("

RESERVED

X&&&&&&&

X&&&&#

X&&&&

RESERVED

/PTION BYTES

3YSTEMMEMORY

X&&&%#

X&&

!("

RESERVED

!0"

RESERVED

!0"

RESERVED

0ERIPHERALS

32!-

#/$%

&LASHMEMORY

&LASHSYSTEMMEMORY

OR32!-DEPENDINGON

"//4CONFIGURATION

RESERVED

2ESERVED

-36

32/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Memory mapping

Table 11. STM32F050x4/6 peripheral register boundary addresses

Bus Boundary address Size Peripheral

AHB2

AHB1

APB

0x4800 1800 - 0x5FFF FFFF

0x4800 1400 - 0x4800 17FF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0000 - 0x4002 03FF

0x4001 8000 - 0x4001 FFFF

0x4001 5C00 - 0x4001 7FFF

0x4001 5800 - 0x4001 5BFF

0x4001 4C00 - 0x4001 57FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 0800 - 0x4001 23FF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 8000 - 0x4000 FFFF

1KB

32KB

9KB

1KB

3KB

1KB

7KB

1KB

32KB

~384 MB Reserved

1KB

GPIOF

Reserved

1KB

Reserved

GPIOC

GPIOB

GPIOA

~128 MB Reserved

1KB Reserved

3KB

1KB

Reserved

CRC

3KB

1KB

3KB

1KB

3KB

1KB

Reserved

FLASH Interface

Reserved

RCC

Reserved

DMA

Reserved

DBGMCU

Reserved

TIM17

TIM16

Reserved

USART1

Reserved

SPI1/I2S1

TIM1

Reserved

ADC

Reserved

EXTI

SYSCFG

Reserved

DocID023683 Rev 2

33/101

Memory mapping STM32F050x4 STM32F050x6

Table 11. STM32F050x4/6 peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral

APB

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 5C00 - 0x4000 6FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 4800 - 0x4000 53FF

0x4000 4400 - 0x4000 47FF

0x4000 3C00 - 0x4000 43FF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1400 - 0x4000 1FFF

0x4000 1000 - 0x4000 13FF

0x4000 0800 - 0x4000 0FFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

3 KB

1KB

2KB

1KB

5KB

1KB

3KB

1KB

2KB

1KB

Reserved

PWR

Reserved

I2C1

Reserved

IWDG

WWDG

RTC

Reserved

TIM14

Reserved

TIM3

TIM2

34/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

= 25 °C and T

= T

A max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3

Unless otherwise specified, typical data are based on T

= 25 °C, V are given only as design guidelines and are not tested.

= V

DDA

= 3.3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 8 .

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9

Figure 8. Pin loading conditions Figure 9. Pin input voltage

0&8SLQ 0&8SLQ

& S)

069

DocID023683 Rev 2

069

35/101

Electrical characteristics

6.1.6

STM32F050x4 STM32F050x6

Power supply scheme

Figure 10. Power supply scheme

6"!4

6 0O WERSWI TCH

"ACKUPCIRCUITRY

,3%24#

7AKEUPLOGIC

"ACKUPREGISTERS

'0)/S

/54

,OGIC

§N&

§&

6$$!

6$$

§ 6$$

§ 633

6$$!

2EGULATOR

+ERNELLOGIC

#05

$IGITAL

-EMORIES

62%&

!$#

$!#

!NALOG

2#S0,,

633!

-36

Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

36/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Figure 11. Current consumption measurement scheme

,''B9%$7

9%$7

,''

9''

,''$

9''$

6.2

069

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 12: Voltage characteristics

Table 13: Current characteristics

, and

Table 14: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 12. Voltage characteristics

(1)

Ratings Min Symbol Max Unit

–V

DDA

Allowed voltage difference for V

> V

DDA

Input voltage on FT and FTf pins

(2)

Input voltage on TTa pins

Input voltage on any other pin

| Δ V

DDx

SSX

− V

Variations between different V

DD power pins

Variations between all the different ground pins

ESD(HBM)

Electrostatic discharge voltage (human body model)

− 0.3

0.4

+ 4.0

4.0

50 see

Section 6.3.11: Electrical sensitivity characteristics

All main power (V

, V

DDA

) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

maximum must always be respected. Refer to

Table 13: Current characteristics for the maximum

allowed injected current values.

V mV

DocID023683 Rev 2

37/101

Electrical characteristics STM32F050x4 STM32F050x6

Symbol

Table 13. Current characteristics

Ratings Max.

Unit

VDD( Σ)

Total current into sum of all VDD_x and VDDSDx power lines

(source)

(1)

120

VSS( Σ)

VDD(PIN)

VSS(PIN)

Total current out of sum of all VSS_x and VSSSD ground lines

(sink)

(1)

Maximum current into each VDD_x or VDDSDx power pin (source)

Maximum current out of each VSS_x or VSSSD ground pin (sink)

(1)

-120

100

-100

Output current sunk by any I/O and control pin 25

IO(PIN)

INJ(PIN)

Output current source by any I/O and control pin

Total output current sunk by sum of all IOs and control pins

(2)

Total output current sourced by sum of all IOs and control pins

(2)

Injected current on FT, FTf and B pins

(3)

Injected current on TC and RST pin

(4)

Injected current on TTa pins

(5)

Total injected current (sum of all I/O and control pins)

(6)

- 25

-80

-5/+0

± 5

± 5 mA

Σ I

INJ(PIN)

± 25

All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

A positive injection is induced by V

while a negative injection is induced by V

. I

INJ(PIN)

exceeded. Refer to Table 12: Voltage characteristics for the maximum allowed input voltage values.

must never be

A positive injection is induced by V

DDA

while a negative injection is induced by V

. I

INJ

(PIN) must never be

exceeded. Refer also to Table 12: Voltage characteristics for the maximum allowed input voltage values. Negative injection

disturbs the analog performance of the device. See note

(2)

below

Table 51: ADC accuracy .

When several inputs are submitted to a current injection, the maximum

INJ(PIN) negative injected currents (instantaneous values).

is the absolute sum of the positive and

Symbol

STG

Table 14. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

38/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

6.3.1 General operating conditions

Symbol

Table 15. General operating conditions

Parameter Conditions Min Max Unit

V f f

HCLK

PCLK

DDA

(1)

BAT

Internal AHB clock frequency

Internal APB clock frequency

Standard operating voltage

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Backup operating voltage

Must have a potential equal to or higher than V

I/O input voltage

TC I/O

TTa I/O

FT and FTf I/O

(2)

BOOT0

LQFP48

Power dissipation at T

= 85 °C for suffix 6 or T suffix 7

(3)

= 105 °C for

UFQFPN32

UFQFPN28

TSSOP20

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

Maximum power dissipation

Low power dissipation

(4)

Maximum power dissipation

Low power dissipation

(4)

Junction temperature range

6 suffix version

7 suffix version

2.4

1.65

3.6

–0.3

+0.3

–0.3

DDA

+0.3

–0.3

5.5

–40

3.6

5.5

364

526

169

182

–40 105

–40 125

–40

105

125

MHz

V mW

°C

When the ADC is used, refer to

Table 49: ADC characteristics

To sustain a voltage higher than V

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

(see

Table 14: Thermal characteristics

In low power dissipation state, T

Thermal characteristics

can be extended to this range as long as T

does not exceed T

Jmax

(see

Table 14:

DocID023683 Rev 2

39/101

Electrical characteristics STM32F050x4 STM32F050x6

6.3.3

The parameters given in

Table 16 are derived from tests performed under the ambient

temperature condition summarized in

Table 15 .

Symbol t

VDD t

VDDA

Table 16. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameter given in Table 17

is derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 15: General operating conditions .

Symbol

Table 17. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

POR/PDR

(1)

Power on/power down reset threshold

Falling edge 1.8

(2) 1.88

1.96

Rising edge 1.84

1.92

2.0

PDRhyst

(1) t

RSTTEMPO

(3)

PDR hysteresis

Reset temporization

1.5

2.5

4.5

The PDR detector monitors V

DD monitors only V

and also V

DDA

(if kept enabled in the option bytes). The POR detector

The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

Guaranteed by design, not tested in production.

mV ms

Symbol

PVD0

PVD1

PVD2

PVD3

PVD4

Table 18. Programmable voltage detector characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

PVD threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.28

2.18

2.38

2.28

2.1

2.19

2.09

2.47

2.37

2.18

2.26

2.08

2.16

2.28

2.37

2.18

2.27

2.38

2.48

2.28

2.38

2.48

2.58

2.38

2.48

2.58

2.69

2.48

2.59

Unit

40/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Table 18. Programmable voltage detector characteristics (continued)

Symbol Parameter Conditions Min

(1)

Typ Max

(1)

Rising edge

PVD5

PVD threshold 5

Falling edge

Rising edge

PVD6

PVD threshold 6

Falling edge

Rising edge

PVD7

PVD threshold 7

Falling edge

PVDhyst

(2)

DD(PVD)

PVD hysteresis

PVD current consumption

Data based on characterization results only, not tested in production.

Guaranteed by design, not tested in production.

2.57

2.47

2.66

2.56

2.76

2.66

2.68

2.79

2.58

2.69

2.78

2.9

2.68

2.88

2.78

100

2.8

2.9

0.15

0.26

Unit

V mV

µA

The parameters given in

Table 19 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in Table 15: General operating conditions

Table 19. Embedded internal reference voltage

Parameter Conditions Min Typ Max Symbol Unit

REFINT

Internal reference voltage

–40 °C < T

< +105 °C 1.16 1.2

1.25

–40 °C < T

< +85 °C 1.16 1.2 1.24

(1)

S_vrefint

Δ V

(2)

REFINT

ADC sampling time when reading the internal reference voltage

Internal reference voltage spread over the temperature range

DDA

= 3 V ±10 mV

5.1

17.1

(3)

µs mV

Coeff

Temperature coefficient -

Data based on characterization results, not tested in production.

Shortest sampling time can be determined in the application by multiple iterations.

Guaranteed by design, not tested in production.

100

(3) ppm/°C

DocID023683 Rev 2

41/101

Electrical characteristics

6.3.5

STM32F050x4 STM32F050x6

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 11: Current consumption measurement scheme

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

The data provided apply to standard dies only.

Typical and maximum current consumption

The MCU is placed under the following conditions:

•

All I/O pins are in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except when explicitly mentioned

•

The Flash memory access time is adjusted to the f

HCLK

frequency (0 wait state from 0 to 24 MHz and 1 wait state above 24 MHz)

• Prefetch is ON when the peripherals are enabled, otherwise it is OFF (to enable prefetch the PRFTBE bit in the FLASH_ACR register must be set before clock setting and bus prescaling)

•

When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in

Table 20 to

Table 26

are derived from tests performed under ambient temperature and supply voltage conditions summarized in

Table 15: General operating conditions

42/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Table 20. Typical and maximum current consumption from V

supply at V

= 3.6

All peripherals enabled All peripherals disabled

Symbol

Parameter

Conditions f

HCLK

Typ

Max @ T

A(1)

Typ

Max @ T

A(1)

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Unit

IDD

Supply current in

Run mode, executing from Flash

External clock (HSE bypass)

Internal clock (HSI)

Supply current in

Run mode, executing from RAM

External clock (HSE bypass)

Internal clock (HSI)

Supply current in

Sleep mode, executing from Flash or RAM

External clock (HSE bypass)

Internal clock (HSI)

48 MHz 18.4

20.0

20.1

20.4

11.4

12.5

12.6

32 MHz 12.4

13.2

13.8

7.9

8.3

8.5

8.6

24 MHz 9.9

10.7

11.0

6.2

6.8

7.0

8 MHz 3.3

3.6

3.8

3.9

2.2

2.6

1 MHz 0.8

1.1

0.7

0.9

48 MHz 18.9

20.9

21.1

21.5

11.7

12.3

12.9

13.1

32 MHz 12.8

13.7

14.2

14.8

8.0

8.7

9.1

24 MHz 9.7

10.4

11.2

11.3

6.1

6.5

6.7

6.9

8 MHz 3.5

4.0

4.1

2.4

2.6

2.7

48 MHz 17.3

19.7

19.8

20.0

10.3

11.2

11.3

11.7

32 MHz 11.2

12.5

12.7

6.7

7.3

7.6

24 MHz 8.9

10.0

10.1

10.2

5.1

5.5

5.8

5.9

8 MHz 2.8

3.1

3.3

3.4

1.7

2.0

2.1

1 MHz 0.3

0.6

1.3

0.2

0.5

0.8

48 MHz 17.4

19.7

20.0

20.2

10.4

11.2

11.3

11.8

32 MHz 11.8

12.8

13.1

13.3

6.8

7.4

7.7

7.9

24 MHz 9.0

10.0

10.1

10.2

5.2

5.7

6.0

8 MHz 3.0

3.2

3.5

3.6

1.8

2.0

2.2

48 MHz 10.7

11.7

11.9

12.5

2.4

2.6

2.7

2.9

32 MHz 7.1

7.8

8.1

8.2

1.6

1.7

1.9

24 MHz 5.5

6.3

6.4

1.3

1.4

1.5

8 MHz 1.8

2.0

2.1

0.4

0.5

1 MHz 0.2

0.5

0.1

48 MHz 10.8

11.9

12.1

12.6

2.4

2.7

2.9

32 MHz 7.3

8.0

8.4

8.5

1.7

1.9

2.0

24 MHz 5.5

6.2

6.5

1.3

1.5

1.6

8 MHz 1.9

2.2

2.3

2.4

0.5

0.6

DocID023683 Rev 2

43/101

Electrical characteristics STM32F050x4 STM32F050x6

Table 21. Typical and maximum current consumption from the V

DDA

supply

DDA

= 2.4 V V

DDA

= 3.6 V

Symbol Parameter

Conditions

(1) f

HCLK

Max @ T

(2)

Max @ T

(2)

Typ Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Unit

DDA

Supply current in

Run mode, code executing from Flash or RAM

Supply current in

Sleep mode, code executing from Flash or RAM

HSE bypass,

PLL on

48 MHz 150 170

32 MHz 104 121

24 MHz 82

8 MHz 2.0

2.7

HSE bypass,

PLL off

1 MHz 2.0

2.7

48 MHz 220 240

HSI clock,

PLL on

32 MHz 174 191

24 MHz 152 167

HSI clock,

PLL off

8 MHz 72 79

HSE bypass,

PLL on

48 MHz 150 170

32 MHz 104 121

24 MHz 82

8 MHz 2.0

2.7

HSE bypass,

PLL off

1 MHz 2.0

2.7

48 MHz 220 240

HSI clock,

PLL on

32 MHz 174 191

24 MHz 152 167

HSI clock,

PLL off

8 MHz 72 79

178

126

100

3.1

248

196

173

178

126

100

3.1

248

196

173

182 164 183

128

103

3.3

252

198

174

182 164 183

128

103

3.3

252

198

174

113

3.5

244

193

168

83.5

113

3.5

244

193

168

83.5

129

102

3.8

263

209

183

129

102

3.8

263

209

183

195

135

106

4.1

275

215

190

195

135

106

4.1

275

215

190

198

138

108

4.4

278

218

192

198

138

108

4.4

278

218

192

Current consumption from the V

DDA

PLL is off, I

DDA

supply is independent of whether the peripherals are on or off. Furthermore when the is independent from the frequency.

Data based on characterization results, not tested in production.

µA

44/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Table 22. Typical and maximum V

consumption in Stop and Standby modes

Typ @V

= V

DDA

) Max

(1)

Symbol Parameter Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

85 °C

105 °C

Unit

Supply current in

Stop mode

Regulator in run mode, all oscillators OFF

Regulator in low-power mode, all oscillators

OFF

Supply current in

Standby mode

LSI ON and IWDG ON

LSI OFF and IWDG

OFF

3.15

0.8

0.65

15.1 15.25 15.45 15.7

3.25

0.95

0.75

3.35

1.05

0.85

3.45

1.2

0.95

3.7

1.35

1.1

1.5

1.3

5.5

(2)

Data based on characterization results, not tested in production unless otherwise specified.

Data based on characterization results and tested in production.

2.5

(2)

µA

upply current

Table 23. Typical and maximum V

DDA

consumption in Stop and Standby modes

Typ @V

= V

DDA

) Max

(1)

Symbol Parameter Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

85 °C

105 °C

Unit

Supply current in

Stop mode

Regulator in run mode, all oscillators OFF

1.85

2 2.15

2.3

2.45

2.6

3.5

Regulator in low-power mode, all oscillators

OFF

1.85

2 2.15

2.3

2.45

2.6

3.5

LSI ON and IWDG ON 2.25

2.5

2.65 2.85 3.05

3.3

Supply current in

Standby mode

LSI OFF and IWDG

OFF

1.75

1.9

2 2.15

2.3

2.5

DDA

Supply current in

Stop mode

Regulator in run mode, all oscillators OFF

1.11 1.15 1.18 1.22 1.27 1.35

Regulator in low-power mode, all oscillators

OFF

1.11 1.15 1.18 1.22 1.27 1.35

LSI ON and IWDG ON 1.5

1.58 1.65 1.78 1.91 2.04

Supply current in

Standby mode

LSI OFF and IWDG

OFF

1 1.02 1.05 1.05 1.15 1.22

Data based on characterization results, not tested in production.

3.5

4.5

µA

DocID023683 Rev 2

45/101

Electrical characteristics STM32F050x4 STM32F050x6

Table 24. Typical and maximum current consumption from V

BAT

supply

Typ @ V

BAT

Max

(1)

Symbol Parameter Conditions

25 °C

85 °C

105 °C

Unit

VBAT

Backup domain supply current

LSE & RTC ON; “Xtal mode”: lower driving capability;

LSEDRV[1:0] = '00'

0.41 0.43 0.53 0.58 0.71 0.80

0.85

LSE & RTC ON; “Xtal mode” higher driving capability;

LSEDRV[1:0] = '11'

0.71 0.75 0.85 0.91 1.06 1.16

1.25

Data based on characterization results, not tested in production.

1.1

1.55

1.5

µA

Typical current consumption

The MCU is placed under the following conditions:

• V

DDA

=3.3 V

• All I/O pins are in analog input configuration

•

The Flash access time is adjusted to f

HCLK

frequency (0 wait states from 0 to 24 MHz,

1 wait state above)

• Prefetch is ON when the peripherals are enabled, otherwise it is OFF

•

When the peripherals are enabled, f

PCLK

= f

HCLK

• PLL is used for frequencies greater than 8 MHz

•

AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

500 kHz respectively

• A development tool is connected to the board and the parasitic pull-up current is around 30 µA

46/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Table 25. Typical current consumption in Run mode, code with data processing running from Flash

Typ

Symbol Parameter Conditions f

HCLK Peripherals enabled

Peripherals disabled

Unit

DDA

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

Supply current in Run mode from V

DD supply

8 MHz

4 MHz

2 MHz

Running from

HSE crystal clock 8 MHz, code executing from Flash

1 MHz

500 kHz

48 MHz

36 MHz

32 MHz

Supply current in Run mode from V

DDA supply

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

0.6

140

109

3.3

1.7

1.3

0.8

18.4

13.9

12.4

9.9

6.6

1.7

1.6

1.5

1.1

µA

0.6

140

109

2.2

1.6

1.2

0.7

11.4

8.9

7.9

6.2

4.3

1.7

1.6

1.5

1.1

DocID023683 Rev 2

47/101

Electrical characteristics STM32F050x4 STM32F050x6

Table 26. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typ

Symbol Parameter Conditions f

HCLK Peripherals enabled

Peripherals disabled

Unit

DDA

Supply current in

Sleep mode from V

DD supply

Supply current in

Sleep mode from

DDA

supply

Running from

HSE crystal clock 8 MHz, code executing from Flash or

RAM

0.6

0.5

140

109

1.9

1.5

1.1

0.8

10.7

8.1

7.1

5.5

3.7

1.7

1.6

1.5

1.1

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz mA

µA

0.3

140

109

0.5

0.4

0.3

2.4

1.8

1.6

1.3

0.9

1.7

1.6

1.5

1.1

48/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 45: I/O static characteristics .

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 28: Peripheral current consumption ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

= V

× f

× C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

DocID023683 Rev 2

49/101

Electrical characteristics STM32F050x4 STM32F050x6

Symbol

Table 27. Switching output I/O current consumption

Parameter Conditions

(1)

I/O toggling frequency (f

)

4 MHz

I/O current consumption

= 3.3 V

C =C

INT

= 3.3 V

EXT

= 0 pF

C = C

INT

+ C

EXT

+ C

= 3.3 V

EXT

= 10 pF

C = C

INT

+ C

EXT

+ C

= 3.3 V

EXT

= 22 pF

C = C

INT

+ C

EXT

+ C

= 3.3 V

EXT

= 33 pF

C = C

INT

+ C

EXT

+ C

= 3.3 V

EXT

= 47 pF

C = C

INT

+ C

EXT

+ C

C = C int

= 2.4 V

EXT

= 47 pF

C = C

INT

+ C

EXT

+ C

C = C int

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

24 MHz

4 MHz

8 MHz

16 MHz

24 MHz

4 MHz

8 MHz

16 MHz

4 MHz

8 MHz

16 MHz

24 MHz

Typ

0.07

3.67

0.66

1.43

2.45

4.97

1.39

2.188

0.32

0.64

1.25

2.23

4.442

0.49

0.15

0.31

0.53

0.92

0.18

0.37

0.76

1.25

3.24

5.02

0.81

1.7

0.94

2.38

3.99

0.64

= 7 pF (estimated value).

Unit mA

50/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 28 . The MCU is placed

under the following conditions:

• all I/O pins are in input mode with a static value at V

or V

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature and V

supply voltage conditions summarized in

Table 12: Voltage characteristics

Table 28. Peripheral current consumption

Typical consumption at 25 °C

Peripheral Unit

ADC

(1)

CRC

DBGMCU

DMA

GPIOA

GPIOB

GPIOC

GPIOF

I2C1

PWR

SPI1/I2S1

SYSCFG

TIM1

TIM2

TIM3

TIM6

TIM14

TIM16

TIM17

USART1

WWDG

0.53

0.10

0.18

0.35

0.48

0.58

0.12

0.06

0.43

0.22

0.63

0.28

1.01

1.00

0.78

0.32

0.45

0.57

0.59

1.07

0.22

DDA

0.964

ADC is in ready state after setting the ADEN bit in the ADC_CR register (ADRDY bit in ADC_ISR is high).

DocID023683 Rev 2

51/101

Electrical characteristics STM32F050x4 STM32F050x6

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.13

. However,

Symbol

Table 29. High-speed external user clock characteristics

Parameter

(1) f

HSE_ext

User external clock source frequency

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

Guaranteed by design, not tested in production.

Conditions Min

0.7V

Typ Max Unit

0.3V

MHz

V ns

Figure 12. High-speed external clock source AC timing diagram

WZ+6(+

9+6(+

9+6(/

WU+6(

7+6(

WI+6( WZ+6(/

069

52/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.13

. However,

Symbol

Table 30. Low-speed external user clock characteristics

Parameter

(1) f

LSE_ext

LSEH

User External clock source frequency

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

OSC32_IN high or low time

OSC32_IN rise or fall time

Guaranteed by design, not tested in production.

Conditions Min

0.7V

450

Typ

32.768

Max

1000

0.3V

Unit kHz

V ns

Figure 13. Low-speed external clock source AC timing diagram

WZ/6(+

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

WZ/6(/

069

DocID023683 Rev 2

53/101

Electrical characteristics

Note:

STM32F050x4 STM32F050x6

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 31 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 31. HSE oscillator characteristics

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit f

OSC_IN

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

=3.3 V, Rm= 30 Ω ,

CL=10 pF@8 MHz

=3.3 V, Rm= 45 Ω ,

CL=10 pF@8 MHz

=3.3 V, Rm= 30 Ω ,

CL=5 pF@32 MHz

=3.3 V, Rm= 30 Ω ,

CL=10 pF@32 MHz

=3.3 V, Rm= 30 Ω ,

CL=20 pF@32 MHz

200

0.4

0.5

0.8

1.5

8.5

MHz k Ω mA g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

2 -

mA/V ms

Resonator characteristics given by the crystal/ceramic resonator manufacturer.

Guaranteed by design, not tested in production.

This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 14

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

54/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

([WHUQDO

UHVHWFLUFXLW

Figure 14. Typical application with an 8 MHz crystal

)

1567

)LOWHU

,QWHUQDOUHVHW

069

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results

obtained with typical external components specified in Table 32

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 32. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit

LSE current consumption

LSEDRV[1:0]=00 lower driving capability

LSEDRV[1:0]= 01 medium low driving capability

LSEDRV[1:0] = 10 medium high driving capability

LSEDRV[1:0]=11 higher driving capability

0.5

0.9

1.3

1.6

µA

LSEDRV[1:0]=00 lower driving capability

LSEDRV[1:0]= 01 medium low driving capability

8 -

g m

Oscillator transconductance

µA/V

LSEDRV[1:0] = 10 medium high driving capability

15 -

LSEDRV[1:0]=11 higher driving capability

25 t

SU(LSE)

(3)

Startup time V

is stabilized 2 -

Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

Guaranteed by design, not tested in production.

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

DocID023683 Rev 2

55/101

Electrical characteristics

Note:

STM32F050x4 STM32F050x6

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 15. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWKLQWHJUDWHG

FDSDFLWRUV

26&B,1 I

+6(

N+]

UHVRQDWRU

'ULYH

SURJUDPPDEOH

DPSOLILHU

26&B287

Note:

069

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

56/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

6.3.7

Electrical characteristics

Internal clock source characteristics

The parameters given in

Table 33 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 15: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI) RC oscillator

Table 33. HSI oscillator characteristics

(1)

Parameter Conditions Min Typ Symbol f

HSI

TRIM

DuCy

(HSI)

Frequency

HSI user trimming step

Duty cycle

ACC

HSI

Accuracy of the HSI oscillator (factory calibrated)

= –40 to 105 °C

= –10 to 85 °C

= 0 to 70 °C

= 25 °C

I t su(HSI)

DDA(HSI)

HSI oscillator startup time

HSI oscillator power consumption

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

Guaranteed by design, not tested in production.

Data based on characterization results, not tested in production.

(2)

–3.8

(3)

–2.9

(3)

–2.3

(3)

–1

(2)

Max

(2)

4.6

(3)

2.9

(3)

2.2

(3)

(2)

100

(2)

Unit

MHz

µs

µA

Figure 16. HSI oscillator accuracy characterization results

!##

(3)

-!8

-).

4!; #=

DocID023683 Rev 2

-36

57/101

Electrical characteristics STM32F050x4 STM32F050x6

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Table 34. HSI14 oscillator characteristics

(1)

Parameter Conditions Min Typ Symbol f

HSI14

TRIM

Frequency

HSI14 user-trimming step

DuCy

(HSI14)

Duty cycle

ACC

HSI14

Accuracy of the HSI14 oscillator (factory calibrated)

= 25 °C

(2)

= –40 to 105 °C –4.2

(3)

= –10 to 85 °C –3.2

(3)

= 0 to 70 °C –2.5

(3)

–1

(2) t su(HSI14)

DDA(HSI14)

HSI14 oscillator startup time

HSI14 oscillator power consumption

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

Guaranteed by design, not tested in production.

Data based on characterization results, not tested in production.

100 150

(2)

5.1

(3)

3.1

(3)

2.3

(3)

(2)

Max Unit

µs

MHz

µA

Figure 17. HSI14 oscillator accuracy characterization results

-!8

-).

-36

58/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 35. LSI oscillator characteristics

(1)

Parameter Min Typ Symbol f

LSI t su(LSI)

(2)

DDA(LSI)

(2)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

DDA

= 3.3 V , T

= –40 to 105 °C unless otherwise specified.

Guaranteed by design, not tested in production.

0.75

Max

1.2

Unit kHz

µs

µA

Wakeup time from low-power mode

The wakeup times given in

Table 36 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The event used to wake up the device depends from the current operating mode:

• Stop or sleep mode: the wakeup event is WFE.

•

The wakeup pin used in sleep, stop and standby modes is PA0.

All timings are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 15: General operating conditions .

Symbol Parameter

Table 36. Low-power mode wakeup timings

Typ @V DD

Conditions

= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V

Max Unit t

WUSTOP

Wakeup from Stop mode

Regulator in run mode

Regulator in low power mode t t

WUSTANDBY

Wakeup from

Standby mode

WUSLEEP

Wakeup from Sleep mode

4.2

8.05

60.35

1.1

4.2

7.05

55.6

1.1

4.2

6.6

53.5

1.1

4.2

6.27

52.02

50.96

1.1

4.2

6.05

1.1

µs

DocID023683 Rev 2

59/101

Electrical characteristics STM32F050x4 STM32F050x6

The parameters given in

Table 37 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 15: General operating conditions

Table 37. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max f

PLL_IN

PLL input clock

(1)

PLL input clock duty cycle

(2)

8.0

(2)

MHz

% f

PLL_OUT t

LOCK

Jitter

PLL

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter -

200

300

(2)

MHz

Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by f

PLL_OUT

Guaranteed by design, not tested in production.

µs ps

60/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Flash memory

The characteristics are given at T

= –40 to 105 °C unless otherwise specified.

Table 38. Flash memory characteristics

Symbol t t

I prog

ERASE t

Parameter Conditions

16-bit programming time T

= –40 to +105 °C

Page (1 KB) erase time T

= –40 to +105 °C

Mass erase time T

= –40 to +105 °C

Write mode

Supply current

Erase mode

Min

Guaranteed by design, not tested in production.

Typ Max

(1)

53.5

Unit

µs ms ms mA mA

Symbol

Table 39. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle

(2)

at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

10 kcycle

(2)

at T

= 55 °C

Data based on characterization results, not tested in production.

Cycling performed over the whole temperature range.

Unit kcycles

Years

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in

Table 40

. They are based on the EMS levels and classes defined in application note AN1709.

DocID023683 Rev 2

61/101

Electrical characteristics STM32F050x4 STM32F050x6

Table 40. EMS characteristics

Symbol

FESD

EFTB

Parameter Conditions

Level/

Class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V

SS pins to induce a functional disturbance f

= 3.3 V, LQFP64, T

HCLK

= 48 MHz

= +25 °C, conforms to IEC 61000-4-2 f

= 3.3 V, LQFP64, T

HCLK

= 48 MHz

= +25 °C, conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

• Unexpected reset

•

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 41. EMI characteristics

Symbol

EMI

Parameter

Peak level

Conditions

= 3.6 V, T

= 25 °C,

LQFP64 package compliant with IEC

61967-2

Monitored frequency band

Max vs. [f

HSE

HCLK

]

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

8/48 MHz

-3

Unit dBµV

62/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 42. ESD absolute maximum ratings

Symbol Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

= +25 °C, conforming to JESD22-A114

Electrostatic discharge

ESD(CDM) voltage (charge device model)

= +25 °C, conforming to JESD22-C101

Data based on characterization results, not tested in production.

2000

500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

•

A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 43. Electrical sensitivities

Static latch-up class

Conditions

= +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

or above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (more than 5 LSB TUE), out of conventional limits of current injection on adjacent pins (more than

DocID023683 Rev 2

63/101

Electrical characteristics STM32F050x4 STM32F050x6

–5 µA) or other functional failure (reset occurrence or oscillator frequency deviation, for example).

The characterization results are given in

Table 44 .

Symbol

INJ

Table 44. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Unit

Injected current on BOOT0

Injected current on all FT and FTf pins with induced leakage current on adjacent pins less than –5 µA

Injected current on all TTa pins with induced leakage current on adjacent pins less than –5 µA

Injected current on all TC & RESET pins with induced leakage current on adjacent pins less than –5 µA

–0

–5

+5 mA

64/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Symbol

V hys

I lkg

General input/output characteristics

Unless otherwise specified, the parameters given in Table 45

are derived from tests

performed under the conditions summarized in Table 15: General operating conditions

. All

I/Os are CMOS and TTL compliant.

Parameter

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

Input leakage current

(2)

Table 45. I/O static characteristics

Conditions Min Typ

TC and TTa I/O

FT and FTf I/O

BOOT0 -

All I/Os except BOOT0 pin

TC and TTa I/O

FT and FTf I/O

BOOT0

All I/Os except BOOT0 pin

TC and TTa I/O

FT and FTf I/O

BOOT0

≤ V

I/O TC, FT and FTf

≤ V

2 V ≤ V

≤ V

DDA

≤ 3.6 V

I/O TTa used in digital mode

0.445 V

+0.398

(1)

0.5 V

+0.2

(1)

0.2 V

+0.95

(1)

0.7 V

200

(1)

100

(1)

300

(1)

= 5 V

I/O FT and FTf

2 V

≤ V

DDA =

3.6 V

≤

3.6 V

I/O TTa used in digital mode

≤ V

DDA

2 V ≤ V

≤ V

DDA

≤ 3.6 V

I/O TTa used in analog mode

Max

0.3 V

+0.07

(1)

0.475 V

–0.2

(1)

0.3 V

–0.3

(1)

0.3 V

±0.

Unit

V mV

±0.

µA

Weak pull-up equivalent resistor

(3)

= V

25 40 55 k Ω

DocID023683 Rev 2

65/101

Electrical characteristics STM32F050x4 STM32F050x6

Symbol Parameter

Table 45. I/O static characteristics (continued)

Conditions Min Typ Max

Weak pull-down equivalent resistor

(3)

I/O pin capacitance

= V

Data based on design simulation only. Not tested in production.

Leakage could be higher than maximum value, if negative current is injected on adjacent pins.

Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order)

Unit k Ω pF

66/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 18

and

Figure 19 for standard I/Os, and

Figure 20 and Figure 21 for 5 V tolerant I/Os. The following curves are design simulation

results, not tested in production.

,+PLQ

Figure 18. TC and TTa I/O input characteristics - CMOS port

,/PD[

7HVWHGLQSURGXFWLRQ

$UHDQRWGHWHUPLQHG

&026VWDQGDUGUHTXLUHPHQWV9

,+PLQ

%DVHGRQGHVLJQVLPXODWLRQV

,/PD[

%DVHGRQGHVLJQVLPXODWLRQV

&026VWDQGDUGUHTXLUHPHQWV9

,/PD[

7HVWHGLQSURGXFWLRQ

069

,+PLQ

Figure 19. TC and TTa I/O input characteristics - TTL port

,/PD[

$UHDQRWGHWHUPLQHG

77/VWDQGDUGUHTXLUHPHQWV9

,+PLQ

%DVHGRQGHVLJQVLPXODWLRQV

,/PD[

%DVHGRQGHVLJQVLPXODWLRQV

77/VWDQGDUGUHTXLUHPHQWV9

,/PD[

-36

DocID023683 Rev 2

67/101

Electrical characteristics STM32F050x4 STM32F050x6

Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port

$UHDQRWGHWHUPLQHG

,+PLQ

&026VWDQGDUGUHTXLUHPHQWV9

,+PLQ

%DVHGRQGHVLJQVLPXODWLRQV

&026VWDQGDUGUHTXLUHPHQWV9

,/PD[

9 ''

,/PD[

%DVHGRQGHVLJQVLPXODWLRQV

-36

Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port

$UHDQRWGHWHUPLQHG

77/VWDQGDUGUHTXLUHPHQWV9

,+PLQ

%DVHGRQGHVLJQVLPXODWLRQV

,/PD[

%DVHGRQGHVLJQVLPXODWLRQV

77/VWDQGDUGUHTXLUHPHQWV9

,/PD[

-36

68/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

OL/

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DD, plus the maximum Run consumption of the MCU sourced on V

DD, cannot exceed the absolute maximum rating

VDD

(see

Table 13: Current characteristics

•

The sum of the currents sunk by all the I/Os on V

plus the maximum Run consumption of the MCU sunk on V

cannot exceed the absolute maximum rating

VSS

(see

Table 13: Current characteristics ).

Output voltage levels

Unless otherwise specified, the parameters given in Table 46

are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 15: General operating conditions . All I/Os are CMOS and TTL compliant (FT, TTa or

TC unless otherwise specified).

Table 46. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= +8 mA

2.7 V < V

< 3.6 V

TTL port

(2)

=+ 8mA

2.7 V < V

< 3.6 V

–0.4

2.4

0.4

(1)(4)

(3)(4)

(1)(4)

(3)(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

2.7 V < V

= +20 mA

2 V < V

< 3.6 V

= +6 mA

< 2.7 V

–1.3

1.3

0.4

–0.4

OLFM+

(1)

Output low level voltage for an FTf I/O pin in FM+ mode

= +20 mA

2.7 V < V

< 3.6 V

0.4

The I

current sunk by the device must always respect the absolute maximum rating specified in

Table 13:

Current characteristics

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

The I

current sourced by the device must always respect the absolute maximum rating specified in

Table 13: Current characteristics

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

Data based on design simulation only. Not tested in production.

DocID023683 Rev 2

69/101

Electrical characteristics STM32F050x4 STM32F050x6

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 22 and

Table 47 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V

supply voltage conditions summarized in

Table 15: General operating conditions

Table 47. I/O AC characteristics

(1)

OSPEEDRy

[1:0] value

(1)

Symbol Parameter Conditions Min Max Unit x0

01 f max(IO)out

Maximum frequency

(2) t f(IO)out

Output high to low level fall time t r(IO)out f max(IO)out

Output low to high level rise time

Maximum frequency

(2) t t f(IO)out r(IO)out

Output high to low level fall time

Output low to high level rise time

= 50 pF, V

= 2 V to 3.6 V

125

(3)

125

(3)

MHz ns

11 f max(IO)out t t f(IO)out r(IO)out

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

= 30 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2.7 V to 3.6 V

= 50 pF, V

= 2 V to 2.7 V

= 50 pF, V

= 2 V to 3.6 V

= 50 pF, V

= 2 V to 3.6 V

(3)

MHz ns

FM+ configuration

(4)

f max(IO)out

Maximum frequency

(2) t f(IO)out

Output high to low level fall time t t r(IO)out

EXTIpw

Output low to high level rise time

Pulse width of external signals detected by the

EXTI controller

(3)

MHz ns ns

The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of

GPIO Port configuration register.

The maximum frequency is defined in Figure 22 .

Guaranteed by design, not tested in production.

When FM+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F05xxx reference manual RM0091 for a detailed description of FM+ I/O configuration.

70/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Figure 22. I/O AC characteristics definition

(;7(51$/

287387

21&/

WU,2RXW WI,2RXW

0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI7DQGLIWKHGXW\F\FOHLV

ZKHQORDGHGE\& / VSHFLILHGLQWKHWDEOH³ ,2$&FKDUDFWHULVWLFV ´

DLG

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 45: I/O static characteristics ).

Unless otherwise specified, the parameters given in Table 48

are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in

Table 15: General operating conditions .

Symbol

Table 48. NRST pin characteristics

Parameter Conditions Min Typ Max Unit

IL(NRST)

(1)

IH(NRST)

(1)

NRST input low level voltage

NRST input high level voltage

V hys(NRST)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

F(NRST)

(1)

NF(NRST)

(1)

NRST input filtered pulse

NRST input not filtered pulse

= V

–0.3

300

200

0.8

+0.3

100

Guaranteed by design, not tested in production.

The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)

V mV k Ω ns ns

DocID023683 Rev 2

71/101

Electrical characteristics STM32F050x4 STM32F050x6

Figure 23. Recommended NRST pin protection

([WHUQDO

UHVHWFLUFXLW

)

1567

)LOWHU

,QWHUQDOUHVHW

069

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 48 . Otherwise the reset will not be taken into account by the device.

72/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Note:

Unless otherwise specified, the parameters given in Table 49 are preliminary values derived

from tests performed under ambient temperature, f

PCLK2 frequency and V

DDA

supply voltage conditions summarized in

Table 15: General operating conditions .

It is recommended to perform a calibration after each power-up.

Symbol

DDA f

ADC f

(1) f

TRIG

(1)

AIN

(1)

ADC

(1)

ADC

(1) t

CAL

(1) t latr

(1)

Parameter

Analog supply voltage for

ADC ON

ADC clock frequency

Sampling rate

Table 49. ADC characteristics

Conditions Min

2.4

External trigger frequency

Conversion voltage range

External input impedance f

ADC

= 14 MHz

See Equation 1 and

Table 50

for details

0.6

0.05

Sampling switch resistance

Internal sample and hold capacitor

Calibration time

Trigger conversion latency f

ADC

= 14 MHz

ADC

= f

PCLK

/2 = 14 MHz f

ADC

= f

PCLK f

ADC

= f

PCLK

/4 = 12 MHz f

ADC

= f

PCLK

/4 f

ADC

= f

HSI14

= 14 MHz 0.188

Jitter

ADC

ADC jitter on trigger conversion f

ADC

= f

HSI14

(1) t

STAB

(1)

Sampling time

Power-up time t

CONV

(1)

Total conversion time

(including sampling time) f

ADC

= 14 MHz

ADC

= 14 MHz

Typ

5.9

0.196

0.219

10.5

Max

3.6

823

DDA

0.259

Unit

MHz

MHz kHz

1/f

ADC

V k Ω k Ω pF

µs

1/f

ADC

µs

1/f

PCLK

µs

1/f

HSI14

0.107

1.5

17.1

239.5

µs

1/f

ADC

µs

1 18

14 to 252 (t

for sampling +12.5 for successive approximation)

µs

1/f

ADC

Guaranteed by design, not tested in production.

DocID023683 Rev 2

73/101

Electrical characteristics STM32F050x4 STM32F050x6

Equation 1: R

AIN

max formula

AIN

< f

----------------------------------------------------------------

ADC

× C

ADC

× ln ( 2 )

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 50. R

AIN

max for f

ADC

= 14 MHz

(1)

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

Guaranteed by design, not tested in production.

(µs)

2.96

3.96

5.11

17.1

0.11

0.54

0.96

2.04

AIN

max (k Ω )

0.4

5.9

11.4

25.2

37.2

Symbol Parameter

Table 51. ADC accuracy

(1)(2) (3)

Test conditions

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f f f f

PCLK

ADC

= 14 MHz, R

DDA

= 3 V to 3.6 V

= 25 °C f

PCLK

= 48 MHz, f

ADC

= 14 MHz, R

AIN

< 10 k Ω ,

DDA

= 2.7 V to 3.6 V

−

40 to 105 °C

PCLK

ADC

DDA

= 48 MHz,

= 25 °C

= 14 MHz, R

AIN

ADC DC accuracy values are measured after internal calibration.

< 10 k Ω ,

< 10 k

= 2.4 V to 3.6 V

Ω ,

Typ

±1.9

±2.8

±0.7

±1.2

±2.8

±0.7

±1.2

±3.3

±1.3

±1

±0.5

±0.7

±0.8

±3.3

±1.9

Max

(4)

±2.8

±3

±1.3

±1.7

±3

±1.3

±1.7

±4

±2

±1.5

±1

±1.5

±4

±2.8

Unit

LSB

74/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and

INJ(PIN)

in Section 6.3.13

does not

Better performance may be achieved in restricted V

DDA

, frequency and temperature ranges.

Data based on characterization results, not tested in production.

Figure 24. ADC accuracy characteristics

66$

(

9 $,1

5 $,1

(

([DPSOHRIDQDFWXDO WUDQVIHUFXUYH

7KHLGHDOWUDQVIHUFXUYH

(QG SRLQWFRUUHODWLRQOLQH

(

7RWDO 8QDGMXVWHG (UURU PD[LPXP GHYLDWLRQ

EHWZHHQ WKHDFWXDODQGWKHLGHDOWUDQVIHU FXUYHV

(

2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO

WUDQVLWLRQDQGWKH ILUVWLGHDORQH

(

*DLQ (UURU GHYLDWLRQ EHWZHHQ WKH ODVW LGHDO

WUDQVLWLRQDQGWKH ODVWDFWXDORQH

(

'LIIHUHQWLDO/LQHDULW\(UURU PD[LPXPGHYLDWLRQ

EHWZHHQ DFWXDOVWHSVDQGWKHLGHDORQH

(

,QWHJUDO /LQHDULW\ (UURU PD[LPXP GHYLDWLRQ

EHWZHHQ DQ\ DFWXDO WUDQVLWLRQ DQG WKH HQG SRLQW

FRUUHODWLRQOLQH

/6%

,'($/

''$

Figure 25. Typical connection diagram using the ADC

-36

9 ''$

9 7

$,1[

& SDUDVLWLF

9 7

, / $

6DPSOHDQGKROG$'&

FRQYHUWHU

$'&

ELW

FRQYHUWHU

& $'&

069

Refer to Table 49: ADC characteristics for the values of R

AIN

, R

ADC

and C

ADC

C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high C this, f

ADC

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 10

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DocID023683 Rev 2

75/101

Electrical characteristics STM32F050x4 STM32F050x6

6.3.16 Temperature sensor characteristics

Table 52. TS characteristics

Symbol

(1)

Avg_Slope

(1)

25 t

START

(1)

S_temp

(1)(2)

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature

Min

4.0

1.34

17.1

Guaranteed by design, not tested in production.

Shortest sampling time can be determined in the application by multiple iterations.

Typ

± 1

4.3

1.43

Max

± 2

4.6

1.52

Unit

°C mV/°C

µs

6.3.17 V

BAT monitoring characteristics

Symbol

Table 53. V

BAT

monitoring characteristics

Parameter Min Typ

(1)

S_vbat

(1)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1mV accuracy

–1

Guaranteed by design, not tested in production.

Shortest sampling time can be determined in the application by multiple iterations.

Max

Unit

K Ω

µs

The parameters given in

Table 54 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol t res(TIM) f

EXT

Res

TIM

Table 54. TIMx

(1)

characteristics

Conditions Min Max Parameter

Timer resolution time

TIMxCLK

= 48 MHz 20.8

Timer external clock frequency on CH1 to CH4 f

TIMxCLK

= 48 MHz

TIMx (except TIM2)

Timer resolution

TIM2 -

TIMxCLK

32 bit

Unit t

TIMxCLK ns

MHz

76/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Table 54. TIMx

(1)

characteristics (continued)

Parameter Conditions Min Max Symbol Unit t

COUNTER

16-bit counter clock period

TIMxCLK

= 48 MHz 0.0208

MAX_COUNT

Maximum possible count with 32-bit counter

TIMxCLK

= 48 MHz -

65536

1365

65536 × 65536

89.48

t t

TIMxCLK

µs

TIMxCLK s

TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17 timers.

Table 55. IWDG min/max timeout period at 40 kHz (LSI)

(1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1638.4

3276.8

6553.6

13107.2

26214.4

These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from

30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 56. WWDG min-max timeout value @48 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.0853

0.1706

0.3413

0.6826

5.4613

10.9226

21.8453

43.6906

Unit ms

DocID023683 Rev 2

77/101

Electrical characteristics STM32F050x4 STM32F050x6

I

C interface characteristics

Unless otherwise specified, the parameters given in Table 57

are derived from tests performed under ambient temperature, f

PCLK frequency and V summarized in

Table 15: General operating conditions .

supply voltage conditions

The I

C interface meets the requirements of the standard I

C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I

C characteristics are described in

Table 57

. Refer also to

Section 6.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

Table 57. I

C characteristics

(1)

Standard mode Fast mode Fast Mode Plus

Symbol Parameter Unit

Min Max Min Max Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time t su(STA)

Start condition hold time

Repeated Start condition setup time t su(STO)

Stop condition setup time t w(STO:STA)

Stop to Start condition time

(bus free)

4.7

4.0

250

(3)

4.0

4.7

4.0

4.7

3450

300

(2)

1000

1.3

0.6

100

(3)

0.6

900

300

0.6 -

0.6

1.3

(2)

0.5

0.26

(4)

0.26

0.5

450

(2)

120

µs ns

µs

μ s s

C b

Capacitive load for each bus line

400 400 550 pF

The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when

I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in production.

The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

78/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Table 58. I2C analog filter characteristics

(1)

Parameter Min Max Symbol t

Pulse width of spikes that are suppressed by the analog filter

Guaranteed by design, not tested in production.

50 260

Figure 26. I

C bus AC waveforms and measurement circuit

6$$ 6$$

2 2 -#5

) #BUS

3$!

3#,

Unit ns

3 4!242%0%!4%$

3 4!24

TSU34!

3 4!24

3$!

TF3$!

TH34!

TR3$!

TW3#,,

TSU3$!

TH3$!

3 4/0

TW34/34!

3#,

TW3#,( TR3#,

TF3#,

TSU34/

-36

Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

SPI/I

S characteristics

Unless otherwise specified, the parameters given in Table 59

for SPI or in

Table 60 for I

S are derived from tests performed under ambient temperature, f

PCLKx frequency and V

supply voltage conditions summarized in Table 15: General operating conditions

Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I

S).

DocID023683 Rev 2

79/101

Electrical characteristics STM32F050x4 STM32F050x6

Symbol Parameter

Table 59. SPI characteristics

Conditions Min Max Unit f

SCK

1/t c(SCK) t r(SCK) t f(SCK) t su(NSS)

(1) t h(NSS)

(1) t t w(SCKH)

(1) w(SCKL)

(1) t t su(MI)

(1) su(SI)

(1) t h(MI)

(1) t h(SI)

(1) t a(SO)

(1)(2) t dis(SO)

(1)(3) t v(SO)

(1) t v(MO)

(1) t h(SO)

(1) t h(MO)

(1)

DuCy(SCK)

SPI clock frequency

Master mode

Slave mode

SPI clock rise and fall time

NSS setup time

Data output valid time

Capacitive load: C = 15 pF

Slave mode

NSS hold time

SCK high and low time

Slave mode

Master mode, f

PCLK

= 36 MHz, presc = 4

Master mode

Data input setup time

Slave mode

Master mode

Data input hold time

Slave mode

Data output access time Slave mode, f

PCLK

= 20 MHz

Data output disable time Slave mode

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Data output hold time

Master mode (after enable edge)

SPI slave input clock duty cycle

Slave mode

4Tpclk

2Tpclk + 10

Tpclk/2 -2

11.5

3Tpclk

22.5

Tpclk/2 + 1

MHz ns ns

Data based on characterization results, not tested in production.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

Figure 27. SPI timing diagram - slave mode and CPHA = 0

E^^ŝŶƉƵƚ ƚĐ;^<Ϳ ƚ^h;E^^Ϳ

W,сϬ

WK>сϬ

W,сϬ

WK>сϭ ƚǁ;^<,Ϳ ƚǁ;^<>Ϳ ƚĂ;^KͿ

D/^K

KhdW hd ƚƐƵ;^/Ϳ

DK^/

/EWhd ƚǀ;^KͿ

D^ K hd

D^ /E ƚŚ;^/Ϳ ƚŚ;^KͿ

/dϲ Khd

/ dϭ /E ƚƌ;^<Ϳ ƚĨ;^<Ϳ

>^ Khd ƚĚŝƐ;^KͿ

>^ /E ƚŚ;E^^Ϳ

DLF

80/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Figure 28. SPI timing diagram - slave mode and CPHA = 1

(1)

166LQSXW

W68166

&3+$

&32/

&3+$

&32/

WZ6&.+

WZ6&./

0,62

287 3 87

WD62

WVX6,

026,

, 1387

WF6&.

WY62

06 % 2 87

WK6,

0 6% ,1 % , 7 ,1

WK62

%, 7 287

WK166

WU6&.

WI6&.

WGLV62

/6% 287

/6% ,1

Measurement points are done at CMOS levels: 0.3V

and 0.7V

Figure 29. SPI timing diagram - master mode

(1)

(IGH

.33INPUT

TC3#+

#0(!

#0/,

#0(!

#0/,

#0(!

#0/,

#0(!

#0/,

-)3/

).0 54

-/3)

/54054

TSU-)

TW3#+(

TW3#+,

-3 ").

TH-)

- 3"/54

TV-/

") 4).

" ) 4/54

TH-/

Measurement points are done at CMOS levels: 0.3V

and 0.7V

TR3#+

TF3#+

,3").

,3"/54

AI6

DocID023683 Rev 2

81/101

Electrical characteristics STM32F050x4 STM32F050x6

Table 60. I

S characteristics

Conditions Symbol Parameter f

1/t c(CK)

S clock frequency

Master mode (data: 16 bits, Audio frequency = 48 kHz)

Slave mode t t t t t r(CK) t f(CK) t w(CKH)

(1) t w(CKL)

(1) t v(WS)

(1) t h(WS)

(1) t su(WS)

(1) t h(WS)

(1)

DuCy(SCK) t su(SD_MR)

(1) t su(SD_SR)

(1) t h(SD_MR)

(1)(2) t h(SD_SR)

(1)(2) v(SD_ST)

(1)(2) h(SD_ST)

(1) v(SD_MT)

(1)(2) h(SD_MT)

(1)

S clock rise time

S clock fall time

I2S clock high time

I2S clock low time

WS valid time

WS hold time

WS setup time

WS hold time

I2S slave input clock duty cycle

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Capacitive load C

Master f

PCLK

Master mode

Slave mode

= 16 MHz, audio frequency = 48 kHz

Slave mode

= 15 pF

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Data based on design simulation and/or characterization results, not tested in production.

Depends on f

PCLK

. For example, if f

PCLK

=8 MHz, then T

PCLK

= 1/f

PLCLK

=125 ns.

Min

0.5

1.597

306

312

Max

1.601

6.5

Unit

MHz ns

% ns

82/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Electrical characteristics

Figure 30. I2S slave timing diagram (Philips protocol)

WF&.

&32/

WZ&.+ WZ&./ WK:6

:6LQSXW

6'WUDQVPLW

WVX:6

/6%WUDQVPLW

WVX6'B65

/6%UHFHLYH

06%WUDQVPLW

06%UHFHLYH

WY6'B67

%LWQWUDQVPLW

WK6'B65

%LWQUHFHLYH

WK6'B67

/6%WUDQVPLW

/6%UHFHLYH 6'UHFHLYH

DLE

Measurement points are done at CMOS levels: 0.3 × V DD and 0.7 × V DD .

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 31. I2S master timing diagram (Philips protocol)

TF#+ TR#+

TC#+

#0/,

TW#+(

#0/,

TV73 TW#+, TH73

73OUTPUT

3$TRANSMIT

,3"TRANSMIT

TSU3$?-2

,3"RECEIVE

-3"TRANSMIT

-3"RECEIVE

TV3$?-4

"ITNTRANSMIT

TH3$?-2

"ITNRECEIVE

TH3$?-4

,3"TRANSMIT

,3"RECEIVE 3$RECEIVE

AIB

Data based on characterization results, not tested in production.

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DocID023683 Rev 2

83/101

Package information STM32F050x4 STM32F050x6

7.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

LQFP48 package information

Figure 32. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

Drawing is not to scale.

"?-%?6

84/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Package information

Symbol

Table 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Min Typ Max Min Typ Max e

L1 k ccc

E3 c

A2 b

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

0.2165

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

DocID023683 Rev 2

85/101

Package information STM32F050x4 STM32F050x6

Figure 33. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint

Dimensions are expressed in millimeters.

AID

86/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 34. LQFP48 marking example (package top view)

3URGXFW

LGHQWLILFDWLRQ

45.'

6WDQGDUG67ORJR

'DWHFRGH

: 88

5HYLVLRQFRGH

3LQLGHQWLILHU

069

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

Samples to run qualification activity.

DocID023683 Rev 2

87/101

Package information

7.2

STM32F050x4 STM32F050x6

UFQFPN32 package information

Figure 35. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline

GGG &

6($7,1*

3/$1(

(

( (

3,1,GHQWLILHU

Drawing is not to scale.

!"?-%?6

88/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Package information

Table 62. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E2 e

L ddd

A3 b

0.500

0.000

0.180

4.900

3.400

4.900

3.400

0.300

0.550

0.020

0.152

0.230

5.000

3.500

5.000

3.500

0.500

0.400

0.600

0.050

0.280

5.100

3.600

5.100

3.600

0.500

0.080

Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.0071

0.1929

0.1339

0.1929

0.1339

0.0118

0.0217

0.0008

0.0060

0.0091

0.1969

0.1378

0.1969

0.1378

0.0197

0.0157

0.0236

0.0020

0.0110

0.2008

0.1417

0.2008

0.1417

0.0197

0.0031

Figure 36. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint

Dimensions are expressed in millimeters.

DocID023683 Rev 2

$%B)3B9

89/101

Package information STM32F050x4 STM32F050x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 37. UFQFPN32 marking example (package top view)

3URGXFW

LGHQWLILFDWLRQ

6WDQGDUG67ORJR

'DWHFRGH

5HYLVLRQFRGH

'RWSLQ

069

Samples to run qualification activity.

90/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

7.3

Package information

UFQFPN28 package information

Figure 38. UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

'HWDLO<

(

'HWDLO=

!"?-%?6

Drawing is not to scale.

Table 63. UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data

(1) millimeters inches

Symbol

Min Typ Max Min Typ Max

T b e

0.500

3.900

2.900

3.900

2.900

0.300

0.250

0.200

0.550

0.000

4.000

3.000

4.000

3.000

0.400

0.350

0.152

0.250

0.500

0.600

0.050

4.100

3.100

4.100

3.100

0.500

0.450

0.300

0.0197

0.1535

0.1142

0.1535

0.1142

0.0118

0.0098

0.0079

0.0217

0.0000

0.1575

0.1181

0.1575

0.1181

0.0157

0.0138

0.0060

0.0098

0.0197

0.0236

0.0020

0.1614

0.1220

0.1614

0.1220

0.0197

0.0177

0.0118

DocID023683 Rev 2

91/101

Package information STM32F050x4 STM32F050x6

Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 39. UFQFPN28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint

Dimensions are expressed in millimeters.

!"?&0?6

92/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 40. UFQFPN28 marking example (package top view)

3URGXFW

LGHQWLILFDWLRQ

'RW

'DWHFRGH

: 88 3

5HYLVLRQFRGH

069

Samples to run qualification activity.

DocID023683 Rev 2

93/101

Package information

7.4

STM32F050x4 STM32F050x6

TSSOP20 package information

Figure 41.TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline

94/101

% %

3%!4).'

0,!.%

'!'%0,!.%

0).

)$%.4)&)#!4)/.

AAA #

9!?-%?6

Drawing is not to scale.

Table 64. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

A2 b e

0.050

0.800

0.190

0.090

6.400

6.200

4.300

0.450

1.000

6.500

6.400

4.400

0.650

0.600

1.000

1.200

0.150

1.050

0.300

0.200

6.600

4.500

0.750

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

0.0177

0.0394

0.2559

0.2520

0.1732

0.0256

0.0236

0.0394

0.0472

0.0059

0.0413

0.0118

0.0079

0.2598

0.1772

0.0295

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Package information

Table 64. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data (continued) millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

k aaa

0°

8°

0.100

0°

Values in inches are converted from mm and rounded to four decimal digits.

8°

0.0039

Figure 42. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint

9!?&0?6

Dimensions are expressed in millimeters.

DocID023683 Rev 2

95/101

Package information STM32F050x4 STM32F050x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 43. TSSOP20 marking example (package top view)

6WDQGDUG67ORJR

3URGXFW

LGHQWLILFDWLRQ

3LQLGHQWLILHU

''1

'DWHFRGH

: 88 3

5HYLVLRQFRGH

069

Samples to run qualification activity.

96/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Package information

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 15: General operating conditions on page 39 .

The maximum chip-junction temperature, T

max, in degrees Celsius, may be calculated using the following equation:

max = T

max + (P

max x Θ

)

Where:

•

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

•

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max =

× I

) +

((V

– V

) × I

), taking into account the actual V

/ I

and V

/ I application.

OH of the I/Os at low and high level in the

Table 65. Package thermal characteristics

Symbol Parameter

Thermal resistance junction-ambient

LQFP48 - 7 × 7 mm

Thermal resistance junction-ambient

UFQFPN32 - 5 × 5 mm

Thermal resistance junction-ambient

UFQFPN28 - 4 × 4 mm

Thermal resistance junction-ambient

TSSOP20

Value

118

110

Unit

°C/W

7.5.2

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Part numbering .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F05xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

DocID023683 Rev 2

97/101

Package information

Note:

STM32F050x4 STM32F050x6

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

= 80 °C (measured according to JESD51-2),

DDmax

= 50 mA, V

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 8 I/Os used at the same time in output at low level with I

= 20 mA, V

= 1.3 V

INTmax

= 50 mA × 3.5 V= 175 mW

IOmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW:

Dmax

= 175 + 272 = 447 mW

Using the values obtained in Table 65

Jmax

is calculated as follows:

– For LQFP48, 55 °C/W

Jmax

= 80 °C + (55°C/W × 447 mW) = 80 °C + 24.585 °C = 104.585 °C

This is within the range of the suffix 6 version parts (–40 < T

General operating conditions on page 39 .

< 105 °C) see Table 15:

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Section 8: Part numbering

With this given P

Dmax

we can find the T

(order code suffix 6 or 7).

Amax

allowed for a given device temperature range

Suffix 6: T

Amax

= T

Jmax

- (55°C/W × 447 mW) = 105-24.585 = 80.415 °C

Suffix 7: T

Amax

= T

Jmax

- (55°C/W × 447 mW) = 125-24.585 = 100.415 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T

remains within the specified range.

Assuming the following application conditions:

Maximum ambient temperature T

Amax

= 100 °C (measured according to JESD51-2),

DDmax

= 20 mA, V

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V

INTmax

= 20 mA × 3.5 V= 70 mW

IOmax

= 20 × 8 mA × 0.4 V = 64 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 64 mW:

Dmax

= 70 + 64 = 134 mW

Thus: P

Dmax

= 134 mW

Using the values obtained in Table 65

Jmax

is calculated as follows:

– For LQFP48, 55 °C/W

Jmax

= 100 °C + (55 °C/W × 134 mW) = 100 °C + 7.37 °C = 107.37 °C

This is above the range of the suffix 6 version parts (–40 < T

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Section 8: Part numbering

) unless we reduce the power dissipation in order to be able to use suffix 6 parts.

98/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6 Part numbering

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office.

Example :

Table 66. Ordering information scheme

STM32 F 050 C 6 T 6 A x

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = General-purpose

Sub-family

050 = STM32F050xx

Pin count

F = 20 pins

G = 28 pins

K = 32 pins

C = 48 pins

Code size

4 = 16 Kbyte of Flash memory

6 = 32 Kbyte of Flash memory

Package

P = TSSOP

U = UFQFPN

T = TQFP

Temperature range

6 = –40 to 85 °C

7 = –40 to 105 °C

Internal code

A = non-optimized die

Blank = standard die

Options xxx = programmed parts

TR = tape and reel

DocID023683 Rev 2

99/101

Revision history STM32F050x4 STM32F050x6

Date

22-Nov-2012

08-Apr-2015

Table 67. Document revision history

Revision Changes

Initial release

Added:

–

Figure 34: LQFP48 marking example (package top view) ,

–

Figure 37: UFQFPN32 marking example (package top view)

–

Figure 40: UFQFPN28 marking example (package top view)

–

Figure 43: TSSOP20 marking example (package top view)

Updated the disclaimer and document status.

100/101

DocID023683 Rev 2

STM32F050x4 STM32F050x6

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DocID023683 Rev 2 101/101

101

Hirdetés