STMicroelectronics M41T00S Datasheet
விளம்பரம்
விளம்பரம்
M41T00S
8
1
SO8, 8-pin SOIC
Features
•
2.0 to 5.5 V clock operating voltage
•
Counters for seconds, minutes, hours, day, date, month, year, and century
•
Software clock calibration
•
Automatic switchover and deselect circuitry
(fixed reference)
•
V
CC
= 2.7 to 5.5 V
2.5 V
≤
V
PFD
≤
2.7 V
•
Serial interface supports I²C bus (400 kHz protocol)
•
Low operating current of 300 mA
•
Oscillator stop detection
•
Battery or SuperCap
TM
backup
•
Operating temperature of - 40 to 85 °C
•
Ultra-low battery supply current of 0.6 mA
Serial real-time clock
Datasheet
-
production data
Description
The M41T00S is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz oscillator
(external crystal controlled). Eight bytes of the
SRAM are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two line, bidirectional I²C interface.
The built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T00S has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button supply when a power failure occurs.
The eight clock address locations contain the century, year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for
28, 29 (leap year - valid until year 2100), 30 and
31 day months are made automatically.
The M41T00S is supplied in an 8-pin SOIC.
October 2021
This is information on a product in full production.
DocID10772 Rev 6 1/28 www.st.com
28
Contents
Contents
M41T00S
Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M41T00S
List of figures
List of figures
DocID10772 Rev 6 3/28
List of tables
List of tables
M41T00S
Table 8.
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 23
Reel dimensions for 12 mm carrier tape - SO8 package (150 mils body width) . . . . . . . . . 25
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M41T00S
1 Diagram
XI
XO
FT/OUT
SDA
SCL
V
BAT
V
CC
V
SS
Figure 1. Logic diagram
VCC VBAT
XI
XO
SCL
SDA
M41T00S FT/OUT
VSS
AI09165
Table 1. Signal names
Oscillator input
Oscillator output
Frequency test / output driver (open drain)
Serial data input/output
Serial clock input
Battery supply voltage
Supply voltage
Ground
Figure 2. 8-pin SOIC connections
XI
XO
V
BAT
V
SS
1
2
3
4
M41T00S
8
7
6
5
V
CC
FT/OUT
(1)
SCL
SDA
AI09166
1. Open drain output
Diagram
DocID10772 Rev 6 5/28
Diagram
CRYSTAL
SDA
SCL
Figure 3. Block diagram
32KHz
OSCILLATOR
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL
CIRCUIT
RTC &
CALIBRATION
FREQUENCY TEST
FT
I
2
C
INTERFACE
OUTPUT DRIVER
OUT
WRITE
PROTECT
INTERNAL
POWER
V
CC
V
BAT
V
SO
V
PFD
COMPARE
1. Open drain output
M41T00S
FT/OUT
(1)
AI09168
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M41T00S
2 Operation
Operation
The M41T00S clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order:
1.
Seconds register
2. Minutes register
3. Century/hours register
4. Day register
5. Date register
6. Month register
7. Year register
8. Calibration register
The M41T00S clock continually monitors V
CC
for an out-of-tolerance condition. Should V
CC fall below V
PFD
, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. Once V
CC
falls below the switchover voltage (V
SO
), the device automatically switches over to the battery and powers down into an ultra-low current mode of operation to preserve battery life.
2.1
Upon power-up, the device switches from battery to V
CC
at V
SO
. When V
CC
rises above
V
PFD
, it will recognize the inputs.
For more information on battery storage life refer to application note AN1012.
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
•
Data transfer may be initiated only when the bus is not busy.
•
During data transfer, the data line must remain stable whenever the clock line is high.
•
Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
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Operation
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
M41T00S
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
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M41T00S Operation
Figure 4. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 5. Acknowledgement sequence
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
START
1
MSB
2 8
LSB
CLOCK PULSE FOR
ACKNOWLEDGEMENT
9
AI00601
2.2
Note:
READ mode
In this mode the master reads the M41T00S slave after setting the slave address (see
). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1).
At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge clock. The M41T00S slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). The update will resume due to a stop condition or when the pointer increments to any non-clock address (07h).
This is true both in READ mode and WRITE mode.
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Operation M41T00S
An alternate READ mode may also be implemented whereby the master reads the
M41T00S slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see
Figure 6. Slave address location
R/W
START SLAVE ADDRESS A
1 1 0 1 0 0 0
AI00602
Figure 7. READ mode sequence
BUS ACTIVITY:
MASTER
SDA LINE S
BUS ACTIVITY:
SLAVE
ADDRESS
WORD
ADDRESS (An)
S
SLAVE
ADDRESS
DATA n DATA n+1
DATA n+X P
AI00899
10/28
Figure 8. Alternative READ mode sequence
BUS ACTIVITY:
MASTER
SDA LINE S
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n DATA n+1 DATA n+X P
AI00895
DocID10772 Rev 6
M41T00S
2.3
Operation
WRITE mode
In this mode the master transmitter transmits to the M41T00S slave receiver. Bus protocol is
. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address “An” will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T00S slave receiver will send an acknowledge clock to the master transmitter after it has received the slave
address see Figure 6 on page 10 and again after it has received the word address and each
data byte.
2.4 Data retention mode
With valid V
CC
applied, the M41T00S can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the power input will be switched from the
V
CC
pin to the battery when V
CC
falls below the battery backup switchover voltage (V
SO
). At this time the clock registers will be maintained by the attached battery supply. On power-up, when V
CC
returns to a nominal value, write protection continues for t
REC
.
For a further, more detailed review of lifetime calculations, please see Application Note
AN1012.
Figure 9. WRITE mode sequence
BUS ACTIVITY:
MASTER
SDA LINE S
WORD
ADDRESS (An)
DATA n DATA n+1 DATA n+X P
BUS ACTIVITY:
SLAVE
ADDRESS AI00591
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Clock operation
3 Clock operation
M41T00S
The 8-byte register map (see Table 2 ) is used to both set the clock and to read the date and
time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers.
Bits D6 and D7 of clock register 02h (century/hours register) contain the CENTURY
ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 03h contain the Day (day of week). Registers 04h, 05h, and 06h contain the date (day of month), month and years. The eighth clock register is the calibration register (this is described in the clock calibration section). Bit D7 of register 00h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second.
The seven clock registers may be read one byte at a time, or in a sequential block. The calibration register (address location 07h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
3.1 Clock registers
The M41T00S offers 8 internal registers which contain clock and calibration data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT
™
TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). The update will resume either due to a stop condition or when the pointer increments to any non-clock address (07h).
Clock registers store data in BCD. The calibration register stores data in binary format.
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M41T00S Clock operation
Addr
00h
01h
02h
03h
04h
05h
06h
07h
D7
ST
OF
CEB
0
0
0
OUT
D6
CB
0
0
D5
10 seconds
10 minutes
D4
0
10 hours
0
10 date
10M 0
10 years
0
FT S
Keys:
0 = must be set to '0'
CB = century bit
CEB = century enable bit
FT = frequency test bit
OF = oscillator fail bit
OUT = output level
S = sign bit
ST = stop bit
Table 2. TIMEKEEPER
®
register map
D3
0
D2 D1
Seconds
Minutes
Hours (24-hour format)
Day of week
Date: day of month
D0
Month
Year
Calibration
Function/range BCD format
Seconds
Minutes
Month
Year
Calibration
00-59
00-59
Century/hours 0-1/00-23
Day 01-7
Date 01-31
01-12
00-99
3.2 Calibrating the clock
The M41T00S is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator frequency error at 25 o
C, which equates to about ±1.53 minutes per month (see
When the calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature. The M41T00S design employs periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 15
. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the calibration register 07h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary
'1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
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Clock operation
Note:
M41T00S
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register (see
).
Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T00S may require.
The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934, “TIMEKEEPER
®
calibration.” This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the FT/OUT pin. The pin will toggle at 512 Hz, when the Stop bit (ST, D7 of 00h) is '0,' and the Frequency Test bit (FT, D6 of 07h) is '1.'
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency.
The FT/OUT pin is an open drain output which requires a pull-up resistor to V
CC
for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
The Frequency test is not available in battery mode.
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M41T00S Clock operation
Figure 10. Crystal accuracy across temperature
3.2.1
3.2.2
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
–40 –30 –20 –10 0
∆ F = K x (T – T
F
K
T
O
O
)
2
= –0.036 ppm/
°
C
2
= 25
°
± 0.006 ppm/
°
C
2
C ± 5
°
C
10 20 30
Temperature
°
C
40 50 60 70 80
AI07888
Figure 11. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Century bit
Bits D7 and D6 of clock register 02h contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
Oscillator fail detection
If the Oscillator Fail bit (OF) is internally set to '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data.
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Clock operation
3.2.3
M41T00S
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the oscillator.
The following conditions can cause the OF bit to be set:
•
The first time power is applied (defaults to a '1' on power-up).
•
The voltage present on V
CC
is insufficient to support oscillation.
•
The ST bit is set to '1.'
•
External interference of the crystal.
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF Bit to '0.'
Output driver pin
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the calibration register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location 07h are a '0,' then the FT/OUT pin will be driven low.
Power mode
VCC Mode
Battery Mode
Table 3. FT/OUT pin status
(FT) D6 of 07h (OUT bit) D7 of 07h
0
0
1
N.A.
0
1
1 or 0
N.A.
Status
Low
High
Frequency Test
High
Note:
3.2.4
The FT/OUT pin is an open drain which requires an external pull-up resistor.
Preferred initial power-on default
Upon initial application of power to the device, the ST and FT bits are set to a '0' state, and the OF and OUT bits will be set to a '1.' All other register bits will initially power-on in a random state (see
).
Table 4. Preferred default values
Condition
Initial power-up
(1)
Subsequent power-up (with battery backup)
(2)
1. State of other control bits undefined.
2. UC = Unchanged
ST
0
UC
Out
1
UC
FT
0
0
OF
1
UC
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M41T00S
4 Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Sym
Table 5. Absolute maximum ratings
Parameter Value
T
STG
V
CC
T
SLD
(1)
V
IO
I
O
P
D
Storage temperature (V
CC
Supply voltage
Input or output voltages
Output current
Power dissipation
off, oscillator off)
Lead solder temperature for 10 seconds
–55 to 125
–0.3 to 7
260
–0.3 to V
CC
+0.3
20
1
1. Reflow at peak temperature of 260 °C (total thermal budget not to exceed 245 °C for greater than 30 seconds).
Unit
°C
V
°C
V mA
W
Caution: Negative undershoots below -0.3 volts are not allowed on any pin while in the battery backup mode
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DC and AC parameters
5 DC and AC parameters
Note:
M41T00S
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC measurement conditions
Parameter M41T00S
Supply voltage (V
CC
)
Ambient operating temperature (T
A
)
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
2.7 to 5.5 V
–40 to 85 °C
100 pF
≤
50 ns
0.2V
CC
to 0.8V
CC
0.3V
CC
to 0.7V
CC
Output Hi-Z is defined as the point where data is no longer driven.
Figure 12. AC measurement I/O waveform
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI02568
Symbol
Table 7. Capacitance
Parameter
(1)(2)
Min Max Unit
C
IN
C
OUT
(3) t
LP
Input capacitance
Output capacitance
Low-pass filter input time constant (SDA and SCL) -
-
-
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz
3. Outputs deselected.
7
10
50 pF pF ns
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M41T00S DC and AC parameters
Sym Parameter
Table 8. DC characteristics
Test condition
(1)
Min Typ Max
I
LI
I
LO
I
CC1
Input leakage current
Output leakage current
Supply current
0 V ≤ V
IN
0 V
≤
V
OUT
≤ V
CC
≤
V
CC
Switch freq = 400 kHz
±1
±1
300
I
CC2
Supply current (standby)
SCL = 0 Hz
All Inputs
≥
V
CC
– 0.2 V
≤ V
SS
+ 0.2 V
70
V
V
IL
IH
Input low voltage
Input high voltage
–0.3
0.7V
CC
V
OL
Output low voltage
Output low voltage (open drain)
(2)
I
OL
= 3.0 mA
I
OL
= 10 mA
FT/OUT Pull-up supply voltage (open drain)
V
BAT
(3)
Backup supply voltage 2.0
I
BAT
Battery supply current
T
A
= 25 °C, V
CC
= 0 V
Oscillator ON, V
BAT
= 3 V
0.6
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 2.7 to 5.5 V (except where noted).
2. For FT/OUT pin (open drain).
3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
4. For rechargeable backup, V
BAT
(max) may be considered to be V
CC
.
0.3V
CC
V
CC
+ 0.3
0.4
0.4
5.5
3.5
1
(4)
Unit
µ A
µ
A
µ A
µ
A
µA
V
V
V
V
V
V
Table 9. Crystal electrical characteristics
Sym fO
Parameter
(1)(2)
Resonant frequency
Series resistance
Min Typ
32.768
Max
60
(3)
RS
C
L
Load capacitance 12.5
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning
Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
Unit kHz k Ω pF
2. Load capacitors are integrated within the M41T00S. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. For applications requiring backup supply operation below 2.5 V, R
S
(max) should be considered 40 k
Ω
.
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DC and AC parameters
VCC
VSO
SDA
SCL tPD
Figure 13. Power down/up mode AC waveforms
DON'T CARE trec
AI00596
M41T00S
Table 10. Power down/up AC characteristics
Symbol t t
PD rec
Parameter
(1)(2)
SCL and SDA at V
IH
before power-down
SCL and SDA at V
IH
after power-up
Min
0
10
Typ
1. V
CC
fall time should not exceed 5 mV/µs.
2. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 2.7 to 5.5 V (except where noted).
Max Unit nS
µS
Sym
Table 11. Power down/up trip points DC characteristics
Parameter
(1)(2)
Min Typ
V
V
PFD
SO
Power-fail deselect
Hysteresis
Battery backup switchover voltage
(V
CC
< V
BAT
; V
CC
< V
PFD
)
Hysteresis
V
V
BAT
BAT
< V
> V
PFD
PFD
2.5
V
V
2.6
25
BAT
PFD
40
1. All voltages referenced to V
SS
.
2. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 2.7 to 5.5 V (except where noted).
Figure 14. Bus timing requirements sequence
Max
2.7
Unit
V mV
V
V mV
SDA tBUF tHD:STA
SCL
P S tHD:STA tR tF tHIGH tLOW tSU:DAT tHD:DAT SR tSU:STA
P tSU:STO
AI00589
20/28 DocID10772 Rev 6
M41T00S DC and AC parameters
Sym
Table 12. AC characteristics
Parameter
(1)
Min Typ Max Units fSCL tLOW tHIGH tR tF tHD:STA
SCL clock frequency
Clock low period
Clock high period
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
(after this period the first clock pulse is generated)
0
1.3
600
600
400
300
300 ns tSU:STA
START condition setup time
(only relevant for a repeated start condition) tSU:DAT
(2) tHD:DAT
Data setup time
Data hold time tSU:STO tBUF
STOP condition setup time
Time the bus must be free before a new
transmission can start
600
100
0
600
1.3
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 2.7 to 5.5 V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
ns ns
µs ns
µs kHz
µs ns ns ns
DocID10772 Rev 6 21/28
Package mechanical information
6 Package mechanical information
M41T00S
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
22/28 DocID10772 Rev 6
M41T00S Package mechanical information
A2 b e
Figure 15. SO8 – 8-lead plastic small package outline h x 45 ˚
A c ccc
D
0.25 mm
GAUGE PLANE k
8
E1 E
1 A1
L1
L
SO-A
Note: Drawing is not to scale.
Table 13. SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data mm inches
Symb
Typ Min Max Typ Min Max k
N ccc h
L
L1
B
C
D
A
A1
A2
E
E1 e
4.90
6.00
3.90
1.27
1.04
0.10
1.25
0.28
0.17
4.80
5.80
3.80
0.25
0.40
0°
8
1.75
0.25
0.48
0.23
5.00
6.20
4.00
0.50
1.27
8°
0.10
0.050
0.041
0.004
0.049
0.011
0.007
0.189
0.228
0.150
0.010
0.016
0°
8
0.069
0.010
0.019
0.009
0.197
0.244
0.157
0.020
0.050
8°
0.004
DocID10772 Rev 6 23/28
Package mechanical information
Figure 16. Carrier tape for SO8 (150 mils body width) package
D P
2
P
0
E
T
A
0
F
TOP COVER
TAPE
B
0
W
M41T00S
K
0
CENTER LINES
OF CAVITY
P
1
USER DIRECTION OF FEED
AM03073v1
Package
SO8
Table 14. Carrier tape dimensions for SO8 (150 mils body width) package
W D E P
0
P
2
F A
0
B
0
K
0
P
1
T Unit
Bulk
Qty
12.00
± 0.30
1.50
+0.10/
–0.00
1.75
± 0.10
4.00
± 0.10
2.00
± 0.10
5.50
± 0.05
6.50
± 0.10
5.30
± 0.10
2.20
± 0.10
8.00
± 0.10
0.30
± 0.05
mm 2500
24/28 DocID10772 Rev 6
M41T00S Package mechanical information
Figure 17. Reel schematic
T
40mm min.
Access hole
At slot location
B
D
C
A
Full radius
Tape slot
In core for
Tape start
2.5mm min.width
N
G measured
At hub
AM04928v1
Table 15. Reel dimensions for 12 mm carrier tape - SO8 package (150 mils body width)
A
(max)
B
(min)
C
D
(min)
N
(min)
G
T
(max)
330 mm
(13-inch)
1.5 mm
13 mm
±
0.2 mm
20.2 mm 60 mm
12.4 mm
+ 2/–0 mm
18.4 mm
Note: The dimensions given in
incorporate tolerances that cover all variations on critical parameters.
DocID10772 Rev 6 25/28
Part numbering
7 Part numbering
M41T00S
Example:
Device type
M41T
Table 16. Ordering information scheme
Supply voltage and write protect voltage
00S = V
CC
= 2.7 to 5.5 V
Package
M = SO8
Temperature range
6 = –40 °C to 85 °C
M41T 00S M 6 F
Shipping method
E = ECOPACK
®
package, tubes
(1)
F = ECOPACK
®
package, tape & reel
1.
Not recommended for new design. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
26/28 DocID10772 Rev 6
M41T00S
8 Revision history
Revision history
Date
10-Feb- 2004
20-Feb-2004
14-Apr-2004
05-May-2004
16-Jun-2004
13-Sep-2004
26-Nov-2004
14-May-2008
17-Oct-2011
06-Oct-2021
Revision
Table 17. Document revision history
Changes
0.1
0.2
1.0
1.1
1.2
2.0
3.0
4
5
6
First draft
Update characteristics (Table 9, 10, 5, 7, 15)
Product promoted; reformatted; update characteristics, including
Lead-free package information (Figure 4, 10; Table 4, 11, 15)
Update DC characteristics (Table 7)
Added package shipping (Table 15)
Update maximum ratings (Table 4)
Promote document; update characteristics; remove references to
SOX18 package (cover page, Figure 4; Table 16)
Reformatted document; updated Section 6, Figure 1, 15, Table 1, 4,
12, 15
Updated title, Features, ECOPACK® text in Section 6: Package mechanical information; added Figure 16, 17, Table 13, 14; added footnote 1 to Table 15: Ordering information scheme; minor textual updates
Updated
Added note in
and new
DocID10772 Rev 6 27/28
M41T00S
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
28/28 DocID10772 Rev 6
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