UM2754
User manual
EVALSTGAP2S: isolated 4 A single gate driver demonstration board
Introduction
The EVALSTGAP2S board allows evaluating all the STGAP2S features while driving a half-bridge power stage with voltage rating up to 1700 V in TO-220 or TO-247 package.
The board allows to easily select and modify the values of relevant external components in order to facilitate driver’s performance evaluation under different applicative conditions and fine pre-tuning of the final application’s components.
Figure 1. EVALSTGAP2S demonstration board
UM2754 - Rev 1 - November 2020
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1
UM2754
Board description and configuration
Board description and configuration
The board allows tuning several design parameters, giving the possibility to evaluate and optimize the performance and switching characteristics of the power stage.
The user can select and mount the power switch of choice either in TO-220 or TO-247 package; the board also allows installing an optional heatsink.
The demonstration board can be populated with isolated DC-DC converters in the standard SIP7 package to supply the gate driving section, which significantly reduce the effort to supply the system and allow fast and easy evaluation of the gate driving performances.
The board is compatible with the whole STGAP2S family in SO-8 package, so it is possible to evaluate the part number of interest just by replacing the gate driver.
Figure 2
shows the position of the main components and connectors on the board.
Figure 2. Main components and connectors position
JP1, JP17
HS gate voltage conf guration
CN5
OUT terminal
CN6
HV terminal
CN3
GNDPWR terminal
U6 isolated DCDC converter for HS
J2
VH HS power supply connector
U2
LS
HS
STGAP2S
C2
HV bus capacitor
J10
Input signals and logic supply screw connector
JP5, JP6, JP7
Input signals conf guration
JP22, R17, D2
VDD logic supply conf guration
J9
Input signals and logic supply stripconnector
JP8, JP9
HS gate resistor conf guration
D3
Bootstrap diode
JP10, JP11
LS gate resistor conf guration
U1
LS
STGAP2S
U5 isolated DCDC converter for LS
J1
VH LS power supply connector
JP12, JP18
LS gate voltage conf guration
UM2754 - Rev 1 page 2/12
Name
J1
J2
J9
J10
CN3
CN5
CN6
UM2754
Board description and configuration
1
1
1
5
6
7
Pin
1 - 2
1 - 2
1
2
3
4
Table 1. Board connectors
Label
DCDCL
DCDCH
IN+_H
IN-_H
IN+_L
IN-_L
GND
VDD
AUX
GNDPWR
OUT
HV
Description
Low-side VH supply voltage
High-side VH supply voltage
High-side driver logic input, active high
High-side driver logic input, active low
Low-side driver logic input, active high
Low-side driver logic input, active low
Logic ground
Logic supply voltage
Auxiliary power supply
Power ground
Power stage output
High voltage power supply
UM2754 - Rev 1 page 3/12
UM2754 - Rev 1
UM2754
Board description and configuration
Table 2. Board jumpers setting
Jumper Permitted configurations
JP1
HS gate voltage configuration: selection of negative
voltage (refer to Table 5
)
JP5
JP6
JP7
Input signals configuration: IN-_L connected to IN+_H
Input signals configuration: IN+_L connected to IN-_H
Input signals configuration: IN-_L connected to IN-_H
JP8
HS gate resistor configuration: connection of CLAMP pin to power gate
JP9
JP10
JP11
HS gate resistor configuration: connection of GOFF pin to turn-off gate path
LS gate resistor configuration: connection of CLAMP pin to power gate
Default condition
Closed
Closed
Closed
Open
Open in EVALSTGAP2SM
Closed in EVALSTGAP2SCM
Closed in EVALSTGAP2SM
Open in EVALSTGAP2SCM
Open in EVALSTGAP2SM
Closed in EVALSTGAP2SCM
Closed in EVALSTGAP2SM
Open in EVALSTGAP2SCM
JP12
JP13
JP14
JP15
JP16
JP17
JP18
JP20
JP21
JP22
LS gate resistor configuration: connection of GOFF pin to turn-off gate path
LS gate voltage configuration: selection of negative
voltage (refer to Table 5
)
LS gate voltage configuration: direct connection of
DCDCL+ to VH_L net
HS gate voltage configuration: connection of DCDCH
0V output reference to OUT net
HS gate voltage configuration: connection of DCDCHto GNDISO_H net
HS gate voltage configuration: direct connection of
DCDCH+ to VH_H net
HS gate voltage configuration: selection of positive
voltage (refer to Table 5
)
LS gate voltage configuration: selection of positive
voltage (refer to Table 5
)
LS gate voltage configuration: connection of DCDCLto GNDISO_L net
LS gate voltage configuration: connection of DCDCL
0V output reference to GNDPWR net
VDD logic supply configuration (refer to Table 3 )
Closed
Open
Open
Closed
Open
Closed
Closed
Closed
Open
Closed 2-3 page 4/12
1.1
UM2754
Logic supply voltage (VDD)
Logic supply voltage (VDD)
•
•
It is possible to provide the gate driver control logic supply VDD in three alternative ways to match driver input threshold with the controlling signals voltage swing:
• Using the onboard 3.3 V Zener D2 regulator to supply VDD. The Zener is supplied from DC-DC input voltage VAUX. So only the 5 V VAUX DC-DC supply input is powered to supply the whole system (default configuration).
Supplying externally VDD net from J9 or J10 (pin 6) with a voltage between 3 V and 5.5 V.
Supplying externally VDD and VAUX together (VDD max. 5.5 V).
In case the default option is not used, it is required to modify JP22 according to
Table 3
and R17 according to
Table 4
also to avoid regulator components damage.
VDD
3.3 V, onboard (default)
3.3 V, external
VDD = VAUX, external
Table 3. Logic supply voltage selection (VDD)
JP22 Note
2-3 closed VDD generated from VAUX with Zener diode D2
Open VDD directly supplied from J9 or J10 (pin 6)
1-2 closed VDD and VAUX (DC-DC supply) tied together by JP22
The R17 resistor value has been selected for using 5 V input DC-DC module. If a different VAUX input voltage is used, follow
Table 4
to modify resistor R17 (which biases Zener D2) to avoid resistor overheating.
Table 4. R17 value selection with a 3.3 V Zener diode D2 regulator
DCDC module supply input voltage VAUX
3.3 V
5 V (default)
12 V
15 V
24 V
R17
Do not care
240 Ω
1200 Ω
1500 Ω
2700 Ω
JP22
1-2 closed
2-3 closed or JP22 open
2-3 closed or JP22 open
2-3 closed or JP22 open
2-3 closed or JP22 open
UM2754 - Rev 1 page 5/12
1.2
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Gate driver supply voltage (VH)
Gate driver supply voltage (VH)
It is possible to provide the gate driver supply voltage VH in several alternative ways:
• Using isolated DC-DC converters in the standard SIP7 package (U5, U6).
•
•
Using the bootstrap diode D3 by supplying the low-side driver via J1 and mounting the resistor R3 (initial suggested value 10 Ω).
Supplying directly J1 and J2 connectors (not mounted) with two separated isolated supplies.
The faster, easier and safer way to supply the board is by using isolated DC-DC converters.
The bootstrap diode supplying method is much simpler and less expensive but does not allow evaluating negative gate driving voltage. The bootstrap diode is 1200 V rated; if a higher bus voltage is required the diode must be replaced accordingly.
Supplying externally via J1 and J2 is generally not recommended, unless using supplies specifically designed for this purpose (with high voltage isolation) or batteries.
Supplies provided from the optional DC-DC or from J1 and J2 connectors are post regulated in order to allow an easy modification of the gate driving voltages. Some predefined supply voltages can be selected through solder jumpers; further tuning can be made by changing the value of the relevant Zener diodes.
Table 5. Gate driving voltage configuration (positive/negative)
Gate driving voltage
+15 V / 0 V (default)
+15 V / -2.7 V
+19 V / 0 V
+19 V / -2.7 V
JP1, JP12
Closed
Open
Closed
Open
JP17, JP18
Closed
Closed
Open
Open
Most suited for:
MOSFET/ IGBT
MOSFET/ IGBT
SiC
SiC
The board has been designed for indifferently using 5 V input and 24 V single output or “12 + 12 V” dual output
DC-DCs.
Other output voltage DC-DCs can be used by modifying the post regulation network.
Other input voltage DC-DCs can be used by modifying R17 (see Section:
Logic supply voltage (VDD)
).
DC-DCs input voltage is connected to VAUX signal, available on J9 and J10.
DC-DCs with SIP7 footprint are available mostly with 1 W and 2 W output rated power. For most applications, 1 W power modules are enough.
Especially for high dV/dt applications, low input to output isolation capacitance (referred to as input to output coupling capacitance) regulators are recommended.
During applicative output transients (dV/dt), the possible noise generated by the isolation capacitance could make user measurements difficult and noisy. To simplify user measurements task, DC-DC input supply is filtered with
FB1 FB2, FB3 and FB4 ferrite beads. In the final application, beads are usually removed for cost reasons. On the other hand, if the user wants to further improve the filter, we suggest replacing the beads with a common mode filter (T1 and T2), like for instance TDK ACM4520-142.
UM2754 - Rev 1 page 6/12
1.3
1.4
1.5
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Drivers logic input signals
Drivers logic input signals
Drivers logic input signals can be applied through the dedicated pins of J9 or J10 connector (refer to Table 1 for
details).
It is possible to reduce the required driving signals exploiting the onboard jumpers according to
Table 6
.
Input configuration
IN+_H = IN-_L
IN+_L = IN-_H
IN-_L = IN-_H
Table 6. Input signals settings
Description
The same input signal is applied to IN+ of high-side driver U2 and IN- of low-side driver U1
The same input signal is applied to IN- of high-side driver U2 and IN+ of low-side driver U1
The same input signal is applied to IN- of high-side driver U2 and IN- of low-side driver U1
Jumper
JP5
JP6
JP7
Default condition
Closed
Closed
Open
Drivers gate resistors
The gate resistors are selected based on the selected power switch and application topology.
It is possible to evaluate different gate drivers of the STGAP2S family by setting few jumpers according to Table 7 .
Table 7. Gate driver resistors and jumper settings
STGAP2SCM
1. •
2. •
Gate driver
STGAP2SM (1)
(2)
Feature
Separated outputs
Miller Clamp
JP8, JP10
Open
Closed
JP9, JP11
Closed
Open
Turn-on resistor
R5, R1
R5, R1
Turn-off resistor
R4, R2
R5 // R4
R1 // R2
The presence of D4 and D5 does not influence turn-off speed and these diodes are not required in the final application. D4 and D5 are mounted on board to speed-up evaluation of STGAP2SC (Miller Clamp version).
R4, D4, R2 and D5 are only required if differentiated turn-on and turn-off speed are required by the user.
Power stage decoupling
As for all switching applications, high voltage supply is properly decoupled and appropriate decoupling capacitor is connected to the board to reduce bus ringing and power switch overvoltage spikes during operation.
The board is equipped with a small 1.25 kV DC rated film capacitor (C2) in a convenient position to operate more safely the power switches. Depending on the application, bus decoupling can be modified also by using the provided footprint and holes for the bus capacitors C1, C2, C34, C35, C36.
IMPORTANT NOTE: DANGER OF DEATH!
High voltage present on the board! Before operating on the board, ensure that all capacitors are discharged.
UM2754 - Rev 1 page 7/12
Revision history
Date
29-Oct-2020
Version
1
Table 8. Document revision history
Changes
Initial release.
UM2754
UM2754 - Rev 1 page 8/12
UM2754
Contents
Contents
1 Board description and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.1
Logic supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
Gate driver supply voltage (VH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3
Drivers logic input signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4
Drivers gate resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5
Power stage decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
UM2754 - Rev 1 page 9/12
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List of tables
List of tables
Table 1. Board connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Board jumpers setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Logic supply voltage selection (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. R17 value selection with a 3.3 V Zener diode D2 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Gate driving voltage configuration (positive/negative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. Input signals settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. Gate driver resistors and jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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List of figures
List of figures
Figure 1. EVALSTGAP2S demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Main components and connectors position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
UM2754 - Rev 1 page 11/12
UM2754
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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UM2754 - Rev 1 page 12/12
