STMicroelectronics PM8908 Datasheet
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PM8908
Monolithic buck converter for DDR memory termination
QFN20 3.5 x 4.0 mm
Datasheet
-
production data
Applications
•
Memory termination regulator for DDR3, DDR4 and low power DDR3/DDR4
•
Notebook/desktop/server
•
Low voltage application for 1 V to 3.5 V input rails
Features
•
Integrated MOSFETs for high efficiency
•
Current COT architecture
•
1 V to 3.5 V input voltage (V
IN
)
•
5.0 V supply voltage (V
CC
)
•
Constant frequency mode
•
1% output voltage accuracy
•
Two programmable switching frequencies (0.6
MHz or 1 MHz)
•
ADJ output voltage from 0.5 V to 2 V
•
Embedded bootstrap diode
•
OV/UV/OC and overtemperature protection
•
Soft-off with integrated discharge resistor
•
External tracking
•
Power Good output
•
QFN20 3.5 x 4.0 mm compact package
Order code
PM8908TR
Description
The PM8908 is a high efficiency monolithic stepdown switching regulator designed mainly for the
DDR termination.
The IC operates from 1 V to 3.5 V input voltage
(V
IN
).
The device uses a COT control loop that provides very good performances in terms of load and line transients. The current sense is internally thermally compensated for optimum precision.
The output voltage is adjusted from 0.5 V to 2 V with ± 1% accuracy overtemperature variations.
The PM8908 also provides external tracking support.
The PM8908 provides positive and negative overcurrent protection as well as over/undervoltage and overtemperature protection. PGOOD output easily provides realtime information on the output voltage.
The PM8908 is available in a QFN20 3.5 x 4.0 mm package.
Table 1. Device summary
Package
QFN20 (3.5 x 4.0 mm)
Packaging
Tape and reel
July 2017
This is information on a product in full production.
DocID027688 Rev 4 1/28 www.st.com
Contents
Contents
PM8908
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Startup and shutdown management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . 16
Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Good (PGOOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/28 DocID027688 Rev 4
PM8908
Contents
QFN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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28
Typical application circuit and block diagram
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
R
M
VCC = 5 V
R
PGOOD
C
VCC
R
2
R
1
C
REF
20
VCC VIN
4, 5
VIN = 1 V to 3.5 V
6 1, 2, 3
GND PGND
19
17
PGOOD
EN
18
PM8908
9
MODE
REFIN
7
REF
BOOT
16
C
PHASE
11, 12, 13,
14, 15
COMP
8
VOUT
10
BOOT
L
C
VIN
VOUT
C
OUT
C
P
C
F
R
F
PM8908
Figure 2. Typical memory termination application circuit
R
M
VCC = 5 V
R
PGOOD
C
VCC
R
VDDQ
1
20
VCC VIN
4, 5
VDDQ = 1.2 V
6
GND PGND
1, 2, 3
19
17
18
9
PGOOD
EN
MODE
REFIN
PM8908
7
REF
C
P
BOOT
16
C
PHASE
11, 12, 13,
14, 15
COMP
VOUT
8
10
BOOT
L
C
VIN
VOUT = 0.6 V
C
OUT
R
1
=R
2
R
2
C
REF
C
F
R
F
4/28 DocID027688 Rev 4
PM8908 Typical application circuit and block diagram
1.2 Block diagram
Figure 3. Block diagram
PGOOD MODE VCC
REFIN
VOUT
COMP
REF
EN
REFIN -16%
VOUT
Hy
PM8908
REFIN +16%
REFIN -30%
Hy
UV
VOUT
REFIN +20%
OV
SS
Voltage
Reference
K
Delay
THERMAL
MONITOR
PHASE
VCC UVLO
COT CONTROL
LOGIC,
PROTECTIONS
&
ADAPTIVE
DEAD TIMES
DEAD TIMES
VCC
GND
PGND
Discharge
CL
Current
Limit
VIN
BOOT
PHASE
PGND
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Pin description and connection diagrams
2 Pin description and connection diagrams
Figure 4. Pin connection (top view)
20 19 18 17 16
PGND
PGND
PGND 3
1
2
VIN
VIN
4
5
PM8908
15 PHASE
14
PHASE
13
PHASE
12 PHASE
11
PHASE
6 7 8 9 10
PM8908
Pin description
No.
3
4
1
2
5
Pin
Name
PGND
VIN
6 GND
7
8
9
10
Table 2. Pin description
Function
Power ground connection, connected to the embedded low-side MOSFET source. Connect to the PGND PCB plane. See
REF
COMP
REFIN
VOUT
Power input voltage, connected to the embedded high-side MOS drain.
Supply range is from 1 V to 3.5 V. Bypass VIN pins to PGND pins close to the
IC package with high quality MLCC capacitors. See
All the internal references are referred to this pin. Connect to the PCB signal ground.
Reference output.
Connect a 1
µ
F MLCC capacitor to GND. See Figure 1 .
Error amplifier output.
Connect with R
F
- C
F
to the REF pin for loop compensation. See
.
Reference input.
Apply a voltage between 0.5 to 2.0 V. Filter with at least 0.01
µ
F MLCC capacitors to GND.
Output voltage sense.
6/28 DocID027688 Rev 4
PM8908 Pin description and connection diagrams
Table 2. Pin description (continued)
Pin
Name
Function
No.
11
12
13
14
15
PHASE
Output inductor connection.
The pins are connected to the embedded MOSFETs (high-side source and
low-side drain). Connect directly to the output inductor. See Figure 1 .
16
17
18
19
20
BOOT
Bootstrap pin.
It provides power supply for the floating high-side MOS driver.
Connect with 0.1 µF to PHASE. See
EN
MODE
PGOOD
Enable.
Switching frequency and the OCL programming pin. See
.
This pin must not be left floating.
Power Good pin.
Open drain output set free after SS has finished and pulled low when V
OUT
is out of the PGOOD window or any protection is triggered.
Pull up to VCC, if not used it can be left floating.
VCC
Device power supply.
Operative voltage is 5.0 V. Filter with at least 1 µF MLCC vs. GND.
Thermal pad
The thermal pad of the device. Connect to the PCB ground plane with multiple
VIAS.
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Thermal data
3 Thermal data
Symbol
R thJA
T
MAX
T
STG
T
J
Table 3. Thermal data
Parameter
Thermal resistance junction to ambient
(Device soldered on demonstration board)
Maximum junction temperature
Storage temperature range
Junction temperature range
PM8908
Value
40
150
-55 to 150
-40 to 150
Unit
°C/W
°C
°C
°C
8/28 DocID027688 Rev 4
PM8908
4 Electrical specifications
4.1
Note:
Electrical specifications
Absolute maximum ratings
Symbol
Table 4. Absolute maximum ratings
Parameter Value
(1)
Unit
VCC
VIN
BOOT
PHASE
To PGND, GND
To PGND, GND
To PGND, GND
To PGND, GND, t < 10 ns
To PHASE
To PGND, GND
To PGND, GND, t < 10 ns
-0.3 to 7
-0.3 to 4
-0.3 to 11
-0.3 to 12.2
(2)
-0.3 to 7
-2 to 4
-2.2 to 7.5
(2)
PGOOD
EN
VOUT
To PGND, GND
To PGND, GND
To PGND, GND
-0.3 to 7
-0.3 to 7
-1.0 to 3.6
REFIN
,
COMP
,
REF, MODE To GND -0.3 to 3.6
V
1.
All voltages need to be lower than V
CC
under any condition.
2.
Regardless of application configuration, it is mandatory not to exceed the AMR voltage value on the BOOT and PHASE pins.
V
V
V
V
V
V
V
V
V
V
Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal.
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Electrical specifications PM8908
4.2 Electrical characteristics
V
CC
= 5.0 V ± 5%, T
A
= 70°C (unless otherwise specified).
Parameter
Table 5. Electrical characteristics
Test conditions Symbol Min. Typ.
Max.
Unit
Supply current and undervoltage lockout
I
IN
VIN shutdown current
I
I
I
CC
CCSD
BSS
V
V
CC
CC
supply current
shutdown current
Boot input current
Shutdown, EN = 0 V
EN = H, V
BOOT
= 4.5 V, V
CC
= 4.5 V,
V
IN
= 3.5 V, V
M
= GND
Shutdown, EN = 0 V
V
BOOT
= 9 V, V
PHASE
= 3.5 V,
V
CC
= 5.5 V
V
CC
V
CC
UVLO
V
CC
supply voltage
V
CC
turn-on
Hysteresis
V
REF
turn-on
REF UVLO
Hysteresis
V
CC
rising
REF rising
0.3
2
4
5
3.6
10
150
4.5
5.0
5.5
4.2
4.37
4.5
440
1.8
100
µ mA
µ
µ
A
A
A
Oscillator, off-time and on-time t f
SW
OFF-min
Oscillator accuracy
Minimum off-time
R
M
= 100 k
Ω
R
M
= 47 k Ω
V
IN
= 1.5 V, V
OUT
= 0.9 V, V
REFIN
= 1 V, f
SW
= 1 MHz / 0.6 MHz
Reference and GM amplifier
∆ V
OUT
V
REF
G
M
Output voltage accuracy
Voltage reference
Transconductance
(1)
I
I
CSK
CSR
COMP pin maximum sinking current
COMP pin maximum sourcing current
V
REFIN
= 1 V, no droop
I
REF
= 0
V
COMP
= 2 V, V
REFIN
- V
OUT
= -80 mV
V
COMP
= 2 V, V
REFIN
- V
OUT
= 80 mV
1
0.6
170
-1 +1
1.95
2.0
2.05
1.00
80
-80
V
V
V
F
A
CM
DM
OSet
-3dB
CS
MHz ns
%
V mS
µ
µ
A
A
Common mode input voltage range
(1)
Differential mode input voltage range
(1)
Input offset
-3 dB frequency
(1)
Current sense gain
0
0
2
80
V mV
0 mV
4.5
6.0
7.5
MHz
Gain from the current of the LS to PWM comp when PWM = OFF
47.3
59.3
mV/A
V
V mV
V mV
10/28 DocID027688 Rev 4
PM8908 Electrical specifications
Symbol
Table 5. Electrical characteristics (continued)
Parameter Test conditions
Soft-end
R
DS
Phase discharge resistance
Overcurrent protection
I
OCL
I
OCLN
Positive overcurrent threshold
Bootstrap switch
LS sourcing, R
Negative overcurrent threshold LS sourcing, R
M
M
= 47 k
Ω
= 47 k
Ω
R
BSS
Boot switch on-resistance
Over and undervoltage protection
I
BOOT
= 10 mA, T
A
= 25 °C
OVP t
OVPd
UVP t
UVPd
OVP threshold
OVP delay
UVP threshold
UVP delay
Undervoltage fault enable delay
Min. Typ.
Max.
Unit
51
4 7.6
11
-11 - 7.6
- 4
12.6
Ω
A
A
Ω
V
OUT
rising
Time from the V
OUT
pinout of + 20% of
REFIN to OVP fault
117 120 123
10
%
V
REFIN
µ s
V
OUT
falling
Time from the V
OUT
pinout of -30% of
REFIN to UVP fault
Time from EN = H to undervoltage ready
External tracking
Time from EN = H to undervoltage ready
65 68
256
2.4
9
71
%
V
REFIN
µ s ms ms
Overtemperature protection
Thermal shutdown threshold
(1)
OTP
Thermal shutdown hysteresis
(1)
PGOOD
145
10
°C
°C
PGOOD
Upper threshold
Lower threshold
V
OUT
rising
Hysteresis
V
OUT
falling
Hysteresis
116
8
84
8
%
V
REFIN
V
PGOOD,L
PGOOD voltage low impedance
I
PGOOD,H
PGOOD leakage high impedance
I
PGOOD_SINK
= 4 mA, V
CC
= 4.5 V 0.338
1
V
µ
A t
PGd t
PGHd t
PGLd
PGOOD startup delay time
PGOOD high delay time
PGOOD low delay time
V
PGOOD
= 5.5 V
External tracking
Time from EN = H to PGOOD high
Rising edge
Falling edge
(2)
0.8
10
1
10
1.2
ms ms
µ s
DocID027688 Rev 4 11/28
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Electrical specifications PM8908
Symbol
Table 5. Electrical characteristics (continued)
Parameter Test conditions
ENABLE
EN
Input logic high
Input logic low
I
EN
MODE
EN input current
I
M
Mode current
SOFT-START
EN rising
EN falling
V
V
EN
= 5 V
MODE from GND to 2.4 V t
SS td
Soft-start time
Delay soft-start time
From EN = H to V
OUT
From EN = H to V
OUT
ramp starts
1.
Guaranteed by design, not subject to test.
2.
Delay time not valid if the UVLO or EN shutdown events are occurring.
Min. Typ.
Max.
Unit
2
15
2.4
750
0.5
3
V
V
µ
A
µ A ms
µ s
12/28 DocID027688 Rev 4
PM8908
5 Device description
Device description
The PM8908 is a high efficiency synchronous step-down monolithic switching regulator capable to deliver or sink the current.
The power input voltage (VIN) can range from 1 V to 3.5 V, the signal input voltage (VCC) can range from 4.5 V to 5.5 V.
The output voltage is regulated to the REFIN voltage which comes from an external reference voltage. The output voltage accuracy is better than ± 1% over the line, load and temperature.
The PM8908 embeds low R
DS(on)
N-channel MOSFETs for both HS (high-side) and LS (lowside).
The high-switching frequency selectable in two values - 600 kHz or 1 MHz and the small package allows very compact VR solutions.
In the COT the t
ON
is function of V
:
IN
, V
OUT
and switching frequency (f
SW
), as shown
Equation 1 t
ON
=
V
-----------------------
V
IN
OUT
⋅ f
S W
The PM8908 features a full set of protections and output voltage monitoring:
•
Precise and accurate overcurrent limit (internally compensated against temperature variations)
•
Over and undervoltage protection
•
Overtemperature protection
•
Undervoltage lockout on analog supply (VCC)
•
Power Good open drain output easily provides real-time information about the output voltage.
The dedicated ENABLE pin (EN) offers easy control on the power sequencing. Forcing the
EN low, the device enters the shutdown state and absorbs a total quiescent current from
VCC and VIN less than 15 µA.
5.1 Power section
The PM8908 integrates two low R
DS(on)
N-channel MOSFETs as low-side and high-side switches, optimized for fast switching transition and high efficiency over the entire load range.
The HS MOSFET drain is connected to the VIN pins (power input), the LS MOSFET source is connected to the PGND pins (power ground), and the HS MOSFET source and LS
MOSFET drain are connected together and to the PHASE pins (see
The driving section is supplied from the VCC pins that assure the proper driving voltage over all the VIN range.
DocID027688 Rev 4 13/28
28
Device description PM8908
To properly supply the power section is advised following:
•
Bypass VIN pins to PGND pins as close as possible to the IC package with high quality
MLCC capacitors.
•
Connect the bootstrap capacitor (typically a 100 nF ceramic capacitor rated to stand
VIN voltage) from the BOOT pin to the PHASE pin to supply the HS driver.
Caution: Do not connect an external bootstrap diode. The IC already integrates an active bootstrap switch to charge the bootstrap capacitor, saving the cost of this external component.
The PM8908 embodies the anti shoot-through and adaptive deadtime control to minimize low-side body diode conduction time and consequently to reduce power losses:
•
When the gate driving voltage of the HS drops (to check high-side MOSFET turn-off), the LS MOSFET is suddenly switched on
•
When the gate driving voltage of the LS drops (to check low-side MOSFET turn-off), the HS MOSFET is suddenly switched on.
5.2 Device configuration
The PM8908 has a programming pin - MODE (pin 18) - which allows choosing the regulator switching frequency and the OCL threshold. This programming feature is performed by selecting the proper resistor, to be mounted between the pin 18 to ground, as summarized
Table 6. Switching frequency and OCL (see Figure 1 on page 4
)
R
M
47 k Ω
68 k
Ω
100 k
Ω f
SW
[kHz]
600
600
1000
OCL (A)
7.6
5.4
5.4
The MODE pin must not be left floating.
Note:
5.3 Startup and shutdown management
The IC monitors the supply voltage on the VCC pin. Once VCC voltage is above the UVLO
(undervoltage lockout) threshold and the EN pin is above the turn-on threshold:
•
If the IC is configured for tracking application (see
), the output voltage is regulated to the REFIN voltage. In order to discriminate between the nontracking and the tracking, there is a delay time of 750
µ s required between the EN or the VCC UVLO threshold and REFIN voltage. REFIN voltage must be applied within 9 ms (typ.) from the EN high (see
•
If the IC is configured for non-tracking application, the output voltage is regulated to the
REFIN voltage, and
the device provides a precise 2.4 ms soft-start time (see Figure 6
).
The power input (VIN) does not have a undervoltage protection function.
14/28 DocID027688 Rev 4
PM8908
V
CC
UVLO
Figure 5. PM8908 turn-on (tracking startup)
Vcc
Device description
EN
EN thr
REFIN
300mV t d t
PGd
V
CC
UVLO
Figure 6. PM8908 turn-on (non-tracking startup)
Vcc
V
OUT
=REFIN
PGOOD
EN
EN thr
REFIN
300mV t dc t d t
SS t
PGHd
DocID027688 Rev 4
V
OUT
=REFIN
PGOOD
15/28
28
Device description PM8908
Figure 7. PM8908 startup time diagram
EN
Case 1 Case 2 Case 3
PM8908 will not perform any
SS by itself but will follow
REFIN as it is observable on
REFIN pin. REFIN need to have an external SS.
PM8908
Latches UVP
0 t dc
= 550 us(typ) t d
=750 us(typ) 9 ms(typ)
Soft-off
The PM8908 implements the soft-off sequence turning off both the HS and LS MOSFETs and connecting the integrated discharge resistor (47
Ω
) between the PHASE and PGND pin.
The PM8908 begins the soft-off sequence, and remains in a latched state, if one of the following conditions occurs:
•
VCC voltage falls below UVLO threshold
•
OVP (overvoltage protection)
•
UVP (undervoltage protection)
•
EN pin is pulled low.
The cycling VCC and EN the IC recover from the latched state with a new soft-start sequence.
5.4
5.4.1
Output voltage monitoring and protection
The PM8908 monitors the output voltage status through the V
OUT
pin and compares the voltage on this pin with the REFIN voltage in order to provide over and undervoltage protection as well as the PGOOD signal.
Overvoltage protection
Overvoltage protection is active as soon as the device is enabled, the VCC is above the respective undervoltage lockout level and REFIN is higher than 300 mV.
16/28 DocID027688 Rev 4
PM8908
5.4.2
5.4.3
5.4.4
Device description
The protection is triggered when the voltage sensed on the V
OUT
pin rises over the OVP threshold and the device acts as follows:
•
De-asserts the PGOOD signal
•
The HS MOSFET is suddenly forced OFF
•
The LS MOSFET is turned on (to discharge the output and protect the load). When
V
OUT
drops below the UVP threshold the LS MOSFET is turned off and the discharge resistor is on. If V
OUT
recrosses the UVP threshold, the LS is turned on again and the discharge resistor is off.
In the overvoltage protection state the negative overcurrent limit (OCLN) is masked.
This protection is latched, cycled EN or VCC to recover.
Undervoltage protection
If VOUT falls below the UVP threshold for at least 256
µ s the IC stops switching and starts a soft-off sequence.
The device acts as follows:
•
De-asserts the PGOOD signal
•
The HS MOSFET and LS MOSFET are forced OFF
•
The discharge resistor is on.
This protection is latched, cycled EN or VCC to recover.
The UVP protection is enabled after the soft-start end.
Power Good (PGOOD)
The PGOOD is an open drain output. During the startup, the PGOOD goes high after 1 ms from the threshold detected.
The PGOOD is forced low, to communicate that the output voltage is no longer in regulation, if one of the following conditions is verified:
•
The voltage of the V
OUT
pin exits from the PGOOD window
•
The device is disabled, EN is forced low
•
VCC voltage is below the UVLO threshold
•
Any protection is triggered (OVP, UVP, OTP).
Overcurrent protection
Overcurrent protection is active as soon as the device is enabled and VCC voltage is above the UVLO level.
The overcurrent function protects the converter from a shorted output or overload by sensing the output current information across the low-side integrated MOSFET.
•
Positive OCL
If the monitored current information is bigger than the overcurrent thresholds, an overcurrent event is detected. The IC delays the next t
ON
until the current drops below the positive OCL limit.
DocID027688 Rev 4 17/28
28
Device description
5.4.5
PM8908
The maximum available load current, with the valley current limit technique, is equal to
:
Equation 2
I
LOA Dmax
= I
OCL
+
1
---
2
⋅ ∆
I
It is the sum of the valley current limit plus the half of the inductor current ripple.
During the overcurrent event the Vout drops until the UVP threshold, de-asserts the PGOOD pin and then enters into the latch state.
•
Negative OCL
The negative OCL circuit operates when the converter is sinking the current from the output load. The IC trigs the next t
ON
until the current drops below the negative OCL limit.
During the overcurrent event the Vout goes up until the OVP threshold, de-asserts the
PGOOD pin and then enters into the latch state.
Overtemperature protection
It is recommended that the device never exceeds the maximum allowable junction temperature. This temperature increase is mainly caused by the total power dissipated from the integrated power MOSFETs.
To avoid any damage to the device when reaching high temperature, the PM8908 implements a thermal shutdown feature: when the junction temperature reaches 145 °C the device turns off both MOSFETs. When the junction temperature drops to 135 °C, the device restarts with a new soft-start sequence.
18/28 DocID027688 Rev 4
PM8908
6 Application information
6.1
Application information
Output voltage setting
The PM8908 integrates a 2 V internal reference (V
REF
), with the total accuracy of ± 1%.
The output voltage, in non-tracking configuration, can be easily programmed connecting the
R
1
and R
2
resistors as follows (see also
•
Connect the REFIN to the REF pin through the R
1
resistor
•
Connect the REFIN pin to the GND through the R
2
resistor
Therefore, the output voltage setting is easily achieved using Equation 3 to select the value
of the R
OS
resistor:
Equation 3
V
OUT
=
V
REF
1 +
(
R
1
⁄
R
2
)
Figure 8. Resistor divider configuration
R
2
R
1
9
7
REFIN
VREF
6.2 Droop setting
In order to reduce the necessary output capacitance amount, the PM8908 can perform the load dependent behavior if the compensation network capacitor, CC, is avoided. The sensed current is used for reference voltage, in the PWM comparator inverting input. So doing, the programmed output voltage is:
Equation 4 where:
V
OUT
= V
RE FIN
– V
DROOP
V
DROOP
=
A
R
CS
⋅
I
LOAD
DROOP
⋅
G
M
DocID027688 Rev 4 19/28
28
Application information PM8908 with:
•
R
DROOP
is the resistor between the COMP pin and the REF pin (see also Figure 9
)
•
I
LOAD
is the output current
•
G
M
is the transconductance of the amplifier (1 mS)
•
A
CS
is the current sense gain (53 mV/A)
Figure 9. Typical application with droop configuration
R
M
VCC = 5 V
R
PGOOD
C
VCC
R
2
R
1
20 4, 5
VIN = 1 V to 3.5 V
VCC VIN
6
GND PGND
1, 2, 3
19
17
PGOOD
EN
18
9
MODE
REFIN
PM8908
7
REF
C
P
BOOT
16
C
PHASE
11, 12, 13,
14, 15
COMP
VOUT
8
10
BOOT
L
C
VIN
VOUT
C
OUT
R
DROOP
C
REF
6.3
6.4
Non-droop setting
The advantage of a non-droop configuration is that the load regulation is flat. It can be implemented by connecting a resistor (R
C
) and a capacitor (C
C
) between the COMP pin and the REF pin (see also
Inductor design
The inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost, and the size. The inductor must be calculated to maintain the ripple current (
∆
I
L
) between 20% and 30% of the maximum output current (typ.). The inductance value can be calculated with the following relationship:
Equation 5
L =
V
------------------------------
F
–
S W
V
⋅
OUT
∆
I
L
⋅
V
--------------
V
IN where f
SW
is the switching frequency, V
IN
is the input voltage, and V
OUT
is the output voltage.
20/28 DocID027688 Rev 4
PM8908
6.5
Application information
Output capacitors
The output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient.
During steady-state conditions, the output voltage ripple is influenced by both the ESR and the capacitive value of the output capacitors as follows:
Equation 6
∆
V
OUT_ESR
=
∆
I
L
⋅
ESR
Equation 7
∆
V
OUT_C
=
∆
I
L
⋅
⋅
1
OUT
⋅
F
SW where
∆
I
L
is the inductor current ripple. In particular, the expression that defines
∆
V
OUT_C takes into consideration the output capacitor charge and discharge as a consequence of the inductor current ripple.
6.6 Input capacitors
The input capacitor bank is designed considering, mainly, the input RMS current that depends on the output deliverable current (I
OUT
) and the duty cycle (D) for the regulation as follows:
Equation 8
I rms
= I
OUT
⋅
D
⋅ (
1 – D
)
The equation reaches its maximum value, I
OUT
/2, with D = 0.5. The losses depend on the input capacitor ESR and, in the worst case, are:
Equation 9
P = ESR
⋅ (
I
OUT
⁄
2
) 2
DocID027688 Rev 4 21/28
28
Application information
6.7
PM8908
Compensation network
The PM8908 device implements a constant on-time control loop. The compensation network is shown in
Figure 10. Compensation network
9
7
REFIN
REF
COMP
8
C
P
C
F
R
F
C
REF
The following procedure shall be followed in order to calculate the best network external components value.
•
Select R
F
value in order to obtain the desired closed loop regulator bandwidth
:
Equation 10
R
F
=
2
π ⋅ f
T
⋅
C
OUT
⋅
R
CS g
M
1
+
2
π ⋅ f
T
5
⋅
1
−
2
π
ESR
⋅ f
T
5
⋅
C
OUT
⋅
ESR
⋅
C
OUT
where:
– f
T
is the crossover frequency, it should be less than about 1/10 of the switching frequency
– R
CS
= 53 m
Ω
•
Select C
F according to
:
Equation 11
C
F
≥
2
π ⋅
1 f
T
5
•
Select C
P
according to
:
⋅
R
F
Equation 12
C
P
=
R
C
ESR
⋅
1
−
2
π ⋅
⋅
C
OUT f
T
5
⋅
ESR
⋅
C
OUT
•
Check the phase margin obtained and repeat the whole procedure if necessary.
22/28 DocID027688 Rev 4
PM8908
7 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
DocID027688 Rev 4 23/28
28
Package information
7.1 QFN20 package information
Figure 11. QFN20 3.5 x 4 x 1.0 mm package outline
PM8908
24/28 DocID027688 Rev 4
".
PM8908 Package information
Symbol
Table 7. QFN20 3.5 x 4 x 1.0 mm package mechanical data
Dimensions (mm)
Min.
Typ.
Max.
D
D2
E
E2 e
A
A1
A3 b
L
K
0.90
0.00
0.18
3.4
2.00
3.9
2.50
0.35
0.20
0.95
0.02
0.152
0.25
3.5
2.10
4.0
2.60
0.50
0.40
1.00
0.05
0.45
0.30
3.6
2.20
4.1
2.70
Figure 12. Recommended footprint
DocID027688 Rev 4
".
25/28
28
Package information
Figure 13. QFN20 3.5 x 4 x 1.0 mm tape and reel
PM8908
Figure 14. QFN20 3.5 x 4 x 1.0 mm winding direction
".
26/28 DocID027688 Rev 4
PM8908
8 Revision history
Revision history
Date
30-Mar-2015
22-Oct-2015
09-Nov-2015
25-Jul-2017
Revision
Table 8. Document revision history
Changes
1
2
3
4
Initial release.
– Added footnote 2 to Table 4.
– Added minimum and maximum dimension values for symbols D and E in Table 7.
First public release.
Updated: A
CS
, R
DS
, R
BSS
and V
PGOOD,L
values in
.
DocID027688 Rev 4 27/28
28
PM8908
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28/28 DocID027688 Rev 4
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