STMicroelectronics STIB1060DM2T-L Datasheet
STMicroelectronics STIB1060DM2T-L is a small low-loss intelligent molded module that combines new ST proprietary control ICs with MDMesh DM2 high-voltage N-channel superjunction MOSFETs, providing fast-recovery diodes for increased efficiency and low EMI. Suitable for any high-efficiency converter and 3-phase inverter system, this device also features an internal bootstrap diode, undervoltage lockout of gate drivers, short-circuit protection, a shutdown input/fault output, and a built-in temperature sensor.
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STIB1060DM2T-L
Datasheet
SLLIMM™ - 2
nd
series IPM, 3-phase inverter, 0.18 Ω typ., 10 A, 600 V
Power MOSFET
Marking area
SDIP2B-26L type L
Product status link
STIB1060DM2T-L
Product summary
Order code STIB1060DM2T-L
Marking
Package
Packing
IB1060DM2T-L
SDIP2B-26L type L
Tube
Features
• IPM 10 A, 600 V, 3-phase MOSFET inverter bridge including 2 control ICs for gate driving
• 3.3 V, 5 V TTL/CMOS inputs with hysteresis
• Internal bootstrap diode
• Undervoltage lockout of gate drivers
• Smart shutdown function
• Short-circuit protection
• Shutdown input/fault output
• Separate open-source outputs
• Built-in temperature sensor
• Comparator for fault protection
• Fast, soft recovery diodes
• 85 kΩ NTC, UL 1434, CA 4 recognized
• Fully isolated package
• Isolation rating of 1500 Vrms/min
• UL recognition: UL 1557, file E81734
Applications
• 3-phase inverters for motor drives
• Linear and BLDC compressor
• Aircon
Description
This new IPM, belonging to the second series of SLLIMM (small low-loss intelligent molded module), provides a compact, high-performance AC motor drive in a simple, rugged design.
It combines new ST proprietary control ICs with the high-voltage N-channel superjunction MDMesh™ DM2, providing fast-recovery diode series to increase efficiency and minimize EMI and overall losses, making it ideal for any high-efficiency converter and 3-phase inverter system. SLLIMM™ is a trademark of STMicroelectronics.
DS12121 - Rev 2 - July 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STIB1060DM2T-L
Internal schematic and pin description
Internal schematic and pin description
Figure 1. Internal schematic diagram and pin configuration
NC (1)
VbootU (2)
VbootV (3)
VbootW (4)
HinU (5)
HinV (6)
HinW (7)
VccH (8)
GND (9)
LinU (10)
LinV (11)
LinW (12)
VccL (13)
SD / OD (14)
Cin (15)
GND (16)
TSO (17)
H-side
L-side
(26) T1
(25) T2
(24) P
23 (U)
(22) V
(21) W
(20) NU
(19) NV
(18) NW
GADG240420171352IG
DS12121 - Rev 2 page 2/23
DS12121 - Rev 2
STIB1060DM2T-L
Internal schematic and pin description
17
18
19
20
21
12
13
14
15
16
22
23
24
25
26
7
8
9
10
11
Pin
1
2
3
4
5
6
LINw
VCCL
SD /OD
CIN
GND
TSO
NW
NV
NU
W
V
U
P
T2
T1
Symbol
NC
VBOOTu
VBOOTv
VBOOTw
HINu
HINv
HINw
VCCH
GND
LINu
LINv
Table 1. Pin description
Description
-
Bootstrap voltage for U phase
Bootstrap voltage for V phase
Bootstrap voltage for W phase
High-side logic input for U phase
High-side logic input for V phase
High-side logic input for W phase
High-side low voltage power supply
Ground
Low-side logic input for U phase
Low-side logic input for V phase
Low-side logic input for W phase
Low-side low voltage power supply
Shutdown logic input (active low) / open-drain (comparator output)
Comparator input
Ground
Temperature sensor output
Negative DC input for W phase
Negative DC input for V phase
Negative DC input for U phase
W phase output
V phase output
U phase output
Positive DC input
NTC thermistor terminal 2
NTC thermistor terminal 1 page 3/23
2
STIB1060DM2T-L
Absolute maximum ratings
Absolute maximum ratings
T
J
= 25 °C unless otherwise noted.
Table 2. Inverter part
Symbol
V
PN
V
PN(surge)
V
DSS
Parameter
Supply voltage between P -N
U
, -N
V
, -N
W
Supply voltage surge among P -N
U
, -N
V
, -N
W
MOSFET blocking voltage (or drain-source voltage) for each MOSFET
(V
IN
= 0)
Drain current (continuous) at T
C
= 25 °C t
± I
D
± I
P
DP
TOT scw
Peak drain current each MOSFET (less than 1 ms)
Total power dissipation at T
C
=25 °C each MOSFET
Short circuit withstand time, V
DS
= 300 V, T
J
= 125 °C, V
CC
= V boot
= 15 V,
V
IN
= 0 to 5 V
1. Applied among HINx, LINx and GND for x = U, V, W
Symbol
V
CC
V
BOOT
V
OUT
V
CIN
V
IN
V
SD/OD
I
SD/OD
V
TSO
I
TSO
Table 3. Control part
Parameter
Supply voltage between V
CCH
-GND, V
CCL
-GND
Bootstrap voltage
Output voltage among U, V, W and GND
Comparator input voltage
Logic input voltage applied among HINx, LINx and GND
Open-drain voltage
Open-drain sink current
Temperature sensor output voltage
Temperature sensor output current
Value
450
500
600
12.5
50
78
12
Min.
Max.
- 0.3
- 0.3
20
619
V
BOOT
- 21 V
BOOT
+ 0.3
- 0.3
20
- 0.3
15
-0.3
-0.3
7
10
5.5
7
V
V
V
Unit
V
V
V mA
V mA
V
A
A
W
Unit
V
V
μs
Symbol
V
ISO
T
J
T
C
Table 4. Total system
Parameter
Isolation withstand voltage applied between each pin and heatsink plate
(AC voltage, t = 60 s.)
Power chips operating junction temperature range
Module operation case temperature range
Value
1500
-40 to 150
-40 to 125
Unit
Vrms
°C
°C
DS12121 - Rev 2 page 4/23
2.1
Thermal data
Symbol
R th(j-c)
Table 5. Thermal data
Parameter
Thermal resistance junction-case single MOSFET
STIB1060DM2T-L
Thermal data
Value
1.59
Unit
°C/W
DS12121 - Rev 2 page 5/23
3
3.1
STIB1060DM2T-L
Electrical characteristics
Electrical characteristics
T
J
= 25 °C unless otherwise noted.
Inverter part
Table 6. Static
Symbol
V
I
DSS
(BR)DSS
R
DS(on)
V
SD
Parameter Test conditions
Zero gate voltage drain current V
DS
= 600 V, V
CC
= V boot
= 15 V
Drain-source breakdown voltage
V
CC
= V boot
= 15 V,
V
IN
D
= 1 mA
Static drain-source turn-on resistance
V
CC
= V boot
= 15 V, V
IN
I
D
= 1.0 A
V
CC
= V boot
= 15 V, V
IN
I
D
= 10 A
Drain-source diode forward voltage
V
IN
D
= 10 A
1. Applied among HINx, LINx and GND for x = U, V, W.
Min.
Typ.
Max.
Unit
100 μA
600 V
0.168
Ω
0.180
0.210
0.98
1.36
V
Table 7. Inductive load switching time and energy
Symbol t on
t c(on)
t off
t c(off)
t rr
E on
E off
E rr
Parameter
Turn-on time
Cross-over time on
Turn-off time
Cross-over time off
Reverse recovery time
Turn-on switching energy
Turn-off switching energy
Reverse recovery energy
V
V
DD
Test conditions
= 300 V, V
IN
CC
D
= V boot
= 10 A
= 15 V,
Min.
-
-
-
-
-
-
-
-
Typ.
560
160
1040
70
155
465
70
23
Max.
-
-
-
-
-
-
-
-
Unit ns
µJ
1. t on
and t off
include the propagation delay times of the internal drive. t
C(on) itself under the internally given gate driving condition.
and t
C(off)
are the switching times of the MOSFET
2. Applied among HINx, LINx and GND for x = U, V, W.
DS12121 - Rev 2 page 6/23
V
CC
+5 V
5 V
0 V
Input
Rsd
STIB1060DM2T-L
Inverter part
Figure 2. Switching time test circuit
VCC
Hin
GND
Boot
HVG
OUT
VCC
Lin
SD
Cin
GND
LVG V
+
DS
-
L
I
D
C
-
+
Vdd
GADG240420171446IG
V
Figure 3. Switching time definition
100% I
D
100% I
D t rr
DS
I
D
I
D
V
DS
DS12121 - Rev 2
V
IN
V IN(ON) t
ON t
C(ON)
10% I
D
90% I
D
10% V
DS
(a) turn-on
V
IN t
OFF
V IN(OFF)
10% V DS t
C(OFF)
10% I D
(b) turn-off
AM09223V2 page 7/23
STIB1060DM2T-L
Control/protection parts
3.2
Control/protection parts
Symbol
V il
V ih
I
INh
I
INl
V
CC_hys
V
CCH_th(on)
V
CCH_th(off)
V
BS_hys
V
BS_th(on)
V
BS_th(off)
I
QBSU
I
QBS
I qccu
I qcc
R
DS(on)
V
CC_hys
V
CCL_th(on)
V
CCL_th(off)
I qccu
I qcc
Parameter
Low logic level voltage
High logic level voltage
IN logic “1” input bias current
IN logic “0” input bias current
Table 8. High- and low-side drivers
Test condition
IN x
= 15 V
IN x
= 0 V
High-side
V
CC
UV hysteresis
V
CCH
UV turn-on threshold
V
CCH
UV turn-off threshold
V
BS
UV hysteresis
V
BS
UV turn-on threshold
V
BS
UV turn-off threshold
Under voltage V
BS
quiescent current
V
BS
quiescent current
Under voltage quiescent supply current
Quiescent current
BS driver ON resistance
V
BS
= 9 V, HINx
V
CC
V
CC
= 9 V, HINx
V
CC
Low-side
V
CC
UV hysteresis
V
CCL
UV turn-on threshold
V
CCL
UV turn-off threshold
Under voltage quiescent supply current
Quiescent current
V
CC
= 10 V, SD pulled to 5 V through R
SD
= 10 kΩ,
CIN = LINx
= 0
V
CC
= 15 V, SD= 5 V,
CIN = LINx
= 0
V
SSD
I
SDh
I
SDl
Smart SD unlatch threshold
SD logic “1” input bias current
SD logic “0” input bias current
1. Applied among HINx, LINx and GND for x = U, V, W
SD = 5 V
SD = 0 V
Symbol
V
TSO
I
TSO_SNK
I
TSO_SRC
Table 9. Temperature sensor output
Parameter
Temperature sensor output voltage
Temperature sensor sink current capability
Temperature sensor source current capability
T
J
= 25 °C
Test condition
Min.
2
80
Typ.
Max.
0.8
150 200
1
Unit
V
V
µA
µA
1.2
11
9.6
0.5
10.1
9.1
1.4
11.5
10.1
1
11
10
55
125
190
560
150
75
170
250
730
1.7
12
10.6
1.6
11.9
10.9
µA
µA
µA
V
V
V
V
V
V
µA
Ω
1.1
10.4
9.0
1.4
11.6
10.3
1.6
12.4
11
600 800
V
V
V
µA
0.5
25
700
0.6
50
900
0.75
70
1
µA
V
µA
µA
Min.
0.974
Typ.
1.16
0.1
Max.
1.345
4
Unit
V mA mA
DS12121 - Rev 2 page 8/23
STIB1060DM2T-L
Control/protection parts
Symbol
I
CIN
V ref
V
OD t
CIN_SD
SR
SD
Table 10. Sense comparator (V
CC
= 15 V, unless otherwise is specified)
Parameter Test condition
CIN input bias current
Internal reference voltage
V
CIN
=1 V
Open-drain low level output voltage I od
= 5 mA
C
IN
comparator delay to SD
SD pulled to 5 V through R
SD
= 10 kΩ; measured applying a voltage step 0-1 V to pin
CIN;
50 % CIN to 90 % SD
SD fall slew rate
SD pulled to 5 V through R
SD
= 10 kΩ;
C
L
= 1 nF through SD and ground;
90 % SD to 10 % SD
Min.
-0.2
460
240
Typ.
510
320
25
Max.
0.2
560
500
410 ns
V/µs
Unit
µA mV mV
The comparator stays enabled even if V
CC
is in the UVLO condition but higher than 4 V.
DS12121 - Rev 2 page 9/23
4
STIB1060DM2T-L
Fault management
Fault management
The device integrates an open-drain output connected to the SD pin. As soon as a fault occurs, the open-drain is activated and the LVGx outputs are forced low. Two types of fault can be identified:
•
Overcurrent (OC) sensed by the internal comparator (see more detail in function );
• Undervoltage on supply voltage (V
CC
)
Each fault enables the SD open drain for a different time, as described in the following table.
Table 11. Fault timing
Symbol
OC
UVLO
Parameter
Over-current event
Under-voltage lockout event
1. Typical value (-40 °C ≤ T
J
≤ +125 °C)
2. Without contribution of the RC network on SD
Event time
≤ 24 μs
> 24 µs
≤ 70 μs
> 70 µs until the VCC_LS exceeds the
VCC_LS UV turn ON threshold
SD open-drain enable time result (1)(2)
24 μs
OC time
70 µs
UVLO time
Actually, the device remains in a fault condition (SD at low logic level and LVGx outputs disabled) for a time also depending on the RC network connected to the SD pin. The network generates a time contribution that is added to the internal value.
Figure 4. Overcurrent timing (without contribution of the RC network on SD)
DS12121 - Rev 2
GIPG120520141638FSR page 10/23
STIB1060DM2T-L
Fault management
Figure 5. UVLO timing (without contribution of the RC network on SD)
DS12121 - Rev 2 page 11/23
4.1
STIB1060DM2T-L
Smart shutdown function
Smart shutdown function
The device integrates a comparator committed to the fault sensing function. The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function.
The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on the
SD input. When the comparator triggers, the device is set in shutdown state and its outputs are all set to low level.
Figure 6. Smart shutdown timing waveforms in case of overcurrent event comp
Vref
CIN
PROTECTION t
CIN_SD
LIN
LVG
SD l open-drain gate
(internal) t
1 t
OC real disable time
Fast shutdown: the driver outputs are set in SD state immediately after comparator triggering even if the SD signal has not yet reached the lower input threshold
SHUTDOWN CIRCUIT
FROM / TO
CONTROLLER
V
BIAS
R
SD
SD
C
SD
R
PD_SD
R
ON_OD
SMART
SD
LOGIC t t where:
1
2 t
2
R
ON_OD
= V
OD
/5 mA, see
= 15 V, unless otherwise is specified) ;
R
PD_SD
(typ.) = 5 V/I
SDh
DS12121 - Rev 2 page 12/23
STIB1060DM2T-L
Smart shutdown function
In common overcurrent protection designs, the comparator output is usually connected to the SD input and an RC network is connected to this SD line in order to provide a mono-stable circuit which implements a protection time that follows the fault condition.
As opposed to common fault detection systems, the device smart shutdown architecture allows the immediate turn-off of output gates driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual switching off of the outputs. In fact, the time delay between the fault and the turning off of the outputs is no longer dependent on the RC value of the external network connected to the pin.
In the smart shutdown circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering.
At the same time, the internal logic turns on the open-drain output and holds it on until the SD voltage goes below the V
SSD
threshold and the t oc
time is elapsed.
The driver outputs restart following the input pins as soon as the voltage at the SD pin reaches the higher threshold of the SD logic input.
The smart shutdown system provides the possibility to increase the time constant of the external RC network (i.e., the disable time after the fault event) up to very high values without increasing the delay time of the protection.
DS12121 - Rev 2 page 13/23
5
5.1
5.2
STIB1060DM2T-L
Temperature monitoring solutions
Temperature monitoring solutions
TSO output
The device integrates a temperature sensor. A voltage proportional to the die temperature is available on the TSO pin. When this function is not used, the pin can be left floating.
Figure 7. V
TSO
output characteristics vs LVIC temperature
V
TSO
(V)
IGBT110820161234TSO
2.8
Min
2.2
1.6
1.0
0.4
0
Max
Typ
25 50 75 100 T (°C)
NTC thermistor
Symbol
R
25
R
125
B
T
Parameter
Resistance
Resistance
B-constant
Operating temperature range
Table 12. NTC thermistor
Test condition
T = 25 °C
T = 125 °C
T = 25 to 100 °C
Min.
-40
Typ.
85
2.6
4092
Max.
125
Unit kΩ kΩ
K
°C
DS12121 - Rev 2 page 14/23
DS12121 - Rev 2
STIB1060DM2T-L
NTC thermistor
R(kΩ)
30
25
20
15
10
5
0
50
Figure 8. NTC resistance vs temperature
R(kΩ)
3000
2500
2000
1500
1000
500
0
-50
Typ
-25
Min
Max
0 25 50 75
GIPG120520142249FSR
100 125 T(°C)
Figure 9. NTC resistance vs temperature - zoom
GIPG120520141304FSR
60
Typ
Max
Min
70 80 90 100 110 120 T(°C) page 15/23
6
Application circuit example
Figure 10. Application circuit example
STIB1060DM2T-L
Application circuit example
DS12121 - Rev 2
MICROCONTROLLER
GADG260420170807IG
Application designers are free to use a different scheme according to the device specifications.
page 16/23
6.1
STIB1060DM2T-L
Guidelines
Guidelines
1.
Input signals HIN, LIN are active-high logic. A 100 kΩ (typ.) pull-down resistor is built-in for each input pin.
To prevent input signal oscillations, the wiring of each input should be as short as possible and the use of
RC filters (R
1
, C
1
) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins.
2.
The use of a bypass capacitor C
VCC
(aluminum or tantalum) can reduce the transient circuit demand on the power supply. Besides, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C
2
(100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to each V cc
pin and in parallel with the bypass capacitor.
3.
The use of an RC filter (R
SF
, C
SF
) prevents protection circuit malfunctions. The time constant (R
SF
x C
SF
) should be set to 1 µs and the filter must be placed as close as possible to the CIN pin.
4.
The SD is an input/output pin (open-drain type if it is used as output). It should be pulled up to a power supply (i.e., MCU bias at 3.3/5 V) by a resistor value, which can keep the I od
no higher than 5 mA (V
OD
≤
500 mV when open-drain MOSFET is ON). The filter on SD should be sized to get a desired re-starting time after a fault event and placed as close as possible to the SD pin.
5.
A decoupling capacitor C
TSO
between 1 nF and 10 nF can be used to increase the noise immunity of the
TSO thermal sensor; a similar decoupling capacitor C
OT
(between 10 nF and 100 nF) can be implemented if the NTC thermistor is available and used. In both cases, their effectiveness is improved if these capacitors are placed close to the MCU.
6.
The decoupling capacitor C
3
(100 to 220 nF with low ESR and low ESL) in parallel with each C boot
filters high-frequency disturbances. Both C boot
and C
3
(if present) should be placed as close as possible to the
U,V,W and V boot
pins. Bootstrap negative electrodes should be connected to the U,V,W terminals directly and separated from the main output wires.
7.
To prevent overvoltage on the V
CC
pin, a Zener diode (Dz1) can be used. Similarly on the V boot diode (Dz2) can be placed in parallel with each C boot
.
pin, a Zener
8.
The use of the decoupling capacitor C
4
(100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor C
Vdc
prevents surge destruction. Both capacitors C
4
and C
Vdc
should be placed as close as possible to the IPM (C
4
has priority over C vdc
).
9.
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an optocoupler is possible.
10. Low inductance shunt resistors should be used for phase leg current sensing.
11. In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible.
12. The connection of the SGN_GND to the PWR_GND at one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation.
These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note.
Symbol
V
PN
V
CC
V
BS t dead f
PWM
T
C
Table 13. Recommended operating conditions
Parameter
Supply voltage
Control supply voltage
High-side bias voltage
Test conditions
Applied among P-Nu, N
V
, N w
Applied to V
CC
-GND
Applied to V
BOOTi
-OUT i
for i = U, V, W
Blanking time to prevent arm-short For each input signal
PWM input signal
-40 °C < T
C
< 100 °C
-40 °C < T
J
< 125 °C
Case operation temperature
Min.
13.5
13
1.5
Typ.
300
15
Max.
400
18
18
Unit
V
V
V
µs
20
100 kHz
°C
DS12121 - Rev 2 page 17/23
STIB1060DM2T-L
Electrical characteristics (curves)
7
Electrical characteristics (curves)
8
4
0
0
Figure 11. Output characteristics
I
D
(A)
16
V
CC
= 15 V
IGBT200920181213OC25
T
J
= 25 °C
12
1 2
T
J
= 150 °C
3 4 V
DS
(V)
I
D
(A)
Figure 13. I
D
vs temperature
IGBT200920181216IDT
12
9
6
3
V
CC
= 15 V, T
J
≤ 150 °C
0
0 25 50 75 100 125 150 T
C
(°C)
Figure 15. E
OFF
switching energy vs drain current
E
OFF
(mJ)
IGBT200920181218SFC
V
DD
= 300 V, V
CC
= V boot
15 V
0.3
T
J
= 150 °C
0.2
0.1
0.0
0 4
T
J
= 25 °C
8 12 16 I
D
(A)
Figure 12. Diode V
SD
vs drain current
V
SD
(V) V
CC
= 15 V
1.0
T
J
= 25 °C
0.8
IGBT200920181215DVF
T
J
= 150 °C
0.6
0.4
0.2
0.0
0 4 8 12 16 I
D
(A)
Figure 14. E
ON
switching energy vs drain current
E
ON
(mJ)
1.8
IGBT200920181217SLC
V
DD
= 300 V, V
CC
= V boot
15 V
1.5
1.2
0.9
0.6
0.3
0.0
0 4
T
J
= 150 °C
8 12
T
J
= 25 °C
16 I
D
(A)
Figure 16. Thermal impedance for MOSFET
K GIPD290720151032FSR
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 10 0 t p
(s)
DS12121 - Rev 2 page 18/23
8
8.1
STIB1060DM2T-L
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
SDIP2B-26L type L package information
Figure 17. SDIP2B-26L type L package outline
DS12121 - Rev 2
8450802_5_type_L page 19/23
DS12121 - Rev 2
Ref.
e4
E
E1
E2 f
D1 e e1 e2 e3
R
T
V f1
F
F1
B1
B2
B3
C
C1
C2
D
A
A1
A2
A3 c
B
STIB1060DM2T-L
SDIP2B-26L type L package information
Table 14. SDIP2B-26L type L package mechanical data
13.90
28.90
3.30
5.00
13.50
28.70
2.55
3.356
1.578
7.42
4.88
2.34
11.90
3.45
0.45
0.35
1.95
0.95
1.55
0.375
0°
Min.
37.50
0.97
0.97
34.70
1.45
23.50
Dimensions (mm)
Typ.
38.00
1.22
1.22
35.00
1.50
24.00
2.85
3.556
1.778
7.62
5.08
12.00
14.40
29.40
3.50
5.50
14.00
29.30
0.50
2.10
1.10
1.575
0.40
2.54
12.40
3.75
1.80
0.60
14.90
29.90
3.70
6.00
14.50
29.80
3.15
3.756
1.978
7.82
5.28
2.74
12.90
4.05
Max.
38.50
1.47
1.47
35.30
1.55
24.50
0.75
0.65
2.25
1.25
1.60
0.425
5° page 20/23
STIB1060DM2T-L
Revision history
Date
02-May-2017
24-Sep-2018
15-Jul-2019
2
3
Table 15. Document revision history
Revision
1
Changes
Initial release
Updated title, features and description on cover page.
Updated Table 2, Table 5 and Table 11.
Updated Section 3, Section 7 and Section 8.1.
Minor text changes
Added feature on cover page.
Minor text changes
DS12121 - Rev 2 page 21/23
STIB1060DM2T-L
Contents
Contents
DS12121 - Rev 2 page 22/23
STIB1060DM2T-L
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS12121 - Rev 2 page 23/23
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