STMicroelectronics L6572 Datasheet
Anúncio
Anúncio
L6572
High voltage smart ballast controller
Datasheet
−
production data
Features
■
■
■
■
■
■
■
■
600 V half-bridge driver
Integrated bootstrap diode
Failure protection logic
Programmable deadtime
Programmable preheated start
Two-step dimming with programmable dimmed current
Thermal powerboost
Closed loop control operation
Figure 1.
Block diagram
GND T S D
Applications
■
■
CFLi
Electronic ballast
SO14
V S
UVLO VREF
COUNTER
IGNITION
RECOGNI-
TION
DAC
2 S TEP
DIMMING
OUTPUT
S TAGE
DEAD
TIME
H S D
L S D
BOOT
HVG
OUT
LVG
CLOCK
RATED
CURRENT
TPB
ZV S
CURRENT
REGULATION
S IGNAL
PROCE SS ING
RDT
S EN S E
RCL RPH RNO RDO
AM14 88 1v1
October 2012
This is information on a product in full production.
Doc ID 023882 Rev 1 1/22 www.st.com
22
Contents
Contents
L6572
Thermal powerboost control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Designing a simple fixed power CFLi application using the L6572 . . . . . 16
Two-step dimmable CFLi application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/22 Doc ID 023882 Rev 1
L6572
1 Description
Description
The L6572 is a high voltage half-bridge driver for current regulation, quasi-self-oscillating ballast.
It contains all functions that are needed to preheat the filaments, to ignite and to operate a fluorescent lamp.
During normal operation of the lamp, the ballast operates either with the nominal or with a reduced resonant current which results in a nominal or a reduced light output of the lamp.
A change between those two possible light outputs of the lamp is triggered by disconnecting the mains voltage for a short time (two-step dimming). The filaments are preheated before the lamp is re-ignited after every disconnection of the mains voltage.
A powerboost function is included to accelerate the startup behavior of the fluorescent lamp when the junction temperature is below a defined temperature.
An undervoltage lockout is active while loading the blocking capacitor via the startup resistor as long as the supply voltage VS is below a defined value. The bootstrap capacitor is loaded before the high-side transistor is switched on the first time to start the oscillation of the ballast.
The output drivers are designed to drive external N-channel power MOSFET and IGBT
(max. input capacity C input
≤ 1 nF) without any additional gate resistor.
A constant deadtime for both switches can be programmed with one external resistor.
The rated resonant current for the nominal lamp operation with nominal light output, the dimmed operation with reduced light output and the preheating phase is defined by three external resistors considering the shunt resistance.
The ratio X
PB
between the nominal rated resonant current during normal operation and the powerboost phase is fixed internally. The time lapse is given by an internally fixed number of load/unload-cycles of an internal capacitor.
An absolute time base, used to regulate periods and intervals, is given by the duration of a load/unload-cycle of the internal capacitor with a load current that is defined with an external resistor.
Doc ID 023882 Rev 1 3/22
Description
Figure 2.
Typical application n.c.
11
14
S i
Br
-
L1
R a 1 3
12
T1
C1 C2
1
R b
D4
9
2 3 4 5 8 6 7
10
T2
R1
C 3
C4
L2
C7 D5
C6
R2
R
PH
R
DO
R
NO
R
CL
R
DT
C5
L6572
AM14 88 2v1
4/22 Doc ID 023882 Rev 1
L6572 Pin connection
Figure 3.
Pin connection
T S D
RPH
RDO
BOOT
HVG
OUT
RNO
RCL
L6572
NC
LVG
GND V S
S EN S E RDT
AM14 883 v1
Table 1.
TSD
RPH
RDO
RNO
RCL
GND
SENSE
RDT
VS
Pin description
Symbol Pin Description
1 Input voltage for dimmed operation detection. Connected to ground if unused.
2
Preheating current programming. A resistor placed between this pin and ground defines the rated load current during the preheating phase.
3
4
Reduced light level current programming. A resistor placed between this pin and ground defines the rated load current during the dimmed operation.
Nominal light level current programming. A resistor placed between this pin and ground defines the rated load current during the normal operation.
5 Time base period programming.
6 Reference voltage of the device.
7
Current sense input. This pin has to be connected to a shunt resistor placed in series with the load.
8
9
Deadtime programming. A resistor paced between this pin and ground allows the deadtime to be programmed between LSG and HSG pulses in the range (1 µs to 5
µs).
Supply voltage of the device. A bulk capacitor and an optional ceramic capacitor must be connected between this pin and ground.
Doc ID 023882 Rev 1 5/22
Electrical ratings L6572
Table 1.
LVG
NC
OUT
HVG
BOOT
Pin description (continued)
Symbol Pin Description
10
Low-side transistor driver. The gate of an N-channel MOSFET or IGBT having an equivalent gate capacitance lower than 1 nF can be directly connected to this pin.
11 Unconnected pin for creepage purpose
12
13
14
Reference voltage of the floating gate driver. To be connected to the middle point of the half-bridge.
High-side transistor driver. The gate of an N-channel MOSFET or IGBT having an equivalent gate capacitance lower than 1 nF can be directly connected to this pin.
Supply voltage of the floating gate driver. A ceramic bootstrap capacitor must be placed between this pin and OUT pin
Table 2.
Symbol
Absolute maximum ratings
Parameter Value
V
S
VRDT
VRPH
VRNO
VRPB
VRCL
VSENSE
VLVG
VOUT
VHVG
Supply voltage
Voltage control resistor
Sense input voltage
Low-side switch gate output
High-side switch source output
High-side switch gate output
VBOOT dVOUT/dt
ITSD
(1)
Floating supply voltage
VBOOT/OUT Floating supply vs out voltage dVBOOT/dt VBOOT slew rate (repetitive)
VOUT slew rate (repetitive)
Supply current tsd-function
1.
The device has an internal Zener clamp between TSD and GND (typical 12.8 V)
15
5
±10
VS
-2,5 to VBOOT - VS
-2,5 to VBOOT - VS
580
VS
± 50
± 50
1,5
Unit
V
V
V
V
V/ns
V/ns mA
V
V
V
V
6/22 Doc ID 023882 Rev 1
L6572 Electrical ratings
Table 3.
Symbol
Recommended operating conditions
Parameter Min.
Max.
Unit
V
S
V
BOOT
V
OUT
V
NO
, V
DO
VPH
(1)
Supply voltage
Floating supply voltage
High-side switch source output
Voltages at pins Rno, Rdo
Voltage on pin RPH
12
-
-1
0.3
0.3
15
500
VBOOT-VS
4.8
V
V
V
1.
No external circuitry has to force any voltage on the pin RPH while the undervoltage lockout is activated.
V
V
Table 4.
Symbol
R thj-amb
T
STG
T
J
T
AMB
Thermal characteristics
Parameter
Max. thermal resistance junction-ambient
Storage temperature
Junction temperature
Ambient temperature (operative)
Value
120
-40 to 150
-40 to 150
-40 to 130
Unit
°C/W
°C
°C
°C
Doc ID 023882 Rev 1 7/22
Electrical characteristics L6572
8/22
(V
S
= 14.4 V, V
BOOT
- V out
= 14.4 V, T
AMB
= 25 °C, unless otherwise specified)
Table 5.
Symbol
Electrical characteristics
Parameter Test condition Min.
Typ.
Max.
Unit
V
SUVP
V
S
turn-ON threshold
V
SUVN
V
S
turn-OFF threshold
V
SUVH
V
S
hysteresis
I
SU
I q
Startup current
I
BOOTLK
BOOT pin leakage current
I
OUTLK
OUT pin leakage current
I
HVG SO
High-side driver source current
I
HVG SI
High-side driver sink current
I
LVG SO
Low-side driver source current
Low-side driver sink current I
LVG SI t
DT
Programmable deadtime t t t t
DT t
DT f
CL f
CL f
CL
T1/2on
T1/2on
T1/2on
XPB t
Minimum deadtime
Maximum deadtime
Frequency clock generator
Minimum frequency
Maximum frequency
Time with T1/2 switched on during preheating phase
Time with T1/2 switched on during normal operation
Time with T1/2 switched on during dimmed operation
XPB = t
T1/2on
T1/2on
(nom)
(powerb) /
10.1
7.3
2.7
11
8
3
11.9
8.7
3.3
V
V
V
V
S
< V
SUVP
160 250 µA
V
S
> V
SUVP
1 2 mA
V
BOOT
= 580 V 5 µA
V
OUT
= 562 V
V
HVG
- V
OUT
= 5 V 20 40
5 µA mA
V
HVG
- V
OUT
= 5 V
V
LVG
= 5 V
40
20
50
40 mA mA
V
LVG
= 5 V
R
DT
= 27 k Ω
40
1.95
R
DT
= 14 k
Ω
,
(1)
1
R
DT
= 40 k Ω ,
(1)
R
CL
= 47 k
Ω
72
R
CL
= 220 k Ω ,
(1)
12
50
2.50
90
3.05
5
108 mA
µs
µs
µs kHz kHz
R
CL
= 22 k Ω ,
(1)
R
PH
= 20 k Ω , R
DT
= 27 k
Ω
testing signal: test
A
3.60
4.17
250
4.70
kHz
µs
RNO = 27 k
Ω
, R
DT
=
27 k Ω testing signal: test B
6.40
7.50
8.40
µs
RDO = 27 k Ω , R
DT
=
27 k
Ω
testing signal: test B
RNO = 27 k
Ω
, R
DT
=
27 k Ω NO: test. signal: test B PB: test. signal: test C
6.40
1.24
7.50
1.34
8.40
1.42
µs tdisc
VZVS
Time to activate UVLO when
VSENSE = VZVS
ZVS threshold referred to SENSE pin
V
LVG
(1)
= V
S
10
330
20
385
30
440
µs mV
Doc ID 023882 Rev 1
L6572 Electrical characteristics
Table 5.
Symbol
Electrical characteristics (continued)
Parameter Test condition Min.
Typ.
Max.
Unit
TPB
Temperature threshold for powerboost activation
VTSD VTSD low voltage threshold
(1)
VTSD-Z Zener voltage on TSD pin ITSD = 600 µA
ITSD Current consumption TSD-function VTSD = 11 V
(2)
64
5.5
11.5
80
6.2
12.8
106
6.9
14.0
°C
V
V
30 40 50 µA
1.
Guaranteed by design.
2.
For a correct operation of the TSD function, the internal clamping diode has always to be turned on with the minimum supply voltage of the device.
Figure 4.
Test signal
HVG
LVG
tT1/2on
S EN S E
Vm t
DT
Aint
T
AM14 88 4v1 where:
●
●
●
Test A: starting voltage Vm = ± 465 mV, half period T = 6,67 μ s (f = 75 kHz; t
DT
μ s)
= 2,5
Test B: starting voltage Vm = ± 340 mV, half period T = 10,0
μ s (f = 50 kHz; t
DT
μ s)
= 2,5
Test C: starting voltage Vm = ± 340 mV, half period T = 12,5 μ s (f = 40 kHz; t
DT
μ s)
= 2,5
● T measured from the falling edge of HVG (LVG) to the falling edge of LVG (HVG).
Doc ID 023882 Rev 1 9/22
Functional description L6572
5.1 Signal processing block
The resonant current is detected with a shunt resistor which delivers a voltage signal to the
SENSE pin that is related to the GND pin.
Voltages at the SENSE pin amount to approx. 400 mV
(rms)
during normal operation respectively up to 10 V
(peak)
during ignition.
An overriding of the amplifier is given by sense voltages above ± 4.5 V.
This block provides the lamp current regulation. It consists of one integrator that loads an internal capacity (C int
) with a current that is directly proportional (factor: Rint1) to the signal at the sense input. The output of the integrator is (T1/2 stands for "LVG or HVG MOSFET"):
Equation 1
V int
=
R int
⋅ C int
⋅
∫
τ
0
V
SENSE t d t
(t = 0: T1/2 switched on; t = τ : T1/2 switched off).
The output signal of the integrator V int
is compared to the rated value (rated resonant current) programmed by RNO, RPH or RDO depending on the operational phase; the relevant comparator triggers the output stage block that switches off the current conducting power transistor.
The internal capacitor C int
is reset during the deadtime of the half-bridge (programmed by
RDT).
Thanks to the implemented ZVS control function, the conducting transistor is switched off at the latest when the resonant current changes its direction. Therefore, the half-bridge operates in the inductive region of the resonance characteristics of the ballast. In the worst case, working close to the pole frequency is allowed.
10/22
The ballast operates the lamps with nominal or reduced light output. A change between these two operation modes is achieved by disconnecting the line voltage for a time t < tTSD.
An internal binary information cell changes its state at the end of every preheating phase.
Depending on the state of this cell, the reduced or the nominal rated resonant current is given to the current regulation unit in order to operate the lamp with nominal or reduced light output.
Doc ID 023882 Rev 1
L6572
5.5
Functional description
The internal information cell is provided with the structure embedded in TSD pin and is able to keep its state as long as the voltage on this pin is above VTSD. When the voltage on the
TSD pin decreases below VTSD before the ballast is reconnected to the mains, the information cell is set to a state that leads to nominal light output of the lamp when the lamp is reconnected to the line voltage next time.
The time tTSD is defined by the voltage of the half-bridge when the oscillation stops, the current consumption (ITSD) of the TSD-pin and the resistor RA. Decreasing the time, tTSD may be achieved by connecting a resistor RB between the TSD pin and GND. (see
When the lamp is operated with reduced light output, the thermal powerboost time (see
) is shortened to 1022 period times of the clock generator in any case.
If the voltage on the TSD pin is kept below 0.5 V until the lamp has ignited, a change between normal operation mode and dimmed operation mode can be achieved by every transition of the voltage on the TSD pin while the lamp is burning: a voltage VTSD < 0.5 V leads to the normal operation, a voltage VTSD > 6.2 V (typ.) leads to the dimmed operation.
Steady-state voltages between 0.5 V and 6.2 V (typ.) on the TSD pin have to be avoided.
The current consumption of the TSD pin is controlled by design with an internal bias circuit that has a compensated temperature behavior.
The two-step dimming function can be deactivated by connecting the TSD pin to GND. In this case, the lamp is always operated with nominal light output.
Rated current generation
A reference current is used to feed the external resistors RPH, RNO and RDO. The voltages formed across these resistors are converted into internal rated voltage for integrator's comparator during each operation phases of the ballast (see
In order to compensate both the tolerances and the temperature variations of such a reference current, it is matched with the current used to charge the integrating capacitance
C int
. As a result, the obtained lamp current has the same tolerance as the external programming resistors even if the relevant rated voltages have noticeable variations.
During the preheating phase, the rated resonant current is defined by the external resistor
RPH.
The length of the preheating phase is defined by the duration of 40960 period times of the clock generator (a frequency fCL=100 kHz results in a duration of the preheating phase of
410 ms).
During the ignition phase, the rated resonant current increases from the preheating level to a level that ensures an operation of the half-bridge very close to the pole frequency of the resonant lamp circuit.
This increase is internally reached with a ramp composed by 31 steps given by the D/Aconverter block. In the first half of the ramp, height out of the ramp steps are smaller than those in the second half of the ramp. The length of each step is defined by the duration of
512 half waves of the resonant current. The last step of the ramp is reached after 15872 half waves (512 x 31).
The end of the ignition phase is reached only when the ignition recognition unit delivers a
). In this case, the ignition phase is ended and the rated resonant
Doc ID 023882 Rev 1 11/22
Functional description L6572 current is set to the powerboost level. Otherwise, the ZVS control prevents the half-bridge from operating below resonance. This condition does not lead to a latched turn-off.
During the powerboost phase, the current defined by the voltage across the RNO resistor is internally increased by the fixed ratio XPB. During the first half of the powerboost phase, the rated resonant current remains constant at the defined level, while during the second half, the rated current decreases in 15 equal steps up to the value of the normal lamp operation.
The length of the powerboost phase is roughly defined by the duration of 4063232 period times of the clock generator. There are 2097152 period times for the constant powerboost level. The decrease to the normal operation level takes place in equal steps with a length of
131072 period times of the clock generator per step.
The duration of the powerboost phase is shortened to 1022 period times of the clock generator when the lamp is already warm or when operated with reduced light output.
During normal operation, two possible rated resonant currents can be achieved related to the output signal of the two-step dimming unit. During the operation of the lamp with nominal light output, the nominal rated value is defined by the external resistor RNO. When operating the lamp with reduced light output, the reduced rated value is defined by the external resistor RDO.
The ratio between both possible rated values of the resonant current leading to reduced or nominal light output is defined by the ratio RNO/RDO.
A cold lamp emits a lower light level even when driven by a correct rated current. To speed up the lamp heating, a higher current is applied during few seconds of nominal operation
(thermal powerboost). The junction-temperature of the device is measured: if it is above
TPB the powerboost phase is entered as described in
directly operated with nominal light output.
The output stage processes the trigger signals from the current regulation unit, the ignition recognition unit and the UVLO block and controls the high-side and low-side driver.
Corresponding with the UVLO function the output stage controls the startup of the device.
The deadtime of the half-bridge is programmed by the external resistor RDT and it is equal for both high-side and low-side driver. It is adjustable between 1 μ s and 5 μ s. A minimum deadtime that avoids cross conduction of the power transistors is ensured by a minimum resistance of the external resistor RDT.
The deadtime generator delays the switch on both of power transistors, while the switch off signal from the output stage runs immediately to the drivers.
12/22 Doc ID 023882 Rev 1
L6572 Functional description
After the turn-on of the ballast, the UVLO is activated until the supply voltage exceeds the specified turn-on threshold voltage VSUVP.
While loading the blocking capacitor after power on, the low-side transistor has to be turned on to charge the bootstrap capacitor before the high-side transistor is switched on the first time.
When the supply voltage falls below the VSUVN threshold the device waits for the condition
"activated LVG and deactivated HVG". The UVLO is activated with a delay time of 1.3
μ s after this condition comes true.
Moreover, a logic UVLO is activated in order to restart the device with the preheating phase when no resonant current is sensed in a period of tdisc.
During the logic UVLO, all logic blocks of the device are reset, but the current references and internal regulators are still on.
The voltage reference delivers a reference signal with a very small tolerance (band gap).
This unit is activated at the beginning of the ignition phase (see
synchronization pulse to the clock generator every time either the current control units are triggered by the signal processing unit or ZVS control turns on the relevant transistor. Being the half of the clock frequency programmed to be lower than resonance frequency, the clock period during the ignition phase is forced to be shorter than the programmed one.
Once the lamp ignites the integral of the operating current, it takes longer time to reach the rated value and the clock period reaches the programmed value.
In this case, the ignition phase is terminated, the ignition recognition unit is deactivated and the rated resonant current is set on the powerboost level.
On the contrary, the end of ignition is not detected and both the half-bridge and the clock remain locked to resonance frequency by ZVS control unit.
This high frequency oscillator provides with time bases for the IC during the various operating phases.
During the preheating phase it delivers a fixed time base for the counter. At the beginning of the ignition phase when the ignition recognition unit is active, the oscillator is synchronized with the output stage. Therefore the timing element of the oscillator is reset with the frequency of the output stage. If one half cycle, of period time of the output stage given by the current regulator exceeds the fixed period time of the clock generator, a trigger signal is formed and given to the output stage and the counter. This leads to a defined termination of the ignition phase. After setting the rated resonant current to the powerboost level, the clock generator continues in a self-oscillating way until it is stopped by the counter at the end of the powerboost phase.
Doc ID 023882 Rev 1 13/22
Functional description L6572
The frequency of the clock generator is fixed with the external resistor RCL, increasing the resistance of RCL and reducing fCL.
5.13 Counter
The counter is formed as binary counter. A digital network generates signals that activate the ignition recognition unit and control the D/A converter and the rated current generation unit. The counter is reset by the UVLO unit.
The D/A converter forms the ramps for the rated resonant current during the ignition phase and the powerboost phase.
Figure 5.
Operating phases
ω
Ire
s
Ignition
Recognition
Prehe
a
t - ph
as
e Ignition Power
b
oo
s
t Norm
a
l
AM14 88 5v1
14/22 Doc ID 023882 Rev 1
L6572 Functional description
Figure 6.
Ignition recognition a ) r a ted re s on a nt c u rrent b )
U(C) clock-gener a tor free-r u nning c) o u tp u t clock-gener a tor d) o u tp u t s t a ge e) f) g) o u tp u t c u rr.-reg.
o u tp u t "A" co u nter o u tp u t "B" co u nter prehe a t-ph as e s ynchronized ignition-ph as e ignition
Figure 7.
Two-step dimming a ) Line volt a ge
(on / off) b ) Light o u tp u t t free -r u nning norm a l oper a tion / power b oo s t-ph as e t t t t t t
AM14 88 6v1 t t t c) Light level
Flip-Flop d) Re s et
Light level
Flip- Flop e) Volt a ge
T S D- pin f) Su pply -
Volt a ge V s
V thre s hold t
Doc ID 023882 Rev 1 t t
AM14 88 7v1
15/22
Application information L6572
6.2
The L6572 is primarily intended to accurately drive, with a minimum number of external components, integrated compact fluorescent lamps. Its particular current control method allows a noticeable extension of lamp lifetime and a higher light quality compared to that obtainable by self oscillating ballasts. Also, the operation of the application during normal operation is very similar to the above mentioned ballasts, but with an improved repeatability
of the lamp parameters (see Figure 2
).
The same advantages can be exploited by separately controlled fluorescent lamp applications, especially CFLs up to 26 W.
Using further external components, higher power ratings are also reachable.
Furthermore, dimming functionality, in particular two-step dimming, helps to implement variable light sources.
Designing a simple fixed power CFLi application using the
L6572
The first step to follow is to define the clock frequency: it can be calculated in order to fit the preheating time requirements. The following equations give the relationships between the typical value of clock period, the preheating time and RCL value.
●
●
RCL k Ω
TCL
μ s
≅
≅ 0.10327
⋅ T
PH m s
0.2364
⋅ RCL k
Ω
●
FCL
KHZ
≅
TCL
μ s
Given the clock frequency, the value of the resonance frequency of the LC cell must be selected higher than the half of the clock frequency in all possible conditions. Otherwise the ignition recognition circuitry may operate incorrectly.
● F
Res
≅
2 π ⋅ L ⋅ C
The range of frequencies related to nominal operation and to the preheating phase can be now selected respectively below and above F
Res
. Considering the operating frequency ranges and the lamp parameters, the value for resonant components can now be selected: different calculation approaches can be adopted.The value of the sense resistor has to be chosen in order to guarantee a sufficient signal level for the ZCD function: at minimum the peak of the resonant current in every condition must be above VZVS. As the reference current of programming resistors is matched the integrator reference current, a relation between the programming resistor value and the obtained voltage*time area (VTA) can be expressed. These relations can be used to evaluate a first tentative value for the programming resistors RPH, RNO and RDO. A subsequent iterative verification on the real project is usually required: in fact, the value of the integral is highly dependent on the real shape of the sense voltage. Deadtime duration somewhat affects the result of the integration as well.
16/22 Doc ID 023882 Rev 1
L6572 Application information
In ideal conditions the resonant current is almost sinusoidal, having a phase term ( Θ ) in respect to the voltage applied by the half-bridge. Generally, it can be written that:
Equation 2
I res t = I 2 ⋅ sin ( 2 π ⋅ f sw
⋅ t – θ )
The term "
Θ
" is here expressed in radiant, but it can be expressed in terms of time.
Moreover, it is always positive as long as the operating point is above the resonance.
Equation 3
I res t = I 2 ⋅ sin ( 2 π ⋅ f sw
⋅ t – 2 π ⋅ f sw
– θ )
The following figure illustrates the case of operation at resonance (red line), with a small phase, usually seen during normal operation (blue line) and finally during preheating (green line) where a 90° phase is experienced.
Figure 8.
Operating phases
The voltage at SENSE pin has the same shape as the resonant current and is rectified and then integrated by the current signal processor of the L6572. It can be easily demonstrated that the integral of the rectified waveform does not depend on the initial phase (
Θ
) but only on the waveform amplitude and frequency.
Equation 4
A =
∫
T1/2on
V
SENSE d t ≅
2 ⋅ I ⋅ R
-----------------------------------------------------------------
2 π ⋅ f
SW
As previously discussed, the non linear behavior of the glow discharge characteristics makes this result quite approximate because the resonant current is not exactly sinusoidal.
Nevertheless it is more accurate during the preheating.
Therefore, suggested starting values for the application dimension are around:
Doc ID 023882 Rev 1 17/22
Application information L6572
Equation 5
R ph k Ω)
≅
R no k Ω)
≅
A ph ( μ V × s )
⋅
A no ( μ V × s )
⋅
20
20
The second relation is also valid for dimmed operations.
A small capacitor placed in parallel with Rph (around 10 pF), helps to improve the preheating phase.
Deadtime can also be fixed during this step.
A useful relationship to find the right value of Rdt, expressed in k
Ω
, given the value of the selected deadtime, expressed in µs is:
Equation 6
R dt
= 10.8
⋅
T dt
Being a non dimmable application, the RDO pin and TSD pin have to be connected to ground. To be noted that CFLi applications up to 25 W are equipped by MOSFETs having small gate charges: therefore no gate resistance is required and the gate pin of the
MOSFETs can be directly connected to driver output.
6.3 Two-step dimmable CFLi application
Once a fixed power application is designed, the dimmability feature can be added by activating TSD pin and RDO.
The first pin is intended to sense the interval between AC turn-off and on, usually using only
Ra. As soon as the AC line is turned off, resonant current decreases and consequently the half-bridge stops switching due to Tdis function. Once this occurs the supply voltage drops below turn-off threshold.
The present voltage across the half-bridge is decreasing, but it is greater than zero keeping the TSD structure well supplied thanks to Ra. The smaller the Ra, the longer the time the
TSD voltage remains above the dimming enable threshold and the slower the required turnoff turn-on action to enable dimming.
If, during the turn-off interval TSD drops below the threshold, the internal memory cell is reset, otherwise it remains in its previous state.
At subsequent turn-on, after preheating, this state is checked to determine which power level is required.
The dimmed area is selected by Rdo: its value is expected to be lower or equal to Rno.
Frequently, the starting voltage across the half-bridge has a wide voltage ripple, and its nominal value is variable as well. For these reasons, a precise design guidance of the selection of Ra cannot be provided. The quickest way to proceed is represented by direct measurements on the real application. Selection of Rdo can be done using the same approach used to determine Rno.
18/22 Doc ID 023882 Rev 1
L6572
7 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
Table 6.
SO-14 mechanical data mm
Dim.
Min.
Typ.
A 1.35
A1 0.10
A2 1.10
B 0.33
C 0.19
D 8.55
E 3.80
e 1.27
H 5.80
h 0.25
L 0.40
K 0 e ddd
0.40
Max.
1.75
0.25
1.65
0.51
0.25
8.75
4.00
6.20
0.50
1.27
8
0.10
Doc ID 023882 Rev 1 19/22
Package mechanical data
Figure 9.
SO-14 package dimensions
L6572
20/22 Doc ID 023882 Rev 1
0016019_E
L6572
Table 7.
Date
31-Oct-2012
Document revision history
Revision
1 Initial release.
Changes
Revision history
Doc ID 023882 Rev 1 21/22
L6572
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