STL20N60M2-EP
Datasheet
N-channel 600 V, 0.240 Ω typ., 9 A MDmesh™ M2 EP
Power MOSFET in a PowerFLAT™ 5x6 HV package
1
2
3
4
PowerFLAT™ 5x6 HV
D(5, 6, 7, 8)
Features
Order code
STL20N60M2-EP
V
DS
600 V
• Extremely low gate charge
• Excellent output capacitance (C
OSS
) profile
• Very low turn-off switching losses
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
0.307 Ω
I
D
9 A
8 7 6 5
G(4)
Applications
• Switching applications
• Tailored for very high frequency converters (f > 150 kHz)
S(1, 2, 3)
1 2 3 4
Top View
AM15540v1
Description
This device is an N-channel Power MOSFET developed using MDmesh™
M2 enhanced performance (EP) technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance, optimized switching characteristics with very low turn-off switching losses, rendering it suitable for the most demanding very high frequency converters.
Product status link
STL20N60M2-EP
Product summary
Order code STL20N60M2-EP
Marking
Package
Packing
20N60M2E
PowerFLAT™ 5x6 HV
Tape and reel
DS11785 - Rev 2 - April 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STL20N60M2-EP
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
I
DM
P
I
E
I
I
GS
D
D
(1)
TOT
AR
AS
Parameter
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed)
Total dissipation at T case
= 25 °C
Avalanche current, repetitive or not repetitive
(pulse width limited by T jmax
)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
; V
DD
= 50 V)
Peak diode recovery voltage slope dv/dt
(2)
dv/dt
(3)
T stg
T j
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 9 A, di/dt=400 A/μs; V
DS
peak ≤ V
(BR)DSS
, V
DD
= 400 V.
3. V
DS
≤ 480 V.
Table 2. Thermal data
Symbol Parameter
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on a 1-inch² FR-4, 2 Oz copper board.
Value
±25
9
5.5
34
57
2.7
138
15
50
-55 to 150
Unit
V
A
A
W
A mJ
V/ns
°C
Value
2.2
59
Unit
°C/W
DS11785 - Rev 2 page 2/16
2
STL20N60M2-EP
Electrical characteristics
Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Table 3. Static
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
V
GS
Test conditions
= 0 V, I
D
= 1 mA
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Zero gate voltage drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source onresistance
V
GS
= 0 V, V
DS
= 600 V
V
T
GS
= 0 V, V
DS
= 600 V, case
= 125 °C
(1)
V
V
V
DS
DS
GS
1. Defined by design, not subject to production test.
= 0 V, V
GS
= V
GS
, I
D
= 10 V, I
= ±25 V
= 250 µA
D
= 4.5 A
Min.
600
Typ.
3.25
4
0.240
Max.
Unit
V
1
100
±10
4.75
0.307
µA
µA
V
Ω
Table 4. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
G
Q g
Q gs
Q gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
V
Equivalent output capacitance V
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
DS
DD
10 V (see
Test conditions
= 100 V, f = 1 MHz, V
= 0 to 480 V, V f = 1 MHz, I
D
= 0 A
= 480 V, I
D
GS
= 0 V
=13 A, V
GS
)
= 0 to
Figure 15. Test circuit for gate charge behavior
GS
= 0 V
Min.
-
-
-
-
-
-
-
-
Typ.
787
50
1.2
89
5.9
22
3.5
10.5
Max.
-
-
-
-
-
-
-
-
Unit pF pF
Ω nC
1. C oss eq
. is defined as a constant equivalent capacitance giving the same charging time as C oss to 80% V
DSS
.
when V
DS
increases from 0
Symbol
E off
Parameter
Turn-off energy (from 90%
V
GS
to 0% I
D
)
Table 5. Switching energy
Test conditions
V
DD
V
GS
= 400 V, I
= 10 V
D
= 2 A, R
G
= 4.7 Ω,
V
DD
= 400 V, I
D
= 5 A, R
G
V
GS
= 10 V
= 4.7 Ω,
Min.
-
-
Typ.
7.2
20.4
Max.
-
-
Unit
μJ
μJ
DS11785 - Rev 2 page 3/16
DS11785 - Rev 2
STL20N60M2-EP
Electrical characteristics
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 300 V, I
D
= 6.5 A, R
G
= 4.7 Ω,
V
GS
= 10 V (see Figure 14. Test circuit for resistive load switching times and Figure 19. Switching time waveform
)
Min.
-
-
-
-
Typ.
10.5
5.2
41
8
Max.
-
-
-
-
Unit ns
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
I
V
GS
SD
SD
Test conditions
= 0 V, I
= 13 A, di/dt = 100 A/µs,
V
DD
= 60 V (see Figure 16. Test circuit for inductive load switching and diode recovery times )
= 13 A, di/dt = 100 A/µs,
V
DD
= 60 V, (see
Figure 16. Test circuit for inductive load switching and diode recovery times )
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
SD
= 9 A
-
-
-
-
-
-
Min.
-
-
-
230
2.3
20
287
2.9
20.2
Typ.
Max.
9
34
1.6
ns
µC
A ns
µC
A
Unit
A
A
V page 4/16
STL20N60M2-EP
Electrical characteristics (curves)
2.1
I
D
(A)
Electrical characteristics (curves)
Figure 1. Safe operating area
GADG210320181119SOA
10 1
10 0
10 -1
Operation in this area is limited by R
DS(on)
10 0 10 1
V
GS
= 10 V
T j
T c
≤ 150 °C
= 25 °C single pulse
10 2 t t p
= 10µs t p
= 100µs t p
= 1ms p
= 10ms
V
DS
(V)
10 -2
10 -1
20
15
10
5
0
0
I
D
(A)
30
Figure 3. Output characteristics
GIPG180220160958OCH
V
GS
= 8, 9, 10 V
V
GS
= 7 V
25
4 8 12
V
GS
= 6 V
V
GS
= 5 V
16 V
DS
(V)
4
2
0
0
8
6
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
10
V
DS
GIPG210120161606QVG V
DS
(V)
600
V
DD
= 480 V,
I
D
= 13 A
500
5 10 15 20 25
400
300
200
100
Q
0 g
(nC)
K
Figure 2. Thermal impedance
ZthPowerFlat_5x6_27_case d =0.5
10 -1 d =0.2
d =0.1
0.05
0.02
0.01
c
10 -2
Single pulse
10 -3
10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t p (s)
I
D
(A)
30
Figure 4. Transfer characteristics
GIPG090220161518TCH
15
10
25
20
5
0
3 4
V
DS
= 17 V
5 6 7 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
GADG210320181529RID
V
GS
= 10 V
0.26
0.25
0.24
0.23
0.22
0 2 4 6 8 I
D
(A)
DS11785 - Rev 2 page 5/16
STL20N60M2-EP
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG210120161637CVR
Ci ss
1000
100
C oss
10
C rss
1
0.1
1 10 100 V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
GIPG020220161245RON
2.2
V
GS
= 10 V
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 11. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GIPG020220161300BDV
1.08
I
D = 1 mA
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T j
(°C)
Figure 8. Output capacitance stored energy
E
OSS
(µJ)
6
GIPG210120161026EOS
3
2
5
4
1
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 10. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG020220161244VTH
1.1
I
D
= 250 µA
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T j
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1
GADG210320181530SDF
T j
= -50 °C
0.9
0.8
0.7
0.6
0.5
0 2 4
T j
= 25 °C
T j
= 150 °C
6 8 I
SD
(A)
DS11785 - Rev 2 page 6/16
Figure 13. Turn-off switching energy vs drain current
Eoff [µJ] GIPG030220161548SDF
20
15
30
25
V
R
V
DD
G
GS
= 400 V
= 4.7 Ω
= 10 V
10
5
0
0 1 2 3 4 5 6 7 Id [A]
STL20N60M2-EP
Electrical characteristics (curves)
DS11785 - Rev 2 page 7/16
STL20N60M2-EP
Test circuits
3
Test circuits
Figure 14. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 16. Test circuit for inductive load switching and diode recovery times
Figure 15. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 17. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 18. Unclamped inductive waveform
V (BR)DSS
V
D
I DM
I D
V DD V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
Figure 19. Switching time waveform
0 t d(on) t on t r
90%
10%
V
GS
V
DS
90% t d(off) t off t f
90%
10%
0
10%
AM01473v1
DS11785 - Rev 2 page 8/16
4
STL20N60M2-EP
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS11785 - Rev 2 page 9/16
4.1
STL20N60M2-EP
PowerFLAT™ 5x6 HV package information
PowerFLAT™ 5x6 HV package information
Figure 20. PowerFLAT™ 5x6 HV package outline
DS11785 - Rev 2
8368143_Rev_3 page 10/16
DS11785 - Rev 2
STL20N60M2-EP
PowerFLAT™ 5x6 HV package information
Dim.
E
E2
D2
D4 e
L
K
A
A1
A2 b
C
D
Table 8. PowerFLAT™ 5x6 HV mechanical data mm
Typ.
Min.
0.80
0.02
0.25
0.30
5.8
5.10
6.05
3.10
4.30
4.8
0.50
1.90
4.40
5
1.27
0.55
2.00
6
5.20
6.15
3.20
Figure 21. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm)
Max.
1.00
0.05
0.50
6.1
5.30
6.25
3.30
4.50
5.1
0.60
2.10
8368143_Rev_3_footprint page 11/16
4.2
STL20N60M2-EP
PowerFLAT™ 5x6 packing information
PowerFLAT™ 5x6 packing information
Figure 22. PowerFLAT™ 5x6 tape (dimensions are in mm)
Pin 1 identification
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
8234350_Tape_rev_C
Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape
DS11785 - Rev 2 page 12/16
Figure 24. PowerFLAT™ 5x6 reel
STL20N60M2-EP
PowerFLAT™ 5x6 packing information
DS11785 - Rev 2 page 13/16
STL20N60M2-EP
Revision history
Table 9. Document revision history
Date
10-Aug-2016
11-Apr-2018
Revision Changes
1 First release.
2
Removed maturity status indication from cover page. The document status is production data.
Updated Section 1 Electrical ratings and
Section 2 Electrical characteristics
.
Added Section 2.1 Electrical characteristics (curves)
.
Minor text changes.
DS11785 - Rev 2 page 14/16
STL20N60M2-EP
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1
PowerFLAT™ 5x6 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
PowerFLAT™ 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DS11785 - Rev 2 page 15/16
STL20N60M2-EP
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DS11785 - Rev 2 page 16/16
