STMicroelectronics L6228 Datasheet
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L6228
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Features
Operating supply voltage from 8 to 52 V
2.8 A output peak current (1.4 A RMS)
R
DS(ON)
0.73 typ. value at T j
= 25 °C
Operating frequency up to 100 KHz
Non-dissipative overcurrent protection
Dual independent constant t
OFF controllers
PWM current
Fast/slow decay mode selection
Fast decay quasi-synchronous rectification
DMOS driver for bipolar stepper motor
Datasheet
-
production data
Decoding logic for stepper motor full and half step drive
Cross conduction protection
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Application
Bipolar stepper motor
Description
The L6228 device is a DMOS fully integrated stepper motor driver with non-dissipative overcurrent protection, realized in BCD technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a two phase bipolar stepper motor including: a dual DMOS full bridge, the constant off time PWM current controller that performs the chopping regulation and the phase sequence generator, that generates the stepping sequence. Available in PowerSO36 and SO24
(20 + 2 + 2) packages, the L6228 device features a non-dissipative overcurrent protection on the high-side power MOSFETs and thermal shutdown.
October 2018
This is information on a product in full production.
DocID9454 Rev 3 1/34 www.st.com
Contents
Contents
L6228
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Normal drive mode (full step two phase on) . . . . . . . . . . . . . . . . . . . . . . . 20
Wave drive mode (full step one phase on) . . . . . . . . . . . . . . . . . . . . . . . . 20
Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 26
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/34 DocID9454 Rev 3
L6228 Block diagram
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DocID9454 Rev 3 3/34
34
Maximum ratings L6228
Symbol
Table 1. Absolute maximum ratings
Parameter
I
V
S
S(peak)
Supply voltage
V
OD
Differential voltage between VS
A
SENSE
A
and VS
B
, OUT1
B
, OUT1
A
, OUT2
A
,
, OUT2
B
, SENSE
B
Bootstrap peak voltage V
BOOT
V
IN
, V
EN
V
REFA
,
V
REFB
V
RCA,
V
RCB
V
SENSEA,
V
SENSEB
Input and enable voltage range
Voltage range at pins V
REFA and V
REFB
Voltage range at pins RC
A
and RC
B
Voltage range at pins SENSE
A
and SENSE
B
Pulsed supply current (for each V
S
pin), internally limited by the overcurrent protection
I
S
T stg
, T
OP
RMS supply current (for each V
S
pin)
Storage and operating temperature range
Test conditions
V
SA
= V
SB
= V
S
V
SA
= V
SB
= V
S
= 60 V;
V
SENSEA
= V
SENSEB
= GND
V
SA
= V
SB
= V
S
-
-
-
-
V
SA
= V
SB
= V
S
; t
PULSE
< 1ms
V
SA
= V
SB
= V
S
-
Value
60
60
V
S
+ 10
-0.3 to +7
-0.3 to +7
Unit
V
V
V
V
V
-0.3 to +7
-1 to +4
3.55
1.4
-40 to 150
V
V
A
A
C
Symbol
Table 2. Recommended operating conditions
Parameter
V
S
Supply voltage
V
OD
Differential voltage between
VS
A
, OUT1
A
, OUT2
A
, SENSE
A
and
VS
B
, OUT1
B
, OUT2
B
, SENSE
B
V
REFA
,
V
REFB
Voltage range at pins V
REFA and V
REFB
V
SENSEA,
V
SENSEB
Voltage range at pins SENSE
A
and SENSE
B
I
OUT f sw
RMS output current
Switching frequency
Test conditions
V
SA
= V
SB
= V
S
V
SA
= V
SB
= V
S
;
V
SENSEA
= V
SENSEB
-
(pulsed t
W
< t rr
)
(DC)
-
-
Min. Max. Unit
8 52 V
52 V
-0.1
-
-
-6
-1
5 V
6
1
V
V
1.4
A
100 KHz
4/34 DocID9454 Rev 3
L6228 Maximum ratings
Symbol
R th-j-pins
R th-j-case
Table 3. Thermal data
Description
Maximum thermal resistance junction pins
Maximum thermal resistance junction case
SO24
15
-
4. Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PowerSO36 Unit
-
2
R th-j-amb1
R th-j-amb1
Maximum thermal resistance junction ambient
Maximum thermal resistance junction ambient
(1)
(2)
55
-
-
36
R th-j-amb1
R th-j-amb2
Maximum thermal resistance junction ambient
Maximum thermal resistance junction ambient
(3)
(4)
-
78
16
63
1. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm 2
(with a thickness of 35 µm).
2. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm
2
(with a thickness of 35 µm).
3. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2
(with a thickness of 35 µm), 16 via holes and a ground layer.
C/W
C/W
C/W
C/W
C/W
C/W
DocID9454 Rev 3 5/34
34
Pin connections L6228
SO24
Figure 2. Pin connections (top view)
CLOCK
CW/CCW
SENSE
A
RC
A
OUT1
A
GND
GND
OUT1
B
RC
B
SENSE
B
VREF
B
HALF/FULL
8
9
10
11
5
6
7
12
1
2
3
4
D99IN1083
24
23
22
21
17
16
15
14
20
19
18
13
VREF
A
RESET
VCP
OUT2
A
VS
A
GND
GND
VS
B
OUT2
B
VBOOT
EN
CONTROL
RESET
VREF
A
CLOCK
CW/CCW
SENSE
A
RC
A
N.C.
OUT1
A
N.C.
N.C.
GND
GND
N.C.
N.C.
VS
A
OUT2
A
N.C.
VCP 7
8
9
10
11
12
1
2
3
4
5
6
13
14
15
16
17
18
D99IN1084
PowerSO36
(1)
30
29
28
27
26
25
36
35
34
33
32
31
24
23
22
21
20
19
VREF
B
SENSE
B
RC
B
N.C.
OUT1
B
N.C.
N.C.
GND
GND
N.C.
N.C.
VS
B
OUT2
B
N.C.
VBOOT
EN
CONTROL
HALF/FULL
1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Table 4. Pin description
Package
SO24
Pin no.
PowerSO36
Pin no.
Name Type
1
2
3
4
5
10
11
12
13
15
CLOCK
CW/CCW
SENSE
A
RC
A
OUT1
A
Function
Logic input
Logic input
Power supply
Step clock input. The state machine makes one step on each rising edge.
Selects the direction of the rotation. HIGH logic level sets clockwise direction, whereas LOW logic level sets counterclockwise direction.
If not used, it has to be connected to GND or +5 V.
Bridge A source pin. This pin must be connected to power ground through a sensing power resistor.
RC pin
Power output
RC network pin. A parallel RC network connected between this pin and ground sets the current controller
OFF-time of the bridge A.
Bridge A output 1.
6/34 DocID9454 Rev 3
L6228 Pin connections
Table 4. Pin description (continued)
Package
SO24 PowerSO36 Name Type Function
Pin no.
Pin no.
6, 7, 18, 19 1, 18, 19, 36
8
9
10
11
12
13
14
15
16
17
20
21
22
22
24
25
26
27
28
29
30
32
33
4
5
7
GND
OUT1
RC
B
SENSE
VREF
B
B
B
GND
Power output
RC pin
Power supply
Analog input
Ground terminals. In SO24 package, these pins are also used for heat dissipation toward the PCB. On
PowerSO36 package the slug is connected to these pins.
Bridge B output 1.
RC network pin. A parallel RC network connected between this pin and ground sets the current controller
OFF-time of the bridge B.
Bridge B source pin. This pin must be connected to power ground through a sensing power resistor.
Bridge B current controller reference voltage.
Do not leave this pin open or connected to GND.
HALF/FULL
CONTROL
EN
VBOOT
OUT2
VS
VS
B
A
OUT2
VCP
B
A
Logic input
Logic input
Logic input
(1)
Step mode selector. HIGH logic level sets HALF STEP mode, LOW logic level sets FULL STEP mode.
If not used, it has to be connected to GND or +5 V.
Decay mode selector. HIGH logic level sets SLOW
DECAY mode. LOW logic level sets FAST DECAY mode.
If not used, it has to be connected to GND or +5 V.
Chip enable. LOW logic level switches OFF all power
MOSFETs of both bridge A and bridge B. This pin is also connected to the collector of the overcurrent and thermal protection to implement overcurrent protection.
If not used, it has to be connected to +5 V through a resistor.
Bootstrap voltage needed for driving the upper power
MOSFETs of both bridge A and bridge B.
Supply voltage
Power output
Power supply
Power supply
Power output
Bridge B output 2.
Bridge B power supply voltage. It must be connected to the supply voltage together with pin VS
A
.
Bridge A power supply voltage. It must be connected to the supply voltage together with pin VS
B
.
Bridge A output 2.
Output Charge pump oscillator output.
DocID9454 Rev 3 7/34
34
Pin connections L6228
Table 4. Pin description (continued)
Package
SO24 PowerSO36 Name Type Function
Pin no.
Pin no.
23
24
8
9
RESET
VREF
A
Logic input
Analog input
Reset pin. LOW logic level restores the Home state
(state 1) on the phase sequence generator state machine.
If not used, it has to be connected to +5 V.
Bridge A current controller reference voltage.
Do not leave this pin open or connected to GND.
1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2 K - 180 K , recommended 100 K
8/34 DocID9454 Rev 3
L6228 Electrical characteristics
Symbol
V
Sth(ON)
V
Sth(OFF)
Turn-on threshold
Turn-off threshold
I
S
Table 5. Electrical characteristics
(T amb
= 25 °C, V s
= 48 V, unless otherwise specified)
Parameter Test Unit
Quiescent supply current
T j(OFF)
Thermal shutdown temperature
Output DMOS transistors
-
-
T j
All bridges OFF;
= -25 °C to 125 °C
(1)
-
5.8
6.3
6.8
5 5.5
6
-
5
165
10 mA
-
V
V
C
R
DS(ON)
I
DSS
High-side + low-side switch ON resistance
Leakage current
V
IL
V
IH
I
IL
I
IH
V th(ON)
V th(OFF)
V th(HYS)
Low level logic input voltage
High level logic input voltage
Low level logic input current
High level logic input current
Turn-on input threshold
Turn-off input threshold
Input threshold hysteresis
Switching characteristics t t t t
D(ON)EN
D(OFF)EN t
RISE t
FALL t
DCLK
CLK(min)L
CLK(min)H f
CLK
Enable to output turn-on delay time (2)
Enable to output turn-off delay time
(2)
Output rise time
(2)
Output fall time
(2)
Clock to output delay time
(3)
Minimum clock time
(4)
Minimum clock time (4)
Clock frequency
T j
= 25 °C
T j
= 125 °C
(1)
EN = low; OUT = V
S
EN = low; OUT = GND
Source drain diodes
V
SD t rr t fr
Forward ON voltage
Reverse recovery time
Forward recovery time
I
SD
= 1.4 A, EN = LOW
I f
= 1.4 A
-
Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
-
-
GND logic input voltage
7 V logic input voltage
-
-
-
-
-
-
-0.3
-
-
-
-0.3
2
-10
-
-
1.47
1.69
W
2.35
2.70
W
-
-
1.15
300
200
2
-
1.3
-
mA mA
V ns ns
-
-
-
0.8
7
-
10 µA
1.8
2.0
V
0.8
1.3
0.25
0.5
-
-
V
V
µA
V
V
I
I
LOAD
= 1.4 A, resistive load 500 650 800 ns
I
LOAD
= 1.4 A, resistive load 500 800 1000 ns
LOAD
= 1.4 A, resistive load 40 250 ns
250 ns
I
I
LOAD
= 1.4 A, resistive load 40
LOAD
= 1.4 A, resistive load -
-
-
-
-
2
-
-
-
-
1
1
µs
µs
µs
100 KHz
DocID9454 Rev 3 9/34
34
Electrical characteristics L6228
Table 5. Electrical characteristics
(T amb
= 25 °C, V s
= 48 V, unless otherwise specified) (continued)
Parameter Test Unit Symbol t
S(MIN) t
H(MIN) t
R(MIN) t
RCLK(MIN) t
DT f
CP
Minimum set-up time
Minimum hold time (5)
Minimum reset time
Deadtime protection
(5)
(5)
Minimum reset to clock delay time
Charge pump frequency
PWM comparator and monostable
(5)
-
-
-
-
-
T j
= -25 °C to 125 °C
(1)
-
-
-
-
0.5
-
-
-
-
-
1
0.6
1
1
1
1
µs
1 MHz
µs
µs
µs
µs
I
RCA,
I
RCB
V offset t
PROP t
BLANK t
ON(MIN) t
OFF
Source current at pins RC
A and RC
B
Offset voltage on sense comparator
Turn OFF propagation delay
(6)
Internal blanking time on SENSE pins
Minimum On time
PWM recirculation time
V
RCA
= V
V
REFA,
RCB
V
REFB
-
= 2.5 V
= 0.5 V
-
R
OFF
= 20 K C
OFF
= 1 nF
R
OFF
= 100 K C
OFF
= 1 nF -
-
-
-
-
I
BIAS
Input bias current at pins VREF
A
and VREF
B
Overcurrent protection t t
I
SOVER
R
OPDR
OCD(ON)
OCD(OFF)
Input supply overcurrent protection threshold
Open drain ON resistance
OCD turn-on delay time
OCD turn-off delay time
(7)
(7)
T j
= -25 °C to 125 °C
(1)
I = 4 mA
I = 4 mA; C
EN
< 100 pF
I = 4 mA; C
EN
< 100 pF
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See
Figure 3: Switching characteristic definition
.
3. See
Figure 4: Clock to output delay time .
4. See
Figure 5: Minimum timing definition; clock input
.
5. See
Figure 6: Minimum timing definition; logic inputs
.
6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
7. See
Figure 7: Overcurrent detection timing definition .
2
-
-
-
3.5
5.5
-
±5
500
1
2.5
13
61
-
2.8
40
200
100
-
3
-
-
-
-
-
10
3.55
60
-
mA mV ns
µs
µA
A
W ns ns
µs
µs
µs
10/34 DocID9454 Rev 3
L6228 Electrical characteristics
Figure 3. Switching characteristic definition
EN
V th(ON)
V th(OFF)
I
OUT
90%
10%
D01IN1316 t
FALL t
D(ON)EN t
RISE t t
D(OFF)EN
Figure 4. Clock to output delay time
CLOCK t
V th(ON) t
I
OUT
D01IN1317 t
DCLK
CLOCK
Figure 5. Minimum timing definition; clock input
V th(OFF)
V th(ON) t
CLK(MIN)L
V th(OFF) t
CLK(MIN)H
D01IN1318 t
DocID9454 Rev 3 11/34
34
Electrical characteristics
Figure 6. Minimum timing definition; logic inputs
CLOCK V th(ON)
LOGIC INPUTS t
S(MIN) t
H(MIN)
RESET
V th(OFF)
V th(ON) t
R(MIN)
D01IN1319 t
RCLK(MIN)
Figure 7. Overcurrent detection timing definition
I
OUT
I
SOVER
L6228
ON
BRIDGE
OFF
V
EN
90%
10% t
OCD(ON) t
OCD(OFF)
D02IN1399
12/34 DocID9454 Rev 3
L6228 Circuit description
5.1 Power stages and charge pump
The L6228device integrates two independent power MOS full bridges. Each power MOS has an R
DS(ON)
= 0.73 (typical value at 25 °C), with intrinsic fast freewheeling diode.
Switching patterns are generated by the PWM current controller and the phase sequence
). Cross conduction protection is achieved using a deadtime
(t
DT
= 1 s typical value) between the switch off and switch on of two power MOSFETs in one leg of a bridge.
Pins VS
A
and VS
B
MUST be connected together to the supply voltage V
S
. The device operates with a supply voltage in the range from 8 V to 52 V. It has to be noticed that the
R
DS(ON)
increases of some percents when the supply voltage is in the range from 8 V to 12 V.
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply voltage V
BOOT
is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in
Figure 8 . The oscillator output (VCP) is a square wave at 600 KHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in
.
Table 6. Charge pump external components values
Component Value
C
BOOT
C
P
R
P
D1
D2
220 nF
10 nF
100
1N4148
1N4148
Figure 8. Charge pump circuit
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DocID9454 Rev 3 13/34
34
Circuit description L6228
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS compatible
logic inputs. The internal structure is shown in Figure 9
. Typical value for turn-on and turn-off thresholds are respectively V th(ON)
= 1.8 V and V th(OFF )
= 1.3 V.
Pin EN (“Enable”) has identical input structure with the exception that the drain of the overcurrent and thermal protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving this pin. The EN input may be driven in one of two configurations as shown in
. If driven by an open drain
(collector) structure, a pull-up resistor R
EN
and a capacitor C
EN
are connected as shown in
. If the driver is a standard Push-Pull structure the resistor R
EN
and the capacitor
C
EN
are connected as shown in
. The resistor R from 2.2 K to 180 K . Recommended values for R
EN
should be chosen in the range
EN
and C
EN
are respectively 100 K and
5.6 nF. More information on selecting the values is found in
Section 7.5: Non-dissipative overcurrent protection on page 21 .
Figure 9. Logic inputs internal structure
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DocID9454 Rev 3
L6228 PWM current control
The L6228device includes a constant off time PWM current controller for each of the two bridges. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power
MOS transistors and ground, as shown in
. As the current in the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input (VREF
A or VREF
B
) the sense comparator triggers the monostable switching the bridge off. The power MOS remains off for the time set by the monostable and the motor current
recirculates as defined by the selected decay mode, described in Section 7: Decay modes on page 19
. When the monostable times out the bridge will again turn on. Since the internal deadtime, used to prevent cross conduction in the bridge, delays the turn on of the power
MOS, the effective off time is the sum of the monostable time plus the deadtime.
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shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. More details regarding the synchronous rectification and the output stage configuration are included in
Section 7: Decay modes on page 19
.
Immediately after the power MOS turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6228 device provides a 1 s blanking time t
BLANK that inhibits the comparator output so that this current spike cannot prematurely retrigger the monostable.
DocID9454 Rev 3 15/34
34
PWM current control L6228
Figure 13. Output current regulation waveforms
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shows the magnitude of the off time t approximately calculated from the equations:
OFF
versus C
OFF
and R
OFF
values. It can be
Equation 1 t
RCFALL
= 0.6 · R
OFF
· C
OFF t
OFF
= t
RCFALL
+ t
DT
= 0.6 · R
OFF
· C
OFF
+ t
DT where R
OFF
and C
OFF
are the external component values and t
DT is the internally generated deadtime with:
Equation 2
20 K R
OFF
100 K
0.47 nF C
OFF
100 nF t
DT
= 1 µs (typical value)
Therefore:
Equation 3 t
OFF(MIN)
= 6.6 µs t
OFF(MAX)
= 6 ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
16/34 DocID9454 Rev 3
L6228 PWM current control
The capacitor value chosen for C pin RCOFF. The rise time t
RCRISE
OFF
also affects the rise time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the on time t
ON depends by motors and supply parameters, has to be bigger than t
of the voltage at the
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
ON smaller than the minimum on time t
ON(MIN)
.
, which
can not be
Equation 4
t
ON
> t
= t
RCRISE t
ON
>
= 600 · C
OFF t
RCRISE
–
2.5
s (typ. value) t
DT
shows the lower limit for the on time t
ON
for having a good PWM current regulation capacity. It has to be said that t
ON
is always bigger than t
ON(MIN) device imposes this condition, but it can be smaller than t device continues to work but the off time t
OFF
RCRISE
- t
is not more constant.
DT
because the
. In this last case the
So, small C
OFF
value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for C
OFF influential will be the noises on the circuit performance.
, the more
Figure 14. t
OFF
versus C
OFF
and R
OFF
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DocID9454 Rev 3 17/34
34
PWM current control
Figure 15. Area where t
ON
can vary maintaining the PWM regulation
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18/34 DocID9454 Rev 3
L6228 Decay modes
The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin is low, the fast decay mode is selected and both transistors in the bridge are switched off during the off time. When the CONTROL pin is high, the slow decay mode is selected and only the low-side transistor of the bridge is switched off during the off time.
shows the operation of the bridge in the fast decay mode. At the start of the off time, both of the power MOS are switched off and the current recirculates through the two opposite freewheeling diodes. The current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. After the deadtime, the lower power MOS in parallel with the conducting diode is turned on in synchronous rectification mode. In applications where the motor current is low it is possible that the current can decay completely to zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower power MOS is operated in synchronous rectification mode. This operation is called “Quasi-synchronous rectification mode”. When the monostable times out, the power MOS are turned on again after some delay set by the deadtime to prevent cross conduction.
shows the operation of the bridge in the slow decay mode. At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the deadtime the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some delay set by the deadtime to prevent cross conduction.
Figure 16. Fast decay mode output stage configurations
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Figure 17. Slow decay mode output stage configurations
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34
Decay modes
7.1
L6228
Stepping sequence generation
The phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges to drive a stepper motor in either full step or half step. Two full step modes are possible, the normal drive mode where both phases are energized each step and the wave drive mode where only one phase is energized at a time. The drive mode is selected by the HALF/FULL input and the current state of the sequence generator as described below. A rising edge of the CLOCK input advances the state machine to the next state. The direction of rotation is set by the CW/CCW input. The RESET input resets the state machine to state.
7.2 Half mode
A HIGH logic level on the HALF/FULL input selects half step mode.
shows the motor current waveforms and the state diagram for the phase sequencer generator. At startup or after a RESET the phase sequencer is at state 1. After each clock pulse the state changes following the sequence 1, 2, 3, 4, 5, 6, 7, 8, etc. if CW/CCW is high (clockwise movement) or 1, 8, 7, 6, 5, 4, 3, 2, etc. if CW/CCW is low (counterclockwise movement).
7.3
7.4
Normal drive mode (full step two phase on)
A LOW level on the HALF/FULL input selects the full step mode. When the low level is applied when the state machine is at an ODD numbered state the normal drive mode is selected.
shows the motor current waveform state diagram for the state machine of the phase sequencer generator. The normal drive mode can easily be selected by holding the HALF/FULL input low and applying a RESET. At startup or after a RESET the state machine is in state 1. While the HALF/FULL input is kept low, state changes following the sequence 1, 3, 5, 7, etc. if CW/CCW is high (clockwise movement) or 1, 7, 5, 3, etc. if
CW/CCW is low (counterclockwise movement).
Wave drive mode (full step one phase on)
A LOW level on the pin HALF/FULL input selects the full step mode. When the low level is applied when the state machine is at an EVEN numbered state the wave drive mode is selected.
shows the motor current waveform and the state diagram for the state machine of the phase sequence generator. To enter the wave drive mode the state machine must be in an EVEN numbered state. The most direct method to select the wave drive mode is to first apply a RESET, then while keeping the HALF/FULL input high apply one pulse to the clock input then take the HALF/FULL input low. This sequence first forces the state machine to state 1. The clock pulse, with the HALF/FULL input high advances the state machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting from this point, after each clock pulse (rising edge) will advance the state machine following the sequence 2, 4, 6, 8, etc. if CW/CCW is high (clockwise movement) or 8, 6, 4, 2, etc. if
CW/CCW is low (counterclockwise movement).
20/34 DocID9454 Rev 3
L6228 Decay modes
Figure 18. Half step mode
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Figure 19. Normal drive mode
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Figure 20. Wave drive mode
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The L6228 device integrates an “Overcurrent Detection” circuit (OCD) for full protection.
This circuit provides protection against a short-circuit to ground or between two phases of the bridge. With this internal overcurrent detection, the external current sense resistor normally used and its associated power dissipation are eliminated.
a simplified schematic of the overcurrent detection circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high-side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current I
REF
. When the
DocID9454 Rev 3 21/34
34
Decay modes
9
''
L6228 output current reaches the detection threshold (typically 2.8 A), the OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3 V typical) by an internal open drain MOS with a pull down capability of 4 mA.
By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.
Figure 21. Overcurrent protection simplified schematic
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shows the overcurrent detection operation. The disable time t
DISABLE
before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by C
EN magnitude is reported in
. The delay time t
DELAY an overcurrent has been detected depends only by C
EN
.
and R
EN
values and its
before turning off the bridge when
value. Its magnitude is reported in
C
EN
is also used for providing immunity to the pin EN against fast transient noises.
Therefore the value of C
EN
should be chosen as big as possible according to the maximum tolerable delay time and the R
EN time.
value should be chosen according to the desired disable
The resistor R values for R
EN disable time.
EN
should be chosen in the range from 2.2 K to 180 K . Recommended
and C
EN
are respectively 100 K and 5.6 nF that allow obtaining 200 s
22/34 DocID9454 Rev 3
L6228
I
OUT
I
SOVER
Figure 22. Overcurrent protection waveforms
Decay modes
V
EN
V
DD
V th(ON)
V th(OFF)
V
EN(LOW)
ON
OCD
OFF
ON
BRIDGE
OFF t
DELAY t
DISABLE t
OCD(ON) t
EN(FALL) t
D(OFF)EN t
OCD(OFF) t
EN(RISE) t
D(ON)EN
D02IN1400
Figure 23. t
DISABLE
versus C
EN
and R
EN
(V
DD
= 5 V)
5
( 1
N 5
( 1
N
5
( 1
N
5
( 1
N
5
( 1
N
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23/34
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Decay modes
Figure 24. t
DELAY
versus C
EN
(V
DD
= 5 V)
L6228
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In addition to the overcurrent protection, the L6228 integrates a thermal protection for preventing the device destruction in case of junction overtemperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switchesoff when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value).
24/34 DocID9454 Rev 3
L6228 Application information
A typical bipolar stepper motor driver application using the L6228 device is shown in
. Typical component values for the application are shown in Table 7 . A high quality
ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins
(VS
A
and VS
B
) and ground near the L6228 device to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor connected from the EN input to ground sets the shutdown time when an overcurrent is detected (see
A
and SENSE
B
) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except EN) are best connected to
5 V (high logic level) or GND (low logic level) (see
Table 4: Pin description on page 6 ). It is
recommended to keep power ground and signal ground separated on the PCB.
Component
C
1
C
2
C
A
C
B
C
BOOT
C
P
C
EN
C
REF
Table 7. Component values for typical application
Value Component
100 µF
100 nF
1 nF
1 nF
220 nF
10 nF
5.6 nF
68 nF
D
1
D
2
R
A
R
B
R
EN
R
P
R
SENSEA
R
SENSEB
Value
1N4148
1N4148
39 K
39 K
100 K
100
0.6
0.6
DocID9454 Rev 3 25/34
34
Application information
9
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Figure 25. Typical application
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8.1 Output current capability and IC power dissipation
From
are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving a two phase stepper motor, for different driving sequences:
HALF STEP mode ( Figure 26 ) in which alternately one phase / two phases are
energized.
NORMAL DRIVE (FULL STEP TWO PHASE ON) mode (
phases are energized during each step.
WAVE DRIVE (FULL STEP ONE PHASE ON) mode ( Figure 28 ) in which only one
phase is energized at each step.
MICROSTEPPING mode ( Figure 29 ), in which the current follows a sine wave profile,
provided through the V ref
pins.
For a given output current and driving sequence the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
26/34 DocID9454 Rev 3
L6228 Application information
Figure 26. IC power dissipation versus output current in HALF STEP mode
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Figure 27. IC power dissipation versus output current in NORMAL mode
(full step two phase on)
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Figure 28. IC power dissipation versus output current in WAVE mode
(full step one phase on)
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Application information L6228
Figure 29. IC power dissipation versus output current in MICROSTEPPING mode
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In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness. Figure 30
junction to ambient thermal resistance values for the PowerSO36 and SO24 packages.
For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board with a 6 cm
2
dissipating footprint (copper thickness of 35 µm), the
R th(j-amb)
is about 35 °C/W.
shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to
15 °C/W.
Figure 30. PowerSO36 junction ambient thermal resistance versus on-board copper area
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28/34 DocID9454 Rev 3
L6228 Application information
Figure 31. SO24 junction ambient thermal resistance versus on-board copper area
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Figure 32. Mounting the PowerSO package
Slug soldered to PCB with dissipating area
Slug soldered to PCB with dissipating area plus ground layer
Slug soldered to PCB with dissipating area plus ground layer contacted through via holes
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DocID9454 Rev 3 29/34
34
Package information L6228
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
Figure 33. PowerSO36 package outline
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30/34 DocID9454 Rev 3
L6228 Package information
Table 8. PowerSO36 package mechanical data
Dimensions
Symbol mm inch
Min. Typ. Max. Min. Typ. Max.
A a1 0.10 a2 a3 0 -
E4 2.90 -
G 0 -
H 15.50
-
3.60 -
0.30 0.004 -
-
-
0.10 0 b 0.22 c 0.23 -
D
(1)
15.80 -
D1 9.40 9.80 0.370 -
E 13.90 e -
14.50 0.547 -
0.65 0.0256
0.435
e3
E1
(1)
11.05
10.90 -
E2 -
E3 5.80 -
2.90 -
6.20 0.228 -
3.20 0.114 -
0.10 0 h -
L 0.80 -
1.10 -
0.570
-
-
0.437
0.114
0.244
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.126
0.004
0.626
0.043
0.043
1. “D” and “E1” do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch).
- Critical dimensions are “a3”, “E” and “G”.
DocID9454 Rev 3 31/34
34
Package information
9.2 SO24 package information
Figure 34. SO24 package outline
L6228
32/34
&
Table 9. SO24 package mechanical data
Dimensions (mm) Dimensions (inch)
Symbol
Min. Typ. Max. Min. Typ. Max.
A 2.35 -
A1 0.10 -
B 0.33 -
C 0.23 -
D
(1)
15.20 -
E 7.40 e -
H 10.0 h 0.25 -
L 0.40 k ddd -
-
0° (min.), 8° (max.)
0.10 -
0.050
0.004
1. D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.
0.104
0.012
0.020
0.013
0.614
0.299
-
0.419
0.030
0.050
DocID9454 Rev 3
L6228 Revision history
Date
03-Sep-2003
18-Feb-2014
03-Oct-2018
Revision
Table 10. Document revision history
Changes
1
2
3
Initial release.
Updated Section : Description on page 1 (removed “MultiPower-” from “MultiPower-BCD technology”
Added Contents on page 2 .
Updated Section 1: Block diagram (added section title, numbered and moved Figure 1: Block diagram from page 1 to page 3.
Added title to Section 2: Maximum ratings on page 4 , added numbers and titles from Table 1: Absolute maximum ratings to Table 3:
Thermal data .
Added title to Section 3: Pin connections on page 6 , added number and title to Figure 2: Pin connections (top view) , renumbered note 1 below Figure 2 , added title to Table 4: Pin description , renumbered note 1 below Table 4 .
Added title to Section 4: Electrical characteristics on page 9 , added title and number to Table 5 , renumbered notes 1 to 7 below Table 5 .
Renumbered Figure 3 to Figure 7 .
Added numbers to Section 5: Circuit description on page 13
(including Section 5.1
and Section 5.2
).
Removed “and uC” from Section 5.2
. Renumbered Table 6 , added header to Table 6 . Renumbered Figure 8 to Figure 11 .
Added numbers to Section 6: PWM current control on page 15 .
Renumbered Figure 12 to Figure 15 . Added titles to Equation 1: on page 16 till Equation 4: on page 17 .
Added numbers to Section 7: Decay modes on page 19
(including Section 7.1
to Section 7.6
). Renumbered Figure 16 to
Figure 24 .
Added numbers to Section 8: Application information on page 25
(including Section 8.1
and Section 8.2
). Renumbered Table 7 , added header to Table 7 . Renumbered Figure 25 to Figure 33 .
Updated Section 9: Package information on page 30 (added main title and ECOPACK text. Added titles from Table 8: PowerSO36 package mechanical data to Table 10: SO24 package mechanical data and from Figure 34: PowerSO36 package outline to Figure 36:
SO24 package outline , reversed order of named tables and figures.
Removed 3D figures of packages, replaced 0.200 by 0.020 inch of max. B value in Table 10 ).
Added cross-references throughout document.
Added Table 11: Document revision history .
Minor modifications throughout document.
Removed PowerDIP24 package from the whole document.
Removed “T j
.
Minor modifications throughout document.
DocID9454 Rev 3 33/34
34
L6228
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
34/34 DocID9454 Rev 3
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