STL47N60M6
Datasheet
N-channel 600 V, 70 mΩ typ., 31 A MDmesh™ M6
Power MOSFET in a PowerFLAT™ 8x8 HV package
4
3
2
1
5
PowerFLAT™ 8x8 HV
Drain(5)
Gate(1)
Driver source (2)
Power source (3, 4)
NG1DS2PS34D5Z
Features
Order code
STL47N60M6
V
DS
600 V
R
DS(on)
max.
82 mΩ
I
D
31 A
• Reduced switching losses
• Lower R
DS(on)
x area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
• Excellent switching performance thanks to the extra driving source pin
Applications
• Switching applications
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
Product status link
STL47N60M6
Product summary
Order code
Marking
Package
Packing
STL47N60M6
47N60M6
PowerFLAT™ 8x8 HV
Tape and reel
DS12382 - Rev 2 - January 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STL47N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt (2)
Gate-source voltage
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Total power dissipation at T
C
= 25 °C
= 100 °C
= 25 °C
dv/dt (3)
T stg
T j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 31 A, di/dt ≤ 400 A/µs, V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V
3. V
DS
≤ 480 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on 1 inch 2 FR-4, 2 Oz copper board
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by T jmax
)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±25
31
20
124
190
15
100
-55 to 150
Unit
V
A
A
A
W
V/ns
V/ns
°C
Value
0.66
50
Unit
°C/W
°C/W
Value
5.3
800
Unit
A mJ
DS12382 - Rev 2 page 2/15
2
STL47N60M6
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4. On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
V
GS
= 0 V, I
Test conditions
D
= 1 mA
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Zero gate voltage drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source on-resistance
1. Defined by design, not subject to production test.
V
GS
= 0 V, V
DS
= 600 V
V
GS
= 0 V, V
DS
= 600 V, T
C
= 125 °C
(1)
V
DS
V
DS
= 0 V, V
= V
GS
GS
, I
D
= ±25 V
= 250 µA
V
GS
= 10 V, I
D
= 15.5 A
Min.
Typ.
Max.
Unit
600 V
3.25
4
1
100
±5
4.75
µA
µA
µA
V
70 82 mΩ
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
G
Q g
Q gs
Q gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
Equivalent output capacitance V
DS
= 0 to 480 V, V
GS
= 0 V
Intrinsic gate resistance f = 1 MHz, I
D
= 0 A
= 0 V
V
DD
= 480 V, I
D
= 36 A, V
GS
= 0 to 10 V
(see Figure 14. Test circuit for gate charge behavior )
Min.
-
-
-
-
-
-
-
-
Typ.
2340
149
3.7
390
1.4
52.2
16.5
23
Max.
-
-
-
-
-
-
-
-
Unit pF pF pF pF
Ω nC nC nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V to 80% V
DSS
DS
increases from 0
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 300 V, I
D
= 18 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13. Switching times test circuit for resistive load and
Figure 18. Switching time waveform )
Min.
Typ.
Max.
Unit
-
-
-
-
21.5
18.7
54.6
8.1
-
-
-
ns ns ns ns
DS12382 - Rev 2 page 3/15
STL47N60M6
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
(1)
I
SDM
, (2) (1)
V
SD
(3)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
I
V
T
SD
SD j
= 36 A, di/dt = 100 A/µs, V
= 36 A, di/dt = 100 A/µs, V
DD
= 60 V,
= 150 °C (see
Figure 15. Test circuit for inductive load switching and diode recovery times )
DD
= 60 V
(see Figure 15. Test circuit for inductive load switching and diode recovery times
)
1. This value is limited by package.
2. Pulse width is limited by safe operating area.
3. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
GS
Test conditions
= 0 V, I
SD
= 31 A
-
-
-
-
-
-
-
Min.
Typ.
Max.
Unit
31 A
124 A
1.6
281
3.67
26.1
424
7.2
34
V ns
µC
A ns
µC
A
DS12382 - Rev 2 page 4/15
STL47N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A) Operation in this area is limited by R
DS(on)
GIPG080120191350SOA
10 2
10 1
10 0
T
J
T
C
≤150 °C
=25 °C
V
GS
=10 V single pulse t p
=1 µs t p
=10 µs t p
=100 µs t p
=1 ms t p
=10 ms
10 -1
10 -1 10 0 10 1 10 2
V
DS
(V)
V
GS
=7, 8, 9, 10 V
I
D
(A)
120
Figure 3. Output characteristics
GIPG101220181057OCH
V
GS
=10 V
V
GS
=9 V
100
80
V
GS
=8 V
60
40
V
GS
=7 V
20
0
0 2 4 6 8 10 12 14 16
V
GS
=6 V
V
DS
(V)
Figure 2. Thermal impedance
K
δ = 0.5
Zth PowerFLAT 8x8 HV
δ = 0.2
10 -1
δ = 0.1
10 -2
δ = 0.05
δ = 0.02
δ = 0.01
Single pulse
10 -3
10 -6 10 -5 10 -4 10 -3 10 -2 t p
(s)
I
D
(A)
120
Figure 4. Transfer characteristics
V
DS
=16 V
GIPG101220181058TCH
100
80
60
40
20
0
4 5 6 7 8 9 V
GS
(V)
Figure 5. Gate charge vs gate-source voltage
V
DS
(V)
V
DD
= 480 V, I
D
= 36 A
GIPG101220181058QVG V
GS
(V)
600
Q g
12
500
V
DS
10
400
Q gs
Q gd
8
300 6
200
100
0
0 10 20 30 40 50 60
4
2
Q
0 g
(nC)
Figure 6. Static drain-source on-resistance
R
DS(on)
(mΩ)
76
V
GS
=10 V
GIPG090120191039RID
74
72
70
68
66
0 5 10 15 20 25 30 I
D
(A)
DS12382 - Rev 2 page 5/15
STL47N60M6
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG101220181057CVR
10 4
10 3
10 2
10 1
10 0
10 -1 f = 1 MHz
10 0 10 1 10 2
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.2
V
GS
= 10 V
GIPG101220181029RON
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T
J
(°C)
Figure 11. Output capacitance stored energy
E
OSS
(µJ)
20
ADG181220181310EOS
16
12
8
4
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
GIPG101220181029VTH
I
D
= 250 μA
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T
J
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.08
I
D
= 1 mA
GIPG101220181055BDV
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.1
GIPG080120191351SDF
T j
= -50 °C
1.0
0.9
0.8
0.7
0.6
0.5
0 5
T j
= 25 °C
T j
= 150 °C
10 15 20 25 30 I
SD
(A)
DS12382 - Rev 2 page 6/15
STL47N60M6
Test circuits
3
Test circuits
Figure 13. Switching times test circuit for resistive load
R
L
V
GS
P
W
GND1
(driver signal)
V
D
R
G
GND2
(power)
D.U.T.
+
2200
µF
3.3
µF
V
DD
AM15855v1
Figure 15. Test circuit for inductive load switching and diode recovery times
25Ω
G
A
D
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
D
L=100µH
G
S
D.U.T.
3.3
µF
+
1000
µF
V
DD
GND1 GND2
AM15857v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V D
I
DM
I D
V
DD V
DD
AM01472v1
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
GND1
100 Ω
D.U.T.
V
G
GND2
GADG180720181011SA
Figure 16. Unclamped inductive load test circuit
L
V
D
I D
V i
P w
GND1 GND2
D.U.T.
+
2200
µF
3.3
µF
V DD
AM15858v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS12382 - Rev 2 page 7/15
4
STL47N60M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS12382 - Rev 2 page 8/15
4.1
STL47N60M6
PowerFLAT™ 8x8 HV package information
PowerFLAT™ 8x8 HV package information
Figure 19. PowerFLAT™ 8x8 HV package outline
DS12382 - Rev 2
8222871_Rev_4 page 9/15
Ref.
D2
E1
E2 e
L
A
A1
A3 b
D
E
STL47N60M6
PowerFLAT™ 8x8 HV package information
Table 8. PowerFLAT™ 8x8 HV mechanical data
Min.
0.75
0.00
0.10
0.90
7.90
7.90
7.10
2.65
4.25
0.40
Dimensions (in mm)
Typ.
0.85
0.20
1.00
8.00
8.00
7.20
2.75
4.35
2.00 BSC
0.50
Figure 20. PowerFLAT™ 8x8 HV footprint
Max.
0.95
0.05
0.30
1.10
8.10
8.10
7.30
2.85
4.45
0.60
Note: All dimensions are in millimeters.
DS12382 - Rev 2
8222871_REV_4_footprint page 10/15
4.2
STL47N60M6
PowerFLAT™ 8x8 HV packing information
PowerFLAT™ 8x8 HV packing information
Figure 21. PowerFLAT™ 8x8 HV tape
P0 (4.0±0.1) P2 (2.0±0.1)
D0 ( 1.55±0.05) T (0.30±0.05)
E (1.75±0.1)
D1 ( 1.5 Min)
P1 (12.00±0.1) A0 (8.30±0.1)
K0 (1.10±0.1)
Note:
Note: Base and Bulk qu antity 3000 pcs
All dimensions are in millimeters.
Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape
8229819_Tape_revA
DS12382 - Rev 2 page 11/15
STL47N60M6
PowerFLAT™ 8x8 HV packing information
Figure 23. PowerFLAT™ 8x8 HV reel
Note: All dimensions are in millimeters.
8229819_Reel_revA
DS12382 - Rev 2 page 12/15
STL47N60M6
Revision history
Date
15-Nov-2017
22-Jan-2019
Revision
1
2
Table 9. Document revision history
Changes
First release
Modified
Table 1. Absolute maximum ratings , Table 2. Thermal data
,
Table 3. Avalanche characteristics
, Table 4. On/off states
,
Table 5. Dynamic ,
Table 6. Switching times and
Table 7. Source-drain diode
.
Added Section 2.1 Electrical characteristics (curves) .
Modified
Section 3 Test circuits .
Minor text changes.
DS12382 - Rev 2 page 13/15
STL47N60M6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
PowerFLAT 8x8 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS12382 - Rev 2 page 14/15
STL47N60M6
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© 2019 STMicroelectronics – All rights reserved
DS12382 - Rev 2 page 15/15
