STMicroelectronics STL110N10F7 Datasheet
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STL110N10F7
N-channel 100 V, 5 mΩ typ., 107 A, STripFET F7 Power MOSFET in a PowerFLAT 5x6 package
G(4)
PowerFLAT 5x6
D(5, 6, 7, 8)
S(1, 2, 3)
8 7 6 5
Features
Order code
STL110N10F7
V
DS
100 V
R
DS(on)
max.
6 mΩ
• Among the lowest R
DS(on)
on the market
• Excellent FoM (figure of merit)
• Low C rss
/C iss
ratio for EMI immunity
• High avalanche ruggedness
Applications
• Switching applications
I
D
107 A
P
TOT
136 W
1 2 3 4
Top View
AM15540v2
Description
This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching.
Product status link
STL110N10F7
Product summary
Order code
Marking
Package
Packing
STL110N10F7
110N10F7
PowerFLAT 5x6
Tape and reel
DS9392 - Rev 6 - March 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STL110N10F7
Electrical ratings
1
Electrical ratings
Symbol
V
DS
V
GS
I
D
I
DM
I
D
I
DM
P
TOT
P
TOT
E
AS
T
J
Table 1. Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
=100 °C
Drain current (pulsed)
Total power dissipation at T
C
= 25 °C
Total power dissipation at T pcb
= 25 °C
Single pulse avalanche energy
Operating junction temperature range
T stg
Storage temperature range
1. This value is rated according to R thj-c.
2. Pulse width limited by safe operating area.
3. This value is rated according to R thj-pcb.
4. Starting T
J
= 25 °C, I
D
= 18 A, V
DD
= 50 V.
Table 2. Thermal resistance
Symbol
R thj-case
R thj-pcb
Thermal resistance junction-case
Thermal resistance junction-pcb
Parameter
1. When mounted on an FR-4 board of 1 inch², 2oz Cu, t < 10 s.
Value
100
±20
107
75
428
21
14
84
136
4.8
490
-55 to 175
Unit
V
V
A
A
A
A
A
A
W
W mJ
°C
Value
1.1
31.3
Unit
°C/W
°C/W
DS9392 - Rev 6 page 2/14
2
DS9392 - Rev 6
STL110N10F7
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 3. On/off states
Symbol Parameter Test conditions
V
(BR)DSS
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, V
DS
= 100 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 100 V, T
C
Gate body leakage current
Gate threshold voltage
V
DS
= 0, V
GS
= 20 V
V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on ‑ resistance V
GS
= 10 V, I
D
= 10 A
1. Defined by design, not subject to production test.
Min.
Typ.
Max.
Unit
100 V
1
µA
10
2.5
5
100
4.5
6 nA
V mΩ
Table 4. Dynamic
Test conditions Symbol
C iss
C oss
C rss
Q g
Q gs
Q gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 50 V, f = 1 MHz, V
GS
= 0 V
V
DD
= 50 V, I
D
= 21 A, V
GS
= 0 to 10 V
(see
Figure 13. Test circuit for gate charge behavior )
-
-
-
-
Min.
Typ.
Max.
Unit
5117 -
992 pF
39
72
30
17
-
-
-
nC
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 50 V, I
D
= 10 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 12. Test circuit for resistive load switching times
and
Figure 17. Switching time waveform )
Min.
Typ.
Max.
Unit
25 ns
-
-
-
36
52
21
-
-
ns ns ns
Table 6. Source-drain diode
Symbol
V
SD
t rr
I
Q rr
RRM
Parameter
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Test conditions
I
SD
= 21 A, V
GS
= 0 V
I
SD
= 21 A, di/dt = 100 A/µs,
V
DD
= 80 V, T
J
= 150 °C
(see
Figure 14. Test circuit for inductive load switching and diode recovery times )
Min.
Typ.
Max.
Unit
1.2
V
-
77
150 ns nC
4.3
A page 3/14
STL110N10F7
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I D
(A)
Figure 1. Safe operating area
AM16083v1
R
DS(on)
10 ration in this area is
Ope
Limited by max
1
0.1
0.1 1
Tj=175°C
Tpcb=25°C
Single pulse
10
10ms
100ms
1s
V DS (V)
I D (A)
160
140
120
100
80
60
40
20
0
0
Figure 3. Output characteristics
AM16084v1
7V
V
GS
= 8, 9, 10 V
2 4 6
6V
8
5V
4V
V DS (V)
Figure 5. Gate charge vs gate-source voltage
V
DS
(V)
12
GADG020320200919QVG
10
8
6
V
I
DD
D
= 50 V
= 21 A
4
2
0
0 10 20 30 40 50 60 70 80 90 Q g
(nC)
Figure 2. Thermal impedance
K
δ=0.5
10 -1
10 -2
0.2
0.1
0.05
0.01
0.02
Z th
= K R thj-pcb
AM16096v1
10 -3
10 -4 10 -3
Single pulse
10 -2 10 -1 10 0 10 1 t p
(s)
50
40
30
20
10
0
0
I
D
(A)
70
Figure 4. Transfer characteristics
AM16085v1
V
DS
=2V
60
2 4 6 8 V
GS
(V)
Figure 6. Static drain-source on-resistance
AM16087v1
R
DS (on)
(m Ω )
5.06
V GS =10V
5.04
5.02
5.00
4.98
4.96
4.94
2 4 6 8 10 12 14 16 18 20 I D (A)
DS9392 - Rev 6 page 4/14
STL110N10F7
Electrical characteristics (curves)
C
(pF)
6000
Figure 7. Capacitance variations
AM16088v1
5000 Cis s
4000
3000
2000
1000
0
0 10 20 30 40 50 60 70 80
Cos s
Crs s
V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
AM16089v1 V
GS(th)
(norm)
1.2
I D =250µA
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
-75 -50 -25 0 25 50 75 100 125 150 T
J
(°C)
Figure 9. Normalized on-resistance vs temperature
AM16090v1
R
DS (on)
(norm)
2
1.8
I
D
=10 A
V GS =10 V
1.6
1.4
1.2
1
0.8
0.6
0.4
-75 -50 -25 0 25 50 75 100 125 150 T
J
(°C)
Figure 10. Source-drain diode forward characteristics
AM16092v1
V S D
(V)
T
J
=-55°C
0.9
T
J
=25°C
0.8
0.7
0.6
T
J
=175°C
0.5
0.4
2 4 6 8 10 12 14 16 18 20 I S D (A)
Figure 11. Normalized V
(BR)DSS
vs temperature
AM16091v1
V (BR)DSS
(norm)
I D =1mA
1.04
1.02
1
0.98
0.96
0.94
-50 -25 0 25 50 75 100 T
J
(°C)
DS9392 - Rev 6 page 5/14
STL110N10F7
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 13. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V (BR)DSS
V D
I DM
I D
V DD V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 17. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS9392 - Rev 6 page 6/14
4
4.1
STL110N10F7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
PowerFLAT 5x6 type C package information
Figure 18. PowerFLAT 5x6 type C package outline
Bottom view
DS9392 - Rev 6
Side view
Top view
8231817_typeC_Rev20 page 7/14
DS9392 - Rev 6
Dim.
E7
K
L
L1
θ
E2
E3
E4
E5
E6 e
E
D2
D3
D4
D5
D6
A
A1
A2 b
C
D
STL110N10F7
PowerFLAT 5x6 type C package information
Table 7. PowerFLAT 5x6 type C package mechanical data mm
Typ.
Min.
0.80
0.02
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.15
5.95
3.50
2.35
0.40
0.08
0.20
0.75
1.05
0.725
0.05
0°
0.325
0.90
0.15
Max.
1.00
0.05
0.50
6.20
5.40
4.45
4.35
5.20
0.55
0.45
6.35
3.70
2.55
0.60
0.28
0.45
1.05
1.35
1.025
0.25
12° page 8/14
DS9392 - Rev 6
STL110N10F7
PowerFLAT 5x6 type C package information
Figure 19. PowerFLAT 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_simp_Rev_20 page 9/14
4.2
STL110N10F7
PowerFLAT 5x6 packing information
PowerFLAT 5x6 packing information
Figure 20. PowerFLAT 5x6 tape (dimensions are in mm)
Pin 1 identification
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
8234350_Tape_rev_C
Figure 21. PowerFLAT 5x6 package orientation in carrier tape
DS9392 - Rev 6 page 10/14
Figure 22. PowerFLAT 5x6 reel
STL110N10F7
PowerFLAT 5x6 packing information
DS9392 - Rev 6 page 11/14
STL110N10F7
Revision history
Date
03-Dec-2012
12-Dec-2013
25-Mar-2014
20-Aug-2014
17-Sep-2018
03-Mar-2020
Revision
1
2
3
4
5
6
Table 8. Document revision history
Changes
First release.
Modified: P
TOT
value and Figure 1 in cover page
Modified: I
D
, I
DM
and P
TOT
values in Table 2
Added: E
AS
value in Table 2
Modified: all values in Table 3
Modified: I
DSS
, I
GSS
and I
D
for R
DS(on)
Updated: the entire typical values in Table 5, 6 and 7
Updated: Figure 13, 14, 15 and 16
Minor text changes
Updated title and features on cover page.
Added P
TOT
value at T
C
= 25 °C in Table 2: Absolute maximum ratings .
Updated Section 4: Package mechanical data .
Modified: title, features and description
Modified: Figure 2 and 3
Updated: Section 4: Package mechanical data .
Minor text changes
Removed maturity status indication.
Updated title and description on cover page.
Updated Table 1. Absolute maximum ratings and Table 6. Source-drain diode .
Updated Section 4.1 PowerFLAT™ 5x6 type C package information .
Minor text changes
Updated
Figure 5. Gate charge vs gate-source voltage .
Minor text changes.
DS9392 - Rev 6 page 12/14
STL110N10F7
Contents
Contents
DS9392 - Rev 6 page 13/14
STL110N10F7
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© 2020 STMicroelectronics – All rights reserved
DS9392 - Rev 6 page 14/14
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