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LED6001
PWM-dimmable single channel LED driver with integrated boost controller
Datasheet
-
production data
HTSSOP-16
Features
• Switching controller section
– 5.5 V to 36 V input voltage range
– Very low shutdown current: I
SHDN
<
10 µA
– Internal +5 V LDO for gate driver supply
– Internal +3.3 V LDO for device supply
– Fixed frequency peak current mode control
– Adjustable (100 kHz to 1 MHz) switching frequency
– External synchronization for multi-device applications
– High performance external MOSFET driver
– Cycle-by-cycle external MOSFET OCP
– Fixed internal soft-start
– Programmable output OVP
– Boost, buck-boost and SEPIC topologies supported
– Thermal shutdown with autorestart
– Output short-circuit detection
• LED control section
– Up to 60 V output voltage
– Constant current control loop
– High-side output current sensing circuitry
– 30 to 300 mV differential sensing voltage
– ± 4% output current reference accuracy
– Output overcurrent protection
– Sensing resistor failure protection
– PWM dimming with auxiliary series switch
– Analog dimming
Applications
• Indoor and architectural LED lighting
• Emergency LED lighting
• Off-grid LED street lighting
• White goods
• Gaming/gambling machines
Description
The LED6001 device is a LED driver that combines a boost controller and a high-side current sensing circuitry optimized for driving one string of high-brightness LEDs. The device is compatible with multiple topologies such as boost, SEPIC and floating load buck-boost. The brightness of the LEDs can be controlled through
PWM dimming and analog dimming (10:1 ratio) by means of two independent pins. Enhanced
PWM dimming can be obtained thanks to a MOSFET in series with the LED string and directly driven by a dedicated pin.
The high-side current sensing, in combination with a P-channel MOSFET, provides an effective protection in case the positive terminal of the LED string is shorted to ground. The high precision current sensing circuitry allows a LED current regulation reference within ± 4% accuracy over the whole temperature range and production spread.
A fault output (open-drain) informs the host system about faulty conditions: device overtemperature, output overvoltage
(disconnected LED string) and LED overcurrent.
Table 1. Device summary
Order code Package Packaging
LED6001
LED6001TR
HTSSOP-16
(exposed pad)
Tube
Tape and reel
February 2020
This is information on a product in full production.
DocID025575 Rev 4 1/26 www.st.com
Contents
Contents
LED6001
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Turn on and power-down sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boost controller operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Boost converter stability and slope compensation . . . . . . . . . . . . . . . . . 14
Switching frequency oscillator and external synchronization . . . . . . . . . 16
LED current regulation and brightness control . . . . . . . . . . . . . . . . . . . . . 17
Linear regulators undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power switch overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output overvoltage and OVFB pin disconnection . . . . . . . . . . . . . . . . . 20
Output rail disconnection detection or output short-circuit to ground . . . 21
2/26 DocID025575 Rev 4
LED6001
1 Typical application circuit
Typical application circuit
Figure 1. Basic application circuit schematic (boost topology)
L
BOOST
D
FW
V
OUT
V
IN
C
IN
V
LDO3
R
FSW
C
COMP
VIN
C
LDO3
V
LDO3
C
VDR
GATE
CSNS
LDO3
PGND
VDR
VFBP
XFAULT
LED6001
PWMI
VFBN
FSW
V
LDO3
OVFB
ADIM
R
COMP
PWMO
COMP
SGND
R
GATE
R
SLOPE
V
OVFB
Q
SW
Q
DIM
C
OUT
R
SNS
R
OVFBH
V
OVFB
R
OVFBL
R
VFB
AM03411
DocID025575 Rev 4 3/26
26
Pin function
2 Pin function
PWMI
FS W
XFAU LT
LDO3
SGND
COMP
ADIM
OV FB
Figure 2. Pin connection (through top view)
1
4
5
2
3
6
7
8
16
15
14
13
12
11
10
9
VFBP
VFBN
VIN
VDR
GATE
PGND
PWMO
CSNS
LED6001
AM03412V1
4/26 DocID025575 Rev 4
LED6001 Pin function
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
-
Pin
Table 2. Pin description
Description
PWMI Device enable and PWM dimming control input.
FSW
Switching frequency setting. A resistor between this pin and SGND sets the desired switching frequency. This pin is also used as synchronization input. If tied high (e.g. connected to LDO3 pin) a 600 kHz switching frequency is set.
XFAULT
LDO3
Fault indicator, open-drain output. This pin is tied low by the device in case of faulty condition. See
for details.
3.3 V linear regulator output and device supply. Connect a 1 μ F (typ.) bypass
MLCC between this pin and SGND as close as possible to the chip.
SGND
COMP
ADIM
OVFB
CSNS
PWMO
PGND
GATE
VDR
VIN
VFBN
VFBP
TPAD
Signal ground. Return for analog circuitry. All setting components must refer to this grounding pin.
Boost controller loop compensation. A simple RC series must be connected
between this pin and SGND for proper loop compensation. See
for details.
Analog dimming control input. The current at the output is linearly controlled by the voltage applied to this pin (0.3 V to 1.2 V). When the device is set to operate in standalone mode, a partition of the LDO3 voltage must be applied to this pin through a resistor divider.
Output overvoltage protection feedback input. Connect to the central tap of a resistor divider at the output.
Boost controller power switch current sensing input. Connect to the source of the external power MOSFET for proper switch overcurrent protection.
PWM dimming control output. This pin provides a PWM output signal (in phase with the one applied to the PWMI pin) for direct control of a dimming N-channel
MOSFET.
Power ground. Return for the VDR linear regulator and the power switch gate drivers. Also used as reference for the power MOSFET current sensing circuitry.
Connect to ground as close as possible to the quiet terminal of the power switch sensing resistor.
Power switch gate driver output. Connect to the gate of the power MOSFET through a small value resistor.
5 V linear regulator output and gate driver supply. Connect a 1 μ F (typ.) bypass
MLCC between this pin and PGND as close as possible to the chip.
Supply voltage input. Connect this pin to the supply power rail. A 1 μ F (typ.) bypass MLCC must be connected between this pin and PGND as close as possible to the chip.
Output current differential sensing input, negative terminal. Connect to the hot terminal (load side) of the high-side sensing resistor.
Output current differential sensing input, positive terminal. Connect to the quiet terminal (output capacitor side) of the high-side sensing resistor.
Thermal pad. Connect to a suitable ground plane area in order to ensure proper heat dissipation. Electrically connected to PGND and SGND.
DocID025575 Rev 4 5/26
26
Block diagram
3 Block diagram
Figure 3. Simplified block diagram
VIN
LDO3
FSW
COMP
XFAULT
PWMI
LED6001
VDR
3.3 V LDO
UVLO detector
EN
5 V LDO
Ramp generator
Sync. detector
OSC
+
+
_
+
Slope compensation
Current sensing
Boost converter control logic
EN Soft start
Output current setting
CSNS
GATE
PGND
ADIM
VFBP
_ g m
+
+
30 mV - 300 mV
VFBN
Thermal protection
Control logic
Fault management
Feedback/output disconnection and overload detection
OVP +
_ 1.2 V
PWM detector
Pow er-down watchdog timer
EN VDR
OVFB
PWMO
PGND
SGND
AM03413
6/26 DocID025575 Rev 4
LED6001
4 Absolute maximum ratings
Absolute maximum ratings
Parameter
Maximum pin voltage
HBM ESD susceptibility
JEDEC JS001
VIN, VFBP, VFBN and ADIM ESD susceptibility
CDM ESD resistivity to SGND
ANSI/ESD STM5.3.1
Table 3. Absolute maximum ratings
Pin
VIN to SGND
VFBP and VFBN to SGND
VDR to SGND
LDO3 to SGND
COMP, CSNS and OVFB to SGND
PGND to SGND
XFAULT, FSW, ADIM and GATE to SGND
PWMI and PWMO to SGND
All pins
VIN, VFBP, VFBN, ADIM to SGND
Corner pins
Non-corner pins
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-2000
Max.
40
65
6
3.6
3.6
0.3
6
6
2000
Unit
V
-4000
-750
-500
4000
750
500
Symbol
T
J,OP
T
STG
T
SHDN
R th,JA
(1)
Table 4. Thermal characteristics
Parameter Conditions
Operating junction temperature
Storage temperature range
Thermal shutdown threshold
Thermal shutdown hysteresis
XFAULT release hysteresis
Junction to ambient thermal resistance
1s0p
2s2p
R th,JC
Junction to case thermal resistance
1. The device mounted on a standard JESD51-5 test board.
Min.
-40
-50
150
55
45
37
160
20
40
Typ.
Max.
150
150
175
Unit
°C
°C/W
DocID025575 Rev 4 7/26
26
Recommended operating conditions
5 Recommended operating conditions
LED6001
Symbol
DC characteristics
V
VIN
V
VDR
V
VFBx
V
FB
AC characteristics f sw f
PWMI t
PWMI,en t
PWMI,dim
Table 5. Recommended operating conditions
Parameter
Supply input voltage range
VDR pin Input voltage range
Feedback input common mode voltage range
Feedback input differential mode voltage range
Conditions Min.
5.5
VDR and VIN shorted together 4.7
VFBP to VFBN
4.4
30
Max. Unit
36
5.5
60
V
300 mV
Switching frequency
Dimming frequency
Minimum PWMI pulse duration for device enable (turn on)
Minimum dimming on-time
PWMI input, f
SW
= 800 kHz
PWMI input, f
SW
= 1 MHz
100 1000
0.1
20 kHz
100 µs
6 µs
8/26 DocID025575 Rev 4
LED6001
6 Electrical characteristics
Electrical characteristics
V
IN
= 12 V, V
VFBP
= 12 V, V
VFBN
= 12 V and T
J
=- 40 °C to 125 °C if not otherwise specified.
Symbol
V
LDO3
Table 6. Electrical characteristics
Parameter
Supply section t t
V
VIN
SHDN
START
Supply voltage range
PWMI turn on threshold
PWMI turn off threshold
PWMI pull-down resistor
PWMI low to shutdown mode delay
Start-up time
3.3 V LDO output voltage
3.3 V LDO line regulation
3.3 V LDO load regulation
Conditions Min. Typ. Max. Unit
PMWI at 3.3 V
C
LDO3
= C
VDR
= 470 nF
6 V ≤ V
IN
≤ 36 V, I
LDO3
PWMI high
= 0.5 mA,
I
LDO3
= 20 mA, PWMI high
6 V ≤ V
IN
≤ 36 V
V
IN
= 6 V, PWMI high
0.5 mA ≤ I
LDO3
≤ 20 mA
5.5
1.34
36
1.65
V
0.7
0.85
1.1
350 570 810 k Ω
10 15 22 ms
100 170 µs
3.2
3.3
5
90
3.4
20
100
V mV
V
LDO3,ON
V
LDO3,OFF
LDO3 undervoltage lockout upper threshold
LDO3 undervoltage lockout lower threshold
LDO3 undervoltage lockout hysteresis
3.3 V LDO current limit
2.2
2.8
3.0
2.5
2.7
2.9
V
50 200 400 mV
30 38 46 mA
V
VDR
5 V LDO output voltage
5 V LDO line regulation
5 V LDO load regulation
VLDO3 = 3.0 V
6 V ≤ V
IN
≤ 36 V
I
VDR
= 0.5 mA, PWMI high
I
VDR
= 40 mA, PWMI high
6 V ≤ V
IN
≤ 36 V
V
IN
= 6 V, PWMI high
0.5 mA ≤ I
VDR
≤ 40 mA
I
VDR
= 25 mA, V
VIN
= 4.8 V
4.8
5.0
5.2
10 40
120 200
150 300
V mV
V
VDR,ON
V
VDR,OFF
5 V LDO dropout voltage
VDR undervoltage lockout upper threshold
VDR undervoltage lockout lower threshold
VDR undervoltage lockout hysteresis
5 V LDO current limit V
VDR
= 4.5 V
4.3
4.6
4.7
V
4.25
4.4
4.55
mV
20 150 300
50 75 100 mA
DocID025575 Rev 4 9/26
26
Electrical characteristics LED6001
Symbol
Power consumption
Table 6. Electrical characteristics (continued)
Parameter Conditions Min. Typ. Max. Unit
I
VIN,SHDN
Shutdown current
I
VIN,Q
Quiescent current
V
IN
= 16 V, PWMI low,
-40 °C ≤ T
J
≤ 25 °C
V
IN
= 16 V, PWMI low,
25 °C ≤ T
J
≤ 125 °C
V
IN
= 16 V, PWMI to LDO3,
-40 °C ≤ T
J
≤ 125 °C switching off-time
V
IN
= 16 V, PWMI high, f
SW
= 200 kHz, C
L
= 3.3 nF
1
1
4
9
1
10
25
1.7
μ A mA
I
VIN,ON
Operating current
Boost controller t
ON,min
Minimum switching on-time
K
FSW
Switching frequency constant f
SW
R
GATE
Adjustable switching frequency
Fixed switching frequency
Synchronization signal frequency capture range
FSW synchronization input high level
FSW synchronization input low level
Synchronization input high level pulse width
Power switch gate driver output resistance t t r,GATE f,GATE t
SS
K
S
V
CSNS,OCP
Power switch gate driver rise time
(20 to 80%)
Power switch gate driver fall time
(80 to20%)
Internal soft-start duration
Slope compensation constant
Power switch OCP detection threshold
5 7
Pulse skipping mode
R
FSW
= 250 k Ω
R
FSW
= 500 k Ω
R
FSW
= 250 k Ω
R
FSW
= 50 k Ω
FSW pin high (LDO3) t
CLK,H
= 250 ns,
V
CLK,L
= 0.8 V, V
CLK,H
= 3.0 V f
CLK
= 100 kHz to 1 MHz, t
CLK,H
= 250 ns f
CLK
= 100 kHz to 1 MHz,
V
CLK,L
= 0.5 V, V
CLK,H
= 2.8 V
Pull-up
100
2.8
250
45
140 180 ns
50 55
MHz
•
k Ω
90 100 110
180 200 220
900 1000 1100
500 600 700 kHz
3
1000
0.5
6
V ns
Ω
Pull-down 1 3
V
VDR
= 5 V, C
L
= 3.3 nF
CSNS pin to PGND
15 30 ns
7 14
2.9
3.5
4.5
ms
3 5 7 A/s
300 360 400 mV
10/26 DocID025575 Rev 4
LED6001 Electrical characteristics
Symbol
Table 6. Electrical characteristics (continued)
Parameter
Output current sensing section
Conditions
V
FB
Feedback voltage (V
VFBP
- V
VFBN differential current sensing voltage)
V
ADIM
= 0.3 V
V
ADIM
= 0.6 V
V
ADIM
= 1.2 V
V
ADIM to LDO3
V
ADIM,OFF
Feedback reference voltage accuracy
ADIM pin voltage turn off threshold
ADIM pin voltage turn off hysteresis
I
VFBP
I
VFBN
Feedback positive input current
Feedback negative input current
V
VFBP
= 12.0 V
V
VFBN
= 11.7 V
V
VFBP
= 12.0 V
V
VFBN
= 11.7 V
PWM dimming control
R
PWMO
PWMO gate driver output resistance
Pull-up
Pull-down t r,PWMO t f,PWMO
PWMO gate driver rise time
(20 to 80%)
PWMO gate driver fall time (80 to 20%)
Fault management section
V
OVFB,th
XFAULT output low level
XFAULT high level leakage current
OVFB input overvoltage detection threshold
OVFB input overvoltage detection hysteresis
OVFB pull-up current
Open load/VFBP pin disconnection detection threshold (differential)
Overload /VFBN pin disconnection detection threshold (differential)
VFBx undervoltage detection threshold
V
VDR
= 5 V, C
L
= 3.3 nF
I
XFAULT
= 4 mA
V
XFAULT
= 5 V
V
OVFB
= 1 V
(V
VFBP
- V
VFBN
)
V
VFBx
respect to SGND
Min. Typ. Max. Unit
20 30 40
110 120 130
280 300 304
288 300 308
260 270 280
5 10 20
-32 -25 -18 mV
μ A
-7 -5 -4
14
3
22
8
50 120
30 60
Ω ns
0.12
0.2
1 4
V
µA
1.14
1.20
1.25
V
70 100 130 mV
0.7
1 1.2
µA
-190 -120 -80 mV
550 600 650
3.0
3.5
4.0
V
DocID025575 Rev 4 11/26
26
Device description
7 Device description
LED6001
The LED6001 device is a LED driver that integrates a boost controller, a high-side current sensing circuitry and a gate driver for an external dimming switch. It has been specifically designed for driving a single string of high-brightness LEDs. The device can support boost, floating buck-boost and SEPIC topologies in order to cover most of applications. A single pin, PWMI, combines both the device enable and PWM dimming control functions.
The brightness of the LED string can be controlled through PWM modulation, analog control of the output current level (by means of a dedicated pin) or a combination of the two.
7.1
7.2
7.2.1
Device supply
The LED6001 device integrates two low dropout linear regulators to derive the + 3.3 V (typ.) main supply and the +5 V supply for the gate drivers. The VIN pin is the input terminal for both linear regulators. Both the linear regulators are enabled when a PWM signal is applied to the PMWI pin. If the PWMI pin is held low for more than 10 ms (min.), the shutdown mode is automatically entered and both the LDOs are turned-off for minimum power consumption.
An undervoltage lockout (UVLO) protection is associated to each linear regulator: in case the output voltage of LDO3 and VDR is below their respective nominal value, the device is no allowed to operate and the XFAULT pin is tied low.
When an external +5 V rail is available, the related internal LDO can be bypassed by connecting together the VIN and VDR pins: in this case the VDR pin is used as supply input.
Boost controller
Turn on and power-down sequences
The LED6001 is turned on and off by acting on the PWMI pin. This digital input combines two functions at the same time: device turn on/off and PWM dimming control.
When a high pulse having a 100 µs (typ.) minimum duration appears at the PWMI pin, the
LDOs are turned on and, after the VDR has reached its nominal value, a soft-start sequence on the boost controller takes place. The output voltage is smoothly increased by releasing in steps the current limit of the boost converter within a fixed 3 ms (typ.) period, unless the feedback voltage reaches 75% of the nominal value in advance.
12/26 DocID025575 Rev 4
LED6001
PWMI
LDO3
VDR
V
OUT t
START
Figure 4. Turn-on and turn-off waveforms t
SHDN t
SS
Device description
I
LED
7.2.2
AM03414
Suddenly after the pulse detection at the PWMI pin, an internal timer is enabled and cleared. The timer starts counting down on every subsequent falling edge. If the PWMI pin is held low for more than 10 ms (typ.), the timer is allowed to expire and the LED6001 automatically turns off minimizing the current consumption.
The start-up time, defined as the delay between the rising edge at the PWMI pin and the first pulse at the GATE pin, clearly depends on the bypass capacitors connected on both LDO3 and VDR pins. With a typical 1 µF MLCC for both pins, the start-up time is in the order of
100 µs.
Boost controller operation
The boost controller of the LED6001 device is based on peak current mode control architecture and can easily support boost, floating buck-boost and SEPIC topologies. The switching frequency of the converter is set through the FSW pin (external clock source or setting resistor toward ground) while the switching duty cycle is modulated by the control loop in order to keep the output (LED) current constant. As a consequence, the output voltage of the boost converter is determined by the LED string.
DocID025575 Rev 4 13/26
26
Device description LED6001
Figure 5. Simplified output regulation circuitry
V
IN
L
C
IN
C
OUT
V
OUT
R
FSW
C
COMP
R
COMP
COMP
V
ADIM
ADIM
FSW
PWMI
_
+ EN
Sync. detector
OSC
EN
I SL
Current ramp generator
50 μA
I SL
Feedback reference setting g m
_
+
30mV 300mV
EN
Enable detector and auto-shutdown counter
S
R
Q
-
+
Q
SW
GATE
PGND
R
SNS
CSNS
R
SLOPE
VFBP
-
+
VFBN
R
VFB
PWMO
Q
DIM
7.2.3
AM03415
The boost controller regulates the output (LED) current by measuring the voltage across the external sensing resistor. The internal circuitry related to the two pins connected to the sensing resistor (VFBP and VFBN) has been designed to implement a high-side sensing scheme and can sustain a relatively high voltage. The voltage drop across the sensing resistor is the actual feedback voltage for the boost regulator control loop and it can be linearly varied by means of the ADIM pin (see
Section 7.3: LED current regulation and brightness control on page 17
for details).
The COMP pin is the output of the transconductance amplifier involved in the regulation loop and a simple RC series must be connected between this pin and SGND to ensure proper loop stability.
Boost converter stability and slope compensation
, the difference between the feedback voltage and the programmed is converted into an error current by the transconductance amplifier. This current, provided at the COMP pin, is turned into a voltage across the compensation network externally connected to the same pin. This voltage, in turn, determines the trip current for the following error amplifier.
When the boost converter operates in continuous conduction mode (CCM) and the switching duty cycle is higher than 50%, sub-harmonic instability may occur.
In order to prevent this, the trip current has to be properly shaped by summing a negative sawtooth ramp voltage (slope compensation) with the amplified error voltage.
14/26 DocID025575 Rev 4
LED6001 Device description
In LED6001 the slope compensation is achieved by injecting a sawtooth current into the
CSNS pin. Therefore the voltage across the CSNS pin is given by:
Equation 1 v
CSNS
(t) = i
MOS
(t) • R
SHUNT
+ i
SL
(t) • R
CSNS
The R
SNS
resistor is usually designed so that the peak voltage is about 15% of the overcurrent threshold at the CSNS pin in order to have a good S/N ratio, while the R
SLOPE resistor is calculated for the desired slope compensation amount (typically at least half the downslope of the inductor current during the switching off-time):
Equation 2
R
SNS
≅
I
50mV
--------------------
Equation 3
R
SLOPE
≥
V
OUT f
–
SW
V
• L
•
R
SNS
--------------
I
SL
Where I
SL
= 50 µA is the maximum current injected by the slope compensation circuitry in the CSNS pin.
Figure 6. Power switch current sensing scheme
V
IN
ISL
OCP
50μA
I
SL
_
+
GATE
CSNS
R
SLOPE
V
SC
360mV
V
SNS
R
SNS
AM03416
DocID025575 Rev 4 15/26
26
Device description
7.2.4 Switching frequency oscillator and external synchronization
LED6001
The switching frequency of the boost controller is simply set by connecting a resistor
between the FSW pin and ground. The resistor can be calculated according to Equation 4 :
Equation 4
R =
K
--------------f
SW
Where K
FSW
= 5 • 10 10 Hz • Ω (typ.) and 100 kHz ≤ f
SW
≤ 1 MHz.
Figure 7. Switching frequency vs. setting resistor at the FSW pin
1000
900
800
700
600
500
400
300
200
100
0
0 50 100 150 200 250
R
FSW
300
)
350 400 450 500 550
AM03417
If the FSW pin is tied high (e.g. connecting it to LDO3), a 600 kHz (typ.) default switching frequency is set.
In case the boost controller of the LED6001 has to be externally synchronized, the FSW pin can be used as synchronization clock input. In this case the external clock must have a frequency in the 100 kHz - 1 MHz range and a 250 ns minimum pulse duration in order to ensure internal oscillator locking.
16/26 DocID025575 Rev 4
LED6001
V
FSW
3 V
Device description
Figure 8. External synchronization signal timing diagram
250 ns
7.3
0.8 V t
AM03418
LED current regulation and brightness control
The brightness of the LEDs connected at the output of the LED6001 can be controlled by applying the desired PWM signal at the PWMI pin. The boost controller is turned on and off according to the duty cycle of the PWMI control signal. When the PWMI is high (and the soft-start has been completed), the output (LED) current is regulated by keeping constant the voltage drop across the external sensing resistor connected between the VFBP and
VFBN pins.
A buffered replica of PWMI is available at the PWMO for driving a dimming N-channel
MOSFET when superior dimming performance is required. In some applications a high-side dimming switch could be desirable (e.g.: protection against output short-circuit to ground or
LED strings using the chassis as return) and a P-channel MOSFET can be used as shown in
Figure 9 . Some additional components may be needed to avoid excessive voltage
between the gate and the source of such MOSFET.
DocID025575 Rev 4 17/26
26
Device description LED6001
V
IN
C
IN
Figure 9. High-side dimming control by using a P-channel MOSFET
L
BOOST
D
FW
V
OUT
C
OUT
R
OVFBH
VIN
R
GATE
C
LDO3
V
LDO3
LDO3
GATE
CSNS
Q
SW
V
OVFB
R
OVFBL
R
SLOPE
R
SNS
VDR
PGND
C
VDR
VFBP
XFAULT LED6001
PWMI
VFBN
FSW V
OVFB
R
GL
D
Z
R
VFB
R
GH
R
FSW
V
LDO3
OVFB
Q
DIMH
ADIM
R
COMP Q
DIML
PWMO
COMP
C
COMP
SGND
AM03419
The regulation loop continuously compares the differential voltage drop with an internal reference and adjusts the switching duty cycle accordingly. In order to provide design flexibility and analog dimming capability, the internal feedback reference can be changed
through the ADIM pin. As visible in Figure 10 , the reference voltage is proportional to the
voltage at the ADIM pin within a limited range.
Equation 5
18/26 DocID025575 Rev 4
LED6001 Device description
Figure 10. Differential feedback reference voltage vs. ADIM pin voltage
V
REF
300 mV
30 mV
260 mV 300 mV 1.2 V
V ADIM
AM03420
In case a fixed output (LED) current is needed or simple PWM dimming is used, the ADIM pin must be connected to the central tap of a resistor divider (supplied by the LDO3 pin) for the desired LED current level. Because of the best LED current accuracy overtemperature is obtained at full scale, a voltage higher than 1.2 V should be applied at the ADIM pin in case the analog dimming is not needed.
If an analog dimming control is required, the voltage at the ADIM pin can be changed runtime within its functional range. A simple way to perform an analog dimming is easily achieved by extracting the average value of a PWM signal through a simple RC low-pass
Figure 11. Simple ADIM pin voltage control through a filtered PWM signal
R f
C f
PWMI
ADIM
LED6001
SGND
AM03421
If the voltage at the ADIM pin is lower than 260 mV, both the PWMO and GATE pins are forced low and the boost converter is temporary disabled. As soon as the ADIM pin voltage is driven inside the operating range, normal operation is resumed.
DocID025575 Rev 4 19/26
26
Device description
7.4
7.4.1
7.4.2
7.4.3
Device protections
LED6001
Linear regulators undervoltage lockout
Both the 5 V and 3.3 V linear regulators of the LED6001 are equipped with an undervoltage lockout (UVLO) protection. The UVLO protections avoid improper device operation in case at least one of the two outputs (VDR and LDO3) is below the allowed level. In particular, the
LED6001 performs the soft-start sequence only after both VDR and LDO3 cross their respective upper UVLO threshold.
Power switch overcurrent
The current flowing through the external power MOSFET is monitored, cycle-by-cycle, by sensing the voltage across the shunt resistor in series with its source. If the voltage drop exceeds the overcurrent protection (OCP) level, the ongoing switching cycle is suddenly terminated (cycle-by-cycle power MOSFET OCP). Normal operation is automatically resumed once the root cause has been removed. The XFAULT pin is not affected by OCP.
As explained in
Section 7.2 on page 12 the slope compensation is added by injecting
a sawtooth current at the CSNS pin. As a consequence, the OCP threshold depends on both the slope compensation amount and the boost converter's operating point:
Equation 6
I =
V – D • I
SL
• R
----------------------------------------------------------------------------------
R
SNS
Where V
CSNS,OCP
= 360 mV (typ.), I
SL
= 50 µA (typ.) and D is the switching duty cycle.
Output overvoltage and OVFB pin disconnection
The output overvoltage fault detection is achieved by comparing the voltage at the OVFB pin with an internal threshold. Because of this fault can potentially damage both the device and the external components, a latched turn off condition is triggered once this event has been detected. A resistor divider connected to the output of the boost converter sets the desired OVP threshold.
The OVFB is internally pulled-up in order to protect the device against an OVFB pin disconnection fault: if the pin is left floating, the OVP is suddenly triggered regardless of the output voltage level. This small pull-up current (I
OVFB,PU
) must be taken into account when
designing an OVP output divider involving high resistance values. Equation 7 allows setting
the desired output OVP level (R
OVPH
and R
OVPL
are the two resistors of the output divider whose central tap is connected to the OVFB pin of LED6001):
Equation 7
V =
R
-------------------------------------------
R
+ R
OVPL
OVPL
V – R
OVPL
• I
Where V
TH,OVFB
= 1.2 V (typ.) and I
OVFB,PU
= 1 µA (typ.).
Once the OVP faulty condition is detected, the LED6001 device suddenly stops switching.
Both GATE and PWMO are forced low and the XFAULT pin is lowered. The condition is
20/26 DocID025575 Rev 4
LED6001 Device description latched and normal operation is resumed by toggling the PWMI pin (PWMI has to be low for more than 10 ms) after the root cause has been removed.
7.4.4 Output rail disconnection detection or output short-circuit to ground
If the connection between the output rail and the output sensing resistor is lost, the voltage of both the VFBP and VFBN pins falls down to zero. The LED6001 detects this faulty condition by comparing the absolute voltage of both VFBP and VFBN pins with an internal
3.3 V threshold and latches-off as a consequence (the GATE and PWMO pins forced low,
XFAULT pin lowered). Normal operation is resumed by toggling the PWMI pin (PWMI has to be low for more than 10 ms) after the root cause has been removed.
When the LED6001 is operating with a boost topology, a similar condition occurs in case of output-to-ground short-circuit. Of course, because of the inherent path between input and output, a real protection against this faulty condition can be achieved only if the device is capable of disconnecting the boost output by means of the dimming switch (e.g. in case a P-channel MOSFET is used as a high-side dimming switch).
V
IN
Figure 12. Load disconnection (1 and 5), open feedback (2 and 3) and open OVFB faulty conditions
L
BOOST D
FW
V
OUT
C
IN
C
OUT
VIN
R
GATE
C
VDR
VDR
GATE
CSNS
Q
SW
V
LDO3
R
SLOPE
1
R
SNS
C
LDO3
LDO3
PGND
XFAULT
LED6001
VFBP
PWMI VFBN
V
FB
2
3
R
VFB
R
ADIML
R
ADIMH
R
FSW
V
LDO3
ADIM
FSW
OVFB
4
V
OVFB
V
OUT
R
OVFBH
R
OVFBL
PWMO
COMP
C
COMP
R
COMP
SGND
5
Q
DIM
AM03422
DocID025575 Rev 4 21/26
26
Device description LED6001
7.4.5 Thermal shutdown
The LED6001 implements an autorestarting thermal protection in order to avoid damages due to excessive die temperature. Once the chip temperature reaches the upper overtemperature protection (OTP) threshold, the ongoing operation is suddenly stopped, both the PWMO and XFAULT pins are held low and the 5 V linear regulator (VDR pin) is turned off. As soon as the die temperature drops below the autorestarting threshold, a new soft-start sequence takes place if the PWMI pin is still high and a 1 ms (typ.) deglitch delay has expired.
The XFAULT pin goes low as soon as the OTP threshold is crossed and it is released once the device temperature drops below a third threshold, lower than the restart one, in order to provide a stable information to the host system.
Faulty condition
Table 7. Faulty conditions management summary
Detection mechanism Consequence
1
2
Output rail/load disconnection
Open feedback (VFBP)
Open feedback (VFBN)
V
VFBP
V
-
VFBx
<3.5 V
VVFBN
<-120 mV
3 LED overcurrent
Output to GND short-circuit
(1)
Open OVFB path
V
VFBP
-
VVFBN
> 600 mV
Device turning-off (latched condition).
GATE, PWMO and XFAULT pins are forced low.
4 V
OVFB
> 1.2 V (internal pull-up)
5
Open PWMO (loss of dimming
MOSFET control)
Output overvoltage
V
OVFB
> 1.2 V
Power switch overcurrent V
CSNS
> 360 mV Ongoing switching cycle terminated
IC overtemperature T
J
> 160 °C (typ.)
Device turning-off (VDR off, LDO3 active).
GATE, PWMO and XFAULT pins are forced low.
Autorestart if T
J
< 140 °C (typ.) and
PWMI still high.
XFAULT pin is released
If T
J
<120 °C (typ.).
1. Output-to-ground short-circuit protection can be achieved only if the device can effectively disconnect the output by acting on the PWMO pin (e.g. a high-side P-channel MOSFET is used as a dimming switch).
22/26 DocID025575 Rev 4
LED6001
8 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
Figure 13. HTSSOP-16 package outline
DocID025575 Rev 4 23/26
26
Package information LED6001
)
Table 8. HTSSOP-16 package mechanical data (1)
Dimensions (mm)
Symbol Note
Min.
Typ.
Max.
D1
E
E1
E2 e
L
L1 k aaa
A
A1
A2 b c
D
0.80
0.19
0.09
4.90
6.20
4.30
0.45
1.00
5.00
3.00
6.40
4.40
3.00
0.65
0.60
1.00
1.20
0.15
1.05
0.30
0.20
5.10
6.60
4.50
0.75
(1)
(2)
(3)
(4)
0.00
8.00
0.10
1. HTSSOP stands for “Thermally Enhanced Variations”.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.
3. The size of exposed pad is variable depending of leadframe design pad size. End user should verify “D1” and “E2” dimensions for each device application.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.
24/26 DocID025575 Rev 4
LED6001
9 Revision history
Date
22-Nov-2013
13-Feb-2014
26-Jun-2014
1 0 Apr -202 0
Revision history
Table 9. Document revision history
Revision Changes
1 Initial release.
2
Updated Figure 2: Pin connection (through top view) on page 4 (renumbered CSNS pin from 8 to 9, switched names of PWMO and CSNS pins).
3
Updated
Section : Applications on page 1
(replaced by new applications).
Minor modifications throughout document.
4
Table 3: Absolute maximum ratings
.
DocID025575 Rev 4 25/26
26
LED6001
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26/26 DocID025575 Rev 4
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