STLVD111
Programmable low voltage
1:10 differential LVDS clock driver
Features
■
■
■
■
■
■
■
■
■
100ps part-to part skew
50ps bank skew
Differential design
Meets LVDS spec. for driver outputs and receiver inputs
Reference voltage available output V
BB
Low voltage V
CC range of 2.375V to 2.625V
High signalling rate capability (exceeds
622MHz)
Support open, short and terminated input failsafe (low output state)
Programmable drivers power off control
Description
The STLVD111 is a low skew programmable 1 to
10 differential LVDS driver, designed for clock distribution. The select signal is fanned out to 10 identical differential outputs.
The STLVD111 is provided with a 11 bit shift register with a serial in and a Control Register.
The purpose is to enable or power off each output clock channel and to select the clock input. The
TQFP32
STLVD111 is specifically designed, modelled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device.
The STLVD111 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can take advantage of the device’s performance to distribute low skew clocks across the backplane or the board.
Obsolete Product(s) - Obsolete Product(s)
Order codes
Part number
STLVD111BFR
May 2007
Temperature range
-40 to 85 °C
Package
TQFP32 (Tape & Reel)
Rev. 8
Packaging
2400 parts per reel
1/19 www.st.com
19
STLVD111
5
6
7
Contents
3
4
1
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Specification of control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
Programmed mode (EN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
Standard mode (EN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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STLVD111
Figure 1.
Pin connections
Pin configuration
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Pin configuration STLVD111
Table 1.
Pin description
Pin n° Symbol Name and function
21
22
23
24
25
15
16
17
18
19
20
9
10
11
12
13
14
3
4
1
2
5
6
7
8
GND
Q9
Q9
Q8
Q8
Q7
Q7
V
CC
Q6
CK
SI
CLK0
CLK0
V
BB
CLK1
CLK1
EN
Q4
Q4
Q3
Q6
Q5
Q5
Q3
GND
Control register clock
Control register serial IN/CLK_SEL
Differential input
Differential input
Output reference voltage
Differential input
Differential input
Device enable/program
Ground
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Supply voltage
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Differential outputs
Ground
26
27
Q2
Q2
Differential outputs
Differential outputs
28 Q1 Differential outputs
29
30
31
32
Q1
Q0
Q0
V
CC
Differential outputs
Differential outputs
Differential outputs
Supply voltage
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STLVD111
2 Maximum
Table 2.
Symbol
Absolute maximum ratings
Parameter
V
CC
V
I
V
O
I
OSD
ESD
Supply voltage
Input voltage
Output voltage
Driver short circuit current
Electrostatic discharge (HBM 1.5K
Ω, 100pF)
Maximum ratings
Value
-0.3 to 2.8
-0.2 to (V
CC
+0.2)
-0.2 to (V
CC
+0.2)
Continuous
>2
Note:
Table 3.
Symbol
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
Recommended operating conditions
Parameter Min.
Typ.
Max.
Unit
V
CC
V
IC
T
A
T
J
Supply voltage
Receiver common mode input voltage
Operating free-air temperature range
Operating junction temperature
2.375
0.5(V
ID
)
-40
-40
2.625
2-0.5(V
ID
)
85
105
V
V
°C
°C
Table 4.
Symbol
R thJC
Thermal data
Parameter
Thermal resistance junction-case
Value
13
Unit
°C/W
Unit
V
V
V
KV
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Electrical characteristics STLVD111
Table 5.
Symbol
V
OD
Δ V
OD
V
OS
Δ V
OS
I
OS
Driver electrical characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless otherwise specified
Note: 1
,
2 )
Parameter Test condition Min.
Typ.
Max.
Unit
Output differential voltage (
Figure 4.
) R
L
= 100 Ω
V
OD
magnitude change
Offset voltage -40 ≤
A
85°C
V
OS
magnitude change
V
O
= 0V
Output short circuit current
V
OD
= 0V
400
1.05
500
1.15
15
7
600
30
1.25
30
30
15 mV mV
V
V mA
Note: 1 All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
2 All typical values are given for V
CC
= 2.5V and T
A
= 25°C unless otherwise stated
Table 6.
Symbol
V
IDH
V
IDL
I
IN
Receiver electrical characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless otherwise specified
Note: 1 , 2 )
Parameter Test condition Min.
Typ.
Max.
Unit
Input threshold high
Input threshold low -100
100 mV mV
Input current
V
I
= 0V
V
I
= 0V
CC
42
2
100
10
μ A
Note: 1 All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
2 All typical values are given for V
CC
= 2.5V and T
A
= 25°C unless otherwise stated
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STLVD111 Electrical characteristics
Table 7.
Driver electrical characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless otherwise specified
Note: 1
,
2 )
Parameter Test condition Min.
Typ.
Max.
Unit Symbol
V
BB
I
CCD
C
IN
C
OUT
V
IH
V
IL
I
I
Output reference voltage
Power supply current
Input capacitance
Output capacitance
Logic input high threshold
Logic input low threshold
Logic input current
V
CC
= 2.5 V
All driver enabled and loaded
V
I
= 0V to V
CC
V
CC
= 2.5 V
V
CC
= 2.5 V
V
CC
= 2.5 V, V
IN
= V
CC
or GND
1.15
2
1.25
125
5
5
1.35
160
0.8
±10
V mA pF pF
V
V
µA
Note: 1 All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified
2 All typical values are given for V
CC
= 2.5V and T
A
= 25°C unless otherwise stated
Table 8.
Symbol t
TLH, t
THL t
PHL, t
PLH f
MAX t
SKEW
LVDS timing characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless otherwise specified)
Parameter Min.
Typ.
Max.
Unit
Transition time
Propagation delay time
Test condition
R
L
= 100 Ω , C
L
= 5 pF,
Figure 7.
,
Figure 8.
)
(
Figure 7.
, Figure 8.
)
220
2
300
2.5
ps ns
700 MHz Maximum input frequency
Bank skew
Part to part skew
Pulse skew
(
Figure 3.
)
(
Figure 4.
)
(
Figure 5.
)
900
50
100
50 ps
Table 9.
Control register timing characteristics (T
A
= -40 to 85 °C, V
CC
= 2.5V ± 5%, unless otherwise specified)
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
Obsolete Product(s) - Obsolete Product(s) t s
100 150
Clock to SI setup time
( Figure 9.
) 2
MHz ns
Clock to SI hold time
( Figure 9.
) 1.5
ns t h t rem
Enable to clock removal time
( Figure 9.
) 1.5
ns t
W
Minimum clock pulse width
( Figure 9.
) 3 ns
7/19
Specification of control register
4 Specification of control register
STLVD111
The STLVD111 is provided with a 11 bit shift register with a Serial In and a Control Register.
The purpose is to enable or power of each output clock channel and to select the clock input. The STLVD111 provides two working modality:
The shift register have a serial input to load the working configuration. Once the configuration is loaded with 11 clock pulse, another clock pulse load the configuration into the control register. The first bit on the serial input line enables the outputs Q9 and Q9, the second bit enables the outputs Q8 and Q8 and so on. The last bit is the clock selection bit.
To restart the configuration of the shift register a reset of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register shift register can be configured on time after each reset.
4.2 Standard mode (EN=0)
In Standard Mode the STLVD111 isn’t programmable, all the clock outputs are enabled. The
LVDS clock input is selected from Clock 0 or Clock 1 with the SI pin as shown in the Truth
Table below.
Table 10.
Truth table of state machine inputs
EN SI CK
L
L
H
H
L
L
H
L
H
X
X
X
Output
All output enabled, Clock 0 selected, control register disabled
All output enabled, Clock 1 selected, control register disabled
First stage stores "L", other stages store the data of previous stage
First stage stores "H", other stages store the data of previous stage
Reset of the state machine, shift register and control register
Table 11.
Serial input sequence
BIT#10 BIT#9 BIT#8 BIT#7 BIT#6 BIT#5 BIT#4 BIT#3 BIT#2 BIT#1 BIT#0 Obsolete Product(s) - Obsolete Product(s)
CLK_SEL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Table 12.
Truth table of the control register
BIT#10 BIT#(0-9)
L
H
X
H
H
L
Qn(0-9)
Clock 0
Clock 1
Qn Output Disabled
8/19
STLVD111
Table 13.
Truth table
CK EN
L
L
L
L
L
L
L
L
L
L
L
L
All drivers enable
SI
L
H
L
L
H
H
Specification of control register
CLK 0
L
H
Open
X
X
X
CLK 0
H
L
Open
X
X
X
CLK 1
X
L
X
X
H
Open
CLK 1
X
H
X
X
L
Open
Q (0-9)
L
L
L
H
H
L
Q(0-9)
H
H
H
L
L
H
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Diagram
5 Diagram
Figure 2.
Logic diagram
STLVD111
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Diagram STLVD111
Figure 3.
Bank skew - t sk(b)
(1)
1.
BANKSKEW is the magnitude of the time difference between outputs with a single driving input terminal
Figure 4.
Part to part skew - t sk(PP)
(1)
Obsolete Product(s) - Obsolete Product(s)
1.
PART TO PART SKEW is the magnitude of the difference in propagation delay times between any specific terminals of two devices when both devices operate with the same input signals, the same supply voltages, and the same temperature, and have identical packages and test circuits.
11/19
Diagram
Figure 5.
Pulse skew - t sk(P)
(1)
STLVD111
1.
PULSE SKEW is the magnitude of the time difference between the high to low and low to high propagation delay times at an output.
Figure 6.
Voltage and current definition
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STLVD111
Figure 7.
Test circuit and voltage definition for the differential output signal
Diagram
.
Figure 8.
Differential receiver to drive propagation delay and drive transition time waveforms
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Diagram STLVD111
Figure 9.
Set-Up, hold and the removal time, maximum frequency, minimum pulse width waveforms
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STLVD111
6 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK
® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
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Package mechanical data STLVD111
DIM.
L
L1
K e
E
E1
E3
C
D
D1
D3
A
A1
A2
B
MIN.
0.05
1.35
0.30
0.09
0.45
0°
9.00
7.00
5.60
0.60
9.00
7.00
5.60
0.80
1.00
3.5°
TQFP32 MECHANICAL DATA mm.
TYP MIN.
1.40
0.37
MAX.
1.6
0.15
1.45
0.45
0.20
0.002
0.053
0.012
0.0035
0.75
7°
0.018
0° inch
TYP.
0.055
0.015
0.354
0.276
0.220
0.031
0.354
0.276
0.220
0.024
0.039
3.5°
MAX.
0.063
0.006
0.057
0.018
0.0079
0.030
7°
D
D1
D3
A
A2
A1
25
24 17
16
0.10mm
.004
Seating Plane
Obsolete Product(s) - Obsolete Product(s)
9
32
8
1
C e
K
TQFP32
0060661/C
16/19
DIM.
T
Ao
Bo
Ko
Po
P
A
C
D
N
STLVD111 Package mechanical data
9.5
9.5
2.1
3.9
11.9
MIN.
12.8
20.2
60
Tape & Reel TQFP32 MECHANICAL DATA mm.
TYP MIN.
MAX.
330
13.2
inch
TYP.
0.504
0.795
2.362
22.4
9.7
9.7
2.3
4.1
12.1
0.374
0.374
0.083
0.153
0.468
MAX.
12.992
0.519
0.882
0.382
0.382
0.091
0.161
0.476
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Revision history
7 Revision history
STLVD111
Table 14.
Revision history
Date Revision
30-May-2007 8
Changes
Order codes has been updated and the document has been reformatted.
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STLVD111
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