I/O1
GND 2
I/O2 3
6 I/O1
5 V
BUS
4 I/O2
Functional diagram (top view)
Product status link
USBLC6-2
USBLC6-2
Datasheet
Very low capacitance ESD protection
Features
• 2 data-line protection
• Protects VBUS
• Very low capacitance: 3.5 pF max.
• Very low leakage current: 150 nA max.
• SOT-666 and SOT23-6L packages
• RoHS compliant
Benefits
• Very low capacitance between lines to GND for optimized data integrity and speed
• Low PCB space consumption: 2.9 mm² max for SOT-666 and 9 mm² max for
SOT23-6L
• Enhanced ESD protection: IEC 61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level
• ESD protection of VBUS
• High reliability offered by monolithic integration
• Low leakage current for longer operation of battery powered devices
• Fast response time
• Consistent D+ / D- signal balance:
– Very low capacitance matching tolerance I/O to GND = 0.015 pF
– Compliant with USB 2.0 requirements
Complies with the following standards:
• IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
Applications
• USB 2.0 ports up to 480 Mb/s (high speed)
• Compatible with USB 1.1 low and full speed
• Ethernet port: 10/100 Mb/s
• SIM card protection
• Video line protection
• Portable electronics
Description
The USBLC6-2SC6 and USBLC6-2P6 are monolithic application specific devices dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet links and video lines.
The very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringently characterized
ESD strikes.
DS4260 - Rev 7 - December 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Characteristics
Symbol
V
PP
T stg
T j
T
L
Table 1. Absolute ratings (T amb
= 25 °C)
Peak pulse voltage
Parameter
IEC 61000-4-2 level 4 standard:
Air discharge
Contact discharge
MIL STD883G-Method 3015-7
Storage temperature range
Operating junction temperature range
Maximum lead temperature for soldering during 10 s at 5 mm
Symbol
I
RM
V
BR
V
F
V
CL
C i/o-GND
ΔC i/o-GND
C i/o-i/o
ΔC i/o-i/o
Parameter
Leakage current
Breakdown voltage between
V
BUS
and GND
Forward voltage
Table 2. Electrical characteristics (T amb
= 25 °C)
Test conditions
V
RM
= 5.25 V
Min.
Value
Typ.
10
I
R
= 1 mA 6
Clamping voltage
I
F
= 10 mA
I
PP
= 1 A, 8/20 μs
Any I/O pin to GND
I
PP
= 5 A, 8/20 μs
Any I/O pin to GND
Capacitance between I/O and
GND
V
R
= 1.65 V 2.5
0.015
Capacitance between I/O
V
R
= 1.65 V 1.2
0.04
Value
15
15
25
-55 to +150
-40 to +150
260
Max.
150
1.1
12
17
3.5
1.7
USBLC6-2
Characteristics
Unit kV
Unit nA
V
V
°C
°C
°C
V pF pF
DS4260 - Rev 7 page 2/20
USBLC6-2
Characteristics (curves)
1.1
Characteristics (curves)
Figure 1. Capacitance versus voltage (typical values)
3.0
C(pF)
2.5
2.0
1.5
1.0
V
F=1MHz
OSC j
=30mV
T =25°C
RMS
0.5
0.0
0.0
0.5
1.0
1.5
Data line voltage (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 2. Line capacitance versus frequency (typical values)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.8
2.6
2.4
2.2
2.0
C(pF)
1 1 0
F(MHz)
1 0 0
V
OSC
=30mV
T =25°C
RMS
V
LINE
=0V to 3.3V
1 0 0 0
Figure 3. Relative variation of leakage current versus junction temperature (typical values)
100
I [T ] / I [T = 25 °C]
V
BUS
= 5 V
10
0.00
S21(dB)
Figure 4. Frequency response
-5.00
-10.00
-15.00
-20.00
100.0k
1.0M
10.0M
F(Hz)
100.0M
1.0G
1
25 50 75 100 125 150
DS4260 - Rev 7 page 3/20
2
2.1
Note:
2.2
USBLC6-2
Technical information
Technical information
Surge protection
The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology.
The clamping voltage V
CL
can be calculated as follow:
V
CL
+ = V
TRANSIL
+ V
F
for positive surges
V
CL
- = - V
F
for negative surges with: V
F
= V
T
+ R d
.Ip
(V
F
forward drop voltage) / (V
T
forward drop threshold voltage) and V
TRANSIL
= V
BR
+ R d_TRANSIL
.I
P
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
R d
= 0.5 Ω and V
T
= 1.1 V
We assume that the value of the dynamic resistance of the transil diode is typically:
R d_TRANSIL
= 0.5 Ω and V
BR
= 6.1 V For an IEC 61000-4-2 surge level 4 (Contact Discharge: V g
= 8 kV, R g
= 330
Ω), V
BUS
= +5 V, and if in first approximation, we assume that:
I p
= V g
/ R g
= 24 A.
So, we find:
V
CL
+ = +31.2 V
V
CL
- = -13 V
The calculations do not take into account phenomena due to parasitic inductances.
Surge protection application example
If we consider that the connections from the pin V
BUS
to V
CC
, from I/O to data line and from GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances L
VBUS
, L
I/O and L
GND
of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (t r
= 1 ns), the voltage V
CL
has an extra value equal to L
I/O
.dl/dt + L
GND
.dI/dt.
The dI/dt is calculated as: dI/dt = I p
/t r
= 24 A/ns
The overvoltage due to the parasitic inductances is:
L
I/O
.dl/dt = L
GND
.dI/dt = 6 nH x 24 A/ns = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be:
V
CL
+ = +31.2 + 144 + 144 = 319.2 V
V
CL
- = -13.1 - 144 - 144 = -301.1 V
We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some recommendations have to be followed (see ).
DS4260 - Rev 7 page 4/20
DS4260 - Rev 7
USBLC6-2
Surge protection application example
Figure 5. ESD behavior: parasitic phenomena due to unsuitable layout
ESD surge on data line
L
I/O
L
I/O di dt
L
VBUS
V
CC pin
V
F
I/O pin
V
TRANSIL
V
CL
V
BUS
Data line
L
GND
GND pin
L
GND di dt
L
I/O di dt
+ L
GND di dt
V
TRANSIL
+ V
F
- V
F
V
CL + = V TRANSIL
+ V + L
I/O di dt
V
CL-
= -V - L
I/O di dt
- L
GND di dt
+ L
GND di dt
V
TRANSIL
V
BR
+ Rd.Ip
= surge > 0 surge > 0
-L
I/O di dt
- L
GND di dt
V
CL+
V
CL-
Positive
Surge
Negative
Surge t t page 5/20
USBLC6-2
How to ensure good ESD protection
2.3
How to ensure good ESD protection
While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena
(see
Figure 6. ESD behavior: layout optimization
and Figure 5. ESD behavior: parasitic phenomena due to unsuitable layout
for layout consideration).
Figure 6. ESD behavior: layout optimization Figure 7. ESD behavior: measurement conditions
ESD SURGE
TEST BOARD
IN OUT
2
3
Unsuitable layout
4
5
6
2
3
Optimized layout
5
4
6
Figure 8. ESD response to IEC 61000-4-2 (+15 kV air discharge)
+5 V
Figure 9. ESD response to IEC 61000-4-2 (-15 kV air discharge)
Note: Important: A good precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector).
DS4260 - Rev 7 page 6/20
2.4
2.4.1
USBLC6-2
Crosstalk behavior
Crosstalk behavior
Crosstalk phenomenon
V
G1
R
G1
R
G2
Figure 10. Crosstalk phenomenon
Line 1
R
L1
Line 2
V
G2
DRIVERS
α
1
V
G1
+ β
12
V
G2
R
L2
RECEIVERS
α
2
V
G2
+ β
21
V
G1
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on load R
L2
is α
2
V
G2
, in fact the real voltage at this point has got an extra value β
21
V
G1
. This part of the V
G1
signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ).
Figure 11. Analog crosstalk measurements
NETWORK ANALYSER
PORT 1
TEST BOARD
NETWORK ANALYSER
PORT 2
Vbus
Figure 11. Analog crosstalk measurements
shows the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see
Figure 12. Analog crosstalk results ).
DS4260 - Rev 7 page 7/20
DS4260 - Rev 7
USBLC6-2
Crosstalk behavior
0.00
Figure 12. Analog crosstalk results dB
- 30.00
- 60.00
- 90.00
- 120.00
100.0k
F (Hz)
1.0M
10.0M
100.0M
1.0G
As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating
signals. The frequency response ( Figure 4. Frequency response
) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies, for instance.
page 8/20
2.5
Application examples
Figure 13. USB 2.0 port application diagram using USBLC6-2
USBLC6-2
Application examples
DEVICE-
UPSTREAM
TRANSCEIVER
SW
2
+ 3.3V
R
PU
SW
1
V BUS
R
X LS/FS
R
X HS
R
T X HS
+
X LS/FS -
R
X HS -
T
X HS -
+
+
GND
T
X LS/FS
+
T
X LS/FS -
R
S
R
S
USBLC6-2SC6
USB connector
V
BUS
D+
D-
GND
+ 5V
Protecting
Bus Switch
HUB-
DOWNSTREAM
TRANSCEIVER
R
PD
R
S
R
S
V BUS
R
X LS/FS
R
X HS
T X HS
X LS/FS -
R
X HS -
T
X HS -
+
GND
T
X LS/FS
+
T
X LS/FS -
R
PD
DEVICE-
UPSTREAM
TRANSCEIVER
SW
2
+ 3.3V
R
PU
SW
1
V
BUS
R
X LS/FS
R
X HS
T
X HS
+
R
X LS/FS -
R
X HS -
T
X HS -
+
+
GND
T
X LS/FS
+
T
X LS/FS -
R
S
R
S
USBLC6-2P6
USB connector
V
BUS
D+
D-
GND
USBLC6-4SC6
R
PD
R
S
R
S
R
X LS/FS
R
X HS
T
X HS
R
X LS/FS -
R
X HS -
T X HS -
+
+
+
GND
T
X LS/FS
+
T X LS/FS -
R
PD
Mode
Low Speed LS
Full Speed FS
High Speed HS
SW 1
Open
Closed
Closed then open
SW 2
Closed
Open
Open
DS4260 - Rev 7 page 9/20
USBLC6-2
PSpice model
Figure 14. T1/E1/Ethernet protection
Tx
SMP75-8
+V
CC
100nF
DATA
TRANSCEIVER
Rx
SMP75-8
+V
CC
100nF
2.6
PSpice model
Figure 15. PSpice model shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined by
the PSpice parameters given in Figure 16. PSpice parameters .
Figure 15. PSpice model
D+in
GND
D-in
LI/O
LGND
LI/O
RI/O
RGND
MODEL = Dlow MODEL = Dhigh
MODEL = Dzener
MODEL = Dlow MODEL = Dhigh
RI/O
RI/O LI/O
RI/O LI/O
RI/O LI/O
D+out
VBUS
D-out
Note: This simulation model is available only for an ambient temperature of 27 °C.
DS4260 - Rev 7 page 10/20
USBLC6-2
PSpice model
Figure 17. USBLC6-2 PCB layout considerations Figure 16. PSpice parameters
BV
CJ0
IBV
M
RS
VJ
TT
Dlow
50
0.9p
1m
0.3333
0.2
0.6
0.1u
Dhigh
50
2.0p
1m
0.3333
0.52
0.6
0.1u
Dzener
7.3
40p
1m
0.3333
0.84
0.6
0.1u
LI/O
RI/O
LGND
RGND
750p
110m
550p
60m
D+in
GND
D-in
1
USBLC6-2
D+out
V
BUS
C
BUS
= 100nF
D-out
DS4260 - Rev 7 page 11/20
3
3.1
USBLC6-2
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
SOT23-6L package information
Figure 18. SOT23-6L package outline
A c
θ
H
E
L
A1
D b e e
A2
Table 3. SOT23-6L package mechanical data
Dimensions
Ref.
A
A1
A2 b c
D
E e
H
L
θ
Min.
0.9
0
0.9
0.30
0.09
2.8
1.5
2.6
0.3
0
Millimeters
Typ.
0.95
Max.
1.45
0.15
1.3
0.5
0.2
3.05
1.75
3
0.6
10
Min.
0.0354
0
0.0354
0.0118
0.0035
0.1102
0.0591
0.1024
0.0118
0
1. Value in inches are converted from mm and rounded to 4 decimal digits
Inches
(1)
Typ.
0.0374
Max.
0.0571
0.0059
0.0512
0.0197
0.0079
0.1201
0.0689
0.1181
0.0236
0.3937
DS4260 - Rev 7 page 12/20
USBLC6-2
SOT23-6L package information
Figure 19. Footprint recommendations, dimensions in mm (inches)
0.60
(0.024)
3.50
(0.138)
2.30
(0.091)
0.95
(0.037)
1.20
(0.047)
1.10
(0.043)
DS4260 - Rev 7 page 13/20
3.2
SOT-666 package information
Figure 20. SOT-666 package outline b
L1
USBLC6-2
SOT-666 package information
D
A
E1
E
L2
A3 e
Table 4. SOT-666 package mechanical data
Ref.
A
A3 b
D
E
E1 e
L1
L2
Min.
0.45
0.08
0.17
1.50
1.50
1.10
0.10
Millimeters
Typ.
0.50
0.19
Max.
0.62
0.18
0.34
1.70
1.70
1.30
0.30
1. Value in inches are converted from mm and rounded to 4 decimal digits
Dimensions
0.004
Min.
0.018
0.003
0.007
0.059
0.059
0.043
Inches (1)
Typ.
0.020
0.007
Max.
0.025
0.007
0.013
0.067
0.067
0.051
0.012
DS4260 - Rev 7 page 14/20
USBLC6-2
SOT-666 package information
Figure 21. Footprint recommendations, dimensions in mm
0.50
0.62
2.60
0.99
0.30
DS4260 - Rev 7 page 15/20
USBLC6-2
Packing information
3.3
Packing information
Figure 22. Marking layout (refer to ordering information table for marking)
Figure 23. Package orientation in reel
X X X X
Figure 25. Reel dimensions (mm)
Figure 24. Tape and reel orientation
Figure 26. Inner box dimensions (mm)
DS4260 - Rev 7 page 16/20
Figure 27. Tape and reel outline
USBLC6-2
Packing information
DS4260 - Rev 7
Ref.
P1
P0
D0
D1
F
K0
P2
W
Table 5. Tape and reel mechanical data
Min.
3.9
3.9
1.45
1
3.45
1.3
1.95
7.9
Dimensions
Millimeters
Typ.
4
4
1.5
3.5
1.4
2
8
3.55
1.6
2.05
8.3
Max.
4.1
4.1
1.6
page 17/20
USBLC6-2
Ordering information
4
Ordering information
Figure 28. Ordering information scheme
USB LC 6 - 2 xxx
Product Designation
Low capacitance
Breakdown Voltage
6 = 6 Volts
Number of lines protected
2 = 2 lines
Packages
SC6 = SOT23-6L
P6 = SOT-666
Table 6. Ordering information
Order code
USBLC6-2SC6
(1)
USBLC6-2P6
(1)
Marking
UL26
F
Package
SOT23-6L
SOT-666
Weight
16.7 mg
2.9 mg
1. The marking code can be rotated by 90° to differentiate assembly location.
Base qty.
3000
3000
Delivery mode
Tape and reel
Tape and reel
DS4260 - Rev 7 page 18/20
USBLC6-2
Revision history
Date
14-Mar-2005
07-Jun-2005
20-Mar-2008
27-Jun-2011
24-Oct-2011
16-Oct-2020
24-Dec-2021
3
4
5
6
7
Table 7. Document revision history
Version
1
2
Changes
Initial release.
Format change to figure 3; no content changed.
Added marking illustrations - Figures 21 and 23. Added ECOPACK statement.
Updated operating junction temperature range in absolute ratings, page 2.
Technical information section updated. Reformatted to current standards.
Updated leakage current for VRM = 5.25 V as specified in USB standard.
Updated marking illustrations Figure 21 and Figure 23.
Updated legal statement.
Minor text changes.
Updated Section ■ Disclaimer
Updated Section 1 Characteristics
DS4260 - Rev 7 page 19/20
USBLC6-2
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© 2021 STMicroelectronics – All rights reserved
DS4260 - Rev 7 page 20/20
