STMicroelectronics FSK power line transceiver Datasheet

ST7538

FSK POWER LINE TRANSCEIVER

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1 FEATURES

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HALF DUPLEX FREQUENCY SHIFT KEYING

(FSK) TRANSCEIVER

INTEGRATED POWER LINE DRIVER WITH

PROGRAMMABLE VOLTAGE AND CURRENT

CONTROL

PROGRAMMABLE INTERFACE:

– SYNCHRONOUS

– ASYNCHRONOUS

SINGLE SUPPLY VOLTAGE (FROM 7.5 UP TO 12.5V)

VERY LOW POWER CONSUMPTION (Iq=5 mA)

INTEGRATED 5V VOLTAGE REGULATOR

(UP TO 100mA) WITH SHORT CIRCUIT

PROTECTION

8 PROGRAMMABLE TRANSMISSION

FREQUENCIES

PROGRAMMABLE BAUD RATE UP TO 4800BPS

RECEIVING SENSITIVITY 250 µ VRMS

SUITABLE TO APPLICATION IN ACCORDANCE

WITH EN 50065 CENELEC SPECIFICATIONS

CARRIER OR PREAMBLE DETECTION

BAND IN USE DETECTION

PROGRAMMABLE REGISTER WITH

SECURITY CHECKSUM

MAINS ZERO CROSSING DETECTION AND

SYNCHRONIZATION

Figure 2. Block Diagram

DVdd AVdd DVss AVss

Figure 1. Package

TEST1 TEST2 TEST3

TQFP44 Slug Down

Table 1. Order Codes

Part Number

ST7538P

■ WATCHDOG TIMER

2 DESCRIPTION

The ST7538 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and a 5V linear regulator. The device operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out, band in use are included.

Realized in Multipower BCD5 technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip.

BU

Package

TQFP44 (Slug down)

RxFo

CD/PD

RxD

CLR/T

CARRIER

DETECTION

PLL

TEST

DIGITAL

FILTER

FSK

DEMOD

IF

FILTER

BU

FILTER

AGC

AMPL

RxTx

TxD

REGOK

FILTER

CONTROL

REGISTER

FSK

MODULATOR

DAC

TX

FILTER

ALC

CURRENT

CONTROL

VOLTAGE

CONTROL

PLI

OSC TIME BASE ZC OP-AMP

+

-

XOut XIn WD TOUT RSTO MCLK ZCout ZCin C_OUT CMINUS CPLUS

VREG

D03IN1407A

RAI

CL

Vsense

ATO

ATOP1

ATOP2

PAVcc

Vdc

PG

November 2005

Rev. 5

1/30

ST7538

Figure 3. Pin Connection (Top view)

CD_PD

DVSS

RXD

RxTx

TXD

GND

TOUT

CLR/T

BU

DVDD

MCLK

7

8

9

3

4

1

2

5

6

10

11

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

33

32

31

30

29

28

27

26

25

24

23

VDC

RAI

RXFO

TEST2

VSENSE

AVDD

XIN

XOUT

SGND

ATO

CL

D01IN1312

Table 2. Pin Description

N°

1

2

3

4

5

Name Type

CD_PD Digital/Output

DVss

RxD

RxTx

TxD

Supply

Digital/Output

Digital/Input with internal pull-up

Description

Carrier or Preamble Detect Output.

"1" No Carrier or Preamble Detected

"0" Carrier or Preamble Detected

Digital Ground

RX Data Output.

Rx or Tx mode selection input.

"1" - RX Session

"0" - TX Session

TX Data Input.

6

7

GND

TOUT

Digital/Input with internal pull-down

Supply

Digital/Output

Substrate Ground (same function as PIN 41)

TX Time Out Event Detection

"1" - Time Out Event Occurred

"0" - No Time-out Event Occurred

8 CLR/T Digital/Output Synchronous Mains Access Clock or Obsolete Product(s) - Obsolete Product(s)

9 BU Digital/Output Band in use Output.

"1" Signal within the Programmed Band

"0" No Signal within the Programmed Band

10

11

12

DVdd

MCLK

RSTO

Supply

Digital/Output

Digital/Output

Digital Supply Voltage

Master Clock Output

Power On or Watchdog Reset Output

2/30

ST7538

Table 2. Pin Description (continued)

N°

13

14

15

16

21

22

23

17

18

19

20

30

31

32

33

34

35

27

28

29

24

25

26

36

Name

TEST 3 Digital/Input with internal pull-down

WD

Type

Digital/Input with internal pull-up

ZCOUT Digital/Output

ZCIN

1 Analog/Input

NC

DVss

Floating

Supply

ATOP1 Power/Output

PAVss Supply

ATOP2 Power/Output

PAV

CC

CL

2

Supply

Analog/Input

ATO Analog/Output

SGND Supply

XOUT Analog I/O

XIN

AVdd

Analog Input

Supply

Vsense

3 Analog/Input

TEST2 Analog/Input

RxFO

RAI

VDC

Analog/Output

Analog/Input

Power

NC floating

TEST1 Digital/Input with internal pull-down

REGOK Digital/Output

Description

Test Input. Must be connected to DVss during Normal Operation

Watchdog input. The Internal Watchdog Counter is cleared on the falling edges.

Zero Crossing Detection Output

Zero Crossing AC Input.

Must be connected to DVss.

Digital Ground

Power Line Driver Output

Power Analog Ground

Power Line Driver Output

Power Supply Voltage

Current Limiting Feedback.

A resistor between CL and AVss sets the PLI Current Limiting Value

Small Signal Analog Transmit Output

Analog Signal Ground

Crystal Output- External Clock Input

Crystal Oscillator Input

Analog Power supply.

Output Voltage Sensing input for the voltage control loop

Test Input must be connected SGND

Receiving Filter Output

Receiving Analog Input

5V Voltage Regulator Output

Must Be connected to DVss.

Test input. Must Be connected to DVss.

Security checksum logic output

"1" - Stored data Corrupted

"0" - Stored data OK

Op-amp Inverting Input.

37

38

39

40

41

C_MINUS

4

C_PLUS

5

Analog/Input

Analog/Input

NC floating

C_OUT Analog/Output

GND Supply

Op-amp Not Inverting Input.

Must Be connected to DVss

Op-amp Output

Substrate Ground (same function as PIN 6)

42 PG Digital/Output Power Good logic Output

"1" - VDC is above 4.5V

Obsolete Product(s) - Obsolete Product(s)

43 REG_DATA Digital/Input Mains or Control Register Access Selector with internal pull-down "1" - Control Register Access

"0" - Mains Access

44 NC floating Must be connected to DVss.

<1>

<2>

<3>

<4>

<5>

If not used this pin must be connected to VDC

Cannot be left floating

Cannot be left floating

If not used this pin must be connected to VDC

If not used this pin must be tied low (SGND or PAVss or DVss)

3/30

ST7538

Table 3. Absolute Maximum Ratings

Symbol

PAV

CC

AV dd

DV dd

Power Supply Voltage

Analog Supply Voltage

Digital Supply Voltage

Parameter

AV ss

/DV ss

Voltage between AV ss

and DV ss

V

I

Digital input Voltage

V

O

I

O

Digital output Voltage

Digital Output Current

V sense

,

XIN,

C_MINUS,

C_PLUS,

CL

Voltage Range at Vsense, XIN, C_MINUS, C_PLUS, CL

Inputs

RAI, ZCIN Voltage Range at RAI, ZCIN Inputs

ATO,

RxFO,

C_OUT,

XOUT

Voltage range at ATO, RxFO, C_OUT, XOUT Outputs

ATOP1,2 Voltage range at Powered ATO Output

ATOP Powered ATO Output Current (*)

T amb

T stg

Operating ambient Temperature

Storage Temperature

ATOP1 Pin Maximum Withstanding Voltage Range

ATOP2 Pin

Test Condition: CDF-AEC-Q100-002- “Human Body Model”

Acceptance Criteria: “Normal Performance”

Other pins

(*) This current is intended as not repetitive pulse current

Value

-0.3 to +14

-0.3 to +5.5

-0.3 to +5.5

-0.3 to +0.3

DV ss

- 0.3 to DV dd

+0.3

DV ss

- 0.3 to DV dd

+0.3

-2 to +2

AV ss

- 0.3 to AV dd

+0.3

Unit

V

V

V

V

V

V mA

V

-AV dd

- 0.3 to AV dd

+0.3

AV ss

- 0.3 to AV dd

+0.3

V

V

AV ss

- 0.3 to +PAV cc

+0.3

400

-40 to +85

-50 to 150

±1500

±1000

±2000

V mArms

°C

°C

V

V

V

Table 4. Thermal Data

Symbol Parameter

R th-j-amb1

R th-j-amb2

Maximum Thermal Resistance Junction-Ambient Steady State(*)

Maximum Thermal Resistance Junction-Ambient Steady State(**)

(*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB

(**) It's the same condition of the point above, without any heatsinking surface on the board.

TQFP44 with slug

35

50

Unit

°

C/W

°

C/W

4/30

ST7538

Table 5. Electrical Characteristcs

(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, Fc = 86kHz, other Control

Register parameters as default value, unless otherwise specified).

Symbol

AV

CC

,

DV

CC

Parameter

Supply Voltages

PAV

CC

- DV

CC

PAV

CC

and DV

CC

Relation during Power-Up Sequence

PAV

CC

- AV

CC

PAV

CC

and DV

CC

Relation during Power-Up Sequence

PAV cc

AI

CC

+ DI

I PAV

CC

CC

Power Supply Voltage

Max allowed slope during

Power-Up

Input Supply Current

Powered Analog Supply

Current

Test Condition

DV

CC

< 4.75V

AV

CC

< 4.75V

Transmission & Receiving mode

Min. Typ.

4.75

5

0.1

0.1

7.5

5

Max.

5.25

1.2

1.2

12.5

100

7

Unit

V

V

V

V

V/ms mA

TX mode (no load)

RX mode

Maximum total current

30

0.5

50

1 mArms mA

370 mArms

Digital I/O

V

IH

V

IL

V

OH

V

OL

R down

R up

Oscillator

XOUT

SWING

XOUT

OFFSET

DC

Xtal

Xtal

ESR

High Logic Level Input Voltage

Low Logic Level input Voltage

High Logic Level Output Voltage I

OH

= -2mA

Low Logic Level Output Voltage I

OL

= 2mA

Pull Down Resistor

Pull up Resistor

XOUT Input Voltage Swing

XOUT Input Voltage Offset

External Clock (see par. 3.8)

2

3.5

1

1.5

100

100

0.8

0.4

3

2.5

V

V

V

V k

Ω k

Ω

V

V

Xtal

CL

XTAL Clock Duty Cycle

Crystal Oscillator frequency

External Oscillator Esr

Resistance

External Oscillator Stabilization

Capacitance

External Clock 40

16

60

40

16

%

MHz

Ω pF

Transmitter

IATO 1 mArms

V

ATO

V

ATODC

Output Transmitting Current on

ATO

Max Carrier Output AC Voltage R

CL

= 1.75k

Ω

V sense (AC)

= 0V

Output DC Voltage on ATO

1.75

1.7

2.3

2.1

3.5

2.5

V

PP

V

HD2

ATO

HD3

ATO

V

ATO

= 2V

PP

-55 -42 dB Second Harmonic Distortion on Obsolete Product(s) - Obsolete Product(s)

Third Harmonic Distortion on -52 -49 dB

ATO

IATOP Output Transmitting Current in programmable current limiting

Vsense connected though a

100pF cap to GND; Rcl=1.85k

Ω

;

R

LOAD

=1

Ω

(as in fig. 17)

250 310 370 mArms

5/30

ST7538

Table 5. Electrical Characteristcs (continued)

(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C

≤

Tamb

≤

85°C, Fc = 86kHz, other Control

Register parameters as default value, unless otherwise specified).

Symbol

V

ATOP(AC)

Parameter

Max Carrier Output AC Voltage for each ATOP1 and ATOP2 pins

Test Condition

R

CL

= 1.75k

Ω ;

V sense (AC)

= 0V

PAVcc

≥

VATOP AC

2

)

+ 7.5V

Min. Typ.

3.5

4.6

Max.

7

Unit

V pp

V

ATOP(DC)

Third Harmonic Distortion on each ATOP1 and ATOP2 pins

Differential Third Harmonic

Distortion

3.5

4.2

5 V

HD2

ATOP

HD3

ATOP

Output DC Voltage on ATOP1 and ATOP2 pins

Second Harmonic Distortion on each ATOP1 and ATOP2 pins

Differential Second Harmonic

Distortion

V

ATOP

= 4V

PP

, PAVCC = 10V

No Load

V

ATOP

= 4V

PP

, PAVCC = 10V

R

LOAD

=50

Ω

(Differential)

Carrier Frequency: 132.5KHz

V

ATOP

= 4V

PP

, PAVCC = 10V

No Load.

V

ATOP

= 4V

PP

, PAVCC = 10V

R

LOAD

=50

Ω

(Differential)

Carrier Frequency: 132.5KHz

R

CL

= 1.75k

Ω;

V sense (AC)

= 0V

-55

-65

-56

-65

-42

-53

-49

-52 dB dB dB dB

VATOP Accuracy with Voltage Control

Loop Active

G

STEP

D

RNG

VCL

TH

ALC Gain Step Control loop gain step

ALC Dynamic Range

Voltage control loop reference threshold on V sense

pin

VCL

HYST

Hysteresis on Voltage loop reference threshold

CCL

TH

CCL

HYST

Current control loop reference threshold on C sense

pin

Hysteresis on Current loop reference threshold

V

SENSE (DC)

V

SENSE

T

RxTx

Output DC Voltage on VSENSE

VSENSE Input Impedance

Carrier Activation Time

Figure 15

Figure 15

Figure 15

Figure 15

-1

0.6

160

1.80

210

1

30

180

±18

1.90

250

+1

1.4

200

2.00

290

G

STEP dB dB mV

PK mV

V mV

Figure 18 - 600 Baud Xtal=16MHz 0.01

Figure 18- 1200 Baud

Xtal=16MHz

0.01

0.01

Figure 18- 2400 Baud

Xtal=16MHz

Figure 18- 4800 Baud

Xtal=16MHz

0.01

1.865

36

1.6

800

400

200

V

K

Ω ms

µ s

µ s

µ s

TALC Carrier Stabilization Time Obsolete Product(s) - Obsolete Product(s) step 16 to step 31,

Figure 18.

Xtal =16MHz

3.2

ms

µ s T

ST

Tstep Figure 18

Xtal =16MHz

200

Receiver

V

IN

Input Sensitivity (Normal Mode)

Input Sensitivity (High Sens.)

0.5

250

2 mV rms

µ

V rms

V rms

V

IN

Maximum Input Signal 2

6/30

ST7538

Table 5. Electrical Characteristcs (continued)

(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C

≤

Tamb

≤

85°C, Fc = 86kHz, other Control

Register parameters as default value, unless otherwise specified).

Symbol

R

IN

V

CD

Parameter

Input Impedance

Test Condition Min. Typ.

80 100

Max.

140

Unit k

Ω mV rms

V

BU

Carrier Detection Sensitivity

(Normal Mode)

Carrier Detection Sensitivity

(High Sensitivity Mode)

Band in Use Detection Level

0.5

250

77

2

85

µ

V rms dB/

µVrms

Voltage Regulator

VDC Linear Regulator Output

Voltage

∆

VDC Line Regulation

Load Regulation

-25<Tj<125 C

0<I

(VDC)

<100mA

-25<Tj<125 C

0<I

(VDC)

<150mA

7.5V<PAVcc<12.5V

I

(VDC)

=10mA

5mA<I

(VDC)

<100mA

PAVcc=7.5V

4.9

4.7

5.05

10

20

5.2

5.2

50

75

V

V mV mV

I(V

DC

)

UVLO

T

RSTO

T

WD

T

WM

Linear Regulator Current

Limitation

Input Under Voltage Lock Out

Threshold

UVLO Hysteresis UVLO

HYS

PG Power Good Output Voltage

Threshold on VDC pin

PG

HYS

PG Hysteresis

Other Functions

Reset Time

Watch-dog Pulse Width

Watch-dog Pulse Period

See Figure 22; Xtal=16MHz

See Figure 22

150

3.7

4.3

50

3.5

180

3.9

340

4.5

250

210

4.1

4.7

1490 mA

V mV

V mV ms ms ms T

WD

+

3.5

Watch-dog Time Out 1.5

s T

WO

T

OUT

TX TIME OUT s Control Register Bit 7 and Bit 8

See Figure 21

Control Register bit 3 and bit 4 see table 11

1

3

Time Out OFF Time See Figure 21 125 ms T

OFF

RxTx 0->1 vs. TOUT Delay 20 T

OFFD

µ s

T

CD

Carrier Detection Time selectable by register

Control Register bit 9 and bit10

500

1

µ s ms

Figure 12 3 ms Obsolete Product(s) - Obsolete Product(s)

T

DCD

CD_PD Propagation Delay Figure 12 300 500

µ s

M

CLK

Master Clock Output

Selectable by register

Control Register bit 15 and bit 16 see table 11 fclock fclock/2 fclock/4

MHz

B

AUD

Baud rate 600

1200

2400

4800

Baud

7/30

ST7538

Table 5. Electrical Characteristcs (continued)

(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C

≤

Tamb

≤

85°C, Fc = 86kHz, other Control

Register parameters as default value, unless otherwise specified).

Symbol

T

B

Parameter

Baud rate Bit Time (=1/

BAUD

)

Test Condition

Control Register bit 3 and bit 4 see table 11

Min. Typ.

1667

833

417

208

Max.

Unit

µ s

Zero Crossing Detection

ZC

DEL

Zero Crossing Detection delay

(delay between the ZCIN and

ZCOUT signals)

ZC

(LOW)

ZC

(HIGH)

Zero Crossing Detection Low

Threshold

Zero Crossing Detection High

Threshold

ZC

(OFFSET)

Zero Crossing Offset

Operational Amplifier

C

OUT(Sync)

C

OUT(Source)

Max Sync Current

Max Source Current

C

IN(Offset)

Input Terminals OFFSET

GBWP Gain Bandwidth Product

Figure 23

Serial Interface

Ts Setup Time

T

H

T

CR

T

CC

T

DS

T

DH

T

CRP

Hold Time

CLR/T vs. REG_DATA or RxTx

CLR/T vs. CLR/T

Setup Time

Hold Time see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10 see figure 6, 7, 8, 9 & 10

-45

5

-20

15

-30

-38

6

T

B

T

B

/4

T

B

/4

T

H

28

-20

7

1

-5

+45

+20

45

-10

+38

9

5

2

T

B

/4

2*T

B

T

B

/2

T

B

/2

T

B

/2

µ s mV mV mV mA mA mV

MHz ns ns

8/30

ST7538

3 FUNCTIONAL DESCRIPTION

3.1 Carrier Frequencies

ST7538 is a multi frequency device: eight programmable Carrier Frequencies are available (see table 6).

Only one Carrier at a time can be used; anyway, it's possible to switch the communication channel during the normal working Mode. Selecting the desired frequency in the Control Register the Transmission and

Reception filters are accordingly tuned.

Table 6. ST7538 Channels List

FCarrier

F0

F1

F2

F3

F4

F5

F6

F7

(1)

F (KHz)

60

66

72

76

82.05

86

110

132.5

3.2 Baud Rates

ST7538 is a multi Baud rate device: four Baud Rate are available (See table 7).

Table 7. ST7538 mark and space tones frequency distance Vs Baud Rate and Deviation

Baud Rate [Baud]

600

1200

2400

(1)

4800

∆

F

(2)

(Hz)

600

600

1200

1200

(1)

2400

2400

4800

Deviation

(3)

1

(4)

0.5

1

0.5

1

0.5

1

Note: 1. Default value

2. Frequency deviation.

3. Deviation = ∆ F / (Baud Rate)

4. Deviation 0.5 Not Allowed

9/30

ST7538

3.3 Mark and Space Frequencies

Mark and Space Communication Frequencies are defined by the following formula:

F ("0") = FCarrier + [ ∆

F ]/2

F ("1") = FCarrier - [ ∆

F ]/2

∆ F(Frequency Deviation) = Deviation*BAUD rate.

Here follows a table listing the correlation between frequency parameters and actual tones frequencies.

Table 8. ST7538 synthesized frequencies

Carrier

Frequency

(KHz)

60

Baud

Rate

600

Deviation

Exact Frequency [Hz]

(Clock=16MHz)

“1” “0”

66

72

76

1200

2400

4800

600

1200

2400

4800

600

1200

2400

4800

600

2400

4800

1

0.5

1

0.5

1

0.5

1

0.5

1

--

0.5

1

0.5

1

--

1

0.5

1

0.5

1

--

1

0.5

1

0.5

1

--

1

0.5

1

0.5

1

75684

75684

75358

75358

74870

74870

73568

71777

71777

71452

71452

70801

70801

69661

65755

65755

65430

65430

64779

64779

63639

59733

59733

59408

59408

58757

58757

57617

76335

76335

76660

76660

77148

77148

78451

72266

72266

72591

72591

73242

73242

74382

66243

66243

66569

66569

67220

67220

68359

60221

60221

60547

60547

61198

61198

62337

Carrier

Frequency

(KHz)

82.05

86

110

132.5

Baud

Rate

Deviation

Exact Frequency [Hz]

(Clock=16MHz)

“1” “0”

600

1200

2400

4800

600

1200

2400

4800

600

1200

2400

4800

600

1200

2400

4800

1

0.5

1

0.5

1

0.5

1

0.5

1

--

0.5

1

0.5

1

--

1

0.5

1

0.5

1

--

1

0.5

1

0.5

1

--

1

0.5

1

0.5

1

81706

81706

81380

81380

80892

80892

79590

85775

85775

85449

85449

84798

84798

83659

109701

109701

109375

109375 110677

108724 111165

108724

107585

132161

132161

131836

131836

131348

131348

130046

82357

82357

82682

82682

83171

83171

84473

86263

86263

86589

86589

87240

87240

88379

110352

110352

110677

111165

112467

132813

132813

133138

133138

133626

133626

134928

10/30

ST7538

3.4 Host Processor Interface

ST7538 exchanges data with the host processor thorough a serial interface.

The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged using RxD, TxD and CLR/T lines.

Four are the ST7538 working modes:

■ Data Reception

■ Data Transmission

■ Control Register Read

■ Control Register Write

REG_DATA and RxTx lines are level sensitive inputs.

Table 9. Data and Control register access bits configuration

REG_DATA

Data Transmission

Data Reception

Control Register Read

0

0

1

Control Register Write 1

RxTx

0

1

1

0

■ Mains Access

ST7538 features two type of communication interfaces:

- Asynchronous

- Synchronous

The selection can be done through the internal Control Register.

Figure 4. Synchronous and Asynchronous ST7538/Host Controller interfaces

Asynchronous

Data Interface

Synchronous

Data Interface

RxD

TxD

RxTx

CLR/T

REG_DATA

RxD

TxD

RxTx

CLR/T

REG_DATA

Host Controller Host Controller

D03IN1415

ST7538 ST7538

Obsolete Product(s) - Obsolete Product(s)

– Asynchronous Mode.

ST7538 allows to interface the Host Controller using a 3 line interface (RXD,TXD & RxTx ).

Data are exchange without any auxiliary Clock reference in an Asynchronous mode without adding any protocol bits. The host controller has to recover the clock reference in receiving Mode and control the Bit time in transmission mode. RxD line is forced to a low logic level when no carrier is detected.

11/30

ST7538

– Synchronous mode.

ST7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/

T & RxTx ). ST7538 is always the master of the communication and provides the clock reference on CLR/

T line.

When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge.

When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD line on CLR/T rising Edge.

If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7538 enters in an Idle State and CLR/T line is forced Low. After Tcc time the modem starts providing received data on RxD line.

If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7538 enters in an Idle State and transmission circuitry is switched on. After Tcc time the modem starts transmitting data present on TXD line

(figure 6) .

Figure 5. Receiving and transmitting data/recovered clock timing

Receiving Bit Synchronization Transmitting Bit Synchronization

CLR/T CLR/T

RxD

D03IN1416

TxD

T

S

T

H

Figure 6. Data Reception -> Data Transmission -> Data reception

T

CC

CLR_T

T

B

RXD

REG_DATA

T

CR

T

CR

RxTx

T

S

T

H

BIT23

TXD

BIT22

T

CC

T

DS

T

DH

D03IN1402

3.5 Control Register Access

The communication with ST7538 Control Register is always synchronous. The access is achieved using the same lines of the Mains interface (RxD, TxD and CLR/T) plus REG_DATA Line.

With REG_DATA = 1 and RxTx =0, the data present on TxD are loaded into the Control Register MSB first.

Obsolete Product(s) - Obsolete Product(s) end of the register access section (REG_DATA falling edge). If more than 24 bits are transferred to

ST7538 only the latest 24 bits are stored inside the Control Register.

With REG_DATA = 1 and RxTx =1, the content of the Control Register is sent on RxD port. The Data on

RxD are stable on CLR/T rising edges MSB First.

12/30

ST7538

Figure 7. Data Reception ➨ Control Register read ➨ Data Reception Timing Diagram

T

CC

T

CC

CLR_T

T

DS

T

DH

RXD

REG_DATA

RxTx

T

CR

T

DS

T

DH

BIT23 BIT22

T

CR

T

B

D03IN1404

Figure 8. Data Reception ➨ Control Register write ➨ Data Reception Timing Diagram

T

CC

T

CC

CLR_T

T

DS

T

DH

RXD

T

CR

T

CR

REG_DATA

T

CR

T

CR

RxTx

TXD

T

S

T

H

BIT23 BIT22

T

B

D03IN1403

Figure 9. Data Transmission ➨ Control Register read ➨ Data Reception Timing Diagram

T

CC

T

CC

CLR_T

T

B

T

DS

T

DH

T

DS

T

DH

RXD BIT23 BIT22

T

CR

T

CR

REG_DATA

T

CR

RxTx

T

S

T

H

TXD

D03IN1405

Figure 10. Data Transmission ➨ Control Register Write ➨ Data Reception Timing Diagram

T

CC

T

CC

CLR_T

TXD

T

B

T

S

T

H

BIT23 BIT22

T

CR

REG_DATA

T

CR

T

CR

RxTx

T

DS

T

DH

RXD

D03IN1401

13/30

ST7538

3.6 Receiving Mode

The receive section is active when RxTx Pin =”1” and REG_DATA=0.

The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass

Filter (62kHz max. bandwidth at -3dB). The Pre-Filter can be removed setting one bit in the Control Register. The Input Stage features a wide dynamic range to receive Signal with a Very Low Signal to Noise

Ratio. The Amplitude of the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a Narrow Band Band-Pass Filter centered around the Selected Channel

Frequency (14kHz max. bandwidth at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal Jitter. RxD Line is forced at logic level “0” when neither mark or space frequencies are detected on RAI Pin.

Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct demodulation.

While ST7538 is in Receiving Mode ( RxTx pin =”1”), the transmit circuitry, Power Line Interface included, are turned off. This allows the device to achieve a very low current consumption (5 mA typ). In Receiving mode ATOP2 pin is internally connected to PAVSS.

■ High Sensitivity Mode

It is possible to increase ST7538 Receiving Sensitivity setting to “1” the High Sensitivity Bit of Control

Register. This Function allows to increase the communication reliability when the ST7538 sensitivity is the limiting factor.

■ Synchronization Recovery System (PLL)

ST7538 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host

Controller.

The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN

Range).

The PLL Lock-in and Lock-out Range is ±

π

/2. When the PLL is in the unlock condition, CLR/T and RxD lines are forced to a low logic level.

When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter.

ST7538 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.

Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL into the un-lock condition.

Figure 11. ST7538 PLL lock-in range

CLR/T

D03IN1417

LOCK-IN RANGE

14/30

ST7538

■ Carrier/Preamble Detection

The Carrier/Preamble Block is a digital Frequency detector Circuit.

It can be used to manage the MAINS access and to detect an incoming signal.

Two are the possible setting:

- Carrier Detection

- Preamble Detection

CARRIER DETECTION: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode).

The CD_PD line is forced to a logic level low when a Carrier is detected.

PREAMBLE DETECTION: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols

(“1010” or “0101” are the symbols sequences detected).

CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range.

To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on

Carrier or Preamble notification signal (See Control Register Paragraph). The Detection Time Bits in the

Control Register define the filter performance. Increasing the Detection Time reduced the false notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a period equal to the detection time and then forced high.

Figure 12. CD_PD Timing during RX

T

DCD

T

CD

CD_PD

RAI

D03IN1418

Figure 13. Receiving Path Block Diagram

RxD

3

Bit 3,4 &14-21

8

CLR/T PLL

Bit 3,4 Bit 3,4

Low Pass

DIGITAL

FILTER

FSK

DEMODULAOR

Bit 9 & 10 Bit 12 & 13

Band Pass

IF FILTER

Bit 0-2

MIXER

LOCAL

OSC

Bit 0 -2

AGC

Band Pass

CHANNEL

FILTER

GAIN

CONTROL

RXFO

31

Bit 23

Band Pass

PRE-FILTER

32

RAI

CD_PD

1

PREAMBLE

DETECTION

Carrier Detection

Low Pass

BU

9

BAND

IN

USE

D03IN1419

15/30

ST7538

3.7 Transmission Mode

The transmit mode is set when RxTx Pin =”0” and REG_DATA Pin =”0”. In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TXD) enter synchronously or asynchronously to the FSK modulator.

– Host Controller Synchronous Communication Mode: on CLR/T rising edge, TXD Line Value is read and sent to the FSK Modulator. ST7538 Manage the Transmission timing according to the BaudRate Selected

– Host Controller Asynchronous Communication Mode: TXD data enter directly to the FSK Modulator.The

Host Controller Manages the Transmission timing

In both conditions no Protocol Bits are added by ST7538.

The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator by direct digital synthesis technique. The frequencies Table in different Configuration is reported in Table 8. The frequencies precision is same as external crystal one’s.

In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle.

Figure 14. Transmitting Path Block Diagram

Bit 7 & 8

TIMER

TOUT

7

THERMAL

SENSOR

Bit 14

Bit 0-5 Bit 0-2

TxD

5

DAC

CLR/T

8

ZCOUT

15

D-TYPE

FLIP

FLOP

FSK

MODULATOR

CLR/T GENERATOR

Band Pass

TRANSMISSION

FILTER

ZERO CROSSING

ZCIN

16

ALC

VOLTAGE

LOOP

29

Vsense

CURRENT

LOOP

23

CL

PLI

PLI

PLI

19

21

24

D03IN1420

ATOP1

ATOP2

ATO

16/30

ST7538

■ Automatic Level Control (ALC)

The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ).

Two are the control loops acting to define the ALC gain:

- A Voltage Control loop

- A Current Control Loop

The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and two internal Voltage references.

- If Vsense < VCL

TH

- VCL

HYST

- If VCL

TH

- VCL

HYST

< Vsense < VCL

TH

+ VCL

HYST

- If Vsense > VCL

TH

+ VLC

HYST

The next gain level is increased by 1 step

No Gain Change

The next gain level is decreased by 1 step

The Current control loop acts to limit the maximum Peak Output current inside ATOP1 and ATOP2.

The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak

Amplitude to reduce the Current inside the Power Line Interface.

The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not dissipating current Sensing). The Output Current Limit (up to 370mArms), is set by means of an external resistor (R

CL

) connected between CL and PAVss. The resistor converts the current sensed into a voltage signal. The Peak current sensing block works as the Output Voltage sensing Block:

- If V(CL) < CCL

TH

- CCL

HYST

- If CCL

TH

- CCL

HYST

< V(CL) < CCL

TH

+ CCL

HYST

- If V(CL) > CCL

TH

+ CLC

HYST

Voltage Control Loop Acting

No Gain Change

The next gain level is decreased by 1 step

Figure 15 shows the typical connection of Current anVoltage control loops.

Figure 15. Voltage and Current Feedback external interconnection Example

Vout

PK

ATOP/ATO Vout

ALC

R1

Vsense

VOLTAGE

LOOP

5.6nF

R2

VCL

HYST

VCL

TH

1.865V (Typ)

CL CURRENT

LOOP

RCL 100pF CCL

HYST

D03IN1421

AVss

AV

SS

CCL

TH Obsolete Product(s) - Obsolete Product(s)

Voltage Control Loop Formula

Vout

PK

≅

R +

R

2

R

-------------------⋅ (

V CL

TH

±

V CL

H YST

)

17/30

ST7538

Table 10. Vout vs. R1 & R2 resistors value

Vout (Vrms)

0.150

0.250

0.350

0.500

0.625

Vout (dB

µ

V)

103.5

108.0

110.9

114.0

115.9

(R1+R2)/R2

1.1

1.9

2.7

3.7

4.7

0.750

0.875

1.000

117.5

118.8

120.0

5.8

6.6

7.6

1.250

121.9

9.5

1.500

123.5

10.8

Notes: The rate of R2 takes in account the input resistance on the SENSE pin (36 K

Ω

).

5.6nF capacitor effect has been neglected.

R2 (K

Ω

) R1

7.5

1.0

5.1

3.6

3.9

5.6

3.3

3.3

2.7

2.0

1.6

1.6

1.6

8.2

11.0

12.0

11.0

10.0

13.0

15.0

Figure 16. Typical Output Current vs. Rcl

Irms

(mA)

325

300

275

250

225

200

175

150

125

100

D01IN1311

2 2.5

3 3.5

4 4.5

5 Rcl(K

Ω

)

■ Integrated Power Line Interface (PLI)

The Power Line Interface (PLI) is a double CMOS AB Class Power Amplifier with the two outputs

(ATOP1 and ATOP2) in opposition of phase.

Two are the possible configuration:

- Single Ended Output (ATOP1).

- Bridge Connection

The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each

Obsolete Product(s) - Obsolete Product(s)

Voltage must fulfil the following formula to work without clipping phenomena:

PAVcc

≥

VATOP AC

2

)

+ 7.5 V

To allow the driving of an external Power Line Interface, the output of the ALC is available even on ATO pin. ATO output has a current capability much lower than ATOP1 and ATOP2.

18/30

Figure 17. PLI Bridge Topology

Vout

PK

INVERTER

ALC

VOLTAGE

LOOP

CURRENT

LOOP

D03IN1422

Figure 18. PLI Startup Timing Diagram

ATOP2

ATOP1 Vout

R1

Vsense

5.6nF

R2

LOAD

CL

PAVss

RCL 100pF

RX/TX

T

ALC

T

RXTX

4V

T

ST

ATOP2 0V

STEP NUMBER 16 17 18 31

D03IN1408

2*Vout

PK

Vout

PK

ST7538

19/30

ST7538

3.8 Crystal Oscillator

ST7538 integrates a sub-threshold driver circuit to realize a 16MHz crystal oscillator.

This circuit is able to drive a maximum load capacitance of 16pF with typical quartz ESR of 40

Ω

.

If the internal driver circuit is used, only one external crystal quartz and two external load capacitors (C

1 e C

2

) are needed to realize the oscillator function (fig.19).

Figure 19. Typical crystal configuration if ST7538 internal crystal driver circuit is used

If an external oscillator is used, XIN must be connected to DVss, while XOUT must satisfy the specifications given in table 5 (see also fig.20).

Figure 20. XOUT waveforms if an external oscillator is used (see table 8 for parameter values)

3.9 Control Register

The ST7538 is a multi-channel and multifunction transceiver. An internal 24 Bits Control Register allows to manage all the programmable parameters (table 11).

The programmable functions are: Obsolete Product(s) - Obsolete Product(s)

■ Channel Frequency

Baud Rate ■

■ Deviation

■ Watchdog

■ Transmission Timeout

■ Frequency Detection Time

20/30

ST7538

■ Zero Crossing Synchronization

■ Detection Method

■ Mains Interfacing Mode

■ Output Clock

■ Input Pre-Filter

■ Sensitivity Mode

Table 11. Control Register Functions

Function Value

0 to 2 Frequencies

60 KHz

66 KHz

72 KHz

76 KHz

82.05 KHz

86 KHz

110 KHz

132.5 KHz

3 to 4 Baud Rate

600

1,200

2,400

4,800

5 Deviation

0.5

1

6 Watchdog

Disabled

Enabled (1.5 s)

7 to 8 Transmission

Time Out

Disabled

1 s

3 s

Not Used

9 to 10 Frequency detection time

500

µ s

1 ms

3 ms

5 ms

1

1

0

0

Bit 10

0

0

1

1

Selection

Bit2 Bit1 Bit0

1

1

1

1

0

0

0

0

Bit 4

1

1

0

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Bit 3

0

1

0

1

Bit 5

0

1

Bit 6

0

1

Bit 8 Bit 7

0

1

0

1

Bit 9

0

1

0

1

Note Default

132.5 kHz

2400

0.5

Enabled

1 sec

1 ms

Disabled

Bit 11 11 Zero Crossing Obsolete Product(s) - Obsolete Product(s)

Enabled

0

1

Disabled

Bit 13 Bit 12

21/30

ST7538

Table 11. Control Register Functions (continued)

12 to 13

14

Function

Detection

Method

Mains

Interfacing

Mode

15 to 16 Output Clock

Value

Carrier detection without conditioning

Carrier detection with conditioning

Preamble detection without conditioning

Preamble detection with conditioning

Synchronous

Asynchronous

16 MHz

8 MHz

4 MHz

Not Used

0

0

1

1

Selection

0

1

0

1

Bit 16

1

1

0

0

Bit 14

0

1

Bit 15

0

1

0

1

Note

Carrier Detection

Notification on CD_PD Line

CLR/T and RxD signal always Present

CLR/T and RxD lines are forced to “0” when Carrier is not detected

Preamble Detection

Notification on CD_PD Line

CLR/T and RxD signal always Present

Preamble Detection

Notification on CD_PD Line

CLR/T and RxD lines are forced to “0” when

Preamble has not been detected or PLL is in

Unlock condition

Default

Preamble detection without conditioning

Asynchronous

4 MHz

17 to 20

21

Not Used

Reserved Do not modify the default value

1001

0

22

23

Sensitivity

Mode

Input Filter

Normal Sensitivity

High Sensitivity

Disabled

Enabled

Bit 22

0

1

Bit 23

0

1

Normal

Disabled

22/30

ST7538

4 AUXILIARY ANALOG AND DIGITAL FUNCTIONS

4.1 Band In Use

The Band in Use Block has a Carrier Detection like function but with a different Input Sensibility (77dB µ V

Typ.) and with a different BandPass filter Selectivity (40dB/Dec).

BU line is forced High when a signal in band is detected.

To prevent BU line false transition, BU signal is conditioned to Carrier Detection Internal Signal.

4.2 Time Out

Time Out Function is a protection against a too long data transmission. When Time Out function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. This function allows ST7538 to automatically manage the CENELEC Medium Access specification. When a time-out event occur, TOUT is forced high, and is held high for at least 125 ms. To Unlock the Time Out condition

RxTx should be forced High. During the time out period only register access or reception mode are enabled.

During Reset sequence if RxTx line =”0” & REG_DATA line =”0”, TIMEOUT protection is suddendly enabled and ST7538 must be configured in data reception after the reset event before starting a new data transmission.

Time Out time is programmable using Control Register bits 7 and 8 (table 11).

Figure 21. Time-out Timing and Unlock Sequence

RxTx

T

OUT

T

OFF

T

OFFD

TOUT

D03IN1409

4.3 Reset & Watchdog

RSTO Output is a reset generator for the application circuitry. During the ST7538 startup sequence is forced low. RSTO becomes high after a T

RSTO

delay from the end of oscillator startup sequence.

Inside ST7538 is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller. The watchdog circuitry generates an internal and external reset (RSTO low for T

RSTO

time) on expiry of the internal watchdog timer. The watchdog timer reset can be achieved applying a negative pulse on WD pin Fig 22.

Figure 22. Reset and Watchdog Timing

T

RSTO

T

WO

T

RSTO

T

WD

T

WM

WD

D03IN1410

23/30

ST7538

4.4 Zero Crossing Detection

The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains.

ZCIN comparator has a threshold fixed at SGND. ZCOUT is a TTL Output forced High after a positive zero-crossing transition, and low after a negative one.

Setting the Bit 11 inside the Control Register to “1” the transmission is automatically synchronized to the mains positive zero-crossing transition. This function is achieved turning on the PLI when RX/TX is low and delaying the CLR/T first transition until the first zero-crossing event. The automatic synchronization procedure can work only if the synchronous interface is programmed. If asynchronous interface is in use the Zero Crossing synchronization can be achieved managing the ZCOUT line.

Figure 23. Synchronous Zero-Crossing Transmission

ZCIN

RxTx

CLR/T

TxD

ZC

DEL

ZCOUT

D03IN1423

4.5 Output Clock

MCLK is the master clock output. The clock frequency sourced can be programed through the control register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4). The transition between one frequency and another is done only at the end of the ongoing cycle.

4.6 Reg OK

REGOK allows to detect an accidental corruption of the Control Register content. If a register content corruption is detected, REGOK goes to "1". REGOK function is disabled during a control register writing session.

4.7 Under Voltage Lock Out

The UVLO function turns off the device if the PAVdd voltage falls under 4V. Hysteresis is 340mV typically.

Obsolete Product(s) - Obsolete Product(s)

4.8 Thermal Shutdown

The ST7538 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170°C ±10% . Hysteresis is around 30°C.

When shutdown threshold is overcome, PLI interface is switched OFF.

Thermal Shutdown event is notified to the HOST controller using TIMEOUT line. When TIMEOUT line is

High, ST7538 junction temperature exceed the shutdown threshold (Not Lached).

24/30 t

ST7538

4.9 5V Voltage Regulator and Power Good Function

ST7538 has an embedded 5V linear regulator externally available to supply the application circuitry.

The linear regulator has a very low quiescent current (50

µ

A) and a current capability of 100mA. The regulator is protected against short circuitry events.

When the regulator Voltage is above the power good threshold (V

PG)

, Power Good line is forced high, while is forced low at startup and when VDC falls below V

PG

- V

PGHYS

Voltage.

Figure 24. Power Good Function

V

DC

4.5V

250mV

Time

PG

PG OK

D03IN1411 Time

4.10 Power-Up Procedure

To ensure ST7538 proper power-Up sequence, PAVcc, AVss and DVss Supply has to fulfil the following rules:

1) PAVcc rising slope must not exceed 100V/ms.

2) When DVdd and AVdd are below 5V (externally supplied): 100mV < PAVcc-AVdd , PAVcc-DVdd < 1.2V.

When AVdd and DVdd supply are connected to VDC, with load < 100mA and filtering capacitor on VDC

< 100uF, the second rule can be ignored.

Figure 25. Power-UP Sequence

Voltage

PAVcc

100V/ms

DVdd, AVdd

5V

PAVcc-AVdd

PAVcc-DVdd

25/30

ST7538

Figure 26. Application Schematic Example with Coupling Tranformer.

26/30

ST7538

5 PACKAGE INFORMATION

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an

ST trademark.

ECOPACK specifications are available at: www.st.com.

5.1 Thermal and Soldering Information

Best thermal performance is acheived when slug is soldered to PCB.

It is recomended to have five solder dots (See fig. 28) without resist to connect the Copper slug to the ground layer on the soldering side. Moreover it is recomeded to connect the ground layer on the soldering side to another ground layer on the opposite side with 15 to 20 vias.

It is suggested to not use the PCB surface below the slug area to interconnect any pin except groung pins.

Figure 27. ST7538 Slug Drawing

Copper Slug

Solder plated

Figure 28. Soldering Information

Cu plate

Solder dots

Lead frame

D03IN1414

0.10mm ±0.05

A

B

L L1

Package Sizes

A

B

10x10x1.4mm

2.00 mm

1.00 mm

L

L1 (Copper plate)

6.00 mm

Obsolete Product(s) - Obsolete Product(s)

L

D03IN1413

If PCB with ground layer, connect copper plate with 15 to 20 vias

L1

27/30

ST7538

Figure 29. TQFP44 (Slug Down) Mechanical Data & Package Dimensions

E1

E3

H

L

D3 e

E

L1

S c

D

D1

A

A1

A2 b

S1

K ccc

DIM.

mm inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

1.60

0.063

0.05

0.15

0.002

0.006

1.35

1.40

1.45

0.053

0.055

0.057

0.30

0.37

0.45

0.012

0.014

0.018

0.09

0.20

0.003

0.008

11.80

12.00

12.20

0.464

0.472

0.480

9.80

10.00

10.20

0.386

0.394

0.401

8.00

0.80

0.315

0.031

11.80

12.00

12.20

0.464

0.472

0.480

9.80

10.00

10.20

0.386

0.394

0.401

8.00

0.315

5.89

0.232

0.45

0.60

0.75

0.018

0.024

0.030

1.00

0.039

6.00

6.00

0.236

0˚ (min.), 3.5˚ (typ.), 7˚(max.)

0.10

0.236

0.004

OUTLINE AND

MECHANICAL DATA

TQFP44 (10x10x1.40mm) with Slug Down

0049510 D

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Table 12. Revision History

Date Revision

January 2004

24-Nov-2005

4

5

Description of Changes

Migration from ST-Press to EDOCS DMS.

Removed “Packet Mode” function.

Inserted new Paragraph 3.8. on Crystal Oscillator.

Added ECOPACK information.

ST7538

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ST7538

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