STL5N80K5
Nchannel 800 V, 1.50 Ω typ., 3 A MDmesh™ K5
Power MOSFET in a PowerFLAT™ 5x6 VHV package
Datasheet - production data
G(4)
PowerFLA
T™ 5x6 VHV
Figure 1: Internal schematic diagram
D(5, 6, 7, 8)
8 7 6 5
S(1, 2, 3)
Order code
STL5N80K5
1
2
3
4
Features
Order code V
DS
R
DS(on)
max.
STL5N80K5 800 V 1.75 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Packing
Tape and reel
I
D
3 A
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
1 2 3 4
Marking
5N80K5
Top View
Table 1: Device summary
Package
PowerFLAT™ 5x6 VHV
April 2017 DocID028514 Rev 3
This is information on a product in full production.
1/16 www.st.com
Contents
Contents
STL5N80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
PowerFLAT™ 5x6 VHV mechanical data ....................................... 10
PowerFLAT™ 5x6 packing information ........................................... 13
5 Revision history ............................................................................ 15
2/16 DocID028514 Rev 3
STL5N80K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
D
(1)
P
TOT
dv/dt (2) dv/dt (3)
T j
T stg
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature range
Storage temperature range
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
≤ 4 A, di/dt =100 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
=640 V.
(3)
V
DS
≤ 640 V.
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2 oz Cu
Symbol
Table 4: Avalanche characteristics
Parameter
I
AR
E
AS
Avalanche current, repetitive or not repetitive
(pulse width limited by T jmax
)
Single pulse avalanche energy
(starting Tj = 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Electrical ratings
Value
± 30
3
1.8
12
38
4.5
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
°C
Value
3.3
59
Unit
°C/W
°C/W
Value
1.2
165
Unit
A mJ
DocID028514 Rev 3 3/16
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
I
GSS
Gate body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
GS
= 0 V, V
DS
= 800 V
V
GS
= 0 V, V
DS
= 800 V
T
C
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±20 V
V
DD
= V
GS
, I
D
= 100 µA
V
GS
= 10 V, I
D
= 2 A
STL5N80K5
Min. Typ. Max. Unit
800 V
1 µA
50 µA
4
±10 µA
5 V
1.50 1.75 Ω
3
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
GS
= 0 V, V
DS
= 0 to 640 V f = 1 MHz , I
D
=0 A
V
DD
= 640 V, I
D
= 4 A
V
GS
= 0 to 10 V
(see Figure 15: "Test circuit for gate charge behavior" )
-
-
-
-
Min. Typ. Max. Unit
-
-
-
177
15
0.3
-
-
- pF pF pF
-
-
33
12
16
5
1.7
2.9
-
-
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
C o(tr)
is a constant capacitance value that gives the same charging time as Coss while V
DS
is rising from 0 to
80% V
DSS
.
(2)
C o(er)
is a constant capacitance value that gives the same stored energy as Coss while V
DS
is rising from 0 to
80% V
DSS
.
4/16 DocID028514 Rev 3
STL5N80K5
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 400 V, I
D
= 2 A, R
G
= 4.7 Ω
V
GS
= 10 V
(see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
12.7
11.7
23
14.8
-
-
-
- ns ns ns ns
I t
I
I
Symbol Parameter
I
SD
Source-drain current
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
t rr
Forward on voltage
Reverse recovery time
Table 8: Source-drain diode
Test conditions
Q
RRM rr
Q rr rr
RRM
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 3 A, V
GS
= 0 V
I
SD
= 4 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 4 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Min. Typ. Max. Unit
- 3 A
- 12 A
- 1.5 V
-
-
-
-
-
-
265
1.59
12
386
2.18
11.3 ns
µC
A ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol Parameter
Table 9: Gate-source Zener diode
Test conditions Min. Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage
I
GS
= ± 1 mA, I
D
= 0 A 30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
DocID028514 Rev 3 5/16
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STL5N80K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/16 DocID028514 Rev 3
STL5N80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Maximum avalanche energy vs starting
T
J
Figure 13: Source-drain diode forward characteristics
DocID028514 Rev 3 7/16
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STL5N80K5
Figure 15: Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
8/16
Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
DocID028514 Rev 3
STL5N80K5
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID028514 Rev 3 9/16
Package information
4.1 PowerFLAT™ 5x6 VHV mechanical data
Figure 20
: PowerFLAT™ 5x6 VHV package outline
1 2 3 4
STL5N80K5
Bottom view
Pin 1 identification
8 7 6 5
Side view
8 7 6 5
10/16
Pin 1 identification
1 2 3 4
DocID028514 Rev 3
Top view
STL5N80K5
D
E
D2
E2
A
A1
A2 b e
L
K
Dim.
Package information
Table 10: PowerFLAT™ 5x6 VHV package mechanical data mm
Min. Typ. Max.
0.80
0.02
0.25
1.00
0.05
0.30
5.00
5.95
4.30
2.40
0.50
2.60
5.20
6.15
4.40
2.50
1.27
0.55
2.70
0.50
5.40
6.35
4.50
2.60
0.60
2.80
DocID028514 Rev 3 11/16
Package information STL5N80K5
Figure 21:
PowerFLAT™ 5x6 VHV recommended footprint (dimensions are in mm)
8368144_REV_3_footprint
12/16 DocID028514 Rev 3
STL5N80K5
4.2 PowerFLAT™ 5x6 packing information
Package information
Figure 22:
PowerFLAT™ 5x6 tape (dimensions are in mm)
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
Figure 23
: PowerFLAT™ 5x6 package orientation in carrier tape
8234350_ Tape_rev_C
DocID028514 Rev 3 13/16
Package information
Figure 24
: PowerFLAT™ 5x6 reel
STL5N80K5
14/16 DocID028514 Rev 3
STL5N80K5
5
Revision history
Revision history
Date Revision
Table 11: Document revision history
Changes
12-Nov-2015
16-May-2016
24-Apr-2017
1
2
3
First release.
Modified: features in cover page
Modified: Table 2: "Absolute maximum ratings", Table 3: "Thermal data", Table 4: "Avalanche characteristics", Table 5: "On/off-state",
Table 6: "Dynamic", Table 7: "Switching times" and Table 8: "Sourcedrain diode"
Added: Section 3.1: "Electrical characteristics (curves)"
Minor text changes
Updated silhouette on cover page.
Updated Section 4 .1: "PowerFLAT™ 5x6 VHV mechanical data" .
Minor text changes.
DocID028514 Rev 3 15/16
STL5N80K5
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16/16 DocID028514 Rev 3
