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Hardware Reference Manual
Confidentiality Notice
SOM
Copyright (c) 2019 eInfochips. - All rights reserved
This document is authored by eInfochips and is eInfochips intellectual property, including the copyrights in all countries in the world. This document is provided under a license to use only with all other rights, including ownership rights, being retained by eInfochips. This file may not be distributed, copied, or reproduced in any manner, electronic or otherwise, without the express written consent of eInfochips.
FCC ID: 2ATUP-Q624300
IC: 25301-Q624300
Version 1.0 - ii - eInfochips Confidential
Hardware Reference Manual
SOM
Contents
Version 1.0 - iii - eInfochips Confidential
Hardware Reference Manual
SOM
Version 1.0 - iv - eInfochips Confidential
Hardware Reference Manual
List of Figures
SOM
Version 1.0 - v - eInfochips Confidential
Hardware Reference Manual
List of Tables
SOM
Version 1.0 - vi - eInfochips Confidential
Hardware Reference Manual
1 Document Details
1.1
Document History
Version Author
Name Date
Reviewer
Name Review
Comment
ID
Approver
Name Date eI
GB
GPIO
GPS
HD
BOM
BT
CPU
CSI
DC
DDR
DSI
1.0
eInfochips 18-July 19 eInfochi ps
Table 1: Document History
1.2
Definition, Acronyms and Abbreviations
Definition/Acronym/Abbreviation Description
BLE Bluetooth Low Energy
Bill of Material
Bluetooth
Central Processing Unit
Camera Serial Interface
Direct Current
Double Data Rate
Display Serial Interface eInfochips
Giga Byte
General Purpose Interface
Global Positioning System
High Definition
SOM
Description
Of Changes
Initial release
Version 1.0 - 7 - eInfochips Confidential
Hardware Reference Manual
HDMI High Definition Multimedia Interface
I2C Inter-Integrated Circuit
IC
Inc.
JTAG
KB
LAN
LPDDR
MIPI
MISO
MMC
MOSI
MP
OTG
PLL
Rx
SOM
SPI
Tx
PMIC
RAM
RF
RoHS
Integrated Circuit
Incorporated
Joint Test Application Group
Kilo Byte
Local Area Network
Lower Power DDR
Mobile protocol working Alliance (not an Acronym)
Master In Slave Out
Multi Media Card
Master Out Slave In
Mega Pixel
On The Go
Phase Loop Locked
Power Management IC
Random Access Memory
Radio Frequency
Restriction of Hazardous Substances
Receive
System On Module
Serial peripheral Interface
Transmit
SOM
Version 1.0 - 8 - eInfochips Confidential
Hardware Reference Manual
UART Universal Asynchronous Interface
USB Universal Serial Bus
Android Debug Bridge ADB
WLAN Wireless LAN
Table 2 : Definition, Acronyms and Abbreviations
SOM
Version 1.0 - 9 - eInfochips Confidential
Hardware Reference Manual
1.3
References
No.
Document
1
2.
ERAGON624 SOM Schematic File
ERAGON624 Carrier Schematic File
Table 3 : References
Version Remarks
1.3
1.3
Version 1.0 - 10 -
SOM eInfochips Confidential
Hardware Reference Manual
2 License Agreement
SOM
The use of this document is subject to and governed by those terms and conditions in the eInfochips Ltd.
Purchase and Software License Agreement for the APQ8053 based development platform, which you or the legal entity you represent, as the case may be, accepted and agreed to when purchasing ERAGON624 development platform from eInfochips Ltd. (“Agreement”). You may use this document, which shall be consider as a part of the defined term “Documentation” for purposes of the Agreement, solely in support of your permitted use of the ERAGON624 development platform under the Agreement. Distribution of this document is strictly prohibited without the express written permission of eInfochips Ltd. and its respective licensors, which they can withhold, condition or delay in its sole discretion. eInfochips is a trademark of eInfochips Ltd., registered in India, USA and other countries.
Qualcomm is a trademark of Qualcomm Inc., registered in the United States and other countries. Other product and brand names used herein may be trademarks or registered trademarks of their respective owners.
This document contains technical data that may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S. and international law is strictly prohibited.
Version 1.0 - 11 - eInfochips Confidential
Hardware Reference Manual
3 Preface
SOM
This document provides an overview of the ERAGON624 SOM based on Qualcomm’s APQ8053 SoC. It provides step-by-step information about hardware components and associated software release Android
8.1.0 (Oreo) used with Carrier KIT.
Intended Audience
This document is intended for technically qualified personnel. It is not intended for general audiences.
Intended Use
The development platform supports a wide range of industry interfaces and offers a comprehensive hardware and software design. It comes with Android software packages. This platform enables developers to evaluate and create solutions targeted at various market segments while customers and
OEMs can build their products based on these designs directly or with customizations.
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4 Overview
SOM
The ERAGON624 SoM provides an ideal building block for simple integration with a wide range of products in target markets requiring rich multimedia functionality, powerful graphics processing and video capabilities, as well as high-processing power, in a compact, RoHS compliant, fan less, cost effective SoM with low power consumption.
The ERAGON624 SoM leverages cutting edge mobile computing for embedded and industrial product designs, based on the Qualcomm Snapdragon™ 624 (APQ8053) 1.8 GHz octacore CPU, high performance
Adreno™ 506 GPU and a dedicated DSP for advanced A/V processing.
The SOM is equipped with full range of interfaces available in the Qualcomm Snapdragon APQ8053 SoC, which are routed on the 300 pins of three (100 pins each) board-to-board connectors.
The APQ8053 SOM supports Android Oreo operating system
The ERAGON624 SoM is ideal for rapid prototyping of product which can be used in customized carried
Board with same Pin-out by end customer. With support for almost all the peripherals, it reduces the design time of innovative applications and helps to achieve early time to market. With variety of peripherals, SOM is targeted for wide range of applications supporting bulk storage, faster connectivity, higher through put and performance at lower power.
Version 1.0 - 13 - eInfochips Confidential
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Key Features
CPU
Qualcomm Snapdragon 624
Octa-core ARM® Cortex® A53 at up to
1.8 GHz per core.
Both quad’s with 512KB L2 cache
64-Bit processor
Qualcomm Adreno 506 GPU.
1920 x 1080p video encoding/ decoding capability
Dual 14 bit ISP(Image Signal Processing)
Qualcomm Hexagon™ DSP
Memory
RAM:
Up to 4GB LPDDR3 at up to 933 MHz clock
Storage:
Up to 64 GB eMMC
Camera
3xMIPI CSI 4 Lane Camera Interface
(Only two can work simultaneously).
SOM
Audio
Input: o 6x Analog mic (WCD9335 Codec) o 3xDigital mic (WCD9335 Codec) o 2x Analog mic (PMIC Codec) o 1xDigital mic (PMIC Codec)
Output: o 1x Stereo Headset Output(WCD9335
Codec ) o 2x Speaker Output(WCD9335 Codec) o 1x Earphone output(WCD9335
Codec) o 2x Lineout(WCD9335 Codec) o 1x Speaker Output(PMIC Codec) o 1x Earphone output(PMIC Codec) o 1x Lineout(PMIC Codec)
Connectivity
WLAN 802.11 b/g/n 2.4GHz and 802.11 a/n/ac 5GHz
Bluetooth 4.2
GPS
Display
2 X MIPI DSI 4 Lane Display Interface
Resolution up to FHD 1920 x 1200, 60fps
Operating System
Android 8.1.0
USB & SD Card Interface
1x USB 3.0 or 2.0 Port
SD Card (SDC2 - 4 bit)
Power Input & Consumption
Voltage In: 3.8V (VBATT+) on J4805 connector from Carrier Board (J13)
Multimedia
Audio and Video as mention above
Miscellaneous
2x UART, 1x I2C, 2x MI2S, 1x SPI, 2x GPIO’s on
LS-Expansion Connector.
Physical & Operating Characteristics
Dimension: o SOM: 60mm x 35mm
Storage Temperature Range: o -20 to 70° C
Operating Temperature Range: o 0 to 60° C
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Applications
SOM
The ERAGON624 SoM is used in a wide range of products across many different target markets. Some of the typical applications are:
Consumer Electronics
Internet of Things
Marine
Automotive
Domestic Robot
Digital signage
Security & Surveillance
Biometric Access Control Systems
Home and Health Hub
Human-machine interface
Home energy management systems
In-flight entertainment
Intelligent industrial control systems
Portable medical
Version 1.0 - 15 - eInfochips Confidential
Hardware Reference Manual
5 Getting Started
SOM
Prerequisites
Before user power up the ERAGON 624 SOM board for the first time, will need following things:
Eragon 624 Carrier Board or Carrier Board with Exact Pin-outs and mating connectors
WiFi BT U.FL connector on SOM should be connected to Antenna on Carrier Board
Power input to Custom made Carrier/ Eragon 624 Carrier Board
Display board embraces 1080p OTM1901A LCD and multi touch capacitive touch panel on Carrier board if provision is given.
FFC Cable for connecting LCD display to the ERAGON 624 Board.
Starting the Eragon624 SOM for the first time with Eragon624 Carrier
To start the board, follow these simple steps:
Step 1. First, connect the ERAGON 624 Board to the Display board through FFC cable (DSI cable)
Step 2. Connect the Micro USB cable to connector J22 of carrier card
Step 3. Ensure that the boot switches SW1 are set to ‘000’, all in off position.
Step 4. Connect the complaint power supply to power connector J23.
Step 5. Press switch SW6 on carrier card for 2-3 seconds and then release.
Now board is in the booting process.
Please note that the first boot takes several minutes due to Androids initialization. Subsequent boot times should be faster.
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Hardware Reference Manual
6 System Block Diagram
SOM
Version 1.0
Figure 1 – ERAGON 624 SOM Block Diagram
- 17 - eInfochips Confidential
Hardware Reference Manual
ERAGON624 BOARD IMAGE
SOM
Figure 2 – ERAGON624 SOM Top View
Version 1.0
Figure 3 – ERAGON624 SOM BOT View
- 18 - eInfochips Confidential
Hardware Reference Manual
SOM
The ERAGON 624 SOM offers a wide boost of interfaces and peripherals, including several high-speed signals through its edge connectors.
The ERAGON624 SOM and Carrier are interfaced through three Hirose DF40C-100DP-0.4V Connectors.
The pin outs for these three connectors is described below,
SOM
Pin No.
J5.11
J5.12
J5.13
J5.14
J5.15
J5.16
J5.17
J5.1
J5.2
J5.3
J5.4
J5.5
J5.6
J5.7
J5.8
J5.9
J5.10
J5.18
J5.19
J5.20
J5.21
J5.22
J5.23
J5.24
J5.25
Version 1.0
J11.14
J11.15
J11.16
J11.17
J11.18
J11.19
J11.20
J11.21
J11.22
J11.23
J11.24
J11.25
J11.6
J11.7
J11.8
J11.9
J11.10
J11.11
J11.12
J11.13
Carrier
Board Pin
Number
J11.1
J11.2
J11.3
J11.4
J11.5
Signal Name
CSI0_CAM_GPIO_1
CSI1_CAM_GPIO_1
CSI0_CAM_GPIO_2
CSI1_CAM_GPIO_2
CSI0_PWDN
CSI2_CAM_GPIO_1
CSI0_RST
CSI2_CAM_GPIO_2
CSI2_PWDN
GND
CSI2_RST
MIPI_CSI2_CLK_N
GND
MIPI_CSI2_CLK_P
MIPI_CSI1_CLK_P
GND
MIPI_CSI1_CLK_N
Default Pin Function
CSI0 Camera GPIO
CSI1 Camera GPIO
CSI0 Camera GPIO
CSI0 Camera GPIO
CSI0 Power Down Signal
CSI2 Camera GPIO
CSI0 Camera Reset Signal
CSI2 Camera GPIO
Ground
CSI2 Camera Reset Signal
MIPI CSI2 Clock Negative
Ground
MIPI CSI2 Clock Positive
MIPI CSI1 Clock Positive
Ground
MIPI CSI1 Clock Negative
MIPI_CSI2_LANE1_P MIPI CSI2 Lane 1 Positive
GND Ground
MIPI_CSI2_LANE1_N MIPI CSI2 Lane 1 Negative
MIPI_CSI1_LANE0_N MIPI CSI1 Lane 0 Negative
GND Ground
MIPI_CSI1_LANE0_P MIPI CSI1 Lane 0 Positive
MIPI_CSI2_LANE0_N MIPI CSI2 Lane 0 Negative
GND Ground
- 19 -
-
-
-
-
-
-
-
-
Operating
Voltage Level
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
CSI2 Camera Power Down signal 1.8V
-
-
-
-
-
1.8V
-
- eInfochips Confidential
J11.35
J11.36
J11.37
J11.38
J11.39
J11.40
J11.41
J11.42
J11.43
J11.44
J11.26
J11.27
J11.28
J11.29
J11.30
J11.31
J11.32
J11.33
J11.34
J11.45
J11.46
J11.47
J11.48
J11.49
J11.50
Hardware Reference Manual
SOM
Pin No.
Carrier
Board Pin
Number
Signal Name
J5.35
J5.36
J5.37
J5.38
J5.39
J5.40
J5.41
J5.42
J5.43
J5.44
J5.26
J5.27
J5.28
J5.29
J5.30
J5.31
J5.32
J5.33
J5.34
J5.45
J5.46
J5.47
J5.48
J5.49
J5.50
Default Pin Function
MIPI_CSI2_LANE0_P
MIPI_CSI1_LANE1_P
MIPI CSI2 Lane0 Positive
MIPI CSI1 Lane 1 Positive
GND Ground
MIPI_CSI1_LANE1_N MIPI CSI1 Lane 1 Negative
MIPI_CSI2_LANE2_P
GND
MIPI CSI2 Lane 2 Positive
Ground
MIPI_CSI2_LANE2_N MIPI CSI2 Lane 2 Negative
MIPI_CSI1_LANE2_P MIPI CSI1 Lane 2 Postive
GND Ground
MIPI_CSI1_LANE2_N MIPI CSI1 Lane 2 Negative
MIPI_CSI2_LANE3_P MIPI CSI2 Lane 3 Positive
GND Ground
MIPI_CSI2_LANE3_N MIPI CSI2 Lane 3 Negative
MIPI_CSI1_LANE3_P MIPI CSI1 Lane 3 Positive
GND Ground
MIPI_CSI1_LANE3_N MIPI CSI1 Lane 3 Negative
MIPI_DSI1_CLK_N
GND
MIPI_DSI1_CLK_P
MIPI DSI1 Clock Negative
Ground
MIPI DSI1 Clock Positive
MIPI_CSI0_CLK_P
GND
MIPI CSI0 Clock Positive
Ground
MIPI_CSI0_CLK_N MIPI CSI0 Clock Negative
MIPI_DSI1_LANE0_N MIPI DSI1 Lane0 Negative
GND Ground
MIPI_DSI1_LANE0_P MIPI DSI1 Lane0 Positive
Version 1.0 - 20 -
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Operating
Voltage Level
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- eInfochips Confidential
Hardware Reference Manual
SOM
Pin No.
J5.51
Carrier
Board Pin
Number
J11.51
Signal Name Default Pin Function
MIPI_CSI0_LANE0_N MIPI CSI0 Lane0 Negative
J11.59
J11.60
J11.61
J11.62
J11.63
J11.64
J11.65
J11.66
J11.67
J11.52
J11.53
J11.54
J11.55
J11.56
J11.57
J11.58
J11.68
J11.69
J11.70
J11.71
J11.72
J11.73
J11.74
J11.75
J5.59
J5.60
J5.61
J5.62
J5.63
J5.64
J5.65
J5.66
J5.67
J5.52
J5.53
J5.54
J5.55
J5.56
J5.57
J5.58
J5.68
J5.69
J5.70
J5.71
J5.72
J5.73
J5.74
J5.75
GND
MIPI_CSI0_LANE0_P
Ground
MIPI CSI0 Lane0 Positive
MIPI_DSI1_LANE1_P MIPI DSI1 Lane1 Positive
GND Ground
MIPI_DSI1_LANE1_N MIPI DSI1 Lane1 Negative
MIPI_CSI0_LANE1_P MIPI CSI0 Lane1 Positive
GND Ground
MIPI_CSI0_LANE1_N MIPI CSI0 Lane1 Negative
MIPI_DSI1_LANE2_N MIPI DSI1 Lane2 Negative
GND Ground
MIPI_DSI1_LANE2_P MIPI DSI1 Lane2 Positive
MIPI_CSI0_LANE2_P MIPI CSI0 Lane2 Positive
GND Ground
MIPI_CSI0_LANE2_N MIPI CSI0 Lane2 Negative
MIPI_DSI1_LANE3_P MIPI DSI1 Lane3 Positive
GND Ground
MIPI_DSI1_LANE3_N MIPI DSI1 Lane3 Negative
MIPI_CSI0_LANE3_P MIPI CSI0 Lane3 Positive
GND Ground
MIPI_CSI0_LANE3_N MIPI CSI0 Lane3 Negative
MIPI_DSI0_CLK_N MIPI DSI0 Clock Negative
GND
MIPI_DSI0_CLK_P
CSI1_RST
Ground
MIPI DSI0 Clock Positive
CSI1 Reset GPIO Signal
Version 1.0 - 21 - eInfochips Confidential
SOM
Operating
Voltage Level
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.8V
Hardware Reference Manual
SOM
Pin No.
J5.76
Carrier
Board Pin
Number
J11.76
Signal Name
GND
J5.77
J5.78
J11.77
J11.78
Default Pin Function
Ground
CSI1_PWDN CSI1 Power Down GPIO Signal
MIPI_DSI0_LANE0_N MIPI DSI0 Lane0 Negative
J5.79
J5.80
J5.81
J5.82
J5.83
J5.84
J5.85
J586
J5.87
J5.88
J5.89
J5.90
J5.91
J5.92
J5.93
J5.94
J5.95
J5.96
J5.97
J5.98
J11.94
J11.95
J11.96
J11.97
J11.98
J5.99 J11.99
J5.100 J11.100
J11.79
J11.80
J11.81
J11.82
J11.83
J11.84
J11.85
J11.86
J11.87
J11.88
J11.89
J11.90
J11.91
J11.92
J11.93
CSI_I2C1_SCL CCI1 Camera I2C Clock Signal
MIPI_DSI0_LANE0_P MIPI DSI0 Lane0 Positive
CSI_I2C1_SDA
GND
CCI1 Camera I2C Data Signal
Ground
CSI_I2C0_SCL CCI0 Camera I2C Clock Signal
MIPI_DSI0_LANE1_P MIPI DSI0 Lane1 Positive
CSI_I2C0_SDA CCI0 Camera I2C Data Signal
MIPI_DSI0_LANE1_N MIPI DSI0 Lane1 Negative
CAM_MCLK2 24Mhz Master Clock 2 signal
GND
GND
Ground
Ground
MIPI_DSI0_LANE3_N MIPI DSI0 Lane3 Negative
CAM_MCLK3 24Mhz Master Clock 3 signal
MIPI_DSI0_LANE3_P MIPI DSI0 Lane3 Positive
GND Ground
GND
CAM_MCLK1
Ground
24Mhz Master Clock 1 signal
MIPI_DSI0_LANE2_P MIPI DSI0 Lane2 Positive
GND Ground
MIPI_DSI0_LANE2_N MIPI DSI0 Lane2 Negative
CAM_MCLK0
GND
24Mhz Master Clock 0 signal
Ground
SOM
Operating
Voltage Level
1.8V
-
1.8V
-
1.8V
-
-
-
-
-
1.8V
-
-
-
-
1.8V
1.8V
-
-
1.8V
-
1.8V
-
1.8V
-
Version 1.0 - 22 - eInfochips Confidential
Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4805.1 J13.1
Signal Name
VBAT
J4805.2 J13.2
J4805.3 J13.3
J4805.4 J13.4
VBAT
VBAT
VBAT
J4805.5 J13.5
J4805.6 J13.6
J4805.7 J13.7
J4805.8 J13.8
J4805.9 J13.9
J4805.10 J13.10
J4805.11 J13.11
J4805.12 J13.12
J4805.13 J13.13
J4805.14 J13.14
J4805.15 J13.15
J4805.16 J13.16
J4805.17 J13.17
J4805.18 J13.18
J4805.19 J13.19
J4805.20 J13.20
J4805.21 J13.21
J4805.22 J13.22
J4805.23 J13.23
J4805.24 J13.24
J4805.25 J13.25
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
GND
VBAT
GND
GND
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
GND
GND
GND
GND
VBUS_USB_IN
Version 1.0 - 23 -
Default Pin Function
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
3.5V-4.4V Input voltage
Ground
3.5V-4.4V Input voltage
Ground
Ground
Ground
Ground
Ground
Ground
USB Input from the USB 3.0
Connector
SOM
Operating
Voltage Level
3.8
-
3.8
-
-
3.8
3.8
3.8
3.8
3.8
-
-
-
-
5
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8 eInfochips Confidential
Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4805.26 J13.26
Signal Name
GND
J4805.27 J13.27 VBUS_USB_IN
J4805.28 J13.28
J4805.29 J13.29
J4805.30 J13.30
J4805.31 J13.31
J4805.32 J13.32
J4805.33 J13.33
J4805.34 J13.34
J4805.35 J13.35
J4805.36 J13.36
J4805.37 J13.37
J4805.38 J13.38
J4805.39 J13.39
J4805.40 J13.40
J4805.41 J13.41
J4805.42 J13.42
J4805.43 J13.43
J4805.44 J13.44
J4805.45 J13.45
J4805.46 J13.46
J4805.47 J13.47
J4805.48 J13.48
J4805.49 J13.49
J4805.50 J13.50
Default Pin Function
GND
VBUS_USB_IN
VSENSE_BATT_M
VBUS_USB_IN
VSENSE_BATT_P
VBUS_USB_IN
VREF_BAT_THERM
Ground
USB Input from the USB 3.0
Connector
Ground
-
5
-
USB Input from the USB 3.0
Connector
PMIC VBATT Voltage negative sense input
USB Input from the USB 3.0
Connector
PMIC VBATT Voltage positive sense input
5
-
5
USB Input from the USB 3.0
Connector
Reference Bias voltage for
Battery Thermistor
5
2.7
PMI Charge Enable control signal -
PMI Battery Thermistor signal -
PMI_CHG_EN
BAT_THERM
GND
BAT_CON_ID
Ground
PMI Battery ID Signal
-
-
USB3_SS_TX_P USB 3.0 Superspeed transmit positive
-
DSI_BACKLIGHT_PWM Display backlight control signal 1.8
USB3_SS_TX_M -
CODEC_DIV_CLK
GND
CODEC_RST_N
USB3_SS_RX_P
AUDIO_INT1
USB3_SS_RX_M
AUDIO_INT2
GND
PMIC_SPKR_DRV_M
USB 3.0 Superspeed transmit negative
9.6 MHz Audio codec Master clock
Ground
Audio codec Reset signal
USB 3.0 Superspeed receive positive
Audio codec interrupt 1
USB 3.0 Superspeed receive negative
Audio interrupt 2
Ground
PMIC speaker out negative
1.8
-
1.8
-
1.8
-
1.8
-
-
SOM
Operating
Voltage Level
Version 1.0 - 24 - eInfochips Confidential
Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4805.51 J13.51
Signal Name
USB_HS_D_M
J4805.52 J13.52
J4805.53 J13.53
J4805.54 J13.54
J4805.55 J13.55
J4805.56 J13.56
J4805.57 J13.57
J4805.58 J13.58
J4805.59 J13.59
J4805.60 J13.60
J4805.61 J13.61
J4805.62 J13.62
J4805.63 J13.63
J4805.64 J13.64
J4805.65 J13.65
J4805.66 J13.66
J4805.67 J13.67
J4805.68 J13.68
J4805.69 J13.69
J4805.70 J13.70
J4805.71 J13.71
J4805.72 J13.72
J4805.73 J13.73
J4805.74 J13.74
J4805.75 J13.75
PMIC_SPKR_DRV_P
USB_HS_D_P
PMIC_MIC3_IN_P
GND
PMIC_MIC3_IN_M
LCD_CABC
PMIC_HPH_R
USB_SNS
PMC_HPH_REF
LCD_BL_LED_K1
PMIC_HPH_L
LCD_BL_LED_K2
PMIC_HS_DET
LCD_VSP
PMIC_MIC2_IN
LCD_VSN
GND
F_LED1
PMIC_MIC1_IN_M
F_LED1
PMIC_MIC1_IN_P
LCD_BL_LED_A
EAR0_M
USB_CC1
Default Pin Function
SOM
Operating
Voltage Level
USB2.0 High speed negative
PMIC speaker out positive
USB2.0 High speed positive
PMIC MIC3 Input positive
Ground
PMIC MIC3 Input negative
PMI Backlight control signal
PMIC Headphone right channel -
-
-
-
-
-
-
PMI USB sense
PMIC Headphone reference
Display backlight LED cathode 1 -
PMIC Headphone left channel -
5
-
Display backlight LED cathode 2 -
PMIC Headphone detect
Display Bias supply positive
PMIC MIC2 Input
Display Bias supply negative
-
5.5
-5.5
Ground
Flash LED out
PMIC MIC1 Input negative
Flash LED out
PMIC MIC1 Input positive
Display backlight LED anode
Earpiece out negative
USB type C input CC1
-
-
-
-
-
-
-
-
Version 1.0 - 25 - eInfochips Confidential
J4805.77 J13.77
J4805.78 J13.78
J4805.79 J13.79
J4805.80 J13.80
J4805.81 J13.81
J4805.82 J13.82
J4805.83 J13.83
J4805.84 J13.84
J4805.85 J13.85
J4805.86 J13.86
J4805.87 J13.87
J4805.88 J13.88
J4805.89 J13.89
J4805.90 J13.90
J4805.91 J13.91
J4805.92 J13.92
J4805.93 J13.93
J4805.94 J13.94
J4805.95 J13.95
J4805.96 J13.96
J4805.97 J13.97
J4805.98 J13.98
J4805.99 J13.99
J4805.100 J13.100
Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4805.76 J13.76
Signal Name
EAR0_P
Default Pin Function
USB_CC2
TX_GTR_THRES
USB_ID
CDC_LO_M
GND
CDC_LO_P
VREG_L2_1P1
PMIC_MIC_BIAS1
VREG_L2_1P1
PMIC_MIC_BIAS2
VREG_L2_1P1
EXT_RF_CLK3
USB_VCONN
VREG_L11_2P95
USB_VCONN
VREG_L11_2P95
VREG_L6_1P8
VREG_L11_2P95
Earpiece out positive
USB type C input CC2
GPIO_112
PMI USB ID input
Codec Lineout negative
Ground
Codec Lineout positive
PMIC LDO2 output voltage
PMIC MIC Bias 1 voltage out
PMIC LDO2 output voltage
PMIC MIC Bias 2 voltage out
PMIC LDO2 output voltage
19.2 MHz RF clock 3
USB Type C Vconn supply
PMIC LDO11 output voltage
USB Type C Vconn supply
PMIC LDO11 output voltage
PMIC LDO6 output voltage
PMIC LDO11 output voltage
AUDIO_SLIMBUS_CLK
VCOIN
Audio slimbus clock
Coil cell voltage
AUDIO_SLIMBUS_D0 Audio slimbus Data 0
VREG_L12_VDDPX2_SDC PMIC LDO12 output voltage
AUDIO_SLIMBUS_D1 Audio slimbus Data 1
VREG_L22_2P8 PMIC LDO22 output voltage
SOM
Operating
Voltage Level
1.2
-
1.2
-
-
2.95
-
2.95
1.8
2.95
1.8
-
1.8
2.95
1.8
2.8
-
-
1.8
-
-
1.8
-
1.2
-
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Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4804.1 J16.1
Signal Name
DSI_TOUCH_INT
J4804.2 J16.2
J4804.3 J16.3
J4804.4 J16.4
J4804.5 J16.5
Default Pin Function
GND
TOUCH_RST
Display touch interrupt
Ground
Display touch reset
APQ_BOOT_CONFIG1 Boot config pin 1
FLASH_STROBE_NOW PMI_MPP_4/Flash strobe
J4804.6 J16.6
J4804.7 J16.7
J4804.8 J16.8
J4804.9 J16.9
J4804.10 J16.10
J4804.11 J16.11
J4804.12 J16.12
J4804.13 J16.13
J4804.14 J16.14
J4804.15 J16.15
J4804.16 J16.16
J4804.17 J16.17
J4804.18 J16.18
J4804.19 J16.19
J4804.20 J16.20
J4804.21 J16.21
J4804.22 J16.22
J4804.23 J16.23
J4804.24 J16.24
J4804.25 J16.25
APQ_BOOT_CONFIG3 Boot config pin 3
LCD_RST_N Display Reset
APQ_BOOT_CONFIG2 Boot config pin 2
LED_GPIO3 GPIO59/Red LED control
GND
GND
BLSP1_SPI_MOSI
SDC2_SDCARD_D3
Ground
Ground
BLSP1 SPI MOSI
SDC2 SDCARD Data 3
BLSP1_SPI_MISO
SDC2_SDCARD_D2
BLSP1_SPI_CS0_N
SDC2_SDCARD_D1
BLSP1 SPI MISO
SDC2 SDCARD Data 2
BLSP1 SPI CS 0
SDC2 SDCARD Data 1
BLSP5_UART_CTS BLSP5 UART CTS
SDC2_SDCARD_CMD SDC2 SDCARD command
BLSP5_UART_RX
SDC2_SDCARD_D0
BLSP5 UART RX
SDC2 SDCARD Data 0
GND
SDC2_SDCARD_CLK
HDMI_RST_N
SDCARD_DET_N
Ground
SDC2 SDCARD clock
HDMI Reset
SDCARD Detect
Version 1.0 - 27 - eInfochips Confidential
SOM
Operating
Voltage Level
1.8
1.8/2.95
1.8
1.8/2.95
1.8
1.8/2.95
1.8
1.8/2.95
-
1.8/2.95
1.8
1.8
1.8
-
1.8
1.8
-
1.8
1.8
1.8
1.8
-
-
1.8
1.8/2.95
Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4804.26 J16.26
Signal Name
BLSP1_SPI_CLK
J4804.27 J16.27 SD_WRITE_PROTECT
J4804.28 J16.28
J4804.29 J16.29
J4804.30 J16.30
J4804.31 J16.31
J4804.32 J16.32
J4804.33 J16.33
J4804.34 J16.34
J4804.35 J16.35
J4804.36 J16.36
J4804.37 J16.37
J4804.38 J16.38
J4804.39 J16.39
J4804.40 J16.40
J4804.41 J16.41
J4804.42 J16.42
J4804.43 J16.43
J4804.44 J16.44
J4804.45 J16.45
J4804.46 J16.46
J4804.47 J16.47
J4804.48 J16.48
J4804.49 J16.49
J4804.50 J16.50
Default Pin Function
BLSP5_UART_TX
GND
BLSP5_UART_RTS
USB_SS_SEL
SPKR_AMP_EN2
BLSP1 SPI clock
Test point
BLSP5 UART TX
Ground
BLSP5 UART RTS
USB switch select
Speaker amplifier Enable 2
GPIO_140 GPIO 140 nRESET/PME_CLEAR_EXP LAN7801 reset
TP_I2C_SCL
SPKR_AMP_EN1
Display I2C clock
Speaker amplifier Enable 1
TP_I2C_SDA
UART_MSM_TX
GND
UART_MSM_RX
DMIC0_CLK
BLSP2_I2C_SDA
DMIC0_DATA
BLSP2_I2C_SCL
MAG_DRDY_INT
Display I2C data
BLSP2 UART transmit/Debug
UART transmit
Ground
BLSP2 UART receive/Debug
UART receive
DMIC0 clock
BLSP2 I2C Data
DMIC0 Data
BLSP2 I2C clock
Magnetometer Interrupt
LED_GPIO2
GYRO_INT
HDMI_INT_GPIO
ACCL_INT1
MI2S_2_D0
GPIO9/Blue LED control
Gyro meter Interrupt
GPIO 54/HDMI Interrupt
Accelerometer Interrupt
MI2S2 Data0
SOM
-
1.8
1.8
1.8
1.8
1.8
1.8
-
1.8
-
1.8
1.8
Operating
Voltage Level
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
-
1.8
1.8
1.8
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Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4804.51 J16.51
Signal Name
ALSP_INT_N
J4804.52 J16.52
J4804.53 J16.53
J4804.54 J16.54
J4804.55 J16.55
J4804.56 J16.56
J4804.57 J16.57
J4804.58 J16.58
J4804.59 J16.59
J4804.60 J16.60
J4804.61 J16.61
J4804.62 J16.62
J4804.63 J16.63
J4804.64 J16.64
J4804.65 J16.65
J4804.66 J16.66
J4804.67 J16.67
J4804.68 J16.68
J4804.69 J16.69
J4804.70 J16.70
J4804.71 J16.71
J4804.72 J16.72
J4804.73 J16.73
J4804.74 J16.74
J4804.75 J16.75
MI2S_2_D1
GND
MI2S_2_WS
VREG_L5_1P8
MI2S_2_SCK
VREG_L5_1P8
BLSP4_UART_TX
GND
BLSP4_UART_RX
WDOG_DISABLE
BLSP4_I2C_SDA
USB_HUB_RST_N
BLSP4_I2C_SCL
MI2S_1_D3
LED_GPIO1
MI2S_1_D0
MI2S_1_SCK
MI2S_1_WS
MI2S_1_D2
MAG_INT
MI2S_1_D1
TEMP_INT
GND
FORCE_USB_BOOT
Default Pin Function
ALSP sensor interrupt
MI2S2 Data1
Ground
MI2S2 Word Sync clock
PMIC LDO5 output
MI2S2 clock
PMIC LDO5 output
BLSP4 UART transmit
Ground
BLSP4 UART receive
Watchdog disable
BLSP4 I2C Data
USB HUB reset
BLSP4 I2C clock
MI2S1 Data3
GPIO8/Green LED control
MI2S1 Data0
MI2S1 clock
MI2S1 Word Sync
MI2S1 Data2
Magnetometer Interrupt
MI2S1 Data1
Temperature sensor Interrupt
Ground
Force USB Boot
SOM
Operating
Voltage Level
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
-
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
-
1.8
1.8
-
1.8
1.8
Version 1.0 - 29 - eInfochips Confidential
Hardware Reference Manual
SOM Pin
No.
Carrier
Board Pin
Number
J4804.76 J16.76
Signal Name
BLSP6_I2C_SDA
J4804.77 J16.77
J4804.78 J16.78
J4804.79 J16.79
J4804.80 J16.80
J4804.81 J16.81
J4804.82 J16.82
J4804.83 J16.83
J4804.84 J16.84
J4804.85 J16.85
J4804.86 J16.86
J4804.87 J16.87
J4804.88 J16.88
J4804.89 J16.89
J4804.90 J16.90
J4804.91 J16.91
J4804.92 J16.92
J4804.93 J16.93
J4804.94 J16.94
J4804.95 J16.95
J4804.96 J16.96
J4804.97 J16.97
J4804.98 J16.98
J4804.99 J16.99
J4804.100 J16.100
KEY_SNAPSHOT
BLSP6_I2C_SCL
KEY_VOL_UP_N
BLSP6_UART_TX
BLSP8_SPI_CS0_N
BLSP6_UART_RX
KEY_FOCUS
BLSP8_SPI_CLK
PMI_WLED_EN_N
BLSP8_SPI_MOSI
GND
BLSP8_SPI_MISO
GND
GND
PRI_MI2S_MCLK_A
PM_RESIN_N1
GND
KYPD_PWR_N1
PRI_MI2S_MCLK_B
GND
GND
PMI_HAP_OUT_N
PRI_MI2S_MCLK_C
PMI_HAP_OUT_P
Default Pin Function
BLSP6 I2C Data 1.8
GPIO86/HDMI Hot Plug detect 1.8
BLSP6 I2C clock 1.8
GPIO85/ Volume Up key
BLSP6 UART transmit
BLSP8 SPI CS0
BLSP6 UART receive
1.8
1.8
1.8
1.8
GPIO87/HDMI Interrupt
BLSP8 SPI clock
PMI White LED Enable
BLSP8 SPI MOSI
Ground
BLSP8 SPI MISO
Ground
Ground
MI2S mater clock A
PM Reset input/ Volume Down -
Ground -
1.8
-
-
1.8
1.8
1.8
-
1.8
-
Power ON key
MI2S mater clock B
Ground
Ground
PMI Haptics Out negative
MI2S mater clock C
PMI Haptics Out positive
-
-
-
1.8
1.8
1.8
-
SOM
Operating
Voltage Level
Version 1.0 - 30 - eInfochips Confidential
Hardware Reference Manual
Major Blocks of ERAGON624 SOM Module
SOM
6.2.1
Processor APQ8053 - Features and interfaces
The Qualcomm APQ8053 includes a customized 64-bit ARM Cortex-A53, 1.8GHz high performance Octacore Processor.
It embraces Qualcomm Adreno TM 506 Graphics Processing Unit; up to 650MHz 3D graphics accelerator with 64-bit addressing.
Qualcomm Hexagon TM DSP to support always-on use cases.
512kB L2 cache memory
Memory Support Features
Non-PoP LPDDR3 SDRAM; 32-bit wide; up to 933MHz RAM through EBI interface.
Support up to 64GB external eMMC v5.1 memory via SDC1 interface.
There is SD card connector also available on carrier card for external storage devices interfaced through SDC2.
Multimedia features
Supports Three 4 Lane CSI Ports at 2.1 Gbps per lane data rate; however only two can work concurrently; as it has only two ISPs
All three MIPI CSI ports supports up to 21MP CMOS and CCD sensors.
Dual FHD (1900x1200) 60fps 4 Lane MIPI DSI ports supported.
Support 1080p at 90fps video encoding.
Two MI2S Ports for Audio interface.
Processor supports one port SLIMbus interface to WCD9335 codec.
APQ8053 also support CDC PDM port to interface with PM8953 for audio applications.
Web technologies
V8 JavaScript Engine optimizations
Webkit browser JPEG hardware decode acceleration
Networking Stack IP and HTTP tuning
Flash 10.x and video processor decode optimization.
Connectivity
8, 4-bits each BLSP Ports which can be configured as UART, I2C and SPI.
One USB 3.0/2.0 Port.
Gigabit Ethernet connectivity on Carrier card in USB3.0 HOST mode.
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Hardware Reference Manual
Wireless Connectivity
With WCN3680B, it supports 802.11 b/g/n mode for 2.4GHz band and with external FEM module; it supports 802.11 a/n/ac mode for 5GHz band.
WCN3680B also supports Bluetooth 4.2 LE and earlier.
With WGR7640 receiver, APQ8053 supports GPS location suite.
Power Management
Combination of PM8953 and PMI8952 interfaced through two 2-line SPMI.
Dedicated clock and reset lines; plus other GPIOs as needed.
SOM
6.2.2
Memory Interface
In ERAGON 624 SOM APQ8053 integrates with single Embedded Multi Chip Package (eMCP) has dual function of LPDDR3 RAM and eMMC v5.1 flash. SOM supports up to 4GB of LPDDR3 RAM at max. 933MHz clock and 64GB of eMMC flash.
The LPDDR3 has 32-bit wide bus width interfaced with APQ8053 through EBI.
The eMMC v5.1 has 8-bit wide bus width interfacing with APQ8053 through SDC1 interface.
6.2.3
Wi-Fi + BT Interface
The ERAGON 624 board deployed Qualcomm’s RF chip WCN3680B solution that integrates two different wireless connectivity technologies into a single device, the interfaces are:
Dual-band 2.4GHz and 5GHz WLAN compliant with IEEE 802.11 a/b/g/n specifications and supports external PA for both bands. ERAGON624 uses external PA at 5GHz band which also supports IEEE802.11 ac mode for data rate up to MCS 9. .
Bluetooth compliant with the BT specifications version 4.2 (BR/EDR + BLE).
All above RF signal is routed through a single antenna. To connect external antenna on ERAGON 624
SOM board, U.FL connector is provided. In addition, support for chip antenna (PN# FR05-S1-NO-1-004
; Gain of 1.5dBi on 2.4GHz & 4.7dBi on 5GHz) is given on ERAGON 624 carrier card. In this case, RF signal from SOM to carrier is carried through U.FL to U.FL cable.
6.2.4
GPS Interface
The ERAGON 624 board supports GPS interface, for which APQ8053 is interfaced with Qualcomm’s GNSS receiver chip WGR7640. U.FL connector is provided on both SOM and Carrier card which are connected through U.FL to U.FL cable. On carrier card GPS chip antenna (PN# 1575AT54A0010 ; Peak gain = 1.3dBi) is used to receive GPS signals. Also we can connect external antenna on U.FL connector on SOM module.
Version 1.0 - 32 - eInfochips Confidential
Hardware Reference Manual
6.2.5
PMIC Interface
SOM
ERAGON624 SOM module has combination of PM8953 and PMI8952 for Power management. Both the
PMICs are interfaced to APQ8053 through two-line SPMI bus.
6.2.6
System LEDs
There are three notification LEDs provided on SOM module as described below,
LED2 (APQ reset out LED): It’s glow indicates that processor came out of reset and booted successfully.
LED3 (Charging LED): Indicates battery charging.
LED4 (Green LED): Indicates that VPH power supply generated.
6.2.7
Shielding
Shields are Mounted on the WiFi (Top) Section, Processor + PMIC + eMMC (Top/Bottom) section & GPS section (Top), as per the FCC requirement for Single Module Certification.
Version 1.0 - 33 - eInfochips Confidential
Hardware Reference Manual
Guidelines to Design Carrier Board
SOM
6.3.1
Power Supply
ERAGON624 SOM can be powered through [email protected] DC input to give power to VBAT pins (as per pinouts table between SOM & Carrier).
6.3.2
Boot Configuration
The ERAGON624 can be configured to function in different modes placing the switch on carrier card.
Below schematic can be followed for Boot configuration:
Figure 4 – Boot Configuration Switch (SW1) schematic
Below table mentions different boot configurations options,
CONFIG_1
(Position-1)
0
0
0
0
CONFIG_2
(Position-2)
0
1
1
0
CONFIG_3
(Position-3)
0
0
1
0
FORCE_USB_BOOT
(Position-4)
0
0
0
1
Function
SDC1 -> SDC2 -> USB 3.0
SDC2 -> SDC1 -> USB 3.0
SDC1 -> USB 3.0
USB 3.0
Table 4: ERAGON 624 BOOT Configuration options
CONFIG switch in ON position indicates level 1. To boot through eMCP make sure switch is 0000.
Version 1.0 - 34 - eInfochips Confidential
Hardware Reference Manual
SOM
Figure 5 – Boot Configuration Switch (SW1)
6.3.3
General Purpose Keys (as per Eragon624 Carrier Board)
There are three general-purpose keys provided on carrier card. Their applications are as below,
SW6 (Power ON/Sleep mode switch): After power ON the board, this key need to be press for
2-3 seconds to boot SOM module. Also if board goes in the sleep mode, then by pressing SW6 we can get board out of sleep mode.
SW5 (Volume up): This key is pressed to up the volume of media.
SW4 (Fast boot switch or Volume down): This switch is pressed to get processor into Fast boot mode or to reduce the volume of media.
Power on switch
Volume Up Switch
Fast Boot
Switch/VOL_DOWN
Switch
Figure 6 – General Purpose Keys
6.3.4
USB Interface
APQ8053 supports one USB2.0 high speed and one USB3.0 Super speed Port that comes to Carrier card through B2B connector. USB3.0 can be further used for ADB/OTG mode for debug purpose.
USB signals can further be used for Gigabit Ethernet (By using USB to Ethernet converter) for USB pendrives or OTG purpose.
6.3.5
Audio Interface
ERAGON624 SOM can support PMIC’s internal codec. On the carrier Board, WCD9335 daughter board
(eI PN# 17_00348_01) can be connected by Placing connector PN# DF40HC(3.0)-30DS-0.4V(51). This daughter board also has WSA8810 audio amplifier interfaced with codec.
Version 1.0 - 35 - eInfochips Confidential
Hardware Reference Manual
SOM
ERAGON624 supports 5 analog MICs,1 headset MIC, 3 Digital MICs, 2 stereo speaker outputs, 1 headset output, 1 Earpiece output, 2 Line outputs and all these peripherals excluding can be connected on headset connector J19, Female headers J17 & J18. These Provisions can be given to carrier board for
Audio interfaces.
Figure 7 – WCD9335 Audio Code Daughter Board (custom made by eInfochips)
Below is the Schematic portion for J28 & J29 to connect the Audio Daughter Board. For layout spacing, need to contact to eInfochips.
Figure 8 – Schematic-1 on Carrier Board for Audio Code Daughter Board
Version 1.0 - 36 - eInfochips Confidential
Hardware Reference Manual
SOM
Figure 9 – Schematic-2 on Carrier Board for Audio Code Daughter Board
Figure 10 – Audio Headset Jack
Version 1.0
Figure 11 – Audio Headset Jack schematic
- 37 - eInfochips Confidential
Hardware Reference Manual
Below is the Pinout Specification of Headset Jack,
Pin Number Net Name
J19.1
J19.2
J19.3
J19.4
J19.5
J19.6
Pin Function
CONN_CDC_MIC2_P
CDC_HPH_L
CDC_HPH_R
CDC_HPH_REF
MBHC
NP
MIC2 Input Positive
Headphone Left Channel
Headphone Right Channel
Headphone Reference Signal (Ground)
Headset Detect Signal
Connected to Ground
Table 5: Headset (J19) Pinout
SOM
Figure 12 – Analog and Digital Codec Headers (J17 & J18)
Below is the Pinout Specification of J17,
Pin Number Net Name
J17.1
J17.2
J17.3
J17.4
J17.5
J17.6
J17.7
J17.8
J17.9
J17.10
J17.11
J17.12
J17.13
J17.14
J17.15
Version 1.0
CONN_CDC_MIC1_P
CONN_CDC_MIC5_P
GND
GND
CONN_CDC_MIC6_P
CONN_CDC_MIC3_P
GND
GND
CDC_SPEAKER1_OUT_P
CONN_CDC_MIC4_P
CDC_SPEAKER1_OUT_M
GND
CDC_EAR_M
CDC_SPEAKER2_OUT_P
CDC_EAR_P
Pin Function
MIC1 Input Positive
MIC5 Input Positive
Ground
Ground
MIC6 Input Positive
MIC3 Input Positive
Ground
Ground
Speaker1 Output Positive
MIC4 Input Positive
Speaker1 Output Negative
Ground
Earpiece Output Negative
Speaker2 Output Positive
Earpiece Output Positive
- 38 - eInfochips Confidential
Hardware Reference Manual
J17.16 CDC_SPEAKER2_OUT_M Speaker2 Output Negative
Table 6: Audio Header (J17) Pinout
SOM
Below is the Pinout Specification of J18,
Pin Number Net Name
J18.9
J18.10
J18.11
J18.12
J18.13
J18.14
J18.15
J18.16
J18.1
J18.2
J18.3
J18.4
J18.5
J18.6
J18.7
J18.8
CDC_MIC_BIAS3
CDC_MIC_BIAS4
GND
GND
CDC_MIC_BIAS1
CDC_DMIC_CLK1
GND
CDC_DMIC_DATA1
CDC_DMIC_CLK0
CDC_DMIC_CLK2
CDC_DMIC_DATA0
CDC_DMIC_DATA2
CDC_LINE_OUT2_P
CDC_LINE_OUT1_P
CDC_LINE_OUT2_M
CDC_LINE_OUT1_M
Pin Function
MIC Bias_3 Voltage
MIC Bias_4 Voltage
Ground
Ground
MIC Bias_1 Voltage
Digital MIC_1 Clock
Ground
Digital MIC_1 Data
Digital MIC_0 Clock
Digital MIC_2 Clock
Digital MIC_0 Data
Digital MIC_2 Data
Line Output_2 Positive
Line Output_1 Positive
Line Output_2 Negative
Line Output_1 Negative
Table 7: Audio Header (J18) Pinout
6.3.6
Sensors
ERAGON624 supports multiple sensors as below,
Magnetometer, Accelerometer& Gyrometer, Pressure sensor and ALSP (Ambient Light and
Proximity) sensor interfaced to APQ8053 through BLSP4_I2C Port
Temperature sensor in interfaced to APQ8053 through BLSP6_I2C Port
6.3.7
Micro SD Card
The ERAGON624 carrier card could be connected with Micro SD card interface for external storage device (SD card). SD card is interfaced with APQ8053 (on SOM) through 4-bit SDC2 data signals along with SDC2 clock and SDC2 command signals. GPIO_133 of APQ8053 is used to detect SD card insertion and removal.
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SOM
Figure 13 – Micro SD card connector schematic for carrier
6.3.8
DSI to HDMI
The Qualcomm APQ8053 Processor does not include a built-in HDMI interface. The ERAGON624 has the built-in MIPI-DSI 4 lanes interface, which is used, as a source for the HDMI output. A DSI to HDMI
Bridge Board can be used to performs this task and it supports a resolution from 480p to 720p at 30Hz.
While the ADV7533 on the DSI to HDMI Bridge board supports automatic input video format timing detection (CEA-861E) and an I2C channel from the APQ8053 allows the user to configure the operation of this Bridge Board. The BLSP3_I2C interface is used from the SoC that connects to the Bridge board.
This DSI to HDMI Bridge Board (eI PN# 17_00278_02) supports audio as well. The ERAGON624 uses a single bit MI2S_1 interface from the APQ8053 chip which is mentioned in the below block. The
ERAGON624 carrier should contains the 14 pin HDMI Audio Connector to connect to the Bridge Board.
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A 3-wire (audio out only) I2S channel is routed directly from the APQ8053 SoC I2S interface pins to the DSI-HDMI bridge Board through HDMI Audio connector.
Figure 14 – DSI to HDMI Audio Connector J26
Pin specifications for J26 is mentioned below,
Pin Number
J26.1
J26.2
J26.3
J26.4
J26.5
J26.6
J26.7
J26.8
J26.9
J26.10
J26.11
J26.12
J26.13
J26.14
Net Name Pin Function
MI2S_1_D0
DSI2HDMI_INT_N
MI2S_1_WS
HDMI_HPD_N
MI2S_1_SCK
CEC_CLK/ PRI_MI2S_MCLK_A
GND
GND
NC
VCC_1V8
NC
VCC_5V0
NC
VCC_3V3
I2S Data 0 signal
HDMI Interrupt Signal
I2S Word Sync Clock l
HDMI Hot Plug Detect Signal
I2S Clock
9.6MHz System Clock frequency
Ground
Ground
Not Connected
1.8V Supply
Not Connected
5V Supply
Not Connected
3.3V Supply
Table 8: HDMI Audio Connector (J26) Pinout
6.3.9
HDMI to CSI Audio interface
The Qualcomm APQ8053 Processor does not include a built-in HDMI interface. The ERAGON624 has the built-in MIPI-CSI 4 lanes interface, which is used, as HDMI input. A HDMI to CSI bridge chip
TC358840 converts HDMI signals to MIPI CSI Signals. These CSI signals interfaced with APQ8053 through MIPI CSI connectors mentioned in CSI section.
This Bridge Board supports audio as well. The ERAGON624 uses a MI2S_1 interface from the APQ8053 chip which is mentioned in the below block. The ERAGON624 contains the 16 pin HDMI Audio
Connector (J27) on the board. A 6-wire (audio input) I2S channel is routed directly from the APQ8053
SoC I2S interface pins to the HDMI to CSI Bridge Board through HDMI Audio connector.
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Figure 15 – HDMI to CSI Audio Connector J27
Pin specifications for J27 is mentioned below,
Pin Number Net Name
J27.1
J27.2
J27.3
J27.4
J27.5
J27.6
J27.7
J27.8
J27.9
J27.10
J27.11
J27.12
J27.13
J27.14
J27.15
J27.16
VCC_3V3
VCC_3V3
VREG_L2_1P1
VCC_1V8
HDMI_I2C_SDA
HDMI_I2C_SCL
MI2S_1_SCK
MI2S_1_WS
MI2S_1_D3
MI2S_1_D2
MI2S_1_D1
MI2S_1_D0
HDMI_INT_GPIO
HDMI_RST_N
GND
GND
Pin Function
3.3V Supply
3.3V Supply
1.2V Supply
1.8V Supply
HDMI I2C Data
HDMI I2C Clock
I2S Clock
I2S Word Sync Clock
I2S Data 3 Signal
I2S Data 2 Signal
I2S Data 1 Signal
I2S Data 0 Signal
HDMI Interrupt
HDMI Reset
Ground
Ground
Table 9: HDMI Audio Connector (J27) Pinout
6.3.10
WiFi + BT chip antenna
As mentioned in ERAGON624 SOM blocks, Wi-Fi + BT RF signal routed from SOM to Carrier card through U.FL-to-U.FL cable connected from connector J8 at SOM and connector J4 at Carrier card. After that, it is interfaced to Fractus chip antenna FR05-S1-NO-1-004 (ref ANTENNA1) to radiate. During the design of carrier Board, customer needs to use the same chip Antenna on application Board.
For Placement & routing of the Antenna on Carrier Board, contact eInfochips to get the detailed information.
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Figure 16 – Routing of UFL cable from SOM to Carrier
6.3.11
GPS chip antenna
GPS receiver signal received from GPS chip antenna 1575AT54A0010E mounted on Carrier card (ref
ANT1) after passing through SAW filter and LNA is routed to SOM module through U.FL-to-U.FL cable connected from connector J21 at Carrier Card to connector J1 at SOM module.
Figure 17 – Routing of UFL cable from SOM to Carrier
6.3.12
M.2 (4G LTE) connector
ERAGON624 SOM to plug 4G LTE modem on Carrier card by placing 75-pin M.2 connector on Carrier
Board Design. This 4G module is interfaced with second downstream port of USB Hub (it can be used to expand USB ports) through which it is connected to APQ8053 processor, MI2S_2 interface, BLSP4 UART interface and few other GPIOs of APQ8053 and Dual SIM card connectors (SIM1-J38, SIM2-J36).
For more details, contact eInfochips.
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Figure 18 – M.2 connector (J35)
SOM
Pinout specifications of J35 are below,
Pin Number Net Name
J35.1 CONFIG_3
J35.2
J35.3
J35.4
J35.5
J35.6
J35.7
J35.8
J35.9
J35.10
J35.11
J35.12
J35.13
J35.14
J35.15
J35.16
J35.17
J35.18
J35.19
J35.20
Version 1.0
Figure 19 – SIM card connectors (J38 & J36)
VCC_3V7_LTE
GND
VCC_3V7_LTE
GND
LTE_MODEM_POWER
USBDN_DP2
LTE_MODEM_W_DISABLE#1
USBDN_DM2
LTE_MODEM_LED#1
GND
NC
NC
NC
NC
NC
NC
NC
NC
MI2S_2_SCK
- 44 -
Pin Function
DNP Pull up (1.8V) & Pull down (GND)
Option
3.7V Supply For LTE Modem
Ground
3.7V Supply For LTE Modem
Ground
LTE Modem Power Control Signal
USB High Speed Data Positive Signal
LTE RF Radio Disable control GPIO
USB High Speed Data Negative Signal
LED Driver Control GPIO
Ground
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
I2S_2 Bit Clock eInfochips Confidential
Hardware Reference Manual
J35.21
J35.22
J35.23
J35.24
J35.25
J35.26
J35.27
J35.28
J35.29
J35.30
CONFIG_0
MI2S_2_D0
LTE_WAKE_HOST#
MI2S_2_D1
LTE_MODEM_DPR
LTE_MODEM_W_DISABLE#2
GND
MI2S_2_WS
USB_SSRXM_DN2
SIM1_RST
Pin Number
J35.47
J35.48
J35.49
J35.50
J35.51
J35.52
J35.53
J35.54
J35.55
J35.56
J35.57
J35.58
J35.59
J35.60
J35.61
J35.62
J35.39
J35.40
J35.41
J35.42
J35.43
J35.44
J35.45
J35.46
J35.31
J35.32
J35.33
J35.34
J35.35
J35.36
J35.37
J35.38
Version 1.0
Net Name
USB_SSRXP_DN2
SIM1_CLK
GND
SIM1_DATA
USB_SSTXM_DN2
SIM1_PWR
USB_SSTXP_DN2
NC
GND
SIM2_DETECT
NC
SIM2_DATA
NC
SIM2_CLK
GND
SIM2_RST
NC
NC
NC
NC
NC
SIM2_PWR
NC
NC
GND
NC
GND
NC
TP26
BLSP1_SPI_MISO
TP27
BLSP4_UART_TX
SOM
DNP Pull Up (1.8V) Option
I2S_2 Data 0
Wake Host Signal
I2S_2 Data 1
Dynamic Power Control
LTE GNSS Radio Disable control GPIO
Ground
I2S_2 Word Sync Clock
USB Super Speed Receive Data Negative
SIM Card _1 Reset Signal
Pin Function
USB Super Speed Receive Data Positive
SIM Card _1 Clock
Ground
SIM Card _1 Data Signal
USB Super Speed Transmit Data Negative
SIM Card _1 Power Supply
USB Super Speed Transmit Data Positive
Not Connected
Ground
SIM Card _2 Detect Signal
Not Connected
SIM Card _2 Data Signal
Not Connected
SIM Card _2 Clock
Ground
SIM Card _2 Reset Signal
Not Connected
SIM Card _2 Power Supply
Not Connected
Not Connected
Ground
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Ground
Not Connected
Test Point
GPIO for Coexistence
Test Point
Coexistence UART Transmit
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J35.63
J35.64
J35.65
J35.66
J35.67
J35.68
J35.69
J35.70
TP28
BLSP4_UART_RX
TP29
SIM1_DETECT
LTE_MODEM_RST#
NC
CONFIG_1
VCC_3V7_LTE_RF
Test Point
Coexistence UART Receive
Test Point
SIM Card _1 Detect Signal
Modem Reset Signal
Not Connected
DNP Pull Up (1.8V) Option
3.7V LTE RF Power Supply
SOM
Pin Number
J35.71
J35.72
J35.73
J35.74
J35.75
Net Name Pin Function
GND
VCC_3V7_LTE_RF
GND
VCC_3V7_LTE_RF
CONFIG_2
Ground
3.7V LTE RF Power Supply
Ground
3.7V LTE RF Power Supply
DNP Pull Up (1.8V) Option
Table 10: M.2 connector (J35) Pinout
SIM Card_1 Connector Pin specifications are as follows,
Pin Number
J38.1
J38.2
J38.3
J38.4
J38.5
J38.6
J38.7
J38.8 to J38.17
Net Name Pin Function
SIM1_PWR_SOCKET
SIM1_RST_ESD
SIM1_CLK_ESD
GND
VPP
SIM1_DATA_ESD
SIM1_DETECT
SIM_SHEILD_GND
SIM1 Power Supply
SIM1 Reset Signal
SIM1 Clock
Ground
Vpp Output
SIM1 Data
SIM1 Card Detect
Shield Ground
Table 11: SIM CARD_1 connector (J38) Pinout
SIM Card_2 Connector Pin specifications are as follows,
Pin Number
J36.1
J36.2
J36.3
J36.4
J36.5
J36.6
J36.7
J36.8 to J36.17
Net Name Pin Function
SIM2_PWR_SOCKET
SIM2_RST_ESD
SIM2_CLK_ESD
GND
VPP
SIM2_DATA_ESD
SIM2_DETECT
SIM_SHEILD_GND
SIM2 Power Supply
SIM2 Reset Signal
SIM2 Clock
Ground
Vpp Output
SIM2 Data
SIM2 Card Detect
Shield Ground
Table 12: SIM CARD_2 connector (J36) Pinout
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6.3.13
RTC
For Time and Date update, ERAGON624 has a support to connect external rechargeable Coin Cell battery on connector J8 at Carrier card.
SOM
Connect +Ve terminal of battery to J8.1 pin and GND to J8.2 pin.
Figure 20 – RTC connector (J8)
6.3.14
Debug Port
ERAGON624 support a debug Port to capture the system logs. Carrier card has on board UART to USB converter chip FT230XQ-R (U55). It converts BLSP2 UART signals routed from SOM to carrier through
B2B connectors to USB high-speed signals.
Therefore, to capture the logs, user only need to connect Micro USB cable to connector J22 on carrier card.
Figure 21 – Debug Port connection (J22)
Pinout specification of J22 mentioned below,
Pin Number Net Name
J22.1
J22.2
J22.3
J22.4
J22.5
VBUS_5V
USB_DEBUG_DM
USB_DEBUG_DP
NC
GND
Pin Function
USB 5V Supply
USB Data Negative
USB Data Positive
Not Connected
Ground
Table 13: Debug Port Connector (J22) Pinout
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7 Electrical Specification
Absolute Maximum Ratings
VBATT+
VCOIN
USB_VBUS
Parameter
Main Battery Input Supply Voltage
Min
-0.3
-0.5 RTC Input Supply Voltage
USB VBUS Input Supply Voltage -0.3
Table 14 : Absolute Maximum Ratings
Max
6.0
3.5
28
Operating Conditions
Parameter
VBATT+ Main Battery Input Supply Voltage
VCOIN RTC Input Supply Voltage
Min
2.5
2.0
Typ
3.6
3.0
USB_VBUS USB VBUS Input Supply Voltage 3.7
Table 15 : Operating Conditions
5.0
Max
4.75
3.25
10
Unit
V
V
V
SOM
Unit
V
V
V
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8 Mechanical Specification
SOM Board Dimensions
SOM
Shields Dimensions
Figure 22 – SOM Module Dimension
Version 1.0
Figure 23 – SOM Module TOP side Shields
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SOM
Figure 24 – SOM Module BOT side Shield
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9 Special Care when using ERAGON624 SOM Board
Development Device Notice
SOM
This device contains RF/digital hardware and software intended for engineering development, engineering evaluation, or demonstration purposes only and is intended for use in a controlled environment. This device is not being placed on the market, leased or sold for use in a residential environment or for use by the general public as an end user device.
Anti-Static Handling Procedure
This device has exposed PCB and chips. Accordingly, proper anti-static precautions should be employed when handling the kit, including:
Use a grounded anti-static mat
Use a grounded wrist or foot strap
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10 About eInfochips
SOM eInfochips is a partner of choice for Fortune 500 companies for product innovation and hi-tech engineering consulting. Since 1994, eInfochips has provided solutions to key verticals like Aerospace &
Defense, Consumer Electronics, Energy & Utilities, Healthcare, Home, Office, and Industrial Automation,
Media & Broadcast, Medical Devices, Retail & e-Commerce, Security & Surveillance, Semiconductor,
Software/ISV and Storage & Compute.
Covering every aspect of the product lifecycle, eInfochips draws from an experience of building 500+ products that have over 10 Million units deployed – to provide solutions on Product Design and
Development, QA and Certifications, Reengineering, Sustenance and Volume Production. Being an innovation driven company, 5% of our revenues are earmarked for building reusable IPs that will accelerate product design cycles and reduce product risks.
About 80% of eInfochips business comes from companies with revenues over $1 Billion, and 60% of total business from building life and mission critical products. eInfochips has the experience, expertise and infrastructure to deliver complex, critical and connected products.
Today, more than 1400 chip mates operate from over 10 Design Centers and dozen Sales Offices spread across Asia, Europe and US.
Our clients have recognized our teams for commitment, teamwork and initiatives that we have brought forward, adding immense value to client processes and products. Chip mates have a strong growth path defined for them, with specific soft-skills training modules – Lagaan, Pegasus and Altius – to groom leaders for the future.
‘At eInfochips we are determined that our growth should empower the ones in need. Every year we contribute 1% of our profits for development in education and healthcare’.
Contact Information:
Corporate Headquarter: eInfochips Ltd.
11 A/B Chandra Colony,
Behind Cargo Motors,
Off. C. G. Road,
Ellis bridge,
Ahmedabad 380 006
Tel +91-79-2656 3705
Fax +91-79-2656 0722
Technical Assistance:
Technical Support:
Sales/Marketing Support:
Version 1.0
USA Office: eInfochips, Inc.
1230 Midas Way, Suite# 200
Sunnyvale, CA 94085.
USA
Tel +1-408-496-1882
Fax +1-801-650-1480 eInfochips Qualcomm portal
( www.supportcenter.einfochips.com
)
- 52 - eInfochips Confidential
FCC Warning
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
-Reorient or relocate the receiving antenna.
-Increase the separation between the equipment and receiver.
-Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
-Consult the dealer or an experienced radio/TV technician for help.
*RF warning for Mobile device:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment.
This equipment should be installed and operated with minimum distance 20cm between the radiator & your body.
IC Warning
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
*RF warning for Mobile device:
This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body.
This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions:
(1) This device may not cause interference; and
(2) This device must accept any interference, including interference that may cause undesired operation of the device.
Cet appareil est conforme aux CNR exemptes de licence d'Industrie Canada . Son fonctionnement est soumis aux deux conditions suivantes :
( 1 ) Ce dispositif ne peut causer d'interférences ; et
( 2 ) Ce dispositif doit accepter toute interférence , y compris les interférences qui peuvent causer un mauvais fonctionnement de l'appareil. la distance entre l'utilisateur et le dispositif ne doit pas être inférieure à 20 cm
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