Advantech SOM-6898 7th Gen Intel Core/Celeron Processors COM Express Compact Module Type 6 Guide

SOM-6898 COMe TYPE6

R120 2019’10’25

０

Contents

1. Introduction ................................................................................................ ７

1.1. About This Document ............................................................................. ７

1.2. Signal Table Terminology ....................................................................... ７

1.3. Terminology ............................................................................................ ８

1.4. Reference Documents ............................................................................ １２

1.5. Revision History ...................................................................................... １２

1.6. SOM-6898 Block Diagram ...................................................................... １３

2. COM Express Type 6 Interfaces ............................................................... １４

2.1. COM Express Type 6 Connector Layout ................................................ １４

2.2. COM Express Type 6 Connector Pin-out ............................................... １５

2.3. PCI Express ............................................................................................ ２３

2.3.1. COM Express A-B Connector and C-D Connector PCIe Groups...................... ２３

2.3.2. General Purpose PCIe Signal Definitions ......................................................... ２３

2.3.3. PCI Express Lane Configurations – Per COM Express Spec ........................... ２８

2.3.4. PCI Express* General Routing Guidelines ....................................................... ２９

2.3.4.1. PCI Express Insertion Loss Budget with Slot Card ................................ ２９

2.3.4.2. PCI Express Insertion Loss Budget with Carrier Board PCIE Device .... ３１

2.3.5. PCI Express* Trace Length Guidelines ............................................................ ３３

2.4 PEG (PCI Express Graphics) *SOM-6898 is not support PEG. .............. ３５

2.4.1 PEG Signal Definitions ...................................................................................... ３５

2.4.2. PEG* General Routing Guidelines ................................................................... ４１

2.4.3. PEG* Trace Length Guidelines ........................................................................ ４２

2.5 Digital Display Interfaces (DDI) ............................................................... ４４

2.5.1. DDI Signal Definitions ...................................................................................... ４４

2.5.2 Digital Display Interfaces (DDI) Routing Guidelines .......................................... ５２

2.5.2.1. DisplayPort Routing Guidelines ............................................................ ５２

2.5.2.2. HDMI / DVI Routing Guidelines ............................................................. ５４

2.5.3. HDMI / DVI Level Shifter Requirements ........................................................... ５６

2.5.4. ESD Protection ................................................................................................ ５６

2.6. LAN Interface .......................................................................................... ５７

2.6.1. LAN Signal Definitions ..................................................................................... ５７

2.6.2. LAN Routing Guidelines ................................................................................... ５９

2.6.3. LAN Trace Length Guidelines .......................................................................... ６０

2.6.4. Reference Ground Isolation and Coupling ....................................................... ６１

０

2.7. USB2.0 Ports .......................................................................................... ６２

2.7.1. USB2.0 Signal Definitions ................................................................................ ６２

2.7.1.1. USB Over-Current Protection (USB_x_y_OC#) ..................................... ６５

2.7.1.2. Powering USB devices during S5 ......................................................... ６５

2.7.2. USB2.0 Routing Guidelines ............................................................................. ６６

2.7.2.1. USB 2.0 General Design Considerations and Optimization ................... ６７

2.7.2.2. USB 2.0 Port Power Delivery ................................................................ ６７

2.7.2.3. USB 2.0 Common Mode Chokes .......................................................... ６８

2.7.2.4. EMI / ESD Protection ............................................................................ ６９

2.7.3. USB2.0 Trace Length Guidelines ..................................................................... ７０

2.8. USB3.0 ................................................................................................... ７１

2.8.1. USB3.0 Signal Definitions ................................................................................ ７１

2.8.1.1. USB Over-Current Protection (USB_x_y_OC#) ..................................... ７４

2.8.1.2. EMI / ESD Protection ............................................................................ ７４

2.8.2. USB3.0 Routing Guidelines ............................................................................. ７５

2.8.3. USB3.0 Trace Length Guidelines ..................................................................... ７６

2.9. SATA ...................................................................................................... ７７

2.9.1. SATA Signal Definitions ................................................................................... ７７

2.9.2. SATA Routing Guidelines ................................................................................ ７９

2.9.2.1. General SATA Routing Guidelines ........................................................ ８０

2.9.3. SATA Trace Length Guidelines ........................................................................ ８１

2.10. LVDS .................................................................................................... ８２

2.10.1. Signal Definitions ........................................................................................... ８２

2.10.1.1. Display Timing Configuration .............................................................. ８５

2.10.1.2. Backlight Control ................................................................................. ８５

2.10.2. LVDS Routing Guidelines .............................................................................. ８６

2.10.3. LVDS Trace Length Guidelines ...................................................................... ８７

2.11. Embedded DisplayPort (eDP) *SOM-6898 is Option function .............. ８８

2.11.1 eDP Signal Definitions .................................................................................... ８８

2.11.2. eDP Trace Length Guidelines ........................................................................ ９０

2.12. VGA ...................................................................................................... ９１

2.12.1. VGA Signal Definitions ................................................................................... ９１

2.12.2. VGA Routing Guidelines ................................................................................ ９３

2.12.2.1. RGB Analog Signals ........................................................................... ９３

2.12.2.2. HSYNC and VSYNC Signals .............................................................. ９３

2.12.2.3. DDC Interface ..................................................................................... ９３

2.12.2.4. ESD Protection/EMI ............................................................................ ９３

１

2.12.3. VGA Trace Length Guidelines ....................................................................... ９４

2.13. Digital Audio Interfaces ......................................................................... ９５

2.13.1. Audio Codec Signal Descriptions ................................................................... ９５

2.13.2. Audio Routing Guidelines............................................................................... ９７

2.13.3. Audio Trace Length Guidelines ................................................................... ９８

2.14. LPC Bus – Low Pin Count Interface ..................................................... ９９

2.14.1. LPC Signal Definition ..................................................................................... ９９

2.14.2. LPC Routing Guidelines ................................................................................. １００

2.14.2.1 General Signals ................................................................................... １００

2.14.2.2 Bus Clock Routing ............................................................................... １０１

2.14.3. LPC Trace Length Guidelines ........................................................................ １０１

2.15. SPI – Serial Peripheral Interface Bus ................................................... １０２

2.15.1. SPI Signal Definition ...................................................................................... １０２

2.15.2. SPI Routing Guidelines .................................................................................. １０４

2.15.3. SPI Trace Length Guidelines ......................................................................... １０４

2.16. General Purpose I2C Bus Interface...................................................... １０５

2.16.1. Signal Definitions ........................................................................................... １０５

2.16.2. I2C Routing Guidelines .................................................................................. １０６

2.16.3. I2C Trace Length Guidelines ......................................................................... １０７

2.16.4. Connectivity Considerations ........................................................................... １０７

2.17. System Management Bus (SMBus) ..................................................... １０８

2.17.1. SMB Signal Definitions .................................................................................. １０９

2.17.2. SMB Routing Guidelines ................................................................................ １１０

2.17.3. SMB Trace Length Guidelines ....................................................................... １１０

2.18. General Purpose Serial Interface ......................................................... １１１

2.18.1. Serial interface Signal Definitions ................................................................... １１１

2.18.2. Serial interface Routing Guidelines ................................................................ １１２

2.18.3. Serial interface Trace Length Guidelines ....................................................... １１２

2.19. CAN Interface *SOM-6898 is not support CAN Interface. .................... １１３

2.19.1. CAN interface Signal Definitions .................................................................... １１３

2.19.2. CAN interface Routing Guidelines .................................................................. １１３

2.19.3. CAN interface Trace Length Guidelines ......................................................... １１４

2.20. Miscellaneous Signals .......................................................................... １１５

2.20.1. Miscellaneous Signals ................................................................................... １１５

2.20.2. Power Management Signals .......................................................................... １１８

2.20.3. Thermal Interface ........................................................................................... １２０

2.20.4. Miscellaneous Signals Routing Guidelines ..................................................... １２０

２

2.20.5. Miscellaneous Signals Trace Length Guidelines ............................................ １２０

3. Power......................................................................................................... １２１

3.1. General Power requirements .................................................................. １２１

3.2. VCC5_SBY Routing ................................................................................ １２１

3.3. ATX and AT Power Sequencing Diagrams ............................................ １２１

3.4. Input Power - Rise Time ......................................................................... １２５

3.5. Design Considerations for Carrier Boards containing FPGAs/CPLDs ... １２６

4. Electrical Characteristics ........................................................................... １２７

4.1. Absolute Maximum Ratings .................................................................... １２７

4.2. DC Characteristics .................................................................................. １２７

4.3. Inrush Current ......................................................................................... １２７

３

List of Tables

Table 1: Signal Table Terminology Descriptions ................................................................ ７

Table 3: Conventions and Terminology ............................................................................. ８

Table 4: COM Express Type6 Pin-out ............................................................................１５

Table 5: General Purpose PCI Express Signal Descriptions ..........................................２３

Table 6: PCI Express* Slot Card / Device Down Trace Length Guidelines .....................３４

Table 7: PEG Signal Description ....................................................................................３５

Table 8: PCI Express* Slot Card / Device Down Trace Length Guidelines .....................４３

Table 9: Port / HDMI / DVI Pin-out of Type 6 ..................................................................４４

Table 10: DDI1 Signal Description ..................................................................................４５

Table 11: DDI2 Signal Description ..................................................................................４７

Table 12: DDI3 Signal Description ..................................................................................４９

Table 13: DisplayPort Insertion Loss Budget ..................................................................５２

Table 14: DisplayPort Connector / Device Down Trace Length Guidelines ....................５３

Table 15: HDMI / DVI (TMDS) Insertion Loss Budget .....................................................５４

Table 16: HDMI / DVI Connector / Device Down Trace Length Guidelines ....................５５

Table 17: LAN Interface Signal Descriptions ..................................................................５７

Table 18: 10/100/1000 Ethernet Insertion Loss Budget, 100 MHz ..................................５９

Table 19: Ethernet Trace Length Guidelines ..................................................................６０

Table 20: USB Signal Descriptions .................................................................................６２

Table 21 USB Insertion Loss Budget, 400 MHz ..............................................................６６

Table 22: USB2.0 Trace Length Guidelines ....................................................................７０

Table 23: USB3.0 Signal Definitions ...............................................................................７１

Table 24: USB3.0 Insertion Loss Budget ........................................................................７５

Table 25: USB3.0 Trace Length Guidelines ....................................................................７６

Table 26: SATA Signal Definitions ..................................................................................７７

Table 27: SATA Insertion Loss Budge ............................................................................７９

Table 28: SATA Trace Length Guidelines .......................................................................８１

Table 29: LVDS Signal Definitions ..................................................................................８２

Table 30: LVDS Trace Length Guidelines .......................................................................８７

Table 31: eDP Signal Definitions ....................................................................................８８

Table 32: DisplayPort Connector / Device Down Trace Length Guidelines ....................９０

Table 33: VGA Signal Definitions ....................................................................................９１

Table 34: VGA Trace Length Guidelines ........................................................................９４

４

Table 35: Audio Codec Signal Descriptions ....................................................................９５

Table 36: Audio Trace Length Guidelines .......................................................................９８

Table 37: LPC Interface Signal Definition .......................................................................９９

Table 38: LPC Trace Length Guidelines ..................................................................... １０１

Table 39: SPI Interface Signal Definition .................................................................... １０２

Table 40: Effect of the BIOS disable signals ............................................................... １０４

Table 41: SPI Trace Length Guidelines ...................................................................... １０４

Table 42: General Purpose I2C Interface Signal Descriptions .................................... １０６

Table 43: I2C Trace Length Guidelines ...................................................................... １０７

Table 44: SMB Signal Definitions ............................................................................... １０９

Table 45: SMB Trace Length Guidelines .................................................................... １１０

Table 46: Serial interface Signal Definitions ............................................................... １１１

Table 47: Serial interface Trace Length Guidelines .................................................... １１２

Table 48: CAN interface Signal Definitions ................................................................. １１３

Table 49: CAN interface Trace Length Guidelines ...................................................... １１４

Table 50: Miscellaneous Signal Definitions ................................................................. １１５

Table 51: Power Management Signal Definitions ....................................................... １１８

Table 52: Thermal Management Signal Definitions .................................................... １２０

Table 53: Power Management Timings ...................................................................... １２４

Table 54: Absolute Maximum Ratings ........................................................................ １２７

Table 55: Input Power Consumption of 12V / 4.75V / 20V .......................................... １２７

Table 56: Inrush Current ............................................................................................. １２７

５

List of Figures

Figure 1: SOM-6898 Block Diagram ...............................................................................１３

Figure 2: COM Express Type6 Connector Layout ..........................................................１４

Figure 3 : Topology for PCI Express Slot Card. ..............................................................３３

Figure 4: Topology for PCI Express Device Down. .........................................................３３

Figure 5: Topology for PCI Express Slot Card. ...............................................................４２

Figure 6: Topology for PCI Express Device Down. .........................................................４２

Figure 7: DisplayPort Loss Budget .................................................................................５２

Figure 8: Topology for DisplayPort .................................................................................５３

Figure 9: HDMI / DVI (TMDS) Loss Budget ....................................................................５４

Figure 10: Topology for HDMI / DVI ................................................................................５５

Figure 11: 10/100/1000 Ethernet Insertion Loss Budget .................................................５９

Figure 12: Topology for Ethernet Jack ............................................................................６０

Figure 13: USB Insertion Loss Budget ............................................................................６６

Figure 14: USB 2.0 Good Downstream Power Connection ............................................６８

Figure 15: USB 2.0 A Common Mode Choke .................................................................６８

Figure 16: Topology for USB2.0 .....................................................................................７０

Figure 17: USB3.0 Insertion Loss Budget .......................................................................７５

Figure 18: Topology for USB3.0 .....................................................................................７６

Figure 19: SATA Insertion Loss Budge ...........................................................................７９

Figure 20: Topology for SATA ........................................................................................８１

Figure 21: Topology for LVDS ........................................................................................８７

Figure 22: Topology for eDP ...........................................................................................９０

Figure 23: Topology for VGA ..........................................................................................９４

Figure 24: Topology for Audio .........................................................................................９８

Figure 25: Topology for LPC ....................................................................................... １０１

Figure 26: Topology for SPI ........................................................................................ １０４

Figure 27: Topology for I2C ........................................................................................ １０７

Figure 28: Topology for SMB ...................................................................................... １１０

Figure 29: Topology for Serial interface ...................................................................... １１２

Figure 30: Topology for CAN interface ....................................................................... １１４

Figure 31: ATX Style Power Up Boot – Controlled by Power Button .......................... １２２

Figure 32: AT Style Power Up Boot ............................................................................ １２４

６

1. Introduction

1.1. About This Document

This design guide provides information for designing a custom system Carrier Board for COM Express

Type 6 Module. It includes Signal Descriptions, Routing Guidelines and Trace Length Guidelines. The main purpose is designing Carrier Board for helping customers fast and easy using the module of

Advantech to be designed.

1.2. Signal Table Terminology

Table 1 below describes the terminology used in this section for the Signal Description tables.

The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level.

The terms “Input” and “Output” and their abbreviations in Table 1 below refer to the Module's view, i.e. an input is an input for the Module and not for the Carrier-Board.

Table 1

: Signal Table Terminology Descriptions

Term

I/O 3.3V

I/O 5V

I 3.3V

I 5V

I/O 3V3_SBY

O 3.3V

O 5V

OD

P

*_S0

PCIE

USB

GbE

SATA

REF

PDS

Description

Bi-directional signal 3.3V tolerant

Bi-directional signal 5V tolerant

Input 3.3V tolerant

Input 5V tolerant

Bi-directional 3.3V tolerant active during Suspend and running state.

Output 3.3V signal level

Output 5V signal level

Open drain output

Power input/output

Signal active during running state.

In compliance with PCI Express Base Specification

In compliance with the Universal Serial Bus Specification

In compliance with IEEE 802.3ab 1000BASE-T Gigabit Ethernet

In compliance with Serial ATA specification

Reference voltage output. May be sourced from a Module power plane.

Pull-down strap. A Module output pin that is either tied to GND or is not connected. Used to signal Module capabilities (pin-out type) to the Carrier

Board.

７

1.3. Terminology

Table 2

: Conventions and Terminology

Terminology

AC ‘97 / HDA

ACPI

ADD2

ADD2/MEC

Basic Module

BIOS

CAN

Carrier Board

Compact Module

CRT

DAC

DDC

DDI

DNI

DP

DP

DVI

Description

Audio CODEC '97/High Definition Audio

Advanced Configuration Power Interface – standard to implement power saving modes in PCAT systems

Advanced Digital Display, 2nd Generation

Advanced Digital Display, 2nd Generation, Media Expansion Card

COM ExpressR 125mm x 95mm Module form factor.

Basic Input Output System – firmware in PC-AT system that is used to initialize system components before handing control over to the operating system.

Controller-area network (CAN or CAN-bus) is a vehicle bus standard designed to allow microcontrollers to communicate with each other within a vehicle without a host computer.

An application specific circuit board that accepts a COM ExpressR Module.

COM ExpressR 95mm x 95mm Module form factor

Cathode Ray Tube

Digital Analog Converter

Display Data Control – VESA (Video Electronics Standards Association) standard to allow identification of the capabilities of a VGA monitor

Digital Display Interface– containing DisplayPort, HDMI/DVI and SDVO

Do Not Install

DisplayPort is a digital display interface standard put forth by the Video

Electronics StandardsAssociation (VESA). It defines a new license free, royalty free, digital audio/videointerconnect, intended to be used primarily between a computer and its display monitor.

DisplayPort is a digital display interface standard put forth by the Video

Electronics StandardsAssociation (VESA). It defines a new license free, royalty free, digital audio/videointerconnect, intended to be used primarily between a computer and its display monitor.

Digital Visual Interface - a Digital Display Working Group (DDWG) standard that defines a standard video interface supporting both digital and analog video signals. The digital signals use TMDS.

８

Terminology

EAPI

EDID

EDP

Gb

GbE

GPI

GPIO

GPO

HDA

EEPROM

EFT

EMI

ESD

ExpressCard

Extended Module

FR4

HDMI

I2C

DE

Legacy Device

Description

Embedded Application Programming Interface

Software interface for COM ExpressR specific industrial functions

• System information

• Watchdog timer

• I2C Bus

• Flat Panel brightness control

• User storage area

• GPIO

Extended Display Identification Data

Embedded DisplayPort (eDP) is a digital display interface standard produced by the Video Electronics Standards Association (VESA) for digital interconnect of Audio and Video.

Electrically Erasable Programmable Read-Only Memory

Electrical Fast Transient

Electromagnetic Interference

Electrostatic Discharge

A PCMCIA standard built on the latest USB 2.0 and PCI Express buses.

COM ExpressR 155mm x 110mm Module form factor.

A type of fiber-glass laminate commonly used for printed circuit boards.

Gigabit

Gigabit Ethernet

General Purpose Input

General Purpose Input Output

General Purpose Output

Intel High Definition Audio (HD Audio) refers to the specification released by

Intel in 2004 for delivering high definition audio that is capable of playing back more channels at higher quality than AC97.

High Definition Multimedia Interface

Inter Integrated Circuit – 2 wire (clock and data) signaling scheme allowing communication between integrated circuits, primarily used to read and load register values.

Integrated Device Electronics – parallel interface for hard disk drives – also known as PATA

Relics from the PC-AT computer that are not in use in contemporary PC systems: primarily the ISA bus, UART-based serial ports, parallel printer ports, PS-2 keyboards, and mice.

Definitions vary as to what constitutes a legacy device. Some definitions include IDE as a legacy device.

９

Terminology

LAN

LPC

LS

LVDS

MEC

Mini Module

MS

NA

NC

OBD-II

OEM

PATA

PC-AT

PCB

PCI

PCI Express (PCIe)

PCI Express Lane

PD

PEG

PHY

Pin-out Type

PS2

PS2 Keyboard

PS2 Mouse

Description

Local Area Network

Low Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy-device support into a single IC.

Least Significant

Low-Voltage Differential Signaling – widely used as a physical interface for

TFT flat panels.

LVDS can be used for many high-speed signaling applications. In this document, it refers only to TFT flat-panel applications.

Media Expansion Card

COM ExpressR 84x55mm Module form factor

Most Significant

Not available

Not connected

On-Board Diagnostics 2nd generation

Original Equipment Manufacturer

Parallel AT Attachment – parallel interface standard for hard-disk drives – also known as IDE,AT Attachment, and as ATA

“Personal Computer – Advanced Technology” – an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s

Printed Circuit Board

Peripheral Component Interface

Peripheral Component Interface Express – next-generation high speed

Serialized I/O bus

One PCI Express Lane is a set of 4 signals that contains two differential lines for Transmitter and two differential lines for Receiver. Clocking information is embedded into the data stream.

Pull Down

PCI Express Graphics

Ethernet controller physical layer device

A reference to one of seven COM ExpressR definitions for the signals that appear on the COM ExpressR Module connector pins.

“Personal System 2” - an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s. The term survives as a reference to the style of mouse and keyboard interface that were introduced with the PS2 system.

１０

Terminology Description

PU

ROM

Pull Up

Read Only Memory – a legacy term – often the device referred to as a

ROM can actually be written to, in a special mode. Such writable ROMs are sometimes called Flash ROMs. BIOS is stored in ROM or Flash ROM.

RTC Real Time Clock – battery backed circuit in PC-AT systems that keeps system time and dateas well as certain system setup parameters

S0, S1, S2, S3, S4, S5 Sleep States defined by the ACPI specificationS0 Full power, all devices

SATA powered

S1Sleep State, all context maintained

S2 Sleep State, CPU and Cache context lost

S3 Suspend to RAM System context stored in RAM; RAM is in standby

S4 Suspend to Disk System context stored on disk

S5 Soft Off Main power rail off, only standby power rail present

Serial AT Attachment: serial-interface standard for hard disks

SDVO

SMBus

SO-DIMM

SPI

TBD

TMDS

TPM

UIM

USB

VESA

WDT

Serial Digital Video Out is a proprietary technology introduced by IntelR to add additional video signaling interfaces to a system. Being phased out

System Management Bus

Small Outline Dual In-line Memory Module

Serial Peripheral Interface

To be determined

Transition Minimized Differential Signaling - a digital signaling protocol between the graphics subsystem and display. TMDS is used for the DVI digital signals. DC coupled

Trusted Platform Module, chip to enhance the security features of a computer system.

User Identity Module

Universal Serial Bus

Video Electronics Standards Association

Watch Dog Timer

１１

1.4. Reference Documents

Document

COM Express Carrier Design Guide Rev. 2.0

Intel EDS Document

Intel Layout Guide Document

ATX12V Power Supply Design Guide Rev. 2.01

1.5. Revision History

Revision Date

0.90 April 14, 2017

1.00 Jun. 04, 2018

1.10

1.20

09 25, 2018

10 25, 2019

PCB Rev. Changes

A101-1

A101-1 1. Modify description of HDA_SDOUT.

A101-1 1.

Modify LPC Clock output to 24MHz.

A101-1 1. Modify PWR_BTN# description.

2. Modify power sequence request.

3. Add Input Power –Rise Time

１２

1.6. SOM-6898 Block Diagram

Figure 1

: SOM-6889 Block Diagram

１３

2. COM Express Type 6 Interfaces

2.1. COM Express Type 6 Connector Layout

Figure 2

: COM Express Type6 Connector Layout

１４

2.2. COM Express Type 6 Connector Pin-out

Table 3

: COM Express Type6 Pin-out

Connector Rows A and B

A28

A29

A30

A31

A32

A13

A14

A15

A16

A17

A8

A9

A10

A11

A12

Pin#

A1

A2

A3

A4

A5

A6

A7

A23

A24

A25

A26

A27

A18

A19

A20

A21

A22

Type 6 Description

GND

GBE0_MDI3-

GBE0_MDI3+

GBE0_LINK100#

GBE0_LINK1000#

GBE0_MDI2-

GBE0_MDI2+

GBE0_LINK#

GBE0_MDI1-

GBE0_MDI1+

GND

GBE0_MDI0-

GBE0_MDI0+

GBE0_CTREF

SUS_S3#

SATA0_TX+

SATA0_TX

SUS_S4#

SATA0_RX+

SATA0_RX

GND

SATA2_TX+

SATA2_TX

SUS_S5#

SATA2_RX+

SATA2_RX

BATLOW#

(S)ATA_ACT#

AC/HDA_SYNC

AC/HDA_RST#

GND

AC/HDA_BITCLK

B28

B29

B30

B31

B32

B13

B14

B15

B16

B17

B8

B9

B10

B11

B12

Pin#

B1

B2

B3

B4

B5

B6

B7

B23

B24

B25

B26

B27

B18

B19

B20

B21

B22

Type 6 Description

GND

GBE0_ACT#

LPC_FRAME#

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_DRQ0#

LPC_DRQ1#

LPC_CLK

GND

PWRBTN#

SMB_CK

SMB_DAT

SMB_ALERT#

SATA1_TX+

SATA1_TX

SUS_STAT#

SATA1_RX+

SATA1_RX-

GND

SATA3_TX+

SATA3_TX-

PWR_OK

SATA3_RX+

SATA3_RX-

WDT

AC/HDA_SDIN2

AC/HDA_SDIN1

AC/HDA_SDIN0

GND

SPKR

１５

Connector Rows A and B

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A37

A38

A39

A40

A41

Pin#

A33

A34

A35

A36

A59

A60

A61

A62

A63

A64

A65

A66

A67

A53

A54

A55

A56

A57

A58

PCIE_TX5-

GPI0

PCIE_TX4+

PCIE_TX4-

GND

PCIE_TX3+

PCIE_TX3-

GND

PCIE_TX2+

PCIE_TX2-

GPI1

PCIE_TX1+

PCIE_TX1-

GND

GPI2

Type 6 Description

AC/HDA_SDOUT

BIOS_DIS0#

THRMTRIP#

USB6-

USB6+

USB_6_7_OC#

USB4-

USB4+

GND

USB2-

USB2+

USB_2_3_OC#

USB0-

USB0+

VCC_RTC

EXCD0_PERST#

EXCD0_CPPE#

LPC_SERIRQ

GND

PCIE_TX5+

１６

PCIE_RX5-

GPO1

PCIE_RX4+

PCIE_RX4-

GPO2

PCIE_RX3+

PCIE_RX3-

GND

PCIE_RX2+

PCIE_RX2-

GPO3

PCIE_RX1+

PCIE_RX1-

WAKE0#

WAKE1#

Type 6 Description

I2C_CK

I2C_DAT

THRM#

USB7-

USB7+

USB_4_5_OC#

USB5-

USB5+

GND

USB3-

USB3+

USB_0_1_OC#

USB1-

USB1+

EXCD1_PERST#

EXCD1_CPPE#

SYS_RESET#

CB_RESET#

GND

PCIE_RX5+

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B37

B38

B39

B40

B41

Pin#

B33

B34

B35

B36

B59

B60

B61

B62

B63

B64

B65

B66

B67

B53

B54

B55

B56

B57

B58

Connector Rows A and B

A77

A78

A79

A80

A81

A82

A83

A84

A85

A86

A87

A72

A73

A74

A75

A76

Pin#

A68

A69

A70

A71

A94

A95

A96

A97

A98

A99

A100

A101

A102

A88

A89

A90

A91

A92

A93

Type 6 Description

PCIE_TX0+

PCIE_TX0-

GND

LVDS_A0+

LVDS_A0-

LVDS_A1+

LVDS_A1-

LVDS_A2+

LVDS_A2-

LVDS_VDD_EN

LVDS_A3+

LVDS_A3-

GND

LVDS_A_CK+

LVDS_A_CK-

LVDS_I2C_CK

LVDS_I2C_DAT

GPI3

RSVD eDP_HPD

PCIE_CLK_REF+

PCIE_CLK_REF-

GND

SPI_POWER

SPI_MISO

GPO0

SPI_CLK

SPI_MOSI

TPM_PP

TYPE10#

SER0_TX

SER0_RX

GND

SER1_TX

SER1_RX

BIOS_DIS1#

VGA_RED

GND

VGA_GRN

VGA_BLU

VGA_HSYNC

VGA_VSYNC

VGA_I2C_CK

VGA_I2C_DAT

SPI_CS#

RSVD

RSVD

GND

FAN_PWMOUT

FAN_TACHIN

Type 6 Description

PCIE_RX0+

PCIE_RX0-

GND

LVDS_B0+

LVDS_B0-

LVDS_B1+

LVDS_B1-

LVDS_B2+

LVDS_B2-

LVDS_B3+

LVDS_B3-

LVDS_BKLT_EN

GND

LVDS_B_CK+

LVDS_B_CK-

LVDS_BKLT_CTRL

VCC_5V_SBY

VCC_5V_SBY

VCC_5V_SBY

VCC_5V_SBY

B77

B78

B79

B80

B81

B82

B83

B84

B85

B86

B87

B72

B73

B74

B75

B76

Pin#

B68

B69

B70

B71

B94

B95

B96

B97

B98

B99

B100

B101

B102

B88

B89

B90

B91

B92

B93

１７

Connector Rows A and B

Pin#

A103

A104

A105

A106

A107

A108

A109

A110

Type 6 Description

LID#

VCC_12V

VCC_12V

VCC_12V

VCC_12V

VCC_12V

VCC_12V

GND

１８

Pin#

B103

B104

B105

B106

B107

B108

B109

B110

Type 6 Description

SLEEP#

VCC_12V

VCC_12V

VCC_12V

VCC_12V

VCC_12V

VCC_12V

GND

Connector Rows C and D

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C5

C6

C7

C8

C9

Pin#

C1

C2

C3

C4

C32

C33

C34

C35

C36

C27

C28

C29

C30

C31

C21

C22

C23

C24

C25

C26

Type 6 Description

GND

GND

USB_SSRX0-

USB_SSRX0+

GND

USB_SSRX1-

USB_SSRX1+

GND

USB_SSRX2-

USB_SSRX2+

GND

USB_SSRX3-

USB_SSRX3+

GND

DDI1_PAIR6+

DDI1_PAIR6-

RSVD

RSVD

PCIE_RX6+

PCIE_RX6-

GND

PCIE_RX7+

PCIE_RX7-

DDI1_HPD

DDI1_PAIR4 +

DDI1_PAIR4 -

RSVD

RSVD

DDI1_PAIR5+

DDI1_PAIR5-

GND

DDI2_CTRLCLK_AUX+

DDI2_CTRLCLK_AUX-

DDI2_DDC_AUX_SEL

RSVD

DDI3_CTRLCLK_AUX+

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D5

D6

D7

D8

D9

Pin#

D1

D2

D3

D4

D32

D33

D34

D35

D36

D27

D28

D29

D30

D31

D21

D22

D23

D24

D25

D26

１９

Type 6 Description

GND

GND

USB_SSTX0-

USB_SSTX0+

GND

USB_SSTX1-

USB_SSTX1+

GND

USB_SSTX2-

USB_SSTX2+

GND

USB_SSTX3-

USB_SSTX3+

GND

DDI1_CTRLCLK_AUX+

DDI1_CTRLCLK_AUX-

RSVD

RSVD

PCIE_TX6+

PCIE_TX6-

GND

PCIE_TX7+

PCIE_TX7-

RSVD

RSVD

DDI1_PAIR0+

DDI1_PAIR0-

RSVD

DDI1_PAIR1+

DDI1_PAIR1-

GND

DDI1_PAIR2+

DDI1_PAIR2-

DDI1_DDC_AUX_SEL

RSVD

DDI1_PAIR3+

Connector Rows C and D

C46

C47

C48

C49

C50

C51

C52

C53

C54

C55

C56

C41

C42

C43

C44

C45

Pin#

C37

C38

C39

C40

C63

C64

C65

C66

C67

C68

C69

C70

C71

C57

C58

C59

C60

C61

C62

TYPE1#

PEG_RX2+

PEG_RX2-

GND

PEG_RX3+

PEG_RX3-

RSVD

RSVD

PEG_RX4+

PEG_RX4-

RSVD

PEG_RX5+

PEG_RX5-

GND

PEG_RX6+

Type 6 Description

DDI3_CTRLCLK_AUX-

DDI3_DDC_AUX_SEL

DDI3_PAIR0+

DDI3_PAIR0-

GND

DDI3_PAIR1+

DDI3_PAIR1-

DDI3_HPD

RSVD

DDI3_PAIR2+

DDI3_PAIR2-

RSVD

DDI3_PAIR3+

DDI3_PAIR3-

GND

PEG_RX0+

PEG_RX0-

TYPE0#

PEG_RX1+

PEG_RX1-

２０

TYPE2#

PEG_TX2+

PEG_TX2-

GND

PEG_TX3+

PEG_TX3-

RSVD

RSVD

PEG_TX4+

PEG_TX4-

GND

PEG_TX5+

PEG_TX5-

GND

PEG_TX6+

Type 6 Description

DDI1_PAIR3-

RSVD

DDI2_PAIR0+

DDI2_PAIR0-

GND

DDI2_PAIR1+

DDI2_PAIR1-

DDI2_HPD

RSVD

DDI2_PAIR2+

DDI2_PAIR2-

RSVD

DDI2_PAIR3+

DDI2_PAIR3-

GND

PEG_TX0+

PEG_TX0-

PEG_LANE_RV#

PEG_TX1+

PEG_TX1-

D46

D47

D48

D49

D50

D51

D52

D53

D54

D55

D56

D41

D42

D43

D44

D45

Pin#

D37

D38

D39

D40

D63

D64

D65

D66

D67

D68

D69

D70

D71

D57

D58

D59

D60

D61

D62

Connector Rows C and D

C81

C82

C83

C84

C85

C86

C87

C88

C89

C90

C91

C76

C77

C78

C79

C80

Pin#

C72

C73

C74

C75

C98

C99

C100

C101

C102

C103

C104

C105

C106

C92

C93

C94

C95

C96

C97

PEG_RX12-

GND

PEG_RX13+

PEG_RX13-

GND

RSVD

PEG_RX14+

PEG_RX14-

GND

PEG_RX15+

PEG_RX15-

GND

VCC_12V

VCC_12V

VCC_12V

Type 6 Description

PEG_RX6-

GND

PEG_RX7+

PEG_RX7-

GND

RSVD

PEG_RX8+

PEG_RX8-

GND

PEG_RX9+

PEG_RX9-

RSVD

GND

PEG_RX10+

PEG_RX10-

GND

PEG_RX11+

PEG_RX11-

GND

PEG_RX12+

PEG_TX12-

GND

PEG_TX13+

PEG_TX13-

GND

RSVD

PEG_TX14+

PEG_TX14-

GND

PEG_TX15+

PEG_TX15-

GND

VCC_12V

VCC_12V

VCC_12V

Type 6 Description

PEG_TX6-

GND

PEG_TX7+

PEG_TX7-

GND

RSVD

PEG_TX8+

PEG_TX8-

GND

PEG_TX9+

PEG_TX9-

RSVD

GND

PEG_TX10+

PEG_TX10-

GND

PEG_TX11+

PEG_TX11-

GND

PEG_TX12+

D81

D82

D83

D84

D85

D86

D87

D88

D89

D90

D91

D76

D77

D78

D79

D80

Pin#

D72

D73

D74

D75

D98

D99

D100

D101

D102

D103

D104

D105

D106

D92

D93

D94

D95

D96

D97

２１

Connector Rows C and D

Pin#

C107

C108

C109

C110

Type 6 Description

VCC_12V

VCC_12V

VCC_12V

GND

２２

Pin#

D107

D108

D109

D110

Type 6 Description

VCC_12V

VCC_12V

VCC_12V

GND

2.3. PCI Express

2.3.1. COM Express A-B Connector and C-D Connector PCIe Groups

COM Express Type 6 Modules have two groups of PCIe lanes. There is a group of up to eight lanes; six are located on COM Express A-B connector and two on C-D connector that are intended for general purpose use, such as interfacing the COM Express Module to Carrier Board PCIe peripherals. A second group of PCIe lanes is defined on the COM Express C-D connector.

This group is intended primarily for the PCIe Graphics interfaces (also referred to as the PEG interface), and is typically 16 PCIe lanes wide. For some Modules, the PEG lanes may be used for general purpose PCIe lanes if the external graphics interface is not in use. This usage is Module and

Module chipset dependent.

2.3.2. General Purpose PCIe Signal Definitions

The general purpose PCI Express interface of the COM Express Type 6 Module on the COM Express

A-B connector consists of up to 6 lanes plus 2 lanes on connector C-D, each with a receive and transmit differential signal pair designated from PCIE_RX0 (+ and -) to PCIE_RX7 (+ and -) and correspondingly from PCIE_TX0 (+ and -) to PCIE_TX7 (+ and -). The 8 lanes may be grouped into various link widths as defined in the COM Express spec.

Table 4

: General Purpose PCI Express Signal Descriptions

Signal

PCIE_RX0+

PCIE_RX0-

PCIE_TX0+

PCIE_TX0-

Pin# Description

B68 PCIe channel 0. Receive Input differential pair.

B69 Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE0 x1 device PETp/n0.

Slot - Connect to PCIE0 x1 Conn pin A16, A17

A68

A69

PERp/n0.

N/C if not used.

PCIe channel 0. Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE0 x1 device PERp/n0.

Slot - Connect to PCIE0 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

I/O

I PCIE

O PCIE

Note

２３

Signal

PCIE_RX1+

PCIE_RX1-

PCIE_TX1+

PCIE_TX1-

PCIE_RX2+

PCIE_RX2-

PCIE_TX2+

PCIE_TX2-

PCIE_RX3+

PCIE_RX3-

Pin# Description

B64 PCIe channel 1. Receive Input differential pair.

B65 Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near to

PCIE1 x1 device PETp/n0.

A64

A65

Slot - Connect to PCIE1 x1 Conn pin A16, A17

PERp/n0.

N/C if not used.

PCIe channel 1. Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE1 x1 device PERp/n0.

B61

B62

A61

A62

Slot - Connect to PCIE1 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

PCIe channel 2. Receive Input differential pair.

Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE2 x1 device PETp/n0.

Slot - Connect to PCIE2 x1 Conn pin A16, A17

PERp/n0.

N/C if not used.

PCIe channel 2. Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE2 x1 device PERp/n0.

Slot - Connect to PCIE2 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

B58

B59

PCIe channel 3. Receive Input differential pair.

Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near to

PCIE3 x1 device PETp/n0.

Slot - Connect to PCIE3 x1 Conn pin A16, A17

PERp/n0.

N/C if not used.

I/O

I PCIE

O PCIE

I PCIE

O PCIE

I PCIE

Note

２４

Signal

PCIE_TX3+

PCIE_TX3-

PCIE_RX4+

PCIE_RX4-

PCIE_TX4+

PCIE_TX4-

PCIE_RX5+

PCIE_RX5-

PCIE_TX5+

PCIE_TX5-

Pin# Description

A58 PCIe channel 3. Transmit Output differential pair.

A59 Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE3 x1 device PERp/n0.

B55

B56

Slot - Connect to PCIE3 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

PCIe channel 4. Receive Input differential pair.

Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near to

PCIE4 x1 device PETp/n0.

A55

A56

B52

B53

Slot - Connect to PCIE4 x1 Conn pin A16, A17

PERp/n0.

N/C if not used.

PCIe channel 4. Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE4 x1 device PERp/n0.

Slot - Connect to PCIE4 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

PCIe channel 5. Receive Input differential pair.

Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near to

PCIE5 x1 device PETp/n0.

Slot - Connect to PCIE5 x1 Conn pin A16, A17

PERp/n0.

N/C if not used.

A52

A53

PCIe channel 5. Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE5 x1 device PERp/n0.

Slot - Connect to PCIE5 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

I/O

O PCIE

Note

I PCIE

O PCIE

I PCIE

O PCIE

２５

Signal

PCIE_RX6+

PCIE_RX6-

PCIE_TX6+

PCIE_TX6-

PCIE_RX7+

PCIE_RX7-

PCIE_TX7+

PCIE_TX7-

PCIE_CLK_REF+

PCIE_CLK_REF-

Pin# Description

C19 PCIe channel 6. Receive Input differential pair.

C20 Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near to

PCIE5 x1 device PETp/n0.

D19

D20

Slot - Connect to PCIE5 x1 Conn pin A16, A17

PERp/n0.

N/C if not used.

PCIe channel 6. Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE6 x1 device PERp/n0.

C22

C23

D22

D23

Slot - Connect to PCIE6 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

PCIe channel 7. Receive Input differential pair.

Carrier Board:

Device - Connect AC Coupling cap 0.22uF

near to

PCIE6 x1 device PETp/n0.

Slot - Connect to PCIE6 x1 Conn pin A16, A17

PERp/n0.

N/C if not used.

PCIe channel 7. Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Carrier Board:

Device - Connect to PCIE7 x1 device PERp/n0.

Slot - Connect to PCIE7 x1 Conn pin B14, B15

PETp/n0.

N/C if not used.

A88

A89

PCIe Reference Clock for all COM Express PCIe lanes, and for PEG lanes.

Carrier Board:

Connect 0Ω in series to

Device - PCIE device REFCLK+, REFCLK-.

Slot - PCIE Conn pin A13 REFCLK+, A14 REFCLK-.

*Connect to PCIE Clock Buffer input to provide

PCIE clocks output for more than one PCIE devices or slots.

N/C if not used.

I/O

I PCIE

O PCIE

I PCIE

O PCIE

O PCIE

Note

２６

Signal

EXCD0_CPPE#

EXCD0_PERST#

EXCD1_CPPE#

EXCD1_PERST#

CB_RESET#

Pin# Description

A49 PCI ExpressCard0: PCI Express capable card request, active low, one per card.

Module has integrated PU resistor to 3.3V

Express Card's CPPE# connects to Power Switch

CPPE# input pin

N/C if not used.

A48 PCI ExpressCard0: reset, active low, one per card

Express Card's PERST# and Express Card's

PERST# connects to Power Switch PERST# output pin.

N/C if not used.

B48 PCI ExpressCard1: PCI Express capable card request, active low, one per card.

Module has integrated PU resistor to 3.3V

Express Card's CPPE# connects to Power Switch

CPPE# input pin

N/C if not used.

B47 PCI ExpressCard1: reset, active low, one per card

Express Card's PERST# connects to Power Switch

PERST# output pin.

N/C if not used

B50 Reset output from Module to Carrier Board. Active low.

Issued by Module chipset and may result from a low

SYS_RESET# input, a low PWR_OK input, a

VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the Module software.

Module has integrated 3.3V buffer and series resistor.

Connect to reset pin of devices except PCI slots or devices.

N/C if not used.

I/O

I 3.3V

CMOS

O 3.3V

CMOS

I 3.3V

CMOS

O 3.3V

CMOS

O 3.3V

Suspend

CMOS

Note

２７

Signal

WAKE0#

Pin# Description

B66 PCI Express wake up event signal.

Module has integrated PU resistor to 3.3VDUAL

Device - Connect to WAKE# pin of PCIE device.

Slot - Connect to WAKE# pin B11 of PCIE slot.

Express Card - Connect to WAKE# pin 11 of

Express Card socket.

N/C if not used.

Notes:

2.3.3. PCI Express Lane Configurations – Per COM Express Spec

I/O

I 3.3V

Suspend

CMOS

Note

According to the COM Express specification, the general purpose PCIe lanes on the A-B connector can be configured as up to eight PCI Express x1 links or may be combined into various combinations of x8, x4, x2 and x1 links that add up to a total of 8 lanes. These configuration possibilities are based on the

COM Express Module's chip-set capabilities.

The COM Express specification defines a "fill order" from mapping PCIe links that are wider than x1 onto the COM Express pins. For example, the spec requires that a x4 PCI Express link be mapped to COM

Express PCI Express lanes 0,1,2 and 3. Refer to the COM Express specification for details.

Note: All PCI Express devices are required to work in x1 mode as well as at their full capability. A x4

PCIe card for example is required by the PCI Express specification to be usable in x4 and / or x1 mode.

２８

2.3.4. PCI Express* General Routing Guidelines

2.3.4.1. PCI Express Insertion Loss Budget with Slot Card

PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board Slot Card

The module transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the module transmit path. The module transmit path insertion loss budget shall be 4.65 dB (3.46 dB + 1.19 dB). The module receive path insertion loss budget shall be 3.46 dB. COM ExpressTM connector loss is accounted for separately.

The Carrier Board transmit and receive insertion loss budgets are the same in this case. The Carrier

Board insertion loss budget shall be 4.40 dB. COM ExpressTM connector and slot card connector losses are accounted for separately.

The slot card transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the slot card’s transmit path. The slot card’s transmit path insertion loss budget is 3.84 dB (2.65 dB + 1.19 dB) per the PCI Express Card Electromechanical Specification Revision 1.1. The slot card’s receive path insertion loss budget is 2.65 dB per the same specification. Slot card connector loss is accounted for separately.

２９

Notes

Segment

Loss (dB) max. Length

[mm/inches]

L

A

3.46

130/5.15

1.19 Coupling

Caps

L

B

L

C

L

D

0.25

4.4

228/9.0

1.25

Allowance for 5.15 inches of module trace 3.45 dB loss @ 0.28 dB / GHz

/ inch and 1.66 dB crosstalk allowance. Coupling caps not included.

1.19 dB loss.

From PCI Express Card Electromechanical Spec., Rev.

1.1, parameters (L

ST

– L

SR

). Includes crosstalk allowance of 0.79 dB.

COM Express

TM

connector at 1.25 GHz measured value: 0.25 dB loss.

Allowance for 9 inches of Carrier Board trace 4.40 db loss @ 0.28 dB /

GHz / inch and a 1.25 dB crosstalk allowance.

1.25 dB loss.

PCI Express Card Electromechanical Spec Rev 1.1 “guard band” allowance for slot connector – includes 1.0 dB connector loss.

L

E

2.65 2.65 dB loss.

From PCI Express Card Electromechanical Spec., Rev.

1.1(without coupling caps; L

AR

). Implied crosstalk allowance is 1.25 dB.

Total 13.20 13.20 dB loss.

PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board Slot Card

For “device up” PCIe Gen 2 operation, the Module PCIe maximum trace length is restricted to 5.0 inches and the Carrier Board maximum trace to 4.45 inches. Shorter lengths will yield additional margin and are encouraged where possible. Results assumed FR4 dielectrics.

Other dielectrics with lower losses could be considered, but were not simulated.

It should be noted that a use case exists that might result in reduced PCI Express bandwidth. This use case is tied to Carrier boards with a PCI Express slot (device up). PCI Express Gen 1 and Gen 2 signaling rates use the same PCI Express connector – there is no mechanical keying mechanism to identify the capabilities of the PCI Express slot or the PCI Express board plugged into the slot. This can lead to the situation where the Module and PCI Express board attempt a PCI Express Gen2 signaling rate connection over a Carrier that does not meet the routing guidelines for Gen 2 signaling rates. In a worst case scenario the devices might connect at Gen2 signaling rate with a high number of errors impacting the actual data throughput. It should be noted that there is a Carrier EEPROM on the Carrier which would allow the Module to determine the Carrier board capabilities but this is not a requirement in

COM.0.

３０

Notes

Segment max. Length

[mm/inches]

L

A

L

B

L

C

L

D

L

E

127/5.0

113/4.45

Allowance for module trace. Coupling cap effects included within simulation.

COM Express™ connector simulated at 2.5 GHz.

Allowance for Carrier Board.

PCI Express Card slot connector simulated at 2.5 GHz.

80/3.15 Slot Card trace length from PCI Express Card Electromagnetical Spec.,

Rev. 1.1

Total 320/12.6 PCIe GEN2 Data clocked architecture

2.3.4.2. PCI Express Insertion Loss Budget with Carrier Board PCIE Device

PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board PCIE Device

The module transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the module transmit path. The module transmit path insertion loss budget shall be 4.65 dB (3.46 dB + 1.19 dB). The module receive path insertion loss budget shall be 3.46 dB. COM ExpressTM connector loss is accounted for separately.

The Carrier Board transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the Carrier Board transmit path. The Carrier Board transmit path insertion loss budget shall be 9.49 dB (8.30 dB + 1.19 dB). The Carrier Board receive path insertion loss shall be 8.30 dB.

COM ExpressTM connector loss is accounted for separately.

３１

Notes

Segment

Loss (dB) max. Length

[mm/inches]

L

A

Coupling

Caps

L

B

L

C

3.46

131/5.15

1.19

0.25

8.3

113/4.45

Allowance for 5.15 inches of module trace 3.46 dB loss @ 0.28 dB / GHz / inch and 1.66 dB crosstalk allowance. Coupling caps not included.

1.19 dB loss. From PCI Express Card Electromechanical Spec., Rev. 1.1, parameters (LST – LSR). Includes crosstalk allowance of 0.79 dB.

COM Express

TM

connector at 1.25 GHz measured value: 0.25 dB loss.

Allowance for 15.85 inches of Carrier Board trace 8.30 dB loss @ 0.28 dB /

GHz / inch and a 2.75 dB crosstalk allowance.

Total

Total 13.2 13.2dB loss

PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board PCIE Device

For “device down” PCIe Gen 2 operation, the Module PCIe maximum trace length is restricted to 5.0 inches and the Carrier Board maximum trace to 8.0 inches. Shorter lengths will yield additional margin and are encouraged where possible. Results assumed FR4 dielectrics. Other dielectrics with lower losses could be considered, but were not simulated.

Segment max. Length

[mm/inches]

Notes

L

A

L

B

L

C

127/5

203/8

Allowance for module trace. Coupling cap effects included within simulation.

COM Express™ connector simulated at 2.5 GHz.

Allowance for Carrier Board trace.

330/13.0 PCIe GEN2 Data clocked architecture

３２

2.3.5. PCI Express* Trace Length Guidelines

Figure 3

: Topology for PCI Express Slot Card.

Figure 4

: Topology for PCI Express Device Down.

３３

Table 5

: PCI Express* Slot Card / Device Down Trace Length Guidelines

Parameter

Signal Group

Main Route Guidelines

PCI Express* expansion

Differential Impedance Target 85Ω±10%

Single End 50Ω±10%

Isolation to equivalent pairs 20 mils (MS) and 15 mils (DS)

Isolation to other signal groups 20 mils (MS) and 15 mils (DS)

Tx/Rx Spacing 20 mils

LA + LB

Lc

Max length of LA+LB+LC

Please see the

Carrier Board Length

Slot Card:

SOM-6898 Layout Checklist

8” (Gen3.0)

Device Down: 9” (Gen3.0)

Length matching Differential pairs (intra-pair): Max.

±5 mils

REFCLK+ and REFCLK- (intra-pair):Max. ±5 mils

Reference Plane GND referencing preferred

Min 40-mil trace edge-to-major plane edge spacing

GND stitching vias required next to signal vias if transitioning layers between GND layers

Power referencing acceptable if stitching caps are used

Max. 2 vias per TX trace, Max. 4 vias per RX trace Carrier Board Via Usage

AC coupling The AC coupling capacitors for the TX lines are incorporated on the COM Express Module. The AC coupling capacitors for RX signal lines have to be implemented on the customer COM Express Carrier

Board. Capacitor type: X7R, 100nF ±10%, 16V, shape

0402.

1

Notes:

1.

AC caps are recommended to be placed close to PCIe device side (avoid placing AC cpas on mid-bus).

Notes

３４

2.4 PEG (PCI Express Graphics) *SOM-6898 is not support PEG.

2.4.1 PEG Signal Definitions

The PEG Port can utilize COM Express PCIe lanes 16-31 and is suitable to drive a link for an external high-performance PCI Express Graphics card, if implemented on the COM Express Module.

Graphics Cards implemented as x16 use COM Express PCIe lanes 16-31; Graphics Cards implemented as x8 lanes should use COM Express PCIe lanes 16-23. Each lane of the PEG Port consists of a receive and transmit differential signal pair designated 'PEG_RX0' (+ and -) to 'PEG_RX15' (+ and -) and correspondingly from 'PEG_TX0' (+ and -) to 'PEG_TX15' (+ and -). The corresponding signals can be found on the Module connector rows C and D.

Table 6

: PEG Signal Description

Signal

PEG_RX0+

PEG_RX0-

PEG_TX0+

PEG_TX0-

PEG_RX1+

PEG_RX1-

PEG_TX1+

PEG_TX1-

Pin# Description

C52

C53

D52

D53

C55

C56

D55

D56

PEG channel 0, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n0.

Slot - Connect to PCIE x16 Conn pin A16, A17

PERp/n0.

N/C if not used.

PEG channel 0, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n0.

Slot - Connect to PCIE x16 Conn pin B14, B15

PETp/n0.

N/C if not used.

PEG channel 1, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n1.

Slot - Connect to PCIE x16 Conn pin A21, A22

PERp/n1.

N/C if not used

PEG channel 1, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n1.

Slot - Connect to PCIE x16 Conn pin B14, B15

PETp/n1.

N/C if not used.

I/O Notes

I PCIE 1

O PCIE

1

I PCIE

1

O PCIE

1

３５

Signal

PEG_RX2+

PEG_RX2-

PEG_TX2+

PEG_TX2-

PEG_RX3+

PEG_RX3-

PEG_TX3+

PEG_TX3-

PEG_RX4+

PEG_RX4-

PEG_TX4+

PEG_TX4-

Pin# Description

C58

C59

PEG channel 2, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n2.

Slot - Connect to PCIE x16 Conn pin A25, A26

PERp/n2.

D58

D59

N/C if not used

PEG channel 2, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n2.

Slot - Connect to PCIE x16 Conn pin B23, B24

PETp/n2.

N/C if not used.

C61

C62

D61

D62

C65

C66

D65

D66

PEG channel 3, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp3.

Slot - Connect to PCIE x16 Conn pin A29, A30

PERp3.

N/C if not used

PEG channel 3, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n3.

Slot - Connect to PCIE x16 Conn pin B27, B28

PETp/n3.

N/C if not used.

PEG channel 4, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n4.

Slot - Connect to PCIE x16 Conn pin A35, A36

PERp/n4.

N/C if not used

PEG channel 4, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n4.

Slot - Connect to PCIE x16 Conn pin B33, B34

PETp/n4.

N/C if not used.

I/O

I PCIE

Notes

1

O PCIE

1

I PCIE

O PCIE

I PCIE

O PCIE

1

1

1

1

３６

Signal

PEG_RX5+

PEG_RX5-

PEG_TX5+

PEG_TX5-

PEG_RX6+

PEG_RX6-

PEG_TX6+

PEG_TX6-

PEG_RX7+

PEG_RX7-

PEG_TX7+

PEG_TX7-

Pin# Description

C68 PEG channel 5, Receive Input differential pair.

C69 Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n5.

Slot - Connect to PCIE x16 Conn pin A39, A40

D68

D69

PERp/n5.

N/C if not used

PEG channel 5, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n5.

Slot - Connect to PCIE x16 Conn pin B37, B38

PETp/n5.

N/C if not used.

C71

C72

D71

D72

C74

C75

PEG channel 6, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n6.

Slot - Connect to PCIE x16 Conn pin A43, A44

PERp/n6.

N/C if not used

PEG channel 6, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n6.

Slot - Connect to PCIE x16 Conn pin B37, B38

PETp/n6.

N/C if not used

PEG channel 7, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n7.

Slot - Connect to PCIE x16 Conn pin A47, A48

D74

D75

PERp/n7.

N/C if not used

PEG channel 7, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n7.

Slot - Connect to PCIE x16 Conn pin B45, B46

PETp/n7.

N/C if not used

I/O

I PCIE

Notes

1

O PCIE

1

I PCIE

O PCIE

I PCIE

O PCIE

1

1

1

1

３７

Signal

PEG_RX8+

PEG_RX8-

PEG_TX8+

PEG_TX8-

PEG_RX9+

PEG_RX9-

PEG_TX9+

PEG_TX9-

PEG_RX10+

PEG_RX10-

PEG_TX10+

PEG_TX10-

Pin# Description

C78 PEG channel 8, Receive Input differential pair.

C79 Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n8.

Slot - Connect to PCIE x16 Conn pin A52, A53

D78

D79

PERp/n8.

N/C if not used

PEG channel 8, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n8.

Slot - Connect to PCIE x16 Conn pin B50, B51

PETp/n8.

N/C if not used

C81

C82

D81

D82

C85

C86

PEG channel 9, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n9.

Slot - Connect to PCIE x16 Conn pin A56, A57

PERp/n9.

N/C if not used

PEG channel 9, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n9.

Slot - Connect to PCIE x16 Conn pin B54, B55

PETp/n9.

N/C if not used

PEG channel 10, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n10.

Slot - Connect to PCIE x16 Conn pin A60, A61

D85

D86

PERp/n10.

N/C if not used

PEG channel 10, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n10.

Slot - Connect to PCIE x16 Conn pin B58, B59

PETp/n10.

N/C if not used

O PCIE

1

I PCIE

O PCIE

I PCIE

O PCIE

1

1

1

1

I/O

I PCIE

Notes

1

３８

Signal

PEG_RX11+

PEG_RX11-

PEG_TX11+

PEG_TX11-

PEG_RX12+

PEG_RX12-

PEG_TX12+

PEG_TX12-

PEG_RX13+

PEG_RX13-

PEG_TX13+

PEG_TX13-

Pin# Description

C88 PEG channel 11, Receive Input differential pair.

C89 Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n11.

Slot - Connect to PCIE x16 Conn pin A64, A65

D88

D89

PERp/n11.

N/C if not used

PEG channel 11, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n11.

Slot - Connect to PCIE x16 Conn pin B62, B63

PETp/n11.

N/C if not used

C91

C92

D91

D92

C94

C95

PEG channel 12, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n12.

Slot - Connect to PCIE x16 Conn pin A68, A69

PERp/n12.

N/C if not used

PEG channel 12, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n12.

Slot - Connect to PCIE x16 Conn pin B66, B67

PETp/n12.

N/C if not used

PEG channel 13, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n13.

Slot - Connect to PCIE x16 Conn pin A72, A73

D94

D95

PERp/n13.

N/C if not used

PEG channel 13, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n13.

Slot - Connect to PCIE x16 Conn pin B70, B71

PETp/n13.

N/C if not used

I/O

I PCIE

O PCIE

I PCIE

I PCIE

1

1

1

Note

1

O PCIE

1

O PCIE

1

３９

Signal

PEG_RX14+

PEG_RX14-

PEG_TX14+

PEG_TX14-

Pin# Description

C98 PEG channel 14, Receive Input differential pair.

C99 Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n14.

Slot - Connect to PCIE x16 Conn pin A76, A77

D98

D99

PERp/n14.

N/C if not used

PEG channel 14, Transmit Output differential pair.

Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n14.

Slot - Connect to PCIE x16 Conn pin B74, B75

PETp/n14.

N/C if not used

PEG_RX15+

PEG_RX15-

C101

C102

PEG channel 15, Receive Input differential pair.

Device - Connect AC Coupling cap 0.22uF

near

COME to PCIE x16 device PETp/n15.

Slot - Connect to PCIE x16 Conn pin A80, A81

PERp/n15.

N/C if not used

PEG channel 15, Transmit Output differential pair. PEG_TX15+

PEG_TX15-

D101

D102 Module has integrated AC Coupling Capacitor.

Device - Connect to PCIE x16 device PERp/n15.

Slot - Connect to PCIE x16 Conn pin B78, B79

PETp/n15.

N/C if not used

PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane order.

Module has integrated PU resistor to 3.3V.

Carrier Board:

Normal - N/C

Reverse - PD 1KΩ to GND

N/C if not used.

Notes:

1.

SON-6898 is not support PEG.

I/O

I PCIE

O PCIE

I PCIE

O PCIE

I 3.3V

CMOS

1

1

1

1

Note

1

４０

2.4.2. PEG* General Routing Guidelines

PEG Configuration

The COM Express PCIe Graphics (PEG) Port is comprised of COM Express PCIe lanes 16-31.

The primary use of this set of signals is to interface to off-Module graphics controllers or cards.

If the PEG interface is not used for an external graphics card SDVO, it may be possible to use these

PCIe lanes for other Carrier Board PCIe devices. The details of this usage are Module and Module chip-set dependent. Operation in a x1 link is also supported. Wider links (x2, x4, x8, x16) are chip-set dependent. Refer to the Module product documentation for details.

The COM Express specification defines a fill order for this set of PCIe lanes. Larger link widths go to the lower lanes. Refer to the COM Express specification for details.

Using PEG Pins for General Purpose PCIe Lanes

The COM Express PEG lanes may be used for general-purpose use if the PEG port is not being used as an interface to an external graphics device. The characteristics of this usage are Module and chip-set dependent.

Modules that employ desktop and mobile chip-sets with PEG capability can usually be set up to allow the

COM Express PEG lanes to be configured as a single general purpose PCIe link, with link width possibilities of x1, x4, x8 or x16. The x1 configuration should always work; the wider links may be

Module and chip-set dependent. Check with your vendor.

Modules based on server-class chip-sets may allow multiple links over the PEG lanes – for example, a x8 link on COM Express PCIe lanes 16 through 23 and a x4 link over lanes 24 through 27. This is

Module and chip-set dependent.

４１

2.4.3. PEG* Trace Length Guidelines

Figure 5

: Topology for PCI Express Slot Card.

Figure 6

: Topology for PCI Express Device Down.

４２

Table 7

: PCI Express* Slot Card / Device Down Trace Length Guidelines

Parameter

Signal Group

Main Route Guidelines

PCI Express* expansion

Differential Impedance Target NA

Single End

Isolation to equivalent pairs

NA

20 mils (MS) and 15 mils (DS)

Isolation to other signal groups 20 mils (MS) and 15 mils (DS)

Tx/Rx Spacing 20 mils

LA + LB NA

Lc

Max length of LA+LB+LC

Length matching

Reference Plane

Carrier Board Via Usage

Carrier Board Length

Slot Card: NA

Device Down: NA

Differential pairs (intra-pair): Max.

NA

REFCLK+ and REFCLK- (intra-pair):Max. NA

GND referencing preferred

Min 40-mil trace edge-to-major plane edge spacing

GND stitching vias required next to signal vias if transitioning layers between GND layers

Power referencing acceptable if stitching caps are used

Max. 2 vias per TX trace, Max. 4 vias per RX trace

2

2

AC coupling The AC coupling capacitors for the TX lines are incorporated on the COM Express Module. The AC coupling capacitors for RX signal lines have to be implemented on the customer COM Express Carrier

Board. Capacitor type: X7R, 100nF ±10%, 16V, shape

0402.

1

Notes:

1.

AC caps are recommended to be placed close to PCIe device side (avoid placing AC cpas on mid-bus).

2.

SOM-6898 is not support PEG.

2

2

2

2

2

2

Notes

2

2

４３

2.5 Digital Display Interfaces (DDI)

Module Types 6 use Digital Display Interfaces (DDI) to provide DisplayPort, HDMI/DVI, and SDVO interfaces. Type 6 Modules can contain up to 3 DDIs (DDI[1:3]) of which DDI[1:3] can support

DisplayPort, HDMI/DVI and DDI[1] can support DisplayPort, HDMI/DVI, and SDVO.

The main difference is that SDVO is only supported DDI[1] for Type 6 Modules.

DisplayPort / HDMI / DVI

DisplayPort was developed by the Video Electronics Standard Association (VESA) in order to create a new digital display port interface to connect a video source to a display device.

DisplayPort can be used to transfer audio and video at the same time, but each one is optional and can be transmitted without the other. A bi-directional, half-duplex auxiliary channel carries device anagement and device control data for the Main Link, such as VESA EDID.

DisplayPort is nowadays on almost all COM Express Modules available as Dual-mode DisplayPort, that can directly emit single-link HDMI and DVI signals using an adapter, which contains a level shifter to adjust for the lower voltages required by DisplayPort. These adapters can be directly implemented on the Carrier Board to have an easy, simple and future proof implementation of HDMI and/or DVI or an inexpensive cable adapter can be directly connectedon the Carrier Board's DisplayPort connector.

2.5.1. DDI Signal Definitions

Type 6 Modules up to 3 DisplayPort interfaces.

Each DisplayPort interface consists of 4 differential lanes, 1 auxiliary lane and 1 hot-plug-detect signal.

The DDC_AUX_SEL pin should be routed to pin 13 of the DisplayPort connector, to enable Dual-Mode.

When HDMI/DVI is directly done on the Carrier Board, this pin shall be pulled to 3.3V with a 100k Ohm resistor to configure the AUX pairs as DDC channels.

Table 8

: Port / HDMI / DVI Pin-out of Type 6

Pin Name

DDIX_PAIR0+

DDIX_PAIR0-

DDIX_PAIR1+

DDIX_PAIR1-

DDIX_PAIR2+

DDIX_PAIR2-

DDIX_PAIR3+

DDIX_PAIR3-

DDIX_HPD

DDIX_CTRLCLK_AUX+

DDI1

Pin#

D26

D27

D29

D30

D32

D33

D36

D37

C24

D15

DDI2

Pin#

DDI3

Pin#

D39 C39

D40 C40

D42 C42

D43 C43

D46 C46

D47 C47

D49 C49

D50 C50

D44 C44

C32 C36

Function (DDIX)

DisplayPort

DPX_LANE0+

DPX_LANE0-

DPX_LANE1+

DPX_LANE1-

DPX_LANE2+

DPX_LANE2-

DPX_LANE3+

DPX_LANE3-

DPX_HPD

DPX_AUX+

Function (DDIX)

HDMI / DVI

TMDSX_DATA2+

TMDSX_DATA2-

TMDSX_DATA1+

TMDSX_DATA1-

TMDSX_DATA0+

TMDSX_DATA0-

TMDSX_CLK+

TMDSX_CLK-

HDMIX_HPD

HDMIX_CTRLCLK

４４

DDIX_CTRLCLK_AUX- D16 C33 C37 DPX_AUX-

DDIX_DDC_AUX_SEL D34 C34 C38

Note: Please verify in the Module's specification if DisplayPort or Dual-Mode

DisplayPort is supported.

HDMIX_CTRLDATA

Table 9

: DDI1 Signal Description

Signal

DDI1_PAIR0+

DDI1_PAIR0-

DDI1_PAIR1+

DDI1_PAIR1-

DDI1_PAIR2+

DDI1_PAIR2-

DDI1_PAIR3+

DDI1_PAIR3-

Pin# Description

D26

D27

D29

D30

D32

D33

D36

D37

DDI channel 1, differential pairs 0.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

DDI channel 1, differential pairs 1.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

DDI channel 1, differential pairs 2.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

DDI channel 1, differential pairs 3.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

I/O

O PCIE

O PCIE

O PCIE

O PCIE

Notes

４５

Signal

DDI1_HPD

DDI1_CTRLCLK_AUX+

DDI1_CTRLCLK_AUX-

DDI1_DDC_AUX_SEL

Pin# Description

C24 DDI channel 1, Hot-Plug Detect.

Module has integrated current blocking circuit and PD resistor to GND

Carrier Board:

D15

D16

For DP, connector to device or DP connector

HP pin.

For HDMI / DVI, connect 3.3V to 5V Level

Shifter to device, HDMI or DVI PD ping.

NC if not used.

DDI channel1, DP AUX function.

DDC_AUX_SEL is no connect.

Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.

Module has integrated AC Coupling

Capacitor, AUX+ PD resistor to GND and

AUX- Pull up to 3.3V.

Carrier Board:

Connect to device or DP connector.

N/C if not used.

DDI channel1, HDMI / DVI I 2 C function.

DDC_AUX_SEL is pulled high.

Carrier Board:

Connect 3.3V-5V Level Shifter to device,

HDMI or DVI connector.

N/C if not used.

D34 Selects the function of

DDI1_CTRLCLK_AUX+ and

DDI1_CTRLDATA_AUX-.

If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

Module has integrated PD resistor to GND.

Carrier Board:

DP1 AUX+/- - N/C

HDMI1: PU 100K to 3.3V

N/C if not used.

I/O

I 3.3V

COMS

I/O PCIE

I/O OD

3.3V

COMS

I 3.3V

COMS

Notes

４６

Table 10

: DDI2 Signal Description

Signal

DDI2_PAIR0+

DDI2_PAIR0-

DDI2_PAIR1+

DDI2_PAIR1-

DDI2_PAIR2+

DDI2_PAIR2-

DDI2_PAIR3+

DDI2_PAIR3-

Pin# Description

D39

D40

D42

D43

D46

D47

D49

D50

DDI channel 2, differential pairs 0.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

DDI channel 2, differential pairs 1.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

DDI channel 2, differential pairs 2.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

DDI channel 2, differential pairs 3.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

I/O

O PCIE

Notes

1

O PCIE 1

O PCIE 1

O PCIE 1

４７

Signal

DDI2_HPD

DDI2_CTRLCLK_AUX+

DDI2_CTRLCLK_AUX-

DDI2_DDC_AUX_SEL

Pin# Description

D44 DDI channel 2, Hot-Plug Detect.

Module has integrated current blocking circuit and PD resistor to GND

Carrier Board:

C32

C33

For DP, connector to device or DP connector

HP pin.

For HDMI / DVI, connect 3.3V to 5V Level

Shifter to device, HDMI or DVI PD ping.

NC if not used.

DDI channel12 DP AUX function.

DDC_AUX_SEL is no connect.

Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.

Module has integrated AC Coupling

Capacitor, AUX+ PD resistor to GND and

AUX- Pull up to 3.3V.

Carrier Board:

Connect to device or DP connector.

N/C if not used.

DDI channel2, HDMI / DVI I 2 C function.

DDC_AUX_SEL is pulled high.

Carrier Board:

Connect 3.3V-5V Level Shifter to device,

HDMI or DVI connector.

N/C if not used.

C34 Selects the function of

DDI2_CTRLCLK_AUX+ and

DDI2_CTRLDATA_AUX-.

If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

Module has integrated PD resistor to GND.

Carrier Board:

DP2 AUX+/- - N/C

HDMI2: PU 100K to 3.3V

N/C if not used.

I/O

I 3.3V

COMS

I/O PCIE

I/O OD

3.3V

COMS

I 3.3V

COMS

Notes

1

1

1

４８

Notes:

1.

SOM-6898 default is not support DDI2, it is option function. If customers want to use DDI2 function, please contact Advantech.

Table 11

: DDI3 Signal Description

Signal

DDI3_PAIR0+

DDI3_PAIR0-

DDI3_PAIR1+

DDI3_PAIR1-

DDI3_PAIR2+

DDI3_PAIR2-

Pin# Description

C39 DDI channel 3, differential pairs 0.

C40 Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

C42

C43

C46

C47

DDI channel 3, differential pairs 1.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

DDI channel 3, differential pairs 2.

Carrier Board:

For DP, connect AC Coupling Capacitors 75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling Capacitors

75~200 nF near COME and Level Shifter to HDMI or

DVI connector.

N/C if not used.

I/O

O PCIE

O PCIE 1

O PCIE 1

Notes

1

４９

Signal

DDI3_PAIR3+

DDI3_PAIR3-

DDI3_HPD

DDI3_CTRLCLK_AUX+

DDI3_CTRLCLK_AUX-

Pin# Description

C49

C50

DDI channel 3, differential pairs 3.

Carrier Board:

For DP, connect AC Coupling Capacitors

75~200 nF near COME to device or DP connector.

For HDMI / DVI, connect AC Coupling

Capacitors 75~200 nF near COME and Level

Shifter to HDMI or DVI connector.

N/C if not used.

C44 DDI channel 3, Hot-Plug Detect.

Module has integrated current blocking circuit and PD resistor to GND

Carrier Board:

For DP, connector to device or DP connector

HP pin.

For HDMI / DVI, connect 3.3V to 5V Level

Shifter to device, HDMI or DVI PD ping.

NC if not used.

C36

C37

DDI channel 3, DP AUX function.

DDC_AUX_SEL is no connect.

Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.

Module has integrated AC Coupling

Capacitor, AUX+ PD resistor to GND and

AUX- Pull up to 3.3V.

Carrier Board:

Connect to device or DP connector.

N/C if not used.

DDI channel1, HDMI / DVI I 2 C function.

DDC_AUX_SEL is pulled high.

Carrier Board:

Connect 3.3V-5V Level Shifter to device,

HDMI or DVI connector.

N/C if not used.

I/O

O PCIE 1

I 3.3V

COMS

I/O PCIE

I/O OD

3.3V

COMS

Notes

1

1

５０

Signal Pin# Description

DDI3_DDC_AUX_SEL

Notes:

1.

SOM-6898 is not support DDI3.

C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-.

If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

Module has integrated PD resistor to GND.

Carrier Board:

DP3 AUX+/- - N/C

HDMI3: PU 100K to 3.3V

N/C if not used.

I/O

I 3.3V

COMS

Notes

1

５１

2.5.2 Digital Display Interfaces (DDI) Routing Guidelines

2.5.2.1. DisplayPort Routing Guidelines

Carriers that support DisplayPort (DisplayPort only or dual mode):

• DC blocking capacitors shall be placed on the Carrier for the DDI[n]_PAIR[0:3] signals.

• The Carrier shall include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the Module.

When implementing DisplayPort on the Carrier Board, the DP_AUX+ line shall have a pulldown resistor to GND. The resistor value should be 100kΩ. The DP_AUX- line shall have a pull-up resistor to 2.5V. The resistor value should be 100kΩ. The resistors shall be placed on the DisplayPort connector side of the AC coupling capacitors. The DP_HP signal shall include a blocking FET to prevent back-drive current damage. The DP_HP signal shall be pulled-down to GND with a 110kΩ resistor.

The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, they only requirement placed on Modules for the DDI signals is the maximum trace length specified below.

Figure 7

: DisplayPort Loss Budget

Table 12

: DisplayPort Insertion Loss Budget

Segment

L

A

L

B

L

C

Total

max. Length

[mm/inches]

127/5.0

TBD

TBD

Notes

Allowance for module trace. Coupling cap effects included within simulation.

COM Express™ connector simulated at 2.5 GHz.

Allowance for Carrier Board trace.

５２

Figure 8

: Topology for DisplayPort

L

A

L

B

TX

-

+

MODULE

CONN

DP

+

RX

-

MODULE CARRIER BOARD

Table 13

: DisplayPort Connector / Device Down Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Isolation to equivalent pairs

Isolation to other signal groups

LA

LB

Max length of LA+LB

Length matching

Reference Plane

Carrier Board Via Usage

AC coupling

Main Route Guidelines

DisplayPort

85 Ω ±10%

50Ω ±10%

20 mils (MS) and 15 mils (DS)

20 mils (MS) and 15 mils (DS)

Please see the SOM-6898 Layout Checklist

Carrier Board Length

DDI differential pairs to DP connector: 6.9”

DDI differential pairs to Device Down: 6.9”

AUX channel: 13”

Differential pairs (intra-pair): Max.

±5 mils

For each channel, match the lengths of the differential pairs (Inter-Pair) to be within a 1-inch window (max length – min length < 1 inch (2.54 cm)).

GND referencing preferred.

Min 40-mil trace edge-to-major plane edge spacing.

Max. 2 vias.

Min = 75 nF

Max = 200 nF

1

Notes:

1.

AC caps are recommended to be placed close to device side (avoid placing AC cpas on mid-bus).

Notes

５３

2.5.2.2. HDMI / DVI Routing Guidelines

When implementing HDMI level shifters shall be used on the TMDS signals. Bi-directional level shifters shall be used between the 3.3V and 5V CTRLCLK and CTRLDATA signals with 2.2kΩ pull-ups to 3.3V and 5V.

Carriers that support TMDS (DVI/HDMI):

• DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pair as the DDC channel.

• Bi-directional level translators shall be placed on the Carrier DDI[n]_CTRLDATA_AUX- and

DDI[n]_CTRLCLK_AUX+ to convert the 3.3V DDC channel on the Module to the 5V DDC channel for the TMDS display.

• Pull-up resistors shall be placed on the Carrier from 3.3V (Module side of level translator) and 5V

(display side of level translator) and the [n]_CTRLDATA_AUX- and DI[n]_CTRLCLK_AUX+ signals.

The pull-up resistor should be 2k.

• Level translators Shall be placed on the Carrier DDI[n]_PAIR[0:3] signals.

• DC blocking capacitors shall be placed on the Carrier for the DDI[n]_PAIR[0:3] signals.

• The Carrier shall include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the module.

The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee.

At this time, they only requirement placed on Modules for the DDI signals is the maximum trace length specified below.

Figure 9

: HDMI / DVI (TMDS) Loss Budget

Table 14

: HDMI / DVI (TMDS) Insertion Loss Budget

Segment

L

A

L

B

L

C

Total

max. Length

[mm/inches]

127/5.0

TBD

TBD

Notes

Allowance for module trace. Coupling cap effects included within simulation.

COM Express™ connector simulated at 2.5 GHz.

Allowance for Carrier Board trace.

５４

Figure 10

: Topology for HDMI / DVI

L

A

L

B

+

TX

-

MODULE

CONN

Level

Shifter

HDMI / DVI

+

RX

-

MODULE CARRIER BOARD

Table 15

: HDMI / DVI Connector / Device Down Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Isolation to equivalent pairs

Isolation to other signal groups

LA

Main Route Guidelines

HDMI / DVI (TMDS)

85 Ω ±10%

50Ω ±10%

20 mils (MS) and 15 mils (DS)

20 mils (MS) and 15 mils (DS)

Please see the SOM-6898 Layout Checklist

LB

Max length of LA+LB

Length matching

Carrier Board Length

DDI differential pairs to HDMI/DVI connector: 6.5”

DDI differential pairs to Device Down: 6.5”

DDC channel: 15”

Differential pairs (intra-pair): Max.

±5 mils

For each channel, match the lengths of the differential pairs (Inter-Pair) to be within a 1-inch window (max length – min length < 1 inch (2.54 cm)).

Reference Plane

Carrier Board Via Usage

AC coupling

GND referencing preferred.

Min 40-mil trace edge-to-major plane edge spacing.

Max. 2 vias.

Min = 75 nF 1

Max = 200 nF

Notes:

1. AC caps are recommended to be placed close to device side (avoid placing AC cpas on mid-bus).

Notes

５５

2.5.3. HDMI / DVI Level Shifter Requirements

The HDMI specification requires the receiver to be terminated to AVCC (nominally 3.3 V) through Rt

(nominally 50 Ω). The HDMI receiver requirements require the native HDMI signals from the SOC to be level shifted. This prevents electrical overstress of the driver and ensure that the receiver is operational within the receiver specifications defined in the High Definition Multimedia Interface Specification 1.4a

.

2.5.4. ESD Protection

HDMI signals are subjected to ESD strikes due to plugging in of the devices through the HDMI cable and frequent human contact that can destroy both the HDMI host and devices on the platform. Therefore these ports need to be protected.

There are a wide variety of ESD protection devices and ESD suppressors readily available in the market such as Metal Oxide Varistors (MOVs), Zener Diode, Transient Voltage Suppressor (TVS), Polymer devices and ESD diode arrays. With 1.65 Gbps of data rate, HDMI is very sensitive to parasitic capacitance. Excessive parasitic capacitance can severely degrade the signal integrity and lead to a compliance or operational failure. To maintain signal integrity, Intel recommends to use ESD suppressors or diode arrays having a low junction capacitance.

Recommended characteristics of an ideal ESD Protection Diode for HDMI:

• Able to withstand at least 8 kV of ESD strikes.

• Low capacitance <1 pF to minimize signal distortion at high data rates as higher capacitance degrade the HDMI signal quality.

• Fast response/rise time to protect from the fast rise time of ESD surge pulses.

• Low-leakage current to minimize static power consumption.

• Ensure the selected ESD solution will not violate HDMI Voff spec. In a low power state a power rail

ESD diode can become forward biased as a result on the HDMI sink (panel) termination of 50 Ω to 3.3

V

• Some ESD devices may impact the trace impedance. Care should be taken while choosing such devices so that the differential-impedance target in the HDMI 1.4 Specification is not violated.

The HDMI 1.4a Specification requires that 8 kV of ESD strikes be tolerated.

The ESD protection devices should be placed as close to the HDMI connector as possible so that when

ESD strikes occur, the discharges can be quickly absorbed or diverted to the ground/power plane before it is coupled to another signal path nearby.

Footprints for ESD components or diode arrays can be provided on board with no stubs and no more than 750 mils (19.05 mm) from the connector. The ESD components can be stuffed depending on the requirement.

５６

2.6. LAN Interface

All COM Express Modules provide at least one LAN port. The 8-wire 10/100/1000BASE-T Gigabit

Ethernet interface compliant to the IEEE 802.3-2005 specification is the preferred interface for this port, with the COM Express Module PHY responsible for implementing auto-negotiation of 10/100BASE-TX vs 10/100/1000BASE-T operation. The carrier may also support a 4-wire 10/100BASE-TX interface from the COM Express Module on an exception basis. Check with your vendor for 10/100 only implementations.

2.6.1. LAN Signal Definitions

The LAN interface of the COM Express Module consists of 4 pairs of low voltage differential pair signals designated from 'GBE0_MDI0' (+ and -) to 'GBE0_MDI3' (+ and -) plus additional control signals for link activity indicators. These signals can be used to connect to a 10/100/1000BASE-T

RJ45 connector with integrated or external isolation magnetics on the

Carrier Board. The corresponding LAN differential pair and control signals can be found on rows A and B of the Module's connector.

Table 16

: LAN Interface Signal Descriptions

Signal

GBE0_MDI0+

GBE0_MDI0-

GBE0_MDI1+

GBE0_MDI1-

Pin# Description

A13

A12

A10

A9

Media Dependent Interface (MDI) differential pair

0. The MDI can operate in 1000, 100, and

10Mbit/sec modes.

Module has integrated termination.

Carrier Board:

Connect to Magnetics Module MDI0+/-

N/C if not used.

Media Dependent Interface (MDI) differential pair

1. The MDI can operate in 1000, 100, and

10Mbit/sec modes.

Module has integrated termination.

Carrier Board:

Connect to Magnetics Module MDI0+/-

N/C if not used

I/O

I/O GBE

Note

I/O GBE

５７

Signal

GBE0_MDI2+

GBE0_MDI02

GBE0_MDI3+

GBE0_MDI3-

Pin# Description

A7

A6

Media Dependent Interface (MDI) differential pair

2. The MDI can operate in 1000, 100, and

10Mbit/sec modes.

Module has integrated termination.

Carrier Board:

A3

A2

Connect to Magnetics Module MDI2+/-

N/C if not used.

Media Dependent Interface (MDI) differential pair

3. The MDI can operate in 1000, 100, and

10Mbit/sec modes.

Module has integrated termination.

Carrier Board:

I/O

I/O GBE

I/O GBE

GBE0_CTREF

Connect to Magnetics Module MDI3+/-

N/C if not used

A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap.

Carrier Board:

0.1uF to ground.

N/C if not used.

A8 Ethernet controller 0 link indicator, active low.

REF

GBE0_LINK#

GBE0_LINK100# A4 Ethernet controller 0 100Mbit/sec link indicator, active low.

O 3.3V

Suspend /

3.3V

OD CMOS

O 3.3V

Suspend /

3.3V

OD CMOS

O 3.3V GBE0_LINK1000# A5 Ethernet controller 0 1000Mbit/sec link indicator,

GBE0_ACT# active low. Suspend /

3.3V

OD CMO

B2 Ethernet controller 0 activity indicator, active low. O 3.3V

Suspend /

3.3V

OD CMO

Note

５８

2.6.2. LAN Routing Guidelines

10/100/1000 Ethernet Insertion Loss Budget

Figure 11

: 10/100/1000 Ethernet Insertion Loss Budget

Segment

L

A

L

B

L

C

L

D

Total

COM ExpressTM Ethernet implementations should conform to insertion loss values less than or equal to those shown in the table above. The insertion loss values shown account for frequency dependent material losses only. Cross talk losses are separate from material losses in the Gb Ethernet pecification.

“Device Down” implementations, in which the Ethernet target device is implemented on the Carrier

Board (for instance, an Ethernet switch), may add the insertion loss for the RJ45 Ethernet jack and integrated magnetics to the Carrier Board budget. This insertion loss value is typically 1 dB. The Carrier

Board insertion loss budget then becomes LC + 1 dB, or 1.15 dB.

Table 17

: 10/100/1000 Ethernet Insertion Loss Budget, 100 MHz

Loss (dB) Notes

COM Express

TM

connector at 100 MHz measured value

24.25

５９

2.6.3. LAN Trace Length Guidelines

Figure 12

: Topology for Ethernet Jack

Table 18

: Ethernet Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Spacing between RX and TX pairs (inter-pair) (s)

Spacing between differential pairs and high-speed periodic signals

Spacing between differential pairs and low-speed non periodic signals

Spacing between digital ground and analog ground plane

(between the magnetics Module and RJ45 connector)

LA

LB

Max length of LA+LB

Main Route Guidelines

GBE0_MDIx+, GBE0_MDIx-

100 Ω ±10%

50Ω ±10%

Min. 50mils

Min. 300mils

Min. 100mils

Min. 60mils

Length matching

Reference Plane

Spacing from edge of plane

Carrier Board Via Usage

Notes:

Please see the SOM-6898 Layout Checklist

Carrier Board Length

COM Express Module to the magnetics Module - 5.0 inches.

Magnetics Module to RJ45 connector - Max. 1.0 inches.

Differential pairs (intra-pair): Max.

± 15 mils

RX and TX pairs (inter-pair) - Max. ±1000mils

GND referencing preferred..

Min. 40mils

Max. 2 vias.

Notes

６０

2.6.4. Reference Ground Isolation and Coupling

The Carrier Board should maintain a well-designed analog ground plane around the components on the primary side of the transformer between the transformer and the RJ-45 receptacle. The analog ground plane is bonded to the shield of the external cable through the RJ-45 connector housing.

The analog ground plane should be coupled to the carrier’s digital logic ground plane using a capacitive coupling circuit that meets the ground plane isolation requirements defined in the 802.3-2005 specification. It is recommended that the Carrier Board PCB design maintain a minimum 30 mil gap between the digital logic ground plane and the analog ground plane.

It's recommended to place an optional GND to SHIELDGND connection near the RJ-45 connector to improve EMI and ESD capabilities.

６１

2.7. USB2.0 Ports

A COM Express Module must support a minimum of 4 USB Ports and can support up to 8 USB Ports. All of the USB Ports must be USB2.0 compliant. There are 4 over-current signals shared by the 8 USB

Ports. A Carrier must current limit the USB power source to minimize disruption of the Carrier in the event that a short or over-current condition exists on one of the USB Ports. A Module must fill the USB

Ports starting at Port 0. The USB SuperSpeed ports 0, 1, 2 and 3, if used, are to be paired with USB 2.0 ports 0, 1, 2 and 3 in the same order. The USB SuperSpeed ports use the same over current signaling mechanism as the USB 2.0 ports, but USB 3.0 allows up to 1A current per port instead of 500mA allowed in USB 2.0. Although USB 2.0 signals use differential signaling, the USB specification also encodes single ended state information in the differential pair, making EMI filtering somewhat challenging. Ports that are internal to the Carrier do not need EMI filters. A USB Port can be powered from the Carrier Main Power or from the Carrier Suspend Power. Main Power is used for USB devices that are accessed when the system is powered on. Suspend Power (VCC_5V_SBY) is used for devices that need to be powered when the Module is in Sleep-State S5. This would typically be for USB devices that support Wake-on-USB. The amount of current available on VCC_5V_SBY is limited so it should be used sparingly.

2.7.1. USB2.0 Signal Definitions

Table 19

: USB Signal Descriptions

Signal

USB0+

USB0-

USB1+

USB1-

Pin# Description

A46

A45

USB Port 0, data + or D+

USB Port 0, data + or D-

Carrier board:

Device - Connect to D+/-

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

B46

B45

USB Port 1, data + or D+

USB Port 1, data + or D-

Carrier board:

Device - Connect to D+/-

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

I/O

I/O USB

Note

I/O USB

６２

Signal

USB2+

USB2-

USB3+

USB3-

USB4+

USB4-

USB5+

USB5-

USB6+

USB6-

Pin# Description

A43 USB Port 2, data + or D+

A42 USB Port 2, data + or D-

Carrier board:

Device - Connect to D+/-

B43

B42

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

USB Port 3, data + or D+

USB Port 3, data + or D-

Carrier board:

Device - Connect to D+/-

A40

A39

B40

B39

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

USB Port 4, data + or D+

USB Port 4, data + or D-

Carrier board:

Device - Connect to D+/-

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

USB Port 5, data + or D+

USB Port 5, data + or D-

Carrier board:

Device - Connect to D+/-

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

A37

A36

USB Port 6, data + or D+

USB Port 6, data + or D-

Carrier board:

Device - Connect to D+/-

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

I/O

I/O USB

Note

I/O USB

I/O USB

I/O USB

I/O USB

６３

Notes:

Signal

USB7+

USB7-

USB_0_1_

OC#

USB_2_3_

OC#

USB_4_5_

OC#

USB_6_7_

OC#

Pin# Description

B37 USB Port 7, data + or D+

B36 USB Port 7, data + or D-

Carrier Board:

Device - Connect to D+/-

Conn. - Connect 90Ω @100MHz Common Choke in series and ESD suppressors to GND to Pin 3 D+ / Pin 2 D-

N/C if not used

B44 USB over-current sense, USB ports 0 and 1.

Carrier Board:

Connect to Overcurrent of Power Distribution Switch and

Bypass 0.1uF to GND

N/C if not used

A44 USB over-current sense, USB ports 2 and 3.

Carrier Board:

Connect to Overcurrent of Power Distribution Switch and

Bypass 0.1uF to GND

N/C if not used

B38 USB over-current sense, USB ports 4 and 5.

Carrier Board:

Connect to Overcurrent of Power Distribution Switch and

Bypass 0.1uF to GND

N/C if not used

A38 USB over-current sense, USB ports 6 and 7.

Carrier Board:

Connect to Overcurrent of Power Distribution Switch and

Bypass 0.1uF to GND

N/C if not used

I/O

I/O USB

Note

I

CMOS

I 3.3V

CMOS

I

CMOS

I

3.3V

3.3V

3.3V

CMOS

６４

2.7.1.1. USB Over-Current Protection (USB_x_y_OC#)

The USB Specification describes power distribution over the USB port, which supplies power for USB devices that are directly connected to the Carrier Board. Therefore, the host must implement over-current protection on the ports for safety reasons. Should the aggregate current drawn by the downstream ports exceed a permitted value, the over-current protection circuit removes power from all affected downstream ports. The over-current limiting mechanism must be resettable without user mechanical intervention. For more detailed information about this subject, refer to the 'Universal Serial

Bus Specifications Revision 2.0', which can be found on the website http://www.usb.org.

Over-current protection for USB ports can be implemented by using power distribution switches on the

Carrier Board that monitor the USB port power lines. Power distribution switches usually have a soft-start circuitry that minimizes inrush current in applications where highly capacitive loads are employed. Transient faults are internally filtered.

Additionally, they offer a fault status output that is asserted during over-current and thermal shutdown conditions. These outputs should be connected to the corresponding COM Express Modules USB over-current sense signals. Fault status signaling is an option at the USB specification. If you don't need the popup message in your OS you may leave the signals USB_0_1_OC#, USB_2_3_OC#,

USB_4_5_OC# and USB_6_7_OC# unconnected.

Simple resettable PolySwitch devices are capable of fulfilling the requirements of USB overcurrent protection and therefore can be used as a replacement for power distribution switches.

Fault status signals are connected by a pullup resistor to VCC_3V3_SBY on COM Express Module.

Please check your tolerance on a USB port with VCC_5V supply.

2.7.1.2. Powering USB devices during S5

The power distribution switches and the ESD protection shown in the schematics can be powered from

Main Power or Suspend Power (VCC_5V_SBY). Ports powered by Suspend Power are powered during the S3 and S5 system states. This provides the ability for the COM Express Module to generate system wake-up events over the USB interface.

６５

2.7.2. USB2.0 Routing Guidelines

USB Insertion Loss Budget

Figure 13

: USB Insertion Loss Budget

COM ExpressTM USB implementations should conform to insertion loss values less than or equal to those shown in the table above. The insertion loss values shown account for frequency dependent material losses only. Cross talk losses are separate from material losses in the USB specification.

"Device Down” implementations, in which the USB target device is implemented on the Carrier Board, may add the ferrite and USB connector insertion loss values to the Carrier Board budget.

The Carrier Board insertion loss budget then becomes LC + LD, or 2.68 dB.

Table 20

USB Insertion Loss Budget, 400 MHz

Segment

L

A

L

B

L

C

L

D

L

E

Total

Loss (dB) Notes

9.20

６６

2.7.2.1. USB 2.0 General Design Considerations and Optimization

Use the following general routing and placement guidelines when laying out a new design. These guidelines help minimize signal quality and EMI problems.

• Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks.

• Separate signal traces into similar categories, and route similar signal traces together (such as routing differential-pairs together).

• Keep USB 2.0 signals clear of the core logic set. High current transients are produced during internal state transitions and can be very difficult to filter out.

• Follow the 20 x h rule by keeping traces at least [20 x (height above the plane)] mils away from the edge of the plane (VCC or GND). For an example stackup, the height above the plane is 4.5 mils (0.114 mm). This calculates to a 90-mil (2.286-mm) spacing requirement from the edge of the plane. This helps prevent the coupling of the signal onto adjacent wires and also helps prevent free radiation of the signal from the edge of the PCB.

• Avoid stubs on high-speed USB signals because stubs cause signal reflections and affect signal quality.

If a stub is unavoidable in the design, the total of all the stubs on a particular line should not be greater than 200 mils (5.08 mm).

2.7.2.2. USB 2.0 Port Power Delivery

The following is a suggested topology for power distribution of VBUS to USB ports.

These circuits provide two types of protection during dynamic attach and detach situations on the bus: inrush current limiting (droop) and dynamic detach flyback protection. These two types require both bulk capacitance (droop) and filtering capacitance (for dynamic detach flyback voltage filtering).

Intel recommends the following:

• Minimize the inductance and resistance between the coupling capacitors and the USB ports.

• Place capacitors as close as possible to the port and the power-carrying traces should be as wide as possible, preferably, a plane.

• Make the power-carrying traces wide enough that the system fuse blows on an over current event. If the system fuse is rated at 1 A, then the power-carrying traces should be wide enough to carry at least

1.5 A.

６７

Figure 14

: USB 2.0 Good Downstream Power Connection

2.7.2.3. USB 2.0 Common Mode Chokes

Testing has shown that common mode chokes can provide required noise attenuation. A design should include a common mode choke footprint to provide a stuffing option in the event the choke is needed to pass EMI testing. Below figure shows the schematic of a typical common mode choke and ESD suppression components. Place the choke as close as possible to the USB connector signal pins.

Figure 15

: USB 2.0 A Common Mode Choke

６８

Common mode chokes distort full-speed and high-speed signal quality. As the common mode impedance increases the distortion increases, therefore test the effects of the common mode choke on full speed and high-speed signal quality. Common mode chokes with a target impedance of 80 Ω to 90 Ω, at 100 MHz, generally provide adequate noise attenuation.

Finding a common mode choke that meets the designer’s needs is a two-step process:

1. Choose a part with the impedance value that provides the required noise attenuation. This is a function of the electrical and mechanical characteristics of the part chosen and the frequency and strength of the noise present on the USB traces that should be suppressed.

2. After obtaining a part that gives passing EMI results, the second step is to test the effect this part has on signal quality. Higher impedance common mode chokes generally have a greater damaging effect on signal quality, so care must be used when increasing the impedance without doing thorough testing.

Thorough testing means that the signal quality must be checked for low-speed, full-speed, and highspeed USB operation.

Further common mode choke information can be found on the high-speed USB Platform

Design Guides available at www.usb.org

.

2.7.2.4. EMI / ESD Protection

To improve the EMI behavior of the USB interface, a design should include common mode chokes, which have to be placed as close as possible to the USB connector signal pins.

Common mode chokes can provide required noise attenuation but they also distort the signal quality of full-speed and high-speed signaling. Therefore, common mode chokes should be chosen carefully to meet the requirements of the EMI noise filtering while retaining the integrity of the USB signals on the

Carrier Board design.

To protect the USB host interface of the Module from over-voltage caused by electrostatic discharge

(ESD) and electrical fast transients (EFT), low capacitance steering diodes and transient voltage suppression diodes have to be implemented on the Carrier Board design. In the USB reference schematics Figure 29 above, this is implemented by using 'SR05 RailClampR' surge rated diode arrays from Semtech ( http://semtech.com

).

６９

2.7.3. USB2.0 Trace Length Guidelines

Figure 16

: Topology for USB2.0

Table 21

: USB2.0 Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Spacing between pairs-to-pairs

(inter-pair) (s)

Spacing between differential pairs and high-speed periodic signals

Spacing between differential pairs and low-speed non periodic signals

LA

LB

Max length of LA+LB

Length matching

Reference Plane

Spacing from edge of plane

Carrier Board Via Usage

Notes:

Main Route Guidelines

USB[7:0]+, USB[7:0]-

85 Ω ±10%

50Ω ±10%

Min. 20 mils

Min. 50 mils

Min. 20 mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

9”

Differential pairs (intra-pair): Max.

±5 mils

GND referencing preferred

Min. 40mils

Try to minimize number of vias

７０

Notes

2.8. USB3.0

USB 3.0 is the third major revision of the Universal Serial Bus (USB) standard for computer connectivity.

It adds a new transfer speed called SuperSpeed (SS) to the already existing LowSpeed (LS), FullSpeed

(FS) and HighSpeed (HS).

USB 3.0 leverages the existing USB 2.0 infrastructure by adding two additional data pair lines to allow a transmission speed up to 5 Gbit/s, which is 10 times faster than USB 2.0 with 480 Mbit/s.

The additional data lines are unidirectional instead of the bidirectional USB 2.0 data lines. USB 3.0 is fully backward compatible to USB 2.0. USB 3.0 connectors are different from USB 2.0 connectors. The

USB 3.0 connector is a super set of a USB 2.0 connector, with 4 additional pins that are invisible to USB

2.0 connectors. A USB 2.0 Type A plug may be used in a USB 3.0 Type A receptacle, but the USB 3.0

SuperSpeed functions will not be available.

2.8.1. USB3.0 Signal Definitions

Table 22: USB3.0 Signal Definitions

Signal Pin# Description

USB_SSTX0+

USB_SSTX0-

D4

D3

USB Port 0, SuperSpeed TX +

USB Port 0, SuperSpeed TX –

Module has integrated AC Coupling Capacitors

Carrier Board:

Device - Connect to StdA_SSRX+/-

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 9

USB_SSTX1+

USB_SSTX1-

D7

D6

StdA_SSTX+ / Pin 8 StdA_SSTX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

USB Port 1, SuperSpeed TX +

USB Port 1, SuperSpeed TX –

Module has integrated AC Coupling Capacitors

Carrier Board:

Device - Connect to StdA_SSRX+/-

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 9

StdA_SSTX+ / Pin 8 StdA_SSTX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

I/O

O PCIE

Note

O PCIE

７１

Signal

USB_SSTX2+

USB_SSTX2-

USB_SSTX3+

USB_SSTX3-

USB_SSRX0+

USB_SSRX0-

Pin# Description

D10 USB Port 2, SuperSpeed TX +

D9 USB Port 2, SuperSpeed TX –

Module has integrated AC Coupling Capacitors

Carrier Board:

D13

D12

Device - Connect to StdA_SSRX+/-

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 9

StdA_SSTX+ / Pin 8 StdA_SSTX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

USB Port 3, SuperSpeed TX +

USB Port 3, SuperSpeed TX –

Module has integrated AC Coupling Capacitors

Carrier Board:

Device - Connect to StdA_SSRX+/-

C4

C3

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 9

StdA_SSTX+ / Pin 8 StdA_SSTX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

USB Port 0, SuperSpeed RX +

USB Port 0, SuperSpeed RX –

Carrier Board:

Device - Connect AC Coupling Capacitors 100nF near COME to StdA_SSTX+/-

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 6

StdA_SSRX+ / Pin 5 StdA_SSRX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

I/O

O PCIE

Note

O PCIE

I PCIE

７２

Notes:

Signal

USB_SSRX1+

USB_SSRX1-

USB_SSRX2+

USB_SSRX2-

USB_SSRX3+

USB_SSRX3-

Pin# Description

C7

C6

USB Port 1, SuperSpeed RX +

USB Port 1, SuperSpeed RX –

Carrier Board:

Device - Connect AC Coupling Capacitors 100nF near COME to StdA_SSTX+/-

C10

C9

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 6

StdA_SSRX+ / Pin 5 StdA_SSRX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

USB Port 2, SuperSpeed RX +

USB Port 2, SuperSpeed RX –

Carrier Board:

Device - Connect AC Coupling Capacitors 100nF near COME to StdA_SSTX+/-

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

C13

C12

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 6

StdA_SSRX+ / Pin 5 StdA_SSRX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

USB Port 3, SuperSpeed RX +

USB Port 3, SuperSpeed RX –

Carrier Board:

Device - Connect AC Coupling Capacitors 100nF near COME to StdA_SSTX+/-

Conn. - Connect 0Ω and 90Ω @100MHz USB3.0

Common Mode Choke(NL) combined in series and

USB3.0 ESD suppressors to GND to Pin 6

StdA_SSRX+ / Pin 5 StdA_SSRX-, the value of CMC depends on EMI and signal integrity performance.

N/C if not used

I/O

I PCIE

I PCIE

I PCIE

Note

７３

2.8.1.1. USB Over-Current Protection (USB_x_y_OC#)

The USB Specification describes power distribution over the USB port, which supplies power for

USB devices that are directly connected to the Carrier Board. Therefore, the host must implement over-current protection on the ports for safety reasons. Should the aggregate current drawn by the downstream ports exceed a permitted value, the over-current protection circuit removes power from all affected downstream ports. The over-current limiting mechanism must be resettable without user mechanical intervention. For more detailed information about this subject, refer to the 'Universal Serial

Bus Specifications Revision 2.0', which can be found on the website http://www.usb.org.

Over-current protection for USB ports can be implemented by using power distribution switches on the

Carrier Board that monitor the USB port power lines. Power distribution switches usually have a soft-start circuitry that minimizes inrush current in applications where highly capacitive loads are employed. Transient faults are internally filtered.

Additionally, they offer a fault status output that is asserted during over-current and thermal shutdown conditions. These outputs should be connected to the corresponding COM Express Modules USB over-current sense signals. Fault status signaling is an option at the USB specification. If you don't need the popup message in your OS you may leave the signals USB_0_1_OC#, USB_2_3_OC#,

USB_4_5_OC# and USB_6_7_OC# unconnected.

Fault status signals are connected by a pullup resistor to VCC_3V3_SBY on COM Express Module.

Please check your tolerance on a USB port with VCC_5V supply.

USB 2.0 port's VCC current limit should be set to 500mA. For USB 3.0 implementations, the VCC current limit is raised to 1A. A different, USB 3.0 compatible, power switch is used.

2.8.1.2. EMI / ESD Protection

To improve the EMI behavior of the USB interface, a design should include common mode chokes, which have to be placed as close as possible to the USB connector signal pins.

Common mode chokes can provide required noise attenuation but they also distort the signal quality of

FullSpeed, HighSpeed and SuperSpeed signaling. Therefore, common mode chokes should be chosen carefully to meet the requirements of the EMI noise filtering while retaining the integrity of the USB signals on the Carrier Board design.

To protect the USB host interface of the Module from over-voltage caused by electrostatic discharge

(ESD) and electrical fast transients (EFT), low capacitance steering diodes and transient voltage suppression diodes have to be implemented on the Carrier Board design.

７４

2.8.2. USB3.0 Routing Guidelines

USB3.0 Insertion Loss Budget

Figure 17

: USB3.0 Insertion Loss Budget

Table 23

: USB3.0 Insertion Loss Budget

Segment

L

A

L

B

L

C

Loss (dB)

1.94

1.20

3.64

Notes

Up to 3 inches of Module trace @ 2.5 GHz

COM Express connector at 2.5 GHz

Up to 5 inches of Carrier Board trace @ 2.5 GHz with Common-Mode

Component

Total 6.78

COM ExpressTM USB implementations should conform to insertion loss values less than or equal to those shown in the table above. The insertion loss values shown account for frequency dependent material losses only. Cross talk losses are separate from material losses in the USB specification.

"Device Down” implementations, in which the USB target device is implemented on the Carrier Board, may add the ferrite and USB connector insertion loss values to the Carrier Board budget.

The Carrier Board insertion loss budget then becomes LC + LD, or 2.68 dB.

７５

2.8.3. USB3.0 Trace Length Guidelines

Figure 18

: Topology for USB3.0

Table 24

: USB3.0 Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Spacing between pairs-to-pairs

(inter-pair) (s)

Spacing between differential pairs and high-speed periodic signals

Spacing between differential pairs and low-speed non periodic signals

LA

LB

Max length of LA+LB

Length matching

Reference Plane

Spacing from edge of plane

Carrier Board Via Usage

Notes:

Main Route Guidelines

USB3.0

85 Ω ±10%

50Ω ±10%

Min. 15 mils

Min. 15 mils

Min. 20 mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

7”

Differential pairs (intra-pair): Max.

GND referencing preferred

Min. 40mils

±5 mils

Max. 3 vias per differential signal trace

７６

Notes

2.9. SATA

Support for up to four SATA ports is defined on the COM Express A-B connector. Support for a minimum of two ports is required for all Module Types. The COM Express Specification allows for both SATA-150 and SATA-300 implementations. Constraints for SATA-300 implementations are more severe than those for SATA-150. The COM Express Specification addresses both in the section on insertion losses.

SATA devices can be internal to the system or external. The eSATA specification defines the connector used for external SATA devices. The eSATA interface must be designed to prevent damage from ESD, comply with EMI limits, and withstand more insertion/removals cycles than standard SATA. A specific eSATA connector was designed to meet these needs. The Esata connector does not have the “L” shaped key, and because of this, SATA and eSATA cables cannot be interchanged.

2.9.1. SATA Signal Definitions

Table 25: SATA Signal Definitions

Signal

SATA0_RX+

SATA0_RX-

SATA0_TX+

SATA0_TX-

SATA1_RX+

SATA1_RX-

Pin#

A19

A20

A16

A17

B19

B20

Description

Serial ATA channel 0, Receive input differential pair.

Module has integrated AC Coupling capacitor

Carrier Board:

Connect to SATA0 Conn pin 6 RX+

Connect to SATA0 Conn pin 5 RX-

N/C if not used.

Serial ATA channel 0, Transmit output differential pair.

Module has integrated AC Coupling capacito

Carrier Board:

Connect to SATA0 Conn pin 2 TX+

Connect to SATA0 Conn pin 3 TX-

N/C if not used.

Serial ATA channel 1, Receive input differential pair.

Module has integrated AC Coupling capacitor

Carrier Board:

Connect to SATA1 Conn pin 6 RX+

Connect to SATA1 Conn pin 5 RX-

N/C if not used.

I/O

I SATA

Note

O SATA

I SATA

７７

Signal

SATA1_TX+

SATA1_TX-

I/O

O SATA

Note

Able to drive

SATA2_RX+

SATA2_RX-

SATA2_TX+

SATA2_TX-

SATA3_RX+

SATA3_RX-

SATA3_TX+

SATA3_TX-

SATA_ACT#

Pin# Description

B16

B17

A25

A26

A22

A23

B25

B26

B22

B23

A28

Serial ATA channel 1, Transmit output differential pair.

Module has integrated AC Coupling capacito

Carrier Board:

Connect to SATA1 Conn pin 2 TX+

Connect to SATA1 Conn pin 3 TX-

N/C if not used.

Serial ATA channel 2, Receive input differential pair.

Module has integrated AC Coupling capacitor

Carrier Board:

Connect to SATA2 Conn pin 6 RX+

Connect to SATA2 Conn pin 5 RX-

N/C if not used.

Serial ATA channel 2, Transmit output differential pair.

Module has integrated AC Coupling capacito

Carrier Board:

Connect to SATA2 Conn pin 2 TX+

Connect to SATA2 Conn pin 3 TX-

N/C if not used.

Serial ATA channel 3, Receive input differential pair.

Module has integrated AC Coupling capacitor

Carrier Board:

Connect to SATA3 Conn pin 6 RX+

Connect to SATA3 Conn pin 5 RX-

N/C if not used.

Serial ATA channel 3, Transmit output differential pair.

Module has integrated AC Coupling capacitor

Carrier Board:

Connect to SATA3 Conn pin 2 TX+

Connect to SATA3 Conn pin 3 TX-

N/C if not used.

Serial ATA activity LED. Open collector output pin driven during SATA command activity.

Module has integrated PU resistor

Carrier Board:

Connect to LED and current limiting resistors 250 to 330 Ω to 3.3V

N/C if not used.

I SATA

O SATA

I SATA

O SATA

O 3.3V

CMOS

OC

1

1

1

1

10 mA

Notes:

SOM-6898 default is not support SATA2 and SATA3, SATA2 is option function. If customers want to use

SATA2 function, please contact Advantech.

７８

2.9.2. SATA Routing Guidelines

SATA Insertion Loss Budget

Figure 19

: SATA Insertion Loss Budge

The Serial ATA source specification provides insertion loss figures only for the SATA cable. There are several cable types defined with insertion losses ranging from 6 dB up to 16 dB. Cross talk losses are separate from material losses in the SATA specification.

The COM ExpressTM SATA Insertion loss budgets presented below represent the material losses and do not include cross talk losses. The COM ExpressTM SATA Insertion loss budgets are a guideline: module and Carrier Board vendors should not exceed the values shown in the tables below.

Table 26

: SATA Insertion Loss Budge

Segment

L

A

Coupling Caps

L

B

L

L

C

D

Total

Segment

L

A

L

C

L

D

Coupling Caps

L

B

Total

SATA Gen 1 Insertion Loss Budget, 1.5 GHz

Loss (dB) Notes

1.26 Up to 3.0 inches of module trace @ 0.28 dB / GHz / inch

0.40

0.25 COM Express TM connector at 1.5 GHz measured value

3.07 Up to 7.2 inches of Carrier Board trace @ 0.28 dB / GHz / inch

6.00 Source specification cable and cable connector allowance

10.98

SATA Gen 2 Insertion Loss Budget, 3.0 GHz

Loss (dB) Notes

1.68 Up to 2.0 inches of module trace @ 0.28 dB / GHz / inch

0.40

0.38 COM Express TM connector at 3.0 GHz measured value

2.52 Up to 3.0 inches of Carrier Board trace @ 0.28 dB / GHz / inch

6.00 Source specification cable and cable connector allowance

10.98

７９

2.9.2.1. General SATA Routing Guidelines

Use the following general routing and placement guidelines when laying out a new design.

• SATA signals must be ground referenced. If changing reference plane is completely unavoidable (that is, ground reference to power reference), proper placement of stitching caps can minimize the adverse effects of EMI and signal quality performance caused by reference plane change. Stitching capacitors are smallvalued capacitors (1 μF or lower in value) that bridge the power and ground planes close to where a high-speed signal changes layers. Stitching caps provide a high frequency current return path between different reference planes. They minimize the impedance discontinuity and current loop area that crossing different reference planes created. The maximum number allowed for SATA to change reference plane is one.

• Route all traces over continuous GND planes, with no interruptions. Avoid crossing over anti-etch if at all possible. Any discontinuity or split in the ground plane can cause signal reflections and should be avoided.

• Minimize layer changes. If a layer change is necessary, ensure that trace matching for either transmit or receive pair occurs within the same layer. Intel recommends to use SATA vias as seldom as possible.

• DO NOT route SATA traces under power connectors, other interface connectors, crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks.

• DO NOT place stubs, test points, test vias on the route to minimize reflection. Utilize vias and connector pads as test points instead.

• For testability, route the TX and RX pairs for a given port on the same layer and close to each other to help ensure that the pairs share similar signaling characteristics. If the groups of traces are similar, a measure of RX pair layout quality can be approximated by using the results from actively testing the TX pair's signal quality.

• Length matching rules are required on SATA differential signals for optimum timing margins, preventing common-mode signals and EMI.Each net within a differentialpair should be length matched on a segment-by-segment basis at the point of discontinuity. Total length mismatch must not be more than

20 mils (0.508 mm). Examples of segments might include breakout areas, routes running between two vias, routes between an AC coupling capacitor and a connector pin, etc. The points of discontinuity would be the via, the capacitor pad, or the connector pin.Matching of TX and RX within the same port and between SATA TX and RX pairs from differential ports is not required. When length matching compensation occurs, it should be made as close as possible to the point where the variation occurs.

• DO NOT serpentine to match RX and TX traces; there is NO requirement to match RX and TX traces.

In addition, DO NOT serpentine to meet minimum length guidelines on RX and TX traces.

• Recommend keeping SATA traces 20 mils (0.508 mm) from any vias on the motherboard whenever possible.

８０

2.9.3. SATA Trace Length Guidelines

Figure 20

: Topology for SATA

Table 27

: SATA Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Signal length available for the

COM Express Carrier Board

Spacing between RX and TX pairs (inter-pair) (s)

Spacing between differential pairs and high-speed periodic signals

Spacing between differential pairs and low-speed non periodic signals

LA

LB

Max length of LA+LB

Length matching

Reference Plane

Spacing from edge of plane

Carrier Board Via Usage

Notes:

Main Route Guidelines

SATA

85 Ω ±10%

50Ω ±10%

3 inches, a redriver may be necessary for GEN3 signaling rates

Min. 20 mils

Min. 50 mils

Min. 20 mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

7”

Differential pairs (intra-pair): Max.

GND referencing preferred

Min. 40mils

±5 mils

A maximum of 2 vias is recommended.

Notes

８１

2.10. LVDS

2.10.1.

Signal Definitions

The COM Express Specification provides an optional LVDS interface on the COM Express A-B connector. Module pins for two LVDS channels are defined and designated as LVDS_A and LVDS_B.

Systems use a single-channel LVDS for most displays. Dual LVDS channels are used for very high-bandwidth displays. Single-channel LVDS means that one complete RGB pixel is transmitted per display input clock. Dual-channel LVDS means that two complete RGB pixels are transmitted per display input clock. The two pixels are adjacent along a display line. Dual-channel LVDS does not mean that two

LVDS displays can be driven.

Each COM Express LVDS channel consists of four differential data pairs and a differential clock pair for a total of five differential pairs per channel. COM Express Modules and Module chipsets may not use all pairs. For example, with 18-bit TFT displays, only three of the four data pairs on the LVDS_A channel are used, along with the LVDS_A clock. The LVDS_B lines are not used. The manner in which RGB data is packed onto the LVDS pairs (including packing order and color depth) is not specified by the COM

Express Specification. This may be Module-dependent.

There are five single-ended signals included to support the LVDS interface: two lines are used for an I2C interface that may be used to support EDID or other panel information and identification schemes.

Additionally, there are an LVDS power enable (LVDS_VDD_EN) and backlight control and enable lines

(LVDS_BKLT_CTRL and LVDS_BKLT_EN).

Table 28

: LVDS Signal Definitions

Signal

LVDS_A0+

LVDS_A0-

LVDS_A1+

LVDS_A1-

Pin# Description

A71

A72

LVDS channel A differential signal pair 0

Carrier Board:

A73

A74

Connect 100Ω @100MHz Common Choke in series to

Reciever - RXinO0+/- with 100Ω termination

Conn. - RXinO0+/-

N/C if not used

LVDS channel A differential signal pair 1

Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever – RxinO1+/- with 100Ω termination

Conn. – RxinO1+/-

N/C if not used

I/O

O LVDS

Note

O LVDS

８２

Signal

LVDS_A2+

LVDS_A2-

LVDS_A3+

LVDS_A3-

LVDS_A_CK+

LVDS_A_CK-

LVDS_B0+

LVDS_B0-

LVDS_B1+

LVDS_B1-

LVDS_B2+

LVDS_B2-

Pin# Description

A75 LVDS channel A differential signal pair 2

A76 Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever – RxinO2+/- with 100Ω termination

A78

A79

Conn. – RxinO2+/-

N/C if not used

LVDS channel A differential signal pair 3

Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever – RxinO3+/- with 100Ω termination

Conn. – RxinO3+/-

N/C if not used

A81

A82

B71

B72

B73

B74

LVDS channel A differential clock pair

Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever - RXOC+/- with 100Ω termination

Conn. - RXOC+/-

N/C if not use

LVDS channel B differential signal pair 0

Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever - RXinE0+/- with 100Ω termination

Conn. - RXinE0+/-

N/C if not used

LVDS channel B differential signal pair 1

Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever – RxinE1+/- with 100Ω termination

B75

B76

Conn. – RxinE1+/-

N/C if not used

LVDS channel B differential signal pair 2

Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever – RxinE2+/- with 100Ω termination

Conn. – RxinE2+/-

N/C if not used

I/O

O LVDS

Note

O LVDS

O LVDS

O LVDS

O LVDS

O LVDS

８３

Signal

LVDS_B3+

LVDS_B3-

LVDS_B_CK+

LVDS_B_CK-

Pin# Description

B77 LVDS channel B differential signal pair 3

B78 Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever – RxinE3+/- with 100Ω termination

B81

B82

Conn. – RxinE3+/-

N/C if not used

LVDS channel B differential clock pair

Carrier Board:

Connect 100Ω @100MHz Common Choke in series to

Reciever - RXEC+/- with 100Ω termination

Conn. - RXEC+/-

N/C if not used

I/O

O LVDS

O LVDS

LVDS_VDD_EN A77 LVDS flat panel power enable.

Carrier Board:

Connect to enable control of LVDS panel power circuit.

N/C if not used

LVDS_BKLT_EN B79 LVDS flat panel backlight enable high active signal

Carrier Board:

Connect to enable control of LVDS panel backlight

O 3.3V,

CMOS

O 3.3V,

CMOS power circuit.

N/C if not used

Note

LVDS_BKLT_CT

RL

B83 LVDS flat panel backlight brightness control

Carrier Board:

Connect to brightness control of LVDS panel backlight power circuit.

N/C if not used

A83 DDC I2C clock signal used for flat panel detection and LVDS_I2C_CK control.

Carrier Board:

Connect to DDC clock of LVDS panel

N/C if not used

LVDS_I2C_DAT A84 DDC I2C data signal used for flat panel detection and control.

Carrier Board:

Connect to DDC data of LVDS panel

N/C if not used

O 3.3V,

CMOS

O 3.3V,

CMOS

I/O 3.3V,

OD

CMOS

８４

2.10.1.1. Display Timing Configuration

The graphic controller needs to be configured to match the timing parameters of the attached flat panel display. To properly configure the controller, there needs to be some method to determine the display parameters. Different Module vendors provide differing ways to access display timing parameters. Some vendors store the data in non-volatile memory with the BIOS setup screen as the method for entering the data, other vendors might use a Module or Carrier based EEPROM. Some vendors might hard code the information into the BIOS, and other vendors might support panel located timing via the signals

LVDS_I2C_CK and LVDS_I2C_DAT with an EEPROM strapped to 1010 000x. Regardless of the method used to store the panel timing parameters, the video BIOS will need to have the ability to access and decode the parameters. Given the number of variables it is recommended that Carrier designers contact

Module suppliers to determine the recommend method to store and retrieve the display timing parameters.

The Video Electronics Standards Association (VESA) recently released DisplayID, a second generation display identification standard that can replace EDID and other proprietary methods for storing flat panel timing data. DisplayID defines a data structure which contains information such as display model, identification information, colorimetry, feature support, and supported timings and formats. The

DisplayID data allows the video controller to be configured for optimal support for the attached display without user intervention. The basic data structure is a variable length block up to 256 bytes with additional 256 byte extensions as required. The DisplayID data is typically stored in a serial EPROM connected to the LVDS_I2C bus. The EPROM can reside on the display or Carrier. DisplayID is not backwards compatible with EDID. Contact VESA (www.vesa.org) for more information.

2.10.1.2. Backlight Control

Backlight inverters are either voltage, PWM or resistor controlled. The COM Express specification provides two methods for controlling the brightness. One method is to use the backlight control and enable signals from the CPU chipset. These signals are brought on COM Express LVDS_BKLT_EN and

LVDS_BKLT_CTRL. LVDS_BKLT_CTRL is a Pulse Width Modulated (PWM) output that can be connected to display inverters that accept a PWM input. The second method it to use the LVDS I2C bus to control an I2C DAC. The output of the DAC can be used to support voltage controlled inverters. The

DAC can be used driving the backlight voltage control input pin of the inverter.

８５

2.10.2. LVDS Routing Guidelines

Route LVDS signals as differential pairs (excluding the five single-ended support signals), with a 100-Ω differential impedance and a 55-Ω, single-ended impedance. Ideally, a LVDS pair is routed on a single layer adjacent to a ground plane. LVDS pairs should not cross plane splits. Keep layer transitions to a minimum. Reference LVDS pairs to a power plane if necessary. The power plane should be well-bypassed.

Length-matching between the two lines that make up an LVDS pair (“intra-pair”) and between different

LVDS pairs (“inter-pair”) is required. Intra-pair matching is tighter than the inter-pair matching.

All LVDS pairs should have the same environment, including the same reference plane and the same number of vias.

８６

2.10.3. LVDS Trace Length Guidelines

Figure 21

: Topology for LVDS

Reference Plane

Spacing from edge of plane

Carrier Board Via Usage

Notes:

Table 29:

LVDS Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Signal length to the LVDS connector available for the COM

Express Carrier Board

Spacing between pair to pairs

(inter-pair) (s)

Spacing between differential pairs and high-speed periodic signals

Spacing between differential pairs and low-speed non periodic signals

LA

LB

Max length of LA+LB

Length matching

Main Route Guidelines

LVDS

100 Ω ±10%

50Ω ±10%

6.75”

Min. 20 mils

Min. 20 mils

Min. 20 mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

ASAP

Differential pairs (intra-pair): Max.

±2.5 mils

Clock and data pairs (intra-pair): Max.

±5 mils data pairs (inter-pair) : Max.

±5 mils

GND referencing preferred

Min. 40mils

Max. of 2 vias per line.

Notes

８７

2.11. Embedded DisplayPort (eDP) *SOM-6898 is Option function

Embedded DisplayPort (eDP) is a digital display interface standard produced by the Video Electronics

Standards Association (VESA) for digital interconnect of Audio and Video.

Embedded DisplayPort defines a standardized display panel interface for internal connections; e.g., graphics interfaces to notebook display panels. It supports advanced power-saving features including seamless refresh rate switching, display panel and backlight control protocol that works through the AUX channel, and Panel Self-Refresh (PSR) feature developed to save system power and further extend battery life in portable PC systems. PSR mode allows the GPU to enter power saving states in between frame updates by including framebuffer memory in the display panel controller.

Embedded DisplayPort is intended to replace LVDS as the interface to flat panel displays integrated into a product. Unlike DisplayPort, embedded DisplayPort does not define a specific connector or pin-out.

The COM Express specification shares the LVDS pins with embedded DisplayPort.

2.11.1 eDP Signal Definitions

eDP is available in Type 6 and type 10 pin-outs as an alternative to the LVDS A channel. The Module can provide LVDS only, eDP only or Dual-Mode for both interfaces. Please refer to relevant Module documentation for the supported interfaces.

Table 30

: eDP Signal Definitions

Signal eDP_TX0+ eDP_TX0- eDP_TX1+ eDP_TX1- eDP_TX2+ eDP_TX2-

Pin#

A75

A76

A73

A74

A71

A72

Description eDP lane 0, TX +/-

Carrier Board:

Connect AC Coupling Capacitors 75~200 nF near eDP connector.

N/C if not used eDP lane 1, TX +/-

Carrier Board:

Connect AC Coupling Capacitors 75~200 nF near eDP connector.

N/C if not used eDP lane 2, TX +/-

Carrier Board:

Connect AC Coupling Capacitors 75~200 nF near eDP connector.

N/C if not used

I/O Note

O PCIe 1

O PCIe 1

O PCIe 1

８８

Signal eDP_TX3+ eDP_TX3- eDP_VDD_EN eDP_BLKT_EN

Pin# Description

A81 eDP lane 3, TX +/-

A82 Carrier Board:

Connect AC Coupling Capacitors 75~200 nF near eDP connector.

I/O

N/C if not used

A77 eDP power enable

Carrier Board:

Connect to enable control of eDP panel power circuit.

N/C if not used

O CMOS

Note

O PCIe 1

1

B79 eDP backlight enable

Carrier Board:

Connect to enable control of eDP panel backlight power circuit.

N/C if not used

O CMOS

1 eDP_BLKT_CTRL B83 EDP backlight brightness control

Carrier Board:

Connect to brightness control of eDP panel backlight eDP_AUX+ eDP_AUX-

A83

A84 power circuit.

N/C if not used eDP auxiliary lane +/-

Carrier Board:

Connect to device or eDP connector.

N/C if not used.

O CMOS

I/O PCIe

1

1 eDP_HPD A87 Detection of Hot Plug / Unplug and notification of the link layer

Carrier Board:

Connector to device or eDP connector HP pin.

I CMOS

1

Notes:

1. SOM-6898 default is not support eDP, it is option function. If customers want to use eDP function, please contact Advantech.

８９

2.11.2. eDP Trace Length Guidelines

Figure 22

: Topology for eDP

Table 31

: DisplayPort Connector / Device Down Trace Length Guidelines

Parameter

Signal Group

Differential Impedance Target

Single End

Isolation to equivalent pairs

Isolation to other signal groups

LA

LB

Max length of LA+LB

Main Route Guidelines eDP

85 Ω ±10%

50Ω ±10%

20 mils (MS) and 15 mils (DS)

20 mils (MS) and 15 mils (DS)

SOM-6898 is not support.

Carrier Board Length eDP differential pairs to eDP connector:

2

2

2

2

2

2

2

Notes

2

Length matching

AUX channel:

Differential pairs (intra-pair): Max. ±5 mils

For each channel, match the lengths of the differential pairs (Inter-Pair) to be within a 1-inch window (max length – min length < 1 inch (2.54 cm)) .

GND referencing preferred.

2

Reference Plane 2

Min 40-mil trace edge-to-major plane edge spacing.

Max. 2 vias. Carrier Board Via Usage

AC coupling Min = 75 nF

Max = 200 nF

2

1, 2

Notes:

1. AC caps are recommended to be placed close to device side (avoid placing AC cpas on mid-bus).

2. SOM-6898 default is not support eDP, it is option function. If customers want to use eDP function, please contact Advantech.

９０

2.12. VGA

2.12.1. VGA Signal Definitions

The interface consists of three analog color signals (Red, Green, Blue); digital Horizontal and Vertical

Sync signals as well as a dedicated I2C bus for Display Data Control (DDC) implementation for monitor capability identification. The corresponding signals can be found on the COM Express Module connector row B.

Table 32: VGA Signal Definitions

Signal

VGA_RED

Pin#

B89

Description

Red component of analog DAC monitor output, designed to drive a 37.5Ω equivalent load.

Carrier Board:

Connect to

1. 150Ω±1% resistor to GND

2. 2-pole filter( 10 pF,bead 47 Ω @100MHz and 22 pF )

3. ESD diode protection connected to 3.3V or 5V. to

VGA Conn Pin 1 RED

N/C if not used

VGA_GRN

VGA_BLU

B91

B92

Green component of analog DAC monitor output, designed to drive a 37.5Ω equivalent load.

Carrier Board:

Connect to

1. 150Ω±1% resistor to GND

2. 2-pole filter( 10 pF,bead 47 Ω @100MHz and 22 pF )

3. ESD diode protection connected to 3.3V or 5V. to

VGA Conn Pin 2 GREEN

N/C if not used

Blue component of analog DAC monitor output, designed to drive a 37.5Ω equivalent load.

Carrier Board:

Connect to

1. 150Ω±1% resistor to GND

2. 2-pole filter( 10 pF,bead 47 Ω @100MHz and 22 pF )

3. ESD diode protection connected to 3.3V or 5V. to

VGA Conn Pin 3 BLUE

N/C if not used

I/O

O Analog

Note

O Analog

O Analog

９１

Signal Pin# Description

VGA_HSYNC B93 Horizontal sync output to VGA monitor.

Carrier Board:

Connect

1. Bead 150~220Ω@100MHz in series

2. Bypass 22pF to GND.

3. ESD diode protection connected to 3.3V or 5V. to VGA Conn Pin 13 Hsync

N/C if not used

VGA_VSYNC B94 Vertical sync output to VGA monitor.

Carrier Board:

Connect

1. Bead 150~220Ω@100MHz in series

2. Bypass 22pF to GND.

3. ESD diode protection connected to 3.3V or 5V. to VGA Conn Pin 14 Vsync

N/C if not used

VGA_I2C_CK B95 DDC clock line (I2C port dedicated to identify VGA monitor capabilities).

Carrier Board:

Connect to VGA Conn Pin 15 SCL with ESD diode to 5V near connector

N/C if not used

VGA_I2C_DAT B96 DDC data line.

Carrier Board:

Connect to VGA Conn Pin 12 SDA with ESD diode to 5V near connector.

N/C if not use

I/O

O 3.3V

CMOS

Note

O 3.3V

CMOS

O 3.3V

CMOS

Level shifter might be necessary

I/O 3.3V

CMOS

Level shifter might be necessary

９２

2.12.2. VGA Routing Guidelines

2.12.2.1. RGB Analog Signals

The RGB signal interface of the COM Express Module consists of three identical 8-bit digital-toanalog converter (DAC) channels. One each for the red, green, and blue components of the monitor signal.

Each of these channels should have a 150Ω ±1% pull-down resistor connected from the DAC output to the Carrier Board ground. A second 150Ω ±1% termination resistor exists on the COM Express Module itself. An additional 75Ω termination resistor exists within the monitor for each analog DAC output signal.

Since the DAC runs at speeds up to 350MHz, special attention should be paid to signal integrity and EMI.

There should be a PI-filter placed on each RGB signal that is used to reduce highfrequency noise and

EMI. The PI-filter consists of two 10pF capacitors with a 120Ω @ 100MHz ferrite bead between them. It is recommended to place the PI-filters and the terminating resistors as close as possible to the standard

VGA connector.

2.12.2.2. HSYNC and VSYNC Signals

The horizontal and vertical sync signals 'VGA_HSYNC' and 'VGA_VSYNC' provided by the COM

Express Module are 3.3V tolerant outputs. Since VGA monitors may drive the monitor sync signals with

5V tolerance, it is necessary to implement high impedance unidirectional buffers. These buffers prevent potential electrical over-stress of the Module and avoid that VGA monitors may attempt to drive the monitor sync signals back to the Module. For optimal ESD protection, additional low capacitance clamp diodes should be implemented on the monitor sync signals. They should be placed between the 5V power plane and ground and as close as possible to the VGA connector.

2.12.2.3. DDC Interface

COM Express provides a dedicated I2C bus for the VGA interface. It corresponds to the VESA™ defined DDC interface that is used to read out the CRT monitor specific Extended Display Identification

Data (EDID™). The appropriate signals 'VGA_I2C_DAT' and 'VGA_I2C_CK' of the COM Express

Module are supposed to be 3.3V tolerant. Since most VGA monitors drive the internal EDID™ EEPROM with a supply voltage of 5V, the DDC interface on the VGA connector must also be sourced with 5V. This can be accomplished by placing a 100kΩ pull-up resistors between the 5V power plane and each DDC interface line. Level shifters for the DDC interface signals are required between the COM Express

Module signal side and the signals on the standard VGA connector on the Carrier Board.

Additional Schottky diodes must be placed between 5V and the pull-up resistors of the DDC signals to avoid backward current leakage during Suspend operation of the Module.

2.12.2.4. ESD Protection/EMI

All VGA signals need ESD protection and EMI filters.

９３

2.12.3. VGA Trace Length Guidelines

Figure 23

: Topology for VGA

Table 33

: VGA Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within CRT

DAC Signal Group

Spacing to Other Signal Group

LA

LB

Max length of LA+LB

Length matching

Main Route Guidelines

VGA

50Ω ±10%

Min. 15mils

Min. 20mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

15.1”

1. Match the trace lengths within R, G, B to ±200 mils.

2. Match the trace lengths of CRT SYNC signals with

CRT DAC signals to ±1000 mils

Reference Plane GND referencing preferred.

Min 20-mil trace edge-to-major plane edge spacing.

Notes:

1. Video filter must be near VGA CONN.

Notes

９４

2.13. Digital Audio Interfaces

The COM Express Specification allocates seven pins on the A-B connector to support digital AC’97 and

HD interfaces to audio Codecs on the Carrier Board. The pins are available on all Module types.

High-definition (HD) audio uses the same digital-signal interface as AC ’97 audio. Codecs for AC ’97 and HD Audio are different and not compatible. Current Module chipsets support HD Audio only.

2.13.1. Audio Codec Signal Descriptions

Table 34

: Audio Codec Signal Descriptions

Signal Pin# Description

AC/HDA_RST# A30 CODEC Reset.

Carrier Board:

AC97 - Connect 0 Ω in series to CODEC pin 11 RESET#

HDA - Connect 0 Ω in series to CODEC pin 11 RESET#

N/C if not used

AC/HDA_SYNC A29 Serial Sample Rate Synchronization.

Carrier Board:

AC97 - Connect 0 Ω in series to CODEC pin 10 SYNC

HDA - Connect 0 Ω in series to CODEC pin 10 SYNC

N/C if not used

AC/HDA_BITCLK A32 24 MHz Serial Bit Clock for HDA CODEC.

Carrier Board:

AC97 - Connect 33-47 Ω in series to CODEC pin 6

BIT_CLK

AC/HDA_SDIN0 B30

HDA - Module has integrated series resistor. Connect 0 Ω in series to CODEC pin 6 BIT_CLK

N/C if not used

AC/HDA_SDOUT A33 Audio Serial Data Output Stream.

Carrier Board:

AC97 - Connect 33-47 Ω in series to CODEC pin 5

SDATA_OUT

HDA - Connect 33-47 Ω in series and PD 10KΩ(NL) to

CODEC pin 5 SDATA_OUT

N/C if not used

Audio Serial Data Input Stream from CODEC[0:2].

AC/HDA_SDIN1

AC/HDA_SDIN2

B29

B28

Carrier Board:

AC97 - Connect 33-47 Ω in series to CODEC pin 8

SDATA_IN

HDA - Connect 33-47 Ω in series and PD 10KΩ(NL) to

CODEC pin 8 SDATA_IN

N/C if not used

I/O

O 3.3V

Suspend

CMOS

O 3.3V

CMOS

O 3.3V

CMOS

O 3.3V

CMOS

I 3.3V

Suspend

CMOS

Note

９５

The codec on a COM Express Carrier Board is usually connected as the primary codec with the codec

ID 00 using the data input line 'AC/HDA_SDIN0'. Up to two additional codecs with ID 01 and ID 10 can be connected to the COM Express Module by using the other designated signals 'AC/HDA_SDIN1' and

'AC/HDA_SDIN2'.

Connect the primary audio codec to the serial data input signal 'AC/HDA_SDIN0' and ensure that the corresponding bit clock input signal 'AC/HDA_BITCLK' is connected to the AC'97/HDA interface of the

COM Express Module.

Clocking over the signal 'AC/HDA_BITCLK' is derived from a 24.576 MHz crystal or crystal oscillator provided by the primary codec in AC97 implementations. The crystal is not required in HDA implementations. This clock also drives the second and the third audio codec if more than one codec is used in the application. For crystal or crystal oscillator requirements, refer to the datasheet of the primary codec.

９６

2.13.2. Audio Routing Guidelines

The implementation of proper component placement and routing techniques will help to ensure that the maximum performance available from the codec is achieved. Routing techniques that should be observed include properly isolating the codec, associated audio circuitry, analog power supplies and analog ground planes from the rest of the Carrier Board. This includes split planes and the proper routing of signals not associated with the audio section.

The following is a list of basic recommendations:

Traces must be routed with a target impedance of 50Ω with an allowed tolerance of ±15%.

Ground return paths for the analog signals must be given special consideration.

Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines.

Locate the analog and digital signals as far as possible from each other.

Partition the Carrier Board with all analog components grouped together in one area and all digital components in another.

Keep digital signal traces, especially the clock, as far as possible from the analog input and voltage reference pins.

Provide separate analog and digital ground planes with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane.

The split between the planes must be a minimum of 0.05 inch wide.

Route analog power and signal traces over the analog ground plane.

Route digital power and signal traces over the digital ground plane.

Position the bypassing and decoupling capacitors close to the IC pins with wide traces to reduce impedance.

Place the crystal or oscillator (depending on the codec used) as close as possible to the codec.

(HDA implementations generally do not require a crystal at the codec)

Do not completely isolate the analog/audio ground plane from the rest of the Carrier Board ground plane.

Provide a single point (0.25 inch to 0.5 inch wide) where the analog/isolated ground plane connects to the main ground plane. The split between the planes must be a minimum of 0.05 inch wide.

Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main Carrier Board ground. That is, no signal should cross the split/gap between the ground planes, because this would cause a ground loop, which in turn would greatly increase EMI emissions and degrade the analog and digital signal quality.

９７

2.13.3. Audio Trace Length Guidelines

Figure 24

: Topology for Audio

Notes:

Table 35

: Audio Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within

Audio Signal Group

Spacing to Other Signal Group

LA

LB

Max length of LA+LB

Length matching

Reference Plane

Main Route Guidelines

Audio

50Ω ±15%

Min. 15mils

Min. 20mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

14.5”

Data to Clock must be matched within 500mils

GND referencing preferred.

Min 20-mil trace edge-to-major plane edge spacing.

Notes

９８

2.14. LPC Bus – Low Pin Count Interface

Since COM Express is designed to be a legacy free standard for embedded Modules, it does not support legacy functionality on the Module, such as PS/2 keyboard/mouse, serial ports, and parallel ports.

Instead, it provides an LPC interface that can be used to add peripheral devices to the Carrier Board design. COM Express also provides interface pins necessary for (optional) Carrier Board resident PS keyboard controllers.

The Low Pin Count Interface was defined by the Intel○ Corporation to facilitate the industry's transition toward legacy free systems. It allows the integration of low-bandwidth legacy I/O components within the system, which are typically provided by a Super I/O controller. Furthermore, it can be used to interface

Firmware Hubs, Trusted Platform Module (TPM) devices, general-purpose inputs and outputs, and

Embedded Controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized data interface, which uses a 24MHzz LPC bus clock. It is straightforward to develop PLDs or FPGAs that interface to the LPC bus.

For more information about LPC bus, refer to the 'IntelR Low Pin Count Interface Specification Revision

1.1'.

2.14.1. LPC Signal Definition

Table 36

: LPC Interface Signal Definition

Signal Pin# Description

LPC_SERIRQ A50 LPC serialized IRQ.

Carrier Board:

Connect to

LPC - SERIRQ

N/C if not use

LPC_FRAME# B3 LPC frame indicates start of a new cycle or termination of a broken cycle.

Carrier Board:

LPC - LFRAME#

FWH - Pin 23 LFRAME#

N/C if not used

I/O

I/O 3.3V

CMOS

O 3.3V

CMOS

Note

９９

Signal

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_DRQ0#

LPC_DRQ1#

LPC_CLK

Pin# Description

B4 LPC multiplexed command, address and data.

B5

B6

B7

Carrier Board:

Connect to

LPC - LAD0 , LAD1, LAD2, LAD3

B8

B9

FWH - Pin 13 LAD0, Pin 14 LAD1, Pin 15

LAD2, Pin 17 LAD3

N/C if not used

LPC encoded DMA/Bus master request.

Carrier Board:

Connect to

LPC - LDRQ0#, LDRQ1#

N/C if not used

B10 LPC clock output 24MHzz.

Carrier Board:

Connect to

LPC - LCLK

FWH - Pin 31 LCLK

N/C if not used

I/O

I/O 3.3V

CMOS

I 3.3V

CMOS

O 3.3V

CMOS

Note

Not all Modules support LPC

DMA. Contact your vendor for information.

Note

Implementing external LPC devices on the COM Express Carrier Board always requires customization of the COM Express Module's BIOS in order to support basic initialization for those LPC devices. Otherwise the functionality of the LPC devices will not be supported by a Plug&Play or ACPI capable system.

2.14.2. LPC Routing Guidelines

2.14.2.1 General Signals

LPC signals are similar to PCI signals and may be treated similarly. Route the LPC bus as 50 Ω, single-ended signals. The bus may be referenced to ground (preferred), or to a well-bypassed power plane or a combination of the two. Point-to-point (daisy-chain) routing is preferred, although stubs up to

1.5 inches may be acceptable. Length-matching among LPC_AD[3:0], LPC_FRAME# are needed

１００

2.14.2.2 Bus Clock Routing

Route the LPC clock as a single-ended, 50 Ω trace with generous clearance to other traces and to itself.

A continuous ground-plane reference is recommended. Routing the clock on a single ground referenced internal layer is preferred to reduce EMI.

The LPC clock implementation should follow the routing guidelines for the PCI clock defined in the COM

Express specification and the 'PCI Local Bus Specification Revision 2.3'.

2.14.3. LPC Trace Length Guidelines

Figure 25

: Topology for LPC

Table 37

: LPC Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within LPC

Signal Group

Spacing to Other Signal Group

LA

LB

Max length of LA+LB

Length matching between single ended signals

Length matching between clock signals

Reference Plane

Via Usage

Notes:

Main Route Guidelines

LPC

50Ω ±15%

Min. 15mils

Min. 15mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

ASAP

Max. 200mils

Max. 200mils

GND referencing preferred.

Try to minimize number of vias

１０１

Notes

2.15. SPI – Serial Peripheral Interface Bus

The SPI interface is defined in this specification to service as an off-module option for BIOS storage. The

SPI interface replaces the LPC Firmware Hub interface, which is now considered a legacy interface for firmware storage (LPC does continue to be used for SuperIO connectivity).

Many current chipsets only specify SPI for BIOS/Firmware storage usage, so the COM.0 specification is limited to that connectivity use-case to enable maximum compatibility across Modules and silicon platforms. Additional features, such as SPI-based Trusted Platform Module support might be added to a given carrier design, but compatibility is not guaranteed across Modules.

2.15.1. SPI Signal Definition

Table 38

: SPI Interface Signal Definition

Signal

SPI_CS#

Pin# Description

B97 Chip select for Carrier Board SPI – may be sourced from chipset SPI0 or SPI1

Carrier Board:

Connect to SPI flash pin 1 Chip Select

N/C if not used

I/O

O CMOS –

3.3V Suspend

SPI_MISO A92 Data in to Module from Carrier SPI

Carrier Board:

Connect 15~33Ω in series to SPI flash pin 2 Serial

Output

N/C if not used

SPI_MOSI A95 Data out from Module to Carrier SPI

Carrier Board:

Connect 33~47 Ω in series to SPI flash pin 5 Serial

Input

N/C if not used

SPI_CLK

I CMOS –

3.3V Suspend

O CMOS –

3.3V Suspend

A94 Clock from Module to Carrier SPI

Carrier Board:

Connect 33~47 Ω in series to SPI flash pin 6 Clock

O CMOS –

3.3V Suspend

N/C if not used

Note

１０２

Signal Pin# Description

SPI_POWER A91 Power supply for Carrier Board SPI – sourced from

Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.

Carriers shall use less than 100mA of SPI_POWER.

SPI_POWER shall only be used to power SPI devices on the Carrier.

Carrier Board:

Connect to SPI flash pin 8 VDD

N/C if not used

BIOS_DIS0# A34 Selection strap to determine the BIOS boot device.

The Carrier should only float these or pull them low, please refer to for strapping options of BIOS disable signals.

Carrier Board:

1 - N/C

0 - PD 1K to GND

BIOS options are shown in Table "Effect of the BIOS disable signals"

I/O

O – 3.3V

Suspend

I CMOS

Note

BIOS_DIS1# B88 Selection strap to determine the BIOS boot device.

The Carrier should only float these or pull them low, please refer to Table X : Effect of the BIOS disable signals on page 119 below for strapping options of

BIOS disable signals.

I CMOS

Carrier Board:

1 - N/C

0 - PD 1K to GND

BIOS options are shown in Table "Effect of the BIOS disable signals"

The signals with the “SPI_” prefix names are used to connect directly to the regarding SPI device.

SPI_CS# is the chip select signal and is usually sourced from the Module's chipset SPI0 or SPI1 signal.

SPI_MISO and SPI_MOSI are the input and output signals and SPI_CLK offers the clock from the

Module to the carrier's device. The SPI_POWER pin can be used to power the SPI devices and it should use less than 100mA in total. The signal is helpful to simplify the SPI schematic, because the Module's

SPI power domain can be either in power state S0 or in S5.

BIOS_DIS[0:1]# signals are used to determine the boot device according to Table X : Effect of the BIOS disable signals below. BIOS_DIS0# (formerly known as BIOS_DISABLE# in COM.0 R1.0) is used to

１０３

disable the on-module BIOS device and enable the LPC firmware hub. For SPI BIOS flash device usage the signal BIOS_DIS1# should be activated to disable the on-module BIOS device and enable the BIOS flash chip on the carrier.

Table 39

: Effect of the BIOS disable signals

0

0

1

1

BIOS_DIS1# BIOS_DIS0# Chipset

SPI CS1#

1

0

1

0

Destination

Module

Module

Module

Carrier

2.15.2. SPI Routing Guidelines

NA

2.15.3. SPI Trace Length Guidelines

Chipset

SPI CS0#

Destination

Module

Module

Carrier

Module

Carrier

SPI_CS#

High

High

SPI0

SPI1

SPI

Descriptor

BIOS Entry Ref

Line

Module

Module

Carrier

Module

SPI0/SPI1 0

Carrier FWH 1

SPI0/SPI1

SPI0/SPI1

2

3

Figure 26

: Topology for SPI

Table 40

: SPI Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within SPI

Signal Group

Spacing to Other Signal Group

LA

LB

Max length of LA+LB

DATA to CLK Maximum Pin to Pin

Length Mismatch

Via Usage

Notes:

Main Route Guidelines

SPI

50Ω ±15%

Min. 10mils

Min. 15mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

6.5”

Max. 500mils

Try to minimize number of vias

１０４

Notes

2.16. General Purpose I2C Bus Interface

The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus originally defined by Philips. The bus is used for low-speed (up to 400kbps) communication between system ICs. The bus is often used to access small serial EEPROM memories and to set up IC registers. The COM Express Specification defines several I2C interfaces that are brought to the Module connector for use on the Carrier. Some of these interfaces are for very specific functions (VGA, LVDS, and DDIX), one interface is the SMBus used primarily for management and one other interface is a general purpose I2C interface. Since COM.0

Rev. 2.0 this interface should support multi-master operation. This capability will allow a Carrier to read an optional Module EEPROM before powering up the Module.

Revision 1.0 of the specification placed the I2C interface on the non-standby power domain. With this connection, the I2C interface can only be used when the Module is powered on. Since the I2C interface is used to connect to an optional Carrier EEPROM and since it is desirable to allow a Module based board controller access to the optional Carrier EEPROM before the Module is powered on, revision 2.0 of this specification changes the power domain of the I2C interface to standby-power allowing access during power down and suspend states. There is a possible leakage issue that can arise when using a

R2.0 Module with a R1.0 Carrier that supports I2C devices. The R1.0 Carrier will power any I2C devices from the non-standby power rail. A R2.0 Module will pull-up the I2C clock and data lines to the standby-rail through a 2.2K resistor. The difference in the power domains on the Module and Carrier can provide a leakage path from the standby power rail to the non-standby power rail.

Vendor interoperability is given via EAPI – Embedded Application Programming Interface, which allows and easier interoperability of COM Express Modules.

2.16.1. Signal Definitions

The general purpose I2C Interface is powered from 3.3V suspend rail. The I2C_DAT is an open collector line with a pull-up resistor located on the Module. The I2C_CK has a pull-up resistor located on the

Module. The Carrier should not contain pull-up resistors on the I2C_DAT and I2C_CK signals. Carrier based devices should be powered from 3.3V suspend voltage. The use of main power line for a Carrier

I2C device will require a bus isolator to prevent leakage to other I2C devices on 3.3V power.

At this time, there is no allocation of I2C addresses between the Module and Carrier. Carrier designers will need to consult with Module providers for address ranges that can be used on the Carrier.

１０５

Table 41

: General Purpose I2C Interface Signal Descriptions

Signal Pin# Description

I2C_CK B33 General Purpose I2C Clock output

Carrier Board:

3.3VSB I2C device - Connect to SCL of I2C device.

3.3V I2C device - Connect 3.3V isolation circuit controlled by COME pin B24 PWR_OK to SCL of I2C device.

5VSB I2C device - Connect 5VSB Level

Shifter to SCL of I2C device.

5V I2C device – Connect an 5V isolation circuit controlled by COME pin B24 PWR_OK to SCL of I2C device.

N/C if not used

I2C_DAT B34 General Purpose I2C data I/O line.

Carrier Board:

3.3VSB I2C device - Connect to SDA of I2C device.

3.3V I2C device - Connect 3.3V isolation circuit controlled by COME pin B24 PWR_OK to SDA of I2C device

5VSB I2C device - Connect 5VSB Level

Shifter to SDA of I2C device

5V I2C device - Connect an 5V isolation circuit controlled by COME pin B24 PWR_OK to SDA of I2C device

N/C if not used

2.16.2. I2C Routing Guidelines

NA

I/O

I/O OD

CMOS

I/O OD

CMOS

Pwr Rail Note

3.3V

Suspend

3.3V

Suspend

１０６

2.16.3. I2C Trace Length Guidelines

Figure 27

: Topology for I2C

Table 42

: I2C Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within SPI

Signal Group

Spacing to Other Signal Group

LA

LB

Main Route Guidelines

I2C

50Ω ±15%

Min. 10mils

Min. 15mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

Notes

Max length of LA+LB

Length Mismatch

Via Usage

Notes:

ASAP

NA

Try to minimize number of vias

2.16.4. Connectivity Considerations

The maximum amount of capacitance allowed on the Carrier General Purpose I2C bus lines (I2C_DAT,

I2C_CK) is specified by Advantech’s Module. The Carrier designer is responsible for ensuring that the maximum amount of capacitance is not exceeded and the rise/fall times of the signals meet the I2C bus specification. As a general guideline, an IC input has 8pF of capacitance, and a PCB trace has 3.8pF per inch of trace length.

１０７

2.17. System Management Bus (SMBus)

The SMBus is primarily used as an interface to manage peripherals such as serial presence detect (SPD) on RAM, thermal sensors, PCI/PCIe devices, smart battery, etc. The devices that can connect to the

SMBus can be located on the Module and Carrier. Designers need to take note of several implementation issues to ensure reliable SMBus interface operation. The SMBus is similar to I2C. I2C devices have the potential to lock up the data line while sending information and require a power cycle to clear the fault condition. SMBus devices contain a timeout to monitor for and correct this condition.

Designers are urged to use SMBus devices when possible over standard I2C devices. COM Express

Modules are required to power SMBus devices from Early Power in order to have control during system states S0-S5. The devices on the Carrier Board using the SMBus are normally powered by the 3.3V main power. To avoid current leakage between the main power of the Carrier Board and the Suspend power of the Module, the SMBus on the Carrier Board must be separated by a bus switch from the

SMBus of the Module. However, if the Carrier Board also uses Suspend powered SMBus devices that are designed to operate during system states S3-S5, then these devices must be connected to the

Suspend powered side of the SMBus, i. e. between the COM Express Module and the bus switch. Since the SMBus is used by the Module and Carrier, care must be taken to ensure that Carrier based devices do not overlap the address space of Module based devices. Typical Module located SMBus devices and their addresses include memory SPD (serial presence detect 1010 000x, 1010 001x), programmable clock synthesizes (1101 001x), clock buffers (1101 110x), thermal sensors (1001 000x), and management controllers (vendor defined address). Contact Advantech for information on the SMBus addresses used.

１０８

2.17.1. SMB Signal Definitions

Table 43

: SMB Signal Definitions

Signal

SMB_CK

SMB_DAT

Pin# Description

B13 System Management Bus bidirectional clock line

Carrier Board:

3.3VSB SMBus device - Connect to

SMBCLK of SMBus device.

3.3V SMBus device - Connect 3.3V isolation circuit controlled by COME pin B24 PWR_OK to SMBCLK of SMBus device.

5VSB SMBus device - Connect 5V Level

Shifter to SMBCLK of SMBus device.

5V SMBus device - Connect 5V isolation circuit controlled by COME pin B24 PWR_OK to SMBCLK of SMBus device

N/C if not used.

B14 System Management bidirectional data line.

Carrier Board:

3.3VSB SMBus device - Connect to

SMBDAT of SMBus device.

3.3V SMBus device - Connect 3.3V isolation circuit controlled by COME pin B24 PWR_OK to SMBDAT of SMBus device.

5VSB SMBus device - Connect 5V Level

Shifter to SMBDAT of SMBus device.

5V SMBus device - Connect 5V isolation circuit controlled by COME pin B24 PWR_OK to SMBDAT of SMBus device

N/C if not used.

SMB_ALERT# B15 System Management Bus Alert

Carrier Board:

Connect to SMBALERT# of SMBus device.

N/C if not used.

Note:

I/O

I/O OD

CMOS

I/O OD

CMOS

I

CMOS

Pwr Rail Note

3.3V

Suspend rail

3.3V

Suspend rail

3.3V

Suspend

Rail

１０９

2.17.2. SMB Routing Guidelines

The SMBus should be connected to all or none of the PCIe/PCI devices and slots. A general recommendation is to not connect these devices to the SMBus.

The maximum load of SMBus lines is limited to 3 external devices. Please contact Advantech if more devices are required.

Do not connect Non-Suspend powered devices to the SMBus unless a bus switch is used to prevent back feeding of voltage from the Suspend rail to other supplies.

Contact Advantech for a list of SMBus addresses used on the Module. Do not use the same address for

Carrier located devices.

2.17.3. SMB Trace Length Guidelines

Figure 28

: Topology for SMB

Table 44

: SMB Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within SPI

Signal Group

Spacing to Other Signal Group

LA

LB

Max length of LA+LB

Length Mismatch

Via Usage

Notes:

Main Route Guidelines

SMB

50Ω ±15%

Min. 10mils

Min. 15mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

ASAP

NA

Try to minimize number of vias

１１０

Notes

2.18. General Purpose Serial Interface

Advantech provides two serial ports on Type 10 and Type 6 COM Express Modules.

2.18.1. Serial interface Signal Definitions

Table 45

: Serial interface Signal Definitions

Signal

SER0_TX

SER0_RX

SER1_TX

SER1_RX

Pin# Description

A98 Transmit Line for Serial Port 0

Carrier Board: connect to

Device - TXD

COM DB-9 port - TxIN of Serial Transceiver and

TxOUT to DB-9 pin 3 TXD

N/C if not used.

A99 Receive Line for Serial Port 0

Carrier Board:

Connect to

Device - RXD

COM DB-9 port - TxOUT of Serial Transceiver and TxIN to DB-9 pin 2 RXD

N/C if not used

A101 Transmit Line for Serial Port 1

Carrier Board: connect to

Device - TXD

COM DB-9 port - TxIN of Serial Transceiver and

TxOUT to DB-9 pin 3 TXD

N/C if not used.

A102 Receive Line for Serial Port 1

Carrier Board:

Connect to

Device - RXD

COM DB-9 port - TxOUT of Serial Transceiver and TxIN to DB-9 pin 2 RXD

N/C if not used

I/O

O CMOS

I CMOS

O CMOS

I CMOS

Note:

Note

１１１

2.18.2. Serial interface Routing Guidelines

NA

2.18.3. Serial interface Trace Length Guidelines

Figure 29

: Topology for Serial interface

Table 46

: Serial interface Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within SPI

Signal Group

Spacing to Other Signal Group

LA

LB

Max length of LA+LB

Length Mismatch

Via Usage

Notes:

Main Route Guidelines

Serial interface

50Ω ±15%

Min. 10mils

Min. 15mils

Please see the SOM-6898 Layout Checklist

Carrier Board Length

NA

NA

Try to minimize number of vias

１１２

Notes

2.19. CAN Interface *SOM-6898 is not support CAN Interface.

CAN bus is a vehicle bus standard designed to allow controllers and devices to communicate with each other without a host computer. CAN bus is a message-based protocol, designed specifically for automotive applications but now also used in other areas such as industrial automation and medical equipment.

Development of CAN bus started originally in 1983. The protocol was officially released in 1986 at the

Society of Automotive Engineers (SAE) congress in Detroit, Michigan. The first CAN controller chips, produced by Intel and Philips, came on the market in 1987. In 1991 the CAN 2.0 specification was published.

Since 2008 CAN bus has been mandatory in any US vehicle in the OBD-II car diagnostic port. It is also used extensively in industrial automation.

2.19.1. CAN interface Signal Definitions

Table 47

: CAN interface Signal Definitions

Signal

CAN_TX

CAN_RX

Pin# Description

A101 Transmit Line for CAN

Carrier Board:

Check your CAN transceiver application notes.

A102 Receive Line for CAN

Carrier Board:

Check your CAN transceiver application notes.

I/O

O CMOS

I CMOS

Note

1

1

Note:

1. SOM-6898 is not support CAN Interface.

2.19.2. CAN interface Routing Guidelines

It should be routed as a differential pair signal with 120 Ohm differential impedance. The end points of

CAN bus should be terminated with 120 Ohms or with 60 Ohms from the CAN_H line and 60 Ohms from the CAN_L line to the CAN Bus reference voltage. Check your CAN transceiver application notes for further details on termination.

１１３

2.19.3. CAN interface Trace Length Guidelines

Figure 30

: Topology for CAN interface

Table 48

: CAN interface Trace Length Guidelines

Parameter

Signal Group

Single End

Nominal Trace Space within SPI

Signal Group

Main Route Guidelines

CAN interface

NA

Min. 10mils

Spacing to Other Signal Group

LA

LB

Max length of LA+LB

Length Mismatch

Min. 15mils

SOM-6898 is not support CAN Interface

Carrier Board Length

NA

NA

Via Usage Try to minimize number of vias

Notes:

1. SOM-6898 is not support CAN Interface

１１４

Notes

1

2.20. Miscellaneous Signals

2.20.1. Miscellaneous Signals

Table 49

: Miscellaneous Signal Definitions

Signal

TYPE0#

TYPE1#

TYPE2#

TYPE10#

SPKR

Pin# Description

C54

C57

D57

The Type pins indicate the COM Express pin-out type of the Module. To indicate the

Module's pin-out type, the pins are either not connected or strapped to ground on the

Module.

The Carrier Board has to implement additional logic, which prevents the system to switch power on, if a Module with an incompatible pin-out type is detected.

A97 Indicates to the Carrier Board that a Type 10

Module is installed. Indicates to the Carrier

Board, that a Rev 1.0/2.0 Module is installed.

TYPE10#

NC Pin-out R2.0

PD Pin-out Type 10 pull down to ground with

47k

12V Pin-out R1.0

B32 Output used to control an external FET or a logic gate to drive an external PC speaker.

Carrier Board:

Connect to Speaker circuit.

N/C if not used

BIOS_DISABLE0# A34 Selection straps to determine the BIOS boot device.

The Carrier should only float these or pull them low.

I/O

O 5V

PDS

O

3.3V

CMOS

BIOS_DISABLE1# B88 Selection straps to determine the BIOS boot device.

The Carrier should only float these or pull them low.

Note

Only Available on T2-T6

I 3.3V

CMOS

I 3.3V

CMOS

See Section

2.15 'SPI –

Serial

Peripheral

Interface

Bus'

See Section

2.15 'SPI –

Serial

Peripheral

Interface

Bus'

１１５

Signal

WDT

KBD_RST# A86 Input signal of the Module used by an external keyboard controller to force a system reset.

KBD_A20GATE A87 Input signal of the Module used by an external

LID# keyboard controller to control the CPU A20 gate line. The A20 gate restricts the memory access to the bottom megabyte of the system. Pulled high on the Module.

A103 LID switch.

Low active signal used by the ACPI operating system for a LID switch.

Carrier Board:

R1.0/R2.x Module both - Connect protection scheme referred to Figure 5-11 of COM.0 R2.0 or Figure 5-13 of COM.0 R2.1 Spec to LID button.

R2.x Module only - Connect to LID button.

N/C if not used.

SLEEP#

Pin# Description

B27 Output indicating that a watchdog time-out event has occurred.

Carrier Board:

Connect to Watchdog trigger input.

N/C if not used

B103 Sleep button.

Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.

Carrier Board:

R1.0/R2.x Module both - Connect protection scheme referred to Figure 5-11 of COM.0 R2.0 or Figure 5-13 of COM.0 R2.1 Spec to Sleep button.

R2.x Module only - Connect to Sleep button.

N/C if not used

I/O

O 3.3V

CMOS

I 3.3V

CMOS

I 3.3V

CMOS

I 3.3V

CMOS

OD

I 3.3V

CMOS

OD

Note

Type 6 is not supported.

Type 6 is not supported.

１１６

GPO0

GPO1

GPO2

GPO3

GPI0

GPI1

GPI2

GPI3

Signal Pin# Description

FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation

(PWM) technique to control the fan’s RPM.

Carrier Board:

R1.0/R2.x Module both - Connect protection scheme referred to Figure 5-11 of COM.0 R2.0 or Figure 5-13 of

COM.0 R2.1 Spec to FAN connector pin 2 PWMOUT via Smart FAN circuit

R2.x Module only - PD 4.7KΩ to GND and connects to

FAN connector pin 2 PWMOUT via Smart FAN circuit

N/C if not used

FAN_TACHIN B102 Fan tachometer input for a fan with a two pulse output.

Carrier Board:

R1.0/R2.x Module both - Connect protection scheme referred to Figure 5-11 of COM.0 R2.0 or Figure 5-13 of

COM.0 R2.1 Spec to FAN connector pin 3 TACHIN via

Smart FAN circuit

R2.x Module only - Connect to FAN connector pin 3

TACHIN via Smart FAN circuit

N/C if not used

TPM_PP

VCC_RTC

B63

A54

A63

A67

A85

A96 Trusted Platform Module (TPM) Physical Presence pin.

Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.

Carrier Board:

Physical Absence - N/C

Physical Presence - PU 1KΩ to 3.3V

N/C if not used

General Purpose Outputs for system specific usage. A93

B54

B57

Carrier Board:

Connect to GPO[3..0]

N/C if not used

General Purpose Input for system specific usage. The signals are pulled up by the Module.

Carrier Board:

Connect to GPI[3..0]

N/C if not used

A47 Real-time clock circuit power input. Nominally +3.0V

I/O

O 3.3V

CMOS

OD

I 3.3V

CMOS

OD

I 3.3V

CMOS

O 3.3V

CMOS

I 3.3V

CMOS

Note:

Note

１１７

2.20.2. Power Management Signals

Table 50

:

Power Management

Signal Definitions

Signal Pin# Description

PWRBTN# B12 Power button low active signal used to wake up the system from S5 state (soft off). This signal is triggered on the falling edge.

Module has integrated PU resistor 10K ohm to 3.3V suspend power and has an internal 50 ms de-bounce on the input.

Carrier Board:

ATX - Connect to Power Button or SIO Power Button output pin (Active low)

AT - N/C

N/C if not used

SYS_RESET#

CB_RESET#

B49 Reset button input. Active low request for Module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.

Carrier Board:

Connect to Reset button

N/C if not used

B50 Reset output signal from Module to Carrier Board.

This signal may be driven low by the Module to reset external components located on the Carrier Board.

Carrier Board:

Connect to reset pin of devices except PCI slots or devices.

N/C if not used.

PWR_OK B24 Power OK status signal generated by the ATX power supply to notify the Module that the DC operating voltages are within the ranges required for proper operation.

Carrier Board:

Connect to power good pin of main power supply ATX -

PW-OK pin 8 of ATX power connector connects 3.3V level shifter to COME PWR_OK.

AT - PG pin P8.1 of AT power connector connects 3.3V level shifter to COME PWR_OK.

Other - PWROK of 12V power generator circuit connects

3.3V level shifter to COME PWR_OK.

N/C is not allowed, if the system is ATX mode.

N/C if not used.

I/O

I 3.3V

Suspend

CMOS

I 3.3V

Suspend

CMOS

O 3.3V

Suspend

CMOS

I 3.3V

CMOS

Note

１１８

Signal

SUS_STAT#

SUS_S3#

SUS_S4#

SUS_S5#

WAKE1#

BATLOW#

Pin# Description

B18 Suspend status signal to indicate that the system will be entering a low power state soon. It can be used by other peripherals on the Carrier Board as an indication that they should go into power-down mode.

Carrier Board:

Connect to LPCPD# of LPC device.

N/C if not used.

A15 S3 Sleep control signal indicating that the system resides in S3 state (Suspend to RAM).

This signal can be used to control the ATX power supply via the 'PS_ON#' signal.

Carrier Board:

Connect to SLP_S3# (Suspend To RAM) of LPC device or

SIO.

N/C if not used.

A18 S4 Sleep control signal indicating that the system resides in S4 state (Suspend to Disk).

Carrier Board:

Connect to SLP_S4# (Suspend To Disk) of LPC device or

SIO.

N/C if not used.

A24 S5 Sleep Control signal indicating that the system resides in S5 State (Soft Off).

Carrier Board:

Connect to SLP_S5# (Soft Off) of LPC device or SIO.

N/C if not used.

B67 General purpose wake-up signal.

Carrier Board:

Connect to PME# of SIO

N/C if not use

A27 Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low. It also can be used to signal some other external power management event.

Carrier Board:

Connect to BATLOW# of Smart Battery.

N/C if not used.

I/O

O 3.3V

Suspend

CMOS

O 3.3V

Suspend

CMOS

O 3.3V

Suspend

CMOS

O 3.3V

Suspend

CMOS

I 3.3V

Suspend

CMOS

I 3.3V

Suspend

CMOS

Note

Note:

１１９

2.20.3. Thermal Interface

Table 51

:

Thermal Management

Signal Definitions

Signal

THRM#

THRMTRIP#

Pin# Description

B35 Thermal Alarm active low signal generated by the external hardware to indicate an over temperature situation. This signal can be used to initiate thermal throttling.

Carrier Board:

Connect to THRM# output of Hardware Monitor.

N/C if not used.

A35 Thermal Trip indicates an overheating condition of the processor. If 'THRMTRIP#' goes active the system immediately transitions to the S5 State (Soft Off).

Carrier Board:

Connect to THERMTRIP# input of devices.

N/C if not used.

Note:

2.20.4. Miscellaneous Signals Routing Guidelines

NA

NA

2.20.5. Miscellaneous Signals Trace Length Guidelines

I/O

I 3.3V

CMOS

O 3.3V

CMOS

Note

１２０

3. Power

3.1. General Power requirements

COM Express calls for the Module to be powered by a single 12V power rail, with a +/-5% tolerance. The

Mini format Modules are specified in COM.0 Rev. 2.1 to support a power input range of 4.75V to 20.0V.

Advantech offer a wide range input even on Compact and Basic Modules. COM Express Modules may consume significant amounts of power – 25 to 50W is common, and higher levels are allowed by the standard. Close attention must be paid by the Carrier Board designer to ensure adequate power delivery.

Details are given in the sections below.

If Suspend functions such as Suspend-to-RAM, Suspend-to-disk, wake on power button press, wake on

USB activity, etc. are to be supported, then a 5V Suspend power source must also be provided to the

Module. If Suspend functions are not used, the Module VCC_5V_SBY pins should be left open. On some

Modules, there may be a slight power efficiency advantage to connecting the Module VCC_5V_SBY rail to VCC_5V rather than leaving the Module pin open.

Please contact Advantech for further details. Carrier Boards typically require other power rails such as

5V, 3.3V, 3.3V Suspend, etc. These may be derived on the Carrier Board from the 12V and 5V Suspend rails.

3.2. VCC5_SBY Routing

The +5V Suspend power rail, if used, should be sized to handle 2A. Most, but not all, Modules will use considerably less than 2A for this power rail. Modules with multiple Ethernet channels and wake-on-LAN capability will use more current. The COM Express Specification allows up to

2A on this rail. Advantech recommends design 2A for VCC5_SBY.

3.3. ATX and AT Power Sequencing Diagrams

A sequence diagram for an ATX style boot from a soft-off state (S5), initiated by a power button press, is shown in Figure 31 below.

A sequence diagram for an AT style boot from the mechanical off state (G3) is shown in Figure 32 below .

In both cases, the VCC_12V, VCC_5V and VCC_3V3 power lines should rise together in a monotonic ramp with a positive slope only, and their rise time should be limited. Please refer to the ATX specification for more details.

１２１

Figure 31

: ATX Style Power Up Boot – Controlled by Power Button

１２２

VCC_5V_SBY (To COMe)

G3

95%

10%

PWR_BTN# (To COMe)

(Or other wake event)

T1

S5

T2

SUS_S3# (From COMe)

PSON# (To ATX PS)

VCC_12V (To COMe)

VCC_5V, VCC3V

For Carrier Board use

(not needed by Module)

PWR_OK (To COMe)

Module Intermal Power Rails

SYS_RESET# (To COMe) (Optional)

CB_RESET# (From COMe)

95%

10%

T3

T4

T6

T5

T7

１２３

S0 S5

T8

95%

Power Down

T9

G3

95%

Figure 32

: AT Style Power Up Boot

VCC_5V_SBY (To COMe)

(Optional)

95%

10%

G3

95%

T1

10%

T4

VCC_12V (To COMe)

PWR_BTN# (To COMe)

(Optional)

SUS_S3# (From COMe)

VCC_5V, VCC3V

For Carrier Board use

(not needed by Module)

T2

S0

~

T8

G3

Power Down

95%

10%

T5

T9

PWR_OK (To COMe)

T6 ~

T7

Module Intermal Power Rails

SYS_RESET# (To COMe) (Optional)

CB_RESET# (From COMe)

Table 52

: Power Management Timings

Sym Description

T1 VCC_5V_SBY rise time from 10% to 95%

T2 Power Button

T3 The power-on time is defined as the time from when PS_ON# is pulled low to when the VCC_12V, VCC_5V and VCC_3V output 95%.

T4 VCC_12V rise time from 10% to 95%

T5 PWR_OK rise time

T6 VCC_12V rise 95% to PWROK rise

T7 See Note 1

T8 VCC_12V fall 95% to VCC_5V_SBY fall 95%

T9 PWR_OK fall to VCC_12V fall 95%.

Min

0.1ms

50ms

0.1ms

0ms

1ms

0ms

1ms

Max

20ms

500ms

20ms

10ms

95%

10%

１２４

Note:

1. There is a period of time (T6 in Figure 30 and Figure 31 above) during which the Carrier Board circuits have power but the COM Express Module main internal power rails are not up. This is because almost all COM Express internal rails are derived from the external VCC_12V and there is a non-zero start-up time for the Module internal power supplies.

Carrier Board circuits should not drive any COM Express lines during the T6 interval except for those identified in the COM Express Specification as being powered from a Suspend power rail. Almost all such signals are active low. Such signals, if used, should be driven low by open drain Carrier Board circuits to assert them. Pull-ups, if present, should be high value (10K to 100K) and tied to

VCC_5V_SBY.

The line PWR_OK may be used during the T6 interval to hold off a COM Express Module boot.

Sometimes this is done, for example, to allow a Carrier Board device such as an FPGA to be configured before the Module boots.

The deployment of Carrier Board pull-ups on COM Express signals should be kept to a minimum in order to avoid back-driving the COM Express signal pins during this interval.

Carrier Board pull-ups on COM Express signal pins are generally not necessary – most signals are pulled up if necessary on the Module.

3.4. Input Power - Rise Time

The input voltages to the COM Express Module VCC_12V, wide input (Mini) and VCC_5V_SBY if used shall rise from ≤10% of nominal to within the regulation ranges within 0.1 ms to 20 ms (0.1 ms ≤ T1/T4 ≤

20 ms). There must be a smooth and continuous ramp of each DC output voltage from 10% to 95% of its final set point within the regulation band. The smooth turn-on requires that, during the 10% to 95% portion of the rise time, the slope of the turn-on waveform must be positive and have a value of between

0 V/ms and [Vout, nominal / 0.1] V/ms. Also, for any 5ms segment of the 10% to 95% rise time waveform, a straight line drawn between the end points of the waveform segment must have a slope ≥ [Vout, nominal / 20] V/ms.

１２５

3.5. Design Considerations for Carrier Boards containing FPGAs/CPLDs

Very often, the Carrier Board will contain custom FPGA or other programmable devices which require the loading of program code before they are usable. The Carrier Board designer needs to take the necessary precautions to ensure that his Carrier Board logic is up and running before the Module starts.

Conflicts can occur if the Module is powered on and allowed to run before devices on the Carrier Board are fully programmed and initialized. A typical example is an FPGA which includes a PCIe device. Such devices must be initialized and ready before the chipset on the Module performs link training and before the BIOS code performs enumeration of PCI devices. The Module should therefore be prevented from starting before Carrier Board devices are ready.

One method to achieve this is to delay assertion of the PWR_OK# signal to the Module until the Carrier

Board initialization process has completed. Note that during the phase when the Carrier Board is powered and the Module is not powered there is potential for back drive voltages from the carrier to the

Module.

Another possibility is to use the SYS_RESET# signal to delay Module start-up. However, depending on the Module implementation and the chipset used, SYS_RESET# may only be a falling edge triggered signal and not a low active signal as was originally intended. In that case, asserting SYS_RESET# may not hold the Module in the reset state. Also, PCIe link training will occur regardless of the reset signal state for some chipsets.

Please refer to the COM.0 R2.1 specification (Power and System Management section) for more details and check the Module provider’s documentation for their implementations of these signals.

１２６

4. Electrical Characteristics

4.1. Absolute Maximum Ratings

Table 53

: Absolute Maximum Ratings

Power

SOM-6898

VIN

VSB

RTC Battery

4.2. DC Characteristics

MIN

4.75 (5-5%)

4.75 (5-5%)

2.0

MAX

20 (19+5%)

5.25 (5+5%)

3.3

Table 54

: Input Power Consumption of 12V / 4.75V / 20V

Intel(R) KBL CORE I7-7600U [email protected] ,SO-DDR4-2133 16GB

Power Plane Maximum Power Consumption

Symbol

+VIN (+12V)

Idle

S0

TAT CPU+GPU100% 33.29W

4.125W

S3

+VIN

(+4.75V)

+VIN (+20V)

+V5SB_CB

RTC Battery

TAT CPU+GPU100%

Idle

TAT CPU+GPU100%

Idle

0.095W

32.83W

4.28W

35W

4.46W

1.0201W

S5

0.318W

1.55

uA

4.3. Inrush Current

Table 55

:

Inrush Current

Power Plane

Symbol

+V5SB_CB

+VIN (+12V)

+VIN (+4.75V)

+VIN (+20V)

G3 to S5

523.42mA

Maximum

S5 to S0

4.066A

1.7953A

2.6415A

UNIT

V

V

V

G3

4.97uA

１２７