ARM Corstone SSE-300 Manual

Arm® Corstone™ SSE -300 with Cortex®-M55 and Ethos™ -U55 : Example Subsystem for MPS3

Revision: C

Application Note AN547

Non-Confidential

Copyright © 2020, 2021 Arm Limited (or its affiliates).

All rights reserved.

Issue C

DAI 0547C

Arm® Corstone™ SSE -300 with Cortex®M55 and Ethos™ -U55 :

Example Subsystem for MPS3 - Application Note AN547

Arm® Corstone™ SSE -300 with Cortex®M55 and Ethos™ -U55 : Example

DAI 0547C

Issue C

Subsystem for MPS3

Application Note AN547

Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved.

Release information

A

B

C

Document history

Issue Date Confidentiality

30 November 2020 Confidential

29 January 2021

30 June 2021

Non-Confidential

Non-Confidential

Change

First Issue

Confidentiality status changed to Non-Confidential

Document title change,

Added selftest support for DS 2020.1

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.

Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES,

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OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A

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This document may include technical inaccuracies or typographical errors.

TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES,

INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR

CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,

ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE

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This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws.

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If any of the provisions contained in these terms conflict with any of the provisions of any click through or signed written agreement covering this document with Arm, then the click through or signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.


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DAI 0547C

Issue C

The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited

(or its affiliates) in the US and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arm's trademark usage guidelines at http://www.arm.com/company/policies/trademarks .


Arm Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.

(LES-PRE-20349)

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

Unrestricted Access is an Arm internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

developer.arm.com

Progressive terminology commitment

Arm values inclusive communities. Arm recognizes that we and our industry have used terms that can be offensive. Arm strives to lead the industry and create change.

This document includes terms that can be offensive. We will replace these terms in a future issue of this document. If you find offensive terms in this document, please email [email protected]

.


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DAI 0547C

Issue C

LICENCE GRANTS

THE END USER LICENCE AGREEMENT FOR THE ARM SYSTEM OR SUBSYSTEM FOR AN ARM FPGA

PROTOTYPING BOARD (“THE LICENCE”), LES -PRE-21902, DEFINES THE LICENCE GRANTS.

DELIVERABLES

Part A

Hardware Binaries:

Encrypted FPGA bitstream file containing various the Arm technology including:

SSE-300 Subsystem

Cortex-M55 Processor

Ethos-U55 Embedded ML Inference processor.

Software Binaries:

Motherboard Configuration Controller binary (mbb_vxxx.ebf), including Keil ® USB and SD card drivers, and

Analog Devices FMC EEPROM reader. selftest binary (an547_st.axf) for CortexM55 in Corstone™ SSE -300.

Documentation:

Documentation, provided as PDF

Part B

Text configuration files (.txt) in the <install_dir>/ Boardfiles/MB/HBI0309x/ directory:

/board.txt

/AN547/an547_vx.txt

/AN547/images.txt

Part C

None

Part D

None


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Page 4 of 64



Contents

DAI 0547C

Issue C

1 Introduction ........................................................................................................................................................... 8

1.1 Intended audience .................................................................................................................................................... 8

1.2 Conventions ............................................................................................................................................................... 8

1.2.1 Glossary .................................................................................................................................................................... 8

1.2.2 Typographical conventions ............................................................................................................................... 9

1.3 Additional reading .................................................................................................................................................... 9

1.4 Feedback.................................................................................................................................................................... 10

1.4.1 Feedback on this product ................................................................................................................................. 10

1.4.2 Feedback on content ......................................................................................................................................... 10

1.4.3 Other information .............................................................................................................................................. 11

2 Preface .................................................................................................................................................................. 12

2.1 Purpose of this application note ........................................................................................................................ 12

2.2 Terms and abbreviations ..................................................................................................................................... 12

2.3 Arm IP version details ........................................................................................................................................... 13

2.4 Encryption key ......................................................................................................................................................... 13

3 Overview .............................................................................................................................................................. 14

3.1 System block diagram ........................................................................................................................................... 14

3.2 SSE-300 Configuration ......................................................................................................................................... 15

3.2.1 Render Settings ................................................................................................................................................... 15

3.2.2 Subsystem static input values......................................................................................................................... 17

3.3 SIE-300 Components ............................................................................................................................................ 18

3.4 SIE-200 Components ............................................................................................................................................ 18

3.5 CoreLink XHB-500 ................................................................................................................................................. 18

3.6 Memory Protection ............................................................................................................................................... 18

3.7 Memory Map Overview ....................................................................................................................................... 19

3.8 Expansion System peripherals ........................................................................................................................... 22

3.8.1 Manager Peripheral Expansion Low Latency Interface Memory Map (HMSTEXPPILL) ........... 22

3.8.2 MSTEXPPIHL Peripheral Map ........................................................................................................................ 25

3.9 FPGA Utilization ..................................................................................................................................................... 27

3.9.1 Total design utilization ...................................................................................................................................... 27

4 Programmers Model ......................................................................................................................................... 28


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DAI 0547C

Issue C

4.1 ITCM ........................................................................................................................................................................... 28

4.2 FPGA SRAM ............................................................................................................................................................. 28

4.3 DTCM ......................................................................................................................................................................... 28

4.4 QSPI ............................................................................................................................................................................. 28

4.5 DDR4 .......................................................................................................................................................................... 28

4.6 AHB GPIO ................................................................................................................................................................. 29

4.7 SPI ................................................................................................................................................................................ 29

4.8 SBCon (I 2 C) ............................................................................................................................................................... 29

4.9 UART ........................................................................................................................................................................... 30

4.10 Color LCD parallel interface ............................................................................................................................ 30

4.11 Ethernet .................................................................................................................................................................. 31

4.12 USB............................................................................................................................................................................ 31

4.13 RTC ........................................................................................................................................................................... 31

4.14 Audio I 2 S .................................................................................................................................................................. 32

4.15 Audio Configuration ........................................................................................................................................... 33

4.16 FPGA system control and I/O .......................................................................................................................... 34

4.17 Serial Configuration Controller (SCC) .......................................................................................................... 35

5 Clock architecture ............................................................................................................................................. 37

5.1 Clocks.......................................................................................................................................................................... 37

5.1.1 Source clocks ........................................................................................................................................................ 37

5.1.2 Generated clocks ................................................................................................................................................ 37

5.1.3 SSE-300 clocks ..................................................................................................................................................... 38

6 FPGA Secure Privilege Control ...................................................................................................................... 39

7 Interrupt Map ...................................................................................................................................................... 43

7.1 UART Interrupts ..................................................................................................................................................... 45

8 Shield Support ..................................................................................................................................................... 46

9 ZIP Bundle Description .................................................................................................................................... 48

9.1 Overall Structure .................................................................................................................................................... 48

9.2 Bundle Directory Tree/Structure ..................................................................................................................... 48

10 Board Revision And Support ........................................................................................................................ 50

10.1 Identifying the MPS3 board revision ............................................................................................................ 50

10.2 Bundle support for specific MPS3 board revisions. ................................................................................. 50


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11 Using AN547 on the MPS3 Board ............................................................................................................... 51

11.1 Pre-Requisites ....................................................................................................................................................... 51

11.2 Loading a prebuilt image onto the MPS3 Board........................................................................................ 51

11.3 UART Serial Ports ................................................................................................................................................ 52

11.4 UART Serial Port Terminal Emulator Settings ........................................................................................... 52

11.5 MPS3 USB Serial port drivers for Windows ............................................................................................... 52

11.6 MCC Memory mapping ...................................................................................................................................... 53

12 Software ............................................................................................................................................................. 54

12.1 Rebuilding software ............................................................................................................................................ 54

12.2 Loading software on the MPS3 board .......................................................................................................... 54

13 Debug .................................................................................................................................................................. 55

13.1 Debug Connectivity ............................................................................................................................................ 55

13.2 Debug support for Keil MDK ........................................................................................................................... 55

13.3 Trace support for Keil MDK ............................................................................................................................. 57

13.4 Debug and Trace support for Arm Development Studio ....................................................................... 58

13.4.1 Establishing a Debug Session ....................................................................................................................... 58

13.4.2 Trace in Debug session ................................................................................................................................... 62


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1 Introduction

1.1

Intended audience

This application note document is written for experienced hardware, System-on-Chip (SoC) and software engineers who might or might not have experience with Arm products. Such engineers typically have experience in writing Verilog and of performing synthesis but might have limited experience of integrating and implementing Arm products.

1.2

Conventions

The following subsections describe conventions used in Arm documents.

DAI 0547C

Issue C

1 Introduction

1.2.1

Glossary

The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.

See the Arm Glossary for more information: https://developer.arm.com/glossary .


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1.2.2

Typographical conventions

Convention Use italic bold monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. monospace bold Denotes language keywords when used outside example code. monospace underline

Introduces citations.

Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.

<and>

Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.

Encloses replaceable terms for assembler syntax where they appear in code or code fragments.

For example:

MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

SMALL CAPITALS

Used in body text for a few terms that have specific technical meanings, that are defined in the Arm ® Glossary. For example,

IMPLEMENTATION DEFINED

,

IMPLEMENTATION SPECIFIC

,

UNKNOWN

, and

UNPREDICTABLE

.

This represents a recommendation which, if not followed, might lead to system failure or damage.

DAI 0547C

Issue C

1 Introduction

This represents a requirement for the system that, if not followed, might result in system failure or damage.

This represents a requirement for the system that, if not followed, will result in system failure or damage.

This represents an important piece of information that needs your attention.

This represents a useful tip that might make it easier, better or faster to perform a task.

This is a reminder of something important that relates to the information you are reading.

1.3

Additional reading

This document contains information that is specific to this product. See the following documents for other relevant information:


Non-Confidential

Page 9 of 64



Document name

Arm® MPS3 FPGA Prototyping Board Technical

Reference Manual

Document ID

100765

Arm® Corstone™ SSE -300 Example Subsystem

Technical Reference Manual

101773

Arm® Corstone™ SSE -300 Example Subsystem

Configuration and Integration Manual

101774

Arm® Ethos™ -U55 NPU Technical reference manual 101885

Arm® CoreLink™ SIE -200 System IP for Embedded

Technical Reference Manual

DDI 0571

Arm® CoreLink™ SIE -300 AXI5 System IP for

Embedded Technical Reference Manual

101526

Licensee only

No

No

Yes

No

No

No

DAI 0547C

Issue C

1 Introduction

Arm® Cortex®-M System Design Kit Technical

Reference Manual

Arm® CoreLink™ XHB -500 Bridge Technical

Reference Manual

DDI 0479

101375

MCBQVGA-TS-Display-v12 – Keil MCBSTM32F200 display board schematic

-

Arm® MPS3 FPGA Prototyping Board Getting

Started Guide

-

No

No

No

No

Table 1-1 : Arm Publications

1.4

Feedback

Arm welcomes feedback on this product and its documentation.

1.4.1

Feedback on this product

If you have any comments or suggestions about this product, contact your supplier and give:

•

The product name.

•

The product revision or version.

•

An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate.

1.4.2

Feedback on content

If you have comments on content, send an email to [email protected]

and give:


Non-Confidential

Page 10 of 64



•

The title Arm® Corstone™ SSE -300 with Cortex®-M55 and Ethos™ -U55 : Example Subsystem for MPS3 Application Note AN547.

DAI 0547C

Issue C

1 Introduction

•

The number DAI 0547C.

•

If applicable, the page number(s) to which your comments refer.

•

A concise explanation of your comments.

Arm tests the PDF only in Adobe Acrobat and Acrobat Reader and cannot guarantee the quality of the represented document when used with any other PDF reader.

Arm also welcomes general suggestions for additions and improvements.

1.4.3

Other information

•

Arm Documentation, https://developer.arm.com/documentation/

•

Arm Technical Support Knowledge Articles, https://www.arm.com/support/technical-support

•

Arm Support

,

https://www.arm.com/support

•

Arm Glossary, https://developer.arm.com/documentation/aeg0014/g

The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.


Non-Confidential

Page 11 of 64



2 Preface

DAI 0547C

Issue C

2 Preface

2.1

Purpose of this application note

This application note describes the features and functionality of the AN547 Soft Macrocell Model (SMM), or

AN547 subsystem. The AN547 SMM is an FPGA image that is a Single Cortex-M55 FPGA implementation of the Corstone SSE-300 with CortexM55 and Ethos™ -U55 Example Subsystem. The example subsystem uses

SIE-300 and SIE-200 components with CMSDK peripherals to provide a reference design.

IDAU

ITCM

KB

MB

MCC

MPC

MSC

PPC

RAM

AHB

APB

BRAM

CMSDK

DMA

DTCM

EAM

FPGA

RAZ/WI

RTC

RTL

SCC

SMM

2.2

Terms and abbreviations

SPI

SRAM

TPIU

TRM

Advanced High-performance Bus

Advanced Peripheral Bus

Block Random Access Memory

Cortex-M System Design Kit

Direct Memory Access

Data Tightly Coupled Memory

Exclusive Access Controller

Field Programmable Gate Array

Implementation Defined Attribution Unit

Instruction Tightly Coupled Memory

Kilobyte

Megabyte

Motherboard Configuration Controller

Memory Protection Controller

M anager Security Controller

Peripheral Protection Controller

Random Access Memory

R ead As Zero/Write Ignored

Real Time Clock

Register Transfer Level

Serial Configuration Controller

Soft Macrocell Model system implemented as an

FPGA image and described in this AN

Serial Peripheral Interface

Static Random Access Memory

Trace Port Interface Unit

Technical Reference Manual


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2.3

Arm IP version details

The following IP packages have been used in this Product.

DAI 0547C

Issue C

2 Preface

Version r0p0 r1p0 r1p0

Description

Arm® Corstone™ SSE -300

The Arm® Corstone™ SSE -300 Example Subsystem is a collection of pre-assembled elements to use as the basis of an Internet of Things (IoT) System on Chip (SoC).

Arm® Ethos™ -U55 NPU

The Arm® Ethos™ -U55 is a Neural Processing Unit (NPU) which improves the inference performance of neural networks.

Arm® CoreLink™ SIE -300

The SIE-300 AXI5 System IP for Embedded provides a set of configurable AXI5 securityaware components. r3p1

BP210

Arm® CoreLink™ SIE -200

The CoreLink SIE-200 System IP for Embedded product is a collection of interconnect, peripheral, and TrustZone® controller components for use with a processor that complies with the ARMv8-M processor architecture.

Cortex-M System Design Kit

Full version of the design kit supporting Cortex-M0, Cortex-M0 DesignStart ® , Cortex-

M0+, Cortex-M3 and Cortex-M4. Also contains the AHB Bus Matrix and advanced AHB components. r1p3-00rel1 Arm® PrimeCell Synchronous Serial Port (PL022)

Arm PrimeCell Synchronous Serial Port

Figure 2-1 : Arm IP versions

2.4

Encryption key

Arm supplies the MPS3 prototyping board with a decryption key programmed into the FPGA. This key is needed to enable loading of prebuilt encrypted images.

Note

The FPGA programming file that is supplied as part of the bundle is encrypted.

Caution

A battery supplies power to the key storage area of the FPGA. Any keys stored in the FPGA might be lost when battery power is lost. If this happens you must return the board to Arm for reprogramming of the key.


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Page 13 of 64



3 Overview

DAI 0547C

Issue C

3 Overview

The AN547 SMM is a Single Cortex-M55 FPGA implementation of the Corstone SSE-300 with Cortex-M55 and

Ethos-U55 Example Subsystem. The example subsystem uses SIE-300 and SIE-200 components with CMSDK peripherals to provide a reference design.

3.1

System block diagram

The following high-level block diagram shows the full MPS3 FPGA System :

Trace

Port

JTAG

Port mps3_fpga_top fpga_specific mps3_fpga_system mps3_system_core clocks resets mps3_core_periph_wrapper

External_masters

MSC IDAU IDAU MSC MSC IDAU fpga_iot_wrapper

Ethos

U55

XSLVEXPMI0 HSLVEXPMI1 HSLVEXPPILL HSLVEXPPIHL

Debug

Corstone SSE-300

XMSTEXPCODE XMSTEXPSRAM XMSTEXPDEV

XSLVTCM

HMSTEXPPILL HMSTEXPPIHL mps3_mem_preload

XHB AHB to AXI

AHB5 Fabric

SMB TO

AHB mps3_core_mem_wrapper

NIC400

AHB5 Fabric

AXI5

MPC

AXI5

MPC

APB

AXI5

MPC

APB mps3_core_mem_mpc_ppc

AHB to

APB

APB APB

APB PPC

AXI4 mps3_fpga_user mps3_peripheral_mem_wrapper mps3_bram_qspi_memsubsys mps3_ddr_peripheral_subsys

AHB PPC APB

Address

Decode

NIC400

FPGA

SRAM

AXI 4 AXI 4 AXI 4

Xilinx

QSPI

XIP

Xilinx

QSPI

Write

NIC400

AXI 4

Xilinx

MIG mps3_core_periph_wrapper

AHB5 Fabric mps3_core_apb_subsystem_0 mps3_core_apb_subsystem_1

AHB to APB

APB PPC

AHB to APB

APB PPC mps3_core_ahb_subsystem

AHB PPC

AHB5 to

AHB-lite mps3_user_periph_wrapper mps3_user_apb_subsystem_0

Address

Decode

I2C x5 mps3_user_apb_subsystem_1

Address

Decode

UART x6

SCC

SPI x3

(master)

Audio

I2Sx2 CharLCD

FPGA

IO regs mps3_user_ahb_subsystem

NIC400

Address

Decode

AHB5 to extmem

AHB

GPIO x4

AHB PPC

Address

Decode

Default

Slave

DMA

Pl081

DMA

Pl081

DMA

Pl081

QSPI flash DDR4 x2

Shield

ADC

TSC x2

Shield

Audio

MCC

LCD x2

Shield

Ethernet

Switches

Buttons

LEDs

Shield/

PMOD 0

& 1

Xilinx IP

NIC-400 Component

SIE-300 Component

SIE-200 Component

XHB-500 Component

Figure 3-1 : MPS3 System Overview


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DAI 0547C

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3 Overview

3.2

SSE-300 Configuration

The following tables show the configuration settings of the SSE-300 subsystem in the AN547 SMM. See the Arm®

Corstone™ SSE -300 Example Subsystem Configuration and Integration Manual for full details of each configuration option.

3.2.1

Render Settings

Configuration Define

NUMCPU

PILEVEL

CPU0TYPE

CPU1TYPE

CPU2TYPE

CPU3TYPE

NUMNPU

NPU0TYPE

NPU1TYPE

NPU2TYPE

NPU3TYPE

NPU0_NUM_MACS

NPU1_NUM_MACS

NPU2_NUM_MACS

NPU3_NUM_MACS

NUM_AXI_SLAVES_EXP_MI

NUM_AHB_SLAVES_EXP_PIHL

NUM_AHB_SLAVES_EXP_PILL

EXPLOGIC_PRESENT

VMMPCBLKSIZE

CPU0_INITNSVTOR_ADDR_INIT

CPU0EXPNUMIRQ

CPU0EXPIRQDIS

CPU0_EXP_IRQTIER

CPU0_INT_IRQTIER

CPU0_EXP_IRQ_PULSE_SPT_PRESENT

CPU0_EXP_IRQ_SYNC_TO_CPU_PRESENT

CPU0_EXP_IRQ_SYNC_TO_EWIC_PRESENT

CPU0_EXP_NMI_PULSE_SPT_PRESENT

CPU0_EXP_NMI_SYNC_TO_CPU_PRESENT

CPU0_EXP_NMI_SYNC_TO_EWIC_PRESENT

DEBUGLEVEL

CPU0_ITM_PRESENT

CPU0_ETM_PRESENT

CPU0_FPU_PRESENT

CPU0_MVE_CONFIG

SECEXT

CPU0_MPU_S

CPU0_MPU_NS


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SSE-300

Default Value

AN547 Value

1

8

8

2

1

2

1

0

1

65b1

0

1

1

0

0

0

128

256

0

0

1

0

1

3

0

1

0

0

0

128

256

0

0

1

0

1

3

0

32

64

2

32

64

2

1

1

1

7

1

1

1

11

0x00000000 0x00000000

64

64b0

65b1

32b1

64b0

65b1

100

100b0

100b1

32b1

100b0

100b1

1

1

2

1

16

16

1

2

1

100b1

0

1

Page 15 of 64



CPU0_SAUDISABLE

CPU0_NUM_SAU_CONFIG

CPU0_DBGLVL

HASCPU0CPIF

CPU0_INSTR_CACHE_SIZE

CPU0_DATA_CACHE_SIZE

CPU0_IRQLVL

CPU0_ITGUBLKSZ

CPU0_DTGUBLKSZ

CPU0_RAR

CPU0_LOCKSTEP

CPU0_CFGITCMSZ

CPU0_CFGDTCMSZ

CPU0MCUROMADDR

CPU0MCUROMVALID

SOCVAR

SOCREV

SOCPRTID

SOCIMPLID

IMPLVAR

IMPLREV

IMPLPRTID

IMPLID

INITTCMEN

INITPAHBEN

LOCKDCAIC

TCM_MID_WIDTH

S_MID_WIDTH

TCM_ID_WIDTH

XS_ID_WIDTH

S_HMASTER_WIDTH

XOM_USER_SIGNAL_PRESENT

CPU0_PMC_PRESENT

NUMVMBANK

VMADDRWIDTH

HASCRYTO

HASCSS

LOGIC_RETENTION_PRESENT

NSMSCEXPRST

MPCEXPDIS

MSCEXPDIS

BRGEXPDIS

PERIPHPPCEXP3DIS

PERIPHPPCEXP2DIS

PERIPHPPCEXP1DIS

PERIPHPPCEXP0DIS

MAINPPCEXP3DIS

MAINPPCEXP2DIS

MAINPPCEXP1DIS

MAINPPCEXP0DIS

5

0

0

5

5

6

2

18

0

0

0

0xA5A5

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0x5A5A

0xE00FE

1

0x0

0x0

0x7E0

0x43B

1

0

5

0x0

0x0

0x74A

0x43B

0b11

0

8

2

1

0b01111

0b01111

3

7

7

1

0

0b1001

0b1001


Non-Confidential

4

0

0

6

5

6

2

21

0

0

0

0xA5A5

0x5A5A

0x5A5A

0x5A5A

0xFFFE

0xF000

0xFE00

0x1FCC

0x5A5A

0x5A5A

0xFFF1

0xBE00

0xE00FE

1

0x0

0x0

0x7E0

0x43B

1

0

5

0x0

0x0

0x74A

0x43B

0b11

0

8

2

0

0b01111

0b01111

3

8

8

1

0

0b1010

0b1010

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3 Overview

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DAI 0547C

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3 Overview

PDCMQCHWIDTH

HASCPU0IWIC

CPU0CPUIDRST

COLDRESET_MODE

BUSPROT_PRESENT

ECC_PRESENT

CPU0_CTI_PRESENT

0

0

1

4

0

0

0

CFGBIGEND

CFGMEMALIAS

CPU0_INITECCEN

0

0b10000

0

PERIPHERAL_INTERCONNECT_ARBITRATION_SCHEME “round”

CPU0_CFGPAHBZE 0b010

CPU0_LOCKPAHB

PERFORM_CONFIGCHECK

1

1

4

0

0

0

0

0

1

0

0b10000

0

“round”

0b010

1

1

Table 3-1 : SSE-300 Render Configuration Settings

3.2.2

Subsystem static input values

The SSE-300 subsystem in AN547 has several inputs which are tied off and therefore static, at the subsystem top level. These are detailed in the below table.

Input

CPU0_INITSVTOR 1

CPU0CFGFPU

CPU0CFGMVE

CPU0MPUNSDISABLE

CPU0MPUSDISABLE

CPU0CFGSSTCALIB

CPU0CFGNSSTCALIB

CPU0INITL1RSTDIS

Tie Off Value

25'h0200000

1'b1

2'b10

1'b0

1'b0

25'h0270FF

25'h0270FF

1'b0

Table 3-2 : Subsystem static input values

CPU0_INITSVTOR is the value for INITSVTOR0RST specified in the SSE-300 TRM .


Non-Confidential

Page 17 of 64



3.3

SIE-300 Components

This system uses the following SIE-300 components:

• AXI5 Memory Protection Controller.

There are 3 MPCs implemented in the FPGA and these are configured with the following block sizes:

MPC

SRAM MPC

QSPI MPC

DDR4 MPC

Block size

16KB

64KB

1MB

3.4

SIE-200 Components

This system uses the following SIE-200 components:

DAI 0547C

Issue C

3 Overview

• TrustZone AHB5 peripheral protection controller

• TrustZone AHB5 Manager security controller

• AHB5 bus matrix

• AHB5 to AHB5 synchronous bridge

• AHB5 to APB synchronous bridge

• TrustZone APB4 peripheral protection controller

• AHB5 default subordinate

3.5

CoreLink XHB-500

This system implements one CoreLink XHB-500, configured for AHB to AXI mode .

3.6

Memory Protection

The SIE-300 MPC, and SIE-200 PPC components can affect memory and I/O security management and must be configured as required for your application. See Arm ® SIE-200 System IP Technical Reference Manual and Arm®

CoreLink™ SIE -300 AXI5 System IP for Embedded Technical Reference Manual .


Non-Confidential

Page 18 of 64



DAI 0547C

Issue C

3 Overview

3.7

Memory Map Overview

The following figure shows the AN547 memory map and how it relates to the Armv8-M reference memory map.

The figure includes IDAU security information for memory regions.

See the Arm® CoreLink™ SIE -200 System IP for Embedded Technical Reference Manual for more information .

0xFFFF_FFFF

0xE010_0000

0xE000_0000

0x8000_0000

External RAM

Instruction and data accesses performed on M-AXI

0x6000_0000

Peripheral

Instruction and data accesses performed on P-AHB or M-AXI

0x4000_0000

0x2000_0000

0x0000_0000

Arm®v8-M

Ref Memory map

Vendor_SYS

Private Peripheral Bus.

Local to Each CPU.

External Device

Instruction and data accesses performed on M-AXI

SRAM

All accesses performed on

DTCM or M-AXI

CODE

All accesses performed on

ITCM or M-AXI

0xFFFF_FFFF

0xE010_0000

0xE000_0000

0xD000_0000

0xC000_0000

0xB000_0000

0xA000_0000

0x9000_0000

0x8000_0000

0x7000_0000

0x6000_0000

0x5800_0000

0x5000_0000

0x4800_0000

0x4000_0000

0x3880_0000

0x3800_0000

0x3200_0000

0x3100_0000

0x3000_0000

0x2880_0000

0x2800_0000

0x2200_0000

0x2100_0000

0x2000_0000

0x1E00_0000

0x1100_0000

0x1000_0000

0x0E00_0000

0x0100_0000

0x0000_0000

AN547

Memory map

Vendor_SYS

Private Peripheral Bus

DDR 4

DDR 4

DDR 4

DDR 4

DDR 4

DDR 4

DDR 4

DDR 4

Secure High Latency

Peripheral Region

Secure Low Latency

Peripheral Region

Non-Secure High Latency

Peripheral Region

Non-Secure Low Latency

Peripheral Region

Reserved

QSPI (8MB)

Reserved

Internal SRAM (2 x 2MB)

DTCM (4 x 128KB)

Reserved

QSPI (8MB)

Reserved

Internal SRAM (2 x 2MB)

DTCM (4 x 128KB)

Reserved

FPGA SRAM (2MB)

ITCM (512KB)

Reserved

FPGA SRAM (2MB)

ITCM (512KB)

Reserved

QSPI WRITE CONFIG

QSPI XIP CONFIG

Reserved

USER APB 3

USER APB 2

USER APB 1

USER APB 0

Reserved

USB

ETHERNET

Reserved

DMA 3

DMA 2

DMA 1

DMA 0

Reserved

USER AHB 3

USER AHB 2

USER AHB 1

USER AHB 0

GPIO 3

GPIO 2

GPIO 1

GPIO 0

Reserved

Subsystem Peripherals

Reserved

PDM

RTC

CLCD

Reserved

UART 3

UART Shield1

UART Shield0

UART 2

UART 1

UART 0

FPGAIO

I2S Audio

SCC

Reserved

I2C DDR4 EEPROM

USER APB

I2C Shield1

I2C Shield0

SPI Shield1

SPI Shield0

SPI ADC

I2C (Audio Conf)

I2C (Touch)

Reserved

U55 TIMING ADAPTER 1

U55 TIMING ADAPTER 0

Reserved

Subsystem Peripherals

0x4800_0000

0x4180_2000

0x4180_1000

0x4180_0000

0x4170_4000

0x4170_3000

0x4170_2000

0x4170_1000

0x4170_0000

0x4160_0000

0x4150_0000

0x4140_0000

0x4120_4000

0x4120_3000

0x4120_2000

0x4120_1000

0x4120_0000

0x4110_8000

0x4110_7000

0x4110_6000

0x4110_5000

0x4110_4000

0x4110_3000

0x4110_2000

0x4110_1000

0x4110_0000

0x4010_0000

0x4000_0000

Non-Secure

0x5000_0000

0x4930_D000

0x4930_C000

0x4930_B000

0x4930_A000

0x4930_9000

0x4930_8000

0x4930_7000

0x4930_6000

0x4930_5000

0x4930_4000

0x4930_3000

0x4930_2000

0x4930_1000

0x4930_0000

0x4920_9000

0x4920_8000

0x4920_7000

0x4920_6000

0x4920_5000

0x4920_4000

0x4920_3000

0x4920_2000

0x4920_1000

0x4920_0000

0x4810_4000

0x4810_3000

0x4810_2000

0x4810_0000

0x4800_0000

Non-Secure

0x5800_0000

0x5180_2000

0x5180_1000

0x5180_0000

0x5170_4000

0x5170_3000

0x5170_2000

0x5170_1000

0x5170_0000

0x5160_0000

0x5150_0000

0x5140_0000

0x5120_4000

0x5120_3000

0x5120_2000

0x5120_1000

0x5120_0000

0x5110_8000

0x5110_7000

0x5110_6000

0x5110_5000

0x5110_4000

0x5110_3000

0x5110_2000

0x5110_1000

0x5110_0000

0x5010_0000

0x5000_0000

Secure

0x6000_0000

0x5930_D000

0x5930_C000

0x5930_B000

0x5930_A000

0x5930_9000

0x5930_8000

0x5930_7000

0x5930_6000

0x5930_5000

0x5930_4000

0x5930_3000

0x5930_2000

0x5930_1000

0x5930_0000

0x5920_9000

0x5920_8000

0x5920_7000

0x5920_6000

0x5920_5000

0x5920_4000

0x5920_3000

0x5920_2000

0x5920_1000

0x5920_0000

0x5810_4000

0x5810_3000

0x5810_2000

0x5810_0000

0x5800_0000

Secure

Figure 3-2 : Memory Map


Non-Confidential

Page 19 of 64

9



The following table shows the memory map.

6

7

8

4

5

2

3

RO

W

ID

1

From

Address

To

Size

0x0000_0000 0x0007_FFFF 512KB

Region

Name

Code

0x0008_0000 0x00FF_FFFF 15.5MB Reserved

0x0100_0000 0x011F_FFFF 2MB Code

0x0120_0000 0x0FFF_FFFF 238MB Reserved

0x1000_0000 0x100F_FFFF 512KB Code

0x1010_0000 0x10FF_FFFF 15.5MB Reserved

0x1100_0000 0x111F_FFFF 2MB Code

0x1120_0000 0x1FFF_FFFF 238MB Reserved

0x2000_0000 0x2007_FFFF 512KB SRAM

Description

ITCM 3

Reserved

FPGA SRAM (2MB) 1

Reserved

ITCM 3

Reserved

FPGA SRAM (2MB) 1

Reserved

DTCM (4 x banks of 128KB) 3

DAI 0547C

Issue C

3 Overview

Alias with

Row ID

5

1

7

3

IDAU Region Values

Security

IDAU

ID

NSC

NS

S

0

1

0

CODE

NSC

15 NS 2 0

10 0x2008_0000 0x20FF_FFFF 15.5MB Reserved

11 0x2100_0000 0x213F_FFFF 4MB

15 0x3000_0000 0x303F_FFFF 512KB

SRAM

12 0x2140_0000 0x27FF_FFFF 108MB Reserved

13 0x2800_0000 0x287F_FFFF 8MB SRAM

14 0x2880_0000 0x2FFF_FFFF 120MB Reserved

SRAM

16 0x3040_0000 0x30FF_FFFF 15.5MB Reserved

Reserved

Internal SRAM Area (SSE-

300 implements 2x2MB) 3

Reserved

QSPI (8MB) 1

Reserved

DTCM (4 x banks of 128KB) 3

17

19

9 S 3

RAM

NSC

17 0x3100_0000 0x313F_FFFF 4MB SRAM

18 0x3140_0000 0x37FF_FFFF 108MB Reserved

19 0x3800_0000 0x387F_FFFF 8MB SRAM

Reserved

Internal SRAM Area (SSE-

300 implements 2x2MB) 3

Reserved

QSPI (8MB) 1

11

13

20 0x3880_0000 0x3FFF_FFFF 120MB Reserved Reserved

21

22

23

24

0x4000_0000

0x4800_0000

0x5000_0000

0x5800_0000

0x47FF_FFFF

0x4FFF_FFFF

0x57FF_FFFF

0x5FFF_FFFF

128MB

128MB

128MB

128MB

Peripheral

Peripheral

Peripheral

Peripheral

Non-Secure Low Latency

Peripheral Region

Non-Secure High Latency

Peripheral Region

Secure Low Latency

Peripheral Region

Secure High Latency

Peripheral Region

25 0x6000_0000 0x6FFF_FFFF 256MB External RAM DDR4 1

23

24

21

22

NS

NS

S

S

NS

26 0x7000_0000 0x7FFF_FFFF 256MB External RAM DDR4 1 S

27 0x8000_0000 0x8FFF_FFFF 256MB

External device

DDR4 1 NS


Non-Confidential

4

4

5

5

6

7

8

0

0

0

0

0

0

0

Page 20 of 64



RO

W

ID

From

Address

To

Size

Region

Name

Description

28

29

30

31

32

0x9000_0000

0xA000_0000

0xB000_0000

0xC000_0000

0xD000_0000

0x9FFF_FFFF

0xAFFF_FFFF

0xBFFF_FFFF

0xCFFF_FFFF

0xDFFF_FFFF

256MB

256MB

256MB

256MB

256MB

External device

External device

External device

External device

External device

DDR4

DDR4

DDR4

DDR4

DDR4

1

1

1

1

1

33 0xE000_0000 0xE00F_FFFF 1MB EPPB

External Private Peripheral

Bus

34

35

0xE010_0000

0xE020_0000

0xE01F_FFFF

0xEFFF_FFFF

1MB

254MB

Vendor_SYS Reserved

Vendor_SYS

Maps to HMSTEXPPILL

Expansion Interface 2

36

37

38

0xF000_0000

0xF010_0000

0xF020_0000

0xF00F_FFFF

0xF01F_FFFF

0xFFFF_FFFF

1MB

1MB

254MB

Vendor_SYS Reserved

Vendor_SYS Reserved

Vendor_SYS

Maps to HMSTEXPPILL

Expansion Interface 2

Alias with

Row ID

DAI 0547C

Issue C

3 Overview

IDAU Region Values

Security

IDAU

ID

NSC

S

NS

S

NS

S

NS

NS

S

S

9

A

B

C

D

Exempt

E

E

Exempt

F

F

Table 3-3 : Memory map overview

0

0

0

0

0

0

0

0

0

This table outlines the main FPGA memories and their positions within the memory map.

Note 1 : Security Access is controlled by MPC.

Note 2 : Accesses to these addresses results in an AHB5 error response.

Note 3 : For security settings, control and features please refer to the Arm® Corstone™ SSE -300

Documentation.


Non-Confidential

Page 21 of 64



DAI 0547C

Issue C

3 Overview

3.8

Expansion System peripherals

All FPGA peripherals are mapped to four areas of the memory map. The addresses and interfaces to access the four regions are:

Non-secure Low Latency region:

• 0x4000_0000 - 0x47FF_FFFF

• Manager Peripheral Expansion Low Latency Interface HMSTEXPPILL

Non-secure High Latency region:

• 0x4800_0000 - 0x4FFF_FFFF

• Manager Peripheral Expansion High Latency Interface HMSTEXPPIHL

Secure Low Latency region:

• 0x5000_0000 - 0x57FF_FFFF

• Manager Peripheral Expansion Low Latency Interface HMSTEXPPILL

Secure High Latency region:

• 0x5800_0000 - 0x5FFF_FFFF

• Manager Peripheral Expansion High Latency Interface HMSTEXPPIHL

To support TrustZone-Arm v8M and allow Software to map these peripherals to Secure or Non-secure address space, all peripherals are mapped twice and either an APB PPC or an AHB PPC gates access to these peripherals.

3.8.1

Manager Peripheral Expansion Low Latency Interface Memory Map

(HMSTEXPPILL)

The following table shows the FPGA peripheral mapping to the Non-secure Low Latency region

ROW

ID

1

10

11

12

13

14

15

16

17

18

5

6

7

8

9

2

3

4

Address

From

0x4000_0000

To

0x400F_FFFF

0x4010_0000

0x4110_0000

0x4110_1000

0x4110_2000

0x4110_3000

0x4110_4000

0x4110_5000

0x4110_6000

0x4110_7000

0x4110_8000

0x4120_0000

0x4120_1000

0x4120_2000

0x4120_3000

0x4120_4000

0x4140_0000

0x4150_0000

0x410F_FFFF

0x4110_0FFF

0x4110_1FFF

0x4110_2FFF

0x4110_3FFF

0x4110_4FFF

0x4110_5FFF

0x4110_6FFF

0x4110_7FFF

0x411F_FFFF

0x4120_0FFF

0x4120_1FFF

0x4120_2FFF

0x4120_3FFF

0x413F_FFFF

0x414F_FFFF

0x415F_FFFF

Size

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

1MB

1MB

Description

Subsystem peripherals

Reserved

GPIO 0

GPIO 1

GPIO 2

GPIO 3

AHB USER 0

AHB USER 1

AHB USER 2

AHB USER 3

Reserved

Reserved

DMA 1

DMA 2

DMA 3

Reserved

Ethernet

USB


Non-Confidential

Alias with

ROW ID

36

37

40

41

42

44

45

30

31

32

33

34

35

Port

AHB

AHB

AHB

Page 22 of 64

ROW

ID

28

29

42

43

44

45

46

47

48

49

50

51

52

53

54

36

37

38

39

40

41

30

31

32

33

34

35

55

56

ROW

ID

19

20

21

22

23

24

25

26

27



Address

From

0x4160_0000

To

0x416F_FFFF

0x4170_0000

0x4170_1000

0x4170_2000

0x4170_3000

0x4170_4000

0x4180_0000

0x4180_1000

0x4180_2000

0x4170_0FFF

0x4170_1FFF

0x4170_2FFF

0x4170_3FFF

0x417F_FFFF

0x4180_0FFF

0x4180_1FFF

0x47FF_FFFF

Size

4KB

4KB

4KB

4KB

4KB

4KB

DAI 0547C

Issue C

3 Overview

Description

Alias with

ROW ID

Port

Reserved

User APB0

User APB1

User APB2

User APB3

47

48

49

50

APB

(Mem)

Reserved

QSPI Config

QSPI Write

52

53

Reserved

Table 3-2: MSTEXPPILL Non-secure Peripheral Map

AHB

The following table shows the FPGA peripheral mapping to the Secure Low Latency region

Address

From

0x5000_0000

To

0x500F_FFFF

0x5010_0000 0x510F_FFFF

0x5110_0000

0x5110_1000

0x5110_2000

0x5110_3000

0x5110_4000

0x5110_5000

0x5110_6000

0x5110_7000

0x5110_8000

0x5120_0000

0x5120_1000

0x5120_2000

0x5120_3000

0x5120_4000

0x5140_0000

0x5150_0000

0x5160_0000

0x5170_0000

0x5170_1000

0x5170_2000

0x5170_3000

0x5170_4000

0x5180_0000

0x5180_1000

0x5180_2000

0x5110_0FFF

0x5110_1FFF

0x5110_2FFF

0x5110_3FFF

0x5110_4FFF

0x5110_5FFF

0x5110_6FFF

0x5110_7FFF

0x511F_FFFF

0x5120_0FFF

0x5120_1FFF

0x5120_2FFF

0x5120_3FFF

0x513F_FFFF

0x514F_FFFF

0x515F_FFFF

0x516F_FFFF

0x5170_0FFF

0x5170_1FFF

0x5170_2FFF

0x5170_3FFF

0x517F_FFFF

0x5180_0FFF

0x5180_1FFF

0x56FF_FFFF

0x5700_0000 0x5700_0FFF

0x5700_1000 0x5700_1FFF

Size

4KB

4KB

4KB

1M

1M

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

Description


Reserved

GPIO 0

GPIO 1

GPIO 2

GPIO 3

AHB USER 0

AHB USER 1

AHB USER 2

AHB USER 3

Reserved

Reserved

DMA 1

DMA 2

DMA 3

Reserved

Ethernet

USB

Reserved

User APB0

User APB1

User APB2

User APB3

Reserved

QSPI Config

QSPI Write

Reserved

SRAM Memory Protection Controller

(MPC)

QSPI Memory Protection Controller

(MPC)

Alias with

ROW ID

25

26

17

18

20

21

22

23

8

9

10

13

14

15

5

6

7

3

4

Port

AHB

AHB

AHB

APB

(Mem)

AHB

APB

(Mem)


Non-Confidential

Page 23 of 64

ROW

ID

57

58



Address

From

0x5700_2000

To

0x5700_2FFF

0x5700_3000 0x57FF_FFFF

Size

4KB

DAI 0547C

Issue C

3 Overview

Description

Alias with

ROW ID

DDR4 Memory Protection Controller

(MPC)

Reserved

Table 3-3: MSTEXPPILL Secure Peripheral Map

Port

Reserved regions respond with RAZ/WI when accessed .


Non-Confidential

Page 24 of 64

16

17

18

19

12

13

14

15

5

6

7

8

9

10

11

1

2

3

4

24

25

26

27

28

29

20

21

22

23

ROW

ID



0x4800_0000

0x4810_0000

0x4810_2000

0x4810_3000

0x4810_3200

0x4810_3400

0x4920_0000

0x4920_1000

0x4920_2000

0x4920_3000

0x4920_4000

0x4920_5000

0x4920_6000

0x4920_7000

0x4920_8000

0x4920_9000

0x4930_0000

0x4930_1000

0x4930_2000

0x4930_3000

0x4930_4000

0x4930_5000

0x4930_6000

0x4930_7000

0x4930_8000

0x4930_9000

0x4930_A000

0x4930_B000

0x4930_C000

0x480F_FFFF

0x4810_1FFF

0x4810_2FFF

0x4810_31FF

0x4810_33FF

0x491F_FFFF

0x4920_0FFF

0x4920_1FFF

0x4920_2FFF

0x4920_3FFF

0x4920_4FFF

0x4920_5FFF

0x4920_6FFF

0x4920_7FFF

0x4920_8FFF

0x492F_FFFF

0x4930_0FFF

0x4930_1FFF

0x4930_2FFF

0x4930_3FFF

0x4930_4FFF

0x4930_5FFF

0x4930_6FFF

0x4930_7FFF

0x4930_8FFF

0x4930_9FFF

0x4930_AFFF

0x4930_BFFF

0x4FFF_FFFF

DAI 0547C

Issue C

3 Overview

3.8.2

MSTEXPPIHL Peripheral Map

Address

From To

Size Description

Alias with

ROW ID

Port

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

Non-Secure Region


Reserved

4KB

0.5KB

0.5KB

Ethos - U55 APB

U55 timing adapter 0 APB


Reserved

FPGA - SBCon I2C (Touch)

FPGA - SBCon I2C (Audio Conf)

FPGA - PL022 (SPI ADC)

FPGA - PL022 (SPI Shield0)


SBCon (I2C - Shield0)

SBCon (I2C – Shield1)

USER APB

FPGA - SBCon I2C (DDR4 EEPROM)

Reserved

FPGA - SCC registers

FPGA - I2S (Audio)

FPGA - IO (System Ctrl + I/O)

UART0 - UART_F[0]

UART1 - UART_F[1]

UART2 - UART_F[2]

UART3 - UART Shield 0


UART5 - UART_F[3]

Reserved

APB0

APB0

APB1

CLCD Config Reg 55

RTC

Reserved

56

Table 3-4: MSTEXPPIHL Non-secure Peripheral Map

40

41

42

43

36

37

38

39

45

46

47

48

49

50

51

52

53

31

32

33

35


Non-Confidential

Page 25 of 64

44

45

46

47

40

41

42

43

34

35

36

37

38

39

30

31

32

33

52

53

54

55

56

57

48

49

50

51

ROW

ID



From

Address

0x5800_0000

0x5810_2000

0x5810_3000

0x5810_3200

0x5810_3400

0x5920_0000

0x5920_1000

0x5920_2000

0x5920_3000

0x5920_4000

0x5920_5000

0x5920_6000

0x5920_7000

0x5920_8000

0x5920_9000

0x5930_0000

0x5930_1000

0x5930_2000

0x5930_3000

0x5930_4000

0x5930_5000

0x5930_6000

0x5930_7000

0x5930_8000

0x5930_9000

0x5930_A000

0x5930_B000

0x5930_C000

To

0x5810_1FFF

0x5810_2FFF

0x5810_31FF

0x5810_33FF

0x591F_FFFF

0x5920_0FFF

0x5920_1FFF

0x5920_2FFF

0x5920_3FFF

0x5920_4FFF

0x5920_5FFF

0x5920_6FFF

0x5920_7FFF

0x5920_8FFF

0x592F_FFFF

0x5930_0FFF

0x5930_1FFF

0x5930_2FFF

0x5930_3FFF

0x5930_4FFF

0x5930_5FFF

0x5930_6FFF

0x5930_7FFF

0x5930_8FFF

0x5930_9FFF

0x5930_AFFF

0x5930_BFFF

0x5FFF_FFFF

DAI 0547C

Issue C

3 Overview

Size Description

Alias with

ROW ID

Port

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

0.5KB

0.5KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

4KB

Secure Region


Ethos - U55 APB



Reserved








USER APB

FPGA - SBCon I2C (DDR4 EEPROM)

Reserved


FPGA - I2S (Audio)


UART0 - UART_F[0]

UART1 - UART_F[1]

UART2 - UART_F[2]



UART5 - UART_F[3]

Reserved

CLCD Config Reg 27

RTC

Reserved

28

Table 3-5: MSTEXPPIHL Secure Peripheral Map

APB0

APB0

APB1

12

13

14

15

17

18

19

20

21

22

23

24

25

8

9

10

11

3

4

5

7

Note

Reserved regions respond with RAZ/WI when accessed.


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3 Overview

3.9

FPGA Utilization

This application note is designed for MPS3 board. The board will use a a Xilinx Kintex Ultrascale XCKU115 FPGA. The FPGA features up to 8MB BRAM (2160 BlocRAM tiles) and up to 663360 LUTs.

Full part number: XCKU115-FLVB1760-1-C.

3.9.1

Total design utilization

The following table shows the total number of LUTs and BRAMs currently used in the provided image.

Site Type

LUTs

Used

270540

Util%

40

BlockRAM Tile 1851 86

Note : These numbers relate to the complete image, not individual IP blocks. The numbers must not be used to infer IP size, or the relative sizes of different IP blocks, because the implementation and system design can significantly differ.


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4 Programmers Model

DAI 0547C

Issue C

4 Programmers Model

This programmers model is supplemental to the CMSDK, SIE-200 and SIE-300 documentation which covers many of the included components in more detail. The connectivity of the system is shown in MPS3 System Overview

Diagram.

4.1

ITCM

The primary boot memory is an ITCM which is implemented with 512KB of FPGA SRAM connected to the ITCM interface of the Cortex-M55 inside the subsystem.

• Size: 512KB FPGA SRAM

• Address Range: 0x0000_0000 - 0x0007_FFFF

• Alias Range: 0x1000_0000 - 0x1007_FFFF

4.2

FPGA SRAM

The code memory is extended with 2MB of internal FPGA SRAM.

• Size: 2MB FPGA SRAM

• Address Range: 0x0100_0000 - 0x011F_FFFF

• Alias Range: 0x1100_0000 - 0x111F_FFFF

4.3

DTCM

The primary data memory is provided by DTCM made up of 4 banks, each implemented as 128KB of internal

FPGA SRAM connected to the 4 DTCM interfaces of the Cortex-M55 inside the subsystem.

• Size: 4 x 128KB FPGA SRAM

• Address Range: 0x2000_0000 - 0x2007_FFFF

• Alias Range: 0x3000_0000 - 0x3007_FFFF

4.4

QSPI

The SMM provides 8MB of external Flash memory which is accessed through a QSPI interface.

• Size: 8MB fitted

• Address Range: 0x2800_0000 - 0x287F_FFFF

• Alias Range: 0x3800_0000 - 0x387F_FFFF

4.5

DDR4

The SMM provides access to 2GB of External DDR4 memory through the DDR4 controller.

• Size: 2GB DDR4 (4GB fitted only 2GB accessible)

• Address Range: 0x6000_0000 - 0xDFFF_FFFF


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DAI 0547C

Issue C

4 Programmers Model

4.6

AHB GPIO

The SMM uses four CMSDK AHB GPIO blocks, each providing 16 bits of I/O. These are connected to the two

Arduino compatible headers shield 0 and 1 as follows:

Shield

SH0_IO [15:0]

SH0_IO [17:16]

SH1_IO [15:0]

SH1_IO [17:16]

GPIO

GPIO0[15:0]

GPIO2[1:0]

GPIO1[15:0]

GPIO2[3:2]

Table 4-1 : GPIO Mapping

The GPIO alternative function lines select whether peripherals or GPIOs are available on each pin. See Shield

Support Section for mappings.

4.7

SPI

The SMM implements three PL022 SPI modules:

• One general purpose SPI module (SPI ADC) is used for communication with an onboard ADC. The analog pins of the Shield headers are connected to the input channels of the ADC.

• Two general purpose SPI modules connect to the Shield headers and provide an SPI interface on each header.

These are alt-functions on the GPIO ports. See Shield Support Section for mappings.

4.8

SBCon (I

2

C)

The SMM implements five SBCon serial modules:

• One SBCon module for use by the Color LCD touch interface.

• One SBCon module to configure the audio controller.

• Two general purpose SBCon modules that connect to Shield0 and Shield1 and provide an I 2 C interface on

each header. These are alt-functions on the GPIO ports. See Shield Support Section for mappings.

• One SBCon module is used to read EEPROM from DDR4 SODIMM.

The selftest software provided with the MPS3 includes example code for the color LCD module control and audio interfaces.

The following table lists the control registers for the two-wire SBCon in offset order from the base memory address. For example, the Touchscreen SBCon non-secure base address is 0x4920_0000 and the secure base address is 0x5920_0000.

Address

0x000

0x000

0x004

Name Access Description

SB_CONTROL Read Read serial control bits:

Bit [0] is SCL

Bit [1] is SDA

SB_CONTROLS Write Set serial control bits:

Bit [0] is SCL

Bit [1] is SDA

SB_CONTROLC Write Clear serial control bits:

Bit [0] is SCL

Bit [1] is SDA

Table 4-2 SBCon Register Map


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4.9

UART

The SMM implements six CMSDK UARTs:

• UART 0 – FPGA_UART0



• UART 3 - Shield 0

• UART 4 - Shield 1

• UART 5 - FPGA_UART3

UART 3 and 4 are alt-functions on the GPIO ports. See Shield Support for mappings.

4.10

Color LCD parallel interface

The color LCD module has two interfaces:

• Parallel bus for sending image data to the LCD.

• I 2 C to transfer data input from the touch screen.

DAI 0547C

Issue C

4 Programmers Model

This is a custom peripheral that provides an interface to a STMicroelectronics STMPE811QTR Port Expander with

Advanced Touch Screen Controller on the Keil MCBSTM32C display board. See MCBQVGA-TS-Display-v12 – Keil

MCBSTM32F200 display board schematic . The Keil display board contains an AM240320LG display panel and uses a Himax HX8347-D LCD controller.

The selftest software provided with the MPS3 includes drivers and example code for both interfaces.

The following table lists CLCD control and data registers in offset order from the base memory address.

The CLCD non-secure base address is 0x4930A000, the secure base address is 0x5930A000.

Address

0x000

0x004

0x008

Name

CHAR_COM

CHAR_DAT

CHAR_RD

Type

Write command, read busy status.

Write data RAM,

Read data RAM.

Captured data from an earlier read command

Information

A write to this address causes a write to the LCD command register. A read from this address causes a read from the LCD busy register.

A write to this address causes a write to the LCD data register. A read from this address causes a read from the LCD data register.

Bits [31:8] : Reserved.

Bits [7:0] : contain the data from last request read, valid only when bit 0 is set in

CHAR_RAW.


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Address

0x00C

0x010

0x014

0x04C

Name

CHAR_RAW

CHAR_MASK

CHAR_STAT

CHAR_MISC

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Issue C

4 Programmers Model

Type

Write to reset access complete flag

Read to determine if data in CHAR_RD is valid

Write interrupt mask

Read status

Miscellaneous

Control

Information

Bits [31:1] : Reserved

Bit [0] : indicates Access Complete (write

0 to clear). The bit is set if read data is valid.

Set bit 0 to 0b1 to enable Access

Complete to generate an interrupt.


Bit [0] : is the state of Access Complete

ANDed with the CHAR_MASK.

Bit Field Description :


Bit [6] : CLCD_BL

Bit [5] : CLCD_RD

Bit [4] : CLCD_RS

Bit [3] : CLCD_RESET

Bit [2] : RESERVED

Bit [1] : CLCD_WR

Bit [0] : CLCD_CS

Table 4-3 : LCD control and data registers

4.11

Ethernet

The SMM design connects to an SMSC LAN9220 device through a static memory interface.

The selftest software includes example code for an internal loopback operation.

4.12

USB

The SMM design connects to a Hi-Speed USB OTG controller (ISP1763) device through a static memory interface.

The selftest software includes example code for an internal loopback operation.

4.13

RTC

The SMM uses PL031 PrimeCell Real Time Clock Controller. A counter in the Controller is incremented every second. The RTC can therefore be used as a basic alarm function or long timebase counter.


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4.14

Audio I

2

S

The I 2 S interface supports transfer of digital audio to and from the Audio CODEC.

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4 Programmers Model

The following table shows the register memory map for I 2 S Audio registers in address offset order from the base memory address. The I2S non-secure base address is 0x49301000, the secure base address is 0x59301000.

Offset Name Description

0x000 CONTROL Control Register

Bits [31:18] Reserved

Bit [17]

Bit [16]

Bit [15]

Audio codec reset control (output pin)

FIFO reset

Reserved

Bits [14:12] Rx Buffer IRQ Water Level - Default 2 (IRQ triggers when less than two-word space is available)

Bit [11] Reserved

Bits [10:8] TX Buffer IRQ Water Level - Default 2 (IRQ triggers when more than two-word space is available)

Reserved Bits [7:4]

Bit [3]

Bit [2]

Rx Interrupt Enable

Rx Enable

0x004

0x008

STATUS

ERROR

Bit [1]

Bit [0]

Tx Interrupt Enable

Tx Enable

Status Register


Bit [5]

Bit [4]

Rx Buffer Full

Rx Buffer Empty

Bit [3]

Bit [2]

Bit [1]

Bit [0]

Error Status Register

Bits [31:2]

Tx Buffer Full

Tx Buffer Empty

Rx Buffer Alert (Depends on Water level)

Tx Buffer Alert (Depends on Water level)

Reserved

Bit [1]

Bit [0]

Rx overrun. Set this bit to clear.

Tx overrun or underrun. Set this bit to clear.

0x00C DIVIDE

0x010 TXBUF

Clock Divide Ratio Register (for left or right clock)


Bits [9:0] LRDIV (Left/Right). The default value is 0x80. 12.288MHz / 48kHz /

2*(L+R) = 128.

Transmit Buffer FIFO Data Register. This is a write-only register.

0x014 RXBUF

Bits [31:16] Left channel

Bits [15:0] Right channel

Receive Buffer FIFO Data Register. This is a read-only register.

Bits [31:16] Left channel

Bits [15:0]

0x018- RESERVED -

Right channel


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Offset Name

0x2FF

0x300 ITCR

Description

0x304

0x308

ITIP1

ITOP1

Integration Test Control Register

Bits [31:1]

Bit [0]

Reserved

ITCR

Integration Test Input Register 1


Bit [0] SDIN

Integration Test Output Register 1


Bit [3]

Bit [2]

Bit [1]

Bit [0]

IRQOUT

LRCK

SCLK

SDOUT

DAI 0547C

Issue C

4 Programmers Model

Table 4-4 Audio I2S Register Map

4.15

Audio Configuration

The SMM implements a simple SBCon interface based on I 2 C. It configures the Cirrus Logic Low Power

Codec with Class D Speaker Driver, CS42L52 part on the MPS3 board.


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DAI 0547C

Issue C

4 Programmers Model

4.16

FPGA system control and I/O

The AN547 SMM implements an FPGA system control block with non-secure base address 0x49302000 and secure base address 0x59302000.

The following table shows the register memory map in offset order from the base memory address.

Offset

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

0x01C

0x020

0x024

0x028

0x04C

Name

FPGAIO->LED0

Information

LED connections


Bits [9:0] LED

FPGAIO-> M55DBGCTRL Cortex-M55 Control signals


Bit [3]

Bit [2]

Bit [1]

Bit [0]

SPNIDEN

SPIDEN

NIDEN

DBGEN

FPGAIO->BUTTON

FPGAIO->GPIOALT2

FPGAIO->CLK1HZ

FPGAIO->CLK100HZ

FPGAIO->COUNTER

FPGAIO->PRESCALE

Buttons


Bits [1:0] Buttons

GPIO Alt Function 2 select:


1Hz up counter

100Hz up counter

Cycle Up Counter - Increments when 32-bit prescale counter equals zero and automatically reloads.

Prescale Reload Value

FPGAIO->PSCNTR

RESERVED

FPGAIO->SWITCH

FPGAIO->MISC

Bits [31:0] Reload value for prescale counter.

Prescale Counter Value

Bits [31:0] Current value of the prescale counter. The prescale counter is reloaded with PRESCALE after reaching 0.

-

Switches


Bits [7:0] Switches

Misc. control


Bit [2] SHIELD1_SPI_nCS

Bit [1] SHIELD0_SPI_nCS

Bit [0] ADC_SPI_nCS

Table 4-5 : System Control and I/O Registers


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DAI 0547C

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4 Programmers Model

4.17

Serial Configuration Controller (SCC)

The SMM implements communication between the MCC and the FPGA system through an SCC interface. read address

Write address

11

Write data

0

43 32 31 0

Read interface CFGDATAIN

31 0

CFGDATAOUT

0

Read data

CFGLOAD

CFGWnR

CFGCLK fpga_scc_if.v

FPGA

Figure 4-1 : Diagram of the SCC Interface

The read-addresses and write-addresses of the SCC interface do not use bits [1:0]

All address words are word-aligned.

The following table shows SCC registers in offset order from the base address. The non-secure base address in 0x49300000, the secure is 0x59300000.

Address

0x000

0x004

0x008

0x00C

0x010

Name

CFG_REG0

CFG_REG1

CFG_REG2

CFG_REG3

CFG_REG4

Information


Bit [1] CPU_WAIT ctrl

Bit [0] Reserved

Bits [31:0] DATA RW


Bit [0] QSPI Select signal



Bits [3:0] Board Revision [r]

0x014 CFG_REG5

0x018 – 0x09C RESERVED

0x0A0

0x0A4

SYS_CFGDATA_RTN

SYS_CFGDATA_OUT

Bits [31:0]

-

Bits [31:0]

Bits [31:0]

ACLK Frequency in Hz

DATA RW

DATA RW

0x0A8 SYS_CFGCTRL

Bit [31]

Start (generates interrupt on write to this bit)

Bit [30] RW access



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MCC



Address

0x0AC

0x0B0

0xFF8

0xFFC

–

Name

SYS_CFGSTAT

0xFF4 RESERVED

SCC_AID

SCC_ID

DAI 0547C

Issue C

4 Programmers Model

Information

Bits [25:20] Function value


Bits [11:0] Device (value of 0/1/2 for supported clocks)


Bit [1] Error

Bit [0]

-

Complete

SCC AID register is read only

Bits [31:24] FPGA build number

Bits [23:20]

V2M-MPS3 target board revision (A = 0, B =

1, C = 2)


Bits [7:0] Number of SCC configuration register

SCC ID register is read only

Bits [31:24] Implementer ID: 0x41 = Arm


Bits [19:16] IP Architecture: 0x5 =AXI

Primary part number in Binary Coded

Bits [15:4] Decimal (BCD): Default value 0x547 =

AN547

Bits [3:0] Reserved

Table 4-6 : SCC Register memory map


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5 Clock architecture

5.1

Clocks

The following sections list clocks entering the FPGA and generated by the SMM.

DAI 0547C

Issue C

5 Clock architecture

5.1.1

Source clocks

The following clocks are inputs to the FPGA from source clocks on the board.

Clock Input Pin

REFCLK24MHZ OSCCLK[0]

ACLK

MCLK

OSCCLK[1]

OSCCLK[2]

GPUCLK

AUDCLK

HDLCDCLK

DBGCLK

OSCCLK[3]

OSCCLK[4]

OSCCLK[5]

CS_TCK

Frequency

24MHz

32MHz

50MHz

50MHz

24.576MHz

23.75MHz

Set by debugger

Note

24MHz reference

Programmable oscillator





JTAG input

CFGCLK

DDR4_REF_CLK c0_sys_clk_p/n

SMBM_CLK

CFG_CLK

SMBM_CLK

Set by MCC

100MHz

SCC register clock from MCC

Differential input clock to DDR4 controller

Set by MCC (40MHz) SMB clock from MCC

Table 5-1 : Source clocks

5.1.2

Generated clocks

The following clocks are generated inside the FPGA from the source clocks on the board.

Clock

MAINCLK

PERIF_CLK

AUDMCLK

AUDSCLK

SDMCLK

CLK32KHZ

CLK100HZ

CLK1HZ

CFGCLK

Source

OSCCLK[1]

Frequency

32MHz

OSCCLK[3]

AUDCLK

AUDCLK

25MHz

12.29MHz

3.07MHz

REFCLK24MHZ 50MHz

REFCLK24MHZ 32kHz

REFCLK24MHZ 100Hz

REFCLK24MHZ 1Hz

CFG_CLK Set by MCC

-

-

-

-

Note

Clock source for SSE-300 and all non- APB peripherals in the design

Clock source for APB peripherals

-

-

SCC register clock from MCC

Table 5-2 : Generated internal clocks


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5.1.3

SSE-300 clocks

The following clocks generated within the FPGA are connected to the SSE-300 subsystem.

SSE-300 Clock Input

SYSCLK

CPU0CLK

AONCLK

CNTCLK

SLOWCLK

FPGA Clock

MAINCLK

MAINCLK

MAINCLK

MAINCLK

CLK32KHZ

Frequency

32MHz

32MHz

32MHz

32MHz

32KHz

DAI 0547C

Issue C

5 Clock architecture

Note

Main System clock

CPUclock

Always On clock

Counter clock

Slow clock

Table 5-3 : SSE-300 clocks


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DAI 0547C

Issue C

6 FPGA Secure Privilege Control

6 FPGA Secure Privilege Control

The SSE-300 Subsystem Secure Privilege and Non-Secure Privilege Control Block provide expansion security control signals to control the security gating units outside the subsystem. The following table lists the connectivity of the system security extension signals.

Component Name Component signals msc_irq

USER MSC msc_irq_clear cfg_nonsec apb_ppc_irq

APB PPC EXP 0 apb_ppc_clear cfg_sec_resp cfg_non_sec cfg_ap apb_ppc_irq apb_ppc_clear

APB PPC EXP 1

APB PPC EXP 2 cfg_sec_resp cfg_non_sec cfg_ap apb_ppc_irq apb_ppc_clear cfg_sec_resp cfg_non_sec cfg_ap

AHB PPC EXP 0

AHB PPC EXP 1

MPC SSRAM ahb_ppc_irq ahb_ppc_clear cfg_sec_resp cfg_non_sec chg_ap ahb_ppc_irq ahb_ppc_clear cfg_sec_resp cfg_non_sec chg_ap secure_error_irq

Security Expansion Signals

SMSCEXPSTATUS[3:1]

SMSCEXPCLEAR[3:1]

NSMSCEXP[0]

SPERIPHPPCEXPSTATUS[0]

SPERIPHPPCEXPCLEAR[0]

SECRESPCFG

PERIPHNSPPCEXP0[15:0]

PERIPHPPPCEXP0[15:0]



SECRESPCFG





SECRESPCFG



SMAINPPCEXPSTATUS[0]

SMAINPPCEXPCLEAR[0]

SECRESPCFG

MAINNSPPCEXP0[15:0]

MAINPPPCEXP0[15:0]

SMAINPPCEXPSTATUS[1]

SMAINPPCEXPCLEAR[1]

SECRESPCFG

MAINNSPPCEXP1[15:0]

MAINPPPCEXP1[15:0]

SMPCEXPSTATUS[2]

Table 6-1 : Security Expansion signals connectivity


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DAI 0547C

Issue C


The following table lists the peripherals that are controlled by SMSCEXP.

Each MSC <n> interface is controlled by SMSCEXPSTATUS[n] and SMSCEXPCLEAR [n].

SMSCEXP Interface Number <n>

0

1

2

3

15:4

Name

Reserved

DMA 1

DMA 2

DMA 3

Reserved

Table 6-2 : Mapping of APB PPC EXP 0

The following table lists the peripherals that are controlled by PERIPHERAL PPC EXP 0.

Each APB <n> interface is controlled by PERIPHNSPPCEXP0[n] and PERIPHPPPCEXP0[n].

13

14

15

APB PPC EXP 0 Interface Number <n> Name

0

1

USER MEM APB0

USER MEM APB0

3:2

4

5

12:6

Reserved

NPU APB0

NPU APB1

Reserved

SSRAM Memory Protection Controller (MPC)

QSPI Memory Protection Controller (MPC)

DDR4 Memory Protection Controller (MPC)

Table 6-3 : Peripherals Mapping of APB PPC EXP 0



4

5

6

7

8

15:9

1

2

3

APB PPC EXP 1 Interface Number <n>

0

Name




FPGA - PL022 (SPI Shield 0)



SBCon (I2C – Shield1)

Reserved

I2C DDR4 EPROM

Reserved



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DAI 0547C

Issue C



7

8

9

10

11

15:12

3

4

5

6

1

2

APB PPC EXP 2 Interface Number <n>

0

Name


FPGA - I2S (Audio)


UART0 - UART_F[0]

UART1 - UART_F[1]

UART2 - UART_F[2]

UART3 - UART Shield0

UART4 - UART Shield1

UART5 - UART_F[3]

Reserved

CLCD

RTC

Reserved


The following table lists the peripherals that are controlled by MAIN PPC EXP 0.

Each APB <n> interface is controlled by MAINNSPPCEXP0[n] and MAINPPPCEXP0[n].

4

5

6

7

8

15:9

1

2

3

AHB PPC EXP 0 Interface Number <n>

0

Name

GPIO_0

GPIO_1

GPIO_2

GPIO_3

User AHB interface 0




Ethernet and USB

Reserved

Table 6-6 : Peripherals Mapping of AHB PPC EXP 0


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The following table lists the peripherals that are controlled by MAIN PPC EXP 1.

Each APB <n> interface is controlled by MAINNSPPCEXP1[n] and MAINPPPCEXP1[n].

DAI 0547C

Issue C


1

2

AHB PPC EXP 1 Interface Number <n>

0

3

15:4

Name

Reserved

DMA 1

DMA 2

DMA 3

Reserved

Table 6-7 : Peripherals Mapping of AHB PPC EXP 1


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7 Interrupt Map

DAI 0547C

Issue C

7 Interrupt Map

The following table shows how the interrupts in this SMM extend the SSE-300 interrupt map by adding to the expansion area.

Interrupt Input Interrupt Source

IRQ[0] Non-secure Watchdog reset Request

IRQ[1] Non-secure Watchdog Interrupt

IRQ[2] SLOWCLK Timer

IRQ[3] Timer 0

IRQ[4] Timer 1

IRQ[5] Timer 2

IRQ[6] Reserved

IRQ[7] Reserved

IRQ[8] Reserved

IRQ[9] MPC Combined (Secure)

IRQ[10] PPC Combined (Secure)

IRQ[11] MSC Combined (Secure)

IRQ[12] Bridge Error Combined Interrupt (Secure)

IRQ[13] Reserved

IRQ[14] MGMT_PPU

IRQ[15] SYS_PPU

IRQ[16] CPU0_PPU

IRQ[17] Reserved

IRQ[18] Reserved

IRQ[19] Reserved

IRQ[20] Reserved

IRQ[21] Reserved

IRQ[22] Reserved

IRQ[23] Reserved

IRQ[24] Reserved

IRQ[25] Reserved

IRQ[26]

IRQ[27]

IRQ[28]

IRQ[29]

IRQ[30]

IRQ[31]

DEBUG_PPU

TIMER 3 AON

CPU0CTIIRQ0

CPU0CTIIRQ01

Reserved

Reserved

IRQ[32]

IRQ[33]

IRQ[34]

IRQ[35]

IRQ[36]

IRQ[37]

System timestamp counter interrupt

UART 0 Receive Interrupt

UART 0 Transmit Interrupt




Source

SSE-300

FPGA

System


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DAI 0547C

Issue C

7 Interrupt Map

Interrupt Input Interrupt Source

IRQ[38] UART 2 Transmit Interrupt

IRQ[39]

IRQ[40]



IRQ[41]

IRQ[42]

IRQ[43]

IRQ[44]

IRQ[45]

IRQ[46]



UART 0 Combined Interrupt




IRQ[64]

IRQ[65]

IRQ[66]

IRQ[67]

IRQ[68]

IRQ[69]

IRQ[70]

IRQ[71]

IRQ[87:72]

IRQ[103:88]

IRQ[119:104]

IRQ[123:120]

IRQ[124]

IRQ[125]

IRQ[126]

IRQ[127]

IRQ[130:128]

IRQ[47]

IRQ[48]

IRQ[49]

IRQ[50]

IRQ[51]

IRQ[52]

IRQ[53]

IRQ[54]

IRQ[55]

IRQ[56]

IRQ[59:57]

IRQ[60]

IRQ[61]

IRQ[62]

IRQ[63]


UART Overflow (0, 1, 2, 3, 4 & 5)

Ethernet

Audio I 2 S

Touch Screen

USB

SPI ADC

SPI (Shield 0)

SPI (Shield 1)

U55 Interrupt

Reserved

DMA 1 Error Interrupt

DMA 1 Terminal Count Interrupt

DMA 1 Combined Interrupt







GPIO 0 Combined Interrupt




GPIO 0 individual interrupts







Reserved

Source

FPGA

System

Table 7-1 : Combined SSE-300 and FPGA System Interrupt Map


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7.1

UART Interrupts

There are six CMSDK UARTs in the system, each with the following interrupt pins:

DAI 0547C

Issue C

7 Interrupt Map

• TXINT

• RXINT

• TXOVRINT

• EXOVRINT

• UARTINT

The TXINT, RXINT and UARTINT interrupt signals of each UART drive a single interrupt input of the SSE-

300 Example Subsystem. In addition, the TXOVERINT and EXOVRINT interrupt signals of all six UARTs, twelve signals in all, are logically ORed together to drive IRQ[47].


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Example Subsystem for MPS3 Application Note AN547

8 Shield Support

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8 Shield Support

This SMM supports external shield devices. To enable the Shield support, two SPI, two UART and two I 2 C interfaces are multiplexed with GPIO over the Shield Headers.

V2M-MPS3 – HBI0309

FPGA Application Note

SPI x2

I2C x2

UART x2

GPIO x3

Shield0

Shield1

Figure 8-1 : Shield Device Expansion

Multiplexing is controlled by the alternative function output from the associated GPIO Register. An experimental second alternative function is multiplexed for pins 1-9 of Shield 0 and these are controlled through GPIOALT2 in the FPGAIO Registers at address offset 0x0C .

The second ALT function is unused on AN547 and is not shown in the following table.

MPS3

SH0_IO0

SH0_IO1

SH0_IO2

SH0_IO3

GPIO

GPIO0_0

GPIO0_1

GPIO0_2

GPIO0_3

ALT Function 1

UART3 RXD – SH0_RXD

UART3 TXD – SH0_TXD

-

-

ALT Description 1

Shield 0 UART Receive

Shield 0 UART Transmit

-

-

SH0_IO4

SH0_IO5

SH0_IO6

SH0_IO7

SH0_IO8

SH0_IO9

SH0_IO10

GPIO0_4

GPIO0_5

GPIO0_6

GPIO0_7

GPIO0_8

GPIO0_9

GPIO0_10

-

-

SPI3 SS – SH0_nCS

-

-

-

-

-

-

-

-

-

-

Shield 0 SPI Chip Select


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MPS3 GPIO ALT Function 1

SH0_IO11

SH0_IO12

SH0_IO13

SH0_IO14

GPIO0_11

GPIO0_12

GPIO0_13

GPIO0_14

SPI3 MOSI – SH0_DO

SPI3 MISO – SH0_DI

SPI3 SCK – SH0_CLK

SBCON2 SDA – SH0_SDA

GPIO0_15

GPIO1_0

GPIO1_1

GPIO1_2

GPIO1_3

GPIO1_4

GPIO1_5

GPIO1_6

GPIO1_7

GPIO1_8

GPIO1_9

GPIO1_10

GPIO1_11

GPIO1_12

GPIO1_13

GPIO1_14

GPIO1_15

SH0_IO15

SH1_IO0

SH1_IO1

SH1_IO2

SH1_IO3

SH1_IO4

SH1_IO5

SH1_IO6

SH1_IO7

SH1_IO8

SH1_IO9

SH1_IO10

SH1_IO11

SH1_IO12

SH1_IO13

SH1_IO14

SH1_IO15

SBCON2 SCL – SH0_SCL

UART4 RXD – SH1_RXD

UART4 TXD – SH1_TXD

-

-

-

-

-

-

-

-

SPI4 SS – SH1_nCS

SPI4 MOSI – SH1_DO

SPI4 MISO – SH1_DI

SPI4 SCK – SH1_CLK

SBCON3 SDA – SH1_SDA

SBCON3 SCL – SH1_SCL

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8 Shield Support

ALT Description 1

Shield 0 SPI Data Out

Shield 0 SPI Data In

Shield 0 SPI Clock

Shield 0 I2C Data

Shield 0 I2C Clock

Shield 1 UART Receive

Shield1 UART Transmit

-

-

-

-

-

-

-

-

Shield 1 SPI Chip Select

Shield 1 SPI Data Out

Shield 1 SPI Data In

Shield 1 SPI Clock

Shield 1 I2C Data

Shield 1 I2C Clock

Table 8-1 : Shield Alternative Function Pinout


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9 ZIP Bundle Description

9.1

Overall Structure

The accompanying .zip

bundle contains:

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• This Application Note Document.

• An example Keil® MDK Version 5.31 software project, that can be run on the MPS3 board peripherals and interfaces.

• Boardfiles/ directory containing the directory structure and files to be loaded onto the MPS3 SD Card.

This is required to configure the MPS3 board to load and run this implementation.

9.2

Bundle Directory Tree/Structure

The directory tree structure of the bundle is shown below.

|-- Boardfiles

| |-- MB

| | |-- HBI0309B

| | |-- HBI0309C

| |-- SOFTWARE

| | |-- an547_st.axf

| |-- config.txt

|-- Docs

| |-- DAI0547C_SSE300_with_Cortex-M55_and_Ethos-U55_FPGA_for_mps3.pdf

|-- Software

| |-- selftest

| |-- apaaci

| |-- apclcd

| |-- apgpio

| |-- aplan

| |-- apleds

| |-- apmain

| |-- apmem

| |-- apqspi

| |-- aprtc


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| |-- apssp

| |-- aptimer

| |-- aptsc

| |-- apuart

| |-- apusb

| |-- RTE

| |-- v2m_mps3

| |-- an547_st.axf

| |-- move.bat

| |-- selftest_mpb.uvoptx

| |-- selftest_mpb.uvprojx

|-- Licence.pdf

|-- Release_Notes.txt

|-- revision_history.txt

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10 Board Revision And Support

10 Board Revision And Support

10.1

Identifying the MPS3 board revision

The bundle supports MPS3 board revisions B and C. The board revision, if not known, can be identified from the silk screen text, inside a marked box, on the board as shown in the diagram below :

Board Part Number and Revision

Figure 10-1 : MPS3 board revision identifier

In this picture the part number is “HBI0309 B ” , which indicates that the board is revision B.

10.2

Bundle support for specific MPS3 board revisions.

There are two subdirectories in the Boardfiles/MB/ directory that correspond to the two supported revisions:

•

•

HBI0309B

HBI0309C

The contents of each of these directories, within the provided .zip

bundle, are identical but the MCC only uses

the contents from the directory name that matches the board part number and revision in use. See 10.1 for

further details on how to identify the board part number and revision.

Only files modified within the directory name that align with the MPS3 board part number and revision are used by the MCC. Care must be taken to ensure that the correct directory contents are modified if required.


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DAI 0547C

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11 Using AN547 on the MPS3 Board

11 Using AN547 on the MPS3 Board

11.1

Pre-Requisites

Before attempting to use the board, you must:

• Read the Arm® MPS3 FPGA Prototyping Board Technical Reference Manual . o In particular, become familiar with the description of the configuration and boot flow.

You must be able to:

• Connect a PC to the MPS3 board using a USB connection (which is required to load files onto the MPS3 board SD card to run the built .bit

file from the FPGA build flow).

• Power the MPS3 board.

• The MPS3 board appears as a mapped drive named “V2M_MPS3”.

• Understand how to power up, reset and establish a serial terminal over the USB connection to a host PC.

11.2

Loading a prebuilt image onto the MPS3 Board

To load the prebuilt AN547 image, follow these steps:

1.

Power up the MPS3 board using the PBON push button and wait for the V2M_MPS3 drive to appear.

2.

Format the V2M_MPS3 drive and copy the contents of <install_dir>/Boardfiles and paste them into the root directory of the attached V2M_MPS3 drive.

Note: You might want to manually modify and merge the contents for certain configuration files.

Alternatively, you can restore the existing configuration files from the /Boardfiles directory. The affected configuration files are: a.

<install_dir>/Boardfiles/config.txt b.

<install_dir>/Boardfiles/MB/HBI0309C/board.txt

3.

Eject the V2M_MPS3 volume from your computer to unmount the drive.

4.

Power cycle the MPS3 board using the PBRST push button and then launch MCC firmware update and FPGA configuration by pressing PBON push button. The LEDs flash rapidly to indicate that a new MCC firmware is being downloaded, (this only occurs the first time the MCC firmware is updated), and that the prebuilt image is being downloaded onto the board. When the bar LEDs next to PBRST button show green and user LED’s

UL0-7 are alternatively lit, the FPGA is programmed.

5.

The color LCD touch screen shows the MPS3 splash screen. Simultaneously, if you have configured the UART to run, the debug UART terminal shows the selftest menu for Application Note AN547.

6.

If the MPS3 board does not boot correctly, refer to the log.txt

in the root directory of the MPS3 board which provides a log file of the files loaded at bootup.


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11.3

UART Serial Ports

Four serial ports are supported on this implementation and are accessible through the MPS3 board Debug USB port:

• Serial Port 0 is connected to the MCC and outputs debug information about the status of the MCC.

• Serial Port 1 is connected to the UART 0.



The logical<>physical mapping of the Serial Ports on a host PC can be confusing due to the way the driver may allocate the port numbers. The Serial Port presented with the lowest number aligns to Serial Port 0 above .

11.4

UART Serial Port Terminal Emulator Settings

All serial ports on this implementation use the following terminal/serial port settings:

•

Baud Rate: 115200 bps

•

•

•

New-Line: CR (Serial port 0) And LF (Serial Port 1,2 and 3 Only)

Data: 8 bits

Parity: none

•

Stop: 1 bit

•

Flow control: none

11.5

MPS3 USB Serial port drivers for Windows

For information on installing drivers to support USB serial port on MPS3 see: https://community.arm.com/dev-platforms/w/docs/381/accessing-mps3-serial-ports-in-windows-10


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4

3



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11.6

MCC Memory mapping

The MCC on the MPS3 has some visibility into the memory for initiating boot memory areas and configuring peripherals if needed. This access is limited to just 4x 64MB, so it is unable to cover the whole map, hence only those regions which are necessary for the design functionality are mapped.

The following table shows the memory map as viewed from the MCC.

2

CS

1

MCC SMB Address MCC Internal SSE-300 Address

0x0000_0000 - 0x0007_FFFF 0x6000_0000 - 0x6007_FFFF 0x0000_0000 - 0x0007_FFFF

0x0100_0000 – 0x011F_FFFF 0x6100_0000 - 0x6107_FFFF 0x1000_0000 - 0x1007_FFFF

0x0200_0000 - 0x0207_FFFF 0x6200_0000 - 0x621F_FFFF 0x0100_0000 - 0x011F_FFFF

0x0300_0000 - 0x031F_FFFF 0x6300_0000 - 0x631F_FFFF 0x1100_0000 - 0x111F_FFFF

0x0400_0000 - 0x04FF_FFFF 0x6400_0000 - 0x64FF_FFFF 0x4100_0000 - 0x41FF_FFFF

Size

512KB

512KB

2MB

2 MB

16 MB

IOFPGA

ITCM NS

ITCM S

FPGA SRAM NS

FPGA SRAM S

0x0500_0000 - 0x05FF_FFFF 0x6500_0000 - 0x65FF_FFFF 0x4900_0000 - 0x49FF_FFFF 16 MB



16 MB

16 MB

Low Latency

Peripherals NS

High Latency

Peripherals NS

Low Latency

Peripherals S

High Latency

Peripherals S

0x0800_0000 - 0x0BFF_FFFF 0x6800_0000 - 0x6BFF_FFFF 0x6000_0000 - 0x63FF_FFFF

0x0C00_0000 - 0x0FFF_FFFF 0x6C00_0000 - 0x6FFF_FFFF 0x7000_0000 - 0x73FF_FFFF

64 MB

64 MB

DDR4 NS

DDR4 S

Table 11-1 : MCC memory map table


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12 Software

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12 Software

12.1

Rebuilding software

Requirements:

• The software directory from the download

• Keil  Vision® 5.31 or later

The following instructions apply to the software package provided :

1.

Navigate to <install_dir>/Software/selftest/

2.

Load selftest_mpb.uvprojx

in Keil uVision

3.

Once loaded, the project can be rebuilt by selecting either: o Project - > Build Target o Project - > Rebuild all target files

• The output can then be found in <install_dir>/Software/selftest/an547_st.axf

12.2

Loading software on the MPS3 board

Requirements:

• MPS3 board powered and USB cable connected

• MPS3 USB mass storage open in a file explorer

The following instructions apply to all versions of software:

1.

Copy the software <install_dir>/Software/selftest/an547_st.axf to the board

<MPS3_dir>/Software folder

2.

Navigate to <MPS3_dir>MB/HBI0309C/AN547 and open the images.txt

file in a text editor

3.

Add a new line for the new software you wish to run and make sure the other lines are commented out, for example :

;IMAGE0FILE: \SOFTWARE\selftest.axf; - selftest uSD

IMAGE0FILE: \SOFTWARE\an547_st.axf ; - selftest uSD

(the compiled an547_st.axf

image is uncommented, which is therefore selected and selftest.axf

is commented out)

The MPS3 can now be booted according to the instructions in the Arm® MPS3 FPGA Prototyping Board Getting

Started Guide that is supplied with the MPS3 board.


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13 Debug

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13 Debug

In this SMM, the subsystem includes an example debug infrastructure that instances DAP-Lite2, debug timestamp generator, Cortex-M55 TPIU, and MCU debug ROM table. The DAP-Lite2 is compliant with Arm® Debug

Interface Architecture Specification ADIv6.0.

For more information about debug infrastructure, see the Arm® Corstone™ SSE -300 Example Subsystem Technical

Reference Manual.

13.1

Debug Connectivity

The following table shows the supported connectivity between the MPS3 Board debug connectors and the

supported debug in the SMM. See Figure 13-3 : MPS3 Board Debug Connector Locations for the locations of the

debug connectors on the board.

Debug Connector Type

20 pin Cortex debug and ETM

P-JTAG

Debug

Yes

SWD

Yes

4-bit Trace 16-bit Trace

No No

20 pin IDC

Mictor 38

Yes

Yes

Yes

Yes

No

Yes

No

No

Table 13-1 : Debug Connectivity and Support

13.2

Debug support for Keil MDK

Debug has been tested using Keil uVision 5.31 with Arm Keil ULINK ™ Pro Armv8-M Debugger and CMSIS-DAP

Armv8-M Debugger.

Apply the following debug settings if using a ULINK Pro Armv8-M Debugger:

• Port: JTAG

• Reset: Autodetect

• Connect: Normal


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Figure 13-1 :Keil MDK debug configuration


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Apply the following debug settings if using CMSIS-DAP Armv8-M Debugger:

• Port: SW

• Reset: Autodetect

• Connect: Normal

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Figure 13-2 :Keil MDK debug configuration

13.3

Trace support for Keil MDK

It is planned to include trace support for SSE-300 in future versions of the Keil Tool. Please follow the announcements of tool and pack updates related to the platform.


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DAI 0547C

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13 Debug

13.4

Debug and Trace support for Arm Development Studio

Development Studio 2020.1 Silver edition or better is required as this provides the support for the subsystem in this implementation and was the version used for testing of this application note.

13.4.1

Establishing a Debug Session

To estalish a debug connection to the Cortex-M55 processor, follow these steps:

Steps:

1.

Ensure the Arm DSTREAM debug probe is : a.

Powered, and connected to the host running the Development Studio software. b.

Connected to the MPS3 using the 20-pin Cortex / 20-pin IDC / Mictor 38 port on the MPS3 as shown below:

20-pin Cortex

20-pin IDC

Mictor 38

Figure 13-3 : MPS3 Board Debug Connector Locations


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13 Debug

2.

Open the Debug Configurations dialog box, by right-clicking in the Debug Control window and selecting debug configurations. This will open the debug configuration window. a.

Double left click on the Generic Arm C/C++ application, this will create a new configuration.

b.

In the connection tab, in the search bar, enter “MPS3”, and select the Cortex -M55 under Cortex-M

Prototyping System (MPS3) Cortex-M55 (SSE-300 Subsystem) as shown in the example below.

Figure 13-4 : Arm DS debug configurations - Connection


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Example Subsystem for MPS3 - Application Note AN547 c.

Next, in the Debugger tab, make sure that the run control is set to Connect only

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Figure 13-5 : Arm DS debug configurations - Debugger


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13 Debug d.

Next, a connection to the DSTREAM needs to be setup. To do this, select the connection tab, select

Browse (highlighted in red), a new window will open giving a list of all possible DSTREAM’s. Choose your DSTREAM and click select (highlighted in blue).

Figure 13-6 : Arm DS connection browser e.

Now click the Apply button followed by the Debug button to start your debug session.

3.

Program execution at this stage can be either single-stepped or set to Run .


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13.4.2

Trace in Debug session

Follow steps in section 13.4.1 and before step 2. e. implement the following steps :

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1.

Click the Edit button next to “DTSL Options” shown below . Connect the debug probe to either 20-pin IDC /

Mictor 38 for trace to work.

Figure 13-7 : Arm DS debug configurations – DTSL Options


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2.

A new window will open, on the first tab select “DSTREAM 4GB Trace Buffer” as shown below :

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3.

On the CortexM55 tab, check the “Enable Cortex M55 core trace” box and then click Apply and then OK


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