Infineon SAK-TC1724N-192F80HR AC Microcontroller Data Sheet

32-Bit

Microcontroller

TC1724

32-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2014-06

Microcontrollers

Edition 2014-06

Published by

Infineon Technologies AG

81726 Munich, Germany

©

2014 Infineon Technologies AG

All Rights Reserved.

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (

www.infineon.com

).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

32-Bit

Microcontroller

TC1724

32-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2014-06

Microcontrollers

Table of Contents


1

2

2.1

3

Summary of Features

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

System Overview of the TC1724

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Pinning

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Identification Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4

5.3

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.3.11.1

5.3.11.2

5.3.11.3

5.3.11.4

5.4

5.4.1

5.4.2

5

5.1

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.5.1

Electrical Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-34

Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39

Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40

Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-45

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47

Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47

Power Sequencing 5V Supply Only . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

Power Sequencing 3.3V Supply Only . . . . . . . . . . . . . . . . . . . . . . . . 5-50

Power Sequencing all Voltages supplied from External . . . . . . . . . . 5-52

Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54

EVR Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57

Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60

ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . 5-62

JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63

DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65

Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . 5-69

SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72

ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75

Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

Data Sheet I-1

TC1724

V1.2, 2014-06

TC1724

5.4.3

5.4.4

5.5


Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78

Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81

Data Sheet I-2 V1.2, 2014-06

TC1724


1 Summary of Features

The SAK-TC1724F-192F133HL / SAK-TC1724F-192F133HR has the following features:

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Single precision Floating Point Unit (FPU)

– 133 MHz operation at full temperature range

• 32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 8 Kbyte Parameter Memory (PRAM)

– 24 Kbyte Code Memory (CMEM)


• Multiple on-chip memories

– 1.5 Mbyte Program Flash Memory (PFLASH) with ECC

– 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 120 Kbyte Data Memory (LDRAM)

– Instruction Cache: up to 8Kbyte (ICACHE, configurable)

– 24 Kbyte Code Scratchpad Memory (SPRAM)

– Data Cache: up to 4 Kbyte (DCACHE, configurable)

– 8 Kbyte Overlay Memory (OVRAM)

– 16 Kbyte BootROM (BROM)

• 16-Channel DMA Controller

• Sophisticated interrupt system with 2

× 255 hardware priority arbitration levels serviced by CPU or PCP2

• High performing on-chip bus structure

– 64-bit Local Memory Buses between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (LFI Bridge)

• Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection

– Four High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction

– One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices

– One High-Speed Micro Link interface (MLI) for serial inter-processor communication

– One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer

– One FlexRay

TM

module with 2 channels (E-Ray).

Data Sheet 1-1 V1.2, 2014-06

TC1724


– One General Purpose Timer Array Module (GPTA) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex

Input/Output management

– Two Capture/Compare Unit 6 (CAPCOM6) kernels

– Two General Purpose Timer (GPT12) modules

• 28 analog input lines for ADC

– 2 independent kernels (ADC0 and ADC1)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

– Broken wire detection

• 2 different FADC input channels

– channels with impedance control and overlaid with ADC1 inputs

– Extreme fast conversion, 21 cycles of

f

FADC

clock

– 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)

• 95 digital general purpose I/O lines (GPIO)

• Digital I/O ports with 3.3 V capability

• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)

• Dedicated Emulation Device chip available (TC1724ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface

• Power Management System

• Clock Generation Unit with PLL

Data Sheet 1-2 V1.2, 2014-06

TC1724


The SAK-TC1724N-192F133HR has the following features:




































Data Sheet 1-3 V1.2, 2014-06

TC1724









f

FADC

clock










Data Sheet 1-4 V1.2, 2014-06

TC1724


The SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR has the following features:




































Data Sheet 1-5 V1.2, 2014-06

TC1724









f

FADC

clock










Data Sheet 1-6 V1.2, 2014-06

TC1724


Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage

• The package and the type of delivery.

For the available ordering codes for the TC1724 please refer to the “Product Catalog

Microcontrollers”

, which summarizes all available microcontroller variants.

This document describes the derivatives of the device.The

Table 1

enumerates these

derivatives and summarizes the differences.

Table 1 TC1724 Derivative Synopsis

Derivative

SAK-TC1724F-192F133HL

Ambient

Temperatur e Range (T

A

)

-40 o

C to

+125 o

C

SAK-TC1724F-192F133HR

1)

-40 o

C to

+125 o

C

SAK-TC1724N-192F133HR -40 o

C to

+125 o

C

SAK-TC1724N-192F80HL -40 o

C to

+125 o

C

CPU/PCP

Freq.

133 MHz

133 MHz

133 MHz

80 MHz

Flash

Size

1.5 MB

1.5 MB

1.5 MB

1.5 MB

ERAY Wire

Yes

Yes

No

No

Bond

Material

Au

Cu

Cu

Au

SAK-TC1724N-192F80HR

2)

-40 o

C to

+125 o

C

80 MHz 1.5 MB No Cu

1) This derivative has the same features as the SAK-TC1724F-192F133HL, except the wire-bonding material.

2) This derivative has the same features as the SAK-TC1724N-192F80HL, except the wire-bonding material.

Data Sheet 1-7 V1.2, 2014-06

TC1724


2 System Overview of the TC1724

The TC1724 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications:

• Reduced Instruction Set Computing (RISC) processor architecture

• Digital Signal Processing (DSP) operations and addressing modes

• On-chip memories and peripherals

DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost. On-chip memory and peripherals are designed to support even the most demanding high-bandwidth real-time embedded control-systems tasks.

Additional high-level features of the TC1724 include:

• Efficient memory organization: instruction and data scratch memories, caches

• Serial communication interfaces – flexible synchronous and asynchronous modes

• Peripheral Control Processor – standalone data operations and interrupt servicing

• DMA Controller – DMA operations and interrupt servicing

• General-purpose timers

• High-performance on-chip buses

• On-chip debugging and emulation facilities

• Flexible interconnections to external components

• Flexible power-management

The TC1724 is a high-performance microcontroller with TriCore CPU, program and data memories, buses, bus arbitration, an interrupt controller, a peripheral control processor and a DMA controller and several on-chip peripherals. The TC1724 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements.

The TC1724 offers several versatile on-chip peripheral units such as serial controllers, timer units, CAPCOM6 and Analog-to-Digital converters. Within the TC1724, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral

Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the

TC1724 ports are reserved for these peripheral units to communicate with the external world.

Data Sheet 2-1 V1.2, 2014-06

TC1724


2.1

Block Diagrams

Figure 1

shows the block diagram of the SAK-TC1724F-192F133HL / SAK-TC1724F-

192F133HR.

ASC0

ASC1

E-Ray

(2 channels)

PMI

16 KB SPRAM

8 KB ICACHE

(Configurable)

FPU

TriCore

CPU

TC1.3.1

133MHz

CPS

Local Memory Bus (LMB)

PMU

1,5 MB PFlash

64 KB Dflash

16 KB BROM

8 KB OVRAM

LFI Bridge

DMI

116 KB LDRAM

4 KB DCACHE

(Configurable)

M

DMA

16 channels

M/S

LBCU

Abbreviations:

ICACHE:

DCACHE

SPRAM:

LDRAM:

OVRAM:

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

Instruction Cache

Data Cache

Scratch-Pad RAM

Local Data RAM

Overlay RAM

Boot ROM

Program Flash

Data Flash

Parameter RAM in PCP

Code RAM in PCP

1.3V, 3.3V

Int. Supply

Optional Ext. Supply

EVR

Embedded

Voltage

Regulator

5V, 3.3V

Single-source

Ext. Supply

OCDS

L1 Debug

Interface

8 KB PRAM

System Peripheral Bus

(SPB)

Interrupt

System

JTAG/DAP

MLI0

PCP2

Core

STM

MemCheck

24 KB CMEM

SCU

FCE

CAPCOM

(CCU60, CCU61)

Ports

GPT12

(GPT 120)

GPT12

(GPT 121)

GPTA 0

SBCU

PLL

E-RAY

PLL

f

E -Ray

f

CPU

BMU

SSC0

SSC1

SSC2

5V

Ext. ADC Supply

ADC0

(5V max,

16 channels )

ADC1

(5V max,

24 channels )

FADC

(3.3V max,

2 differential channels )

16

8

4

Ext.

Request

Unit

MultiCAN

(3 Nodes,

64 MO)

MSC0

SSC3

BlockDiagram

TC1724F

V0.8

Figure 1 SAK-TC1724F-192F133HL / SAK-TC1724F-192F133HR Block

Diagram

Data Sheet 2-2 V1.2, 2014-06

TC1724


Figure 2

shows the block diagram of the SAK-TC1724N-192F133HR.

ASC0

ASC1

CAPCOM

(CCU60, CCU61)

GPT12

(GPT 120)

GPT12

(GPT 121)

GPTA 0

PMI

16 KB SPRAM

8 KB ICACHE

(Configurable)

FPU

TriCore

CPU

TC1.3.1

133MHz

CPS


PMU

1,5 MB PFlash

64 KB Dflash

16 KB BROM

8 KB OVRAM

LFI Bridge

DMI

116 KB LDRAM

4 KB DCACHE

(Configurable)

M

DMA

16 channels

M/S

LBCU

Abbreviations:

ICACHE:

DCACHE

SPRAM:

Instruction Cache

Data Cache

Scratch-Pad RAM

LDRAM:

OVRAM:

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

Local Data RAM

Overlay RAM

Boot ROM

Program Flash

Data Flash


Code RAM in PCP

1.3V, 3.3V

Int. Supply


EVR

Embedded

Voltage

Regulator

5V, 3.3V

Single-source

Ext. Supply

OCDS

L1 Debug

Interface

8 KB PRAM


(SPB)

Interrupt

System

JTAG/DAP

MLI0

PCP2

Core

STM

MemCheck

24 KB CMEM

SCU

FCE

Ports

SBCU

PLL

f

CPU

BMU

SSC0

SSC1

SSC2

5V

Ext. ADC Supply

ADC0

(5V max,

16 channels )

ADC1

(5V max,

24 channels )

FADC

(3.3V max,


16

8

4

Ext.

Request

Unit

MultiCAN

(3 Nodes,

64 MO)

MSC0

SSC3

BlockDiagram

TC1724N

V0.8

Figure 2 SAK-TC1724N-192F133HR Block Diagram

Data Sheet 2-3 V1.2, 2014-06

TC1724


Figure 3

shows the block diagram of the SAK-TC1724N-192F80HL / SAK-TC1724N-

192F80HR.

ASC0

ASC1

CAPCOM

(CCU60, CCU61)

GPT12

(GPT 120)

GPT12

(GPT 121)

GPTA 0

PMI

16 KB SPRAM

8 KB ICACHE

(Configurable)

FPU

TriCore

CPU

TC1.3.1

80MHz

CPS


PMU

1,5 MB PFlash

64 KB Dflash

16 KB BROM

8 KB OVRAM

LFI Bridge

DMI

116 KB LDRAM

4 KB DCACHE

(Configurable)

M

DMA

16 channels

M/S

LBCU

Abbreviations:

ICACHE:

DCACHE

SPRAM:

LDRAM:

OVRAM:

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

Instruction Cache

Data Cache

Scratch-Pad RAM

Local Data RAM

Overlay RAM

Boot ROM

Program Flash

Data Flash


Code RAM in PCP

1.3V, 3.3V

Int. Supply


EVR

Embedded

Voltage

Regulator

5V, 3.3V

Single-source

Ext. Supply

OCDS

L1 Debug

Interface

8 KB PRAM


(SPB)

Interrupt

System

JTAG/DAP

MLI0

PCP2

Core

STM

MemCheck

24 KB CMEM

SCU

FCE

Ports

SBCU

PLL

f

CPU

BMU

SSC0

SSC1

SSC2

5V

Ext. ADC Supply

ADC0

(5V max,

16 channels )

ADC1

(5V max,

24 channels )

FADC

(3.3V max,


16

8

4

Ext.

Request

Unit

MultiCAN

(3 Nodes,

64 MO)

MSC0

SSC3

BlockDiagram

TC1724N

V0.8

Figure 3 SAK-TC1724N-192F80HL / SAK-TC1724N-192F80HR Block Diagram

Data Sheet 2-4 V1.2, 2014-06

TC1724


Figure 4

shows the block diagram of the SAK-TC1724F-192F80HR.

ASC0

ASC1

E-Ray

(2 channels)

PMI

16 KB SPRAM

8 KB ICACHE

(Configurable)

FPU

TriCore

CPU

TC1.3.1

80MHz

CPS


PMU

1,5 MB PFlash

64 KB Dflash

16 KB BROM

8 KB OVRAM

LFI Bridge

DMI

116 KB LDRAM

4 KB DCACHE

(Configurable)

M

DMA

16 channels

M/S

LBCU

Abbreviations:

ICACHE:

DCACHE

SPRAM:

LDRAM:

OVRAM:

BROM:

PFlash:

DFlash:

PRAM:

CMEM:

Instruction Cache

Data Cache

Scratch-Pad RAM

Local Data RAM

Overlay RAM

Boot ROM

Program Flash

Data Flash


Code RAM in PCP

1.3V, 3.3V

Int. Supply


EVR

Embedded

Voltage

Regulator

5V, 3.3V

Single-source

Ext. Supply

OCDS

L1 Debug

Interface

8 KB PRAM


(SPB)

Interrupt

System

JTAG/DAP

MLI0

PCP2

Core

STM

MemCheck

24 KB CMEM

SCU

FCE

CAPCOM

(CCU60, CCU61)

Ports

GPT12

(GPT 120)

GPT12

(GPT 121)

GPTA 0

SBCU

PLL

E-RAY

PLL

f

E -Ray

f

CPU

BMU

SSC0

SSC1

SSC2

5V

Ext. ADC Supply

ADC0

(5V max,

16 channels )

ADC1

(5V max,

24 channels )

FADC

(3.3V max,


16

8

4

Ext.

Request

Unit

MultiCAN

(3 Nodes,

64 MO)

MSC0

SSC3

BlockDiagram

TC1724F

V0.8

Figure 4 SAK-TC1724F-192F80HR Block Diagram

Data Sheet 2-5 V1.2, 2014-06

TC1724

3 Pinning

Figure 5

shows the logic symbol for TC1724

Pinning

General Control

PORST

TESTMODE

ESR0

ESR1

OCDS /

JTAG Control

Analog Inputs

Analog Power

Supply

Digital Circuitry

Power Supply

TRST

TCK / DAP0

TMS / DAP1

AN[16:0],

AN19, AN23,

AN25,

AN[39:32]

V

DD M

V

SSM

V

AR EF0

V

AGN D 0

V

5

V

D D

V

D D P

V

SS

EVR Pass

Device Gate

V

PD G

4

5

4

2

1

Figure 5

TC172 4

12

9

Port 0

Port 1

14

16

Port 2

2

16

Port 3

Port 4

9

Port 5

Port 8

9

4

Port 9

Port 11

4

Port 12

Alternate Functions

GPTA, SCU, E-RAY

1)

CCU6

, MSC0,

SCU, GPTA, SSC1,

OCDS, CCU6, GPT12

GPTA, SSC0/1, MSC0, MLI0,

CCU6, GPT12

GPTA, ASC0/1, SSC0/1, SCU,

CAN, MSC0

GPTA, SCU,

CCU6, GPT12

GPTA, E-RAY 1) , SSC0/2, CAN,

CCU6, GPT12, SCU, ADC1

CCU6, GPT12, SSC3, GPTA

GPTA, CCU6, CAN, OCDS/JTAG

Overlaid digital /analog inputs

Overlaid digital /analog inputs

XTAL1

XTAL2 Oscillator

1)Only available for

SAK -TC1724F-192F133HL, SAK- TC1724F-192F133HR

TC1724_LogSym_144

TC1724 Logic Symbol

Data Sheet 3-1 V1.2, 2014-06

TC1724

Pinning

REQ7/CC62/CC62INA/B/CAPINA/B/SLSO20/OUT40/IN40/P5.0

SLSO21/OUT41/IN41/P5.1

COUT62/SLSO22/OUT42/IN42/P5.2

SLSO23/OUT43/IN43/P5.3

RXDCAN2/OUT80/P9.0

TXDCAN2/OUT81/P9.1

SLSI2A/SLSO24/OUT44/IN44/P5.4

MRST2A/OUT45/IN45/P5.5

MTSR2A/OUT46/IN46/P5.6

SCLK2A/OUT47/IN47/P5.7

1)

/P5.15

V

DD

CC60INC/CC60/OUT87/P9.7

COUT60/OUT88/P9.8

CC61/CC61INA/B/OUT6/TXDA1

OUT7/RXDCAN0/TXDB1

1)

/P5.8

COUT61/OUT8/TXENA

COUT63/OUT9/TXENB

1)

1)

/P5.10

/P5.11

CCPOS0A/T12HRB/T3INA/B/AD1EMUX0/SLSO07/OUT19/P5.12

CCPOS1A/T13HRB/T3EUDA/B/OUT20/AD1EMUX1/P5.13

CCPOS2A/T12HRC/T13HRC/T4INA/B/OUT36/AD1EMUX2/RXDA1

1)

/P5.14

V

DDP

1) V

DD

V

V

5

PDG

AN39/DIG19/P12.3

AN38/DIG18/P12.2

AN37/DIG17/P12.1

AN36/DIG16/P12.0

AN35

AN34

AN33

AN32

AN7

AN25/DIG9/P11.9

AN23/DIG7/P11.7

29

30

31

32

25

26

27

28

33

34

35

36

21

22

23

24

17

18

19

20

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

1) This pin is used as standby power supply in emulation device.

TC1724

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

P3.4/MTSR0/OUT88

P3.7/SLSO02/SLSO12/SLSI0/OUT89

P3.3/MRST0/OUT87

P3.2/SCLK0/OUT86

P3.8/SLSO06/TXD1/OUT90/REQ14

P3.6/SLSO01/SLSO11/SLSOANDO1

P3.5/SLSO00/SLSO10/SLSOANDO0

P8.13/OUT4/COUT60

P8.3/SLSI3/CC61INC/CC61/OUT51/SLSO30

P8.4/OUT99/COUT62/SLSO31

ESR0

PORST

ESR1

P1.1/IN17/OUT17/OUT73/T13HRE/CTRAPB

TESTMODE

P1.15/BRKIN/BRKOUT

P1.0/REQ15/IN16/OUT16/OUT72/T3OUT/BRKIN/BRKOUT

TCK/DAP0

TRST

P9.6/TDO/BRKIN/BRKOUT

TMS/DAP1

P9.5/TDI/BRKIN/BRKOUT

V

5

V

DDP

V

DD

V

SS

XTAL2

XTAL1

V

SS

P1.4/IN20/EMGSTOP/OUT20/OUT76/COUT61

P1.3/IN19/OUT19/OUT75/COUT63

P1.11/IN27/IN51/SCLK1B/OUT27/OUT51/CCPOS0C/T2INA/B

P1.10/IN26/IN50/OUT26/OUT50/SLSO17

P1.9/IN25/IN49/MRST1B/OUT25/OUT49/CCPOS1C/T2EUDA/B

P1.8/IN24/IN48/MTSR1B/OUT24/OUT48/CCPOS2C/T4EUDA/B

P4.3/IN31/IN55/OUT31/OUT55/EXTCLK0/T12HRE/CTRAPA

1) Only available for

SAK-TC1724F-192F133HL, SAK-TC1724F-192F133HR

TC1724_QFP144

Figure 6 TC1724 Pinning for PG-LQFP-144-17 package

Table 3-1

Pin Symbol

Port 0

Pin Definitions and Functions (

PG-LQFP-144-17 package)

Ctrl.

Type Function

Data Sheet 3-2 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

121 P0.0

IN0

CCU60

CCU61

HWCFG0

OUT0

OUT56

CCU60

122 P0.1

IN1

SDI1

HWCFG1

OUT1

OUT57

CCU60

123 P0.2

IN2

HWCFG2

OUT2

OUT58

Reserved

124 P0.3

IN3

HWCFG3

OUT3

OUT59

Reserved


PG-LQFP-144-17 package) (cont’d)

Ctrl.

Type Function

I

I

O1

O2

O3

I

I

I

I/O0 A1/

PU

I

O1

O2

O3

I

I/O0 A1/

PU

I

O1

O2

O3

I

I

I/O0 A1/

PU

O1

O2

O3

I

I/O0 A1+/

PU

-

-

Port 0 General Purpose I/O Line 0

GPTA0 Input 0

CC60INA

CC60INB

Hardware Configuration Input 0

GPTA0 Output 0

GPTA0 Output 56

CC60


GPTA0 Input 1

MSC0 Serial Data Input 1


GPTA0 Output 1

GPTA0 Output 57

COUT60


GPTA0 Input 2


GPTA0 Output 2

GPTA0 Output 58


GPTA0 Input 3


GPTA0 Output 3

GPTA0 Output 59

Data Sheet 3-3 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

134 P0.4

IN4

HWCFG4

OUT4

OUT60

EVTO0

135 P0.5

IN5

HWCFG5

OUT5

OUT61

EVTO1

141 P0.6

IN6

HWCFG6

REQ2

OUT6

OUT62

EVTO2

142 P0.7

IN7

HWCFG7

REQ3

OUT7

OUT63

EVTO3



Ctrl.

Type Function

I

I/O0 A1/

PD

I

O1

O2

O3

I

I/O0 A1/

PD

I

I

O1

O2

O3

I

O1

O2

O3

I

I/O0 A1/

PU

I

I

I/O0 A1/

PU

I

O1

O2

O3


GPTA0 Input 4


GPTA0 Output 4

GPTA0 Output 60

MCDS event output 0


GPTA0 Input 5


GPTA0 Output 5

GPTA0 Output 61



GPTA0 Input 6


External Request Input 2

GPTA0 Output 6

GPTA0 Output 62



GPTA0 Input 7



GPTA0 Output 7

GPTA0 Output 63


Data Sheet 3-4 V1.2, 2014-06

TC1724

Pinning

143 P0.14

IN14

REQ4

CCU61

OUT14

OUT70

CCU60

144 P0.15

IN15

REQ5

OUT15

OUT71

CCU60

Port 1

Table 3-1 Pin Definitions and Functions (


Pin Symbol

136 P0.12

IN12

CCU60

CCU61

OUT12

OUT68

TXENA

137 P0.13

IN13

OUT13

OUT69

TXENB

I

I

I

I/O0 A1+/

PU

O1

O2

O3

I

I

I/O0 A1+/

PU

O1

O2

O3

Ctrl.

Type Function

I

I

I

I/O0 A2/

PU

O1

O2

O3


GPTA0 Input 12

CTRAPB

T13HRE

GPTA0 Output 12

GPTA0 Output 68

E-Ray Channel A transmit Data Output enable

1)

I

I/O0 A2/

PU

O1

O2

O3


GPTA0 Input 13

GPTA0 Output 13

GPTA0 Output 69

E-Ray Channel B transmit Data Output enable

1)


GPTA0 Input 14


CC61INC

GPTA0 Output 14

GPTA0 Output 70

CC61


GPTA0 Input 15


GPTA0 Output 15

GPTA0 Output 71

COUT61

Data Sheet 3-5 V1.2, 2014-06

TC1724

Pinning



Pin Symbol

92

95

78

79

P1.0

REQ15

IN16

BRKIN

OUT16

OUT72

GPT120

BRKOUT

P1.1

IN17

Ctrl.

Type Function

CCU60

CCU61

OUT17

OUT73

Reserved

P1.3

IN19

OUT19

OUT75

CCU61

P1.4

IN20

I

I

O1

O2

O3

EMGSTOP I

OUT20 O1

OUT76

CCU61

O2

O3

I

I/O0 A1/

PU

O1

O2

O3

I

I/O0 A1/

PU

I

I

I

I/O0 A2/

PU

O1

O2

O3

O

I

I/O0 A1/

PU

-



GPTA0 Input 16

Break Input

GPTA0 Output 16

GPTA0 Output 72

T3OUT

Break Output (controlled by OCDS module)


GPTA0 Input 17

T13HRE

CTRAPB

GPTA0 Output 17

GPTA0 Output 73


GPTA0 Input 19

GPTA0 Output 19

GPTA0 Output 75

COUT63


GPTA0 Input 20

Emergency Stop Input

GPTA0 Output 20

GPTA0 Output 76

COUT61

Data Sheet 3-6 V1.2, 2014-06

TC1724

Pinning



Pin Symbol

74

75

76

P1.8

IN24

IN48

MTSR1B

CCU61

GPT120

GPT121

OUT24

OUT48

MTSR1B

P1.9

IN25

IN49

MRST1B

CCU61

GPT120

GPT121

OUT25

OUT49

MRST1B

P1.10

IN26

IN50

OUT26

OUT50

SLSO17

Ctrl.

Type Function

I

O1

O2

O3

I

I

I

I

I

O1

O2

O3

I

I/O0 A1+/

PU

I

I

I

I

I

I/O0 A1+/

PU

I

O1

O2

O3

I

I/O0 A1+/

PU


GPTA0 Input 24

GPTA0 Input 48

SSC1 Slave Receive Input B (Slave Mode)

CCPOS2C

T4EUDB

T4EUDA

GPTA0 Output 24

GPTA0 Output 48

SSC1 Master Transmit Output B (Master Mode)


GPTA0 Input 25

GPTA0 Input 49

SSC1 Master Receive Input B (Master Mode)

CCPOS1C

T2EUDB

T2EUDA

GPTA0 Output 25

GPTA0 Output 49

SSC1 Slave Transmit Output B (Slave Mode)


GPTA0 Input 26

GPTA0 Input 50

GPTA0 Output 26

GPTA0 Output 50

SSC1 Slave Select Output 7

Data Sheet 3-7 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

77

93

P1.11

IN27

IN51

SCLK1B

CCU61

GPT120

GPT121

OUT27

OUT51

SCLK1B

P1.15

BRKIN

Reserved

Reserved

Reserved

BRKOUT

Port 2

61 P2.0

IN32

CCU60

CCU61

OUT32

TCLK0

CCU61



Ctrl.

Type Function

O1

O2

O3

O

I

I

I

I

I

I/O0 A1+/

PU

I

O1

O2

O3

I

I/O0 A2/

PU

-

-

-


GPTA0 Input 27

GPTA0 Input 51

SSC1 Clock Input B

CCPOS0C

T2INB

T2INA

GPTA0 Output 27

GPTA0 Output 51

SSC1 Clock Output B


Break Input

Break Output (controlled by OCDS module)

I

I

I

I/O0 A2/

PU

O1

O2

O3


GPTA0 Input 32

CC62INB

CC62INA

GPTA0 Output 32

MLI0 Transmitter Clock Output 0

CC62

Data Sheet 3-8 V1.2, 2014-06

TC1724

Pinning



Pin Symbol

62

63

64

P2.1

IN33

TREADY0A I

CCU61 I

CCU60

GPT120

GPT121

OUT33

SLSO03

SLSO13

P2.2

IN34

CCU60

CCU61

OUT34

TVALID0A

CCU61

P2.3

IN35

CCU60

CCU60

CCU61

GPT120

GPT121

OUT35

TDATA0

Reserved

I

I

I

I

I

I

I

I

Ctrl.

Type Function

I

I/O0 A2/

PU

O1

O2

O3

I

I/O0 A2/

PU

I

I

O1

O2

O3

I

I/O0 A2/

PU

O1

O2

O3

-


GPTA0 Input 33

MLI0 Transmitter Ready Input A

CCPOS0A

T12HRB

T2INA

T2INB

GPTA0 Output 33

SSC0 Slave Select Output Line 3

SSC1 Slave Select Output Line 3


GPTA0 Input 34

CC61INB

CC61INA

GPTA0 Output 34

MLI0 Transmitter Valid Output

CC61


GPTA0 Input 35

T12HRC

T13HRC

CCPOS2A

T4EUDA

T4EUDB

GPTA0 Output 35

MLI0 Transmitter Data Output

Data Sheet 3-9 V1.2, 2014-06

TC1724

Pinning



Pin Symbol Ctrl.

Type Function

65

66

67

68

132

P2.4

IN36

RCLK0A

OUT36

CCU61

Reserved

I

I

I/O0 A2/

O1

PU

P2.5

IN37

CCU60

CCU61

CCU61

P2.6

IN38

RVALID0A

Reserved

OUT38

I

I

I

O2

O3

I/O0

OUT37 O1

RREADY0A O2

A2/

PU

O3

I

I/O0 A2/

PU

I

I

O1

CCU61

Reserved

P2.7

RDATA0A I

O2

O3

I/O0 A2/

PU

IN39

OUT39

CCU61

Reserved

P2.8

SLSO04

SLSO14

EN00

I

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

-

-

-

-


GPTA0 Input 36

MLI Receiver Clock Input A

GPTA0 Output 36

COUT63


GPTA0 Input 37

CC60INB

CC60INA

GPTA0 Output 37

MLI0 Receiver Ready Output A

CC60


GPTA0 Input 38

MLI Receiver Valid Input A

GPTA0 Output 38

COUT62


MLI Receiver Data Input A

GPTA0 Input 39

GPTA0 Output 39

COUT60




MSC0 Enable Output 0

Data Sheet 3-10 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

128 P2.9

SLSO05

SLSO15

EN01

129 P2.10

MRST1A

MRST1A

Reserved

Reserved

130 P2.11

SCLK1A

SCLK1A

Reserved

FCLP0B

131 P2.12

MTSR1A

MTSR1A

Reserved

SOP0B

133 P2.13

SLSI11

SDI0

CCU60

CCU61

Reserved

SLSO16

GPT120

Port 3



Ctrl.

Type Function

I/O0 A2/

O1

PU

O2

O3

I

I/O0 A1+/

PU

O1

O2

O3

I

I/O0 A1+/

PU

O1

O2

O3

I

I/O0 A1+/

PU

O1

O2

O3

I

I

I

I

I/O0 A1+/

PU

O1

O2

O3

-

-

-

-

-




MSC0 Enable Output 1


SSC1 Master Receive Input A

SSC1 Slave Transmit Output


SSC1 Clock Input A

SSC1 Clock Output A

MSC0 Clock Output Positive B


SSC1 Slave Receive Input A

SSC1 Master Transmit Output A

MSC0 Serial Data Output Positive B


SSC1 Slave Select Input 1


CTRAPA

T12HRE


T6OUT

Data Sheet 3-11 V1.2, 2014-06

TC1724

Pinning




Type Function

112 P3.0

RXD0A

REQ6

RXD0A

Reserved

OUT84

111 P3.1

TXD0

Reserved

OUT85

I

I

I/O0 A1+/

O1

PU

O2

O3

I/O0 A1+/

O1

PU

O2

O3

I

I/O0 A1+/

PU

105 P3.2

SCLK0

106

SCLK0

Reserved

OUT86

P3.3

MRST0

MRST0

Reserved

OUT87

108 P3.4

MTSR0 I

O1

O2

O3

I

I/O0 A1+/

PU

O1

O2

O3

I/O0 A2/

PU

MTSR0

Reserved

O1

O2

102

OUT88

P3.5

O3

I/O0 A1+/

O1

PU

SLSO00

SLSO10 O2

SLSOANDO0 O3

-

-

-

-

-


ASC0 Receiver Input A (Async. & Sync. Mode)


ASC0 Output (Sync. Mode)

GPTA0 Output 84


ASC0 Output

GPTA0 Output 85


SSC0 Clock Input (Slave Mode)

SSC0 Clock Output (Master Mode)

GPTA0 Output 86


SSC0 Master Receive Input (Master Mode)

SSC0 Slave Transmit Output (Slave Mode)

GPTA0 Output 87


SSC0 Slave Receive Input (Slave Mode)

SSC0 Master Transmit Output (Master Mode)

GPTA0 Output 88




SSC0 AND SSC1 Slave Select Output 0

Data Sheet 3-12 V1.2, 2014-06

TC1724

Pinning




Type Function

103 P3.6

SLSO01

107 P3.7

SLSI0

I/O0 A1+/

O1

PU

SLSO11 O2

SLSOANDO1 O3

I

I/O0 A2/

PU

SLSO02

SLSO12

OUT89

104 P3.8

I

O1

O2

O3

I/O0 A2/

PU

114

REQ14

SLSO06

TXD1

OUT90

P3.9

RXD1A

RXD1A

Reserved

O1

O2

O3

I

I/O0 A1/

PU

O1

O2

O3 OUT91

113 P3.10

REQ0

Reserved

120

Reserved

OUT92

P3.11

REQ1

I

I/O0 A1/

O1

O2

O3

PU

I

I/O0 A1/

PU

Reserved

Reserved

OUT93

O1

O2

O3

-

-

-

-

-




SSC0 AND SSC1 Slave Select Output 1


SSC0 Slave Select Input 1



GPTA0 Output 89




ASC1 Transmit Output

GPTA0 Output 90


ASC1 Receiver Input A

ASC1 Receiver Output A (Synchronous Mode)

GPTA0 Output 91



GPTA0 Output 92



GPTA0 Output 93

Data Sheet 3-13 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

119 P3.12

RXDCAN0

RXD0B

RXD0B

Reserved

OUT94

118 P3.13

TXDCAN0

TXD0

OUT95

110 P3.14

RXDCAN1

RXD1B

SDI2

RXD1B

Reserved

OUT96

109 P3.15

TXDCAN1

TXD1

OUT97

Port 4



Ctrl.

Type Function

I

I/O0 A1/

PU

I

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

I

I/O0 A1/

PU

I

I

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

-

-


CAN Node 0 Receiver Input

ASC0 Receiver Input B

ASC0 Receiver Output B (Synchronous Mode)

GPTA0 Output 94


CAN Node 0 Transmitter Output


GPTA0 Output 95



ASC1 Receiver Input B


ASC1 Receiver Output B (Synchronous Mode)

GPTA0 Output 96




GPTA0 Output 97

Data Sheet 3-14 V1.2, 2014-06

TC1724

Pinning



Pin Symbol

72

73

P4.2

IN30

IN54

CCU60

CCU61

GPT120

GPT121

OUT30

OUT54

EXTCLK1

P4.3

IN31

IN55

CCU60

CCU61

OUT31

OUT55

EXTCLK0

Port 5

1 P5.0

REQ7

IN40

CCU60

CCU61

GPT120

GPT121

OUT40

CCU60

SLSO20

I

I

I

I

I

I

Ctrl.

I

I

I

O1

O2

O3

I

I

I

I

I

I/O0 A2/

PU

I

O1

O2

O3

I

I/O0 A2/

PU

I/O0 A1+/

PU

O1

O2

O3

Type Function


GPTA0 Input 30

GPTA0 Input 54

T13HRB

CCPOS1A

T2EUDA

T2EUDB

GPTA0 Output 30

GPTA0 Output 54

External Clock 1 Output


GPTA0 Input 31

GPTA0 Input 55

T12HRE

CTRAPA

GPTA0 Output 31

GPTA0 Output 55

External Clock 0 Output



GPTA0 Input 40

CC62INA

CC62INB

CAPINB

CAPINA

GPTA0 Output 40

CC62


Data Sheet 3-15 V1.2, 2014-06

TC1724

Pinning



Pin Symbol

2

3

4

7

8

P5.1

IN41

OUT41

Reserved

SLSO21

P5.2

IN42

OUT42

CCU60

SLSO22

P5.3

IN43

OUT43

Reserved

SLSO23

P5.4

IN44

SLSI2A

OUT44

Reserved

SLSO24

P5.5

IN45

MRST2A

OUT45

Reserved

MRST2

Ctrl.

Type Function

I

I/O0 A1+/

PU

O1

O2

O3

I

I/O0 A1+/

PU

O1

O2

O3

I

I/O0 A1+/

PU

O1

O2

O3

I

O1

O2

O3

I

I

I/O0 A1+/

PU

O1

O2

O3

I

I/O0 A1+/

PU

-

-

-

-


GPTA0 Input 41

GPTA0 Output 41



GPTA0 Input 42

GPTA0 Output 42

COUT62



GPTA0 Input 43

GPTA0 Output 43



GPTA0 Input 44

SSC2 Slave Select Input A

GPTA0 Output 44



GPTA0 Input 45

SSC2 Master Receive Input A (Master Mode)

GPTA0 Output 45


Data Sheet 3-16 V1.2, 2014-06

TC1724

Pinning

Table 3-1

CCU60



Pin Symbol

9

10

15

16

17

P5.6

IN46

MTSR2A

OUT46

Reserved

MTSR2

P5.7

IN47

SCLK2A

OUT47

Reserved

SCLK2

P5.8

CCU60

CCU61

OUT6

TXDA1

CCU60

P5.9

RXDCAN0

OUT7

TXDB1

Reserved

P5.10

OUT8

TXENA

Ctrl.

I

I/O0 A1+/

PU

I

O1

O2

O3

I

I/O0 A1+/

PU

I

O1

O2

O3

I

I/O0 A2/

PU

I

O1

O2

O3

I

I/O0 A2/

PU

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

Type Function

-

-

-


GPTA0 Input 46


GPTA0 Output 46



GPTA0 Input 47

SSC2 Clock Input A (Slave Mode)

GPTA0 Output 47



CC61INA

CC61INB

GPTA0 Output 6

E-Ray Channel A transmit Data Output

CC61



GPTA0 Output 7

E-Ray Channel B transmit Data Output


GPTA0 Output 8

E-Ray Channel A transmit Data Output enable

1)

COUT61

1)

1)

Data Sheet 3-17 V1.2, 2014-06

TC1724

Pinning



Pin

18

19

20

21

Symbol

P5.11

OUT9

TXENB

Ctrl.

Type Function

I/O0 A2/

O1

PU

O2


GPTA0 Output 9

E-Ray Channel B transmit Data Output enable

1)

CCU60

P5.12

CCU60

CCU61

GPT120

GPT121

OUT19

O3

I

I/O0 A1+/

PU

I

I

I

O1

SLSO07 O2

AD1EMUX0 O3

P5.13

CCU60 I

I/O0 A1+/

PU

CCU61

GPT120

GPT121

OUT20

I

I

I

O1

Reserved O2

AD1EMUX1 O3

P5.14

RXDA1 I

I/O0 A1+/

PU

CCU60

CCU61

CCU61

GPT120

GPT121

OUT36

Reserved O2

AD1EMUX2 O3

I

I

I

I

I

O1

-

-

COUT63


CCPOS0A

T12HRB

T3INA

T3INB

GPTA0 Output 19


ADC1 External Multiplexer Control Output 0


CCPOS1A

T13HRB

T3EUDA

T3EUDB

GPTA0 Output 20



E-Ray Channel A Receive Data Input 1

CCPOS2A

T12HRC

T13HRC

T4INA

T4INB

GPTA0 Output 36

1)


Data Sheet 3-18 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

11 P5.15

RXDB1

OUT37

Reserved

TXDCAN0

Port 8

117 P8.0

SCLK3

CCU60

GPT120

GPT121

Reserved

OUT48

SCLK3

116 P8.1

MRST3

CCU60

GPT120

GPT121

Reserved

OUT49

MRST3

115 P8.2

MTSR3

CCU60

GPT120

GPT121

Reserved

OUT50

MTSR3



Ctrl.

Type Function

I

I/O0 A1+/

PU

O1

O2

O3

-


E-Ray Channel B Receive Data Input 1

GPTA0 Output 37


1)

I

I

I

I

I

I

I

I

I

I

I

I

I/O0 A2/

PU

O1

O2

O3

I/O0 A2/

PU

O1

O2

O3

I/O0 A2/

PU

O1

O2

O3

-

-

-


SSC3 Clock Input (Slave Mode)

CCPOS0C

T3INB

T3INA

GPTA0 Output 48



SSC3 Master Receive Input (Master Mode)

CCPOS1C

T3EUDB

T3EUDA

GPTA0 Output 49




CCPOS2C

T4INB

T4INA

GPTA0 Output 50


Data Sheet 3-19 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

100 P8.3

SLSI3

CCU60

CCU61

OUT51

SLSO30

99 P8.4

OUT99

CCU61

SLSO31

69

70

P8.5

CCU60

OUT100

CCU61

SLSO32

P8.6

OUT101

Reserved

71

CCU61

P8.7

CCU60

OUT102

Reserved

CCU61

101 P8.13

OUT4

Reserved

CCU61

Port 9



Ctrl.

Type Function

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

I

I/O0 A2/

PU

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

I

I/O0 A2/

PU

I

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

I

I/O0 A2/

PU

-

-

-


SSC3 Slave Select Input B

CC61INC

CC61

GPTA0 Output 51



GPTA0 Output 99

COUT62



CC60INC

GPTA0 Output 100

CC60




COUT61


CC62INC


CC62


GPTA0 Output 4

COUT60

Data Sheet 3-20 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

5

6

P9.0

RXDCAN2

Reserved

OUT80

Reserved

P9.1

TXDCAN2

OUT81

Reserved

140 P9.2

Reserved

OUT82

CCU60

139 P9.3

Reserved

OUT83

CCU60

138 P9.4

87

CCU61

Reserved

OUT84

CCU60

P9.5

TDI

BRKIN

Reserved

Reserved

Reserved

BRKOUT



Ctrl.

Type Function

I

I/O0 A1/

PU

O1

O2

O3

I/O0 A2/

O1

PU

O2

O3

I/O0 A1/

O1

PU

O2

I

O1

O2

O3

O

O3

I/O0 A1/

O1

PU

O2

O3

I

I/O0 A1/

PU

O1

O2

O3

I

I/O0 A2/

PU

-

-

-

-

-

-

-

-

-



GPTA0 Output 80



GPTA0 Output 81


GPTA0 Output 82

COUT63


GPTA0 Output 83

COUT62


CC62INC

GPTA0 Output 84

CC62


JTAG Serial Data Input

OCDS Break Input

OCDS Break Output (controlled by OCDS module)

Data Sheet 3-21 V1.2, 2014-06

TC1724

Pinning

13

14

Port 11

38 P11.0

37

Dig0

AN16

P11.3

Dig3

AN19

36 P11.7

Dig7

AN23

P9.7

CCU61

Reserved

OUT87

CCU60

P9.8

Reserved

OUT88

CCU60

Table 3-1

TDO



Pin Symbol

89 P9.6

TDO

BRKIN

Reserved

Reserved

Reserved

BRKOUT

Ctrl.

I

I/O0 A2/

PU

I

O1

O2

O3

O

O

Type Function

I

I/O0 A1/

PU

O1

O2

O3

I/O0 A1/

O1

PU

O2

O3

-

-

-

-

-


JTAG Serial Data Output

OCDS Break Input

OCDS Break Output (controlled by OCDS module)

JTAG Serial Data Output (controlled by OCDS module)


CC60INC

GPTA0 Output 87

CC60


GPTA0 Output 88

COUT60

I

I

I

I

I

I

I

I

I

D / S Port 11 General Purpose I/O Line 0

Digital Input 0

Analog Input : ADC1.CH0

3)


2)

Digital Input 3



Digital Input 7


3)

3)

2)

2)

Data Sheet 3-22 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

35 P11.9

Dig9

AN25

Port 12

29

28

27

26

P12.0

Dig16

AN36

P12.1

Dig17

AN37

P12.2

Dig18

AN38

P12.3

Dig19

AN39

49

48

47

46

52

51

34

50

Analog Input Port

57 AN0

56

55

54

53

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12



I

I

I

Ctrl.

Type Function


2)

Digital Input 9


3)

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I


Digital Input 16


3)

2)


2)



3)


2)



3)


2)

D

D

D

D

D

D

D

D

D

D

D

D

D



3)

Analog Input 0: ADC0.CH0

3)


3)



3)

3)


3)


3)


3)


3)


3)


3)




3)

3)

3)

Data Sheet 3-23 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

AN13

AN14

AN15

AN16

AN19

AN23

AN25

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39 26

44

43

42

41

30

29

28

27

35

33

32

31

45

40

39

38

37

36

V

V

DDM

SSM

V

AREF0

V

AGND0

V

DD

12,

23

5)

,

58,

84,

125



-

I

-

-

-

-

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Ctrl.

Type Function

D

D


3)

D


3)


3)

D / S Analog Input 16: ADC1.CH0, Dig0

3)


3)


3)

D

D


3)

D

Analog Input 32: FADC_FADIN0P

4)

Analog Input 33: FADC_FADIN0N

4)

Analog Input 34: FADC_FADIN1P

4)

D

Analog Input 35: FADC_FADIN1N

4)


3)


3)


3)

-

-

-

-

-


3)

ADC Analog Part Power Supply (3.3V - 5V)

ADC Analog Part Ground

ADC0 and ADC1 Reference Voltage

ADC Reference Ground

Digital Core Power Supply (1.3V)

-

Port Power Supply (3.3V)

22,

59,

85,

126

V

DDP

Data Sheet 3-24 V1.2, 2014-06

TC1724

Pinning

Table 3-1

Pin Symbol

24,

60,

86

127

V

5



-

Ctrl.

Type Function

-

EVR Power Supply (5V)

25

V

V

PDG

SS

-

EVR Pass Device Gate

If this pin is connected to ground, the internal pass devices are used and the external pass device bypassed.

Digital Ground

80,

83

-

81

82

88

90

91

94

96

XTAL1

XTAL2

I

O

Main Oscillator Input

Main Oscillator Output

TMS

DAP1

TRST

I

I

I/O

A2/

PD

JTAG State Machine Control Input

Device Access Port Line 1

A1/

PD

JTAG Reset Input

TCK

DAP0

I

I

A1/

PD

JTAG Clock Input

Device Access Port Line 0

I/PU

Test Mode Select Input

TESTMODE I

ESR1 I/O A2/

PD

External System Request Reset Input 1

97

98

PORST

ESR0

I I/PU

Power On Reset

I/O A2

External System Request Reset Input 0

Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset.

1) Only applicable for SAK-TC1724F-192F133HL, SAK-TC1724F-192F133HR.

2) Analog input overlayed with digital input functionality. The related port logic is used to configure the input as either analog input (default after reset) or digital input. The related port logic supports only the port input features as the connected pads are input only pads.

3) IOZ1 valid for this pin is the parameter with overlayed = No in the ADC parameter table.

4) IOZ1 valid for this pin is the parameter with overlayed = Yes in the ADC parameter table.

5) For the emulation device (ED), this pin is bonded to VDD

SB devide device, this pin is bonded to a VDD pad.

(ED Stand By RAM supply). In the production

Data Sheet 3-25 V1.2, 2014-06

Legend for

Table 3-1

Column “Ctrl.”:

I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXX

B

)

O = Output

O0 = Output with IOCR bit field selection PCx = 1X00



B

B

(ALT1)

B

(ALT2)

O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)

Column “Type”:

A1 = Pad class A1 (LVTTL)

A1+ = Pad class A1+ (LVTTL)

A2 = Pad class A2 (LVTTL)

D = Pad class D (ADC)

I = Pad class I (LVTTL)

S = Pad class D (ADC) / Pad class S (Digital)

PU = with pull-up device connected during reset (PORST = 0)

PD = with pull-down device connected during reset (PORST = 0)

TR = tri-state during reset (PORST = 0)

TC1724

Pinning

Data Sheet 3-26 V1.2, 2014-06

TC1724

4 Identification Registers

The Identification Registers uniquely identify the device.


Table 2

Short Name

CBS_JDPID

CBS_JTAGID

SCU_MANID

SCU_CHIPID

SCU_RTID

SAK-TC1724F-192F133HL Identification Registers

Value

0000 6350

H

101D 0083

H

0000 1820

H

0300 A601

H

0000 0001

H

Address

F000 0408

H

F000 0464

H

F000 0644

H

F000 0640

H

F000 0648

H

Stepping

AB

AB

AB

AB

AB

Table 3

Short Name

CBS_JDPID

CBS_JTAGID

SCU_MANID

SCU_CHIPID

SCU_RTID

SAK-TC1724F-192F133HR Identification Registers

Value

0000 6350

H

101D 0083

H

0000 1820

H

8300 A601

H

0000 0001

H

Address

F000 0408

H

F000 0464

H

F000 0644

H

F000 0640

H

F000 0648

H

Stepping

AB

AB

AB

AB

AB

Table 4

Short Name

CBS_JDPID

CBS_JTAGID

SCU_MANID

SCU_CHIPID

SCU_RTID

SAK-TC1724F-192F133HR Identification Registers

Value

0000 6350

H

101D 0083

H

0000 1820

H

8300 A601

H

0000 0002

H

Address

F000 0408

H

F000 0464

H

F000 0644

H

F000 0640

H

F000 0648

H

Stepping

AC

AC

AC

AC

AC

Table 5

Short Name

CBS_JDPID

CBS_JTAGID

SCU_MANID

SAK-TC1724N-192F133HR Identification Registers

Value

0000 6350

H

101D 0083

H

0000 1820

H

Address

F000 0408

H

F000 0464

H

F000 0644

H

Stepping

AC

AC

AC

Data Sheet 4-1 V1.2, 2014-06

TC1724


Table 5

Short Name

SCU_CHIPID

SCU_RTID


(cont’d)

Value

8300 9B01

H

0000 0002

H

Address

F000 0640

H

F000 0648

H

Stepping

AC

AC

Table 6

Short Name

CBS_JDPID

CBS_JTAGID

SCU_MANID

SCU_CHIPID

SCU_RTID

SAK-TC1724N-192F80HL Identification Registers

Value

0000 6350

H

101D 0083

H

0000 1820

H

1300 9B01

H

0000 0001

H

Address

F000 0408

H

F000 0464

H

F000 0644

H

F000 0640

H

F000 0648

H

Stepping

AB

AB

AB

AB

AB

Table 7

Short Name

CBS_JDPID

CBS_JTAGID

SCU_MANID

SCU_CHIPID

SCU_RTID


Value

0000 6350

H

101D 0083

H

0000 1820

H

9300 9B01

H

0000 0001

H

Address

F000 0408

H

F000 0464

H

F000 0644

H

F000 0640

H

F000 0648

H

Stepping

AB

AB

AB

AB

AB

Table 8

Short Name

CBS_JDPID

CBS_JTAGID

SCU_MANID

SCU_CHIPID

SCU_RTID


Value

0000 6350

H

101D 0083

H

0000 1820

H

9300 9B01

H

0000 0002

H

Address

F000 0408

H

F000 0464

H

F000 0644

H

F000 0640

H

F000 0648

H

Stepping

AC

AC

AC

AC

AC

Data Sheet 4-2 V1.2, 2014-06

TC1724


5 Electrical Parameters

This specification provides all electrical parameters of the TC1724.

5.1

General Parameters

5.1.1

Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1724 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

•

CC

Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1724 and must be regarded for a system design.

•

SR

Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1724 designed in.

Data Sheet 5-1 V1.2, 2014-06

TC1724


5.1.2

Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the

Section 5.2.1

.

Table 9 Pad Driver and Pad Classes Overview

Class Power

A

Supply

3.3 V

Type Sub Class Speed

Grade

LVTTL

I/O,

LVTTL outputs

A1

(e.g. GPIO)

A1+

(e.g. serial

I/Os)

25

MHz

Load

50 pF

Leakage

150°C

6 MHz 100 pF 500 nA

1

μA

1)

ADC

A2

(e.g. serial

I/Os)

–

40

MHz

–

50 pF 3

μA

– –

DE

5 V

I

3.3 V LVTTL

(input only)

– – – –

1) Two values are given: for

T

J

= 150 °C and a 50% higher value for

T

J

= 160 °C.

Termination

No

Series termination recommended

Series termination recommended

Data Sheet 5-2 V1.2, 2014-06

TC1724


5.1.3

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Table 10

Parameter

Absolute Maximum Rating Parameters

Symbol Values

Min. Typ. Max.

Storage temperature

Voltage at 1.3 V power supply pins with respect to

V

SS

Voltage at 3.3 V power supply pins with respect to

V

SS

Voltage at 5 V power supply pins with respect to

V

SS

Voltage on any Class A input pin and dedicated input pins with respect to

V

SS

Voltage on any Class D analog input pin with respect to

V

AGND

Voltage on any shared Class

D analog input pin with respect to

V

SSAF

, if the FADC is switched through to the pin.

Input current on any pin during overload condition

Absolute maximum sum of all input circuit currents for one port group during overload condition

1)

Absolute maximum sum of all input circuit currents during overload condition

T

ST

V

DD

V

SR

V

V

IN

V

AIN

V

AREFx

V

DDP

DDM

AINF

I

IN

I

IN

Σ

I

IN

SR -65 –

SR – –

–

SR –

–

–

SR -0.6 –

SR

SR

-0.6 –

-0.6 –

-10 –

-75 –

– –

160

2.0

4.33

7.0

V

DDP or max. 4.33

7.0

7.0

+10

+75

|200|

+ 0.5

Unit Note /

Test Con dition

°C

–

V –

V

V

V

V

V mA mA mA

–

–

Whatever is lower

–

–

Data Sheet 5-3 V1.2, 2014-06

1) The port groups are defined in

Table 15

.

TC1724


Data Sheet 5-4 V1.2, 2014-06

TC1724


5.1.4

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification.

Table 11

defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

• full operation life-time (24000 h) is not exceeded

•

Operating Conditions

are met for

– pad supply levels (

– temperature

V

DDP

or

V

DDM

)

If a pin current is out of the


but within the overload parameters,

then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters.

Note: An overload condition on one or more pins does not require a reset.

Table 11

Parameter

Overload Parameters

Symbol

Input current on any digital pin during overload condition

Absolute sum of all input circuit currents for one port group during overload condition

1)

Input current on analog pins

I

I

IN

ING

I

INANA

Absolute sum of all analog input currents for analog inputs of a single ADC during overload condition

Absolute sum of all input circuit currents during overload condition

I

Σ

INSAS

I

INS

1) The port groups are defined in

Table 15

.

Values

Min. Typ. Max.

-5 – +5

-70 –

-3 –

-15 –

-100 –

+70

+3

+15

100

Unit Note /

Test Con dition

mA mA mA mA mA

Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.

Data Sheet 5-5 V1.2, 2014-06

TC1724


Table 12

Pad Type

A1 / A1+

A2

D / S

PN-Junction Characterisitics for positive Overload

I

IN

= 3 mA

U

IN

=

V

DDP

+ 0.6 V

U

IN

=

U

IN

=

V

DDP

+ 0.5 V

V

DDM

+ 0.6 V

I

IN

= 5 mA

U

IN

=

V

DDP

-

U

IN

=

V

DDP

+ 0.7 V

+ 0.6 V

Table 13

Pad Type

A1 / A1+

A2

D / S

PN-Junction Characterisitics for negative Overload

I

IN

= -3 mA

U

IN

=

V

SS

- 0.6 V

U

IN

=

U

IN

=

V

SS

- 0.5 V

V

SSM

- 0.6 V

I

IN

= -5 mA

U

IN

=

V

SS

-

U

IN

=

V

SS

- 0.7 V

- 0.6 V

Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery without having any negative reliability impact on the operational life-time.

Data Sheet 5-6 V1.2, 2014-06

TC1724


5.1.5


The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC1724. All parameters specified in the following tables refer to these operating conditions, unless otherwise noticed.

Digital supply voltages applied to the TC1724 from external must be static regulated voltages which allow a typical voltage swing of ± 5 %.

All parameters specified in the following tables refer to these operating conditions

(

Table 14

), unless otherwise noticed in the Note / Test Condition column.

Table 14

Parameter

Overload coupling factor for analog inputs, negative

Overload coupling factor for analog inputs, positive

CPU Frequency

Operating Conditions Parameters

f

Symbol

K

Values

Min.

Typ

.

OVAN

CC

− −

Max.

K

OVAP

CC

−

CPU

SR

−

−

−

−

−

Unit Note /

Test Condition

0.0001

0.00001

133

80

I

I

OV

≥ -2 mA;

OV

≤ 0 mA; analog pad= 5.0 V

I

I

OV

≥ 0 mA;

OV

≤ 3 mA; analog pad= 5.0 V

MHz SAK-TC1724F-

192F133HL;

SAK-TC1724F-

192F133HR;

SAK-TC1724N-

192F133HR

MHz SAK-TC1724N-

192F80HL;

SAK-TC1724N-

192F80HR

Data Sheet 5-7 V1.2, 2014-06

TC1724


Table 14

Parameter

FPI Frequency

Operating Conditions Parameters

(cont’d)

Symbol Values

Max.

Unit Note /

Test Condition

LMB Frequency

PCP Frequency

Inactive device pin current

Short circuit current of digital outputs

1)

f f f

Min.

Typ

.

FPI

SR

− −

I

I

−

LMB

SR

−

−

PCP

SR

−

−

ID

SR -1

SC

SR -5

−

−

−

−

−

−

−

110

80

133

80

133

80

1

5

MHz SAK-TC1724F-

192F133HL;

SAK-TC1724F-

192F133HR;

SAK-TC1724N-

192F133HR

MHz SAK-TC1724N-

192F80HL;

SAK-TC1724N-

192F80HR

MHz SAK-TC1724F-

192F133HL;

SAK-TC1724F-

192F133HR;

SAK-TC1724N-

192F133HR

MHz SAK-TC1724N-

192F80HL;

SAK-TC1724N-

192F80HR

MHz SAK-TC1724F-

192F133HL;

SAK-TC1724F-

192F133HR;

SAK-TC1724N-

192F133HR

MHz SAK-TC1724N-

192F80HL;

SAK-TC1724N-

192F80HR mA

All power supply voltages

V

DDx

= 0 mA

Data Sheet 5-8 V1.2, 2014-06

TC1724


Table 14 Operating Conditions Parameters

(cont’d)

Parameter Symbol Values Unit Note /

Test Condition

Absolute sum of short circuit currents of the device

Absolute sum of short circuit currents per pin group

Ambient

Temperature

Junction temperature

Core Supply Voltage

Σ

Σ

T

T

I

I

SC_D

Min.

Typ

.

CC

− −

SC_PG

CC

−

A

SR -40

J

SR -40

−

−

−

Max.

100

70

125

160 mA mA

°C

°C

V

DD

SR 1.17

1.3

1.43

2)

V Only required if externally supplied

5)

ADC analog supply voltage

EVR supply voltage

V

DDM

SR 2.97

5.0

5.5

3)

V

Digital supply voltage for IO pads

VDDP voltage to ensure defined pad states

6)

Digital ground voltage

V

5

SR 4.00

5.0

5.5

2.97

3.3

3.63

V

DDP

SR 2.97

3.3

3.63

4)

V

V

DDPPA

CC 0.65

−

SS

SR 0

−

−

−

V

V

V

V

V

5.0V single supply

3.3V single supply

Only required if externally supplied

5)

Analog ground voltage for

V

DDM

V

SSM

SR -0.1

0

1) Applicable for digital outputs.

0.1

V

2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less than

100

μs and the cumulated sum of the pulses does not exceed 1 h.


100



100


5) No external inductive load permissable if EVR is used.

6) This parameter is valid under the assumption the PORST signal is constantly at low level during the powerup/power-down of

V

DDP

.

Data Sheet 5-9 V1.2, 2014-06

TC1724


3

4

Table 15

Group

1

2

Pin Groups for Overload / Short-Circuit Current Sum Parameter

Pins

P5.[15:2], P9.[1:0], P9.[8:7]

P0.[7:0], P0.[15:12], P2.[13:8], P3.[1:0], P3.[4:3], P3.7, P3.[15:9], P5.[1:0],

P8.[2:0], P9.[4:2]

P1.[1:0], P1.15, P3.2, P3.[6:5], P3.8, P8.[4:3], P8.13, P9.[6:5]

P1.[4:3], P1.[11:8], P2.[7:0], P4.[3:2], P8.[7:5]

Data Sheet 5-10 V1.2, 2014-06

TC1724


5.2

5.2.1

DC Parameters

Input/Output Pins

Table 16

Parameter

Standard_Pads Parameters

Pin capacitance (digital inputs/outputs)

Pull-down current

Symbol Values

C

Min.

Typ.

Max.

IO

CC

− −

10

|

I

PDL

| CC

−

10

−

−

150

−

Pull-Up current |

I

PUH

| CC 10

−

−

Spike filter always blocked pulse duration

Spike filter pass-through pulse duration

t

SF1

CC

t

SF2

CC 120

−

−

−

−

−

100

10

−

Unit Note /

Test Condition

pF

μA

μA

μA

μA ns

T

A

= 25 °C;

f

= 1 MHz

V

i

≥ 0.6 x

V

DDP

V

V

V

i

≥ 0.36 x

DDP

V

V

i

≤ 0.6 x

V

DDP

V

V

V

i

≤ 0.36 x

DDP

V only PORST pin ns only PORST pin

Table 17 Standard_Pads Class_A1

Parameter

Input Hysteresis for pads of all A classes

1)

Input Leakage Current

Class A1

Symbol Values

HYSA

Min.

Typ.

Max.

CC 0.1 x

V

DDP

−

I

OZA1

CC -500

−

−

500

-750

−

750

Ratio Vil/Vih, A1 pads

V

V

ILA1

/

IHA1

CC

0.6

− −

Unit Note /

Test Condition

V nA nA

V

i

≤

V

DDP

-40°C

≤

T

V;

J

V

i

≥ 0 V;

≤ 150°C

V

i

≤

V

DDP

150°C

V;

< T

J

V

i

≥ 0 V;

≤ 160°C

Data Sheet 5-11 V1.2, 2014-06

TC1724


Table 17

Parameter

Standard_Pads Class_A1

(cont’d)

Symbol Values

On-Resistance of the class A1 pad, weak driver

R

DSONW

CC

Min.

Typ.

Max.

−

450 600

−

210 340

On-Resistance of the class A1 pad, medium driver

Fall time,pad type A1

Rise time, pad type A1

t

R

DSONM

CC

t

RA1

CC

−

−

FA1

CC

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

Unit Note /

Test Condition

155

110

150

50

140

550

18000 ns

65000 ns

150

50

140

550

Ohm

Ohm

Ohm

Ohm ns ns ns ns ns ns ns ns

18000 ns

65000 ns

I

OH

> -0.5 mA;

P_MOS

I

OL

< 0.5 mA;

N_MOS

I

OH

> -2 mA;

P_MOS

I

OL

< 2 mA;

N_MOS

C

L

= 20 pF; pin out driver= weak

C

L

= 50 pF; pin out driver= medium

C

L


C

L


C

L


C

L


C

L


C

L


C

L


C

L


C

L


C

L


Data Sheet 5-12 V1.2, 2014-06

TC1724



(cont’d)


Test Condition

Input high voltage, class A1 pads

Input low voltage, class

A1 pads

Output voltage high, class A1 pads

V

IHA1

SR

Min.

Typ.

Max.

0.6 x

V

DDP

− min(

V

DP

+

0.3,

3.6)

D

V

ILA1

SR -0.3

−

V

OHA1

CC

V

DDP

- 0.4

−

0.36 x

V

DDP

−

2.4

−

V

DDP

- 0.4

−

2.4

−

−

−

−

V

V

V

V

V

V

I

OH

≥ -1.4 mA; pin out driver= medium

I

OH

≥ -2 mA; pin out driver= medium

I

OH

≥ -400 μA; pin out driver= weak

I

OH


Output voltage low, class A1 pads

V

OLA1

CC

−

−

−

−

0.4

0.4

V

V

I

OL

≤ 2 mA; pin out driver= medium

I

OL

≤ 500 μA; pin out driver= weak

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be guaranteed that it suppresses switching due to external system noise.

Table 18

Parameter

Standard_Pads Class_A1+ l

Symbo Values

Min.

0.1 x

V

DDP

.

Typ

−

Max.

−

Input Hysteresis for

A1+ pads

1)

Input Leakage

Current Class A1+

HYSA1

+

CC

I

OZA1+

CC

-1000

−

Unit Note /

Test Condition

V

1000 nA

Data Sheet 5-13 V1.2, 2014-06

TC1724


Table 18

Parameter

weak driver

Standard_Pads Class_A1+

(cont’d)

l

Symbo

Min.

Values

On-Resistance of the class A1+ pad,

R

DSONW

CC

−

−

.

Typ Max.

450 600

210 340

On-Resistance of the class A1+ pad, medium driver

On-Resistance of the class A1+ pad, strong driver

Fall time, pad type

A1+

t

R

DSONM

CC

R

DSON1+

CC

FA1+

C

C

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

Unit Note /

Test Condition

155

110

110

80

150

28

16

50

140

550

Ohm

Ohm

Ohm

Ohm

Ohm

Ohm ns ns ns ns ns ns

18000 ns

65000 ns

I

OH

> -0.5 mA;

P_MOS

I

OL

< 0.5 mA;

N_MOS

I

OH

> -2 mA;

P_MOS

I

OL

< 2 mA;

N_MOS

I

OH

> -2 mA;

P_MOS

I

OL

< 2 mA;

N_MOS

C

L


C

L

= 50 pF; edge= slow; pin out driver= strong

C

L

= 50 pF; edge= soft ; pin out driver= strong

C

L


C

L


C

L


C

L


C

L


Data Sheet 5-14 V1.2, 2014-06

TC1724

Table 18

Parameter

Standard_Pads Class_A1+

(cont’d)

l

Symbo

Min.

Values

Max.

Rise time, pad type

A1+

t

RA1+

C

C

−

−

.

Typ

−

−

150

28

Input low voltage,

Class A1+ pads

Ratio Vil/Vih, A1+ pads

−

V

ILA1+

SR

V

V

ILA1+

/

IHA1+

CC

-0.3

0.6

−

−

−

−

−

−

Input high voltage,

Class A1+ pads

V

IHA1+

SR

0.6 x

V

DDP

−

−

−

−

−

−

−

−

16

50

140

550 ns

18000 ns ns ns

65000 ns min(

V

D

DP

+

0.3,

3.6)

0.36 x

V

DDP

−

V

V ns ns ns


Unit Note /

Test Condition

C

L


C

L

= 50 pF; edge= slow ; pin out driver= strong

C

L


C

L


C

L


C

L


C

L


C

L


Data Sheet 5-15 V1.2, 2014-06

TC1724


Table 18 Standard_Pads Class_A1+

(cont’d)

Parameter l

Symbo Values Unit Note /

Test Condition

Output voltage high, class A1+ pads

Output voltage low, class A1+ pads

V

V

OHA1+

CC

OLA1+

CC

Min.

V

V

−

−

−

DDP

- 0.4

−

2.4

2.4

V

2.4

.

Typ

DDP

- 0.4

−

−

−

DDP

- 0.4

−

−

−

−

−

Max.

−

−

−

−

−

−

0.4

0.4

0.4

V

V

V

V

V

V

V

V

V

I

OH


I

OH

≥ -1.4 mA; pin out driver= strong

I

OH


I

OH

≥ -2 mA; pin out driver= strong

I

OH


I

OH


I

OL


I

OL

≤ 2 mA; pin out driver= strong

I

OL



Table 19

Parameter


Symbol

Input Hysteresis for A2 pads

1)

HYSA2

CC

Min.

0.1 x

V

DDP

Values

Typ. Max.

− −

Unit Note /

Test Condition

V

Data Sheet 5-16 V1.2, 2014-06

TC1724


Table 19

Parameter

Input Leakage


(cont’d)

Symbol Values

current Class A2

Min.

I

OZA2

CC -6000

Typ. Max.

−

6000

Unit Note /

Test Condition

nA nA

V

V

V

V

i

< i

>

V

V

V

DDP

/ 2 - 1 V;

DDP

/ 2 + 1 V; i

≥ 0 V; i

≤

DDP

V

V

V

i

> i

<

V

V

DDP

/ 2 - 1 V;

DDP

/ 2 + 1 V

-3000

Ratio Vil/Vih, A2 pads

On-Resistance of the class A2 pad, weak driver

V

V

ILA2

/

IHA2

CC

R

DSONW

CC

0.6

−

−

On-Resistance of the class A2 pad, medium driver

R

DSONM

CC

−

−

On-Resistance of the class A2 pad, strong driver

R

DSON2

CC

−

−

−

−

3000

−

450 600

−

−

−

210 340

−

155

110

42

22

Ohm

Ohm

Ohm

Ohm

Ohm

Ohm

I

OH

> -0.5 mA;

P_MOS

I

OL

< 0.5 mA;

N_MOS

I

OH

> -2 mA;

P_MOS

I

OL

< 2 mA;

N_MOS

I

OH

> -2 mA;

P_MOS

I

OL

< 2 mA;

N_MOS

Data Sheet 5-17 V1.2, 2014-06

TC1724


Table 19

Parameter

Fall time, pad type A2


(cont’d)

Symbol Values

t

FA2

CC

Min.

−

Typ. Max.

−

150

− −

7

−

−

−

−

−

−

−

−

10

−

3.7

−

5

−

16

−

−

50

7.5

−

140

Unit Note /

Test Condition

ns ns ns ns ns ns ns ns ns

C

L


C

L

= 50 pF; edge= medium ; pin out driver= strong

C

L

= 50 pF; edge= mediumminus ; pin out driver= strong

C

L

= 50 pF; edge= sharp ; pin out driver= strong

C

L

= 50 pF; edge= sharpminus ; pin out driver= strong

C

L


C

L


C

L


C

L


Data Sheet 5-18 V1.2, 2014-06

TC1724

Table 19

Parameter


(cont’d)

Symbol Values

Min.

−

Typ. Max.

−

550

− −

18000

Rise time, pad type A2

Data Sheet

t

RA2

CC

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

5-19

65000

150

7.0

10

3.7

5

16

50

7.5

140


Unit Note /

Test Condition

ns ns ns ns ns ns ns ns ns ns ns ns

C

L


C

L


C

L


C

L


C

L

= 50 pF; edge= medium ; pin out driver= strong

C

L

= 50 pF; edge= mediumminus ; pin out driver= strong

C

L


C

L

= 50 pF; edge= sharpminus ; pin out driver= strong

C

L


C

L


C

L


C

L


V1.2, 2014-06

TC1724



(cont’d)

Parameter Symbol Values

Typ. Max.

−

550

Unit Note /

Test Condition

Min.

− ns

C

L


−

−

−

−

18000

65000 ns ns

C

L


C

L


Input high voltage, class A2 pads

Input low voltage,

Class A2 pads

V

V

IHA2

SR 0.6 x

V

ILA2

SR -0.3

DDP

−

− min(

V

+ 0.3,

DDP

3.6)

0.36 x

V

DDP

−

V

V

Output voltage high, class A2 pads

V

OHA2

CC

V

V

DDP

- 0.4

−

DDP

- 0.4

−

2.4

2.4

−

−

−

−

−

V

V

V

V

I

OH


I

OH

≥ -1.4 mA; pin out driver= strong

I

OH


I

OH

≥ -2 mA; pin out driver= strong

Output voltage low, class A2 pads

V

OLA2

V

CC

−

DDP

- 0.4

−

2.4

−

−

−

−

−

−

−

−

0.4

0.4

0.4

V

V

V

V

V

I

OH


I

OH


I

OL


I

OL

≤ 2 mA; pin out driver= strong

I

OL



Data Sheet 5-20 V1.2, 2014-06

TC1724


Table 20 Standard_Pads Class_I


Min.

Typ.

Max.

Unit Note /

Test Condit ion

V Input Hysteresis Class I

1)

Input Leakage Current

HYSI

CC 0.1 x

−

V

DDP

I

OZI

CC -1000

−

-1500

−

−

1000 nA -40°C

150°C

≤

T

J

≤

1500 nA 150°C

< T

J

≤

160°C

−

Ratio between low and high input threshold

V

ILI

/

V

IHI

CC 0.6

−

Input high voltage, class I pins

V

IHI

SR 0.6

V

DDP min(

V

D

DP

+

0.3,

3.6)

V

Input low voltage, Class I pads

V

ILI

SR -0.3

−

0.36 x

V

DDP

V


Class S pad parameters are only valid for

V

DDM

= 4.75 V to 5.25 V.

Table 21

Parameter

Standard_Pads Class_S

Symbol Values

HYSS

Min.

Typ.

Max.

CC 0.3

− −

Input Hysteresis for class S pads

1)

Input leakage current

Input voltage high

I

V

OZS

CC

−300 −

IHS

CC

− −

300

3.6

Unit Note /

Test Condition

V nA

V

Data Sheet 5-21 V1.2, 2014-06

TC1724


Table 21 Standard_Pads Class_S

(cont’d)

Parameter

Input voltage low

V

ILS

Delta

2)

Symbol Values Unit Note /

Test Condition

V

V

Min.

Typ.

Max.

ILS

CC 1.9

ILSD

CC -50

−

−

−

50

V mV Maximum input low state treshold

( variation over

1ms

V

nt)

DDP

= consta


2) V

ILSD

is implemented to ensure J2716 specification. It can’t be guaranteed that it suppresses switching due to external noise.

Data Sheet 5-22 V1.2, 2014-06

TC1724


5.2.2

Analog to Digital Converters (ADCx)

ADC parameter in

Table 22

are valid for

V

DD

5.25 V;

T

J

= 150°C.

= 1.235 V to 1.365 V;

V

DDM

= 4.75 V to

Table 22

Parameter

5V ADC Parameters

Symbol

Switched capacitance at the analog voltage inputs

1)

Total capacitance of an analog input

Switched capacitance at the positive reference voltage input

2)3)

Total capacitance of the voltage reference inputs

2)

Differential Non-Linearity

Error

4)5)6)7)

C

AINSW

CC

C

AINTOT

CC

C

AREFSW

CC

Min.

−

−

−

C

AREFTOT

CC

−

EA

CC

DNL

-3

Values

Typ. Max.

9 20

Unit

pF

20 30

15 30

20 40

−

3 pF pF pF

LSB

Gain Error

4)5)6)7)

Integral Non-

Linearity

4)5)6)7)

Offset Error

4)5)6)7)

EA

CC

GAIN

EA

CC

INL

EA

CC

OFF

-3.5

-3

-4

−

−

−

3.5

3

4

LSB

LSB

LSB

Note /

Test Condition

ADC resolution= 12bit

8) 9)


8) 9)

ADC resolution= 12-

bit

8) 9)


8) 9)

Data Sheet 5-23 V1.2, 2014-06

TC1724

Table 22

Parameter


(cont’d)

Symbol Values

Converter clock

f

ADC

SR

Min.

4

Typ. Max.

−

110

Internal ADC clock

Charge consumption per conversion

4

f

ADCI

CC 1

Q

CONV

CC

70

−

80

−

85

11)

20

100


Unit

MHz

MHz

MHz pC

Note /

Test Condition

SAK-TC1724F-

192F133HL;

SAK-TC1724F-

192F133HR;

SAK-TC1724N-

192F133HR

SAK-TC1724N-

192F80HL;

SAK-TC1724N-

192F80HR

10) charge needs to be provided via

V

AREF0

Data Sheet 5-24 V1.2, 2014-06

TC1724

Table 22

Parameter


(cont’d)

Symbol Values

Input leakage at analog inputs

12)

I

OZ1

CC

Min.

-100

Typ. Max.

−

500

-100

−

600 nA nA


Unit Note /

Test Condition

V

V

V

i i

≥ 0.97 x

DDM

≤

V

V;

DDM

V; overlayed= No

V

V

V

i i

≥ 0.97 x

DDM

≤

V

V;

DDM

V; overlayed= Yes

-500

-600

−

−

100

100 nA nA

V

V

V

i

≥ 0 V; i

≤ 0.03 x

V;

DDM overlayed= No

V

V

V

i

≤ 0.03 x i

DDM

V;

≥ 0 V; overlayed= Yes

-100

−

200 nA

Input leakage current at

Varef0


Vagnd0

ON resistance of the transmission gates in the analog voltage path

-100

I

OZ2

CC -2

I

OZ3

CC -2

R

AIN

CC

−

−

−

−

300

2

2 nA

μA

μA

900 1500 Ohm

V

V

V

V

i

> 0.03 x

V; i

DDM

< 0.97 x

DDM

V; overlayed= No

V

V

V

V

i

> 0.03 x

V; i

DDM

< 0.97 x

DDM

V; overlayed= Yes

V

V

AREF0

≥ 0V

AREF0

≤

V

;

DDM

V

V

V

AGND0

≥ 0V;

AGND0

≤

V

DDM

V

Data Sheet 5-25 V1.2, 2014-06

TC1724


Table 22

Parameter

ON resistance for the

ADC test (pull down for

AIN7)

Resistance of the reference voltage input path


(cont’d)

Symbol

R

R

AIN7T

CC

AREF

CC

Min.

180

−

Values Unit Note /

Test Condition

Typ. Max.

550 900 Ohm Test feature available only for odd AINx pins

500 1000 Ohm 500 Ohm increased if

AIN[1:0] used as reference input

−

50

13)

Broken wire detection delay against VAGND

Broken wire detection delay against VAREF

Sample time

Calibration time after bit

ADC_GLOBCFG.SUCAL is set

Total Unadjusted

Error

5)6)15)

t

BWG

CC

−

t

BWR

CC

−

t

S

CC 2

t

CAL

CC

−

TUE

CC -4

−

−

−

−

50

257

T

ADCI

4352 cycles

4

16)

14)

LSB ADC resolution= 12bit

− −

5

μs

Wakeup time from analog powerdown, fast mode

Wakeup time from analog powerdown, slow mode

Analog reference

ground

2)

t

AWAF

CC

t

AWAS

CC

V

AGND0

SR

−

V

SSM

-

0.05

−

−

10

μs

Analog input voltage

Analog reference voltage

2)

Analog reference voltage range

5)6)2)

V

V

V

V

AIN

SR

AREF0

SR

AREF0

-

AGND0

SR

V

AGND0

V

+

AGND0

V

DDM

/2

−

−

V

DDM

/2

−

V

AREF0

-

V

DDM

/2

V

AREF0

V

0.05

18)

DDM

+

17)

V

V

V

V

DDM

+

0.05

V

Data Sheet 5-26 V1.2, 2014-06

TC1724


1) The sampling capacity of the conversion C-network is pre-charged to

V

AREF

/2 before the sampling moment.

Because of the parasitic elements the voltage measured at AINx can deviate from

V

AREF

/2.

2) Applies to AINx, when used as auxiliary reference input.

3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage.

4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.

5) If the analog reference voltage range is below

V

DDM

but still in the defined range of

V

DDM

/ 2 and

V

DDM

is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),

TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.

6) If a reduced analog reference voltage between 1V and

V

DDM

/ 2 is used, then there are additonal decrease in the ADC speed and accuracy.

7) If the analog reference voltage is >

V

DDM

, then the ADC converter errors increase.

8) For 10-bit conversions the error value must be multiplied with a factor 0.25.


10) If the alternate reference is used or

f

ADCI

is more than 16 MHz, the accuracy of the ADC may decrease.

11) For a conversion time of 1 µs a rms value of 85µA result for

I

AREF0.

12) The leakage current definition is a continous function,as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine the characteristic points of the given countinuous linear approximation they do not define step function.

13) The broken wire detection delay against

V

AGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 250

μs. Results below 10% (199

H

).


V

AREF is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10

μs. This function is influenced by leakage current, in particular at high temperature.Results above 60% (999

H

).

15) Measured without noise.

16) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB

17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).

18) If the reference voltage

V

AREF

increase or the

V

DDM

decrease, so that then the accuracy of the ADC decrease by 4LSB12.

V

AREF

= (

V

DDM

+ 0.05V to

V

DDM

+ 0.07V),

Data Sheet 5-27 V1.2, 2014-06

TC1724


ADC parameter in

Table 23

are valid for

V

DD

3.465 V;

T

J

= 150°C.

= 1.235 V to 1.365 V;

V

DDM

= 3.135 V to

Table 23

Parameter

3.3V ADC Parameters l

Symbo

Switched capacitance at the analog voltage inputs

1)

Total capacitance of an analog input

Switched capacitance at the positive reference voltage input

2)3)

Total capacitance of the

voltage reference inputs

2)

Differential Non-Linearity

Error

4)5)6)7)

C

C

C

W

C

T

AINSW

CC

AINTOT

CC

AREFS

CC

AREFTO

CC

EA

CC

DNL

Min.

−

−

−

−

-4

Gain Error

4)5)6)7)

Integral Non-

Linearity

4)5)6)7)

Offset Error

4)5)6)7)

Converter clock

f

EA

CC

EA

CC

EA

CC

GAIN

INL

OFF

ADC

SR

-3.5

-4

-4

4

4

Values

Typ.

Max.

9 20

20

15

20

−

−

−

−

−

−

30

30

40

4

3.5

4

4

110

80

Unit

pF pF pF pF

Note /

Test Condition

LSB

LSB

LSB


8) 9)

ADC resolution= 12-

bit

8) 9)


8) 9)

LSB ADC resolution= 12-

bit

8) 9)

MHz SAK-TC1724F-

192F133HL;

SAK-TC1724F-

192F133HR;

SAK-TC1724N-

192F133HR

MHz SAK-TC1724N-

192F80HL;

SAK-TC1724N-

192F80HR

Data Sheet 5-28 V1.2, 2014-06

TC1724

Table 23

Parameter

3.3V ADC Parameters

(cont’d)

Values l

Symbo

Internal ADC clock

Min.

1

Typ.

Max.

−

20

Charge consumption per conversion

11)

f

ADCI

CC

Q

CONV

CC

− −

70 pC


Unit

MHz

Note /

Test Condition

10)

Input leakage at analog inputs

12)


Varef


Vagnd

I

OZ1

C

C

-100

-100

-500

-600

-100

-100

I

OZ2

CC -2

I

OZ3

CC -2

−

−

−

−

−

−

−

−

500

600

100

100

200

300

2

2 nA nA nA nA nA nA

μA

μA charge needs to be provided via

V

AREF0

V

V

V

i i

≥ 0.97 x

DDM

≤

V

V;

DDM

V; overlayed= No

V

V

V

i i

≥ 0.97 x

DDM

≤

V

V;

DDM

V; overlayed= Yes

V

V

V

i

≥ 0 V; i

≤ 0.03 x

DDM

V; overlayed= No

V

V

i

≤ 0.03 x

DDM

V;

V

i

≥ 0 V; overlayed= Yes

V

V

V

V

i

> 0.03 x

V; i

DDM

< 0.97 x

V;

DDM overlayed= No

V

V

V

V

i

> 0.03 x

V; i

DDM

< 0.97 x

DDM

V; overlayed= Yes

V

AREF0

≤

V

DDM

V

V

AGND0

≤

V

DDM

V

Data Sheet 5-29 V1.2, 2014-06

TC1724


Table 23 3.3V ADC Parameters

(cont’d)

Parameter l

Symbo Values Unit

Typ.

Max.

3500 9000 Ohm

Note /

Test Condition

ON resistance of the transmission gates in the analog voltage path

ON resistance for the

ADC test (pull down for

AIN7)

Resistance of the reference voltage input path

R

AIN

C

R

R

C

AIN7T

CC

AREF

CC

Min.

−

180

−

800 1800 Ohm Test feature available only for odd AINx pins

1700 3000 Ohm 500 Ohm increased if

AIN[1:0] used as reference input

−

50

13)

Broken wire detection delay against VAGND

Broken wire detection delay against VAREF

Sample time

Calibration time after bit

ADC_GLOBCFG.SUCAL is set

Total Unadjusted

Error

5)6)15)

t t t

BWG

CC

−

t

BWR

CC

−

S

CC 2

CAL

CC

−

−

−

−

50

257

14)

T

ADCI

4352 cycles

TUE

CC

-4.5

−

4.5

16)

LSB ADC resolution= 12bit

Analog reference

ground

2)

V

AGND0

SR

V

SSM

-

0.05

−

V

AREF0

-

V

DDM

/2

V

Analog input voltage


2)

V

V

AIN

SR

AREF0

SR

V

AGND0

−

V

+

AGND0

V

DDM

/2

−

V

DDM

/2

−

V

V

AREF0

DDM

0.05

18)

+

17)

V

V

Analog reference voltage range

5)6)2)

V

V

AREF0

-

AGND0

SR

V

DDM

+

0.05

V

1) The sampling capacity of the conversion C-network is pre-charged to

V

AREF

/2 before the sampling moment.

Because of the parasitic elements the voltage measured at AINx can deviate from

V

AREF

/2.

Data Sheet 5-30 V1.2, 2014-06

TC1724


2) Applies to AINx, when used as auxiliary reference input.

3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage.

4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.

5) If the analog reference voltage range is below

V

DDM

but still in the defined range of

V

DDM

/ 2 and

V

DDM

is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),

TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.

6) If a reduced analog reference voltage between 1V and the ADC speed and accuracy.

V

DDM

/ 2 is used, then there are additonal decrease in

7) If the analog reference voltage is >

V

DDM

, then the ADC converter errors increase.



10) If the alternate reference is used, or

f

ADCI

is more than 16 MHz, or STC is lower than 8, the accuracy of the ADC may decrease.

11)

Q

CONV

is calculated as

Q

CONV

=

C

AREF

*

V

AREF

. The Qconv can be calculated according to this formula.

12) The leakage current definition is a continous function,as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine the characteristic points of the given countinuous linear approximation they do not define step function.

13) The broken wire detection delay against conversion rate of not more than 250

V

AGND is measured in numbers of consecutive precharge cycles at a

μs. Results below 10% (199

H

).


V

AREF is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10

μs. This function is influenced by leakage current, in particular at high temperature.Results above 60% (999

H

).

15) Measured without noise.

16) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB

17) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).

18) If the reference voltage

V

AREF

increase or the

V

DDM

decrease, so that then the accuracy of the ADC decrease by 4LSB12.

V

AREF

= (

V

DDM

+ 0.05V to

V

DDM

+ 0.07V),

Table 24 Conversion Time

(Operating Conditions apply)

Parameter

Conversion time with post-calibration

Conversion time without post-calibration

t

Symbol Values

C

CC 2

×

T

ADC

+ (4 + STC + n)

×

T

ADCI

2

×

T

ADC

+ (2 + STC + n)

×

T

ADCI

Unit Note

μs n = 8, 10, 12 for n - bit conversion

T

T

ADC

ADCI

= 1 /

= 1 /

f

FPI

f

ADCI

Data Sheet 5-31 V1.2, 2014-06

R

EXT

V

AIN

=

C

EXT

ANx

V

AGNDx

TC1724


Analog Input Circuitry

R

AIN, On

R

AIN7T

C

AINTOT

- C

AINSW

C

AINSW

V

AREFx

V

AREF

V

AGNDx

Figure 7 ADCx Input Circuits

Reference Voltage Input Circuitry

R

AREF, On

C

AREFTOT

- C

AREFSW

C

AREFSW

Analog_InpRefDiag

Data Sheet 5-32 V1.2, 2014-06

TC1724


Ioz1

500nA

200nA

100nA

-100nA

3%

-500nA

Ioz1

600nA

Single ADC Input

Overlayed ADC/FADC Input

300nA

100nA

-100nA

3%

Figure 8

-600nA

ADCx Analog Inputs Leakage

V

IN

[V

DDM

%]

97% 100%

97%

V

IN

[V

DDM

100%

%]

Data Sheet 5-33 V1.2, 2014-06

TC1724


5.2.3

Fast Analog to Digital Converter (FADC)

FADC parameter are valid for

V

DDM

= 4.75 V to 5.25 V;

T

J

= 150°C.

Table 25

Parameter

DNL error

FADC Parameters with

V

DDM

= 5V

Symbol Values

EF

Min.

Typ.

Max.

DNL

CC -1

−

1

-1

-2

-2.5

-2

-2.5

−

−

−

−

−

1

2

Unit Note /

Test Condition

LSB

LSB

LSB

2.5

LSB

2 LSB

2.5

LSB

V

IN

mode= differential

Gain = 1, 2

V

IN

mode= single ended

Gain = 1, 2

V

IN

mode= differential

Gain = 4, 8

T

J

= 150°C

1)

V

IN

mode= differential

Gain = 4, 8

T

J

= 160°C

1)

V

IN

mode= single ended

Gain = 4, 8

T

J

= 150°C

1)

V

IN

mode= single ended

Gain = 4, 8

T

J

= 160°C

1)

Data Sheet 5-34 V1.2, 2014-06

TC1724


Table 25

Parameter

INL error


V

DDM

= 5V

(cont’d)

GRADient error

Symbol

EF

CC

EF

GRAD

-5

-5.5

-5.5

-6

-6

INL

CC -4

-4

Values

Min.

Typ.

Max.

-5

−

5

−

−

−

−

−

−

−

5

5

5

6

6

4

4

Unit Note /

Test Condition

%

%

%

%

%

%

LSB

LSB

V

IN

mode= differential ;

Gain

< 4

V

IN

mode= single ended ;

Gain< 4

V

IN


Gain

= 4

V

IN


Gain

= 4

V

IN


Gain

= 8

V

IN


Gain

= 8

V

IN

mode= differential

V

IN

mode= single ended

Data Sheet 5-35 V1.2, 2014-06

TC1724


Table 25

Parameter

Offset error


V

DDM

= 5V

(cont’d)

Symbol Values

EF

Min.

Typ.

Max.

OFF

CC -90

−

90

-90

-20

−

−

90

20

Unit Note /

Test Condition

mV mV mV

V

IN


Calibration= No

V

IN


Calibration= No

V

IN


Calibration= Yes

2)3)

-20

−

20 mV

V

IN


Calibration= Yes

2)3)

−

80 mV Error of common mode voltage

V

FAREFI

/2

Channel amplifier cutoff frequency

Converter clock

Conversion time

Input resistance of the analog voltage path (Rn,

Rp)

t f

EF

CC

REFI

-80

f

COFF

CC 2

FADC

SR

C

CC

4

4

−

R

FAIN

CC 100

−

−

−

−

−

−

MHz

110 MHz SAK-TC1724F-

192F133HL;

SAK-TC1724F-

192F133HR;

SAK-TC1724N-

192F133HR

80

21

f

MHz SAK-TC1724N-

192F80HL;

SAK-TC1724N-

192F80HR

1 /

FADC

200 kOh m

For 10-bit conversion

Data Sheet 5-36 V1.2, 2014-06

TC1724


Table 25 FADC Parameters with

V

DDM

= 5V

(cont’d)


Test Condition

Settling time of a channel amplifier after changing

ENN or ENP

t

Min.

Typ.

Max.

SET

CC

− −

5

μs

Analog input voltage range

4)

Wakeup time from analog powerdown, fast mode

t

V

AINF

SR

V

FWAF

CC

−

SSM

−

−

V

5

DDP

V

μs

Wakeup time from analog powerdown, slow mode

t

FWAS

CC

− −

10

μs

Analog reference ground

V

FAGNDI

CC

− 0 −

V Internally generated


V

FAREFI

CC

− 3.3

− 5)6)

V Internally generated

1) No missing codes.

2) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed minimium once per week.

3) The offser error voltage drifts over the whole temperature range maximum +-3LSB.

4) The accuracy values is valid between 5% and 90%of

V

AINF

5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100


6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage overshoots).

The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized.

Data Sheet 5-37 V1.2, 2014-06

FAINxN

V

SSM

FAINxP

FADC Analog Input Stage

R

N

-

+

V

FAREF

/2

R

P

+

-

TC1724


V

FAREF

V

FAREF

(from IVR)

FADC Reference Voltage

Input Circuitry

I

FAREF

V

FAGND

FADC _InpRefDiag

Figure 9 FADC Input Circuits

Data Sheet 5-38 V1.2, 2014-06

TC1724


5.2.4

Oscillator Pins

Table 26 OSC_XTAL Parameters


Test Condition

Input current at XTAL1

Input frequency

f

I

Min.

Typ. Max.

IX1

CC -25

OSC

SR 4

8

−

−

−

25

40

25

μA

V

V

IN

> 0 V;

IN

<

V

DDP

MHz Direct Input

Mode selected

MHz External Crystal

Mode selected

Oscillator start-up time

1)

Input high voltage at

XTAL1

2)

Input low voltage at

XTAL1

Input hysteresis for

XTAL1 pad

3)

t

OSCS

CC

−

V

IHX x

V

DDP

V

ILX

SR -0.5

HYSAX

CC

−

−

−

−

−

10

V

DDP

+

0.5

0.3 x

V

DDP

200 ms

V

V mV

1)

t

OSCS

*

V

is defined from the moment when

V

DDP

= 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3

DDP

. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystral suppliers.

2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 *

V

DDP

is necessary.


Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier.

Data Sheet 5-39 V1.2, 2014-06

TC1724


5.2.5

Power Supply Current

The total power supply current defined below consists of leakage and switching component.

Application relevant values are typically lower than those given in the following two tables and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations).

•

•

•

•

•

•

The operating conditions for the parameters in the following table are:

V

DD

=1.365 V,

V

DDP

=3.47 V,

V

DDM

=5.1 V,

f

LMB

=133 / 80 MHz,

T

J

=160 °C

The realisic power pattern defines the following conditions:

•

•

•

•

•

•

f f

T

V

V

V

J

=150 °C

LMB

FPI

DD

DDP

DDM

=

f

PCP

=

f

= 1.326 V

= 3.366 V

= 5.1 V

CPU

= 133 / 80 MHz

= 66.5 / 80 MHz

The max power pattern defines the following conditions:

f f

T

V

V

V

J

=160 °C

LMB

FPI

DD

DDP

DDM

=

f

PCP

=

= 1.37 V

f

= 3.47 V

= 5.25 V

CPU

= 133 / 80 MHz

= 66.5 / 80MHz

Data Sheet 5-40 V1.2, 2014-06

TC1724


Table 27

Parameter

I

DD

current at

PORST Low

PORST pad output current

Sum of all 1.3 V supply currents

I

DDP

current at

PORST Low

Power Supply Parameters

Symbol Values

Core active mode supply current

1)

Unit Note / Test Condition

I

DD

CC

.

Min

−

−

Typ. Max.

−

−

310 mA power pattern= max ;




212 mA power pattern= realistic ;




248 mA power pattern= max ;

SAK-TC1724N-192F80HL





110 mA

I

DD_PORST

CC

I

DDPORST

CC

I

DDSUM

CC

−

−

−

13

−

−

− mA

I

T

DDP_PORS

CC

−

−

−

−

212 mA power pattern= realistic;








6 mA

Data Sheet 5-41 V1.2, 2014-06

TC1724


Table 27

Parameter

I

DDP

current no pad activity

2)

ADC 5V power supply current

EVR Supply current


(cont’d)

Symbol Values Unit Note / Test Condition

.

Min

I

DDP

CC

−

−

−

−

Typ. Max.

−

−

−

−

I

DDP_

PORST

+ 83 mA including flash read current

I

DDP_

PORST

+ 62 mA including flash programming current

3)

I

DDP_

PORST

+

91

4) mA including flash erase verify current

3)

32 mA

I

DDM

CC

I

V5

CC

− −

−

−

−

−

−

−

375 mA power pattern= max; mode = 5V only with ext. pass device;



370 mA power pattern= max; mode = 5V only with ext. pass device


280 mA power pattern= real; mode = 5V only with ext. pass device;



275 mA power pattern= real; mode = 5V only with ext. pass device;



Data Sheet 5-42 V1.2, 2014-06

TC1724


Table 27

Parameter

EVR Supply current dissipation


(cont’d)


Maximum power

I

V5

PD

CC

CC

.

Min

−

−

−

−

Typ. Max.

−

−

−

−

310 mA power pattern= max; mode = 5V only without ext. pass device;



235 mA power pattern= real; mode = 5V only without ext. pass device;



902 mW power pattern= max; mode = all external;




744 mW power pattern= realistic mode = all external;




Data Sheet 5-43 V1.2, 2014-06

TC1724


Table 27

Parameter


(cont’d)


Maximum power dissipation

PD

CC

.

Min

−

−

−

−

Typ. Max.

−

−

−

−

1970 mW power pattern= max; mode = 5V only with ext. pass device;



1950 mW power pattern= max; mode = 5V only with ext. pass device;


1428 mW power pattern= realistic mode = 5V only with ext. pass device;



1403 mW power pattern= realistic mode = 5V only with ext. pass device;



PD

CC

−

−

−

−

810 mW power pattern= max; mode = all external;



669 mW power pattern= realistic; mode = all external;



Data Sheet 5-44 V1.2, 2014-06

TC1724


Table 27

Parameter


(cont’d)


.

Min Typ. Max.


PD

CC

− −

1628 mW power pattern= max; mode = 5V only without ext. pass device;



− −

1200 mW power pattern= realistic mode = 5V only without ext. pass device;



1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer application will most probably be lower than this value, but must be evaluated separately.

2) For operations including the D-Flash the required current is always lower than the current for non-DFlash operations.

3) Relevant for the power supply dimensioning, not for thermal considerations.

4) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes of up to 15 mA for maximum 5 ms per flash module.

5.2.5.1

Calculating the 1.3 V Current Consumption

The current consumption of the 1.3 V rail compose out of two parts:

• Static current consumption

• Dynamic current consumption

The static current consumption is related to the device temperature T

J

and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. These two parts needs to be added in order to get the rail current consumption.

(1)

I

0

=

C

×

×

T

J

C

(2)

I

0

=

C

×

×

T

J

Data Sheet 5-45 V1.2, 2014-06

TC1724


Function 1 defines the typical static current consumption and Function 2 defines the maximum static current consumption. Both functions are valid for V

DD

= 1.326 V.

For the dynamic current consumption using the application pattern and

f

LMB

=

f

PCP

= 2 *

f

FPI

the function 4 applies:

(3)

IDym =

MHz

× ]

For the dynamic current consumption using the application pattern and the function 5 applies:

f

LMB

=

f

PCP

=

f

FPI

(4)

IDym =

MHz

× ] and this finally results in

(5)

IDD = I0 IDYM

Data Sheet 5-46 V1.2, 2014-06

TC1724


5.3

AC Parameters

All AC parameters are defined with maximum driver strength unless otherwise stated.

5.3.1

Testing Waveforms

V

DD P

V

SS

90%

10%

t

R

90%

t

F

10% rise_fall

Figure 10 Rise/Fall Time Parameters

V

D DP

V

SS

V

D DE

/ 2 Test Points

V

DDE

/ 2 mct04881_a.vsd

Figure 11 Testing Waveform, Output Delay

V

Load

+ 0.1 V

V

Load

- 0.1 V

Timing

Reference

Points

V

OH

- 0.1 V

V

OL

- 0.1 V

MCT04880_new

Figure 12 Testing Waveform, Output High Impedance

Data Sheet 5-47 V1.2, 2014-06

TC1724


5.3.2

Power Sequencing 5V Supply Only

V

5.5V

5V

3.3V

1.3V

4.0V

3.63V

2.97

1.43V

1.17V

t

PORST (output)

PORST (input)

A B

C D E t

Power-Up_EVR_1.vsd

Figure 13 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence

The events for the above points in the power-up/down sequence

• A :external supplied voltage reaches operating level

• B: external supplied and internal generated voltages reaches operating levels

• C: internal generated voltage drops below operating level

• D: internal generated voltage resumes operating level

• E: external supplied voltage leaves operating level

P0.4 and P0.5 should be kept at the selected setting of '0' or '1' until external supplied voltage has reached its operating level.

The following list of rules applies to the power-up/down sequence:

• All ground pins V

SS

must be externally connected to one single star point in the system. Regarding the DC current component, all ground pins are internally directly connected.

• The latch-up risk is minimized if the I/O currents are limited to:

– 20 mA for one pin group

– AND 100 mA for the completed device I/Os

Data Sheet 5-48 V1.2, 2014-06

TC1724


– AND additionally before power-up / after power-down:

1 mA for one pin in inactive mode (0 V on all power supplies)

• The PORST signal may be deactivated after all VDD5, and VAREF0 power-supplies and the oscillator have reached stable operation, within the normal operating conditions.

• At normal power down the PORST signal should be activated within the normal operating range, and then the power supplies may be switched off. Care must be taken that all Flash write or delete sequences have been completed.

• In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rule number 2.

• Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible.

• Additionally, regarding the ADC reference voltage VAREF0:

– VAREF0 must power-up at the same time or later then VDDM, and

– VAREF0 must power-down either earlier or at latest to satisfy the condition

VAREF0 < VDDM + 0.5 V. This is required in order to prevent discharge of

VAREF0 filter capacitance through the ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA.

Data Sheet 5-49 V1.2, 2014-06

TC1724


5.3.3

Power Sequencing 3.3V Supply Only

V

3.3V

3.63V

2.97V

1.3V

1.43V

1.17V

t

PORST (output)

PORST (input)

A B

C D E

t

Power-Up_EVR_2.vsd

Figure 14 3.3 V / 1.3 V Power-Up/Down Sequence

The events for the above points in the power-up/down sequence

• A :external supplied voltage reaches operating level

• B: external supplied and internal generated voltages reaches operating levels

• C: internal generated voltage drops below operating level

• D: internal generated voltage resumes operating level

• E: external supplied voltage leaves operating level

P0.4 and P0.5 should be kept at the selected setting of '0' or '1' until external supplied voltage has reached its operating level.



SS


• The latch-up risk is minimized if the I/O currents are limited to:



Data Sheet 5-50 V1.2, 2014-06

TC1724




• The PORST signal may be deactivated after all VDD3.3, and VAREF0 powersupplies and the oscillator have reached stable operation, within the normal operating conditions.


• In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rule number 2.







Data Sheet 5-51 V1.2, 2014-06

TC1724

5.3.4

V

5.5V

5V

4.5V

3.63V

3.3V

1.3V

2.97V

1.43V

1.17V


Power Sequencing all Voltages supplied from External

V

AREF

0.5V

0.5V

0.5V

V

DDP

PORST power down power fail

Power-Up 10.v

Figure 15 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence

P0.4 and P0.5 should be kept at the selected setting until external supplied voltage has reached its operating level.



SS


• At any moment in time to avoid increased latch-up risk, each power supply must be higher then any lower_power_supply - 0.5 V, or:

VDD5 > VDDP - 0.5 V; VDD5 > VDD - 0.5 V;VDDP > VDD - 0.5 V, see

Figure 15

.

– The latch-up risk is minimized if the I/O currents are limited to:





Data Sheet 5-52 V1.2, 2014-06

TC1724


• During power-up and power-down, the voltage difference between the power supply pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names, that are internally connected via diodes, must be lower than 100 mV. On the other hand, all power supply pins with the same name (for example all VDDP), are internally directly connected. It is recommended that the power pins of the same voltage are driven by a single power supply.

• The PORST signal may be deactivated after all VDD5, VDDP, VDD, and VAREF0 power-supplies and the oscillator have reached stable operation, within the normal operating conditions.


• At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V power supply voltage falls 10% below the nominal level. If, under these conditions, the PORST is activated during a Flash write, only the memory row that was the target of the write at the moment of the power loss will contain unreliable content. In order to ensure clean power-down behavior, the PORST signal should be activated as close as possible to the normal operating voltage range.

• In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4.







Data Sheet 5-53 V1.2, 2014-06

TC1724


5.3.5

Power, Pad and Reset Timing

Table 28

Parameter

Boot Time

1)2)

Reset Timings Parameters

Application Reset

l

Symbo

t

B

CC 150

Power on Reset

Boot Time

3)4)

EVR Startup time from Supply ramp-up till

PORST release

HWCFG pins hold time from

ESR0 rising edge

HWCFG pins setup time to

ESR0 rising edge

Ports inactive after ESR0 reset active

Ports inactive after PORST reset active

5)

Minimum PORST active time after power supplies are stable at operating levels

t t

BP

CC

EVR

CC

t

HDH

SR

t

HDS

CC

t

PI

CC

t

PIP

CC

t

POA

CC

Min.

150

−

−

16 /

f

0

−

−

4.5

FPI

Values t

Uni Note / Test Condition

Typ. Max.

−

−

810

μs




1140

μs



−

2.5

ms

860

1100

μs

−

−

−

−

−

−

−

8/

f

FPI

150

− ns ns ns ns ms

6)

Data Sheet 5-54 V1.2, 2014-06

TC1724


Table 28 Reset Timings Parameters

(cont’d)

Parameter l

Symbo Values t

Uni Note / Test Condition

TESTMODE / TR

ST hold time from

PORST rising edge

t

POH

SR

Min.

100

Typ. Max.

− − ns

PORST rise time

t

POR

SR

− −

50 ms

TESTMODE / TR

ST setup time to

PORST rising edge

t

POS

SR

0

− − ns

Application Reset inactive after

PORST deassertion

t

POR_APP

SR

− −

40

7) μs

1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts.

2) The given time includes the time of the internal reset extension for a configured value of

SCU_RSTCNTCON.RELSA = 0x05BE.

3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts.

4) The given time includes the internal reset extension time for the System and Application Reset which is visible through ESR0.

5) This parameter includes the delay of the analog spike filter in the PORST pad.

6) This parameter represents the additional time required to ensure that external crystal is stable and operational at PORST.

7) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the

Application Reset is extended.

Data Sheet 5-55 V1.2, 2014-06

TC1724


V5

‐10%

VDDP

VDD

PORST

TRST

ESR0

HWCFG

Pads

Figure 16

V

DDPPA t

BP

t

EVR

t

POA

t

POH

t

POH

t

hd

t

HDH

t

PIP

t

PI

t

PI

Pad‐state undefined

Tri‐state or pull device active

As programmed t

PIP

Power, Pad and Reset Timing

t

hd

t

PIP

t

HDH

t

PI

t

HDH

t

PI

t

PI

V

DD

‐12%

V

DDPPA

Data Sheet 5-56 V1.2, 2014-06

TC1724

5.3.6

EVR Parameter

Table 29

Parameter

Pass device detector

Symbol

Pull-up current at VDPG

I

PU_VDPG

SR

Values

Min.

Typ. Max.

0.7

−

2.0

Input low voltage

V

IL

SR 0

−

1.5


Unit Note /

Test Condition

mA

V

V

V

DD5

≥ 4.5V;

DD5

≤ 5.5V

Table 30

Parameter

Output

Capacitance on

V

DDP

EVR Parameters

Symbol

C

OUT33

CC

Values

Min. Typ.

Max.

−

6.8

−

−

2.2

−


µF

µF

I

LOAD

>

310 mA;

ESR < 50mΩ; with external pass device, additional decoupling capacitor on each supply pin,




I

LOAD

≤ 310 mA;

ESR < 50mΩ; with internal pass device, additional decoupling capacitor on each supply pin,



Data Sheet 5-57 V1.2, 2014-06

TC1724

Table 30

Parameter

Output

Capacitance on

V

DD

EVR Parameters

(cont’d)

Symbol Values

C

OUT13

CC

Min. Typ.

Max.

−

6.8

−

Input

Capacitance on

V

5

−

C

IN5

CC

−

−

4.7

6.8

4.7

Undervoltage

Reset threshold for external supply

Output accuracy of

EVR33 after trimming

Dynamic Load

Regulation of

EVR33

Dynamic Line

Regulation of

EVR33

V

RST5

CC

∆

CC

∆

33

V

V

OUT33

LOREG

CC

∆

33

V

LIREG

CC

−

−

-

225

−

−

-80

−

−

-25

−

−

−

−

2.97

4.5

+80

+225 mV dI / dt = 150mA /10 ns

+25



µF

µF

µF

µF

V

V

I

LOAD

<

250 mA;

ESR < 50mΩ; additional decoupling capacitor on each supply pin,




I

LOAD

<

250 mA;

ESR < 50mΩ; additional decoupling capacitor on each supply pin,


SAK-TC1724N-192F80HR depending on ext. regulator



SAK-TC1724N-192F133HR depending on ext. regulator



3.3V single supply

5.0 single supply mV 4.5V

≤

1 mA

≤

V

I

IN

≤ 5.5V;

OUT

≤310mA mV dV5 / dt = 1V / ms

1 … 310mA,

4.5V … 5.5V

Data Sheet 5-58 V1.2, 2014-06

TC1724


Table 30

Parameter

EVR Parameters

(cont’d)


Undervoltage

Reset threshold for EVR33

Current drawn from EVR33 for external devices with internal pass devices.

Output accuracy of

EVR13 after trimming

Dynamic Load

Regulation of

EVR13

Dynamic Line

Regulation of

EVR13

Undervoltage

Reset threshold for EVR13

Current drawn from EVR13 for external devices

Supply ramp-up

V

RST33

CC

EXI

33

SR

∆

CC

∆

13

V

V

∆

13

V

LIREG

CC

V

RST13

CC

EXI

13

SR

SR

SR

OUT13

LOREG

CC

Min. Typ.

Max.

− −

2.97

−

-

100

−

-30

−

−

-10

−

−

−

−

−

−

−

30

+30

V mA No inductive loads allowed.

Decoupling capacitor >

330 nF mV 2.97V

≤

1 mA

≤

I

V

+100 mV 5.0V/3.3V single supply, dI / dt = 150mA /10 ns

+10

1.17

10

50 mV 5.0V/3.3V single supply, dV5 / dt=1V / ms

1 … 250mA, 2.97V … 3.63V

V mA No inductive loads allowed.

Decoupling capacitor >

100 nF

V/ms

IN

≤ 3.63V;

OUT

≤250mA

Data Sheet 5-59 V1.2, 2014-06

TC1724


5.3.7

Phase Locked Loop (PLL)

Table 31

Parameter

PLL_SysClk Parameters

Accumulated Jitter

PLL base frequency

VCO input frequency

VCO frequency range

PLL lock-in time

t

L

CC

Symbol Values

D

P

Min.

Typ.

Max.

CC -7

f

PLLBASE

CC 50

f

REF

CC 8

f

VCO

CC 400

−

200

−

−

7

320

16

720

14

14

−

−

200

400

μs

μs

Unit Note /

Test Condition

ns

MHz

MHz

MHz

N > 32

N ≤ 32

Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock

Bus clock

f f

VCO

(and with it the LMB-

LMB

) is constantly adjusted to the selected frequency. The PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter that is limited. This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle.

This is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible.

Two formulas are defined for the (absolute) approximate maximum value of jitter

[ns] dependent on the K2 - factor, the LMB clock frequency number

m

of consecutive

f

LMB

clock periods.

f

D

m

in

LMB

in [MHz], and the

D

m ns for

=

(

K2

≤

100

)

⎛

⎝

K2

×

f

740

LMB

[

MHz

]

+ 5

⎞

⎠ and

( m

≤ (

f

LMB

[

MHz

] )

×

⎛

⎝

(

1 – 0 01

×

f

×

K2

LMB

[

) × (

MHz m – 1

)

+

, ×

K2

⎠

⎞

(6)

(7) else

D

m ns =

K2

×

f

740

LMB

[

MHz

]

+ 5

Data Sheet 5-60 V1.2, 2014-06

TC1724


With rising number

m

of clock cycles the maximum jitter increases linearly up to a value of

m

that is defined by the K2-factor of the PLL. Beyond this value of

m

the maximum accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock frequency

f

LMB

results in a higher absolute maximum jitter value.

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed

C

L

= 20 pF with the maximum driver and sharp edge.

Oscillator Watchdog (OSC_WDT)

The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The

OSC_WDT checks for too low frequencies and for too high frequencies.

The frequency that is monitored is

f

OSCREF which is derived for

f

OSC

.

(8) f

O S C R E F

= f

-----------------------------------

OSCVAL + 1

The divider value SCU_OSCCON.OSCVAL has to be selected in a way that

f

OSCREF is

2.5 MHz.

Note: f

OSCREF

has to be within the range of 2 MHz to 3 MHz and should be as close as possible to 2.5 MHz.

The monitored frequency is too low if it is below 1.25 MHz and too high if it is above

7.5 MHz. This leads to the following two conditions:

• Too low:

f

• Too high:

OSC

f

OSC

< 1.25 MHz

× (SCU_OSCCON.OSCVAL+1)

> 7.5 MHz

× (SCU_OSCCON.OSCVAL+1)

Note: The accuracy is 30% for these boundaries.

Data Sheet 5-61 V1.2, 2014-06

5.3.8

ERAY Phase Locked Loop (ERAY_PLL)

TC1724


Table 32

Parameter

PLL_ERAY Parameters

Symbol Values

Min.

Typ.

Max.

−

0.8

Accumulated jitter at

SYSCLK pin

Accumulated_Jitter

PLL Base Frequency of the ERAY PLL

VCO input frequency of the ERAY PLL

VCO frequency range of the ERAY PLL

PLL lock-in time

D

PP

CC -0.8

D

P

CC -0.5

f

PLLBASE_ERAY

CC 50

f

REF

CC 20

f

VCO_ERAY

CC 450

t

L

CC 5.6

−

250

−

−

−

0.5

360

40

500

200

Unit Note /

Test Con dition

ns ns

MHz

MHz

MHz

μs

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed C

L

= 20 pF with the maximum driver and sharp edge.

Data Sheet 5-62 V1.2, 2014-06

TC1724


5.3.9

JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Note: These parameters are not subject to production test but verified by design and/or characterization.

Table 33 JTAG Parameters


TCK clock period

TCK high time

TCK low time

TCK clock rise time

TCK clock fall time

t

1

SR

t

2

SR

t

3

SR

t

4

SR

t

5

SR

t

6

SR

Min.

Typ.

Max.

25

10

10

−

−

6.0

−

−

−

−

−

−

−

−

−

4

4

−

TDI/TMS setup to TCK rising edge

TDI/TMS hold after TCK rising edge

t

7

SR 6.0

−

TDO valid after TCK falling edge

1)

t

8

CC 3.0

−

−

−

−

−

TDO high impedance to valid from TCK falling edge

2)

TDO valid output to high impedance from TCK falling edge

t t

9

10

CC

CC

− −

TDO hold after TCK falling edge

t

18

CC 2

−

1) The falling edge on TCK is used to generate the TDO timing.

2) The setup time for TDO is given implicitly by the TCK cycle time.

−

−

13

14

13.5

− ns ns ns ns ns ns

Unit Note /

Test Condition

ns ns ns ns ns ns

C

C

C

C

L

= 20 pF

L

=50 pF

L

= 50 pF

L

= 50 pF

Data Sheet 5-63 V1.2, 2014-06

t

1

0.5

V

D D P

t

2

t

3

Figure 17 Test Clock Timing (TCK)

t

5

TCK

t

6

t

7

TC1724


0.9

V

D D P

0.1

V

D D P

t

4

MC_ JTAG_TCK

TMS

t

6

t

7

TDI

t

9

t

8

t

10

TDO

t

18

MC_JTAG

Figure 18 JTAG Timing

Data Sheet 5-64 V1.2, 2014-06

TC1724


5.3.10

DAP Interface Timing

The following parameters are applicable for communication through the DAP debug interface.

Note: These parameters are not subject to production test but verified by design and/or characterization.

Table 34 DAP Parameters

Parameter

DAP0 clock period

1)

DAP0 high time

DAP0 low time

1)

DAP0 clock rise time

DAP0 clock fall time

Symbol Values

t

TCK

SR 12.5

t

12

SR 4

t

13

SR 4

t

14

SR

−

t

15

SR

−

t

16

SR 6.0

Min.

Typ.

Max.

−

−

−

−

−

−

−

−

−

2

2

−

Unit Note /

Test Condition

ns ns ns ns ns

DAP1 setup to DAP0 rising edge ns

DAP1 hold after DAP0 rising edge

t

17

SR 6.0

− − ns

DAP1 valid per DAP0 clock period

2)

t

19

CC 8

10

−

−

−

− ns ns

1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state.

2) The Host has to find a suitable sampling point by analyzing the sync telegram response.

C

L

= 20 pF;

f

= 80 MHz

C

L

= 50 pF;

f

= 40 MHz

t

1 1

0.5

V

DD P

t

1 2

t

1 3

t

1 5

t

1 4

0.9

V

D DP

0.1

V

D DP

MC_DAP0

Figure 19 Test Clock Timing (DAP0)

Data Sheet 5-65 V1.2, 2014-06

DAP0

DAP1

Figure 20 DAP Timing Host to Device

DAP1

Figure 21 DAP Timing Device to Host

t

1 6

t

1 7

t

1 1

t

1 9

TC1724


MC_ DAP1_RX

MC_ DAP1_TX

Data Sheet 5-66 V1.2, 2014-06

TC1724

5.3.11

Peripheral Timings


Note: Peripheral timings are not subjected to production test. They are verified by design

/ characterization.

5.3.11.1

Micro Link Interface (MLI) Timing

MLI Transmitter Timing

t

13

t

14

t

10

t

12

TCLKx

t

15

t

11

t

15

TDATAx

TVALIDx

t

16

t

17

TREADYx

MLI Receiver Timing

t

23

RCLKx

t

20

t

21

t

25

t

26

t

22

RDATAx

RVALIDx

t

27

RREADYx

t

24

t

27

MLI_Tmg_2.vsd

Figure 22

Data Sheet

MLI Interface Timing

5-67 V1.2, 2014-06

TC1724


Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx.

The MLI parameters are valid for C

L

= 50 pF, strong driver medium edge.

Table 35 MLI Receiver

Parameter

RCLK clock period

RCLK high time

1)2)

RCLK low time

1)2)

RCLK rise time

3)

RCLK fall time

3)

RDATA/RVALID setup time before RCLK falling edge

RDATA/RVALID hold time after RCLK falling edge

RREADY output delay time

t t t t t

Symbol

Min.

t

20

SR 1 /

21

SR

−

t

22

SR

−

t

23

SR

−

24

SR

−

25

SR 4.2

26

SR 2.2

27

SR 0

f

FPI

Values

Typ.

−

−

−

0.5 x

t

20

0.5 x

t

20

−

−

−

Max.

−

−

−

4

4

−

−

16

Unit Note /

Test Condition

ns ns ns ns ns ns ns ns

1) The following formula is valid: t21 + t22 = t20.

2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver timing parameters.

3) The RCLK max. input rise/fall times are best case parameters for fFPImax. For reduction of EMI, slower input signal rise/fall times can be used for longer RCLK clock periods.

Table 36

Parameter

MLI Transmitter

TCLK clock period

TCLK high time

1)2)

TCLK low time

1)2)

Symbol Values

t

10

CC

Min.

Typ.

Max.

2 x 1 /

f

FPI

t

11

CC 0.45 x

t

10

t

12

CC 0.45 x

t

10

t

−

0.5 x

t

10

0.5 x

10

−

0.55 x

0.55 x

t

10

t

10 ns ns

Unit Note /

Test Condition

ns

Data Sheet 5-68 V1.2, 2014-06

TC1724


Table 36 MLI Transmitter

(cont’d)


Test Condition

TCLK rise time

TCLK fall time

TDATA/TVALID output delay time

TREADY setup time before TCLK rising edge

TREADY hold time after TCLK rising edge

t t

Min.

Typ.

Max.

t

13

CC

−

t

14

CC

−

t

15

CC -3

16

SR 18

17

SR -2

−

−

−

−

−

0.3 x

t

0.3 x

t

4.4

−

−

10

3)

10

3)

ns ns ns ns ns

1) The following formula is valid: t11 + t12 = t10.

2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be regarded additionally to t11 / t12.

3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended for TCLK.

5.3.11.2

Micro Second Channel (MSC) Interface Timing

The MSC parameters are valid for C

L

= 50 pF.

Table 37

Parameter

MSC Parameters

FCLP clock period

1)2)

Symbol Values

t

40

CC

Min.

Typ.

Max.

2 x

T

MSC

3)

− −

Unit Note /

Test Condition

ns

Data Sheet 5-69 V1.2, 2014-06

TC1724

Table 37

Parameter

MSC Parameters

(cont’d)

Symbol

SOP

4)

/ENx outputs delay

from FCLP

4)

rising edge

-2

0

Values

t

45

Min.

Typ.

Max.

CC -5

−

5

−

−

10

21


SDI bit time

SDI rise time

SDI fall time

t

46

CC 8 x

T

MSC

t

48

SR

−

t

49

SR

−

−

−

−

−

200

200

1) FCLP signal rise/fall times are only defined by the pad rise/fall times.

2) FCLP signal high and low can be minimum 1 / TMSC

3) TMSC = TSYS = 1 / fSYS.

4) SOP / FCLP either propagated by CMOS strong driver and non soft edge.

ns ns

Unit Note /

Test Condition

ns ns ns

ENx with strong driver and sharp (minus ) edge;

CMOS mode

ENx with strong driver and medium

(minus) edge

ENx with strong driver and soft edge ns

t

40

FCLP

t

45

SOP

EN

t

48

SDI

Figure 23

Data Sheet

t

46

MSC Interface Timing

5-70

t

45

t

46

0.9 V

DDP

0.1 V

DDP

t

49

0.9 V

DDP

0.1 V

DDP

MSC_Tmg_1.vsd

V1.2, 2014-06

TC1724


Note: The data at SOP should be sampled with the falling edge of FCLP in the target device.

Data Sheet 5-71 V1.2, 2014-06

TC1724

5.3.11.3

SSC Master/Slave Mode Timing


The SSC parameters are valid for C

L

= 50 pF, strong driver medium edge.

Table 38

Parameter

Parameters

Symbol Values

Min.

Typ.

Max.

SCLK clock period

1)2)3)

MTSR/SLSOx delay from

SCLK rising edge

MRST setup to SCLK

latching edge

3)

MRST hold from SCLK

latching edge

3)

SCLK input clock period

1)3)

SCLK input clock duty cycle

t t t t t

50

51

52

53

54

CC

CC

SR

SR

SR

2 x 1 /

f

FPI

0

16.5

0

4 x 1 /

f

FPI

t

55

_

t

54

SR 45

−

−

−

−

−

−

−

8

−

−

−

55

MTSR setup to SCLK

latching edge

3)4)

MTSR hold from SCLK latching edge

SLSI setup to first SCLK latching edge

SLSI hold from last SCLK latching edge

5)

t t t t

56

57

58

59

SR

SR

SR

SR

1 /

f

+ 1

1 /

f

+ 5

1 /

f

FPI

+ 5

7

FPI

FPI

−

−

−

−

−

−

−

−

MRST delay from SCLK shift edge

SLSI to valid data on

MRST

t t

60

61

CC

CC

0

−

−

−

16.5

16.5

1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.

2) SCLK signal high and low times can be minimum 1xT.

3) Tmin = TSYS = 1/fSYS.

4) Fractional divider switched off, internal baud rate generation used.

Unit Note /

Test Conditi on

ns ns ns ns ns

% ns ns ns ns ns ns

Data Sheet 5-72 V1.2, 2014-06

TC1724


5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair of shifting / latching edges.

t

50

SCLK

1)2)

t

51

t

51

MTSR

1)

MRST

1)

t

52

t

53

Data valid

t

51

SLSOn

2)

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0

and the first SCLK high pulse is in the first one of a transmission.

SSC_TmgMM

Figure 24 Master Mode Timing

Data Sheet 5-73 V1.2, 2014-06

TC1724


SCLK

1)

MTSR

1)

t

60

t

54

First shift

SCLK edge

t

55

t

56

t

57

Data valid

First latching

SCLK edge

t

55

t

60

t

56

t

57

Data valid

Last latching

SCLK edge

MRST

1)

SLSI

t

61

t

58

t

59

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_TmgSM

Figure 25 Slave Mode Timing

Data Sheet 5-74 V1.2, 2014-06

TC1724


5.3.11.4

ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with

C

L

= 25 pF.

The ERAY interface is only available for the SAK-TC1724F-192F133HL and SAK-

TC1724F-192F133HR .

Table 39 ERAY Parameters


Test Condition

Min.

Typ.

Max.

t

60

CC 997.75

−

1002.25 ns Time span from last BSS to FES without the influence of quartz tolerancies (d10Bit_TX)

1)

TxD data valid from fsample flip flop txd_reg

TxDA, TxDB

(dTxAsym)

2)3)

Time span between last

BSS and FES without influence of quartz tolerancies

(d10Bit_RX)

1)4)5)

t t

61

CC

-

63

t

62

−

SR 966

−

−

1.5

ns

1046.1

ns

Asymmetrical delay of rising and falling edge

(TxDA, TxDB)

RxD capture by fsample

(RxDA/RxDB sampling flip-flop) (dRxAsym)

5)

TxD data delay from sampling flip-flop

t

64

CC

-

t

65

dTxdly

CC

−

−

−

−

−

−

3.0

10.0

15.0

ns ns ns

Asymmetrical delay of rising and falling edge

(RxDA, RxDB)

Px_PDRz.PDy

= 000

B

Px_PDRz.PDy

= 001

B

RxD capture delay by sampling flip-flop

dRxdly

CC

− −

10.0

ns

1) This includes the PLL_ERAY accumulated jitter.

2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.

Quarz tolerance and PLL_ERAY accumulated jitter are not included.

3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |

t

FA2

-

t

RA2

|

≤ 1 ns.

4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) *

V

DDP

FlexRay standard input thresholds. For input thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.

Data Sheet 5-75 V1.2, 2014-06

TC1724


5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * to satisfy the following inequality: -1.6ns

≤ |

t

FA2

-

t

RA2

|

≤ 1.3ns.

V

DDP

to 80% *

V

DDP

, according to the FlexRay

Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have

BSS

(Byte Start Sequence)

TXD

t

sample

TXD

BSS

(Byte Start Sequence)

RXD

t

61

Last CRC Byte

t

60

Last CRC Byte

t

63

t

sample

RXD

t

64

Figure 26 ERAY Timing

FES

(Frame End Sequence)

t

62

FES

(Frame End Sequence)

0.9 V

DD

0.1 V

DD

0.7 V

DD

0.3 V

DD

t

65

0.7 V

DD

0.3 V

DD

0.7 V

DD

0.3 V

DD

ERAY_TIMING

Data Sheet 5-76 V1.2, 2014-06

TC1724


5.4

Package and Reliability

5.4.1

Package Parameters

Table 40

Device

Thermal Characteristics of the Package

Package R

ΘJCT

1)

R

B

ΘJC

1)

R

ΘJCL

1)

Unit Note

TC1724 PG-LQFP-144-17 9.0

0.4

28.1

K/W

1) The top and bottom thermal resistances between the case and the ambient ( with the thermal resistances between the junction and the case given above ( the total thermal resistance between the junction and the ambient ( the case and the ambient ( under user responsibility.

R

TCAT

,

R

R

TJA

R

R

TCAT

,

TJCT

,

R

R

TCAB

) are to be combined

TJCB

), in order to calculate

). The thermal resistances between

TCAB

) depend on the external system (PCB, case) characteristics, and are

The junction temperature can be calculated using the following equation:

T

J

=

T

A

+

R

TJA

×

P

D

, where the

R

TJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance

R

TJA

can be obtained from the upper four partial thermal resistances.

Data Sheet 5-77 V1.2, 2014-06

5.4.2

Package Outline

TC1724


Figure 27

Table 41

Ex

Ey

Package Outlines PG-LQFP-144-17

Exposed pad Dimensions

7.5 mm

7.5 mm

You can find all of our packages, sorts of packing and others in our Infineon Internet

Page “Products”: http://www.infineon.com/products.

5.4.3

Flash Memory Parameters

The data retention time of the TC1724’s Flash memory depends on the number of times the Flash memory has been erased and programmed.

Data Sheet 5-78 V1.2, 2014-06

TC1724


Table 42 FLASH32 Parameters

Parameter

Data Flash Erase

Time per Sector

Program Flash Erase

Time per 256 KByte

Sector

Program time data flash per page

2)

t

ERD

Min.

Typ.

Max.

CC

− −

3

1)

t

ERP

CC

−

t

PRD

CC

−

−

−

5

Program time program flash per page

3)

Data Flash

Endurance

Erase suspend delay

Wait time after margin change

Program Flash

Retention Time,

Physical Sector

5)6)

Program Flash

Retention Time,

Logical Sector

5)6)

UCB Retention

Time

5)6)

Wake-Up time

2)

t t t t t t t

Symbol

PRP

CC

N

E

CC 60000

4)

FL_ErSusp

CC

−

FL_MarginDel

SR 10

RET

RETL

RTU

CC 20

WU

−

−

−

CC 20

CC 20

CC

−

Values

−

−

−

−

−

−

−

−

−

−

Unit Note /

Test Condition

s s

5.3

15.9

5.3

ms ms ms without reprogramming with two reprogramming cycles without reprogramming

10.6

− ms with one reprogramming cycle cycles Min. data retention

5 years

15

− ms

μs

−

− years Max. 1000 erase/ program cycles years Max. 100 erase/ program cycles

− years Max. 4 erase/ program cycles per UCB

270

μs

Data Sheet 5-79 V1.2, 2014-06

TC1724


Table 42 FLASH32 Parameters

(cont’d)


Test Condition

Min.

Typ.

Max.

DFlash wait state configuration

PFlash wait state configuration

WS

WS

DF

SR

PF

SR

50ns

x

f

LMB

26ns

x

f

LMB

−

−

−

−

1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can increase by up to 100%.

2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each reprogramming takes additional 5 ms.

3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5 ms.

4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.

5) Storage and inactive time included.

6) At average weighted junction temperature of

T

minimum 0.7 years.

T

j

= 100°C, or the retention time at average weighted temperature j

= 110°C is minimum 10 years, or the retention time at average weighted temperature of

T

j

= 150°C is

5.4.4

Quality Declarations

Table 43

Parameter

Quality Parameters


Operation

Lifetime

1)

ESD susceptibility according to

Human Body

Model (HBM)

t

V

OP

HBM

Min. Typ. Max.

– – 24000 hours –

2)

– – 2000 V

ESD susceptibility according to

Charged Device

Model (CDM)

V

CDM

– – 500 V

Moisture

Sensitivity Level

MSL – – 3 –

1) This lifetime refers only to the time when the device is powered on.

Conforming to

JESD22-A114-B

Conforming to

JESD22-C101-C

Conforming to Jedec

J-STD-020C for 240°C

Data Sheet 5-80 V1.2, 2014-06

TC1724

2) For worst-case temperature profile equivalent to:

1200 hours at

3600 hours at

7200 hours at

11000 hours at

1000 hours at

T

T

T

T

j j

= 125...160

j

= 110...125

= 100...110

T

j

= 25...110

j

= -40...25

o o o o o

C

C

C

C

C


5.5

Revision History

Changes from V0.3 to V0.4D1

• Operating Conditions

– Added footnote 3 and 4

– Updated

– Added

f

K

CPU

OVAN

and

,

f

LMB

,

f

K

OVAP

PCP

,

f

max values

FPI max for SAK-TC1724F-192F133HL, SAK-TC1724F-

192F133HR, SAK-TC1724N-192F80HR, SAK-TC1724N-128F80HR.

– Updated limits for

–

Added I

Updated

Σ

I

I

V

DD,

IN,

Σ

IN

–

SC_PG

• Standard Pad Class A1

V

DDM,

V

DDP

.

– Changed

R

DSON1

to R

DSONM

, added new condition “PMOS” for 140ohms, added a new condition for “NMOS” with a max value of 100ohms

– Added

R

DSONW

– Changed min value of


• Standard Pad Class A1+

V

V

IHA1

to 0.6 x

ILA1

/

V

IHA1

V

DDP

to 0.6

– Added HYSA1+

– Added

– Added

–

R

DSON1+

V

R

ILA1+

/

DSONW

V

,

IHA1+

R

DSONM

, added new condition “PMOS” for 85ohms, added a new condition for

“NMOS” with a max value of 70ohms


V

IHA1+

to 0.6 x

– Deleted -2000nA to 2000nA limits for

V

DDP

I

OZA1+

• Standard Pad Class A2

– Added HYSA2

– Added

–

R

DSON2

R

DSONW

,

R

DSONM

, added new condition “PMOS” for 25ohms, added a new condition for

“NMOS” with a max value of 20ohms

–

–

–

t

FA2

, added max 18000ns for CL=20000pF; pinout driver=medium, 65000ns for

CL=20000pF;pinout driver=weak

t t

RA2

, removed 140ns for CL=150pF;pinout driver=weak

RA2

, added 550ns for CL=150pF,pinout driver=weak, 18000ns for CL=20000pF, pinout driver=medium, 65000ns for CL=20000pF, pinoutdriver=weak

• Standard Pad Class F

– Added HYSF

Data Sheet 5-81 V1.2, 2014-06

TC1724


– Changed min value of VIHF to 0.6 x VDDP

– Added min value of

R R t

V

, t

ILF

/

– Added

DSONW

,

– Deleted note for

DSONM

FF

• Standard Pad Class I

RF

V

IHF

as 0.6


V


V

IHI

to 0.6 x

ILI

/

V

IHI

V

DDP

as 0.6

• LVDS Pads

– Removed input hysteresis F, HYSF

– Added note “Parallel termination 100 Ohm +-1%” for

t

FL

, t

• Standard Pad Class S

RL,

t

SET_LVDS

– Changed max value of


– Added input leakage current,

• ADC parameters

V

V

IHS

ILS

to 3.6

to 2.1

I

OZS

– Changed typ value of

– Changed typ value of

– Updated notes for

– Changed

f f f f

ADCI

EA

to max 20MHz

t

C

C

AINSW

to 9pF

AINTOT

to 20pF

DNL

,EA

GAIN

,TUE

t

,EA

INL

,EA

OFF

– Added

– Added

ADC

of 110MHz where ffpimax=110MHz

ADC


– Updated min of 4MHz

ADC

– Added sample time,

S

, 2 to 255 tADCI

– Added calibration time after reset,

CAL

max 4352 cycles

– Included footnote for TUE for 10-bit and 8-bit conversion

– Removed

– Removed

I

I

AIN7T

(covered by

AREF

, added

– Updated notes for

• FADC parameters

I

OZ2

Q

CONV

and

I

R

AIN7T

OZ3

– Updated typ value of 900Ohm for

)

R

AIN

– Updated note for

–

FADC

EF

Updated note for EF

– Added

– Added

f f

GRAD

OFF


FADC


– Added conversion time,

t

– Added analog input voltage range,V

• OSC XTAL parameters

C

AINF

– Added

f

OSC



V

V

IHX

ILX

to

V

DDP

to -0.5V

+0.5V

– Added typ values for internal load capacitors,

C

L0

to

C

L3

, 2.5pF, 2.5pF, 4pF, 6.5pF

– Added HYSAX

• Power Supply parameters

Data Sheet 5-82 V1.2, 2014-06

TC1724


– Updated

– Added

I

I

DD

DDP,

for

– Added text to of

– Added PD for

f f

I

DDM,

CPU

DDP_FP

=80MHz for max and realistic patterns

f

CPU

I

– Updated PD values for max and real patterns, all external, and 5V only with ext.pass device mode

f

CPU

=133MHz

CPU

=133MHz to the note for the PD parameter.

=80Mhz for max and realistic patterns for both all external mode

– Current consumption for LVDS pad pairs is updated for all LVDS pads in total

– Deleted the redundant

– Updated

– Deleted

I

R

I

I

DDP_FP,

THJA

parameter

• Power Sequencing

DDP

DDP_PORST

,

I

DD_PORST

– Added Power Sequencing for 3.3V Supply Only section

• Power, Pad and Reset Timing parameters

– Removed redundant note for

t

HDH

,

t

HDS

– Added text from note “TESTMODE/TRST” to the name of

t

POH

and

t

POS note

• EVR Parameters

, deleted

– Added

I

PU_VDPG

,

V

IH

and

V

IL

parameters in Pass Device Detector Table

– Added EVR Parameter Table

• PLL SYSCLK parameters

– Changed max value for

f

VCO

– Added min value of 50us for

t

L

– Included formula 1 and 2

– Removed note for peak-to-peak noise on pad supply voltage

• PLL ERAY parameters

– Changed typ value to 250MHz for

t f

PLLBASE

– Added min value of 50us for

L

– Removed note for peak-to-peak noise on pad supply voltage

• JTAG Interface parameters

– Changed to ‘=’ signs in the notes for

t

8

,

• DAP parameters

t

9

and

t

10

• Peripheral Timings

– Removed note for Peripheral Timings “Peripheral timing parameters are not subject to production test. They are verified by design/characterization.”

• MLI Timing

– Added text for MLI parameters valid for CL=25pF

• MLI Receiver parameters

– Changed

f

SYS

to 110MHz in footnote 3

• MLI Tranmitter parameters

– Changed

t

13

, TCLK rise time and

• MSC parameters

t

14

, TCLK fall time to 0.3 x t10

– Added text for MSC parameters valid for CL=25pF

– Added limits for different pad drive strength of

t

45

Data Sheet 5-83 V1.2, 2014-06

TC1724


• parameters

– Changed min value of t

t

52

• ERAY parameters

to 16.5ns



t t

60

61

-

t

62

– Changed min and max values of

t

63


t

64

– Added

dTxdly

, dRxdly

-

t

65

– Updated ERAY timing figure

• Flash32 parameters

– Updated

t

PRD

,

t

PRP


WS

DF

– Updated footnote 3

to 50ns x

f

LMB

• Package parameters

– Added

R

THJCT

• Package outline

,

R

THJCB

,

R

THJCL

for LQFP144

– Added package outline for LQFP176

Changes from V0.5 to V0.6

• Added max limit for

V

RST5 for 5.0V single supply

• Removed note above MLI Transmitter table

•

•

• Updated limits for

•

•

Updated conditions for

Updated limits for

Updated limits for

Updated limits for

R

R

R

R t

FL

DSONW

DSONW

DSONW

DSONW and

and

and

and

and

• Added footnote 7 to ADC table

t

RL for LVDS pad parameters

R

R

R

R

DSONM

for Class A1 pads

DSONM

DSONM

and

and

R

R

DSON1+

for Class A1+ pads

for Class A2 pads

DSONM

DSON2

for Class F pads

•

•

•

Updated

Changed

Q

CONV of ADC table

Updated conditions to

t

• Removed condition for

t

L of PLL Sysclk

19 of DAP from SR to CC

V

• Added FADC input circuit

5

•

•

•

•

•

•

•

t

Updated max limit for

BWG and

Added

V t

BWR

FAREFI

t

I

V

V

AGND0

and min limit for are added to ADC table

• Updated description of

t

CAL

Added a placeholder for

R

AIN, at a separate ADC table for



t t

V

DDM

AWAF,

FWAF,

• Removed limits of gain=8 for

and

• Updated limit of

Typo in Note for

V5

FAGNDI

R t t

AIN7T,

EF

R

=3.3V

DNL,

AWAS to both ADC tables for

FWAS to FADC table for

GRAD

parameters

SF2

to min 120ns

AREF,

at 80MHz is corrected.

t

S,

f

V

AREF0

ADCI,

EA

V

EA

V

INL,

EA

V

GAIN,

EA and V

OFF,

TUE

DDM

=5V

DDM

=5V,

DDM

=3.3V

DDM

=3.3V

Data Sheet 5-84 V1.2, 2014-06

TC1724


• Updated max limit of

I

Σ

I

IN

.

• Added

IN

.

• Added Pin Reliability in Overload subchapter.

• Removed sentence “Exposure to conditions within the maximum ratings will not affect device reliability.” Replaced with the Pin Reliability in Overload subchapter.

• Added definition of driver strength settings, updated footnote 4 for ERAY Interface

Timing

•

•

•

•

•

• Updated TC1724

I

DD_PORST

V5

for max and real patterns, with and without ERAY,

V5

for max pattern,

PD

I

DDP

f t

to max 110mA

DDP_PORST

to max 6mA

DD

for real pattern,

• Added new parameter

•

•

•

Updated max limits of Flash parameters

Updated representation of

Updated limits of

Updated limits of

Updated limits of

Updated max limit of

Updated TC1724

Updated TC1724

• Updated

PD

I

I

I

I

I

I

DDSUM

DDM to 32mA

f

PRD,

t

PRP

CPU=133MHz,

for real pattern,

f

CPU=80MHz to max 212mA

CPU=133MHz, all external supplies.

for max and real patterns, with and without ERAY,

f f

CPU=133MHz

CPU=133MHz,

•

•

•

•

•

•

V f

CPU=80MHz, 5V only without external pass device.

LOREG33

and ∆

LIREG33

• Updated limits and test condition for 5.0V single supply ∆

•

5V only with external pass device.

Updated TC1724

Updated limit for

Removed

V

PD

R

for max and real patterns,

DSON2

of A2 pad, P_MOS

IH

for Pass Device Detector

Updated limits for

V

IL

of Pass Device Detector

Updated limits and test conditions for ∆

Updated test condition for 5.0V single supply ∆

Corrected typ and max limits for

C

OUT33

and

• Application reset boot time limits are updated

C

V

LOREG13

OUT13

• Added limit and test condition for 3.3V single supply ∆

V

V

V

LIREG13

LOREG13

and ∆

V

LIREG13

•

•

Added min limit for

Added a new parameter

t

I

OZS

,

V

STT

ILSD

• Updated limits for

BP

• Removed typical text from load of Peripheral Timing sections.

•

•

•

EF

EF

GRAD with Gain=4 is changed to TBD

V

REFI

DDM

Updated limits of is changed to TBD

• Added a placeholder for

•

•

Limits for

Min limit for

Added for

V

DDM

=3.3V

Added max and typ limits for

P

R

FAIN,

R

EF

DNL,

RAIN for

D

for real pattern,

f

EF

V

INL,

DDM

EF

=3.3V

CPU=80MHz,

• Added new variant SAK-TC1724F-192F80HR

GRAD,

EF

OFF

at a separate ADC table to max 669mW

• Updated text for Note column of

N

E

Data Sheet 5-85 V1.2, 2014-06

TC1724


• Corrected typo for Class D pads in PN-Junction Characteristics for positive/negative overload tables

•

•

•

•

Updated limits of

Updated limits of

Updated limits of

Updated limits of

I

I

P

I

• Corrected typo for

DD

for max pattern,

DD

for max pattern,

D

for max pattern,

DD

for max pattern,

C

OUT13

• Updated load jump current for

• Changed min to typ value for

C

C

OUT33

IN5

f f f f

CPU=133MHz,

CPU=80MHz,

CPU=133MHz,

CPU=80MHz,

and

C

OUT13 to max 310mA to max 248mA to max 902mA to max 810mA

for

f

CPU

=80MHz


• Name of package is updated


• Absolute maximum rating section for is updated for

t

V

DDP,

V

IN

,

V

AIN

,

V

AREF0,

V

AINF

• A footnote is added to

ERD

• A note is added, updated pad supply levels in Pin Reliability in Overload section

• Updated min limit for

I t

17

of MLI

• Added a footnote to

DDP

• Included text to power sequencing sections for setting of P0.4 and P0.5.

•

•

Added limits for

EF

Changed STT to

t

DNL for Gain= 4, 8

EVR

, updated Power, Pad and Reset Timing figure

• Changed min limit of

•

•

• Updated limit and test condition for

•

Changed min limit of

Removed

I

PU_VDPG

Updated limit for

• Updated limit and test condition for ∆

PSRR

C

for

IN5

t t

L

L

for PLL_ERAY timing

for PLL_Sysclk timing

V

DD5

PSRR

≥2.97V,

V

V

C

DD5

£3.63V

OUT33

,

V

V

C

OUT13

LOREG33

• Removed

33

,

13

• Updated test condition for ∆

LOREG13

• Updated limit and test condition for ∆

LIREG13

• Updated min limit for MSC t45, strong sharp setting, CMOS mode

• Added ∆

V

OUT33

, ∆

V

OUT13

parameters

• Updated first sentence for Chapter 5.3

• Added text for MLI and SSC parameters for validity of strong driver medium edge only

• Updated description for

t

52 and

t

53

• Changed SSC parameters from CC to SR for

t

56,

t

57,

t

58, and

t

59

• Changed min to max limit for EVR Supply ramp-up parameter

• Updated min limit for

I

PU_VDPG


• Added limits for

EF

• Added limits for

EF

GRAD

for Gain= 4, 8

REFI

Data Sheet 5-86 V1.2, 2014-06

TC1724


•

• A footnote is added for

•

•

• Added min limit for

•

Updated

V

FAGNDI

,

Updated limit for

Updated limit for

C

C

Updated limits for

f

V

OUT13

IN5

V

FAREFI

5

ADCI

V

V

, t

, changed from SR to CC

FAREFI

BWG

I

,

• Updated limits for ADC table,

R

AIN7T

,

EA

DNL

,

EA

GAIN,

EA

INL, ,

t

BWR

V

DDM

EA

,

• Corrected typo in test condition for

t

=3.3V,

OFF,

R

AWAF,

TUE f t

AWAS

ADCI

, Q

,

, t t

CONV

FWAF,

,

BWG

,

SC_D

DSON

• Removed footnote 2 from

Σ

• Added footnote 3 to

DDM

• Corrected typo for Class F in Table 14 and Table 15

t t

FWAS

BWR

,

t

AWAF,

t

AWAS

,

t

FWAF,

,

t

FWAS,

•

•

•

• Updated max limit for ADC parameter

•

•

Updated max limit for ADC parameter

Added footnote 2 for

Changed

t

26

,

t

27

from CC to SR

Added footnote 5 to

Added

t

POR_APP

t t

9

59

t

S

of JTAG parameter

V

parameter of Reset Timing parameters

• Updated max limit for ERAY parameter

t

AIN

60


• Updated limits for ADC table,

EA

DNL

,

EA

GAIN,

EA

INL ,

EA

OFF,

V

TUE

DDM

=3.3V,

, Q

CONV

• Added new marking options for TC1724

• Updated description for

t

CAL

• Added a footnote to

Q

CONV


f

ADCI

, t

BWG

,

t

BWR

,

t

AWAF,

t

AWAS,

R

AIN7T

,

•

•

• change change extend

t t

K

48

from 100ns to 200ns in table 29

49

from 100ns to 200ns in table 29

OVAN

conditon from

I

OV

≤ 0 mA;

I

OV

≥ -1 mA to

• clearify leakage definition for A1 and I pads for 150°C

I

OV

< T

≤ 0 mA;

J

I

≤ 160°C

OV

≥ -2 mA

•

•

• change change change

t

V

R

ILS

from 2.1V to 1.9V in table 25

56

from 1 /

AIN

f

FPI

to 1 /

f

FPI

+ 1 in table 30

from 4500 Ohm to 9000 Ohm in table 15

• remove the following product options:

– SAK-TC1724N-192F133HL

– SAK-TC1724F-128F133HL

– SAK-TC1724F-128F133HR

– SAK-TC1724N-128F133HL

– SAK-TC1724N-128F133HR

– SAK-TC1724N-128F80HL

– SAK-TC1724N-128F80HR

– SAK-TC1724N-192F133HL

Data Sheet 5-87 V1.2, 2014-06

TC1724


– SAK-TC1724F-128F80HR

• shift the product SAK-TC1724N-192F133HR from step AB to AC

• add for products SAK-TC1724F-192F133HR and SAK-TC1724N-192F80HR step

AC

Data Sheet 5-88 V1.2, 2014-06

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

Infineon SAK-TC1724N-192F80HR AC Microcontroller Data Sheet

32-Bit

Microcontroller

TC1724

32-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2014-06

Microcontrollers

Edition 2014-06

Published by

Infineon Technologies AG

81726 Munich, Germany

2014 Infineon Technologies AG

All Rights Reserved.

Legal Disclaimer

Information

Warnings

32-Bit

Microcontroller

TC1724

32-Bit Single-Chip Microcontroller

Data Sheet

V1.2 2014-06

Microcontrollers

Table of Contents

1 Summary of Features

2 System Overview of the TC1724

3 Pinning

4 Identification Registers

5 Electrical Parameters

Analog Input Circuitry

Reference Voltage Input Circuitry

FAINxN

FAINxP

FADC Analog Input Stage

/2

FADC Reference Voltage

Input Circuitry

V

3.3V

1.3V

t

PORST (output)

PORST (input)

t

5.5V

4.5V

3.63V

2.97V

1.43V

1.17V

0.5

TCK

0.9

0.1

TMS

TDI

TDO

0.5

0.9

0.1

MLI Transmitter Timing

MLI Receiver Timing

BSS

TXD

TXD

BSS

RXD

Last CRC Byte

Last CRC Byte

RXD

FES

FES

Related manuals

Infineon

SAK-TC1766-192F80HL BD

Infineon

SAK-TC1728N-192F133HR AC

Infineon

SAK-TC1762-128F80HL AC