Atmel AT90S1200 Datasheet

Features

• Utilizes the AVR ® RISC Architecture

• AVR - High-performance and Low-power RISC Architecture

– 89 Powerful Instructions - Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Up to 12 MIPS Throughput at 12 MHz

• Data and Nonvolatile Program Memory

– 1K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 64 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In System Programming

• Special Microcontroller Features

– Low-power Idle and Power Down Modes

– External and Internal Interrupt Sources

– Selectable On-chip RC Oscillator for Zero External Components

• Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.0 mA

– Idle Mode: 0.4 mA

– Power Down Mode: <1 µA

• I/O and Packages

– 15 Programmable I/O Lines

– 20-pin PDIP and SOIC

• Operating Voltages

– 2.7 - 6.0V (AT90S1200-4)

– 4.0 - 6.0V (AT90S1200-12)

• Speed Grades

– 0 - 4 MHz, (AT90S1200-4)

– 0 - 12 MHz, (AT90S1200-12)

Description

The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the

(continued)

Pin Configuration

8-bit

Microcontroller with 1K bytes

In-System

Programmable

Flash

AT90S1200

Rev. 0838E–04/99

1

AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

Block Diagram

Figure 1. The AT90S1200 Block Diagram

2

AT90S1200

AT90S1200

The architecture supports high level languages efficiently as well as extremely dense assembler code programs. The

AT90S1200 provides the following features: 1K bytes of In-System Programmable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32 general purpose working registers, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for program downloading and two software selectable power saving modes. The

Idle Mode stops the CPU while allowing the registers, timer/counter, watchdog and interrupt system to continue functioning.

The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip In-System Programmable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable

Flash on a monolithic chip, the Atmel AT90S1200 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90S1200 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The

Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S1200 as listed on page 27.

Port D (PD6..PD0)

Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA.

As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S1200 as listed on page 31.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 2 . Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

3

Figure 2. Oscillator Connections

HC

MAX 1 HC BUFFER

C2

XTAL2

C1

XTAL1

GND

Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.

Figure 3. External Clock Drive Configuration

On-chip RC Oscillator

An on-chip RC oscillator running at a fixed frequency of 1 MHz can be selected as the MCU clock source. If enabled, the

AT90S1200 can operate with no external components. A control bit - RCEN in the Flash Memory selects the on-chip RC oscillator as the clock source when programmed (“0”). The AT90S1200 is normally shipped with this bit unprogrammed

(“1”). Parts with this bit programmed can be ordered as AT90S1200A. The RCEN-bit can be changed by parallel programming only. When using the on-chip RC oscillator for serial program downloading, the RCEN bit must be programmed in parallel programming mode first.

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle.

4

AT90S1200

Figure 4. The AT90S1200 AVR RISC Architecture

AT90S1200

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data memories. The program memory is accessed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is

In-System Programmable Flash memory.

With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a

3 level deep hardware stack dedicated for subroutines and interrupts.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters,

A/D-converters, and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.

5

General Purpose Register File

Figure 5 shows the structure of the 32 general purpose registers in the CPU.

Figure 5. AVR CPU General Purpose Working Registers

7 0

General

Purpose

Working

Registers

R0

R1

R2

…

…

R28

R29

R30 (Z-Register)

R31

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or on a single register apply to the entire register file.

Register 30 also serves as an 8-bit pointer for indirect address of the register file.

ALU - Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logic and bit-functions.

In-System Programmable Flash Program Memory

The AT90S1200 contains 1K bytes on-chip In-System Programmable Flash memory for program storage. Since all instructions are single 16-bit words, the Flash is organized as 512 x 16. The Flash memory has an endurance of at least 1000 write/erase cycles.

The AT90S1200 Program Counter is 9-bit wide, thus addressing the 512 words Flash program memory.

See page 34 for a detailed description on Flash data downloading.

Program and Data Addressing Modes

The AT90S1200 AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the AT90S1200. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.

6

AT90S1200

Register Direct, Single Register Rd

Figure 6. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Indirect

Figure 7. Indirect Register Addressing

The register accessed is the one pointed to by the Z-register (R30).

AT90S1200

7

Register Direct, Two Registers Rd and Rr

Figure 8. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

I/O Direct

Figure 9. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

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AT90S1200

AT90S1200

Relative Program Addressing, RJMP and RCALL

Figure 10. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.

Subroutine and Interrupt Hardware Stack

The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts. The hardware stack is 9 bit wide and stores the Program Counter - PC - return address while subroutines and interrupts are executed.

RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels

1-2 are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack.

If more than 3 subsequent subroutine calls or interrupts are executed, the first values written to the stack are overwritten.

EEPROM Data Memory

The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 23 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control register. For the SPI data downloading, see page 42 for a detailed description.

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution and internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used.

Figure 11 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

9

Figure 11. The Parallel Instruction Fetches and Instruction Executions

T1 T2

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T3 T4

Figure 12 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 12. Single Cycle ALU Operation

T1 T2 T3 T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

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AT90S1200

AT90S1200

I/O Memory

The I/O space definition of the AT90S1200 is shown in the following table:

Table 1. The AT90S1200 I/O Space

Address Hex Name

$3F

$3B

SREG

GIMSK

Function

Status REGister

General Interrupt MaSK register

$32

$21

$1E

$1D

$39

$38

$35

$33

TIMSK

TIFR

MCUCR

TCCR0

TCNT0

WDTCR

EEAR

EEDR

Timer/Counter Interrupt MaSK register

Timer/Counter Interrupt Flag register

MCU general Control Register

Timer/Counter 0 Control Register

Timer/Counter 0 (8-bit)

Watchdog Timer Control Register

EEPROM Address Register

EEPROM Data Register

$1C

$18

$17

$16

EECR

PORTB

DDRB

PINB

EEPROM Control Register

Data Register, Port B

Data Direction Register, Port B

Input Pins, Port B

$12

$11

PORTD

DDRD

Data Register, Port D

Data Direction Register, Port D

$10 PIND Input Pins, Port D

$08 ACSR Analog Comparator Control and Status Register

Note: Reserved and unused locations are not shown in the table.

All AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and

OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The different I/O and peripherals control registers are explained in the following sections.

11

Status Register - SREG

The AVR status register - SREG - at I/O space location $3F is defined as:

Bit

$3F

Read/Write

Initial value

7

I

R/W

0

6

T

R/W

0

5

H

R/W

0

4

S

R/W

0

3

V

R/W

0

2

N

R/W

0

1

Z

R/W

0

0

C

R/W

0

SREG

• Bit 7 - I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6 - T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

• Bit 5 - H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.

• Bit 4 - S: Sign Bit, S = N

⊕

V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set Description for detailed information.

• Bit 3 - V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.

• Bit 2 - N: Negative Flag

The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set

Description for detailed information.

• Bit 1 - Z: Zero Flag

The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.

• Bit 0 - C: Carry Flag

The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information.

Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

Reset and Interrupt Handling

The AT90S1200 provides 3 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set

(one) together with the I-bit in the status register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request

0 etc.’

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AT90S1200

AT90S1200

Table 2. Reset and Interrupt Vectors

Vector No.

1

Program Address

$000

2

4

5

$001

$002

$003

Source

RESET

INT0

TIMER0, OVF0

ANA_COMP

Interrupt Definition

Hardware Pin, Power-on Reset and Watchdog Reset

External Interrupt Request 0

Timer/Counter0 Overflow

Analog Comparator

The most typical and general program setup for the Reset and Interrupt Vector Addresses are:

Address Labels Code Comments

$000 rjmp RESET ; Reset Handler

$001

$002

$003

;

$004

… rjmp rjmp rjmp

EXT_INT0

TIM0_OVF

ANA_COMP

MAIN: <instr> xxx

… … …

; IRQ0 Handler

; Timer0 Overflow Handler

; Analog Comparator Handler

; Main program start

Reset Sources

The AT90S1200 has three sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V

POT

).

• External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.

• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 13 shows the reset logic. Table 3 defines the timing and electrical parameters of the reset circuitry. Note that Power On Reset timing is clocked by the internal RC oscillator. Refer to characterization data for RC oscillator frequency at other V

CC

voltages.

Figure 13. Reset Logic

13

Table 3. Reset Characteristics (V

CC

= 5.0V)

Parameter Symbol

V

POT

(1)

Power-On Reset Threshold Voltage (rising)

Power-On Reset Threshold Voltage (falling)

Min

0.8

Typ

1.2

Max

1.6

0.2

0.4

0.6

V

RST

Pin Threshold Voltage t t

POR

TOUT

Power-On Reset Period

Reset Delay Time-Out Period (The Time-out period equals 16K WDT cycles. See “Typical

Characteristics” on page 48. for typical WDT frequency at different voltages).

2

11

3

16

Notes: 1. The Power-On Reset will not work unless the supply voltage has been below Vpot (falling).

0.85V

CC

4

21 ms

Power-on Reset

A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 13, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after V

CC

has reached the Power-on Threshold voltage - V

POT

, regardless of the V

CC

rise time (see Figure 14).

Figure 14. MCU Start-Up, RESET Tied to V

CC

.

V

POT

VCC

Units

V

V

V ms

V

RST

RESET

TIME-OUT t

TOUT

INTERNAL

RESET

If the build-in start-up delay is sufficient, RESET can be connected to V

CC

directly or via an external pull-up resistor. By holding the RESET pin low for a period after V

CC

has been applied, the Power-on Reset period can be extended. Refer to

Figure 15 for a timing example on this.

14

AT90S1200

AT90S1200

Figure 15. MCU Start-up, RESET Controlled Externally

V

POT

VCC

RESET

TIME-OUT

V

RST t

TOUT

INTERNAL

RESET

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the

Reset Threshold Voltage - V

RST

on its positive edge, the delay timer starts the MCU after the Time-out period t

TOUT

has expired.

Figure 16. External Reset During Operation

VCC

RESET

TIME-OUT

INTERNAL

RESET

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to page 22 for details on operation of the Watchdog.

15

Figure 17. Watchdog Reset During Operation

Interrupt Handling

The AT90S1200 has two Interrupt Mask control registers GIMSK - General Interrupt MASK register - at I/O space address

$3B and the TIMSK - Timer/Counter Interrupt MaSK register at I/O address $39.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI - is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active.

Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

General Interrupt Mask Register - GIMSK

Bit

$3B

Read/Write

Initial value

R

0

7

-

6

INT0

R/W

0

R

0

5

-

R

0

4

-

R

0

3

-

R

0

2

-

R

0

1

-

R

0

0

GIMSK

• Bit 7 - Res: Reserved bit

This bit is a reserved bit in the AT90S1200 and always read as zero.

• Bit 6 - INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.

The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or low level sensed. INT0 can be activated even if the pin is configured as an output. See also page 17.

• Bits 5..0 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and always read as zero.

16

AT90S1200

AT90S1200

Timer/Counter Interrupt Mask Register - TIMSK

Bit

$39

Read/Write

Initial value

R

0

7

-

R

0

6

-

R

0

5

-

R

0

4

-

R

0

3

-

R

0

2

-

1

TOIE0

R/W

0

R

0

0

TIMSK

• Bits 7..2 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and always read as zero.

• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the

TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

• Bit 0 - Res: Reserved bit

This bits is a reserved bit in the AT90S1200 and always read as zero.

Timer/Counter Interrupt FLAG Register - TIFR

Bit

$38

Read/Write

Initial value

R

0

7

-

R

0

6

-

R

0

5

-

R

0

4

-

R

0

3

-

R

0

2

-

1

TOV0

R/W

0

R

0

0

TIFR

• Bits 7..2 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and always read as zero.

• Bit 1 - TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG Ibit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

• Bit 0 - Res: Reserved bit

This bits is a reserved bit in the AT90S1200 and always read as zero.

External Interrupts

The external interrupt is triggered by the INT0 pin. The interrupt can trigger on rising edge, falling edge or low level. This is set up as described in the specification for the MCU control register - MCUCR. When INT0 is level triggered, the interrupt is pending as long as INT0 is held low.

The interrupt is triggered even if INT0 is configured as an output. This provides a way to generate a software interrupt.

The interrupt flag can not be directly accessed by the user. If an external edge triggered interrupt is suspected to be pending, the flag can be cleared as follows.

1.

Disable the external interrupt by clearing the INT0 flag in GIMSK.

2.

Select level triggered interrupt.

3.

Select desired interrupt edge.

4.

Re-enable the external interrupt by setting INT0 in GIMSK.

17

Interrupt Response Time

The interrupt execution response for all the enabled

AVR

interrupts is 4 clock cycles minimum. 4 clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this

4 clock cycle period, the Program Counter (9 bits) is pushed onto the Stack. The vector is normally a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (9 bits) is popped back from the Stack and the I flag in SREG is set. When the

AVR

exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Subroutine and Interrupt Stack is a 3-level true hardware stack, and if more than 3 nested subroutines and interrupts are executed, only the most recent 3 return addresses are stored.

MCU Control Register - MCUCR

The MCU Control Register contains general microcontroller control bits for general MCU control functions.

Bit

$35

Read/Write

Initial value

R

0

7

-

R

0

6

-

5

SE

R/W

0

4

SM

R/W

0

R

0

3

-

R

0

2

-

1

ISC01

R/W

0

0

ISC00

R/W

0

MCUCR

• Bits 7, 6 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and always read as zero.

• Bit 5 - SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the

MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

• Bit 4 - SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode.

When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph “Sleep Modes” on the following page.

• Bits 3, 2 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and always read as zero.

• Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 bit 1 and bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask in the

GIMSK register is set. The level and edges on the external INT0 pin that activate the interrupt are defined as:

Table 4. Interrupt 0 Sense Control

ISC01

0

ISC00

0

Description

The low level of INT0 generates an interrupt request.

0

1

1

0

Reserved

The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register.

Otherwise an interrupt can occur when the bits are changed.

18

AT90S1200

AT90S1200

The value on the INT0 pin is sampled before detecting edges. If edge interrupt is selected, pulses with a duration longer than one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and the I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction makes the MCU enter the Idle Mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset. If wakeup from the

Analog Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the

Analog Comparator Control and Status register - ACSR. This will reduce power consumption in Idle Mode. When the MCU wakes up from Idle mode, the CPU starts program execution immediately.

Power Down Mode

When the SM bit is set (one), the SLEEP instruction makes the MCU enter the Power Down Mode. In this mode, the external oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a watchdog reset (if enabled), an external level interrupt on INT0 can wake up the MCU.

Note that when a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the reset delay time-out period t

TOUT

. Otherwise, the device will not wake up.

Timer/Counter0

The AT90S1200 provides one general purpose 8-bit Timer/Counter. The Timer/Counter0 gets the prescaled clock from the

10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.

Timer/Counter0 Prescaler

Figure 18 shows the general Timer/Counter0 prescaler.

19

Figure 18. Timer/Counter0 Prescaler

T0

TCK0

The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the

Timer/Counter0, added selections as CK, external clock source and stop, can be selected as clock sources. Figure 19 shows the block diagram for Timer/Counter0.

Figure 19. Timer/Counter 0 Block Diagram

T0

20

AT90S1200

AT90S1200

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Register - TCCR0. The overflow status flag is found in the

Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter0 Control Register - TCCR0.

The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register - TIMSK.

When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.

The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions.

Timer/Counter0 Control Register - TCCR0

Bit

$33

Read/Write

Initial value

R

0

7

-

R

0

6

-

R

0

5

-

R

0

4

-

R

0

3

-

2

CS02

R/W

0

1

CS01

R/W

0

• Bits 7..3 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and always read as zero.

• Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0

The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer/Counter0.

0

CS00

R/W

0

Table 5. Clock 0 Prescale Select

CS02

0

CS01

0

1

1

1

0

1

0

0

0

1

1

1

0

0

1

1

0

1

0

1

CS00

0

1

0

Description

Stop, the Timer/Counter0 is stopped.

CK

CK / 8

CK / 64

CK / 256

CK / 1024

External Pin T0, falling edge

External Pin T0, rising edge

TCCR0

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting.

Timer Counter 0 - TCNT0

Bit

$32

Read/Write

Initial value

7

MSB

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

LSB

R/W

0

TCNT0

The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.

21

Watchdog Timer

The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1MHz This is the typical value at V

CC

= 5V.

See characterization data for typical values at other V

CC

levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted, see Table 6 for a detailed description. The WDR - Watchdog Reset - instruction resets the

Watchdog Timer. Eight different clock cycle periods can be selected to determine the maximum period between two WDR instructions to avoid that the Watchdog Timer resets the MCU. If the reset period expires without another WDR instruction, the AT90S1200 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 15.

Figure 20. Watchdog Timer

Watchdog Timer Control Register - WDTCR

Bit

$21

Read/Write

Initial value

R

0

7

-

R

0

6

-

R

0

5

-

R

0

4

-

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

0

WDP0

R/W

0

WDTCR

• Bits 7..4 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and will always read as zero.

• Bit 3 - WDE: Watchdog Enable

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled.

• Bits 2..0 - WDP2..0: Watchdog Timer Prescaler 2,1 and 0

The WDP2..0 determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 6.

22

AT90S1200

AT90S1200

Table 6. Watchdog Timer Prescale Select

WDP2

0

0

1

1

0

0

WDP1

0

0

1

1

0

0

WDP0

0

1

0

1

0

1

Number of WDT

Oscillator cycles

16K cycles

32K cycles

64K cycles

128K cycles

256K cycles

512K cycles

Typical time-out at V

CC

= 3.0V

47 ms

94 ms

0.19 s

0.38 s

0.75 s

1.5 s

Typical time-out at V

CC

= 5.0V

15 ms

30 ms

60 ms

0.12 s

0,24 s

0.49 s

1 1 0 1,024K cycles 3.0 s 0.97 s

1 1 1 2,048K cycles 6.0 s 1.9 s

Note: The frequency of the watchdog oscillator is voltage dependent as shown in “Typical Characteristics” on page 48.

The WDR - Watchdog Reset - instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the watchdog timer may not start to count from zero.

EEPROM Read/Write Access

The EEPROM access registers are accessible in the I/O space.

The write access time is in the range of 2.5 - 4ms, depending on the V

CC

voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precaution must be taken. In heavily filtered power supplies, V

CC

is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “EEPROM Control

Register - EECR” on page 24 for details on this.

When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed.

EEPROM Address Register - EEAR

Bit

$1E

Read/Write

Initial value

R

0

7

-

R

0

6

-

5

EEAR5

R/W

0

4

EEAR4

R/W

0

3

EEAR3

R/W

0

2

EEAR2

R/W

0

1

EEAR1

R/W

0

0

EEAR0

R/W

0

EEAR

• Bit 7,6 - Res: Reserved bits

These bits are reserved bit in the AT90S1200 and will always read as zero.

• Bits 5..0 - EEAR5..0: EEPROM Address

The EEPROM Address Register - EEAR5..0 - specifies the EEPROM address in the 64-byte EEPROM space. The

EEPROM data bytes are addressed linearly between 0 and 63.

23

EEPROM Data Register - EEDR

Bit

$1D

Read/Write

Initial value

7

MSB

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

LSB

R/W

0

EEDR

• Bits 7..0 - EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

EEPROM Control Register - EECR

Bit

$1C

Read/Write

Initial value

R

0

7

-

R

0

6

-

R

0

5

-

R

0

4

-

R

0

3

-

R

0

2

-

1

EEWE

R/W

0

0

EERE

R/W

0

EECR

• Bits 7..2 - Res: Reserved bits

These bits are reserved bits in the AT90S1200 and will always be read as zero.

• Bit 1 - EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. When the write access time (typically 2.5ms at V

CC

= 5V and 4ms at V

CC

= 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 - EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the

EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the

EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for two cycles before the next instruction is executed.

Caution: If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during EEPROM write operation to avoid these problems.

Prevent EEPROM Corruption

During periods of low V

CC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the

EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):

1.

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low V

CC

Reset Protection circuit, often referred to as a Brown-Out Detector (BOD). Please refer to application note AVR 180 for design considerations regarding power-on reset and low voltage detection.

2.

Keep the AVR core in Power Down Sleep Mode during periods of low V

CC

. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.

3.

Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory can not be updated by the CPU, and will not be subject to corruption.

24

AT90S1200

AT90S1200

Analog Comparator

The analog comparator compares the input values on the positive input PB0 (AIN0) and the negative input PB1 (AIN1).

When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog

Comparator Output, ACO is set (one). The comparator’s output can be set to trigger the Analog Comparator interrupt. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 21 .

Figure 21. Analog Comparator Block Diagram

Analog Comparator Control and Status Register - ACSR

Bit

$08

Read/Write

Initial value

7

ACD

R/W

0

R

0

6

-

5

ACO

R

0

4

ACI

R/W

0

3

ACIE

R/W

0

R

0

2

-

1

ACIS1

R/W

0

0

ACIS0

R/W

0

ACSR

• Bit 7 - ACD: Analog Comparator Disable

When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog

Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

• Bit 6 - Res: Reserved bit

This bit is a reserved bit in the AT90S1200 and will always read as zero.

• Bit 5 - ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

• Bit 4 - ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog

Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation.

• Bit 3 - ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated.

When cleared (zero), the interrupt is disabled.

• Bit 2 - Res: Reserved bit

This bit is a reserved bit in the AT90S1200 and will always read as zero.

25

• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 7.

Table 7. ACIS1/ACIS0 Settings

ACIS1

0

0

1

ACIS0

0

1

0

Interrupt Mode

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

Note: When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.

I/O Ports

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).

Port B

Port B is an 8-bit bi-directional I/O port.

Three I/O memory address locations are allocated for the Port B, one each for the Data Register - PORTB ($18), Data

Direction Register - DDRB ($17) and the Port B Input Pins - PINB ($16). The Port B Input Pins address is read only, while the Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.

The Port B pins with alternate functions are shown in the following table:

Table 8. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB0

PB1

PB5

PB6

PB7

AIN0 (Analog comparator positive input)

AIN1 (Analog comparator negative input)

MOSI (Data input line for memory downloading)

MISO (Data output line for memory uploading)

SCK (Serial clock input)

When the pins are used for the alternate function, the DDRB and PORTB register has to be set according to the alternate function description.

26

AT90S1200

AT90S1200

Port B Data Register - PORTB

Bit

$18

Read/Write

Initial value

7

PORTB7

R/W

0

6

PORTB6

R/W

0

Port B Data Direction Register - DDRB

Bit

$17

Read/Write

Initial value

7

DDB7

R/W

0

6

DDB6

R/W

0

5

PORTB5

R/W

0

5

DDB5

R/W

0

4

PORTB4

R/W

0

4

DDB4

R/W

0

3

PORTB3

R/W

0

3

DDB3

R/W

0

2

PORTB2

R/W

0

2

DDB2

R/W

0

1

PORTB1

R/W

0

1

DDB1

R/W

0

0

PORTB0

R/W

0

0

DDB0

R/W

0

PORTB

DDRB

Port B Input Pin Address - PINB

Bit

$16

Read/Write

Initial value

7

PINB7

R

Hi-Z

6

PINB6

R

Hi-Z

5

PINB5

R

Hi-Z

4

PINB4

R

Hi-Z

3

PINB3

R

Hi-Z

2

PINB2

R

Hi-Z

1

PINB1

R

Hi-Z

0

PINB0

R

Hi-Z

PINB

The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port

B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.

Port B as General Digital I/O

All 8 pins in Port B have equal functionality when used as digital I/O pins.

PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) and the pin is configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active.

Table 9. DDBn Effect on Port B Pins

DDBn

0

PORTBn

0

I/O

Input

0

1

1

0

1 1

Note: n: 7,6...0, pin number.

Input

Output

Output

Pull up

No

Yes

No

No

Comment

Tri-state (Hi-Z)

PBn will source current if ext. pulled low.

Push-Pull Zero Output

Push-Pull One Output

Alternate Functions of Port B

The alternate pin functions of Port B are:

• SCK - Port B, Bit 7

SCK, Clock input pin for memory up/downloading.

• MISO - Port B, Bit 6

MISO, Data output pin for memory uploading.

• MOSI - Port B, Bit 5

MOSI, Data input pin for memory downloading.

27

• AIN1 - Port B, Bit 1

AIN1, Analog Comparator Negative Input. When configured as an input (DDB1 is cleared (zero) and with the internal MOS pull up resistor switched off [PB1 is cleared (zero)], this pin also serves as the negative input of the on-chip analog comparator.

• AIN0 - Port B, Bit 0

AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared (zero) and with the internal MOS pull up resistor switched off [PB0 is cleared (zero)], this pin also serves as the positive input of the on-chip analog comparator.

Port B Schematics

Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.

Figure 22. Port B Schematic Diagram (pins PB0 and PB1)

28

AT90S1200

Figure 23. Port B Schematic Diagram (Pins PB2, PB3 and PB4)

AT90S1200

2,

Figure 24. Port B Schematic Diagram, Pin PB5

29

Figure 25. Port B Schematic Diagram, Pin PB6

Figure 26. Port B Schematic Diagram, Pin PB7

30

AT90S1200

AT90S1200

Port D

Three I/O memory address locations are allocated for the Port D, one each for the Data Register - PORTD ($12), Data

Direction Register - DDRD ($11) and the Port D Input Pins - PIND ($10). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write.

Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA.

As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated.

Some Port D pins have alternate functions as shown in the following table:

Table 10. Port D Pins Alternate Functions

Port Pin Alternate Function

PD2

PD4

INT0 (External interrupt 0 input)

T0 (Timer/Counter 0 external input)

Port D Data Register - PORTD

Bit

$12

Read/Write

Initial value

R

0

7

-

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

0

PORTD0

R/W

0

PORTD

Port D Data Direction Register - DDRD

Bit

$11

Read/Write

Initial value

R

0

7

-

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

0

DDD0

R/W

0

DDRD

Port D Input Pins Address - PIND

Bit

$10

Read/Write

Initial value

R

0

7

-

6

PIND6

R

Hi-Z

5

PIND5

R

Hi-Z

4

PIND4

R

Hi-Z

3

PIND3

R

Hi-Z

2

PIND2

R

Hi-Z

1

PIND1

R

Hi-Z

0

PIND0

R

Hi-Z

PIND

The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each

Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.

31

Port D as General Digital I/O

PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PORTDn is set (one) when DDDn is configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTDn bit has to be cleared (zero) or the pin has to be configured as an output pin. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active.

Table 11. DDDn Bits Effect on Port D Pins

DDDn PORTDn I/O Pull up

0

0

0

1

Input

Input

1 0 Output

1 1

Note: n: 6…0, pin number.

Output

No

Yes

No

No

Comment

Tri-state (Hi-Z)

PDn will source current if ext. pulled low.

Push-Pull Zero Output

Push-Pull One Output

Alternate Functions for Port D

The alternate functions of Port D are:

• T0 - Port D, Bit 4

T0, Timer/Counter0 clock source. See the Timer description for further details.

• INT0 - Port D, Bit 2

INT0, External Interrupt source 0. See the interrupt description for further details.

Port D Schematics

Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.

Figure 27. Port D Schematic Diagram (Pins PD0, PD1, PD3, PD5 and PD6)

32

AT90S1200

Figure 28. Port D Schematic Diagram (Pin PD2)

AT90S1200

Figure 29. Port D Schematic Diagram (Pin PD4)

MOS

PULL-

UP

PD4

RL

RP

WP:

WD:

RL:

RP:

RD:

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

SENSE CONTROL

CS02 CS01 CS00

RD

RESET

Q

R

DDD4

D

C

WD

RESET

Q

R

PORTD4

D

C

WP

TIMER0 CLOCK

SOURCE MUX

33

Memory Programming

Program and Data Memory Lock Bits

The AT90S1200 MCU provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 12. The Lock bits can only be erased with the Chip Erase command.

Table 12. Lock Bit Protection Modes

Memory Lock Bits Protection Type

Mode

1

2

LB1

1

0

LB2

1

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled.

(1)

3 0 0 Same as mode 2, and verify is also disabled.

Note: 1. In Parallel mode, further programming of the Fuse bits are also disabled. Program the Fuse bits before programming the

Lock bits.

Fuse Bits

The AT90S1200 has two Fuse bits, SPIEN and RCEN.

• When the SPIEN Fuse bit is programmed (“0”), Serial Program Downloading is enabled. Default value is programmed

(“0”).

• When the RCEN Fuse bit is programmed (“0”), MCU clocking from the internal RC oscillator is selected. Default value is erased (“1”). Parts with this bit pre-programmed (“0”) can be delivered on demand.

The Fuse bits are not accessible in Serial Programming Mode. The status of the Fuse bits is not affected by Chip Erase.

Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space.

For the AT90S1200

(Note:)

they are:

1.

$00: $1E (indicates manufactured by Atmel)

2.

$01: $90 (indicates 1 kB Flash memory)

3.

$02: $01 (indicates AT90S1200 device when $01 is $90)

Note: When both Lock bits are programmed (Lock mode 3), the Signature Bytes can not be read in serial mode. Reading the

Signature Bytes will return: $00, $01 and $02.

Programming the Flash and EEPROM

Atmel’s AT90S1200 offers 1K bytes of in-system reprogrammable Flash Program memory and 64 bytes of EEPROM Data memory.

The AT90S1200 is normally shipped with the on-chip Flash Program memory and EEPROM Data memory arrays in the erased state (i.e. contents = $FF) and ready to be programmed. This device supports a High-Voltage (12V) Parallel programming mode and a Low-Voltage Serial programming mode. The +12V is used for programming enable only, and no current of significance is drawn by this pin. The serial programming mode provides a convenient way to download Program and Data into the AT90S1200 inside the user’s system.

34

AT90S1200

AT90S1200

The Program and Data memory arrays on the AT90S1200 are programmed byte-by-byte in either programming modes.

For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the serial programming mode.

During programming, the supply voltage must be in accordance with Table 13.

Table 13. Supply voltage during programming

Part

AT90S1200

Serial programming

2.7 - 6.0V

Parallel programming

4.5 - 5.5V

Parallel Programming

This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Lock bits and

Fuse bits in the AT90S1200.

Figure 30. Parallel Programming

Signal Names

In this section, some pins of the AT90S1200 are referenced by signal names describing their function during parallel programming rather than their pin names, see Figure 30 and Table 14. Pins not described in Table 14 are referenced by pin names.

The XA1/XA0 pins determines the action executed when the XTAL1 pin is given a positive pulse. The coding is shown in

Table 15.

35

When pulsing WR or OE, the Command loaded determines the action executed. The Command is a byte where the different bits are assigned functions as shown in Table 16.

Table 14. Pin Name Mapping

Signal Name in

Programming Mode

RDY/BSY

Pin Name

PD1

OE

WR

BS

XA0

XA1

DATA

PD2

PD3

PD4

PD5

PD6

PB0-7

I

I

I/O Function

O 0: Device is busy programming, 1: Device is ready for new command

Output Enable (Active low)

Write Pulse (Active low)

I

I Byte Select (‘0’ selects low byte, ‘1’ selects high byte)

XTAL Action Bit 0

I XTAL Action Bit 1

I/O Bidirectional Databus (Output when OE is low)

.

Table 15. XA1 and XA0 Coding

XA1

0

XA0

0

Action when XTAL1 is Pulsed

Load Flash or EEPROM Address (High or low address byte for Flash determined by BS)

0

1

1

1

0

1

Load Data (High or low data byte for Flash determined by BS)

Load Command

No Action, Idle

Table 16. Command Byte Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse Bits

Write Lock Bits

Write Flash

Write EEPROM

Read Signature Bytes

Read Fuse and Lock Bits

Read Flash

Read EEPROM

36

AT90S1200

AT90S1200

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1.

Apply supply voltage according to Table 13, between V

CC

and GND.

2.

Set the RESET and BS pin to “0” and wait at least 100 ns.

3.

Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode.

Chip Erase

The Chip Erase command will erase the Flash and EEPROM memories, and the Lock bits. The Lock bits are not reset until the Flash and EEPROM have been completely erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash or EEPROM is reprogrammed.

Load Command “Chip Erase”

1.

Set XA1, XA0 to “10”. This enables command loading.

2.

Set BS to “0”.

3.

Set DATA to “1000 0000”. This is the command for Chip erase.

4.

Give XTAL1 a positive pulse. This loads the command.

5.

Give WR a t

WLWH_CE wide negative pulse to execute Chip Erase, t

WLWH_CE is found in Table 17. Chip Erase does not generate any activity on the RDY/BSY pin.

Programming the Flash

A: Load Command “Write Flash”

1.

Set XA1, XA0 to “10”. This enables command loading.

2.

Set BS to “0”

3.

Set DATA to “0001 0000”. This is the command for Write Flash.

4.

Give XTAL1 a positive pulse. This loads the command.

B: Load Address High Byte

1.

Set XA1, XA0 to “00”. This enables address loading.

2.

Set BS to “1”. This selects high byte.

3.

Set DATA = Address high byte ($00 - $01)

4.

Give XTAL1 a positive pulse. This loads the address high byte.

C: Load Address Low Byte

1.

Set XA1, XA0 to “00”. This enables address loading.

2.

Set BS to “0”. This selects low byte.

3.

Set DATA = Address low byte ($00 - $FF)

4.

Give XTAL1 a positive pulse. This loads the address low byte.

D: Load Data Low Byte

1.

Set XA1, XA0 to “01”. This enables data loading.

2.

Set DATA = Data low byte ($00 - $FF)

3.

Give XTAL1 a positive pulse. This loads the data low byte.

E: Write Data Low Byte

1.

Set BS to “0”. This selects low data.

2.

Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low.

3.

Wait until RDY/BSY goes high to program the next byte.

(See Figure 31 for signal waveforms.)

F: Load Data High Byte

37

1.

Set XA1, XA0 to “01”. This enables data loading.

2.

Set DATA = Data high byte ($00 - $FF)

3.

Give XTAL1 a positive pulse. This loads the data high byte.

G: Write Data High Byte

1.

Set BS to “1”. This selects high data.

2.

Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low.

3.

Wait until RDY/BSY goes high to program the next byte.

(See Figure 32 for signal waveforms.)

The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory locations.

• Address high byte needs only be loaded before programming a new 256 word page in the Flash.

• Skip writing the data value $FF, that is the contents of the entire Flash and EEPROM after a Chip Erase.

These considerations also applies to EEPROM programming, and Flash, EEPROM and Signature bytes reading.

Figure 31. Programming the Flash Waveforms

DATA $10 ADDR. HIGH ADDR.LOW

DATA LOW

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET 12V

OE

38

AT90S1200

AT90S1200

Figure 32. Programming the Flash Waveforms (Continued)

DATA DATA HIGH

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET +12V

OE

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to Programming the Flash for details on Command and

Address loading):

1.

A: Load Command “0000 0010”.

2.

B: Load Address High Byte ($00 - $01).

3.

C: Load Address Low Byte ($00 - $FF).

4.

Set OE to “0”, and BS to “0”. The Flash word low byte can now be read at DATA.

5.

Set BS to “1”. The Flash word high byte can now be read from DATA.

6.

Set OE to “1”.

Programming the EEPROM

The programming algorithm for the EEPROM data memory is as follows (refer to Programming the Flash for details on

Command, Address and Data loading):

1.

A: Load Command “0001 0001”.

2.

C: Load Address Low Byte ($00 - $3F).

3.

D: Load Data Low Byte ($00 - $FF).

4.

E: Write Data Low Byte.

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to Programming the Flash for details on Command and

Address loading):

1.

A: Load Command “0000 0011”.

2.

C: Load Address Low Byte ($00 - $3F).

3.

Set OE to “0”, and BS to ‘0’. The EEPROM data byte can now be read at DATA.

4.

Set OE to “1”.

39

Programming the Fuse Bits

The algorithm for programming the Fuse bits is as follows (refer to Programming the Flash for details on Command and

Data loading):

1.

A: Load Command “0100 0000”.

2.

D: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Bit 5 = SPIEN Fuse

Bit 0 = RCEN Fuse

Bit 7-6,4-1 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3.

Give WR a t

WLWH_PFB wide negative pulse to execute the programming, the Fuse bits does not generate any activity on the RDY/BSY pin.

t

WLWH_PFB is found in Table 17. Programming

Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to Programming the Flash for details on Command and

Data loading):

1.

A: Load Command “0010 0000”.

2.

D: Load Data Low Byte. Bit n = “0” programs the Lock bit.

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

Bit 7-3,0 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3.

E: Write Data Low Byte.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to Programming the Flash for details on Command loading):

1.

A: Load Command “0000 0100”.

2.

Set OE to “0”, and BS to “1”. The Status of Fuse and Lock bits can now be read at DATA (“0” means programmed).

Bit 7 = Lock Bit1

Bit 6 = Lock Bit2

Bit 5 = SPIEN Fuse

Bit 0 = RCEN Fuse

3.

Set OE to “1”.

Observe especially that BS needs to be set to “1”.

Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and

Address loading):

1.

A: Load Command “0000 1000”.

2.

C: Load Address Low Byte ($00 - $02).

Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

3.

Set OE to “1”.

40

AT90S1200

AT90S1200

Parallel Programming Characteristics

Figure 33. Parallel Programming Timing

XTAL1 t

XLWL t

DVXH t

XHXL t

XLDX t

BVWL

Data & Contol

(DATA, XA0/1, BS) t

WLWH

WR

RDY/BSY t

WHRL

OE

DATA t

XLOL t

OLDV

Table 17. Parallel Programming Characteristics, T

A

= 25

°

C ± 10%, V

CC

=5V ± 10%

Symbol Parameter Min Typ

V

PP

I

PP t

DVXH t

XHXL

Programming Enable Voltage

Programming Enable Current

Data and Control Setup before XTAL1 High

XTAL1 Pulse Width High

11.5

67

67 t t t t

XLDX t

XLWL t

BVWL

RHBX

WLWH

WHRL

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

BS Valid to WR Low

BS Hold after RDY/BSY High

WR Pulse Width Low

(1)

WR High to RDY/BSY Low

(2)

WR Low to RDY/BSY High

(2)

67

67

67

67

67 t

WLRH t

XLOL t

OLDV

XTAL1 Low to OE Low

OE Low to DATA Valid

0.5

67 t

OHDZ t

WLWH_CE

OE High to DATA Tri-stated

WR Pulse Width Low for Chip Erase 5 t

WLWH_PFB

WR Pulse Width Low for Programming the Fuse

Bits 1.0

Notes: 1. Use t

WLWH_CE

2. If t

WLWH for Chip Erase and

is held longer than t

WLRH t

WLWH_PFB for Programming the Fuse Bits.

, no RDY/BSY pulse will be seen.

20

0.7

20

10

1.5

t

RHBX t

WLRH t

OHDZ

Max

12.5

250

0.9

20

15

1.8

ms ns ns ns ms

Units

V

µ

Α ns ns ns ns ns ns ns ns ms

41

Serial Downloading

Both the Program and Data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output), see Figure 34. After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed.

Figure 34. Serial Programming and Verify

For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the

Program and EEPROM arrays into $FF.

The Program and EEPROM memory arrays have separate address spaces: $0000 to $01FF for Flash Program memory and $000 to $03F for EEPROM Data memory.

Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and

XTAL2. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low: > 1 XTAL1 clock cycle

High: > 4 XTAL1 clock cycles

Serial Programming Algorithm

When writing serial data to the AT90S1200, data is clocked on the rising edge of SCK.

When reading data from the AT90S1200, data is clocked on the falling edge of SCK. See Figure 35, Figure 36 and Table

20 for timing details.

To program and verify the AT90S1200 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 17 ):

1.

Power-up sequence:

Apply power between V

CC

and GND while RESET and SCK are set to ‘0’. If a crystal is not connected across pins

XTAL1 and XTAL2 or the device is not running from the internal RC oscillator, apply a clock signal to the XTAL1 pin. If the programmer can not guarantee that SCK is held low during power-up, RESET must be given a positive pulse after

SCK has been set to ‘0’.

2.

Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the

MOSI (PB5) pin.

3.

If a Chip Erase is performed (must be done to erase the Flash), wait t

WD_ERASE

after the instruction, give RESET a positive pulse, and start over from Step 2. See Table 21 on page 45 for t

WD_ERASE value.

42

AT90S1200

AT90S1200

4.

The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written.

Wait t

WD_PROG

after transmitting the instruction. In an erased device, no $FFs in the data file(s) needs to be programmed. See Table 22 on page 45 for t

WD_PROG value.

5.

Any memory location can be verified by using the Read instruction which returns the content at the selected address at the serial output MISO (PB6) pin.

At the end of the programming session, RESET can be set high to commence normal operation.

6.

Power-off sequence (if needed):

Set XTAL1 to ‘0’ (if a crystal is not used or the device is running from the internal RC oscillator).

Set RESET to ‘1’.

Turn V

CC

power off.

Data Polling EEPROM

When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value

P1 until the auto-erase is finished, and then the value P2. See Table 18 for P1 and P2 values.

At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time t

WD_PROG before programming the next byte. See Table 22 for t

WD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain

$FF, can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device.

Table 18. Read back value during EEPROM polling

Part P1

AT90S1200 $00

P2

$FF

Data Polling Flash

When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF.

At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for at least t

WD_PROG

before programming the next byte. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped.

Figure 35. Serial Programming Waveforms

43

Table 19. Serial Programming Instruction Set for AT90S1200

Instruction

Programming

Enable

Byte 1

Instruction Format

Byte 2 Byte 3 Byte4 Operation

1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming while RESET is low.

Chip Erase

Read Program

Memory

Write Program

Memory

1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase both Flash and EEPROM memory arrays.

0010 H000 0000 000a bbbb bbbb oooo oooo Read H (high or low) byte o from Program memory at word address a:b.

0100 H000 0000 000a bbbb bbbb iiii iiii Write H (high or low) byte i to Program memory at word address a:b.

1010 0000 0000 0000 00bb bbbb oooo oooo Read data o from EEPROM memory at address b.

Read EEPROM

Memory

Write EEPROM

Memory

1100 0000 0000 0000 00bb bbbb iiii iiii Write data i to EEPROM memory at address b.

Write Lock Bits 1010 1100 1111 1 211 xxxx xxxx xxxx xxxx Write Lock bits. Set bits 1,2=’0’ to program Lock bits.

0011 0000 xxxx xxxx xxxx xxbb oooo oooo Read Signature byte o from address b.

(1)

Read Signature

Byte

Note: a = address high bits

b = address low bits

H = 0 - Low byte, 1- High byte

o = data out

i = data in x = don’t care

1 = Lock Bit 1

2 = Lock Bit 2

Note: 1. The Signature bytes are not readable in Lock mode 3, i.e. both Lock bits programmed.

44

AT90S1200

AT90S1200

Serial Programming Characteristics

Figure 36. Serial Programming Timing

MOSI t

OVSH

SCK t

SHOX t

SLSH t

SHSL

MISO t

SLIV

Table 20. Serial Programming Characteristics, T

A

= -40

°

C to 85

°

C, V

CC

=2.7 - 6.0V (Unless otherwise noted)

Symbol Parameter Min Typ Max

1/t

CLCL t

CLCL

1/t

CLCL t

CLCL t

SHSL t

SLSH t

OVSH t

SHOX t

SLIV

Oscillator Frequency (V

CC

= 2.7 - 4.0V)

Oscillator Period (V

CC

= 2.7 - 4.0V)

Oscillator Frequency (V

CC

= 4.0 - 6.0V)

Oscillator Period (V

CC

= 4.0 - 6.0V)

SCK Pulse Width High

SCK Pulse Width Low

MOSI Setup to SCK High

MOSI Hold after SCK High

SCK Low to MISO Valid

0

250

0

83.3

4 t

CLCL t

CLCL

1.25 t

CLCL

2.5 t

CLCL

10 16

4

12

32 ns ns ns ns

Units

MHz ns

MHz ns ns

Table 21. Minimum wait delay after the Chip Erase instruction

Symbol t

WD_ERASE

3.2V

18 ms

3.6V

14 ms

4.0V

12 ms

Table 22. Minimum wait delay after writing a Flash or EEPROM location

Symbol t

WD_PROG

3.2V

9 ms

3.6V

7 ms

4.0V

6 ms

5.0V

8 ms

5.0V

4 ms

45

Electrical Characteristics

Absolute Maximum Ratings*

Operating Temperature.................................. -55

°

C to +125

°

C

Storage Temperature ..................................... -65°C to +150°C

Voltage on any Pin except RESET with respect to Ground ................................-1.0V to V

CC

+0.5V

Voltage on RESET with respect to Ground......-1.0V to +13.0V

Maximum Operating Voltage ............................................ 6.6V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V

CC

and GND Pins................................ 200.0 mA

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

46

AT90S1200

AT90S1200

DC Characteristics

T

A

= -40

°

C to 85

°

C, V

CC

= 2.7V to 6.0V (unless otherwise noted)

Symbol Parameter Condition

V

IL

V

IL1

V

IH

V

IH1

V

IH2

V

OL

V

OH

I

IL

Input Low Voltage

Input Low Voltage

Input High Voltage

Input High Voltage

Input High Voltage

Output Low Voltage

(3)

(Ports B,D)

Output High Voltage

(4)

(Ports B,D)

Input Leakage

Current I/O pin

(Except XTAL1)

(XTAL1)

(Except XTAL1, RESET)

(XTAL1)

(RESET)

I

OL

= 20 mA, V

CC

I

OL

= 10 mA, V

CC

= 5V

= 3V

I

OH

= -3 mA, V

CC

= 5V

I

OH

= -1.5 mA, V

CC

= 3V

Vcc = 6V, pin low

(Absolute value)

Min

-0.5

-0.5

0.6 V

CC

(2)

0.7 V

CC

(2)

0.85 V

CC

(2)

4.3

2.3

Typ Max

0.3 V

CC

(1)

0.1

(1)

V

CC

+ 0.5

V

CC

+ 0.5

V

CC

+ 0.5

0.6

0.5

8.0

µA

I

IH

Input Leakage

Current I/O pin

Vcc = 6V, pin high

(Absolute value)

980 nA

RRST

R

I/O

Reset Pull-up Resistor

I/O Pin Pull-Up Resistor

100

35

500

120 k k

Ω

Ω

Active Mode, V

CC

= 3V,

4MHz

3.0

mA

I

CC

Power Supply Current

I

CC

Power Down Mode (5)

Idle Mode V

CC

= 3V, 4MHz

WDT enabled, V

CC

= 3V

WDT disabled, V

CC

= 3V

9

<1

1.0

15.0

2.0

mA

µA

µA

V

ACIO

Analog Comparator

Input Offset Voltage

V

CC

= 5V 40 mV

I

ACLK

Analog Comparator

Input Leakage Current

V

CC

= 5V

V in

= V

CC

/2

-50 50 nA t

ACPD

Analog Comparator

Propagation Delay

V

CC

= 2.7V

V

CC

= 4.0V

750

500 ns

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:

1] The sum of all I

OL

, for all ports, should not exceed 200 mA

2] The sum of all II

OL

, for port D0-D5 and XTAL2 should not exceed 100 mA.

3] The sum of all I

OL

, for ports B0-B7 and D6 should not exceed 100 mA.

If I

OL

exceeds the test condition, V

OL

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

4. Although each I/O port can source more than the test conditions (3mA at Vcc = 5V, 1.5mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:

1] The sum of all I

OH

, for all ports, should not exceed 200 mA

2] The sum of all I

OH

3] The sum of all I

OH

, for port D0-D5 and XTAL2 should not exceed 100 mA.

, for ports B0-B7 and D6 should not exceed 100 mA.

If I

OH

exceeds the test condition, V

OH

may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.

5. Minimum V

CC

for Power Down is 2V.

V

V

V

V

V

V

Units

V

V

V

47

External Clock Drive Waveforms

Figure 37. Ecternal Clock Drive

VIL1

VIH1

External Clock Drive

Symbol

1/t

CLCL t

CLCL t

CHCX t

CLCX t

CLCH t

CHCL

Parameter

Oscillator Frequency

Clock Period

High Time

Low Time

Rise Time

Fall Time

V

CC

= 2.7V to 4.0V

Min Max

4 0

250

100

100

1.6

1.6

V

CC

= 4.0V to 6.0V

Min Max

12 0

83.3

33.3

33.3

0.5

0.5

Units

MHz ns ns ns

µ s

µ s

Typical Characteristics

The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail to rail output is used as clock source.

The power consumption in power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C

L

* V

CC

*f where C

L

= load capacitance,

V

CC

= operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power Down mode with Watchdog timer enabled and Power Down mode with Watchdog timer disabled represents the differential current drawn by the watchdog timer.

48

AT90S1200

AT90S1200

Figure 38. Active Supply Current vs. Frequency

ACTIVE SUPPLY CURRENT vs. FREQUENCY

18

16

14

12

10

8

2

0

6

4

0 1

V cc

= 2.7V

V cc

= 6V

V cc

= 5.5V

V cc

= 5V

V cc

= 4.5V

V cc

= 4V

V cc

= 3.6V

V cc

= 3.3V

V cc

= 3.0V

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Frequency (MHz)

Figure 39. Active Supply Current vs. V

CC

ACTIVE SUPPLY CURRENT vs. V

cc

FREQUENCY = 4 MHz

10

9

6

5

8

7

4

3

2

1

0

2 2.5

3 3.5

4

V cc

(V)

4.5

5

T = -40 ˚ C

T = 25 ˚ C

5.5

T = 85 ˚ C

6

49

Figure 40. Active Supply Current vs. V

CC

, Device Clocked by Internal Oscillator

ACTIVE SUPPLY CURRENT vs. V

cc

DEVICE CLOCKED BY INTERNAL RC OSCILLATOR

7

6

5

4

3

2

1

0

2 2.5

3 3.5

4

V cc

(V)

4.5

5

T = 25 ˚ C

5.5

T = 85 ˚ C

6

Figure 41. Idle Supply Current vs. Frequency

IDLE SUPPLY CURRENT vs. FREQUENCY

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Frequency (MHz)

V cc

= 6V

V cc

= 5.5V

V cc

= 2.7V

V cc

= 5V

V cc

= 4.5V

V cc

= 4V

V cc

= 3.6V

V cc

= 3.3V

V cc

= 3.0V

50

AT90S1200

AT90S1200

Figure 42. Idle Supply Current vs. V

CC

IDLE SUPPLY CURRENT vs. V

cc

FREQUENCY = 4 MHz

2.5

2

1.5

1

0.5

0

2

T = -40 ˚ C

T = 25 ˚ C

T = 85 ˚ C

2.5

3 3.5

4

V cc

(V)

4.5

5 5.5

6

Figure 43. Idle Supply Current vs. V

CC

, Device Clocked by Internal Oscillator

IDLE SUPPLY CURRENT vs. V

cc

DEVICE CLOCKED BY INTERNAL RC OSCILLATOR

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

2 2.5

3 3.5

4

V cc

(V)

4.5

5 5.5

T = 25 ˚ C

T = 85 ˚ C

6

51

Figure 44. Power Down Supply Current vs. V

CC

, Watchdog Timer Disabled

POWER DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER DISABLED

0.8

0.6

0.4

0.2

0

2

1.8

1.6

1.4

1.2

1

2.5

3 4.5

5 3.5

V cc

(V)

4 5.5

T = 85 ˚ C

T = 70 ˚ C

6

T = 45 ˚ C

T = 25 ˚ C

Figure 45. Power Down Supply Current vs. V

CC

, Watchdog Timer Enabled

POWER DOWN SUPPLY CURRENT vs. V

cc

WATCHDOG TIMER ENABLED

140

120

100

80

60

40

20

0

2 2.5

3 3.5

4

V cc

(V)

4.5

5 5.5

T = 25 ˚ C

T = 85 ˚ C

6

52

AT90S1200

AT90S1200

Figure 46. Internal RC Oscillator Frequency vs. V

CC

INTERNAL RC OSCILLATOR FREQUENCY vs. V

cc

1600

1400

1200

1000

800

600

400

200

0

2 2.5

3 3.5

4 4.5

5

T = 25 ˚ C

5.5

T = 85 ˚ C

6

Figure 47. Analog Comparator Current vs. V

CC

ANALOG COMPARATOR CURRENT vs. V

cc

1.2

1

0.8

T = -40 ˚ C

0.6

0.4

0.2

0

2 2.5

3 4.5

5 5.5

T = 85 ˚ C

6

T = 25 ˚ C

3.5

V cc

(V)

4

53

Analog comparator offset voltage is measured as absolute offset

Figure 48. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

18

16

14

12

10

4

2

8

6

0

0 0.5

1 1.5

2 2.5

3

Common Mode Voltage (V)

3.5

T = 25 ˚ C

4

T = 85 ˚ C

4.5

5

Figure 49. Analog Comparator Offset Voltage vs. Common Mode Voltage

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

10

T = 25 ˚ C

8

6

T = 85 ˚ C

4

2

0

0 0.5

1 1.5

Common Mode Voltage (V)

2 2.5

3

54

AT90S1200

AT90S1200

Figure 50. Analog Comparator Input Leakage Current

ANALOG COMPARATOR INPUT LEAKAGE CURRENT

V = 6V

CC

T = 25 ˚ C

40

30

60

50

20

10

0

-10

0 0.5

1 1.5

2 2.5

3 3.5

4 4.5

5 5.5

6 6.5

7

Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 51. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

120

T = 25 ˚ C

100

T = 85 ˚ C

80

60

40

20

0

0 0.5

1 1.5

2 2.5

3 3.5

4 4.5

5

55

Figure 52. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

30

25

20

T = 25 ˚ C

T = 85 ˚ C

15

10

5

0

0 0.5

1 1.5

2 2.5

3

Figure 53. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

50

40

30

20

70

60

10

0

0 0.5

1 1.5

T = 25 ˚ C

2

T = 85 ˚ C

2.5

3

56

AT90S1200

AT90S1200

Figure 54. I/O Pin Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

T = 25 ˚ C

20

18

16

14

12

10

8

6

4

2

0

0 0.5

1

T = 85 ˚ C

1.5

2 2.5

3 3.5

4 4.5

5

Figure 55. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

25

T = 25 ˚ C

20

T = 85 ˚ C

15

10

5

0

0 0.5

1 1.5

2

57

Figure 56. I/O Pin source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

6

T = 25 ˚ C

5

T = 85 ˚ C

4

3

2

1

0

0 0.5

1 1.5

2 2.5

3

Input threshold is measured at the center point of the hysteresis

Figure 57. I/O Pin Input Threshold Voltage vs. V

CC

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

cc

T = 25 ˚ C

2.5

2

1.5

1

0.5

0

2.7

4.0

5.0

58

AT90S1200

Figure 58. I/O Pin Input Hysteresis vs. V

CC

I/O PIN INPUT HYSTERESIS vs. V

cc

T = 25 ˚ C

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

2.7

4.0

AT90S1200

5.0

59

AT90S1200 Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

Reserved

WDTCR

Reserved

Reserved

EEAR

EEDR

EECR

Reserved

Reserved

Reserved

PORTB

DDRB

PINB

Reserved

Reserved

Reserved

PORTD

DDRD

PIND

Reserved

Reserved

Reserved

ACSR

Reserved

Reserved

TCNT0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

SREG

Reserved

Reserved

Reserved

GIMSK

Reserved

TIMSK

TIFR

Reserved

Reserved

MCUCR

Reserved

TCCR0

$1A

$19

$18

$17

$16

$15

$14

$13

$12

$22

$21

$20

$1F

$1E

$1D

$1C

$1B

$11

$10

$0F

...

$09

$08

…

$00

$29

$28

$27

$26

$25

$24

$23

$32

$31

$30

$2F

$2E

$2D

$2C

$2B

$2A

$3F

$3E

$3D

$3C

$3B

$3A

$39

$38

$37

$36

$35

$34

$33

I

-

-

-

-

-

-

-

-

PORTB

DDB7

PINB7

-

-

-

ACD

T

INT0

-

-

-

-

-

-

PORTB

DDB6

PINB6

PORTD

DDD6

PIND6

-

H

-

-

-

SE

-

-

-

PORTB

DDB5

PINB5

PORTD

DDD5

PIND5

ACO

S

-

-

-

SM

-

PORTB

DDB4

PINB4

PORTD

DDD4

PIND4

ACI

V

-

-

-

-

-

Timer/Counter0 (8 Bit)

WDE

PORTB

DDB3

PINB3

PORTD

DDD3

PIND3

ACIE

N

-

-

-

-

CS02

WDP2

EEPROM Address Register

EEPROM Data Register

-

PORTB

DDB2

PINB2

PORTD

DDD2

PIND2

-

Z

-

TOIE0

TOV0

ISC01

CS01

WDP1

EEWE

PORTB

DDB1

PINB1

PORTD

DDD1

PIND1

ACIS1

C

-

-

-

ISC00

CS00

WDP0

EERE

PORTB

DDB0

PINB0

PORTD

DDD0

PIND0

ACIS0

12

16

17

17

18

21

21

22

23

24

24

27

27

27

31

31

31

25

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

60

AT90S1200

AT90S1200

Instruction Set Summary

Mnemonics Operands Description

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

CPSE

CP

CPC

CPI

SBRC

SBRS

SBIC

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

SBR

CBR

INC

DEC

TST

CLR

SER

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers

ADC

SUB

SUBI

Rd, Rr

Rd, Rr

Rd, K

Add with Carry two Registers

Subtract two Registers

Subtract Constant from Register

SBC

SBCI

AND

ANDI

OR

ORI

EOR

COM

NEG

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Rd

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Rd,K

Rd,K

Rd

Rd

Rd

Rd

Rd

BRANCH INSTRUCTIONS

RJMP k

RCALL

RET k

RETI

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Rd,Rr

Rd,Rr

Rd,Rr

Rd,K

Rr, b

Rr, b

P, b

k

k

k

P, b s, k s, k

k

k

Relative Jump

Relative Subroutine Call

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

Compare with Carry

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

k

k

k

k

k

k

k

k

k

k

k

k

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

BRID k Branch if Interrupt Disabled

DATA TRANSFER INSTRUCTIONS

LD

ST

Rd,Z

Z,Rr

Load Register Indirect

Store Register Indirect

MOV

LDI

IN

OUT

Rd, Rr

Rd, K

Rd, P

P, Rr

Move Between Registers

Load Immediate

In Port

Out Port

Operation Flags

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rd ← Rd • Rr

Z,C,N,V,H

Z,C,N,V,H

Z,C,N,V,H

Z,C,N,V,H

Z,C,N,V,H

Z,C,N,V,H

Rd ← Rd • K

Rd ← Rd v Rr

Rd ← Rd v K

Rd ← Rd

⊕

Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Z,N,V

Z,N,V

Z,N,V

Z,N,V

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd ← Rd • (FFh - K)

Rd ← Rd + 1

Z,N,V

Z,N,V

Rd ← Rd - 1 Z,N,V

Rd ← Rd • Rd Z,N,V

Rd ← Rd

⊕

Rd Z,N,V

Rd ← $FF None

PC ← PC + k + 1

PC ← PC + k + 1

PC ← STACK

PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

Rd - Rr - C

Rd - K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC ← PC + k + 1 if (SREG(s) = 0) then PC ← PC + k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if (I = 1) then PC ← PC + k + 1 if (I = 0) then PC ← PC + k + 1

Rd ← (Z)

(Z) ← Rr

Rd ← Rr

Rd ← K

Rd ← P

P ← Rr

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

I

None

None

Z, N,V,C,H

Z, N,V,C,H

Z, N,V,C,H

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

#Clocks

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

4

4

2

3

1 / 2

1

1

1 / 2

1

1

1

1

2

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

61

Instruction Set Summary (Continued)

Mnemonics Operands Description

SEN

CLN

SEZ

CLZ

SEI

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register

CBI P,b Clear Bit in I/O Register

LSL

LSR

ROL

ROR

ASR

Rd

Rd

Rd

Rd

Rd

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

Rd s s

Rr, b

Rd, b

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow

Clear Twos Complement Overflow

Set T in SREG

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

No Operation

Sleep

Watch Dog Reset

Operation Flags

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0) ← C,Rd(n+1)

←

Rd(n),C ← Rd(7)

None

None

Z,C,N,V

Z,C,N,V

Rd(7) ← C,Rd(n)

←

Rd(n+1),C ← Rd(0)

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0) ← Rd(7..4),Rd(7..4) ← Rd(3..0)

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

Z,C,N,V

Z,C,N,V

Z,C,N,V

None

SREG(s)

SREG(s)

T

None

C ← 0

N ← 1

N ← 0

Z ← 1

Z ← 0

I ← 1

I ← 0

I

C

C

N

N

Z

Z

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

I

S

S

V

V

T

T ← 0 T

H ← 1 H

H ← 0 H

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

None

None

None

#Clocks

1

3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

2

62

AT90S1200

Ordering Information

(1)

Speed (MHz)

4

Power Supply

2.7 - 6.0V

Ordering Code

AT90S1200-4PC

AT90S1200-4SC

AT90S1200-4YC

AT90S1200-4PI

AT90S1200-4SI

AT90S1200-4YI

12 4.0 - 6.0V

AT90S1200-12PC

AT90S1200-12SC

AT90S1200-12YC

AT90S1200-12PI

AT90S1200-12SI

AT90S1200-12YI

Note: 1. Order AT90S1200A-XXX for devices with the RCEN fuse programmed.

20P3

20S

20Y

20P3

20S

20Y

Package

20P3

20S

20Y

20P3

20S

20Y

AT90S1200

Operation Range

Commercial

(0

°

C to 70

°

C)

Industrial

(-40

°

C to 85

°

C)

Commercial

(0

°

C to 70

°

C)

Industrial

(-40

°

C to 85

°

C)

20P3

20S

20Y

Package Type

20-lead, 0.300" Wide Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC)

20-lead, 5.3 mm Wide, Plastic Shrink Small Outline Package (SSOP)

63

Packaging Information

20P3, 20-lead, 0.300" Wide,

Plastic Dual Inline Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 BA

1.060(26.9)

.980(24.9)

PIN

1

.280(7.11)

.240(6.10)

.210(5.33)

MAX

SEATING

PLANE

.150(3.81)

.115(2.92)

.110(2.79)

.090(2.29)

.900(22.86) REF

.070(1.78)

.045(1.13)

.015(.381) MIN

.022(.559)

.014(.356)

.325(8.26)

.300(7.62)

0

15

REF

.014(.356)

.008(.203)

.090(2.29)

MAX

.005(.127)

MIN

.430(10.92) MAX

20Y, 20-lead, 5.3 mm Wide,

Plastic Shrink Small Outline Package (SSOP)

Dimensions in Millimeters and (Inches)

0.38 (.015)

0.25 (.010)

5.38 (.212)

5.20 (.205)

7.90 (.311)

7.65 (.301)

PIN 1 ID

64

7.33 (.289)

7.07 (.278)

0.65 (.0256) BSC

2.67 (.105)

2.34 (.092)

0.21 (.008)

0.05 (.002)

0.20 (.008)

0.09 (.004)

0

8

REF

0.95 (.037)

0.63 (.025)

AT90S1200

20S, 20-lead, 0.300" Wide,

Plastic Gull-Wing Small Outline (SOIC)

Dimensions in Inches and (Millimeters)

0.020 (0.508)

0.013 (0.330)

0.299 (7.60)

0.291 (7.39)

0.420 (10.7)

0.393 (9.98)

PIN 1

.050 (1.27) BSC

0.513 (13.0)

0.497 (12.6)

0

8

REF

0.035 (0.889)

0.015 (0.381)

0.012 (0.305)

0.003 (0.076)

0.013 (0.330)

0.009 (0.229)

0.105 (2.67)

0.092 (2.34)

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© Atmel Corporation 1999.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems.

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are registered trademarks and trademarks of Atmel Corporation.

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0838E–04/99/xM