Nuvoton N3290x Data Sheet

N3290x

Data Sheet

ARM926-based Media Processor

Nuvoton Technology Corp.

http://www.nuvoton.com/

1 Release Date: May. 2013

Rev. A5.1

N3290 X DATASHEET

The information in this document is subject to change without notice.

The Nuvoton Technology Corp. shall not be liable for technical or editorial errors or omissions contained herein; nor for incidental or consequential damages resulting from the furnishing, performance, or use of this material.

This documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine readable form without prior consent, in writing, from the


Nuvoton Technology Corp. All rights reserved.


http://www.nuvoton.com/


Rev. A5.1


N3290x

ARM926-based Media Processor

Table of Contents

1.

GENERAL DESCRIPTION ................................................................................................................................... 5

1.1

Applications .............................................................................................................................................. 5

2.

FEATURES........................................................................................................................................................... 6

3.

PIN DIAGRAM .................................................................................................................................................... 12

3.1

N32901U1DN (LQFP-128) ..................................................................................................................... 12

3.2

N32901U2DN (LQFP-128) ..................................................................................................................... 13

3.3

N32903U1DN (LQFP-128) ..................................................................................................................... 14

3.4

N32905U1DN (LQFP-128) ..................................................................................................................... 15

3.5

N32905U2DN (LQFP-128) ..................................................................................................................... 16

3.6

N32903R1DN (TQFP-64) ....................................................................................................................... 17

3.7

N32901R1DN (LQFP-64) ....................................................................................................................... 18

4.

PIN DESCRIPTION ............................................................................................................................................ 19

4.1

Pin Description & Cross Reference ........................................................................................................ 19

4.2

Pin Type Description .............................................................................................................................. 28

5.

ELECTRICAL SPECIFICATION ......................................................................................................................... 29

5.1

Absolute Maximum Rating ..................................................................................................................... 29

5.2

DC Characteristics (Normal I/O) ............................................................................................................ 29

5.3

Audio DAC Characteristics ..................................................................................................................... 30

5.4

ADC Characteristics .................................................................................................................................. 31

5.5

AC Characteristics (Digital Interface) ......................................................................................................... 31

5.6

Power-on Sequence ............................................................................................................................... 40

5.7

Thermal characteristics of LQFP-128 Package ..................................................................................... 40

6.

ORDERING INFORMATION .............................................................................................................................. 41

6.1

Part Number Definition ........................................................................................................................... 41

6.2

Difference between N32901U1DN, N32903U1DN, N32905U1DN and N32905U2DN .......................... 41

7.

PACKAGE OUTLINE .......................................................................................................................................... 42




Rev. A5.1


7.1

LQFP-128 (14X14X1.4mm body, 0.4mm pitch) ..................................................................................... 42

7.2

TQFP-64 (10X10X1.0mm body, 0.5mm pitch) ....................................................................................... 43

7.3

LQFP-64 (10X10X1.4mm body, 0.5mm pitch) ....................................................................................... 46

8.

REVISION HISTORY.......................................................................................................................................... 47




Rev. A5.1


1. GENERAL DESCRIPTION

The N3290xUxDN is built on the ARM926EJ-S CPU core and integrated with JPEG codec, CMOS sensor interface,

32-channel SPU (Sound Processing Unit), ADC, DAC, for meeting various kinds of application needs while saving the

BOM cost. The combination of ARM926 @ 200MHz, synchronous DRAM, 2D BitBLT accelerator, CMOS image sensor interface, LCD panel interface, USB 1.1 Host & USB2.0 HS Device makes the N3290xUxDN the best choice for LCD ELA devices.

Maximum resolution for the N3290xUxDN is XVGA (1,024x768) @ TFT LCD panel. The 2D BitBLT accelerator accelerates the graphic compution to make the rendering smooth and off-load CPU to save power consumption.

The N3290xUxDN is well-positioned in terms of cost/performance for the applications which bitmap graphics is extensively used or CMOS Image Sensor (CIS) interface is required.

The N3290xUxDN is for application under Linux OS and leverage the driver availability of emerging functionalities like

Wi-Fi, browser, etc. On the other hand, the open source code environment also give the product development more flexible.

To meet the different requirement of the overall system BOM cost, the different size of DRAM is stacked with N3290x main SoC into one package, that is, multi-chip package (MCP). The N32901U1DN is particularly designed with the

128-pin LQFP package and the 1Mbitx16 SDRAM is stacked inside the MCP. The N32903U1DN is particularly designed with the 128-pin LQFP package and the 4Mbitx16 SDRAM is stacked inside the MCP. The 16Mbitx16

SDRAM is stacked inside the N32905UxDN MCP to ensure higher performance and minimize the system design efforts, like EMI & noise coupling. Total BOM cost could be reduced by employing 2-layer PCB along with the elimination of damping resistors, EMI prevention components, etc. Advantages including, but not limited to, less PCB space, shorter lead time, and higher / reliable production yield.

1.1 Applications

 ELA (Educational Learning Aid)

 HMI

 Security

 Home Appliance

 Advertisement




Rev. A5.1


2. FEATURES

 CPU

 ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache

 Frequency up to [email protected] core power operation voltage

 JTAG interface supported for development and debugging

 Internal SRAM & ROM

 8KB internal SRAM and 16KB IBR internal booting ROM supported

 IBR booting messages displayed by UART console for debugging supported

 Different system booting modes supported:

 Memory card

 SD card

 SD-to-NAND flash bridge

 Raw NAND Flash

 SPI Flash

 USB

 EDMA (Enhanced DMA)

 Totally 5 DMA channels supported

 4 peripheral DMA channels for transfer between memory and on-chip peripherals,











 such as ADC, UART and SPI

 One dedicated channel for memory-to-memory transfer

Byte, half-word and word data width types supported

Single and burst transfer modes supported

Block transfer supported in memory-to-memory transfer channel

Color format transformation supported in memory-to-memory transfer channel

 Source color format could be RGB555, RGB565 and YCbCr422

 Destination color format could be RGB555, RGB565 and YCbCr422

Auto reload supported for continuous data transfer

Interrupt generation supported in the half-of-transfer or end-of-transfer

 Capture (CMOS Sensor I/F)





CCIR601 & CCIR656 interfaces supported for connection to CMOS image sensor

Resolution up to 2M pixel for Still Image Capture, 640x480 (VGA) resolution for MJPEG











Video Streaming

YUV422 and RGB565 color format supported for data-in from CMOS sensor

YUV422, RGB565, RGB555 and Y-only color format supported for data storing to system memory

Planar and packet data formats supported for data storing to system memory

Image cropping supported with the cropping window up to 4096x2048

Image scaling-down supported

 Vertical and horizontal scaling-down for preview mode supported



 The scaling factor is N/M

 Two pairs of configurable 8-bit N and 8-bit M for vertical and horizontal scalingdown

 The value of N has to equal to or less than M

 Frame rate control supported

Combines two interlace fields to a single frame supported for data in from TV-decoder

 JPEG Codec

 Baseline Sequential mode JPEG codec function compliant with ISO/IEC 10918-1




Rev. A5.1

N3290 X DATASHEET international JPEG standard supported.

 Planar Format

 Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format image

 Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only) format image

 Support to decode YCbCr 4:2:2 transpose format

 Support arbitrary width and height image encode and decode

 Support three programmable quantization-tables

 Support standard default Huffman-table and programmable Huffman-table for decode

 Support arbitrarily 1X~8X image up-scaling function for encode mode

 Support down-scaling function for encode and decode modes

 Support specified window decode mode

 Support quantization-table adjustment for bit-rate and quality control in encode mode

 Support rotate function in encode mode

 Packet Format

 Support to encode interleaved YUYV format input image, output bitstream 4:2:2 and

4:2:0 format

 Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image

 Support decoded output image RGB555, RGB565 and RGB888 formats.

 The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards

 Support arbitrary width and height image encode and decode

 Support three programmable quantization-tables

 Support standard default Huffman-table and programmable Huffman-table for decode

 Support arbitrarily 1X~8X image up-scaling function for encode mode

 Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for decode mode

 Support specified window decode mode

 Support quantization-table adjustment for bit-rate and quality control in encode mode

 2D Accelerator

 BitBLT operation

 2x2 transform matrix with effects:

 Scale

 Translate

 Rotate

 Shear

 Alpha blending and color transformation supported

 Source format for operations: supported color format of source bitmap

 Fill

 Rectangle Fill with single color – ARGB8888

 Fill with blending effect supported

 Supported color formats

 Source

 16 bits/pixel – RGB565

 32 bits/pixel – ARGB8888

 1 bit/pixel, 2 bits/pixel, 4 bits/pixel, 8 bits/pixel with RGB color palette

 Destination

 16 bits/pixel – RGB565

 32 bits/pixel – ARGB8888




Rev. A5.1


 VPOST

 8/16/18/24-bit SYNC type and 8/9/16/18/24-bit MPU type TFT LCD supported

 Color format supported:

 YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data in

 YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data out

 XGA (1024x768), SVGA (800x600), WVGA (800x480), D1 (720X480), VGA (640x480),

WQVGA (480x272), QVGA (320x240) and HVGA (640x240) resolution supported

 The maximum resolution is up to D1 (720X480) for TV output

 The maximum resolution is up to 1024X768 for TFT LCD panel for still image displaying

 The maximum resolution is up to 480x272 for TFT LCD panel for MJPEG video displaying up to 25fps.

 Display scaler – to fit different size of LCD panels

 Horizontal: At most 4.0x scale

 Vertical: At most 3.0x scale

 For SYNC type LCD:

 For 8-bit bus

 CCIR601 YCbCr422 packet mode (NTSC/PAL) supported

 CCIR601 RGB Dummy mode (NTSC/PAL) supported

 CCIR656 interface supported

 RGB Through mode supported

 For 16/18/24-bit bus

 Parallel pixel data output mode (1-pixel/1-clock)

 NTSC/PAL interlace & non-interlace output supported

 Color format transform supported:

 Color format transform between YCbCr422 and RGB565

 Color format transform from YCbCr422 to RGB888

 TV encoder supported

 Dual screen, outputs to TV and LCD simultaneously with same content, supported

 LCD panel should be 320X240 MPU-type, or 8-bit SYNC-type LCD panel with TV timing

 Notch filter for NTSC supported to remove the rainbow color effect

 Support OSD function to overlap system information like battery life, brightness tuning, volume tuning or muting, etc.

 Frame Switch Controller

 Frame relation controlled between VPOST and Capture supported

 2 modes supported to switch Frame Buffer Base

 Frame Ratio Mode (16 selectable ratio)

 Frame sync mode

 Double/triple buffers supported

 SPU (Sound Processing Unit)

 32 stereo channels supported

 PCM8/PCM16/4-bit MDPCM/TONE source format supported

 7-bit volume control supported for each of 32 channels

 5-bit pan control supported for each L/R of 32 channels

 10-band equalizer supported

 Special code supported for loop playing and event detection




Rev. A5.1


 Audio DAC

 16-bit stereo DAC supported with headphone driver output

 H/W volume control supported

 I2S Controller

 I2S interface supported to connect external audio codec

 16/18/20/24-bit data format supported

 Storage Interface Controller

 Interface to NAND Flash:

 8-bit data bus width supported

 SLC and MLC type NAND Flash supported

 512B, 2KB, 4KB, and 8KB page size NAND Flash supported

 ECC4, ECC8, ECC12 and ECC15 algorithm supported for ECC generation, error detection and error correction

 PBA-NAND flash supported

 Interface to SD/MMC/SDIO/SDHC/micro-SD cards supported

 SD-to-NAND flash bridge supported

 DMA function supported to accelerate the data transfer between system memory and

NAND Flash or SD/MMC/SDIO/SDHC/micro-SD

 USB Device Controller

 USB2.0 HS (High-Speed) x 1 port

 6 configurable endpoints supported

 Control, Bulk, Interrupt and Isochronous transfers supported

 Suspend and remote wakeup supported

 USB Host Controller

 USB1.1 Host one H/W Engine, two pin locations.

 Fully compliant with USB Revision 1.1 specification

 Open Host Controller Interface (OHCI) Revision 1.0 compatible

 Full-speed (12Mbps) and low-speed (1.5Mbps) USB devices supported

 Control, Bulk, Interrupt and Isochronous transfers supported

 Timer & Watch-Dog Timer

 Two 32-bit with 8-bit pre-scalar timers supported

 One programmable 24-bit Watch-Dog Timer supported

 PWM

 4 PWM channel outputs supported

 16-bit counter supported for each PWM channel

 Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM channels

 Two clock-dividers supported and each divider shared by two PWM channels

 Two Dead-Zone generators supported and each generator shared by two PWM channels

 Auto reloaded mode and one-shot pulse mode supported

 Capture function supported

 UART

 A high speed UART supported:

 Baud rate is up to 1M bps

 4 signals TX, RX, CTS and RTS supported




Rev. A5.1


 A normal UART supported:

 Baud rate is up to 115.2K bps

 2 signals TX and RX supported only

 SPI

 One SPI controller is supported

 Both master and slave mode are supported in SPI interface

 Two chip selection signals for two SPI devices

 I2C

 One I2C channel supported

 Compatible with Philips’s I 2 C standard and only master mode supported

 Multi-master operation supported

 Advanced Interrupt Controller

 Total 32 interrupt source supported

 Configurable interrupt type:

 Low-active level triggered interrupt

 High-active level triggered interrupt

 Low-active edge (falling edge) triggered interrupt

 High-active edge (rising edge) triggered interrupt

 Individual interrupt mask bit for each interrupt source

 8 different priority levels supported

 Daisy-chain priority mechanism supported for interrupts with same priority level

 Low priority interrupt automatic masking supported for interrupt nesting

 RTC

 Independent power plane supported

 32.768 KHz crystal oscillation circuit supported

 Time counter (second, minute, hour) and Calendar counter (day, month, year) supported

 Alarm supported (second, minute, hour, day, month and year)

 12/24-hour mode and Leap year supported

 Alarm to wake chip up from Standby mode or from Power-down mode supported

 Wake chip up from Power-down mode by input pin supported

 Power-off chip by register setting supported

 Power-on timeout is supported for low battery protection

 GPIO

 80 programmable general purpose I/Os supported and separated into 5 groups

 Individual configuration supported for each I/O signal

 Configurable interrupt control functions supported

 Configurable de-bounce circuit supported for interrupt function

 ADC

 Multi-channel, 10-bit ADC supported

 2 channels dedicated for 4-wire resistive touch sensor inputs

 2 channels dedicated for Audio ADC with Microphone pre-Amp & AGC

 3 channels reserved for various purposes, like LVD (Low Voltage Detection), keypad input, and light sensor

 Input voltage range from 0V ~ 3.3V supported




Rev. A5.1


 Maximum 25MHz input clock supported

 Maximum 400K/s conversion rate supported

 LVR (Low Voltage Reset) supported

 Power Management

 Advanced power management including Power Down, Deep Standby, CPU Standby, and

Normal Operating modes

 Normal Operating Mode

 Core power is 1.8V and chip is in normal operation

 CPU Standby Mode

 Core power is 1.8V and only ARM CPU clock is turned OFF

 Deep Standby Mode

 Core power is 1.8V and all IP clocks are turned OFF

 Power Down Mode

 Only the RTC power is ON. Other 3.3V and 1.8V power are OFF

 Software Support

 Development Tools

 Bootloader / Diagnostic Program / NAND Writer Program: ADS 1.2 or RVDS 2.x or 3.x

 Linux Kernel (2.6.17.14) / System Manager: GCC 4.2

 TurboWriter / Sync Tool: Microsoft VC 6.0

 NAND Flash File System

 FAT12, FAT16 and FAT32 with long filename are supported

 Hidden disk is supported

 RAM disk is supported

 S/W audio Library

 Decoders with ADPCM / MP3 / ACC / OGG / WMA format support

 32-polyphony Wavetable MIDI synthesizer

 Programmable sampling rate and target bit rate

 USB Driver

 MS (Mass Storage) Class

 HID (Human Interface Device) Class

 Operating Voltage

 I/O: 3.3V

 Core: 1.8V for 200MHz

 Package

 LQFP-128 (MCP, stacked with DDR @ 1.8V and SDR @ 1.8V)




Rev. A5.1


3. PIN DIAGRAM

3.1 N32901U1DN (LQFP-128)

GPB[1] /

GPB[0] /

SDDAT1[0]/

SDDAT1[1] /

UHL_DM1 /

UHL_DP1 /

GPB[14] /

GPB[13] /

LMVSYNC /

WDT_RST_ /

GPD[12]

GPD[13]

/

/

GPD[14]

GPD[15]

/

/

GPE[4] /

GPE[5] /

GPE[6] /

GPE[7] /

GPE[2] /

GPE[3] /

SPCLK

SCLKO

ISDA

ISCK

SPI0_CLK

SPI0_CS0_

SPI0_DI

SPI0_DO

SDDAT[2]

SDDAT[3]

SDCMD

SDCLK

SDDAT[0]

SDDAT[1]

XIN

XOUT

VDD18

MVSSQ

MVDDQ

MVSSQ

MVDDQ

MVDD

MVREF

UD_VDD18

UD_VSS

UD_DM

UD_DP

UD_VDD33

UD_REXT

MVDD

VSS

LVDATA[17]

1

10

20

30

LMVSYNC SPI

SVSYNC SFIELD URRXD URTXD VDD



90

80

70

MVSSQ

ADAC_HPOUT_L

ADAC_HPVSS33

MVDDQ

MVDDQ

MVSSQ

MVREF

MVSS

VDD18

UD_CDET

TRST_ / HUR_RTS / SPI0_CS1_/ GPD[4]

TDO / HUR_CTS / PWM3 / GPD[3]

TDI

TMS

TCK

RST_

/ HUR_RXD / PWM2

/ HUR_TXD / PWM1

/ SPI1_CS1_/ PWM0

/

/

/

GPD[2]

GPD[1]

GPD[0]

GPA[0]

GPA[1]

GPA[2]

GPA[3]

GPA[4]

/ SD_CD_

/ LMVSYNC

/ UHL_DP1

/ UHL_DM1

GPA[5] / SPI0_CS1_

GPA[6] SPI1_CS1_

VDD33

RTC_VDD

RTC_RPWR

RTC_RWAKE_

RTC_XIN

RTC_XOUT

ADC_AIN[3]

MVSS

/ / / / / / / / /

/ / / / / / / /

LHSYNC VDD


Rev. A5.1


3.2 N32901U2DN (LQFP-128)

GPB[1] /

GPB[0] /

SDDAT1[0]/

SDDAT1[1] /

GPB[14] /

GPB[13] /

UHL_DM1 /

UHL_DP1 /

LMVSYNC /

WDT_RST_ /

GPD[12]

GPD[13]

GPD[14]

GPD[15]

/

/

/

/

SPCLK

SCLKO

ISDA

ISCK

SPI0_CLK

SPI0_CS0_

SPI0_DI

SPI0_DO

SDDAT[2]

SDDAT[3]

GPE[4] /

GPE[5] /

GPE[6] /

GPE[7] /

GPE[2] /

GPE[3] /

SDCMD

SDCLK

SDDAT[0]

SDDAT[1]

XIN

XOUT

VDD18

MVSSQ

MVDDQ(3.3V)

MVSSQ

MVDDQ(3.3V)

MVDD(3.3V)

NC

UD_VDD18

UD_VSS

UD_DM

UD_DP

UD_VDD33

UD_REXT

MVDD

VSS

LVDATA[17]

1

10

20

30

LMVSYNC SPI

URRXD URTXD VDD



90

80

70

MVSSQ

ADAC_HPOUT_L

ADAC_HPVDD33

ADAC_HPVSS33

MVDDQ (3.3V)

MVDDQ (3.3V)

MVSSQ

NC

MVSS

VDD18

UD_CDET

TRST_

TDO / HUR_CTS / PWM3

TDI

/ HUR_RTS / SPI0_CS1_/ GPD[4]


/

/

GPD[3]

GPD[2]

TMS

TCK

RST_


/ SPI1_CS1_/ PWM0

/ GPD[1]

/ GPD[0]

GPA[0]

GPA[1]

GPA[2]

/ SD_CD_

/ LMVSYNC

GPA[3]

GPA[4]

/ UHL_DP1

/ UHL_DM1

GPA[5] / SPI0_CS1_

GPA[6] SPI1_CS1_

VDD33

RTC_VDD

RTC_RPWR

RTC_RWAKE_

RTC_XIN

RTC_XOUT

ADC_AIN[3]

MVSS

/ / / / / / / / /

/ / / / / / / /

LHSYNC VDD


Rev. A5.1


3.3 N32903U1DN (LQFP-128)

GPB[1] /

GPB[0] /

SDDAT1[0]/

SDDAT1[1] /

UHL_DM1 /

UHL_DP1 /

GPB[14] /

GPB[13] /

LMVSYNC /

WDT_RST_ /

GPD[12]

GPD[13]

/

/

GPD[14]

GPD[15]

/

/

GPE[4] /

GPE[5] /

GPE[6] /

GPE[7] /

GPE[2] /

GPE[3] /

SPCLK

SCLKO

ISDA

ISCK

SPI0_CLK

SPI0_CS0_

SPI0_DI

SPI0_DO

SDDAT[2]

SDDAT[3]

SDCMD

SDCLK

SDDAT[0]

SDDAT[1]

XIN

XOUT

VDD18

MVSSQ

MVDDQ

MVSSQ

MVDDQ

MVDD

MVREF

UD_VDD18

UD_VSS

UD_DM

UD_DP

UD_VDD33

UD_REXT

MVDD

VSS

LVDATA[17]

1

10

20

30

LMVSYNC SPI


90

80

70

MVSSQ

ADAC_HPOUT_L

ADAC_HPVSS33

MVDDQ

MVDDQ

MVSSQ

MVREF

MVSS

VDD18

UD_CDET

TRST_ / HUR_RTS / SPI0_CS1_/ GPD[4]

TDO / HUR_CTS / PWM3 / GPD[3]

TDI

TMS

TCK

RST_



/ SPI1_CS1_/ PWM0

/

/

/

GPD[2]

GPD[1]

GPD[0]

GPA[0]

GPA[1]

GPA[2]

/ SD_CD_

/ LMVSYNC

GPA[3]

GPA[4]

/ UHL_DP1

/ UHL_DM1

GPA[5] / SPI0_CS1_

/

VDD33

RTC_VDD

RTC_RPWR

RTC_RWAKE_

RTC_XIN

RTC_XOUT

ADC_AIN[3]

MVSS



/ / / / / / / / /

/ / / / / / / /

LHSYNC VDD


Rev. A5.1


3.4 N32905U1DN (LQFP-128)

GPB[1] /

GPB[0] /

SDDAT1[0]/

SDDAT1[1] /

UHL_DM1 /

UHL_DP1 /

GPB[14] /

GPB[13] /

LMVSYNC /

WDT_RST_ /

GPD[12]

GPD[13]

GPD[14]

GPD[15]

/

/

/

/

GPE[4] /

GPE[5] /

GPE[6] /

GPE[7] /

GPE[2] /

GPE[3] /

SPCLK

SCLKO

ISDA

ISCK

SPI0_CLK

SPI0_CS0_

SPI0_DI

SPI0_DO

SDDAT[2]

SDDAT[3]

SDCMD

SDCLK

SDDAT[0]

SDDAT[1]

XIN

XOUT

VDD18

MVSSQ

MVDDQ

MVSSQ

MVDDQ

MVDD

MVREF

UD_VDD18

UD_VSS

UD_DM

UD_DP

UD_VDD33

UD_REXT

MVDD

VSS

LVDATA[17]

1

10

20

30

LMVSYNC SPI


90

80

70

MVSSQ

ADAC_HPOUT_L

ADAC_HPVSS33

MVDDQ

MVDDQ

MVSSQ

MVREF

MVSS

VDD18

UD_CDET

TRST_


TDI


/ GPD[3]

/ GPD[2] / HUR_RXD / PWM2

TMS / HUR_TXD / PWM1

TCK / SPI1_CS1_/ PWM0

RST_

/

/

GPD[1]

GPD[0]

GPA[0]

GPA[1]

GPA[2]

GPA[3]

GPA[4]

/ SD_CD_

/ LMVSYNC

/ UHL_DP1

GPA[5]

/ UHL_DM1

/ SPI0_CS1_

VDD33

RTC_VDD

RTC_RPWR

RTC_RWAKE_

RTC_XIN

RTC_XOUT

ADC_AIN[3]

MVSS



/ / / / / / / / /

/ / / / / / / /

LHSYNC VDD


Rev. A5.1


3.5 N32905U2DN (LQFP-128)

GPB[1] /

GPB[0] /

SDDAT1[0]/

SDDAT1[1] /

UHL_DM1 /

UHL_DP1 /

GPB[14] /

GPB[13] /

LMVSYNC /

WDT_RST_ /

GPD[12]

GPD[13]

GPD[14]

GPD[15]

/

/

/

/

GPE[4] /

GPE[5] /

GPE[6] /

GPE[7] /

GPE[2] /

GPE[3] /

SPCLK

SCLKO

ISDA

ISCK

SPI0_CLK

SPI0_CS0_

SPI0_DI

SPI0_DO

SDDAT[2]

SDDAT[3]

SDCMD

SDCLK

SDDAT[0]

SDDAT[1]

XIN

XOUT

VDD18

MVSSQ

MVDDQ

MVSSQ

MVDDQ

MVDD

MVREF

UD_VDD18

UD_VSS

UD_DM

UD_DP

UD_VDD33

UD_REXT

MVDD

VSS

LVDATA[17]

1

10

20

30

LMVSYNC SPI

URRXD URTXD VDD

90

80

70

MVSSQ

ADAC_HPOUT_L

ADAC_HPVSS33

MVDDQ

MVDDQ

MVSSQ

MVREF

MVSS

VDD18

UD_CDET

TRST_


TDI


/ GPD[3]

/ GPD[2] / HUR_RXD / PWM2

TMS / HUR_TXD / PWM1

TCK / SPI1_CS1_/ PWM0

RST_

/

/

GPD[1]

GPD[0]

GPA[0]

GPA[1]

GPA[2]

GPA[3]

GPA[4]

/ SD_CD_

/ LMVSYNC

/ UHL_DP1

GPA[5]

/ UHL_DM1

/ SPI0_CS1_

VDD33

RTC_VDD

RTC_RPWR

RTC_RWAKE_

RTC_XIN

RTC_XOUT

ADC_AIN[3]

MVSS



/ / / / / / / / /

/ / / / / / / /

LHSYNC VDD


Rev. A5.1


3.6 N32903R1DN (TQFP-64)

/ GPB / GPB

GPD[13] / SPI0_CS0_

GPD[14] /

GPD[15] /

GPE[4] /

GPE[5] /

GPE[6] /

GPE[7] /

GPE[2] /

GPE[3] /

SPI0_DI

SPI0_DO

SDDAT[2]

SDDAT[3]

SDCMD

SDCLK

SDDAT[0]

SDDAT[1]

XIN

XOUT

MVREF

PLL_VDD18

UD_DM

UD_DP

UD_VDD33

1

5

10

15

45

40

35

ADAC_HPOUT_R

ADAC_HPOUT_L

ADAC_HPVDD33

ADAC_HPVSS33

MVDD18

MVREF

VDD18

UD_CDET

HUR_RXD / PWM2 / GPD[2]

HUR_TXD / PWM1 / GPD[1]

RST_

GPA[1] / SD_CD

GPA[3] / UHL_DP1

GPA[4] / UHL_DM1

GPA[5] / SPI0_CS1_

ADC_AIN[2]




Rev. A5.1


3.7 N32901R1DN (LQFP-64)

/ GPB / GPB

GPD[13] / SPI0_CS0_

GPD[14] /

GPD[15] /

GPE[4] /

SPI0_DI

SPI0_DO

SDDAT[2]

GPE[5] /

GPE[6] /

GPE[7] /

GPE[2] /

GPE[3] /

SDDAT[3]

SDCMD

SDCLK

SDDAT[0]

SDDAT[1]

XIN

XOUT

VSS

PLL_VDD18

UD_DM

UD_DP

UD_VDD33

1

5

10

15

45

40

35

ADAC_HPOUT_R

ADAC_HPOUT_L

ADAC_HPVDD33

ADAC_HPVSS33

MVDD33

VSS

VDD18

UD_CDET

HUR_RXD / PWM2 / GPD[2]

HUR_TXD / PWM1 / GPD[1]

RST_

GPA[1] / SD_CD

GPA[3] / UHL_DP1

GPA[4] / UHL_DM1

GPA[5] / SPI0_CS1_

ADC_AIN[2]




Rev. A5.1


4. PIN DESCRIPTION

4.1 Pin Description & Cross Reference

Pin Name

I/O

Type

Description

Clock & Reset

XIN

XOUT

RST_

I 27MHz/12MHz Crystal Input

O 27MHz/12MHz Crystal Output

IOSU System Reset, Input, Low Active

Watch-Dog Reset, Output, Low Active

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

PWM0

GPD[0]

TMS

HUR_TXD

PWM1

GPD[1]

TDI

HUR_RXD

PWM2

GPD[2]

TDO

HUR_CTS

JTAG Interface

TCK

SPI1_CS1_

PWM3

GPD[3]

TRST_

HUR_RTS

SPI0_CS1_

GPD[4]

IOD

IOU

IOU

JTAG Interface Test Clock, Input

SPI Port 1 Device Select 1, Output, Low

Active

PWM Channel 0

GPIO Port D Bit 0

JTAG Interface Test Mode Select, Input

High-Speed UART TX Data, Output

PWM Channel 1


●

●

JTAG Interface Test Data In, Input

High-Speed UART RX Data, Input

PWM Channel 2


●

IOU JTAG Interface Test Data Out, Output

High-Speed UART Clear-To-Send, Input,

Low Active

PWM Channel 3


IOU JTAG Interface Test Reset, Input, Low

Active

High-Speed UART Reset-To-Send, Output,

Low Active


Active


●

●



●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●


Rev. A5.1


Pin Name

I/O

Type

Description

NAND Interface

NCS0_ IOU NAND Interface Chip Select 0, Output, Low

Active

SD Port 2 Data Bit 1 SDDAT2[1]

GPE[8]

NCS1_

SDDAT2[0]

GPE[9]

NALE

GPIO Port E Bit 8

IOU NAND Interface Chip Select 1, Output, Low

Active

SD Port 2 Data Bit 0


GPE[10]

NCLE

IOU NAND Interface Address-Latch-Enable,

Output, High Active


IOU NAND Interface Command-Latch-Enable,

Output, High Active

GPIO Port E Bit 11 GPE[11]

NBUSY0_

SDDAT2[3]

GPD[5]

NBUSY1_

SDDAT2[2]

GPD[6]

NRE_

IOU NAND Interface Busy 0, Input, Low Active



IOU NAND Interface Busy 1, Input, Low Active



SDCLK2

GPD[7]

IOU NAND Interface Read Enable, Output, Low

Active

SD Port 2 Clock, Output


NWR_ IOU NAND Interface Write Enable, Output, Low

Active

SD Port 2 Command/Response SDCMD2

GPD[8]

ND[7:0]

CHIPCFG[7:0]


IOU NAND Interface Data Bit [7:0]

Chip Power-On Configuration Bit [7:0],

Input

Sensor/Video-In Interface

●

●

●

●

●

●

●

●

●



●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●


Rev. A5.1


Pin Name

I/O

Type

Description

SCLKO

UHL_DP1

SDDAT1[1]

GPB[0]

SPCLK

UHL_DM1

SDDAT1[0]

GPB[1]

SVSYNC

I2S_BCLK

SDCMD1

GPB[3]

SFIELD

I2S_WS

SDDAT1[3]

GPB[4]

SPDATA[0]

I2S_DOUT

SDDAT1[2]

GPB[5]

SPDATA[1]

I2S_DIN

GPB[6]

I2C Interface

ISCK

GPB[13]

ISDA

LMVSYNC

LFMARK

GPB[14]

IOU Clock to Sensor Module, Output

USB Host Like Interface, DP


GPIO Port B Bit 0

IOU Sensor Interface Pixel Clock, Input

USB Host Like Interface, DM



IOU Sensor Interface VSYNC, Input

I2S Interface Clock, Input

SD Port 1 Command/Response


IOU Sensor Interface Even/ODD Field Indicator,

Input

I2S Interface Word Select, Output



IOU Sensor Interface Data Bit 0, Input

I2S Interface Data Output



IOU Sensor Interface Data Bit 1, Input

I2S Interface Data Input


IOU I2C Interface Clock, Output


IOU I2C Interface Data

MPU Mode VSYNC, Output

Frame Mark, Input




●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●


Rev. A5.1


Pin Name

I/O

Type

Description

LCD/Display Interface

LPCLK

GPB[15]

IOU LCD Interface Pixel Clock, Output


LHSYNC

GPD[9]

IOU LCD Interface HSYNC, Output, High Active


LVSYNC

GPD[10]

LVDE

GPD[11]

LVDATA[0]

GPC[0]

LVDATA[1]

GPC[1]

IOU LCD Interface VSYNC, Output, High Active


IOU LCD Interface Data Enable, Output, High

Active


IOU LCD Interface Data Bit 0

GPIO Port C Bit 0

LVDATA[2]

GPC[2]

LVDATA[3]

GPC[3]

LVDATA[4]

GPC[4]

CHIPCFG[8]







LVDATA[5]

GPC[5]

CHIPCFG[9]

LVDATA[6]

GPC[6]

CHIPCFG[10]

LVDATA[7]

GPC[7]

LVDATA[8]

●

●

●

●

●

●

●

●



Chip Power-On Configuration Bit [8], Input



Chip Power-On Configuration Bit [9], Input



●

●

●

Chip Power-On Configuration Bit [10],

Input




●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

● ●

● ●

● ●

● ●

● ●

● ●

● ●

● ●

● ●

● ●

● ●

●

●

●

● ● ●




Rev. A5.1


Pin Name

I/O

Type

Description

SPDATA[3]

GPC[11]

LVDATA[12]

KPI_SI[4]

SPDATA[4]

GPC[12]

LVDATA[13]

KPI_SI[5]

SPDATA[5]

GPC[13]

LVDATA[14]

KPI_SI[6]

SPDATA[6]

GPC[14]

LVDATA[15]

KPI_SI[7]

SPDATA[7]

KPI_SI[0]

SPDATA[0]

GPC[8]

LVDATA[9]

KPI_SI[1]

SPDATA[1]

GPC[9]

LVDATA[10]

KPI_SI[2]

SPDATA[2]

GPC[10]

LVDATA[11]

KPI_SI[3]

KPI Scan In Bit 0

Sensor Interface Data Bit 0, Input































● ● ● ● ● ● ●

● ● ● ● ● ● ●

● ● ● ● ● ● ●

● ● ● ● ● ● ●

● ● ● ● ● ● ●

● ● ● ● ● ● ●

● ● ● ● ● ● ●


Rev. A5.1


Pin Name

I/O

Type

Description

GPC[15]

LVDATA[16]

SHSYNC

GPE[0]

LVDATA[17]

SVSYNC

GPE[1]

UART Interface

URTXD

SPI1_CS1_



Sensor Interface HSYNC, Input



Sensor Interface VSYNC, Input


●

●

GPA[10]

URRXD

LMVSYNC

LFMARK

GPA[11]

SPI 0 Interface

SPI0_CLK

IOU UART TX Data, Output


Active

IOU UART RX Data, Input

GPIO Port A Bit 10



GPIO Port A Bit 11

GPD[12]

SPI0_CS0_

GPD[13]

SPI0_DI

GPD[14]

SPI0_DO

GPD[15]

SD Card Interface

SDCLK

IOU SPI Port 0 Clock

Output in Master Mode

Input in Slave Mode


IOU SPI Port 0 Device Select 0, Low Active

Output in Master Mode

Input in Slave Mode


IOU SPI Port 0 Data Input


IOU SPI Port 0 Data Output


IOU SD Port 0 Clock, Output

●

●

●

●

●

●

●



●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●


Rev. A5.1


Pin Name

I/O

Type

Description

GPE[7]

SDCMD

GPE[6]

SDDAT[0]

GPE[2]

SDDAT[1]

GPE[3]

SDDAT[2]

GPE[4]

SDDAT[3]

GPE[5]

GPIO A

GPA[0]

GPA[1]

SD_CD_

GPA[2]

LMVSYNC

LFMARK

KPI_SO[0]

GPA[3]

UHL_DP1

KPI_SO[1]

GPA[4]

UHL_DM1

KPI_SO[2]

GPA[5]

SPI0_CS1_


IOU SD Port 0 Command/Response


IOU SD Port 0 Data Bit 0








●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

KPI_SO[3]

GPA[6]

SPI1_CS1_

IOU GPIO Port A Bit 0


SD Card Detect, Input, Low Active




KPI Scan Out Bit 0


USB Host 1.0 Lite Port 1, D+



USB Host 1.0 Lite Port 1, D-




Active




●

●

●

●

●

●

●



●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●


Rev. A5.1


Pin Name

I/O

Type

Description

KPI_SO[4]

GPA[7]

KPI_SO[5]

RTC (Real Time Clock)

RTC_XIN

(32768Hz)

RTC_XOUT

(32768Hz)

RTC_RWAKE_

RTC_RPWR

I

O

I

32768Hz Crystal Input

32768Hz Crystal Output

Wakeup Enable, Input, Low Active

OD Power Enable, Open-Drain

USB 2.0 Device Interface

UD_CDET

UD_DP

UD_DM

UD_REXT

I USB Device Connect Detect, Input, High

Active

IO USB 2.0 Device D+

IO USB 2.0 Device D-

IO External Resistor Connect

Recommend to connect 12.1K

Ω resistor to ground for USB 2.0 PHY

TV Out

TVDAC_TVOUT

Active




TVDAC_REXT

TVDAC_COMP

TVDAC_VREF

O Composite/Chroma Output

Connect an external 75 Ω resistor to ground of TVDAC as TV terminal impedence

IO External Resistor Connection

Recommend to connect 160 Ω resistor to ground of TVDAC

O External Capacitor Connection

Connect 0.1uF capacitor to VDD33 of TVDAC

O Reference Voltage Output

Connect 0.1uF capacitor to ground of

TVDAC

ADC & Touch Panel

ADC_AIN[3]

ADC_AIN[2]

I

I

ADC Analog Input Channel 3

ADC Analog Input Channel 2

●

●

●

●

●

●

●

●

●

●

●



●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●


Rev. A5.1


Pin Name

I/O

Type

Description




Rev. A5.1


Pin Name

I/O

Type

Description

TVDAC_VSS33

ADC_VDD33

ADC_VSS33

ADAC_HPVDD33

ADAC_HPVSS33

ADAC_AVDD33

ADAC_AVSS33

VDD33

VDD18

VSS

P

G

P

G

P

P

G

G

P

G

TV DAC Ground (0V)

ADC Power (3.3V)

ADC Ground (0V)

Audio DAC Headphone Driver Power (3.3V)

Audio DAC Headphone Driver Ground (0V)

Audio DAC Power (3.3V)

Audio DAC Ground (0V)

I/O Power (3.3V)

Core Logic Power (1.8V)

Ground (0V)

4.2 Pin Type Description

Type Description

I

O

OD

IO

Input

Output

Open Drain output

Input / Output

IOD

IOU

Input with pull-Down / Output

Input with pull-Up / Output

IOSU Input with Schmitt trigger & pull-Up/ Output

P Power

G Ground

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●




Rev. A5.1


5. ELECTRICAL SPECIFICATION

5.1 Absolute Maximum Rating

Parameters

Ambient Temperature

Storage Temperature

Voltage On Any Pin

Power Supply Voltage (Core Logic)

Power Supply Voltage (I/O Buffer)

Injection Current (Latch-Up Testing)

Crystal Frequency

5.2 DC Characteristics (Normal I/O)

Symbol Parameter

VDD33 I/O Buffer Post-Driver Voltage

MVDD33 SDRAM Operation Voltage

VDD18

Core Logic and I/O

Buffer Pre-Driver

Voltage

200MHz

100MHz

Condition

MVDDQ/

MVDD

RTC_VDD

DDR Operation

Voltage

100MHz

RTC Power Supply

I

RTC_VDD

RTC Supply Current

V

IH

Input High Voltage

V

IL

V

T

Input Low Voltage

Threshold Point

V

V

I

I

T+

T-

CC

L

RTC_VDD<VDD18

Schmitt Trigger Low to High

Threshold Point

Schmitt Trigger High to Low

Threshold Point

Core Power Supply Current

Input Leakage Current

F

CPU

= 200MHz,

MCLK = 100MHz,

VDD18 = 1.8V



Min. Typ. Max. Unit

3.0

3.0

3.3

3.3

3.6

3.6

V

V

1.62 1.8 1.98 V

1.7

Values

-20 °C ~ 85 °C

-40 °C ~ 125 °C

-0.3V ~ 3.6V

-0.5V ~ 2.5V

-0.5V ~ 4.6V

100mA

2MHz ~ 27MHz

1.8 1.9

1.7 1.8 1.9

1.2

-

1.8

-

4

-

2.0

-0.3

-

-

5.5

0.8

1.45 1.58 1.74

1.44 1.42 1.56

0.89 1.06 0.99

- 160

-

V

V

V uA

V

V

V

V

V mA

-10

-

10 uA


Rev. A5.1


Symbol Parameter Condition

I

OZ

R

PU

R

PD

V

OL

V

OH

Tri-State Output Leakage

Current

Pull-Up Resistor

Pull-Down Resistor

Output Low Voltage

Output High Voltage

I

OL

I

OH

Low Level Output

Current

High Level Output

Current

4mA I/O V

OL

= 0.4V

4mA I/O V

OH

= 2.4V

5.3 Audio DAC Characteristics


-10

39

40

-

2.4

-

-

-

65

56

-

-

4.0

5.9

Test conditions: RL = 10K / 50pF, BW = 20Hz ~ 20KHz, Freq.= 1KHz, Sample Rate = 48KHz.

Parameter Min Typ Max

10

116

108

0.4

-

-

-

Unit uA k Ω k Ω

V

V mA mA

Operating Voltage 3.0 3.3 3.6 V

Reference Voltage

Reference Capacitor

Full Scale output voltage

Maximum Output Power

Maximum Output Power @ 32ohm load

Maximum Output Power @ 16ohm load

L-Channel SNR

R-Channel SNR

L-Channel THD+N

R-Channel THD+N

L-Channel THD+N @ 32ohm load

R-Channel THD+N @ 32ohm load

L-Channel THD+N @ 16ohm load

R-Channel THD+N @ 16ohm load

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DAC_VDD/2

0.1

1.32

85

-64

-64

-63

-

-

-

86

-63

-62

-62

-

-

-

-

-

-

-

-

-

-

-

52

46

41 dBV dBV dB dB dB

V uF

Vrms mW mW mW dB dB dB




Rev. A5.1


5.4 ADC Characteristics

Parameter

SAR ADC Input Voltage Range

Resolution of ADC

Signal-to-Noise Plus Distortion of ADC from Line In

Integral Non-Linearity of ADC

Differential Non-Linearity of ADC

No Missing Code

AD Conversion Rate=ADCCLK/16

5.5 AC Characteristics (Digital Interface)

5.5.1 Clock Input Characteristics

T

XIN

XIN

T

XINWH

Min.

3.0

-

-

-

-

-

-

T

XINWL

Typ.

-

-

TBD

±2.0

±0.8

10

-

Max.

3.6

10

-

-

-

-

400

Unit

V bit dB

LSB

LSB bit

KHz

F

XIN

= 1 / T

XIN

XIN

DUTY

= T

XINWH

/ ( T

XINWH

+ T

XINWL

)


F

XIN

Clock Input Frequency

XIN

DUTY

Clock Input Duty Cycle

Min.

-

45

Typ.

12 / 27

50

Max. Unit

-

55

MHz

%




Rev. A5.1


5.5.2 SDRAM Interface

T

MCLK

MCLK

Command Out

MCS_

MRAS_

MCAS_

MWE_

MA

MBA

MDQS0

MDQS1

Data Output

MD[15:0]

T

MWL

T

MODLY

T

MWH

T

MDQSH

T

MDSU

T

MDH

T

MOH

T

MDQSL


T

T

T

T

T

MCLK

MWL

SWH

MOH

MODLY

MCLK Clock Cycle Time

MCLK Clock Low Time

6

0.45

MCLK Clock High Time

Command and Address Output

Delay Time

0.45

-

Command and Address Output

Hold Time

2

T

MDQSH

MDQS0/MDQS1 High Time

T

MDQSL

MDQS0/MDQS1 Low Time

T

T

MDSU

MDH

VREF

MD to MDQS0/MDQS1 Setup Time

MD to MDQS0/MDQS1 Hold Time

IO reference voltage

0.4

0.4

0.6

0.6

0.49


-

-

-

-

12 ns

0.55 T

MCLK

0.55 T

MCLK

2 ns

-

-

-

-

-

-

-

0.6

0.6

-

-

0.51 ns

T

MCLK

T

MCLK ns ns

VDD




Rev. A5.1


5.5.3 Sensor/Video-In Interface

T

SWL

F

SPCLK

T

SWH

SPCLK

T

SISU

T

SIH

SHSYNC

SVSYNC

SFIELD

SPDATA[7:0]

Symbol

F

SPCLK

T

SWL

T

SWH

T

T

SISU

SIH

Parameter

SPCLK Clock Frequency

SPCLK Clock Low Time

SPCLK Clock High Time

SHSYNC, SVSYNC, SFIELD,

SPDATA[7:0] Setup Time

SHSYNC, SVSYNC, SFIELD,

SPDATA[7:0] Hold Time


-

10

10

1.0

-

-

-

-

50

-

-

-

MHz ns ns ns

1.0

- - ns




Rev. A5.1


5.5.4 I2S Interface

T

AWL

F

ABCLK

T

AWH

I2S_BCLK

Input Mode

I2S_DIN

T

AISU

T

AIH

Output Mode

I2S_WS

I2S_DOUT

Symbol

F

ABCLK

T

AWL

T

AWH

T

AISU

T

AIH

T

AODLY

T

AOH

T

AODLY

T

AOH

Parameter

I2S_BCLK Clock Frequency

I2S_BCLK Clock Low Time

I2S_BCLK Clock High Time

I2S_DIN Setup Time

-

31.25

31.25

10

I2S_DIN Hold Time

I2S_DOUT Output Delay

Time

I2S_DOUT Output Hold Time

10

-

0.1


-

-

-

-

-

16

-

-

-

-

-

-

0.5

-

MHz ns ns ns ns ns ns




Rev. A5.1


5.5.5 LCD/Display Interface

SYNC Type LCD

LPCLK

T

LWL

F

LPCLK

T

LWH

LHSYNC

LVSYNC

LVDE

LVDATA[15:0]

Symbol

F

LPCLK

T

LWL

T

LWH

T

LODLY

T

LOH

T

LODLY

T

LOH

Parameter

LPCLK Clock Frequency

LPCLK Clock Low Time

LPCLK Clock High Time

LHSYNC, LVSYNC, LVDE and

LVDATA Output Delay Time

LHSYNC, LVSYNC, LVDE and

LVDATA Output Hold Time


-

18.5

18.5

-

-

-

-

-

27

-

-

1.3

MHz ns ns ns

0.67 - - ns




Rev. A5.1


MPU Type LCD

LPCLK (CS_)

T

LAS

LVDE (RS)

T

LCSS T

LWR

80 Mode:

LHSYNC (WR_)

T

LDODLY

LVDATA[15:0]

T

LEN

68 Mode:

LVSYNC (EN)

Symbol Parameter Condition

T

LCSS

T

LCSH

T

LAS

CS_ to WR_ Setup Time

CS_ to WR_ Hold Time

RS to WR_ Setup Time

T

LAH

RS to WR_ Hold Time

T

LDODLY

LVDATA Output Delay Time

T

T

LDOH

LWR

T

LEN

LVDATA Output Hold Time

WR_ Pulse Width

EN Pulse Width

80 Mode

68 Mode

Note: PCLK is the period of one APB bus clock.

T

LAH

T

LCSH

T

LDOH


1

-

1

1

1

2

1

1

-

-

-

-

-

-

-

-

-

-

-

-

1

-

-

-

PCLK

PCLK

PCLK

PCLK

PCLK

PCLK

PCLK

PCLK




Rev. A5.1


5.5.6 SPI Interface

T

SPWL

F

SPCLK

T

SPWH

SPI0_CLK

Input Mode

SPI0_DI

T

SPISU

T

SPIH

Output Mode

SPI0_DO

T

SPODLY


F

SPCLK

T

SPWL

T

SPWH

T

SPISU

SPI0_CLK Clock Frequency

SPI0_CLK Clock Low Time

SPI0_CLK Clock High Time

SPI0_DI Setup Time

T

SPIH

SPI0_DI Hold Time

T

SPODLY

SPI0_DO Output Delay Time

T

SPOH

SPI0_DO Output Hold Time

T

SPOH


-

20

20

10

10

-

0.2

-

-

-

-

-

-

-

25

-

-

-

-

1

-

MHz ns ns ns ns ns ns




Rev. A5.1


5.5.7 NAND Interface

NCS0_

NCS1_

NALE

NCLE

T

NWL

T

NWH

NWR_

ND[7:0]

(write)

T

NODLY

T

NOH

NRE_

T

NISU

T

NIH

ND[7:0]

(Read)


T

NWL

T

NWH

NWR_ High Hold Time

T

NODLY

ND[7:0] Output Delay Time

T

T

NOH

NISU

T

NIH

Write Pulse Low Width

ND[7:0] Output Hold Time

ND[7:0] Data in Setup Time

ND[7:0] Data in hold time


10

10

-

10

3.2

1

-

-

-

-

-

-

-

-

2.5

-

-

-

ns ns ns ns ns ns




Rev. A5.1


5.5.8 SD Card Interface

T

SDWL

F

SDCLK

T

SDWH

SDCLK

Input Mode

SDCMD,

SDDAT[3:0]

T

SDISU

T

SDIH

Output Mode

SDCMD,

SDDAT[3:0]

T

SDODLY

T

SDOH


Clock SDCLK

F

SDCLK

Clock Frequency in Data

Transfer Mode


- - 24 MHz

F

SDCLK

T

SDWL

T

SDWH

Identification Mode

Clock Low Time

Clock High Time

10

10

Input SDCMD, SDDAT[3:0] (referenced to SDCLK)

T

T

SDISU

SDIH

Input Setup Time

Input Hold Time

6

2

-

Output SDCMD, SDDAT[3:0] (referenced to SDCLK)

T

SDODLY

Output Delay Time

T

SDOH

Output Hold Time

-

2.5

-

-

-

-

-

-

400

-

-

-

-

14

-

KHz ns ns ns ns ns ns




Rev. A5.1


5.6 Power-on Sequence

5.7 Thermal characteristics of LQFP-128 Package



Thermal Performance of LQFP-128 under Forced Convection


Rev. A5.1


6. ORDERING INFORMATION

PART NO. PACKAGE TYPE

N32901U1DN LQFP-128, MCP

1

N32903R1DN TQFP-64, MCP

DESCRIPTION

Stacked 1Mbit x16 SDR MCP with LCD, CIS and I2S interface.

Stacked 4Mbit x 16 DDR MCP with CIS, SDHC and I2S interface



Stacked 4Mbit x16 DDR MCP with LCD,CIS and I2S interface.

Stacked 16Mbit x16 DDR MCP with LCD, CIS and I2S interface.

N32905U2DN LQFP-128, MCP Stacked 16Mbit x16 DDR MCP with LCD,CIS interface & TV output.

6.1 Part Number Definition

6.2 Difference between N32901U1DN, N32903U1DN, N32905U1DN and N32905U2DN

MCPed SDRAM

Type/Capacity

Analog Composite TV Output I2S Interface

N32901U1DN

N32901U2DN

N32903U1DN

N32905U1DN

N32905U2DN

SDR/2MBytes

SDR/2MBytes

DDR/8MBytes

DDR/32MBytes

DDR/32MBytes

-

-

-

V

V

V

-

V

V

-

1

MCP stands for Multi-Chip Package.




Rev. A5.1


7. PACKAGE OUTLINE

7.1 LQFP-128 (14X14X1.4mm body, 0.4mm pitch)




Rev. A5.1


7.2 TQFP-64 (10X10X1.0mm body, 0.5mm pitch)




Rev. A5.1





Rev. A5.1


UNIT: mm




Rev. A5.1


7.3 LQFP-64 (10X10X1.4mm body, 0.5mm pitch)

A

A

1

A

2 b c

D

E e

H

D

H

E

L

L

1 y

0

Symbol

Dimension in inch

Min Nom Max

0.063

0.002

0.053

0.007

0.004

0.055

0.008

0.006

0.057

0.011

0.008

0.018

0.393

0.393

0.020

0.472

0.472

0.024

0.030

0.039

0

0.004

3.5

7

Dimension in mm

Min Nom Max

1.60

0.05

1.35

0.17

0.09

1.40

0.20

0.15

1.45

0.27

0.20

10.00

10.00

0.50

0.45

12.00

12.00

0.60

1.00

0.75

0

0.10

3.5

7




Rev. A5.1


8. REVISION HISTORY

VERSION DATE

A0

A1

Jul. 25, 2012

Aug. 1, 2012

A2

A2.1

A3

A3.1

A3.2

A3.3

A3.4

A4.0

A5.0

A5.1

Aug. 30, 2012

Sept. 17, 2012

Oct. 15, 2012

Oct. 26, 2012

Nov. 8, 2012

Nov. 10, 2012

Jan. 21, 2013

Mar. 15, 2013

May. 1, 2013

May. 3,2013

PAGE

ALL

36

ALL

22

23,35

35

6,7,8,9

35

4, 5, 10, 23

ALL

ALL

28

DESCRIPTION

 Initial release.

 Add stacked DRAM size into order Information

 Add N32901U1DN Information

 Correct the N32905U2DN Pin Diagram

 1Mx16 MVDD and MVDDQ are changed from 3.3V to

1.8V for consistence with N32905 and N32903

 Extend Operation Temperature Range

 Add Parts Feature Difference Table

 Add Part Number Definition

 Add CCIR Still Image and Video Recommanded

Resolutions.

 Add LCD Display for Still Image and Video

Recommanded Resolutions.

 Modify One SPI H/W Engine to Support Two SPI Devices by Two Chip Selection Signals when SPI0 is in Master

Mode. For LQFP128 package, only SPI0 is active.

 Add USB 1.1 Host One H/W Controller, Three Different

Pin Locations Information.

 Remove Adobe Flash Feature from Comparision Table.

 Update the AC characteristics.

 Add N32903R1DN

 Add N32901R1DN Information.

 Add N32901U2DN Information.

 Add SDRAM and DDR Operation Voltage Spec

Important Notice

Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life.

All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.




Rev. A5.1

Nuvoton N3290x Data Sheet

Data Sheet

Table of Contents

1. GENERAL DESCRIPTION

2. FEATURES

3. PIN DIAGRAM

4. PIN DESCRIPTION

5. ELECTRICAL SPECIFICATION

XIN

MCLK

Command Out

MDQS0

MDQS1

Data Output

MD[15:0]

SPCLK

I2S_BCLK

Input Mode

Output Mode

SYNC Type LCD

LPCLK

LHSYNC

LVSYNC

LVDE

LVDATA[15:0]

MPU Type LCD

LPCLK (CS_)

LVDE (RS)

80 Mode:

LHSYNC (WR_)

LVDATA[15:0]

68 Mode:

LVSYNC (EN)

SPI0_CLK

Input Mode

Output Mode

NCS0_

NCS1_

NALE

NCLE

NWR_

ND[7:0]

(write)

NRE_

ND[7:0]

(Read)

SDCLK

Input Mode

Output Mode

6. ORDERING INFORMATION

7. PACKAGE OUTLINE

UNIT: mm

8. REVISION HISTORY

Important Notice

Related manuals

Nuvoton

N3291xUxDN

Nuvoton

N9H26 series - ARM9 CPU core and integrated

Case Logic

NCLE4K

Nuvoton

NuMaker-HMI-N9H26

Case Logic

NCLE20F

PQI

Cool Drive U339, 16GB

Nuvoton

NuMaker NuEZcam

Nuvoton

NuMaker-HMI-N9H20

ESAB

Arc 4001i - Origo™ Arc 4001i

Table of contents