Freescale ColdFire MCF5282, MCF5216 microcontroller User’s Manual
The ColdFire MCF5282 and MCF5216 microcontrollers offer a powerful and flexible solution for a wide range of embedded applications. Featuring a Version 2 ColdFire core, these devices provide a high-performance, low-power solution that can be customized to meet your specific needs. The ColdFire MCF5282 and MCF5216 microcontrollers are supported by a comprehensive set of peripheral modules, including a Fast Ethernet controller, FlexCAN, I2C, QSPI, and QADC, providing the functionality needed for a wide range of embedded applications. These devices include 64KB of SRAM, 512KB of Flash memory, and support for SDRAM.
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Devices Supported: MCF5214 MCF5216 MCF5280 MCF5281 MCF5282 Document Number: MCF5282UM Rev. 3 2/2009 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 MCF5282 and MCF5216 ColdFire® Microcontroller User’s Manual How to Reach Us: Home Page: Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] Freescale Semiconductor Literature Distribution Center P.O. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. MCF5282UM Rev. 3 2/2009 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 www.freescale.com I2C Module FlexCAN Module General Purpose I/O Module Chip Configuration Module (CCM) Queued Analog-to-Digital Converter (QADC) Reset Controller Module Debug Support IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Memory Map Revision History Index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A B IND Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules DMA Timers Queued Serial Peripheral Interface Module (QSPI) UART Modules 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A B IND Overview ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module DMA Controller Module Fast Ethernet Controller (FEC) Watchdog Timer Module Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules DMA Timers Queued Serial Peripheral Interface Module (QSPI) UART Modules I2C Module FlexCAN Module General Purpose I/O Module Chip Configuration Module (CCM) Queued Analog-to-Digital Converter (QADC) Reset Controller Module Debug Support IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Memory Map Revision History Index Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 1 1.1 1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.1.1.4 Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.1.2 System Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.1.3 External Interface Module (EIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.4 Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.6 General Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.7 Interrupt Controllers (INTC0/INTC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.8 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.1.9 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.1.10 UART Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.1.11 DMA Timers (DTIM0-DTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.12 General-Purpose Timers (GPTA/GPTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.13 Periodic Interrupt Timers (PIT0-PIT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.14 Software Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.15 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.16 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 MCF5282-Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.1 Fast Ethernet Controller (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.2 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.3 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.4 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.5 Queued Analog-to-Digital Converter (QADC) . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Chapter 2 ColdFire Core 2.1 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . 2.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.7 Access Control Registers (ACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.8 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freescale Semiconductor 2-1 2-1 2-2 2-4 2-4 2-5 2-6 2-7 2-7 2-7 2-7 v Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 1 Overview Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC) 3.1 3.2 3.3 vi Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1.1 Introduction to the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.3 Accumulator Registers (ACC0–3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.4 Accumulator Extension Registers (ACCext01, ACCext23) . . . . . . . . . . . . . . . . 3-7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3.1.1 Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.3 2.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.10 Memory Base Address Registers (RAMBAR, FLASHBAR) . . . . . . . . . . . . . . . 2-8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.1 Version 2 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.2 Instruction Set Architecture (ISA_A+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.3.1 Exception Stack Frame Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.4.1 Access Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.4.2 Address Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.4.3 Illegal Instruction Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.4.4 Divide-By-Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.5 Privilege Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.6 Trace Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.7 Unimplemented Line-A Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.8 Unimplemented Line-F Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.9 Debug Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.10 RTE and Format Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.11 TRAP Instruction Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.12 Unsupported Instruction Exception . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.13 Interrupt Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.14 Fault-on-Fault Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.15 Reset Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.5.1 Timing Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.2 MOVE Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.3 Standard One Operand Instruction Execution Times . . . . . . . . . . . . . 2-28 2.3.5.4 Standard Two Operand Instruction Execution Times . . . . . . . . . . . . . 2-28 2.3.5.5 Miscellaneous Instruction Execution Times . . . . . . . . . . . . . . . . . . . . 2-30 2.3.5.6 EMAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.3.5.7 Branch Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 3-11 3-12 3-12 3-12 3-13 3-14 3-14 Chapter 4 Cache 4.1 4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Access Control Registers (ACR0, ACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Interaction with Other Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Memory Reference Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Cache Coherency and Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Cache Miss Fetch Algorithm/Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-1 4-1 4-2 4-3 4-6 4-7 4-7 4-8 4-8 4-8 4-9 Chapter 5 Static RAM (SRAM) 5.1 5.2 5.3 SRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 SRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 SRAM Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-1 5-1 5-3 5-3 5-4 Chapter 6 ColdFire Flash Module (CFM) 6.1 6.2 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 CFM Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Flash Base Address Register (FLASHBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 CFM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.1 CFM Configuration Register (CFMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.2 CFM Clock Divider Register (CFMCLKD) . . . . . . . . . . . . . . . . . . . . . . . Freescale Semiconductor 6-1 6-2 6-4 6-5 6-5 6-7 6-8 6-8 6-9 vii Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 3.3.2 3.3.3 3.3.4 3.3.5 3.3.1.2 Saving and Restoring the EMAC Programming Model . . . . . . . . . . . . 3.3.1.3 MULS/MULU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1.4 Scale Factor in MAC or MSAC Instructions . . . . . . . . . . . . . . . . . . . . EMAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 6.6 6.7 6-10 6-12 6-13 6-14 6-15 6-16 6-16 6-17 6-17 6-17 6-17 6-18 6-19 6-21 6-21 6-22 6-22 6-23 6-23 6-23 6-23 Chapter 7 Power Management 7.1 7.2 7.3 viii Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3.1 Low-Power Interrupt Control Register (LPICR) . . . . . . . . . . . . . . . . . . 7.2.3.2 Low-Power Control Register (LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1.3 Doze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1.5 Peripheral Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.1 ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.2 Static Random-Access Memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.4 System Control Module (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.5 SDRAM Controller (SDRAMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.6 Chip Select Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-1 7-2 7-2 7-2 7-4 7-5 7-5 7-5 7-6 7-6 7-6 7-6 7-6 7-6 7-6 7-7 7-7 7-7 7-7 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.4 6.3.4.3 CFM Security Register (CFMSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.4 CFM Protection Register (CFMPROT) . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.5 CFM Supervisor Access Register (CFMSACC) . . . . . . . . . . . . . . . . . 6.3.4.6 CFM Data Access Register (CFMDACC) . . . . . . . . . . . . . . . . . . . . . . 6.3.4.7 CFM User Status Register (CFMUSTAT) . . . . . . . . . . . . . . . . . . . . . . 6.3.4.8 CFM Command Register (CFMCMD) . . . . . . . . . . . . . . . . . . . . . . . . . CFM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Program and Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3.1 Setting the CFMCLKD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3.2 Program, Erase, and Verify Sequences . . . . . . . . . . . . . . . . . . . . . . . 6.4.3.3 Flash Valid Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3.4 Flash User Mode Illegal Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.5 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Security Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Back Door Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Erase Verify Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 8 System Control Module (SCM) 8.1 8.2 8.3 8.4 8.5 8.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4.1 Internal Peripheral System Base Address Register (IPSBAR) . . . . . . . . . . . . . 8-2 8.4.2 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4.3 Core Reset Status Register (CRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.4 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.5 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Internal Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.2 Arbitration Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.2.1 Round-Robin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.2.2 Fixed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.3 Bus Master Park Register (MPARK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 System Access Control Unit (SACU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3.1 Master Privilege Register (MPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.6.3.2 Peripheral Access Control Registers (PACR0–PACR8) . . . . . . . . . . . 8-13 Freescale Semiconductor ix Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.3.2.7 DMA Controller (DMAC0–DMA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.8 UART Modules (UART0, UART1, and UART2) . . . . . . . . . . . . . . . . . . 7-8 7.3.2.9 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.10 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.11 DMA Timers (DMAT0–DMAT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.12 Interrupt Controllers (INTC0, INTC1) . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.13 Fast Ethernet Controller (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.14 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.15 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.16 Chip Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.17 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.2.18 Edge Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.2.19 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3) . . . . . 7-10 7.3.2.21 Queued Analog-to-Digital Converter (QADC) . . . . . . . . . . . . . . . . . . 7-11 7.3.2.22 General Purpose Timers (GPTA and GPTB) . . . . . . . . . . . . . . . . . . 7-11 7.3.2.23 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.3.2.24 ColdFire Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.2.25 BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.2.26 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.3 Summary of Peripheral State During Low-Power Modes . . . . . . . . . . . . . . . . 7-13 Chapter 9 Clock Module 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.1 Normal PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.2 1:1 PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.3 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Low-power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5.1 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5.2 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.3 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.4 CLKMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.5 RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.6.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.6.2.1 Synthesizer Control Register (SYNCR) . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.6.2.2 Synthesizer Status Register (SYNSR) . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.7.1 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.7.2 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.7.3 System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.7.4 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.7.4.1 Phase and Frequency Detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.7.4.2 Charge Pump/Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.3 Voltage Control Output (VCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.4 Multiplication Factor Divider (MFD) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.5 PLL Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.6 PLL Loss of Lock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.7.4.7 PLL Loss of Lock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.8 Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.9 Loss of Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.10 Alternate Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.11 Loss of Clock in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 Chapter 10 Interrupt Controller Modules 10.1 68K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 x Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 8.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 & GPACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 10.4 10.5 Chapter 11 Edge Port Module (EPORT) 11.1 11.2 11.3 11.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt/General-Purpose I/O Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . 11.4.2.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . 11.4.2.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . 11.4.2.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . 11.4.2.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-1 11-2 11-3 11-3 11-3 11-3 11-4 11-5 11-5 11-6 11-6 Chapter 12 Chip Select Module 12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Chip Select Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 General Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1.1 8-, 16-, and 32-Bit Port Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1.2 External Boot Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 Chip Select Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1.1 Chip Select Address Registers (CSAR0–CSAR6) . . . . . . . . . . . . . . 12.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6) . . . . . . . . . . . . . . . . 12.4.1.3 Chip Select Control Registers (CSCR0–CSCR6) . . . . . . . . . . . . . . . Freescale Semiconductor 12-1 12-1 12-3 12-3 12-3 12-4 12-4 12-6 12-6 12-6 12-7 xi Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 10.2 10.3 10.1.1.1 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.1.1.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.1.1.3 Interrupt Vector Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.3.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.3.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) . . . . . . . . . . . . . . . . . . . . 10-9 10.3.4 Interrupt Request Level Register (IRLRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) . . . . . . . . . 10-11 10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)) . . . . . . . . . . . . . . . . . . . 10-12 10.3.6.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) . . . . . 10-16 Prioritization Between Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 Low-Power Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 13.1 13.2 13.3 13.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Bus and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.4.1 Bus Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.4.2 Data Transfer Cycle States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.4.3 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.4.4 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.4.5 Fast Termination Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4.6 Back-to-Back Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.4.7 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.7.1 Line Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.7.2 Line Read Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.7.3 Line Write Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.5 Misaligned Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 Chapter 14 Signal Descriptions 14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.1 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17 14.1.2 External Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.2.1 External Interface Module (EIM) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.2.1.1 Address Bus (A[23:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.2 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.3 Byte Strobes (BS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.4 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.5 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.6 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.7 Read/Write (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.8 Transfer Size(SIZ[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.9 Transfer Start (TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.10 Transfer In Progress (TIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.1.11 Chip Selects (CS[6:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2 SDRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.1 SDRAM Row Address Strobe (SRAS) . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.2 SDRAM Column Address Strobe (SCAS) . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.3 SDRAM Write Enable (DRAMW) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0]) . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.5 SDRAM Clock Enable (SCKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3 Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.1 Reset In (RSTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 xii Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 13 External Interface Module (EIM) Freescale Semiconductor 14-22 14-22 14-22 14-22 14-22 14-22 14-22 14-23 14-23 14-23 14-23 14-23 14-23 14-23 14-23 14-24 14-24 14-24 14-24 14-24 14-24 14-24 14-24 14-25 14-25 14-25 14-25 14-25 14-25 14-25 14-25 14-25 14-26 14-26 14-26 14-26 14-26 14-26 14-26 14-27 14-27 14-27 14-27 14-27 14-27 xiii Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.3.2 Reset Out (RSTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3.3 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3.4 XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3.5 Clock Output (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4 Chip Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4.1 RCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4.2 CLKMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5.1 External Interrupts (IRQ[7:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6 Ethernet Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.1 Management Data (EMDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.2 Management Data Clock (EMDC) . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.3 Transmit Clock (ETXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.4 Transmit Enable (ETXEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.5 Transmit Data 0 (ETXD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.6 Collision (ECOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.7 Receive Clock (ERXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.8 Receive Data Valid (ERXDV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.9 Receive Data 0 (ERXD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.10 Carrier Receive Sense (ECRS) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.11 Transmit Data 1–3 (ETXD[3:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.12 Transmit Error (ETXER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.13 Receive Data 1–3 (ERXD[3:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.14 Receive Error (ERXER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.7 Queued Serial Peripheral Interface (QSPI) Signals . . . . . . . . . . . . . . . . . . . 14.2.7.1 QSPI Synchronous Serial Output (QSPI_DOUT) . . . . . . . . . . . . . . 14.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN) . . . . . . . . . . . . . 14.2.7.3 QSPI Serial Clock (QSPI_CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8 FlexCAN Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8.1 FlexCAN Transmit (CANTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8.2 FlexCAN Receive (CANRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.9 I2C Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.9.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.9.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.10UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.10.1 Transmit Serial Data Output (UTXD[2:0]) . . . . . . . . . . . . . . . . . . . 14.2.10.2 Receive Serial Data Input (URXD[2:0]) . . . . . . . . . . . . . . . . . . . . 14.2.10.3 Clear-to-Send (UCTS[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.10.4 Request-to-Send (URTS[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.11General Purpose Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.11.1 GPTA[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.11.2 GPTB[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.11.3 External Clock Input (SYNCA/SYNCB) . . . . . . . . . . . . . . . . . . . . 14.2.12DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14-27 14-27 14-28 14-28 14-28 14-28 14-28 14-28 14-28 14-28 14-29 14-29 14-29 14-29 14-29 14-29 14-29 14-29 14-30 14-30 14-30 14-30 14-30 14-31 14-31 14-31 14-31 14-32 14-32 14-32 14-32 14-32 14-32 14-32 14-32 14-32 14-32 Chapter 15 Synchronous DRAM Controller Module 15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2 Block Diagram and Major Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 SDRAM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv 15-1 15-1 15-1 15-3 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.12.1 DMA Timer 0 Input (DTIN0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.2 DMA Timer 0 Output (DTOUT0) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.3 DMA Timer 1 Input (DTIN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.4 DMA Timer 1 Output (DTOUT1) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.5 DMA Timer 2 Input (DTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.6 DMA Timer 2 Output (DTOUT2) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.7 DMA Timer 3 Input (DTIN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.12.8 DMA Timer 3 Output (DTOUT3) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13Analog-to-Digital Converter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.1 QADC Analog Input (AN0/ANW) . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.2 QADC Analog Input (AN1/ANX) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.3 QADC Analog Input (AN2/ANY) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.4 QADC Analog Input (AN3/ANZ) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.5 QADC Analog Input (AN52/MA0) . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.6 QADC Analog Input (AN53/MA1) . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.7 QADC Analog Input (AN55/TRIG1) . . . . . . . . . . . . . . . . . . . . . . . 14.2.13.8 QADC Analog Input (AN56/TRIG2) . . . . . . . . . . . . . . . . . . . . . . . 14.2.14Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.14.1 JTAG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST) . . . . . . . . 14.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS) . . . . . . . . . . . . . . . . . 14.2.14.4 Development Serial Input/Test Data (DSI/TDI) . . . . . . . . . . . . . . . 14.2.14.5 Development Serial Output/Test Data (DSO/TDO) . . . . . . . . . . . 14.2.14.6 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.14.7 Debug Data (DDATA[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.14.8 Processor Status Outputs (PST[3:0]) . . . . . . . . . . . . . . . . . . . . . . 14.2.15Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.15.1 Test (TEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.16Power and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.16.1 QADC Analog Reference (VRH, VRL) . . . . . . . . . . . . . . . . . . . . . 14.2.16.2 QADC Analog Supply (VDDA, VSSA) . . . . . . . . . . . . . . . . . . . . . 14.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL) . . . . . . . . . . . . . . . . . . . 14.2.16.4 QADC Positive Supply (VDDH) . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.16.5 Power for Flash Erase/Program (VPP) . . . . . . . . . . . . . . . . . . . . . 14.2.16.6 Power and Ground for Flash Array (VDDF, VSSF) . . . . . . . . . . . 14.2.16.7 Standby Power (VSTBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.16.8 Positive Supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.16.9 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 16 DMA Controller Module 16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 DMA Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 DMA Request Control (DMAREQC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.3 DMA Transfer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4 DMA Controller Module Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4.1 Source Address Registers (SAR0–SAR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.4.2 Destination Address Registers (DAR0–DAR3) . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.4.3 Byte Count Registers (BCR0–BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.4.4 DMA Control Registers (DCR0–DCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.4.5 DMA Status Registers (DSR0–DSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.5 DMA Controller Module Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) . . . . . . . . . . . . . . . 16-11 16.5.2 Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.2.1 Dual-Address Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3 Channel Initialization and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.1 Channel Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.2 Programming the DMA Controller Module . . . . . . . . . . . . . . . . . . . 16-12 16.5.4 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.1 Auto-Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.2 Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.5.5 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 Freescale Semiconductor xv Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.2.1 DRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2 Memory Map for SDRAMC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2.1 DRAM Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1) . . . . . . . . 15-6 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1) . . . . . . . . . . . . . . 15-8 15.2.3 General Synchronous Operation Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.2.3.1 Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.2.3.2 SDRAM Byte Strobe Connections . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.3.3 Interfacing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.3.4 Burst Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.3.5 Auto-Refresh Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.2.3.6 Self-Refresh Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.2.4 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.2.4.1 Mode Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.3 SDRAM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.3.1 SDRAM Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.3.2 DCR Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.3.3 DACR Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.3.4 DMR Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.3.5 Mode Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.3.6 Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.1 Full and Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2 Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.1 10 Mbps and 100 Mbps MII Interface . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.2 10 Mpbs 7-Wire Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.3 Address Recognition Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.4 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.4.1 MIB Block Counters Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.4.2 Ethernet Interrupt Event Register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.4.3 Interrupt Mask Register (EIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.4.4 Receive Descriptor Active Register (RDAR) . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.4.5 Transmit Descriptor Active Register (TDAR) . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.4.6 Ethernet Control Register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.4.7 MII Management Frame Register (MMFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17.4.8 MII Speed Control Register (MSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17.4.9 MIB Control Register (MIBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.4.10Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.4.11Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 17.4.12Physical Address Lower Register (PALR) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 17.4.13Physical Address Upper Register (PAUR) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.14Opcode/Pause Duration Register (OPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.15Descriptor Individual Upper Address Register (IAUR) . . . . . . . . . . . . . . . . . 17-20 17.4.16Descriptor Individual Lower Address Register (IALR) . . . . . . . . . . . . . . . . . 17-20 17.4.17Descriptor Group Upper Address Register (GAUR) . . . . . . . . . . . . . . . . . . 17-21 17.4.18Descriptor Group Lower Address Register (GALR) . . . . . . . . . . . . . . . . . . . 17-21 17.4.19Transmit FIFO Watermark Register (TFWR) . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.4.20FIFO Receive Bound Register (FRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.4.21FIFO Receive Start Register (FRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 17.4.22Receive Descriptor Ring Start Register (ERDSR) . . . . . . . . . . . . . . . . . . . . 17-23 17.4.23Transmit Buffer Descriptor Ring Start Registers (ETSDR) . . . . . . . . . . . . . 17-24 17.4.24Receive Buffer Size Register (EMRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.5.1 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.5.1.1 Driver/DMA Operation with Buffer Descriptors . . . . . . . . . . . . . . . . 17-25 17.5.1.2 Ethernet Receive Buffer Descriptor (RxBD) . . . . . . . . . . . . . . . . . . 17-27 17.5.1.3 Ethernet Transmit Buffer Descriptor (TxBD) . . . . . . . . . . . . . . . . . . 17-29 17.5.2 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 xvi Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 17 Fast Ethernet Controller (FEC) 17-30 17-31 17-32 17-32 17-32 17-33 17-34 17-35 17-35 17-38 17-41 17-42 17-42 17-42 17-42 17-43 17-43 Chapter 18 Watchdog Timer Module 18.1 18.2 18.3 18.4 18.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5.2.1 Watchdog Control Register (WCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5.2.2 Watchdog Modulus Register (WMR) . . . . . . . . . . . . . . . . . . . . . . . . 18.5.2.3 Watchdog Count Register (WCNTR) . . . . . . . . . . . . . . . . . . . . . . . . 18.5.2.4 Watchdog Service Register (WSR) . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18-1 18-2 18-2 18-2 18-2 18-3 18-3 18-4 18-5 18-5 Chapter 19 Programmable Interrupt Timers (PIT0–PIT3) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1.3 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.1 PIT Control and Status Register (PCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.2 PIT Modulus Register (PMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.3 PIT Count Register (PCNTRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freescale Semiconductor 19-1 19-1 19-1 19-1 19-2 19-3 19-5 19-5 19-6 19-6 xvii Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.5.2.1 Hardware Controlled Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.3 User Initialization (Prior to Setting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . 17.5.4 Microcontroller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.5 User Initialization (After Setting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . . . 17.5.6 Network Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.7 FEC Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.7.1 Duplicate Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.8 FEC Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.9 Ethernet Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.10Hash Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.11Full Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.12Inter-Packet Gap (IPG) Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.13Collision Managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.14MII Internal and External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.15Ethernet Error-Managing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.15.1 Transmission Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.15.2 Reception Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 20 General Purpose Timer Modules (GPTA and GPTB) 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 xviii Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.1 GPTn[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.2 GPTn3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.3 SYNCn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS) . . . . . . . . . . 20-5 20.5.2 GPT Compare Force Register (GPCFORC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M) . . . . . . . . . . . . . . . . . . . 20-6 20.5.4 GPT Output Compare 3 Data Register (GPTOC3D) . . . . . . . . . . . . . . . . . . . 20-7 20.5.5 GPT Counter Register (GPTCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.5.6 GPT System Control Register 1 (GPTSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV) . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5.8 GPT Control Register 1 (GPTCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5.9 GPT Control Register 2 (GPTCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.5.10GPT Interrupt Enable Register (GPTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.5.11GPT System Control Register 2 (GPTSCR2) . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.5.12GPT Flag Register 1 (GPTFLG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 20.5.13GPT Flag Register 2 (GPTFLG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 20.5.14GPT Channel Registers (GPTCn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.5.15Pulse Accumulator Control Register (GPTPACTL) . . . . . . . . . . . . . . . . . . . 20-14 20.5.16Pulse Accumulator Flag Register (GPTPAFLG) . . . . . . . . . . . . . . . . . . . . . 20-15 20.5.17Pulse Accumulator Counter Register (GPTPACNT) . . . . . . . . . . . . . . . . . . 20-16 20.5.18GPT Port Data Register (GPTPORT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.5.19GPT Port Data Direction Register (GPTDDR) . . . . . . . . . . . . . . . . . . . . . . . 20-17 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.6.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.6.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.6.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.6.7 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8.1 GPT Channel Interrupts (CnF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8.2 Pulse Accumulator Overflow (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 19.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.3.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 Chapter 21 DMA Timers (DTIM0–DTIM3) 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2.1 DMA Timer Mode Registers (DTMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2.2 DMA Timer Extended Mode Registers (DTXMRn) . . . . . . . . . . . . . . . . . . . . . 21-5 21.2.3 DMA Timer Event Registers (DTERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.2.4 DMA Timer Reference Registers (DTRRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.2.5 DMA Timer Capture Registers (DTCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.2.6 DMA Timer Counters (DTCNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.3 Reference Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.4.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.4.2 Calculating Time-Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10 Chapter 22 Queued Serial Peripheral Interface (QSPI) 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.3.1 QSPI Mode Register (QMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.3.2 QSPI Delay Register (QDLYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.3.3 QSPI Wrap Register (QWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.3.4 QSPI Interrupt Register (QIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.3.5 QSPI Address Register (QAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.3.6 QSPI Data Register (QDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.3.7 Command RAM Registers (QCR0–QCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.1 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.1 Receive RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.2 Transmit RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 Freescale Semiconductor xix Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.8.3 Pulse Accumulator Input (PAIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.8.4 Timer Overflow (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 22-12 22-12 22-13 22-14 22-14 22-15 Chapter 23 UART Modules 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.3.1 UART Mode Registers 1 (UMR1n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.3.2 UART Mode Register 2 (UMR2n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.3.3 UART Status Registers (USRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.3.4 UART Clock Select Registers (UCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.3.5 UART Command Registers (UCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.3.6 UART Receive Buffers (URBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 23.3.7 UART Transmit Buffers (UTBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.3.8 UART Input Port Change Registers (UIPCRn) . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.3.9 UART Auxiliary Control Register (UACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 23.3.10UART Interrupt Status/Mask Registers (UISRn/UIMRn) . . . . . . . . . . . . . . . 23-13 23.3.11UART Baud Rate Generator Registers (UBG1n/UBG2n) . . . . . . . . . . . . . . 23-15 23.3.12UART Input Port Register (UIPn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15 23.3.13UART Output Port Command Registers (UOP1n/UOP0n) . . . . . . . . . . . . . 23-16 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 23.4.1 Transmitter/Receiver Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 23.4.1.1 Programmable Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17 23.4.1.2 Calculating Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17 23.4.2 Transmitter and Receiver Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 23.4.2.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 23.4.2.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20 23.4.2.3 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21 23.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 23.4.3.1 Automatic Echo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.3.2 Local Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.3.3 Remote Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 23.4.5 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.1 Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.2 Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5.1 Interrupt and DMA Request Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 xx Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 22.4.1.3 Command RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.2 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.3 Transfer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.4 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.5 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 24 I C Interface 2 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.2.1 I2C Address Register (I2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.2.2 I2C Frequency Divider Register (I2FDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.2.3 I2C Control Register (I2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.4 I2C Status Register (I2SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.5 I2C Data I/O Register (I2DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.3.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.3.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.3.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.3.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.3.6 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.3.7 Clock Synchronization and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.3.8 Handshaking and Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4.2 Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4.3 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.7 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 Chapter 25 FlexCAN 25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.1.1 FlexCAN Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.1.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.3 Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.3.1 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.3.1.1 Common Fields for Extended and Standard Format Frames . . . . . . 25.3.1.2 Fields for Extended Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . Freescale Semiconductor 25-1 25-2 25-3 25-4 25-4 25-4 25-5 25-7 xxi Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 23.5.1.1 Setting up the UART to Generate Core Interrupts . . . . . . . . . . . . . 23-26 23.5.1.2 Setting up the UART to Request DMA Service . . . . . . . . . . . . . . . 23-27 23.5.2 UART Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-29 Chapter 26 General Purpose I/O Module 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii 26-1 26-4 26-4 26-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 25.3.1.3 Fields for Standard Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.3.2 Message Buffer Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.4 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25.4.1 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25.4.2 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.2.1 Self-Received Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3 Message Buffer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.1 Serial Message Buffers (SMBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.2 Transmit Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.3 Receive Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.4 Locking and Releasing Message Buffers . . . . . . . . . . . . . . . . . . . . 25-11 25.4.4 Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 25.4.5 Overload Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.6 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.7 Listen-Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.8 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.8.1 Configuring the FlexCAN Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.4.9 FlexCAN Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.4.10FlexCAN Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.4.11Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.4.11.1 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.4.11.2 Low-Power Stop Mode for Power Saving . . . . . . . . . . . . . . . . . . . 25-15 25.4.11.3 Auto-Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.4.12Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5.1 CAN Module Configuration Register (CANMCR) . . . . . . . . . . . . . . . . . . . . . 25-18 25.5.2 FlexCAN Control Register 0 (CANCTRL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.5.3 FlexCAN Control Register 1 (CANCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.5.4 Prescaler Divide Register (PRESDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.5.5 FlexCAN Control Register 2 (CANCTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.5.6 Free Running Timer (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.5.7 Rx Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.5.7.1 Receive Mask Registers (RXGMASK, RX14MASK, RX15MASK) . 25-24 25.5.8 FlexCAN Error and Status Register (ESTAT) . . . . . . . . . . . . . . . . . . . . . . . . 25-25 25.5.9 Interrupt Mask Register (IMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27 25.5.10Interrupt Flag Register (IFLAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28 25.5.11FlexCAN Receive Error Counter (RXECTR) . . . . . . . . . . . . . . . . . . . . . . . . 25-29 25.5.12FlexCAN Transmit Error Counter (TXECTR) . . . . . . . . . . . . . . . . . . . . . . . . 25-30 Chapter 27 Chip Configuration Module (CCM) 27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.2 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.4.1 RCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.4.2 CLKMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.4.3 D[26:24, 21, 19:16] (Reset Configuration Override) . . . . . . . . . . . . . . . . . . . . 27.5 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.3.1 Chip Configuration Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 27.5.3.2 Reset Configuration Register (RCON) . . . . . . . . . . . . . . . . . . . . . . . 27.5.3.3 Chip Identification Register (CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freescale Semiconductor 27-1 27-1 27-1 27-1 27-2 27-2 27-2 27-2 27-3 27-3 27-3 27-3 27-4 27-4 27-5 27-6 27-6 27-7 27-8 xxiii Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10 26.3.2.1 Port Output Data Registers (PORTn) . . . . . . . . . . . . . . . . . . . . . . . 26-10 26.3.2.2 Port Data Direction Registers (DDRn) . . . . . . . . . . . . . . . . . . . . . . 26-11 26.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn) . . . . . . . . . . . . 26-13 26.3.2.4 Port Clear Output Data Registers (CLRn) . . . . . . . . . . . . . . . . . . . 26-14 26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR) . . . . . . . . . . . . . 26-16 26.3.2.6 Port E Pin Assignment Register (PEPAR) . . . . . . . . . . . . . . . . . . . 26-17 26.3.2.7 Port F Pin Assignment Register (PFPAR) . . . . . . . . . . . . . . . . . . . 26-19 26.3.2.8 Port J Pin Assignment Register (PJPAR) . . . . . . . . . . . . . . . . . . . . 26-20 26.3.2.9 Port SD Pin Assignment Register (PSDPAR) . . . . . . . . . . . . . . . . . 26-21 26.3.2.10 Port AS Pin Assignment Register (PASPAR) . . . . . . . . . . . . . . . . 26-21 26.3.2.11 Port EH/EL Pin Assignment Register (PEHLPAR) . . . . . . . . . . . . 26-22 26.3.2.12 Port QS Pin Assignment Register (PQSPAR) . . . . . . . . . . . . . . . 26-23 26.3.2.13 Port TC Pin Assignment Register (PTCPAR) . . . . . . . . . . . . . . . . 26-24 26.3.2.14 Port TD Pin Assignment Register (PTDPAR) . . . . . . . . . . . . . . . . 26-25 26.3.2.15 Port UA Pin Assignment Register (PUAPAR) . . . . . . . . . . . . . . . . 26-26 26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.4.2 Port Digital I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 Chapter 28 Queued Analog-to-Digital Converter (QADC) 28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.3.1 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.4 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.4.1 Port QA Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.4.1.1 Port QA Analog Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.1.2 Port QA Digital Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.2 Port QB Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.2.1 Port QB Analog Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.2.2 Port QB Digital I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.3 External Trigger Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.4 Multiplexed Address Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.5 Multiplexed Analog Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.6 Voltage Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.4.7 Dedicated Analog Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.4.8 Dedicated Digital I/O Port Supply Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.6 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.6.1 QADC Module Configuration Register (QADCMCR) . . . . . . . . . . . . . . . . . . . 28-7 28.6.2 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.6.3 Port Data Registers (PORTQA & PORTQB) . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.6.4 Port QA and QB Data Direction Register (DDRQA & DDRQB) . . . . . . . . . . . 28-9 28.6.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28.6.5.1 QADC Control Register 0 (QACR0) . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28.6.5.2 QADC Control Register 1 (QACR1) . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28.6.5.3 QADC Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . . . . . . . . 28-14 28.6.6 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.6.6.1 QADC Status Register 0 (QASR0) . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.6.6.2 QADC Status Register 1 (QASR1) . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.6.7 Conversion Command Word Table (CCW) . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.6.8 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 28.6.8.1 Right-Justified Unsigned Result Register (RJURR) . . . . . . . . . . . . 28-27 28.6.8.2 Left-Justified Signed Result Register (LJSRR) . . . . . . . . . . . . . . . . 28-27 28.6.8.3 Left-Justified Unsigned Result Register (LJURR) . . . . . . . . . . . . . . 28-28 xxiv Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 27.6.3 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.5 Clock Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.6 Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 Freescale Semiconductor 28-28 28-28 28-29 28-29 28-31 28-31 28-31 28-32 28-33 28-33 28-33 28-34 28-34 28-34 28-34 28-34 28-34 28-36 28-45 28-46 28-47 28-47 28-47 28-48 28-48 28-48 28-49 28-49 28-50 28-50 28-51 28-51 28-52 28-52 28-53 28-55 28-56 28-56 28-56 28-58 28-61 28-62 28-64 28-66 28-67 xxv Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 28.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.1 Result Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.2 External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.2.1 External Multiplexing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.2.2 Module Version Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.3 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.3.1 Analog-to-Digital Converter Operation . . . . . . . . . . . . . . . . . . . . . . 28.7.3.2 Conversion Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.3.3 Channel Decode and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.3.4 Sample Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.3.5 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.3.6 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.7.3.7 Successive Approximation Register (SAR) . . . . . . . . . . . . . . . . . . 28.7.3.8 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8 Digital Control Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.1 Queue Priority Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.1.1 Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.1.2 Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.5 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.6.1 Software-Initiated Single-Scan Mode . . . . . . . . . . . . . . . . . . . . . . . 28.8.6.2 Externally Triggered Single-Scan Mode . . . . . . . . . . . . . . . . . . . . . 28.8.6.3 Externally Gated Single-Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . 28.8.6.4 Interval Timer Single-Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.7 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.7.1 Software-Initiated Continuous-Scan Mode . . . . . . . . . . . . . . . . . . . 28.8.7.2 Externally Triggered Continuous-Scan Mode . . . . . . . . . . . . . . . . . 28.8.7.3 Externally Gated Continuous-Scan Mode . . . . . . . . . . . . . . . . . . . . 28.8.7.4 Periodic Timer Continuous-Scan Mode . . . . . . . . . . . . . . . . . . . . . 28.8.8 QADC Clock (QCLK) Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.9 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.10Conversion Command Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.8.11Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9 Signal Connection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9.1 Analog Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9.2 Analog Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9.3 Conversion Timing Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9.4 Analog Supply Filtering and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9.5 Accommodating Positive/Negative Stress Conditions . . . . . . . . . . . . . . . . . 28.9.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9.7 Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.9.7.1 Settling Time for the External Circuit . . . . . . . . . . . . . . . . . . . . . . . 28-67 28-68 28-68 28-68 Chapter 29 Reset Controller Module 29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.3.1 RSTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.3.2 RSTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.4.1 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.4.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5 29.5.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5 29.5.1.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.3 Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.4 Loss-of-Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.5 Loss-of-Lock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.6 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.7 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.2 Reset Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.5.2.1 Synchronous Reset Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.2.2 Internal Reset Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.2.3 Power-On Reset/Low-Voltage Detect Reset . . . . . . . . . . . . . . . . . . 29-9 29.5.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.3.1 Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.3.2 Reset Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 Chapter 30 Debug Support 30.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.3 Real-Time Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.3.1 Begin Execution of Taken Branch (PST = 0x5) . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.4.1 Revision A Shared Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.4.2 Address Attribute Trigger Register (AATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.4.3 Address Breakpoint Registers (ABLR, ABHR) . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.4.4 Configuration/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10 30.4.5 Data Breakpoint/Mask Registers (DBR, DBMR) . . . . . . . . . . . . . . . . . . . . . . 30-12 xxvi Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 28.9.7.2 Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.10.1Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.10.2Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.6 30.7 30.8 30-13 30-14 30-16 30-16 30-18 30-18 30-19 30-19 30-20 30-21 30-22 30-37 30-37 30-38 30-38 30-39 30-39 30-43 30-45 Chapter 31 IEEE 1149.1 Test Access Port (JTAG) 31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.1 Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.1.1 JTAG_EN — JTAG Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.1.2 TCLK — Test Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.1.3 TMS/BKPT — Test Mode Select / Breakpoint . . . . . . . . . . . . . . . . . 31.3.1.4 TDI/DSI — Test Data Input / Development Serial Input . . . . . . . . . . 31.3.1.5 TRST/DSCLK — Test Reset / Development Serial Clock . . . . . . . . 31.3.1.6 TDO/DSO — Test Data Output / Development Serial Output . . . . . 31.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2.1 Instruction Shift Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2.2 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2.3 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2.4 JTAG_CFM_CLKDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2.5 TEST_CTRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4.2.6 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.1 JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freescale Semiconductor 31-2 31-2 31-2 31-2 31-2 31-3 31-3 31-3 31-3 31-4 31-4 31-4 31-4 31-4 31-4 31-5 31-5 31-5 31-5 31-5 31-5 31-6 31-6 xxvii Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 30.5 30.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR) . . . . . . . . . . . . 30.4.7 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.1 CPU Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.2 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.2.1 Receive Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.2.2 Transmit Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.3 BDM Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.3.1 ColdFire BDM Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.3.2 Command Sequence Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5.3.3 Command Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.6.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.6.1.1 Emulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.6.2 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . Processor Status, DDATA Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.7.1 User Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.7.2 Supervisor Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31-7 31-7 31-8 31-8 31-8 31-8 31-9 31-9 31-9 31-9 31-9 Chapter 32 Mechanical Data 32.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9 Chapter 33 Electrical Characteristics 33.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.4 Power Consumption Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.5 Phase Lock Loop Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7 33.6 QADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8 33.7 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.8 External Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-11 33.9 Processor Bus Output Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.10General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-18 33.11Reset and Configuration Override Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-19 33.12I2C Input/Output Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-20 33.13Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-21 33.13.1MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK) . . 33-21 33.13.2MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK) . . . . . 33-22 33.13.3MII Async Inputs Signal Timing (ECRS and ECOL) . . . . . . . . . . . . . . . . . . 33-23 33.13.4MII Serial Management Channel Timing (EMDIO and EMDC) . . . . . . . . . . 33-23 33.14DMA Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.15QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.16JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-25 33.17Debug AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-27 xxviii Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 31.5.3.1 External Test Instruction (EXTEST) . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.2 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.3 SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.4 TEST_LEAKAGE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.5 ENABLE_TEST_CTRL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.6 HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.7 LOCKOUT_RECOVERY Instruction . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.8 CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3.9 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6.1 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6.2 Nonscan Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix B Revision History B.1 B.2 B.3 B.4 B.5 B.6 B.7 Changes Between Rev. 0 and Rev. 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Changes Between Rev. 0.1 and Rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Changes Between Rev. 1 and Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Changes Between Rev. 2 and Rev. 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 Changes Between Rev. 2.1 and Rev. 2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 Changes Between Rev. 2.2 and Rev. 2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 Changes Between Rev. 2.3 and Rev. 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 Freescale Semiconductor xxix Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Appendix A Register Memory Map xxx Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 The primary objective of this user’s manual is to define the functionality of the MCF5282 processor for use by software and hardware developers. The information in this book, except for changes to the flash and Ethernet functionality, also applies to the MCF5280, MCF5281, MCF5216, and MCF5214. The information in this book is subject to change without notice, as described in the disclaimers on the title page. As with any technical documentation, it is the reader’s responsibility to be sure he is using the most recent version of the documentation. To locate any published errata or updates for this document, refer to the world-wide web at http://www.freescale.com/coldfire. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5282. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire® architecture. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture. General Information The following documentation provides useful information about the ColdFire architecture and computer architecture in general: • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield • Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson. • Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A . Patterson and John L. Hennessy. ColdFire Documentation ColdFire documentation is available from the sources listed on the back cover of this manual, as well as our web site, http://www.freescale.com/coldfire. Freescale Semiconductor xxxi Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 About This Book • • • User’s manuals — These books provide details about individual ColdFire implementations and are intended to be used in conjunction with the ColdFire Programmers Reference Manual. Data sheets — Data sheets provide specific data regarding pin-out diagrams, bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations. Product briefs — Each device has a product brief that provides an overview of its features. This document is roughly equivalent to the overview (Chapter 1) of an device’s reference manual. Application notes — These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of ColdFire documentation, refer to http://www.freescale.com/coldfire. Conventions This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase. mnemonics In code and tables, instruction mnemonics are shown in lowercase. italics Italics indicate variable command parameters. Book titles in text are set in italics. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit1 longword A 32-bit data unit x In some contexts, such as signal encodings, x indicates a don’t care. n Used to express an undefined numerical value ~ NOT logical operator & AND logical operator | OR logical operator 1The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. xxxii Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 • This chapter provides an overview of the microprocessor features, including the major functional components. 1.1 Key Features A block diagram of the MCF528x and MCF521x is shown in Figure 1-1. The main features are as follows: • Static Version 2 ColdFire variable-length RISC processor — Static operation — On-chip 32-bit address and data path — Processor core and bus frequency up to 80 MHz — Sixteen general-purpose 32-bit data and address registers — ColdFire ISA_A with extensions to support the user stack pointer register, and four new instructions for improved bit processing — Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms — Illegal instruction decode that allows for 68K emulation support • System debug support — Real-time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging — Real time debug support, with one user-visible hardware breakpoint register (PC and address with optional data) that can be configured into a 1- or 2-level trigger • On-chip memories — 2-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache — 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC) with standby power supply support — 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses (256 Kbytes on the MCF5281 and MCF5214, no Flash on MCF5280) – This product incorporates SuperFlash® technology licensed from SST. • Power management — Fully-static operation with processor sleep and whole chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used • Fast Ethernet Controller (FEC) (not available on the MCF5214 and MCF5216) — 10BaseT capability, half- or full-duplex — 100BaseT capability, half- or limited-throughput full-duplex — On-chip transmit and receive FIFOs — Built-in dedicated DMA controller Freescale Semiconductor 1-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 1 Overview • • • 1-2 — Memory-based flexible descriptor rings — Media-independent interface (MII) to transceiver (PHY) FlexCAN 2.0B Module — Includes all existing features of the Freescale TouCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard data and remote frames (up to 109 bits long) – Extended data and remote frames (up to 127 bits long) – 0–8 bytes data length – Programmable bit rate up to 1 Mbit/sec — Up to 16 message buffers (MBs) – Configurable as receive (Rx) or transmit (Tx) – Support standard and extended messages — Unused message buffer (MB) space can be used as general-purpose RAM space — Listen-only mode capability — Content-related addressing — No read/write semaphores — Three programmable mask registers – Global (for MBs 0-13) – Special for MB14 – Special for MB15 — Programmable transmit-first scheme: lowest ID or lowest buffer number — “Time stamp” based on 16-bit free-running timer — Global network time, synchronized by a specific message — Programmable I/O modes — Maskable interrupts Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic — Maskable interrupts — DMA support — Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity — Up to 2 stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two UARTs — Transmit and receive FIFO buffers I2C module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview Overview • • • Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable master bit rates — Up to 16 pre-programmed transfers Queued analog-to-digital converter (QADC) — 8 direct, or up to 18 multiplexed, analog input channels — 10-bit resolution +/- 2 counts accuracy — Minimum 7 μS conversion time — Internal sample and hold — Programmable input sample time for various source impedances — Two conversion command queues with a total of 64 entries — Sub-queues possible using pause mechanism — Queue complete and pause software interrupts available on both queues — Queue pointers indicate current location for each queue — Automated queue modes initiated by: – External edge trigger and gated trigger – Periodic/interval timer, within QADC module [Queue 1 and 2] – Software command — Single-scan or continuous-scan of queues — Output data readable in three formats: – Right-justified unsigned – Left-justified signed – Left-justified unsigned — Unused analog channels can be used as digital I/O — Low pin-count configuration implemented Four 32-bit DMA timers — 15-ns resolution at 80 MHz (66 MHz for MCF5214 and MCF5216) — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input-capture capability with programmable trigger edge on input pin — Output-compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or reference-compare — DMA trigger capability on input capture or reference-compare Two 4-channel general purpose timers — Four 16-bit input capture/output compare channels per timer — 16-bit architecture — Programmable prescaler — Pulse widths variable from microseconds to seconds — Single 16-bit pulse accumulator Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 • 1-3 • • • • • • 1-4 — Toggle-on-overflow feature for pulse-width modulator (PWM) generation — One dual-mode pulse accumulation channel per timer Four periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down Software watchdog timer — 16-bit counter — Low-power mode support Phase locked loop (PLL) — Crystal or external oscillator reference — 2- to 10-MHz reference frequency for normal PLL mode — 33- to 80-MHz (66 MHz for MCF5214/16) oscillator reference frequency for 1:1 mode — Low-power modes supported — Separate clock output pin Two interrupt controllers — Support for up to 63 interrupt sources per interrupt controller (a total of 126), organized as follows: – 56 fully-programmable interrupt sources – 7 fixed-level interrupt sources — Seven external interrupt signals — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low-power modes DMA controller — Four fully programmable channels — Dual-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 x 32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — Software-programmable connections between the 11 DMA requesters in the UARTs (3), 32-bit timers (4) plus external logic (4) and the four DMA channels External bus interface — Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.) — SDRAM controller supports 8-, 16-, and 32-bit wide memory devices — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 32-bit bidirectional data bus — 24-bit address bus — Up to seven chip selects available — Byte/write enables (byte strobes) Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview • • • • — Ability to boot from internal Flash memory or external memories that are 8, 16, or 32 bits wide Reset — Separate reset in and reset out signals — Seven sources of reset: – Power-on reset (POR) – External – Software – Watchdog – Loss of clock – Loss of lock – Low-voltage detection (LVD) — Status flag indication of source of last reset Chip integration module (CIM) — System configuration during reset — Support for single chip, master, and test modes — Selects one of four clock modes — Sets boot device and its data port width — Configures output pad drive strength — Unique part identification number and part revision number General purpose I/O interface — Up to 142 bits of general purpose I/O for MCF5280/1/2 — Up to 134 bits of general purpose I/O for MCF5214/6 — Coherent 32-bit control — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO JTAG support for system-level board testing Freescale Semiconductor 1-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview Reset Controller JTAG Port External Interface Module Test Controller Debug Module Ports Module ColdFire V2 Core Flash Module 64K SRAM Note: Not present on MCF5280 DIV Interrupt Controller 1 Internal Bus Arbiter System Control Module (SCM) Interrupt Controller 0 DMA Controller 2-Kbyte D-Cache/I-Cache Chip Selects Edgeport EMAC DRAM Controller UART0 Serial I/O Clock Module (PLL) UART1 Serial I/O UART2 Serial I/O DMA Timer Modules (DTIM0– DTIM3) I2C Module Watchdog Timer FEC Note: Not present on MCF5214 and MCF5216 QADC General Purpose Timer A General Purpose Timer B QSPI FlexCAN PIT Timers (PIT0– PIT3) Figure 1-1. MCF528x and MCF521x Block Diagram 1-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chip Configuration Power Management Overview Overview Version 2 ColdFire Core The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire instruction set architecture revision A with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF5282 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost. 1.1.1.1 Cache The 2-Kbyte cache can be configured into one of three possible organizations: a 2-Kbyte instruction cache, a 2-Kbyte data cache or a split 1-Kbyte instruction/1-Kbyte data cache. The configuration is software-programmable by control bits within the privileged cache configuration register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory, organized as 128 lines, each containing 16 bytes of data. The memories consist of a 128-entry tag array (containing addresses and control bits) and a 2-Kbyte data array, organized as 512 x 32 bits. The tag and data arrays are accessed in parallel using the following address bits: Table 1-1. Cache Configuration Configuration Tag Address Data Array Address 2 Kbyte I-Cache [10:4] [10:2] 2 Kbyte D-Cache [10:4] [10:2] Split I-/D-Cache 0 Instruction Fetches Operand Accesses 0, [9:4] 1, [9:4] 0, [9:2] 1, [9:2] If the desired address is mapped into the cache memory, the output of the data array is driven onto the ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped into the tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch. The cache module includes a 16-byte line fill buffer used as temporary storage during miss processing. For all data cache configurations, the memory operates in write-through mode and all operand writes generate an external bus cycle. 1.1.1.2 SRAM The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. Freescale Semiconductor 1-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 1.1.1 The SRAM module is also accessible by non-core bus masters, for example the DMA and/or the FEC. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. As an example, system performance can be increased significantly if Ethernet packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing. 1.1.1.3 Flash This product incorporates SuperFlash® technology licensed from SST. The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module for integration with the processor core. The CFM is constructed with eight banks of 32K x 16-bit Flash arrays to generate 512 Kbytes of 32-bit Flash memory NOTE The CFM on the MCF5281 and MCF5214 is constructed with four banks of 32K x 16-bit Flash arrays to generate 256 Kbytes of 32-bit Flash memory. The MCF5280 does not contain a CFM. These arrays serve as electrically erasable and programmable, non-volatile program and data memory. The Flash memory is ideal for program and data storage for single-chip applications allowing for field reprogramming without requiring an external programming voltage source. The CFM interfaces to the V2 ColdFire core through an optimized read-only memory controller which supports interleaved accesses from the 2-cycle Flash arrays. A “backdoor” mapping of the Flash memory is used for all program, erase, and verify operations. It also provides a read datapath for non-core masters (for example, DMA). 1.1.1.4 Debug Module The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Freescale’s 683xx family of parts. The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the CLKOUT output provide execution status, captured operand data, and branch target addresses defining the dynamic execution path of the processor at the CPU’s clock rate. 1.1.2 System Control Module This section details the functionality of the System Control Module (SCM) which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the system control registers and logic. Specifically, the system control includes the internal peripheral system base address register (IPSBAR), the processor’s dual-port RAM 1-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview base address register (RAMBAR), and system control registers that include low-power and core watchdog timer control. 1.1.3 External Interface Module (EIM) The external interface module handles the transfer of information between the internal core and memory, peripherals, or other processing elements in the external address space. Programmable chip-select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing. Base memory address and block size are programmable, with some restrictions. For example, the starting address must be on a boundary that is a multiple of the block size. Each chip select can be configured to provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from user mode access or read-only access. 1.1.4 Chip Select Programmable chip select outputs provide a glueless connection to external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing. 1.1.5 Power Management The MCF5282 incorporates several low-power modes of operation which are entered under program control and exited by several external trigger events. An integrated Power-On Reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The Low Voltage Detect (LVD) section monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage is higher than the standby voltage. If the supply voltage to chip falls below the standby battery voltage, the RAM is switched over to the standby supply. 1.1.6 General Input/Output Ports All of the pins associated with the external bus interface may be used for several different functions. Their primary function is to provide an external memory interface to access off-chip resources. When not used for this function, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported. The digital I/O pins on the MCF5282 are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins. 1.1.7 Interrupt Controllers (INTC0/INTC1) There are two interrupt controllers on the MCF5282, each of which can support up to 63 interrupt sources for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level. Freescale Semiconductor 1-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview Overview SDRAM Controller The SDRAM controller provides all required signals for glueless interfacing to a variety of JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the address and data buses, SRAS, SCAS, DRAMW, SDRAM_CS[1:0], and SCKE are dedicated SDRAM signals. 1.1.9 Test Access Port The MCF5282 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The MCF5282 implementation supports the following: • Perform boundary-scan operations to test circuit board electrical continuity • Sample MCF5282 system pins during operation and transparently shift out the result in the boundary scan register • Bypass the MCF5282 for a given circuit board test by effectively reducing the boundary-scan register to a single bit • Disable the output drive to pins during circuit-board testing • Drive output pins to stable levels 1.1.10 UART Modules The MCF5282 contains three full-duplex UARTs that function independently. The three UARTs can be clocked by the system clock, eliminating the need for an external crystal. Each UART has the following features: • Each can be clocked by the system clock, eliminating a need for an external UART clock • Full-duplex asynchronous/synchronous receiver/transmitter channel • Quadruple-buffered receiver • Double-buffered transmitter • Independently programmable receiver and transmitter clock sources • Programmable data format: — 5–8 data bits plus parity — Odd, even, no parity, or force parity — One, one-and-a-half, or two stop bits • Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode • Automatic wake-up mode for multidrop applications • Four maskable interrupt conditions • All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation 1-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 1.1.8 • • Detection of breaks originating in the middle of a character Start/end break interrupt/status 1.1.11 DMA Timers (DTIM0-DTIM3) There are four independent, DMA-transfer-generating 32-bit timers (DTIM0, DTIM1, DTIM2, DTIM3) on the MCF5282. Each timer module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The selected clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference compare mode. By configuring the internal registers, each timer may be configured to assert an external signal, generate an interrupt on a particular event, or cause a DMA transfer. 1.1.12 General-Purpose Timers (GPTA/GPTB) The two general-purpose timers (GPTA and GPTB) are 4-channel timer modules. Each timer consists of a 16-bit programmable counter driven by a 7-stage programmable prescaler. Each of the four channels for each timer can be configured for input capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator. 1.1.13 Periodic Interrupt Timers (PIT0-PIT3) The four periodic interrupt timers (PIT0, PIT1, PIT2, PIT3) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor intervention. Each timer can either count down from the value written in its PIT modulus register, or it can be a free-running down-counter. 1.1.14 Software Watchdog Timer The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. 1.1.15 Phase Locked Loop (PLL) The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity, the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS. 1.1.16 DMA Controller The Direct Memory Access (DMA) controller module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module provides four channels (DMA0–DMA3) that allow Freescale Semiconductor 1-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software, explicitly setting a DCRn[START] bit or the occurrence of a hardware event from one of the on-chip peripheral devices, such as a capture event or an output reference event in a DMA timer (DTIMn) for each channel. The DMA controller supports dual-address mode to on-chip devices. 1.1.17 Reset The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep track of what caused the last reset. The power management registers for the internal low-voltage detect (LVD) circuit are implemented in the reset module. There are seven sources of reset: • External • Power-on reset (POR) • Watchdog timer • Phase-locked loop (PLL) loss of lock • PLL loss of clock • Software • Low-voltage detection (LVD) reset External reset on the RSTO pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset, and LVD control and status bits for setup and use of LVD reset or interrupt. 1.2 1.2.1 MCF5282-Specific Features Fast Ethernet Controller (FEC) The MCF5282’s integrated Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. The FEC supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to complete the interface to the media. NOTE The MCF5214 and MCF5216 devices do not contain an FEC module. 1.2.2 FlexCAN The FlexCAN module is a communication controller implementing the CAN protocol. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of real-time processing, reliable operation in a harsh EMI environment, cost-effectiveness, and required bandwidth. FlexCAN contains 16 message buffers. 1.2.3 I2C Bus The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. 1-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview Overview Queued Serial Peripheral Interface (QSPI) The queued serial peripheral interface module provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU intervention between transfers. 1.2.5 Queued Analog-to-Digital Converter (QADC) The QADC is a 10-bit, unipolar, successive approximation converter. A maximum of 8 analog input channels can be supported using internal multiplexing. A maximum of 18 input channels can be supported in the internal/external multiplexed mode. The QADC consists of an analog front-end and a digital control subsystem. The analog section includes input pins, an analog multiplexer, and sample and hold analog circuits. The analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array and a high-gain comparator. The digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. Also included are the periodic/interval timer, control and status registers, the 64-entry conversion command word (CCW) table, and the 64-entry result table. Freescale Semiconductor 1-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 1.2.4 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Overview 1-14 Freescale Semiconductor 2.1 Introduction This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the ColdFire Family Programmer’s Reference Manual. 2.1.1 Overview As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer. IAG Instruction Address Generation IC Instruction Fetch Cycle IB FIFO Instruction Buffer Instruction Fetch Pipeline Address [ 31 :0] Read Data[31:0] Operand Execution Pipeline & Select, DSOC Decode Operand Fetch Write Data[31:0] AGEX Address Generation, Execute Figure 2-1. V2 ColdFire Core Pipelines The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the Freescale Semiconductor 2-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 2 ColdFire Core instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions. The V2 ColdFire core pipeline stages include the following: • Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage) — Instruction address generation (IAG) — Calculates the next prefetch address — Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus — Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO queue • Two-stage operand execution pipeline (OEP) — Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the required components for effective address calculation, or the operand fetch cycle — Address generation/execute cycle (AGEX)—Calculates operand address or executes the instruction When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the IB until it is required by the OEP. For register-to-register and register-to-memory store operations, the instruction passes through both OEP stages once. For memory-to-register and read-modify-write memory operations, an instruction is effectively staged through the OEP twice: the first time to calculate the effective address and initiate the operand fetch on the processor’s local bus, and the second time to complete the operand reference and perform the required function defined by the instruction. The resulting pipeline and local bus structure allow the V2 ColdFire core to deliver sustained high performance across a variety of demanding embedded applications. 2.2 Memory Map/Register Description The following sections describe the processor registers in the user and supervisor programming models. The programming model is selected based on the processor privilege level (user mode or supervisor mode) as defined by the S bit of the status register (SR). Table 2-1 lists the processor registers. The user-programming model consists of the following registers: • 16 general-purpose 32-bit registers (D0–D7, A0–A7) • 32-bit program counter (PC) • 8-bit condition code register (CCR) • EMAC registers (described fully in Chapter 3, “Enhanced Multiply-Accumulate Unit (EMAC: — Four 48-bit accumulator registers partitioned as follows: – Four 32-bit accumulators (ACC0–ACC3) – Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23). 2-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC arithmetic operations generally affect the entire 48-bit destination. — One 16-bit mask register (MASK) — One 32-bit Status register (MACSR) including four indicator bits signaling product or accumulation overflow (one for each accumulator: PAV0–PAV3) The supervisor programming model is to be used only by system control software to implement restricted operating system functions, I/O control, and memory management. All accesses that affect the control features of ColdFire processors are in the supervisor programming model, which consists of registers available in user mode as well as the following control registers: • 16-bit status register (SR) • 32-bit supervisor stack pointer (SSP) • 32-bit vector base register (VBR) • 32-bit cache control register (CACR) • 32-bit access control registers (ACR0, ACR1) • Two 32-bit memory base address registers (RAMBAR, FLASHBAR) Table 2-1. ColdFire Core Programming Model BDM1 Register Width Access (bits) Reset Value Written with Section/Page MOVEC Supervisor/User Access Registers Load: 0x080 Store: 0x180 Data Register 0 (D0) 32 R/W 0xCF20_6080 No 2.2.1/2-4 Load: 0x081 Store: 0x181 Data Register 1 (D1) 32 R/W 0x13B0_1080 No 2.2.1/2-4 Data Register 2–7 (D2–D7) 32 R/W Undefined No 2.2.1/2-4 32 R/W Undefined No 2.2.2/2-4 Supervisor/User A7 Stack Pointer (A7) 32 R/W Undefined No 2.2.3/2-5 0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 No 3.2.1/3-3 0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF No 3.2.2/3-5 MAC Accumulators 0–3 (ACC0–3) 32 R/W Undefined No 3.2.3/3-6 0x807 MAC Accumulator 0,1 Extension Bytes (ACCext01) 32 R/W Undefined No 3.2.4/3-7 0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23) 32 R/W Undefined No 3.2.4/3-7 0x80E Condition Code Register (CCR) 8 R/W Undefined No 2.2.4/2-6 Load: 0x082–7 Store: 0x182–7 Load: 0x088–8E Address Register 0–6 (A0–A6) Store: 0x188–8E Load: 0x08F Store: 0x18F 0x806, 0x809, 0x80A, 0x80B Freescale Semiconductor 2-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core ColdFire Core BDM1 Width Access (bits) Register 0x80F Program Counter (PC) 32 R/W Written with Section/Page MOVEC Reset Value Contents of location 0x0000_0004 No 2.2.5/2-7 Supervisor Access Only Registers 0x002 Cache Control Register (CACR) 32 R/W 0x0000_0000 Yes 2.2.6/2-7 Access Control Register 0–1 (ACR0–1) 32 R/W See Section Yes 2.2.7/2-7 0x800 User/Supervisor A7 Stack Pointer (OTHER_A7) 32 R/W Contents of location 0x0000_0000 No 2.2.3/2-5 0x801 Vector Base Register (VBR) 32 R/W 0x0000_0000 Yes 2.2.8/2-7 0x80E Status Register (SR) 16 R/W 0x27-- No 2.2.9/2-8 0xC04 Flash Base Address Register (FLASHBAR) 32 R/W 0x0000_0000 Yes 2.2.10/2-8 0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes 2.2.10/2-8 0x004–5 1 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 30, “Debug Support”. 2.2.1 Data Registers (D0–D7) D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers. NOTE Registers D0 and D1 contain hardware configuration details after reset. See Section 2.3.4.15, “Reset Exception” for more details. BDM: Load: 0x080 + n; n = 0-7 (Dn) Store: 0x180 + n; n = 0-7 (Dn) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 Data W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – (D2-D7) Reset (D0, D1) See Section 2.3.4.15, “Reset Exception” Figure 2-2. Data Registers (D0–D7) 2.2.2 Address Registers (A0–A6) These registers can be used as software stack pointers, index registers, or base address registers. They can also be used for word and longword operations. 2-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 2-1. ColdFire Core Programming Model (continued) BDM: Load: 0x088 + n; n = 0–6 (An) Store: 0x188 + n; n = 0–6 (An) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Address W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 2-3. Address Registers (A0–A6) 2.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two program-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operation mode, as shown in the following: if SR[S] = 1 then else A7 = Supervisor Stack Pointer OTHER_A7 = User Stack Pointer A7 = User Stack Pointer OTHER_A7 = Supervisor Stack Pointer The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the responsibility of the external development system to determine, based on the setting of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This functionality is enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is cleared, only a single stack pointer (A7), defined for ColdFire ISA_A, is available. EUSP is cleared at reset. To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP: move.l Ay,USP;move to USP move.l USP,Ax;move from USP These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other instruction references to the stack pointer, explicit or implicit, access the active A7 register. NOTE The SSP is loaded during reset exception processing with the contents of location 0x0000_0000. Freescale Semiconductor 2-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core BDM: Load: 0x08F (A7) Store: 0x18F (A7) 0x800 (OTHER_A7) Access: A7: User or BDM read/write OTHER_A7: Supervisor or BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Address W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 2-4. Stack Pointer Registers (A7 and OTHER_A7) 2.2.4 Condition Code Register (CCR) The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations. The extend bit (X) is also an input operand during multiprecision arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare (CMP), Bcc, or Scc instructions are executed. BDM: LSB of Status Register (SR) R Access: User read/write BDM read/write 7 6 5 0 0 0 4 3 2 1 0 X N Z V C — — — — — W Reset: 0 0 0 Figure 2-5. Condition Code Register (CCR) Table 2-2. CCR Field Descriptions Field 7–5 2-6 Description Reserved, must be cleared. 4 X Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified result. 3 N Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if result equals zero; otherwise cleared. 1 V Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand size; otherwise cleared. 0 C Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core ColdFire Core Program Counter (PC) The PC contains the currently executing instruction address. During instruction execution and exception processing, the processor automatically increments contents of the PC or places a new value in the PC, as appropriate. The PC is a base address for PC-relative operand addressing. The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004. BDM: 0x80F (PC) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Address W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 2-6. Program Counter Register (PC) 2.2.6 Cache Control Register (CACR) The CACR controls operation of the instruction/data cache memories. It includes bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and write-protect fields. The CACR is described in Section 4.2.1, “Cache Control Register (CACR).” 2.2.7 Access Control Registers (ACRn) The access control registers define attributes for user-defined memory regions. These attributes include the definition of cache mode, write protect, and buffer write enables. The ACRs are described in Section 4.2.2, “Access Control Registers (ACR0, ACR1).” 2.2.8 Vector Base Register (VBR) The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on a 1 MB boundary. BDM: 0x801 (VBR) Access: Supervisor read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base Address W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 2-7. Vector Base Register (VBR) Freescale Semiconductor 2-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.2.5 ColdFire Core Status Register (SR) The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and before any compare (CMP), Bcc, or Scc instructions execute. BDM: 0x80E (SR) Access: Supervisor read/write BDM read/write System Byte 15 R W Reset T 0 14 0 0 13 12 S M 1 0 11 Condition Code Register (CCR) 10 0 0 9 8 I 1 1 1 7 6 5 0 0 0 0 0 0 4 3 2 1 0 X N Z V C — — — — — Figure 2-8. Status Register (SR) Table 2-3. SR Field Descriptions Field Description 15 T Trace enable. When set, the processor performs a trace exception after every instruction. 14 Reserved, must be cleared. 13 S Supervisor/user state. 0 User mode 1 Supervisor mode 12 M Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or move to SR instructions. 11 Reserved, must be cleared. 10–8 I Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or equal to current level, except edge-sensitive level 7 requests, which cannot be masked. 7–0 CCR Refer to Section 2.2.4, “Condition Code Register (CCR)”. 2.2.10 Memory Base Address Registers (RAMBAR, FLASHBAR) The memory base address registers are used to specify the base address of the internal SRAM and flash modules and indicate the types of references mapped to each. Each base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. FLASHBAR determines the base address of the on-chip flash, and RAMBAR determines the base address of the on-chip RAM. For more information, refer to Section 5.3.1, “SRAM Base Address Register (RAMBAR)” and Section 6.3.2, “Flash Base Address Register (FLASHBAR)”. 2-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.2.9 ColdFire Core 2.3.1 Functional Description Version 2 ColdFire Microarchitecture From the block diagram in Figure 2-1, the non-Harvard architecture of the processor is readily apparent. The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional 32-bit data buses. This structure minimizes the core size without compromising performance to a large degree. A more detailed view of the hardware structure within the two pipelines is presented in Figure 2-9 and Figure 2-10 below. In these diagrams, the internal structure of the instruction fetch and operand execution pipelines is shown: IAG +4 IC IB Opword Core Bus Address Extension 1 Core Bus Read Data FIFO IB Extension 2 Figure 2-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram Freescale Semiconductor 2-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.3 DSOC AGEX RGF Core Bus Address Opword Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For sequential prefetches, the next instruction address is generated by adding four to the last prefetch address. This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus (if there are no pending operand memory accesses assigned a higher priority). After the prefetch address is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and returns the instruction read data back to the IFP during the cycle. If the accessed data is not present in a local memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in the IC stage until the referenced data is available. As the prefetch data arrives in the IFP, it can be loaded into the FIFO instruction buffer or gated directly into the OEP. The V2 design uses a simple static conditional branch prediction algorithm (forward-assumed as not-taken, backward-assumed as taken), and all change-of-flow operations are calculated by the OEP and the target instruction address fed back to the IFP. The IFP and OEP are decoupled by the FIFO instruction buffer, allowing instruction prefetching to occur with the available core bus bandwidth not used for operand memory accesses. For the V2 design, the instruction buffer contains three 32-bit locations. Consider the operation of the OEP for three basic classes of non-branch instructions: • Register-to-register: op • Embedded load: op • Ry,Rx <mem>y,Rx Register-to-memory (store) move Ry,<mem>x For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) from the dual-ported register file, while the actual 2-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU, barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of instructions, and the execution time is typically a single machine cycle. See Figure 2-11. Operand Execution Pipeline DSOC RGF AGEX Rx new Rx Ry Opword Core Bus Address Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-11. V2 OEP Register-to-Register For memory-to-register (embedded-load) instructions, the instruction is effectively staged through the OEP twice with a basic execution time of three cycles. First, the instruction is decoded and the components of the operand address (base register from the RGF and displacement) are selected (DS). Second, the operand effective address is generated using the ALU execute engine (AG). Third, the memory read operand is fetched from the core bus, while any required register operand is simultaneously fetched (OC) from the RGF. Finally, in the fourth cycle, the instruction is executed (EX). The heavily-used 32-bit load instruction (move.l <mem>y,Rx) is optimized to support a two-cycle execution time. The following example in Figure 2-12 shows an effective address of the form <ea>y = (d16,Ay), i.e., a 16-bit signed displacement added to a base register Ay. Freescale Semiconductor 2-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core Operand Execution Pipeline DSOC AGEX RGF <ea>y Ay Opword Core Bus Address d16 Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-12. V2 OEP Embedded-Load Part 1 Operand Execution Pipeline DSOC AGEX Rx RGF new Rx Core Bus Address Opword Extension 1 Core Bus Write Data Extension 2 Core Bus Read Data <mem>y Figure 2-13. V2 OEP Embedded-Load Part 2 For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed simultaneously allowing single-cycle execution. See Figure 2-14 where the effective address is of the form <ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax. 2-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store operation for a three-cycle execution time. Operand Execution Pipeline DSOC AGEX Ax RGF Ry <ea>x Opword Extension 1 Core Bus Address d16 Core Bus Write Data Extension 2 Core Bus Read Data Figure 2-14. V2 OEP Register-to-Memory The pipeline timing diagrams of Figure 2-15 depict the execution templates for these three classes of instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown progressing down the operand execution pipeline. Freescale Semiconductor 2-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core Core clock Register-to-Register OEP.DSOC OC OEP.AGEX next EX Core Bus Embedded-Load OEP.DSOC DS OEP.AGEX OC AG Core Bus next EX op read Register-to-Memory (Store) OEP.DSOC OEP.AGEX DSOC next AGEX op write Core Bus Figure 2-15. V2 OEP Pipeline Execution Templates 2.3.2 Instruction Set Architecture (ISA_A+) The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes based on extensive analysis of embedded application code. The ISA was optimized for code compiled from high-level languages where the dominant operand size was the 32-bit integer declaration. This approach minimized processor complexity and cost, while providing excellent performance for compiled applications. After the initial ColdFire compilers were created, developers noted there were certain ISA additions that would enhance code density and overall performance. Additionally, as users implemented ColdFire-based designs into a wide range of embedded systems, they found certain frequently-used instruction sequences that could be improved by the creation of additional instructions. The original ISA definition minimized support for instructions referencing byte- and word-sized operands. Full support for the move byte and move word instructions was provided, but the only other opcodes supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas: 1. Enhanced support for byte and word-sized operands 2. Enhanced support for position-independent code 3. Miscellaneous instruction additions to address new functionality 2-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core Table 2-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details see the ColdFire Family Programmer’s Reference Manual. Table 2-4. Instruction Enhancements over Revision ISA_A Instruction Description BITREV The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31]. BYTEREV FF1 The contents of the destination data register are byte-reversed; new Dn[31:24] equals old Dn[7:0],..., new Dn[7:0] equals old Dn[31:24]. The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then loaded with the offset count from bit 31 where the first set bit appears. Move from USP USP → Destination register Move to USP STLDSR 2.3.3 Source register → USP Pushes the contents of the status register onto the stack and then reloads the status register with the immediate data value. Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors differ from the M68000 family because they include: • A simplified exception vector table • Reduced relocation capabilities using the vector-base register • A single exception stack frame format • Use of separate system stack pointers for user and supervisor modes. All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire processors require more software support to recover from certain access errors. See Section 2.3.4.1, “Access Error Exception” for details. Exception processing includes all actions from fault condition detection to the initiation of fetch for first handler instruction. Exception processing is comprised of four major steps: 1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to be cleared and the interrupt priority mask to set to current interrupt request level. 2. The processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to special locations within the interrupt controller’s address space with the interrupt level encoded in the address. Freescale Semiconductor 2-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core 3. The processor saves the current context by creating an exception stack frame on the system stack. The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to by the supervisor stack pointer (SSP). As shown in Figure 2-16, the processor uses a simplified fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next). 4. The processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1 MB boundary. This instruction address is generated by fetching an exception vector from the table located at the address defined in the vector base register. The index into the exception table is calculated as (4 × vector number). After the exception vector has been fetched, the vector contents determine the address of the first instruction of the desired handler. After the instruction fetch for the first opcode of the handler has initiated, exception processing terminates and normal instruction processing continues in the handler. All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see Table 2-5). The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are device-specific peripheral interrupt vectors. See Chapter 10, “Interrupt Controller Modules” for details on the device-specific interrupt sources. Table 2-5. Exception Vector Assignments 2-16 Vector Number(s) Vector Offset (Hex) Stacked Program Counter Assignment 0 0x000 — Initial supervisor stack pointer 1 0x004 — Initial program counter 2 0x008 Fault Access error 3 0x00C Fault Address error 4 0x010 Fault Illegal instruction 5 0x014 Fault Divide by zero 6–7 0x018–0x01C — Reserved 8 0x020 Fault Privilege violation 9 0x024 Next Trace 10 0x028 Fault Unimplemented line-A opcode 11 0x02C Fault Unimplemented line-F opcode 12 0x030 Next Debug interrupt 13 0x034 — Reserved 14 0x038 Fault Format error 15–23 0x03C–0x05C — Reserved 24 0x060 Next Spurious interrupt 25–31 0x064–0x07C — Reserved Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core ColdFire Core 1 Vector Number(s) Vector Offset (Hex) Stacked Program Counter Assignment 32–47 0x080–0x0BC Next Trap # 0-15 instructions 48–63 0x0C0–0x0FC — Reserved 64–255 0x100–0x3FC Next Device-specific interrupts Fault refers to the PC of the instruction that caused the exception. Next refers to the PC of the instruction that follows the instruction that caused the fault. All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically intended for use as the first instruction of an interrupt service routine that services multiple interrupt requests with different interrupt levels. For more details, see ColdFire Family Programmer’s Reference Manual. 2.3.3.1 Exception Stack Frame Definition Figure 2-16 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the second longword contains the 32-bit program counter address. SSP → 31 30 29 28 27 Format 26 25 24 23 22 21 20 19 18 17 FS[3:2] Vector + 0x4 16 15 14 13 12 11 10 9 FS[1:0] 8 7 6 5 4 3 2 1 0 Status Register Program Counter Figure 2-16. Exception Stack Frame Form The 16-bit format/vector word contains three unique fields: • A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor, indicating a two-longword frame format. See Table 2-6. Table 2-6. Format Field Encodings • Original SSP @ Time of Exception, Bits 1:0 SSP @ 1st Instruction of Handler Format Field 00 Original SSP - 8 0100 01 Original SSP - 9 0101 10 Original SSP - 10 0110 11 Original SSP - 11 0111 There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See Table 2-7. Freescale Semiconductor 2-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 2-5. Exception Vector Assignments (continued) ColdFire Core • FS[3:0] Definition 00xx Reserved 0100 Error on instruction fetch 0101 Reserved 011x Reserved 1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read 1101 Reserved 111x Reserved The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt. See Table 2-5. 2.3.4 2.3.4.1 Processor Exceptions Access Error Exception The exact processor response to an access error depends on the memory reference being performed. For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an instruction for execution. Therefore, faults during instruction prefetches followed by a change of instruction flow do not generate an exception. When the processor attempts to execute an instruction with a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this type of exception, the programming model has not been altered by the instruction generating the access error. If the access error occurs on an operand read, the processor immediately aborts the current instruction’s execution and initiates exception processing. In this situation, any address register updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory. The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes. Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. Accordingly, the PC contained in the exception stack frame merely represents the location in the program when the access error was signaled. All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its 2-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 2-7. Fault Status Encodings execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction. 2.3.4.2 Address Error Exception Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is set) results in an address error exception. Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective addressing mode generates an address error, as does an attempted execution of a full-format indexed addressing mode, which is defined by bit 8 of extension word 1 being set. If an address error occurs on a JSR instruction, the Version 2 ColdFire processor calculates the target address then the return address is pushed onto the stack. If an address error occurs on an RTS instruction, the Version 2 ColdFire processor overwrites the faulting return PC with the address error stack frame. 2.3.4.3 Illegal Instruction Exception The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits. The first instruction word is known as the operation word (or opword), while the optional words are known as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode (opmode), and the low-order 6 bits define the effective address. See Figure 2-17. The opword line definition is shown in Table 2-8. 15 14 13 12 11 Line 10 9 8 7 6 5 4 OpMode 3 2 1 0 Effective Address Mode Register Figure 2-17. ColdFire Instruction Operation Word (Opword) Format Table 2-8. ColdFire Opword Line Definition Opword[Line] Instruction Class 0x0 Bit manipulation, Arithmetic and Logical Immediate 0x1 Move Byte 0x2 Move Long 0x3 Move Word 0x4 Miscellaneous 0x5 Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc) 0x6 PC-relative change-of-flow instructions Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR) 0x7 Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) 0x8 Logical OR (OR) 0x9 Subtract (SUB), Subtract Extended (SUBX) Freescale Semiconductor 2-19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core ColdFire Core Opword[Line] Instruction Class 0xA EMAC, Move 3-bit Quick (MOV3Q) 0xB Compare (CMP), Exclusive-OR (EOR) 0xC Logical AND (AND), Multiply Word (MUL) 0xD Add (ADD), Add Extended (ADDX) 0xE Arithmetic and logical shifts (ASL, ASR, LSL, LSR) 0xF Cache Push (CPUSHL), Write DDATA (WDDATA), Write Debug (WDEBUG) In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations (line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors associated with illegal opwords in these two lines. Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively. ColdFire cores do not provide illegal instruction detection on the extension words on any instruction, including MOVEC. 2.3.4.4 Divide-By-Zero Attempting to divide by zero causes an exception (vector 5, offset equal 0x014). 2.3.4.5 Privilege Violation The attempted execution of a supervisor mode instruction while in user mode generates a privilege violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode instructions. There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in user mode for debugging purposes. 2.3.4.6 Trace Exception To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger to monitor program execution. The stop instruction has the following effects: 1. The instruction before the stop executes and then generates a trace exception. In the exception stack frame, the PC points to the stop opcode. 2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction. 2-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 2-8. ColdFire Opword Line Definition (continued) 3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in the previous step. If the processor is not in trace mode and executes a stop instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the stop, and the SR reflects the value loaded in step 2. Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap exception and then passes control to the corresponding handler. If the system requires that a trace exception be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the exception stack frame set) and pass control to the trace handler before returning from the original exception. 2.3.4.7 Unimplemented Line-A Opcode A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the attempted execution of an undefined line-A opcode. 2.3.4.8 Unimplemented Line-F Opcode A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when attempting to execute an undefined line-F opcode. 2.3.4.9 Debug Interrupt See Chapter 30, “Debug Support,” for a detailed explanation of this exception, which is generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle, but rather calculates the vector number internally (vector number 12). Additionally, SR[M,I] are unaffected by the interrupt. 2.3.4.10 RTE and Format Error Exception When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted RTE execution (where the format is not equal to {4,5,6,7}) generates a format error. The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction. The selection of the format value provides some limited debug support for porting code from M68000 applications. On M68000 family processors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE is attempted using this old format, it generates a format error on a ColdFire processor. If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame. Freescale Semiconductor 2-21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core ColdFire Core TRAP Instruction Exception The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls. The TRAP instruction may be used to change from user to supervisor mode. 2.3.4.12 Unsupported Instruction Exception If execution of a valid instruction is attempted but the required hardware is not present in the processor, an unsupported instruction exception is generated. The instruction functionality can then be emulated in the exception handler, if desired. All ColdFire cores record the processor hardware configuration in the D0 register immediately after the negation of RESET. See Section 2.3.4.15, “Reset Exception,” for details. 2.3.4.13 Interrupt Exception Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an IACK cycle. See ,” for details on the interrupt controller. 2.3.4.14 Fault-on-Fault Halt If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to to exit this state. 2.3.4.15 Reset Exception Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered. The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I] field to the highest level (level 7, 0b111). Next, the VBR is initialized to zero (0x0000_0000). The control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled. NOTE Other implementation-specific registers are also affected. Refer to each module in this reference manual for details on these registers. After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address 0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state. 2-22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.3.4.11 ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM to determine the hardware configuration. Information loaded into D0 defines the processor hardware configuration as shown in Figure 2-18. BDM: Load: 0x080 (D0) Store: 0x180 (D0) 31 30 29 Access: User read-only BDM read-only 28 R 27 26 25 24 23 22 PF 21 20 19 18 VER 17 16 REV W Reset 1 15 R MAC 1 14 DIV 0 0 1 1 13 12 11 10 0 0 0 0 0 0 EMAC FPU 1 1 0 0 9 8 7 6 0 0 1 0 0 0 0 0 5 4 3 2 1 0 ISA DEBUG W Reset 0 1 1 0 1 0 0 0 0 0 0 0 Figure 2-18. D0 Hardware Configuration Info Table 2-9. D0 Hardware Configuration Info Field Description Field Description 31–24 PF Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present. 23–20 VER ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core. 0001 V1 ColdFire core 0010 V2 ColdFire core (This is the value used for this device.) 0011 V3 ColdFire core 0100 V4 ColdFire core 0101 V5 ColdFire core Else Reserved for future use 19–16 REV Processor revision number. The default is 0b0000. 15 MAC MAC present. This bit signals if the optional multiply-accumulate (MAC) execution engine is present in processor core. 0 MAC execute engine not present in core. (This is the value used for this device.) 1 MAC execute engine is present in core. 14 DIV Divide present. This bit signals if the hardware divider (DIV) is present in the processor core. 0 Divide execute engine not present in core. 1 Divide execute engine is present in core. (This is the value used for this device.) 13 EMAC 12 FPU EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in processor core. 0 EMAC execute engine not present in core. 1 EMAC execute engine is present in core. (This is the value used for this device.) FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core. 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core. Freescale Semiconductor 2-23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core ColdFire Core Field Description 11–8 Reserved. 7–4 ISA ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core. 0000 ISA_A 0001 ISA_B 0010 ISA_C 1000 ISA_A+ (This is the value used for this device.) Else Reserved 3–0 Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core. DEBUG 0000 DEBUG_A 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 1001 DEBUG_B+ 1011 DEBUG_D+ 1111 DEBUG_D+PST Buffer Else Reserved Information loaded into D1 defines the local memory hardware configuration as shown in the figure below. BDM: Load: 0x1 (D1) Store: 0x1 (D1) 31 R 30 CLSZ Access: User read-only BDM read-only 29 28 27 CCAS 26 25 24 23 22 CCSZ 21 20 19 FLASHSZ 18 17 16 0 0 0 W Reset R 0 0 0 1 0 0 1 1 1 0 1 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBSZ UCAS SRAMSZ W Reset 0 0 0 1 1 0 0 0 0 Figure 2-19. D1 Hardware Configuration Info Table 2-10. D1 Hardware Configuration Information Field Description Field Description 31–30 CLSZ Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size. 29–28 CCAS Configurable cache associativity. 00 Four-way 01 Direct mapped (This is the value used for this device) Else Reserved for future use 2-24 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 2-9. D0 Hardware Configuration Info Field Description (continued) ColdFire Core Field Description 27–24 CCSZ Configurable cache size. Indicates the amount of instruction/data cache. The cache configuration options available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the CACR register. 0000 No configurable cache 0001 512B configurable cache 0010 1KB configurable cache 0011 2KB configurable cache (This is the value used for this device) 0100 4KB configurable cache 0101 8KB configurable cache 0110 16KB configurable cache 0111 32KB configurable cache Else Reserved 23–19 FLASHSZ Flash bank size. 0000-0111 No flash 1000 64-KB flash 1001 128-KB flash 1010 256-KB flash 1011 512-KB flash (This is the value used for this device) Else Reserved for future use. 18–16 Reserved 15–14 MBSZ Bus size. Defines the width of the ColdFire master bus datapath. 00 32-bit system bus datapath (This is the value used for this device) 01 64-bit system bus datapath Else Reserved 13–8 Reserved, resets to 0b010000 7–3 SRAMSZ 2–0 2.3.5 SRAM bank size. 00000 No SRAM 00010 512 bytes 00100 1 KB 00110 2 KB 01000 4 KB 01010 8 KB 01100 16 KB 01110 32 KB 10000 64 KB (This is the value used for this device) 10010 128 KB Else Reserved for future use Reserved. Instruction Execution Timing This section presents processor instruction execution times in terms of processor-core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where: • C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution. Freescale Semiconductor 2-25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 2-10. D1 Hardware Configuration Information Field Description (continued) • R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1). This section includes the assumptions concerning the timing values and the execution time details. 2.3.5.1 Timing Assumptions For the timing data presented in this section, these assumptions apply: 1. The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or extension words. 2. The OEP does not experience any sequence-related pipeline stalls. The most common example of stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE operations (except MOVEM), certain hardware resources within the processor are marked as busy for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of resources and this stall does not apply. 3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core. 4. All operand data accesses are aligned on the same byte boundary as the operand size; for example, 16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4 addresses. The processor core decomposes misaligned operand references into a series of aligned accesses as shown in Table 2-11. Table 2-11. Misaligned Operand References 2.3.5.2 address[1:0] Size Bus Operations Additional C(R/W) 01 or 11 Word Byte, Byte 2(1/0) if read 1(0/1) if write 01 or 11 Long Byte, Word, Byte 3(2/0) if read 2(0/2) if write 10 Long Word, Word 2(1/0) if read 1(0/1) if write MOVE Instruction Execution Times Table 2-12 lists execution times for MOVE.{B,W} instructions; Table 2-13 lists timings for MOVE.L. NOTE For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode. 2-26 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core ET with {<ea> = (d16,PC)} equals ET with {<ea> = (d16,An)} ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d8,An,Xi*SF)} Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Core The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w and xxx.l. Table 2-12. MOVE Byte and Word Execution Times Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1) (Ay)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1) -(Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1)) 3(1/1) (d16,Ay) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — — (d8,Ay,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — — xxx.w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — xxx.l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — (d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — — (d8,PC,Xi*SF) 4(1/0) 4(1/1) 4(1/1) 4(1/1)) — — — #xxx 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — — Table 2-13. MOVE Long Execution Times Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) xxx.wl Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (Ay)+ 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -(Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (d16,Ay) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,Ay,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — xxx.w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — xxx.l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — — (d16,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — — (d8,PC,Xi*SF) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — — #xxx 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — — Freescale Semiconductor 2-27 ColdFire Core Standard One Operand Instruction Execution Times Table 2-14. One Operand Instruction Execution Times Effective Address Opcode <EA> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx BITREV Dx 1(0/0) — — — — — — — BYTEREV Dx 1(0/0) — — — — — — — CLR.B <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — CLR.W <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — CLR.L <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — EXT.W Dx 1(0/0) — — — — — — — EXT.L Dx 1(0/0) — — — — — — — EXTB.L Dx 1(0/0) — — — — — — — FF1 Dx 1(0/0) — — — — — — — NEG.L Dx 1(0/0) — — — — — — — NEGX.L Dx 1(0/0) — — — — — — — NOT.L Dx 1(0/0) — — — — — — — SCC Dx 1(0/0) — — — — — — — SWAP Dx 1(0/0) — — — — — — — TST.B <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) TST.W <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) TST.L <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0) 2.3.5.4 Standard Two Operand Instruction Execution Times Table 2-15. Two Operand Instruction Execution Times Effective Address Opcode 2-28 <EA> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) xxx.wl #xxx ADD.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) ADD.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ADDI.L #imm,Dx 1(0/0) — — — — — — — ADDQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ADDX.L Dy,Dx 1(0/0) — — — — — — — AND.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) AND.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ANDI.L #imm,Dx 1(0/0) — — — — — — — Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.3.5.3 ColdFire Core Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 2-15. Two Operand Instruction Execution Times (continued) Effective Address Opcode <EA> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) xxx.wl #xxx ASL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) ASR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) BCHG Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — BCHG #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — BCLR Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — BCLR #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — BSET Dy,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — BSET #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — BTST Dy,<ea> 2(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) — BTST #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — — CMP.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) CMPI.L #imm,Dx 1(0/0) — — — — — — — DIVS.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) DIVU.W <ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0) DIVS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — DIVU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — EOR.L Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — EORI.L #imm,Dx 1(0/0) — — — — — — — LEA <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) — LSL.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) LSR.L <ea>,Dx 1(0/0) — — — — — — 1(0/0) MOVEQ.L #imm,Dx — — — — — — — 1(0/0) OR.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) OR.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ORI.L #imm,Dx 1(0/0) — — — — — — — REMS.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — REMU.L <ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — — SUB.L <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) SUB.L Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — SUBI.L #imm,Dx 1(0/0) — — — — — — — SUBQ.L #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — SUBX.L Dy,Dx 1(0/0) — — — — — — — Freescale Semiconductor 2-29 ColdFire Core Miscellaneous Instruction Execution Times Table 2-16. Miscellaneous Instruction Execution Times Effective Address Opcode <EA> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx CPUSHL (Ax) — 11(0/1) — — — — — — LINK.W Ay,#imm 2(0/1) — — — — — — — MOVE.L Ay,USP 3(0/0) — — — — — — — MOVE.L USP,Ax 3(0/0) — — — — — — — MOVE.W CCR,Dx 1(0/0) — — — — — — — MOVE.W <ea>,CCR 1(0/0) — — — — — — 1(0/0) MOVE.W SR,Dx 1(0/0) — — — — — — — MOVE.W <ea>,SR 7(0/0) — — — — — — 7(0/0) 2 MOVEC Ry,Rc 9(0/1) — — — — — — — MOVEM.L <ea>,and list — 1+n(n/0) — — 1+n(n/0) — — — MOVEM.L and list,<ea> — 1+n(0/n) — — 1+n(0/n) — — — 3(0/0) — — — — — — — 2(0/1) — NOP PEA <ea> PULSE 2(0/1) 4 5 — 2(0/1) — — 1(0/0) — — — — — — — 3(0/1) STLDSR #imm — — — — — — — 5(0/1) STOP #imm — — — — — — — 3(0/0) 3 TRAP #imm — — — — — — — 15(1/2) TPF 1(0/0) — — — — — — — TPF.W 1(0/0) — — — — — — — TPF.L 1(0/0) — — — — — — — UNLK Ax 2(1/0) — — — — — — — WDDATA <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) — WDEBUG <ea> — 5(2/0) — — 5(2/0) — — — 1The n is the number of registers moved by the MOVEM opcode. a MOVE.W #imm,SR instruction is executed and imm[13] equals 1, the execution time is 1(0/0). 3The execution time for STOP is the time required until the processor begins sampling continuously for interrupts. 4PEA execution times are the same for (d16,PC). 5 PEA execution times are the same for (d8,PC,Xn*SF). 2If 2-30 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.3.5.5 ColdFire Core EMAC Instruction Execution Times Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 2.3.5.6 Table 2-17. EMAC Instruction Execution Times Effective Address Opcode <EA> Rn (An) (An)+ -(An) (d16,An) (d8,An, xxx.wl Xn*SF) #xxx MAC.L Ry, Rx, Raccx 1(0/0) — — — — — — — MAC.L Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)1 — — — MAC.W Ry, Rx, Raccx 1(0/0) — — — — — — — MAC.W Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)1 — — — MOVE.L <ea>y, Raccx 1(0/0) — — — — — — 1(0/0) MOVE.L Raccy,Raccx 1(0/0) — — — — — — — MOVE.L <ea>y, MACSR 5(0/0) — — — — — — 5(0/0) MOVE.L <ea>y, Rmask 4(0/0) — — — — — — 4(0/0) MOVE.L <ea>y,Raccext01 1(0/0) — — — — — — 1(0/0) MOVE.L <ea>y,Raccext23 1(0/0) — — — — — — 1(0/0) MOVE.L Raccx,<ea>x 1(0/0)2 — — — — — — — MOVE.L MACSR,<ea>x 1(0/0) — — — — — — — MOVE.L Rmask, <ea>x 1(0/0) — — — — — — — MOVE.L Raccext01,<ea.x 1(0/0) — — — — — — — MOVE.L Raccext23,<ea>x 1(0/0) — — — — — — — MSAC.L Ry, Rx, Raccx 1(0/0) — — — — — — — MSAC.W Ry, Rx, Raccx 1(0/0) — — — — — — — MSAC.L Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)1 — — — MSAC.W Ry, Rx, <ea>, Rw, Raccx — (1/0) (1/0) (1/0) (1/0)1 — — — MULS.L <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) — — — MULS.W <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) (1/0) (1/0) 4(0/0) MULU.L <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) — — — MULU.W <ea>y, Dx 4(0/0) (1/0) (1/0) (1/0) (1/0) (1/0) (1/0) 4(0/0) 1 2 Effective address of (d16,PC) not supported Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] equals 1---, -11-, --11) Freescale Semiconductor 2-31 ColdFire Core The execution times for moving the contents of the Racc, Raccext[01,23], MACSR, or Rmask into a destination location <ea>x shown in this table represent the best-case scenario when the store instruction is executed and there are no load or M{S}AC instructions in the EMAC execution pipeline. In general, these store operations require only a single cycle for execution, but if preceded immediately by a load, MAC, or MSAC instruction, the depth of the EMAC pipeline is exposed and the execution time is four cycles. 2.3.5.7 Branch Instruction Execution Times Table 2-18. General Branch Instruction Execution Times Effective Address Opcode <EA> Rn (An) (An)+ -(An) (d16,An) (d16,PC) (d8,An,Xi*SF) (d8,PC,Xi*SF) xxx.wl #xxx BRA — — — — 2(0/1) — — — BSR — — — — 3(0/1) — — — JMP <ea> — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) — JSR <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) — RTE — — 10(2/0) — — — — — RTS — — 5(1/0) — — — — — Table 2-19. Bcc Instruction Execution Times 2-32 Opcode Forward Taken Forward Not Taken Backward Taken Backward Not Taken Bcc 3(0/0) 1(0/0) 2(0/0) 3(0/0) Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NOTE 3.1 Introduction This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors. 3.1.1 Overview The EMAC design provides a set of DSP operations that can improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture. The MAC provides functionality in three related areas: 1. Signed and unsigned integer multiplication 2. Multiply-accumulate operations supporting signed and unsigned integer operands as well as signed, fixed-point, and fractional operands 3. Miscellaneous register operations The ColdFire family supports two MAC implementations with different performance levels and capabilities. The original MAC features a three-stage execution pipeline optimized for 16-bit operands, with a 16x16 multiply array and a single 32-bit accumulator. The EMAC features a four-stage pipeline optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit accumulators. The first ColdFire MAC supported signed and unsigned integer operands and was optimized for 16x16 operations, such as those found in applications including servo control and image compression. As ColdFire-based systems proliferated, the desire for more precision on input operands increased. The result was an improved ColdFire MAC with user-programmable control to optionally enable use of fractional input operands. EMAC improvements target three primary areas: • Improved performance of 32 × 32 multiply operation. • Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges between the accumulator and the pipeline’s general-purpose registers • A 48-bit accumulation data path to allow a 40-bit product, plus 8 extension bits increase the dynamic number range when implementing signal processing algorithms The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module (Figure 3-1). Freescale Semiconductor 3-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC) Operand Y Operand X X Shift 0,1,-1 +/- Accumulator(s) Figure 3-1. Multiply-Accumulate Functionality Diagram 3.1.1.1 Introduction to the MAC The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond scope of any processor architecture and may require full DSP implementation. To balance speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for single-cycle pipelined operations with a possible accumulation after product generation. This functionality is common in many signal processing applications. The ColdFire core architecture is also modified to allow an operand to be fetched in parallel with a multiply, increasing overall performance for certain DSP operations. Consider a typical filtering operation where the filter is defined as in Equation 3-1. N–1 y(i) = N–1 ∑ a ( k )y ( i – k ) + ∑ b ( k )x ( i – k ) k=1 Eqn. 3-1 k=0 Here, the output y(i) is determined by past output values and past input values. This is the general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies and product summing. To show this point, reduce Equation 3-1 to a simple, four-tap FIR filter, shown in Equation 3-2, in which the accumulated sum is a past data values and coefficients sum. 3 y(i) = ∑ b ( k )x ( i – k ) = b ( 0 )x ( i ) + b ( 1 )x ( i – 1 ) + b ( 2 )x ( i – 2 ) + b ( 3 )x ( i – 3 ) Eqn. 3-2 k=0 3-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) Enhanced Multiply-Accumulate Unit (EMAC) Memory Map/Register Definition The following table and sections explain the MAC registers: Table 3-1. EMAC Memory Map BDM1 1 Register Width (bits) Access Reset Value Section/Page 0x804 MAC Status Register (MACSR) 32 R/W 0x0000_0000 3.2.1/3-3 0x805 MAC Address Mask Register (MASK) 32 R/W 0xFFFF_FFFF 3.2.2/3-5 0x806 MAC Accumulator 0 (ACC0) 32 R/W Undefined 3.2.3/3-6 0x807 MAC Accumulator 0,1 Extension Bytes (ACCext01) 32 R/W Undefined 3.2.4/3-7 0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23) 32 R/W Undefined 3.2.4/3-7 0x809 MAC Accumulator 1 (ACC1) 32 R/W Undefined 3.2.3/3-6 0x80A MAC Accumulator 2 (ACC2) 32 R/W Undefined 3.2.3/3-6 0x80B MAC Accumulator 3 (ACC3) 32 R/W Undefined 3.2.3/3-6 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 43, “Debug Module.” 3.2.1 MAC Status Register (MACSR) The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags. Operational mode bits control whether operands are signed or unsigned and whether they are treated as integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding is performed. Negative, zero, and multiple overflow condition flags are also provided. BDM: 0x804 (MACSR) Access: Supervisor read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 8 PAVn 7 6 OMC S/U Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 F/I R/T N Z V EV 0 0 0 0 0 0 Figure 3-2. MAC Status Register (MACSR) Table 3-2. MACSR Field Descriptions Field Description 31–12 Reserved, must be cleared. 11–8 PAVn Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator forms the general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR instruction or the accumulator is loaded directly. Bit 11: Accumulator 3 ... Bit 8: Accumulator 0 Freescale Semiconductor 3-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 3.2 Enhanced Multiply-Accumulate Unit (EMAC) 3-4 Field Description 7 OMC Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set to the appropriate constant (see S/U field description) on any operation that overflows the accumulator. After saturation, the accumulator remains unaffected by any other MAC or MSAC instructions until the overflow bit is cleared or the accumulator is directly loaded. 6 S/U Signed/unsigned operations. In integer mode: S/U determines whether operations performed are signed or unsigned. It also determines the accumulator value during saturation, if enabled. 0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive (0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the product value that overflowed. 1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest value (0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction. In fractional mode: S/U controls rounding while storing an accumulator to a general-purpose register. 0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose register as a 32-bit value. 1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to a general-purpose register. See Section 3.3.1.1, “Rounding”. The resulting 16-bit value is stored in the lower word of the destination register. The upper word is zero-filled. This rounding procedure does not affect the accumulator value. 5 F/I Fractional/integer mode. Determines whether input operands are treated as fractions or integers. 0 Integers can be represented in signed or unsigned notation, depending on the value of S/U. 1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to 1 - 2-15 for 16-bit fractions and -1 to 1 - 2-31 for 32-bit fractions. See Section 3.3.4, “Data Representation." 4 R/T Round/truncate mode. Controls rounding procedure for move.l ACCx,Rx, or MSAC.L instructions when in fractional mode. 0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator. Additionally, when a store accumulator instruction is executed (move.l ACCx,Rx), the 8 lsbs of the 48-bit accumulator logic are truncated. 1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest 40-bit value. If the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to the nearest even (lsb = 0) value. See Section 3.3.1.1, “Rounding”. Additionally, when a store accumulator instruction is executed (move.l ACCx,Rx), the lsbs of the 48-bit accumulator logic round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared and MACSR[R/T] is set, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction. 3 N Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. 2 Z Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 3-2. MACSR Field Descriptions (continued) Enhanced Multiply-Accumulate Unit (EMAC) Field Description 1 V Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction, indicating that the result cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC operation and uses the appropriate PAVn flag in the next-state V evaluation. 0 EV Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode or the 40 lsbs in fractional mode of the destination accumulator. However, the result remains accurately represented in the combined 48-bit accumulator structure. Although an overflow has occurred, the correct result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSAC operations may return the accumulator to a valid 32/40-bit result. Table 3-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits. Table 3-3. Summary of S/U, F/I, and R/T Control Bits 3.2.2 S/U F/I R/T Operational Modes 0 0 x Signed, integer 0 1 0 Signed, fractional Truncate on MAC.L and MSAC.L No round on accumulator stores 0 1 1 Signed, fractional Round on MAC.L and MSAC.L Round-to-32-bits on accumulator stores 1 0 x Unsigned, integer 1 1 0 Signed, fractional Truncate on MAC.L and MSAC.L Round-to-16-bits on accumulator stores 1 1 1 Signed, fractional Round on MAC.L and MSAC.L Round-to-16-bits on accumulator stores Mask Register (MASK) The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones. This register performs a simple AND with the operand address for MAC instructions. The processor calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address can be constrained to a certain memory region. This is used primarily to implement circular queues with the (An)+ addressing mode. This minimizes the addressing support required for filtering, convolution, or any routine that implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows: mac.sz Ry,RxSF,<ea>yand ,Rw Freescale Semiconductor 3-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 3-2. MACSR Field Descriptions (continued) The and operator enables the MASK use and causes bit 5 of the extension word to be set. The exact algorithm for the use of MASK is: if extension word, bit [5] = 1, the MASK bit, then if <ea> = (An) oa = An and {0xFFFF, MASK} if <ea> = (An)+ oa = An An = (An + 4) and {0xFFFF, MASK} if <ea> =-(An) oa = (An - 4) and An = (An - 4) and {0xFFFF, MASK} {0xFFFF, MASK} if <ea> = (d16,An) oa = (An + se_d16) and {0xFFFF0x, MASK} Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also shown. Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations. BDM: 0x805 (MASK) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 W 8 7 6 5 4 3 2 1 0 MASK Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 3-3. Mask Register (MASK) Table 3-4. MASK Field Descriptions Field Description 31–16 Reserved, must be set. 15–0 MASK Performs a simple AND with the operand address for MAC instructions. 3.2.3 Accumulator Registers (ACC0–3) The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers form the entire 48-bit result. 3-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) BDM: 0x806 (ACC0) 0x809 (ACC1) 0x80A (ACC2) 0x80B (ACC3) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 Accumulator W Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 3-4. Accumulator Registers (ACC0–3) Table 3-5. ACC0–3 Field Descriptions Field Description 31–0 Accumulator 3.2.4 Store 32-bits of the result of the MAC operation. Accumulator Extension Registers (ACCext01, ACCext23) Each pair of 8-bit accumulator extension fields are concatenated with the corresponding 32-bit accumulator register to form the 48-bit accumulator. For more information, see Section 3.3, “Functional Description.” BDM: 0x807 (ACCext01) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R ACC0U W ACC0L 8 7 ACC1U 6 5 4 3 2 1 0 ACC1L Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 3-5. Accumulator Extension Register (ACCext01) Table 3-6. ACCext01 Field Descriptions Field Description 31–24 ACC0U Accumulator 0 upper extension byte 23–16 ACC0L Accumulator 0 lower extension byte 15–8 ACC1U Accumulator 1 upper extension byte 7–0 ACC1L Accumulator 1 lower extension byte Freescale Semiconductor 3-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) BDM: 0x808 (ACCext23) Access: User read/write BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R W ACC2U ACC2L 8 7 ACC3U 6 5 4 3 2 1 0 ACC3L Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 3-6. Accumulator Extension Register (ACCext23) Table 3-7. ACCext23 Field Descriptions Field 3.3 Description 31–24 ACC2U Accumulator 2 upper extension byte 23–16 ACC2L Accumulator 2 lower extension byte 15–8 ACC3U Accumulator 3 upper extension byte 7–0 ACC3L Accumulator 3 lower extension byte Functional Description The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC, execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if no MAC hardware is present. The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of the product to or from the value in an accumulator. Optionally, the product may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions. Multiply-accumulate operations support 16- or 32-bit input operands in these formats: • Signed integers • Unsigned integers • Signed, fixed-point, fractional numbers The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the destination accumulator. For fractional operands, the entire 64-bit product is calculated and truncated or rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is combined with the destination accumulator. For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. 3-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) Figure 3-7 and Figure 3-8 show relative alignment of input operands, the full 64-bit product, the resulting 40-bit product used for accumulation, and 48-bit accumulator formats. OperandY X Product 32 OperandX 32 0 23 40 Extended Product 8 40 8 40 + Accumulator 8 Extension Byte Upper [7:0] Accumulator [31:0] Extension Byte Lower [7:0] Figure 3-7. Fractional Alignment X Product OperandY 32 OperandX 32 24 8 32 Extended Product + 8 8 32 Accumulator 8 8 32 Extension Byte Upper [7:0] Accumulator [31:0] Extension Byte Lower [7:0] Figure 3-8. Signed and Unsigned Integer Alignment Therefore, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that each 48-bit accumulator is the concatenation of 16-bit accumulator extension register (ACCextn) contents and 32-bit ACCn contents, the specific definitions are: if MACSR[6:5] == 00 /* signed integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} if MACSR[6:5] == 01 or 11 /* signed fractional mode */ Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6:5] == 10 /* unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects the register. Freescale Semiconductor 3-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC instructions have an effective issue rate of 1 cycle, regardless of input operand size or type. All arithmetic operations use register-based input operands, and summed values are stored in an accumulator. Therefore, an additional MOVE instruction is needed to store data in a general-purpose register. One new feature in EMAC instructions is the ability to choose the upper or lower word of a register as a 16-bit input operand. This is useful in filtering operations if one data register is loaded with the input data and another is loaded with the coefficient. Two 16-bit multiply accumulates can be performed without fetching additional operands between instructions by alternating word choice during calculations. The EMAC has four accumulator registers versus the MAC’s single accumulator. The additional registers improve the performance of some algorithms by minimizing pipeline stalls needed to store an accumulator value back to general-purpose registers. Many algorithms require multiple calculations on a given data set. By applying different accumulators to these calculations, it is often possible to store one accumulator without any stalls while performing operations involving a different destination accumulator. The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP engines. Existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can efficiently move large data blocks by generating line-sized burst references. The ability to load an operand simultaneously from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable. The programming model includes a mask register (MASK), which can optionally be used to generate an operand address during MAC + MOVE instructions. The register application with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands. 3.3.1 Fractional Operation Mode This section describes behavior when the fractional mode is used (MACSR[F/I] is set). 3.3.1.1 Rounding When the processor is in fractional mode, there are two operations during which rounding can occur: 1. Execution of a store accumulator instruction (move.l ACCx,Rx). The lsbs of the 48-bit accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared, the low-order 8 bits round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction. 2. Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero, multiplying two 32-bit numbers creates a 64-bit product truncated to the upper 40 bits; otherwise, it is rounded using round-to-nearest (even) method. To understand the round-to-nearest-even method, consider the following example involving the rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest 16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L. • If R0.L is less than 0x8000, the result is truncated to the value of R0.U. • If R0.L is greater than 0x8000, the upper word is incremented (rounded up). 3-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) • If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on the lsb of R0.U, so the result is always even (lsb = 0). — If the lsb of R0.U equals 1 and R0.L equals 0x8000, the number is rounded up. — If the lsb of R0.U equals 0 and R0.L equals 0x8000, the number is rounded down. This method minimizes rounding bias and creates as statistically correct an answer as possible. The rounding algorithm is summarized in the following pseudocode: if R0.L < 0x8000 then Result = R0.U else if R0.L > 0x8000 then Result = R0.U + 1 else if lsb of R0.U = 0 then Result = R0.U else Result = R0.U + 1 /* R0.L = 0x8000 */ The round-to-nearest-even technique is also known as convergent rounding. 3.3.1.2 Saving and Restoring the EMAC Programming Model The presence of rounding logic in the EMAC output datapath requires special care during the EMAC’s save/restore process. In particular, any result rounding modes must be disabled during the save/restore process so the exact bit-wise contents of the EMAC registers are accessed. Consider the memory structure containing the EMAC programming model: struct macState { int acc0; int acc1; int acc2; int acc3; int accext01; int accext02; int mask; int macsr; } macState; The following assembly language routine shows the proper sequence for a correct EMAC state save. This code assumes all Dn and An registers are available for use, and the memory location of the state save is defined by A7. EMAC_state_save: move.l clr.l move.l move.l move.l move.l move.l move.l move.l move.l movem.l macsr,d7 d0 d0,macsr acc0,d0 acc1,d1 acc2,d2 acc3,d3 accext01,d4 accext23,d5 mask,d6 #0x00ff,(a7) ; ; ; ; save the macsr zero the register to ... disable rounding in the macsr save the accumulators ; save the accumulator extensions ; save the address mask ; move the state to memory This code performs the EMAC state restore: EMAC_state_restore: Freescale Semiconductor 3-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) movem.l move.l move.l move.l move.l move.l move.l move.l move.l move.l (a7),#0x00ff #0,macsr d0,acc0 d1,acc1 d2,acc2 d3,acc3 d4,accext01 d5,accext23 d6,mask d7,macsr ; restore the state from memory ; disable rounding in the macsr ; restore the accumulators ; restore the accumulator extensions ; restore the address mask ; restore the macsr Executing this sequence type can correctly save and restore the exact state of the EMAC programming model. 3.3.1.3 MULS/MULU MULS and MULU are unaffected by fractional-mode operation; operands remain assumed to be integers. 3.3.1.4 Scale Factor in MAC or MSAC Instructions The scale factor is ignored while the MAC is in fractional mode. 3.3.2 EMAC Instruction Set Summary Table 3-8 summarizes EMAC unit instructions. Table 3-8. EMAC Instruction Summary Command Mnemonic Description Multiply Signed muls <ea>y,Dx Multiplies two signed operands yielding a signed result Multiply Unsigned mulu <ea>y,Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate mac Ry,RxSF,ACCx msac Ry,RxSF,ACCx Multiplies two operands and adds/subtracts the product to/from an accumulator Multiply Accumulate with Load mac Ry,Rx,<ea>y,Rw,ACCx msac Ry,Rx,<ea>y,Rw,ACCx Multiplies two operands and combines the product to an accumulator while loading a register with the memory operand Load Accumulator move.l {Ry,#imm},ACCx Loads an accumulator with a 32-bit operand Store Accumulator move.l ACCx,Rx Writes the contents of an accumulator to a CPU register Copy Accumulator move.l ACCy,ACCx Copies a 48-bit accumulator Load MACSR move.l {Ry,#imm},MACSR Writes a value to MACSR Store MACSR move.l MACSR,Rx Write the contents of MACSR to a CPU register Store MACSR to CCR move.l MACSR,CCR Write the contents of MACSR to the CCR Load MAC Mask Reg move.l {Ry,#imm},MASK Writes a value to the MASK register Store MAC Mask Reg move.l MASK,Rx Writes the contents of the MASK to a CPU register Load Accumulator Extensions 01 move.l {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit operand 3-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) Enhanced Multiply-Accumulate Unit (EMAC) Command Mnemonic Description Load Accumulator Extensions 23 move.l {Ry,#imm},ACCext23 Loads the accumulator 2,3 extension bytes with a 32-bit operand Store Accumulator Extensions 01 move.l ACCext01,Rx Writes the contents of accumulator 0,1 extension bytes into a CPU register Store Accumulator Extensions 23 move.l ACCext23,Rx Writes the contents of accumulator 2,3 extension bytes into a CPU register 3.3.3 EMAC Instruction Execution Times The instruction execution times for the EMAC can be found in Section 2.3.5.6, “EMAC Instruction Execution Times”. The EMAC execution pipeline overlaps the AGEX stage of the OEP (the first stage of the EMAC pipeline is the last stage of the basic OEP). EMAC units are designed for sustained, fully-pipelined operation on accumulator load, copy, and multiply-accumulate instructions. However, instructions that store contents of the multiply-accumulate programming model can generate OEP stalls that expose the EMAC execution pipeline depth: mac.w Ry, Rx, Acc0 move.l Acc0, Rz The MOVE.L instruction that stores the accumulator to an integer register (Rz) stalls until the program-visible copy of the accumulator is available. Figure 3-9 shows EMAC timing. Three-cycle regBusy stall move mac DSOC move AGEX mac move EMAC EX1 mac move mac EMAC EX2 mac EMAC EX3 mac EMAC EX4 Accumulator 0 old new Figure 3-9. EMAC-Specific OEP Sequence Stall In Figure 3-9, the OEP stalls the store-accumulator instruction for three cycles: the EMAC pipleline depth minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the recently updated accumulator 0 value is available. Freescale Semiconductor 3-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 3-8. EMAC Instruction Summary (continued) As with change or use stalls between accumulators and general-purpose registers, introducing intervening instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC instruction stalls. A major benefit of the EMAC is the addition of three accumulators to minimize stalls caused by exchanges between accumulator(s) and general-purpose registers. 3.3.4 Data Representation MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand type: 1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2(N-1) < operand < 2(N-1) - 1. The binary point is right of the lsb. 2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N - 1. The binary point is right of the lsb. 3. Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number, aN-1aN-2aN-3... a2a1a0, its value is given by the equation in Equation 3-3. N–2 value = – ( 1 ⋅ a N – 1 ) + ∑2 –( i + 1 – N ) ⋅ ai Eqn. 3-3 i=0 This format can represent numbers in the range -1 < operand < 1 - 2(N-1). For words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2-15); the most positive longword is 0x7FFF_FFFF or (1 - 2-31). 3.3.5 MAC Opcodes MAC opcodes are described in the ColdFire Programmer’s Reference Manual. Remember the following: • Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that involves the product and the accumulator. • The overflow (V) flag is managed differently. It is set if the complete product cannot be represented as a 40-bit value (this applies to 32 × 32 integer operations only) or if the combination of the product with an accumulator cannot be represented in the given number of bits. The EMAC design includes an additional product/accumulation overflow bit for each accumulator that are treated as sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction. See Section 3.2.1, “MAC Status Register (MACSR)”. • For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator) and MSAC (multiply and subtract from accumulator) instructions does not include a reference to the single accumulator. For the EMAC, assemblers support this syntax and no explicit reference to an accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the destination accumulator is explicitly defined. 3-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) • The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because a product can overflow, the following guidelines are implemented: — For unsigned word and longword operations, a zero is shifted into the product on right shifts. — For signed, word operations, the sign bit is shifted into the product on right shifts unless the product is zero. For signed, longword operations, the sign bit is shifted into the product unless an overflow occurs or the product is zero, in which case a zero is shifted in. — For all left shifts, a zero is inserted into the lsb position. The following pseudocode explains basic MAC or MSAC instruction functionality. This example is presented as a case statement covering the three basic operating modes with signed integers, unsigned integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {}, indicates a concatenation operation. switch (MACSR[6:5]) /* MACSR[S/U, F/I] */ { case 0: /* signed integers */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) then { MACSR.PAVn = 0 /* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]} else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]} if (U/Lx == 1) then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]} else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]} } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0] /* check for product overflow */ if ((product[63:39] != 0x0000_00_0) and and (product[63:39] != 0xffff_ff_1)) then { /* product overflow */ MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC and and MACSR.OMC == 1) then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff } Freescale Semiconductor 3-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) /* sign-extend to 48 bits before performing any scaling */ product[47:40] = {8{product[39]}} /* sign-extend */ /* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* SF = “>> 1” */ product[39:0] = {product[39], product[39:1]} break; } if (MACSR.PAVn == 0) then {if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0] } /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVn = 1 MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 } /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1)) then MACSR.EV = 0 else MACSR.EV = 1 break; case 1,3: /* signed fractionals */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) then { MACSR.PAVn = 0 if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000} if (U/Lx == 1) 3-16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) Enhanced Multiply-Accumulate Unit (EMAC) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 then operandX[31:0] = {Rx[31:16], 0x0000} else operandX[31:0] = {Rx[15:0], 0x0000} } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1 /* check for product rounding */ if (MACSR.R/T == 1) then { /* perform convergent rounding */ if (product[23:0] > 0x80_0000) then product[63:24] = product[63:24] + 1 else if ((product[23:0] == 0x80_0000) and and (product[24] == 1)) then product[63:24] = product[63:24] + 1 } /* sign-extend to 48 bits and combine with accumulator */ /* check for the -1 * -1 overflow case */ if ((operandY[31:0] == 0x8000_0000) and and (operandX[31:0] == 0x8000_0000)) then product[71:64] = 0x00 /* zero-fill */ else product[71:64] = {8{product[63]}} /* sign-extend */ if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[71:24] else result[47:0] = ACCx[47:0] + product[71:24] /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVn = 1 MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000 } /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1)) then MACSR.EV = 0 else MACSR.EV = 1 break; case 2: /* unsigned integers */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) then { MACSR.PAVn = 0 /* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/Lx == 1) Freescale Semiconductor 3-17 Enhanced Multiply-Accumulate Unit (EMAC) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 then operandX[31:0] = {0x0000, Rx[31:16]} else operandX[31:0] = {0x0000, Rx[15:0]} } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0] /* check for product overflow */ if (product[63:40] != 0x0000_00) then { /* product overflow */ MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC and and MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ result[47:0] = 0xffff_ffff_ffff } /* zero-fill to 48 bits before performing any scaling */ product[47:40] = 0 /* zero-fill upper byte */ /* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* SF = “>> 1” */ product[39:0] = {0, product[39:1]} break; } /* combine with accumulator */ if (MACSR.PAVn == 0) then {if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0] } /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC and and MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ 3-18 Freescale Semiconductor } /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 } break; Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) result[47:0] = 0xffff_ffff_ffff 3-19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Enhanced Multiply-Accumulate Unit (EMAC) 3-20 Freescale Semiconductor 4.1 Introduction This chapter describes cache operation on the ColdFire processor. 4.1.1 Features Features include the following: • Configurable as instruction, data, or split instruction/data cache • 2-Kbyte direct-mapped cache • Single-cycle access on cache hits • Physically located on the ColdFire core's high-speed local bus • Nonblocking design to maximize performance • Separate instruction and data 16-Byte line-fill buffers • Configurable instruction cache miss-fetch algorithm 4.1.2 Introduction The cache is a direct-mapped, single-cycle memory. It may be configured as an instruction cache, a write-through data cache, or a split instruction/data cache. The cache storage is organized as 128 lines, each containing 16 bytes. The memory storage consists of a 128-entry tag array (containing addresses and a valid bit), and a data array containing 2 Kbytes, organized as 512 × 32 bits. Cache configuration is controlled by bits in the cache control register (CACR), detailed later in this chapter. For the instruction or data-only configurations, only the associated instruction or data line-fill buffer is used. For the split cache configuration, one-half of the tag and storage arrays is used for an instruction cache and one-half is used for a data cache. The split cache configuration uses the instruction and the data line-fill buffers. The core’s local bus is a unified bus used for instruction and data fetches. Therefore, the cache can have only one fetch, instruction or data, active at one time. For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in parallel: fetch address bits [10:4] addressing the tag array, and fetch address bits [10:2] addressing the storage array. For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [9:4] provide the rest of the tag array address. The tag array outputs the address mapped to the given cache location along with the valid bit for the line. This address field is compared to bits [31:11] for instructionor data-only configurations and to bits [31:10] for a split configuration of the fetch address from the local bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the Freescale Semiconductor 4-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 4 Cache output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access in a single cycle. The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded into the cache. The cache also contains separate 16-byte instruction and data line-fill buffers that provide temporary storage for the last line fetched in response to a cache miss. With each fetch, the contents of the associated line fill buffer are examined. Thus, each fetch address examines the tag memory array and the associated line fill buffer to see if the desired address is mapped into either hardware resource. A cache hit in the memory array or the associated line-fill buffer is serviced in a single cycle. Because the line fill buffer maintains valid bits on a longword basis, hits in the buffer can be serviced immediately without waiting for the entire line to be fetched. If the referenced address is not contained in the memory array or the associated line-fill buffer, the cache initiates the required external fetch operation. In most situations, this is a 16-byte line-sized burst reference. The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is released after the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer. External Data[31:0] Local Address Bus 31 10 43 2 1 0 31 4 I or D Line Buffer Storage Data Index Tag Index I or D Line Buffer Address = MUX Fill Hit 31 11 TAG VALID 0 31 0 0 DATA 511 127 = MUX Tag Hit Local Data Bus Figure 4-1. 2-Kbyte Cache Block Diagram 4.2 Memory Map/Register Definition Three supervisor registers define the operation of the cache and local bus controller: the cache control register (CACR) and two access control registers (ACR0, ACR1). Table 4-1 below shows the memory map 4-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Cache of these registers. The CACR and ACRs can only be accessed in supervisor mode using the MOVEC instruction with an Rc value of 0x002, 0x004 and 0x005, respectively. Table 4-1. Cache Memory Map BDM1 Register Width (bits) Access2 Reset Value Section/Page 0x002 Cache Control Register (CACR) 32 W 0x0000_0000 4.2.1/4-3 0x004 Access Control Register 0 (ACR0) 32 W See Section 4.2.2/4-6 0x005 Access Control Register 1 (ACR1) 32 W See Section 4.2.2/4-6 1 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 30, “Debug Support.” 2 Readable through debug. 4.2.1 Cache Control Register (CACR) The CACR controls the operation of the cache. The CACR provides a set of default memory access attributes used when a reference address does not map into the spaces defined by the ACRs. The CACR is a 32-bit, write-only supervisor control register. It is accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in background debug mode (BDM). Therefore, the register diagram, Figure 4-2, is shown as read/write. At system reset, the entire register is cleared. BDM: 0x002 (CACR) 31 R W Reset R Access: Supervisor write-only Debug read/write 30 29 0 0 0 0 0 0 15 14 13 0 0 0 0 0 0 CENB 28 27 26 25 0 0 0 0 12 11 10 0 0 0 0 CPD CFRZ W Reset 24 22 21 20 CINV DISI DISD INVI INVD 0 0 0 0 0 0 9 8 5 4 CEIB DCM DBWE 0 23 0 0 7 6 0 0 0 0 DWP EUSP 0 0 19 18 17 16 0 0 0 0 0 0 0 0 1 0 3 2 0 0 0 0 CLNF 0 0 Figure 4-2. Cache Control Register (CACR) Table 4-2. CACR Field Descriptions Field Description 31 CENB Cache enable. The memory array of the cache is enabled only if CENB is asserted. This bit, along with the DISI (disable instruction caching) and DISD (disable data caching) bits, control the cache configuration. 0 Cache disabled 1 Cache enabled Table 4-3 describes cache configuration. 30–29 Reserved, must be cleared. Freescale Semiconductor 4-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Cache Cache Field Description 28 CPDI Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry defined by bits [10:4] of the address is invalidated if CPDI is cleared. If CPDI is set, no operation is performed. 0 Enable invalidation 1 Disable invalidation 27 CFRZ Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten. If a given cache location is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ is asserted. 0 Normal Operation 1 Freeze valid cache lines 26–25 Reserved, must be cleared. 24 CINV Cache invalidate. The cache invalidate operation is not a function of the CENB state (this operation is independent of the cache being enabled or disabled). Setting this bit forces the cache to invalidate all, half, or none of the tag array entries depending on the state of the DISI, DISD, INVI, and INVD bits. The invalidation process requires several cycles of overhead plus 128 machine cycles to clear all tag array entries and 64 cycles to clear half of the tag array entries, with a single cache entry cleared per machine cycle. The state of this bit is always read as a zero. After a hardware reset, the cache must be invalidated before it is enabled. 0 No operation 1 Invalidate all cache locations Table 4-4 describes how to set the cache invalidate all bit. 23 DISI Disable instruction caching. When set, this bit disables instruction caching. This bit, along with the CENB (cache enable) and DISD (disable data caching) bits, control the cache configuration. See the CENB definition for a detailed description. 0 Enable instruction caching 1 Disable instruction caching Table 4-3 describes cache configuration and Table 4-4 describes how to set the cache invalidate all bit. 22 DISD Disable data caching. When set, this bit disables data caching. This bit, along with the CENB (cache enable) and DISI (disable instruction caching) bits, control the cache configuration. See the CENB definition for a detailed description. 0 Enable data caching 1 Disable data caching Table 4-3 describes cache configuration and Table 4-4 describes how to set the cache invalidate all bit. 21 INVI CINV instruction cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split cache configuration, this bit is part of the control for the invalidate all operation. See the CINV definition for a detailed description Table 4-4 describes how to set the cache invalidate all bit. 20 INVD CINV data cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split cache configuration, this bit is part of the control for the invalidate all operation. See the CINV definition for a detailed description Table 4-4 describes how to set the cache invalidate all bit. 19–11 Reserved, must be cleared. 10 CEIB Cache enable non-cacheable instruction bursting. Setting this bit enables the line-fill buffer to be loaded with burst transfers under control of CLNF[1:0] for non-cacheable accesses. Non-cacheable accesses are never written into the memory array. See Table 4-7. 0 Disable burst fetches on non-cacheable accesses 1 Enable burst fetches on non-cacheable accesses 4-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 4-2. CACR Field Descriptions (continued) Cache Field Description 9 DCM Default cache mode. This bit defines the default cache mode. For more information on the selection of the effective memory attributes, see Section 4.3.2, “Memory Reference Attributes. 0 Caching enabled 1 Caching disabled 8 DBWE Default buffered write enable. This bit defines the default value for enabling buffered writes. If DBWE = 0, the termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and the operation buffered in the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and the external bus. Generally, enabled buffered writes provide higher system performance but recovery from access errors can be more difficult. For the ColdFire core, reporting access errors on operand writes is always imprecise and enabling buffered writes further decouples the write instruction and the signaling of the fault 0 Disable buffered writes 1 Enable buffered writes 7–6 Reserved, must be cleared. 5 DWP Default write protection 0 Read and write accesses permitted 1 Only read accesses permitted 4 EUSP Enable user stack pointer. See Section 2.2.3, “Supervisor/User Stack Pointers (A7 and OTHER_A7)”for more information on the dual stack pointer implementation. 0 Disable the processor’s use of the User Stack Pointer 1 Enable the processor’s use of the User Stack Pointer 3–2 1–0 CLNF Reserved, must be cleared. Cache line fill. These bits control the size of the memory request the cache issues to the bus controller for different initial instruction line access offsets. See Table 4-6 for external fetch size based on miss address and CLNF. Table 4-3 shows the relationship between CACR[CENB, DISI, & DISD] bits and the cache configuration. Table 4-3. Cache Configuration as Defined by CACR CACR [CENB] CACR [DISI] CACR [DISD] Configuration 0 x x N/A 1 0 0 Split Instruction/ Data Cache 1 KByte direct-mapped instruction cache (uses upper half of tag and storage arrays) and 1 KByte direct-mapped write-through data cache (uses lower half of tag and storage arrays) 1 0 1 Instruction Cache 2 KByte direct-mapped instruction cache (uses all of tag and storage arrays) 1 1 0 Data Cache Description Cache is completely disabled 2 KByte direct-mapped write-through data cache (uses all of tag and storage arrays) Table 4-4 shows the relationship between CACR[DISI, DISD, INVI, & INVD] and setting the cache invalidate all bit (CACR[CINV]). Freescale Semiconductor 4-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 4-2. CACR Field Descriptions (continued) Cache 4.2.2 CACR [DISI] CACR [DISD] CACR [INVI] CACR [INVD] 0 0 0 0 Split Instruction/ Data Cache Invalidate all entries in 1-KByte instruction cache and 1-KByte data cache 0 0 0 1 Split Instruction/ Data Cache Invalidate only 1 KByte data cache 0 0 1 0 Split Instruction Data Cache Invalidate only 1 KByte instruction cache 0 0 1 1 Split Instruction/ Data Cache No invalidate 1 0 x x Instruction Cache Invalidate 2 KByte instruction cache 0 1 x x Data Cache Invalidate 2 KByte data cache Configuration Operation Access Control Registers (ACR0, ACR1) The ACRs provide a definition of memory reference attributes for two memory regions (one per ACR). This set of effective attributes is defined for every memory reference using the ACRs or the set of default attributes contained in the CACR. The ACRs are examined for every processor memory reference not mapped to the flash or SRAM memories. The ACRs are 32-bit, write-only supervisor control register. They are accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be read when in background debug mode (BDM). Therefore, the register diagram, Figure 4-3, is shown as read/write. At system reset, both registers are disabled with ACRn[EN] cleared. NOTE IPSBAR space should not be cached. The combination of the CACR defaults and the two ACRn registers must define the non-cacheable attribute for this address space. BDM: 0x004 (ACR0) 0x005 (ACR1) Access: Supervisor write-only BDM read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R W AB AM Reset – – – – – – – – – – – – – – – – EN 0 14 13 SM – – 12 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 0 0 6 5 CM BWE – – 4 3 0 0 0 0 2 WP – 1 0 0 0 0 0 Figure 4-3. Access Control Registers (ACRn) 4-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 4-4. Cache Invalidate All as Defined by CACR Cache Field Description 31–24 AB Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the ACR address mask. If the address matches, the attributes for the memory reference are sourced from the given ACR. 23–16 AM Address mask. Masks any AB bit. If a bit in the AM field is set, the corresponding bit of the address field comparison is ignored. 15 EN ACR Enable. Hardware reset clears this bit, disabling the ACR. 0 ACR disabled 1 ACR enabled 14–13 SM Supervisor mode. Allows the given ACR to be applied to references based on operating privilege mode of the ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses. 00 Match if user mode 01 Match if supervisor mode 1x Match always—ignore user/supervisor mode 12–7 Reserved, must be cleared. 6 CM 5 BWE Cache mode. 0 Caching enabled 1 Caching disabled Buffered write enable. Defines the value for enabling buffered writes. If BWE is cleared, the termination of an operand write cycle on the processor's local bus is delayed until the system bus cycle is completed. Setting BWE terminates the write cycle on the local bus immediately and the operation is then buffered in the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and the system bus. Generally, the enabling of buffered writes provides higher system performance but recovery from access errors may be more difficult. For the V2 ColdFire core, the reporting of access errors on operand writes is always imprecise, and enabling buffered writes simply decouples the write instruction from the signaling of the fault even more. 0 Writes are not buffered. 1 Writes are buffered. 4–3 Reserved, must be cleared. 2 WP Write protect. Defines the write-protection attribute. If the effective memory attributes for a given access select the WP bit, an access error terminates any attempted write with this bit set. 0 Read and write accesses permitted 1 Only read accesses permitted 1–0 Reserved, must be cleared. 4.3 Functional Description The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's memory references appear as supervisor data accesses but the unit can be programmed to generate user-mode accesses and/or instruction fetches. The cache processes any fetch access in the normal manner. 4.3.1 Interaction with Other Modules Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous fetch processing. Freescale Semiconductor 4-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 4-5. ACRn Field Descriptions If the referenced address is mapped into the SRAM module, that module services the request in a single cycle. In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion. 4.3.2 Memory Reference Attributes For every memory reference the ColdFire core or the debug module generates, a set of effective attributes is determined based on the address and the access control registers (ACRs). This set of attributes includes the cacheable/non-cacheable definition, the precise/imprecise handling of operand write, and the write-protect capability. In particular, each address is compared to the values programmed in the ACRs. If the address matches one of the ACR values, the access attributes from that ACR are applied to the reference. If the address does not match either ACR, then the default value defined in the cache control register (CACR) is used. The specific algorithm is as follows: if (address == ACR0_address including mask) Effective Attributes = ACR0 attributes else if (address == ACR1_address including mask) Effective Attributes = ACR1 attributes else Effective Attributes = CACR default attributes 4.3.3 Cache Coherency and Invalidation The cache does not monitor data references for accesses to cached instructions. Therefore, software must maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code segments if instructions are cached. The cache invalidation can be performed in several ways. For the instruction- or data-only configurations, setting CACR[CINV] forces the entire cache to be marked as invalid. The invalidation operation requires 128 cycles because the cache sequences through the entire tag array, clearing a single location each cycle. For the split configuration, CACR[INVI] and CACR[INVD] can be used in addition to CACR[CINV] to clear the entire cache, only the instruction half, or only the data half. Any subsequent fetch accesses are postponed until the invalidation sequence is complete. The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed, the cache entry defined by bits [10:4] of the source address register is invalidated, provided CACR[CPDI] is cleared. For the split data/instruction cache configuration, software directly controls bit 10 that selects whether an instruction cache or data cache line is being accessed. These invalidation operations can be initiated from the ColdFire core or the debug module. 4.3.4 Reset A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[CINV] before the cache can be enabled. 4-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Cache Cache Cache Miss Fetch Algorithm/Line Fills As discussed in Section 4.1.2, “Introduction,” the cache hardware includes a 16-byte, line-fill buffer for providing temporary storage for the last fetched line. With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in the tag memory and the line-fill buffer generates an external fetch. For data misses, the size of the external fetch is always 16 bytes. For instruction misses, the size of the external fetch is determined by the value contained in the 2-bit CLNF field of the CACR and the miss address. Table 4-6 shows the relationship between the CLNF bits, the miss address, and the size of the external fetch. Table 4-6. Initial Fetch Offset vs. CLNF Bits Longword Address Bits[3:2] CLNF[1:0] 00 01 10 11 00 Line Line Line Longword 01 Line Line Longword Longword 1X Line Line Line Line Depending on the runtime characteristics of the application and the memory response speed, overall performance may be increased by programming the CLNF bits to values 00 or 01. For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is accessed first followed by the remaining three longwords that are accessed by incrementing the longword address in a modulo-16 fashion as shown below: if miss address[3:2] = 00 fetch sequence = 0x0, 0x4, 0x8, 0xC if miss address[3:2] = 01 fetch sequence = 0x4, 0x8, 0xC, 0x0 if miss address[3:2] = 10 fetch sequence = 0x8, 0xC, 0x0, 0x4 if miss address[3:2] = 11 fetch sequence = 0xC, 0x0, 0x4, 0x8 After an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache maintains a special most-recently-used indicator that tracks the contents of the associated line-fill buffer versus its corresponding cache location. At the time of the miss, the hardware indicator is set, marking the line-fill buffer as most recently used. If a subsequent access occurs to the cache location defined by bits [10:4] (or bits [9:4] for split configurations of the fill buffer address), the data in the cache memory array is now most recently used, so the hardware indicator is cleared. In all cases, the indicator defines whether the contents of the line-fill buffer or the memory data array are most recently used. At the time of the next cache miss, the contents of the line-fill buffer are written into the memory array if the entire line is present, and the line-fill buffer data is most recently used compared to the memory array. Generally, longword references are used for sequential instruction fetches. If the processor branches to an odd word address, a word-sized instruction fetch is generated. Freescale Semiconductor 4-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 4.3.5 For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable references under control of CACR[CEIB]. With this bit set, a non-cacheable instruction fetch is processed, as defined by Table 4-7. For this condition, the line-fill buffer is loaded and subsequent references can hit in the buffer, but the data is never loaded into the memory array. Table 4-7 shows the relationship between CACR bits CENB and CEIB and the type of instruction fetch. Table 4-7. Instruction Cache Operation as Defined by CACR 4-10 CACR [CENB] CACR [CEIB] Type of Instruction Fetch 0 0 N/A Cache is completely disabled; all instruction fetches are word or longword in size. 0 1 N/A All instruction fetches are word or longword in size 1 X Cacheable 1 0 Non-cacheable All instruction fetches are word or longword in size, and not loaded into the line-fill buffer 1 1 Non-cacheable Instruction fetch size is defined by Table 4-6 and loaded into the line-fill buffer, but are never written into the memory array. Description Fetch size is defined by Table 4-6 and contents of the line-fill buffer can be written into the memory array Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Cache 5.1 • • • • • 5.2 SRAM Features One 64-Kbyte SRAM Single-cycle access Physically located on processor's high-speed local bus Memory location programmable on any 0-modulo-64 Kbyte address Byte, word, longword address capabilities SRAM Operation The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-64K address within the 4-GByte address space. The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can service processor-initiated access or memory-referencing commands from the debug module. Depending on configuration information, instruction fetches may be sent to both the cache and the SRAM block simultaneously. If the reference is mapped into the region defined by the SRAM, the SRAM provides the data back to the processor, and the cache data discarded. Accesses from the SRAM module are not cached. The SRAM is dual-ported to provide DMA access. The SRAM is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master. See Chapter 8, “System Control Module (SCM)” for more information. 5.3 SRAM Programming Model The SRAM programming model includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management. 5.3.1 SRAM Base Address Register (RAMBAR) The configuration information in the SRAM base address register (RAMBAR) controls the operation of the SRAM module. • The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only access to this register. • The RAMBAR can be read or written from the debug module in a similar manner. • All undefined bits in the register are reserved. These bits are ignored during writes to the RAMBAR, and return zeroes when read from the debug module. • The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are unaffected. Freescale Semiconductor 5-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 5 Static RAM (SRAM) Static RAM (SRAM) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Reset Undefined R/W W 15 14 Field 13 — 12 11 10 9 8 PRI1 PRI2 SPV Reset 7 WP 6 — 5 4 3 2 1 0 C/I SC SD UC UD V Undefined R/W 0 W Address CPU + 0xC05 Figure 5-1. SRAM Base Address Register (RAMBAR) Table 5-1. SRAM Base Address Register Bits Name Description 31–16 BA Base address. Defines the 0-modulo-64K base address of the SRAM module. By programming this field, the SRAM may be located on any 64-Kbyte boundary within the processor’s 4-Gbyte address space. 15–12 — Reserved, should be cleared. 11–10 PRI1, PRI2 Priority bit. PRI1 determines if DMA or CPU has priority in upper 32k bank of memory. PRI2 determines if DMA or CPU has priority in lower 32k bank of memory. If bit is set, CPU has priority. If bit is cleared, DMA has priority. Priority is determined according to the following table. PRI[1:2] Upper Bank Priority Lower Bank Priority 00 01 10 11 DMA Accesses DMA Accesses CPU Accesses CPU Accesses DMA Accesses CPU Accesses DMA Accesses CPU Accesses NOTE: The Freescale-recommended setting for the priority bits is 00. 5-2 9 SPV Secondary port valid. Allows access by DMA 0 DMA access to memory is disabled. 1 DMA access to memory is enabled. NOTE: The BDE bit in the second RAMBAR register must also be set to allow dual port access to the SRAM. For more information, see Section 8.4.2, “Memory Base Address Register (RAMBAR).” 8 WP Write protect. Allows only read accesses to the SRAM. When this bit is set, any attempted write access will generate an access error exception to the ColdFire processor core. 0 Allows read and write accesses to the SRAM module 1 Allows only read accesses to the SRAM module 7–6 — Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 The RAMBAR contains several control fields. These fields are shown in Figure 5-1 Static RAM (SRAM) Bits Name 5–1 C/I, SC, SD, UC, UD Description Address space masks (ASn) These five bit fields allow certain types of accesses to be “masked,” or inhibited from accessing the SRAM module. The address space mask bits are: C/I = CPU space/interrupt acknowledge cycle mask SC = Supervisor code address space mask SD = Supervisor data address space mask UC = User code address space mask UD = User data address space mask For each address space bit: 0 An access to the SRAM module can occur for this address space 1 Disable this address space from the SRAM module. If a reference using this address space is made, it is inhibited from accessing the SRAM module, and is processed like any other non-SRAM reference. These bits are useful for power management as detailed in Section 5.3.4, “Power Management.” 0 5.3.2 V Valid. A hardware reset clears this bit. When set, this bit enables the SRAM module; otherwise, the module is disabled. 0 Contents of RAMBAR are not valid 1 Contents of RAMBAR are valid SRAM Initialization After a hardware reset, the contents of the SRAM module are undefined. The valid bit of the RAMBAR is cleared, disabling the module. If the SRAM requires initialization with instructions or data, the following steps should be performed: 1. Load the RAMBAR mapping the SRAM module to the desired location within the address space. 2. Read the source data and write it to the SRAM. There are various instructions to support this function, including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance. 3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields. The ColdFire processor or an external emulator using the debug module can perform these initialization functions. 5.3.3 SRAM Initialization Code The following code segment describes how to initialize the SRAM. The code sets the base address of the SRAM at 0x20000000 and then initializes the SRAM to zeros. RAMBASE EQU $20000000 RAMVALID EQU $00000001 move.l #RAMBASE+RAMVALID,D0 ;load RAMBASE + valid bit into D0. movec.l D0, RAMBAR ;load RAMBAR and enable SRAM Freescale Semiconductor ;set this variable to $20000000 5-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 5-1. SRAM Base Address Register (continued) Static RAM (SRAM) lea.l RAMBASE,A0 ;load pointer to SRAM move.l #16384,D0 ;load loop counter into D0 clr.l (A0)+) ;clear 4 bytes of SRAM subq.l #1,D0 ;decrement loop counter bne.b SRAM_INIT_LOOP ;if done, then exit; else continue looping SRAM_INIT_LOOP: 5.3.4 Power Management As noted previously, depending on the configuration defined by the RAMBAR, instruction fetch and operand read accesses may be sent to the SRAM and cache simultaneously. If the access is mapped to the SRAM module, it sources the read data and the unified cache access is discarded. If the SRAM is used only for data operands, asserting the ASn bits associated with instruction fetches can decrease power dissipation. Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation. Table 5-2 shows some examples of typical RAMBAR settings. Table 5-2. Typical RAMBAR Setting Examples 5-4 Data Contained in SRAM RAMBAR[7:0] Code Only 0x2B Data Only 0x35 Both Code And Data 0x21 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 The following loop initializes the entire SRAM to zero The MCF5282 incorporates SuperFlash® technology licensed from SST. The ColdFire Flash Module (CFM) is constructed with eight banks of 32K x 16-bit Flash to generate a 512-Kbyte, 32-bit wide electrically erasable and programmable read-only memory array. The CFM is ideal for program and data storage for single-chip applications and allows for field reprogramming without external high-voltage sources. The voltage required to program and erase the Flash is generated internally by on-chip charge pumps. Program and erase operations are performed under CPU control through a command-driven interface to an internal state machine. All Flash physical blocks can be programmed or erased at the same time; however, it is not possible to read from a Flash physical block while the same block is being programmed or erased. The array used makes it possible to program or erase one pair of Flash physical blocks under the control of software routines executing out of another pair. NOTE The MCF5281 and MCF5214 implements only 256 Kbytes of Flash; half that of the MCF5282 and MCF5216. The MCF5280 does not contain a Flash module. 6.1 Features Features of the CFM include: • 512-Kbytes of Flash memory on the MCF5282 and MCF5216 • 256-Kbytes of Flash memory on the MCF5281 and MCF5214 • Basic Flash access time of 2 clock cycles. Optimized processor Flash interface reduces basic Flash access time through interleaving and speculative reads. • Automated program and erase operation • Concurrent verify, program, and erase of all array blocks • Read-while-write capability • Optional interrupt on command completion • Flexible scheme for protection against accidental program or erase operations • Access restriction controls for both supervisor/user and data/program space operations • Security for single-chip applications • Single power supply (system VDD) used for all module operations • Auto-sense amplifier timeout for low-power, low-frequency read operations NOTE Enabling Flash security will disable BDM communications. NOTE When Flash security is enabled, the chip will boot in single-chip mode regardless of the external reset configuration. Freescale Semiconductor 6-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 6 ColdFire Flash Module (CFM) ColdFire Flash Module (CFM) Block Diagram The CFM module shown in Figure 6-1 contains the Flash physical blocks, the ColdFire Flash bus and IP bus interfaces, Flash interface, register blocks, and the BIST engine. Each 128-Kbyte Flash physical block is arranged as two 32,768-word (16 bits) memory arrays. Each of these memory arrays is designated as xH or xL, where x represents one of the four Flash physical blocks (0–3) and H/L represents the high or low 16 bits of each longword of logical memory. Each of these words may be read as either individual bytes or aligned words. Aligned longword access is provided by concatenating the outputs of the each of the two memory arrays within the Flash physical block. Simple reads of bytes, aligned words, and aligned longwords require two 66-MHz clock cycles, although the processor’s Flash interface includes logic that reduces the effective access time through two-way longword interleaving and speculative reads. Flash physical blocks are interleaved on longword (4-byte) boundaries. Therefore, all Flash program, erase, and verify commands operate on adjacent Flash physical blocks and are initiated with a single aligned 32-bit write to the appropriate array location. Any other write operation will cause a cycle termination transfer error. Page erase operates simultaneously on two interleaving erase pages in adjacent Flash physical blocks. Each Flash physical block is organized as 1024 rows of 128 bytes with a single erase page consisting of 8 rows (1024 bytes). Since page erase operates simultaneously on two interleaving and adjacent physical Flash blocks, each erase row is comprised of four 16-bit entries in each of two memory arrays within each of two Flash physical blocks. The first row of Flash is made up of 0H_0L_1H_1L [0] through 0H_0L_1H_1L [31], where each [n] represents four 16-bit words from each memory array in each of two physical blocks, for a total of 256 bytes. Since a single erase page consists of 8 rows of 256 bytes, or 2048 bytes, the first erase page is physically located at 0H_0L_1H_1L [0] through 0H_0L_1H_1L [255]. Mass erase operates simultaneously on two adjacent Flash physical blocks in their entirety and erases a total of 256 Kbytes of Flash space. Therefore, it takes two mass erase operations, one on mass erase block 0 and one on mass erase block 1, to erase the full 512K CFM Flash on the MCF5282 and MCF5216. An erased Flash bit reads 1 and a programmed Flash bit reads 0. The CFM features a sense amplifier timeout (SATO) block that automatically reduces current consumption during reads at low system clock frequencies. 6-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.2 ColdFire Flash Module (CFM) Memory Array Block 0H 32K x 16 Flash Physical Block 3 Memory Array Block 0L 32K x 16 SATO SATO • • • Flash Physical Block 0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Internal Bus Memory Array Block 3H 32K x 16 SATO Memory Array Block 3L 32K x 16 SATO Flash Interface BIST Engine Flash Control Registers VDDF VSSF Backdoor Access Note: Mass Erase Block 0 (256 Kbytes) = Flash Physical Block 0 and Flash Physical Block 1. Mass Erase Block 1 (256 Kbytes) = Flash Physical Block 2 and Flash Physical Block 3 (MCF5282 and MCF5216 only) Figure 6-1. CFM Block Diagram Freescale Semiconductor 6-3 ColdFire Flash Module (CFM) Memory Map Figure 6-2 shows the memory map for the CFM array. The CFM array can reside anywhere in the memory space of the MCU. The starting address of the array is determined by the CFM array base address which must reside on a natural size boundary; that is, the CFM array base address must be an integer multiple of the array size. The CFM register space must reside on a 64 byte boundary as determined by the CFM register base address. Figure 6-2 shows how multiple 32,768 by 16-bit Flash physical blocks interleave to form a contiguous non-volatile memory space. Each pair of 32-bit blocks (even and odd) interleave every 4 bytes to form a 256-Kbyte section of memory. NOTE The CFM on the MCF5281 and MCF5214 is constructed with four banks of 32K x 16-bit Flash arrays to generate 256 Kbytes of 32-bit Flash memory. Logical Block 1 (256 Kbytes) 0x0007 FFFF Flash Physical Block 2 0x0004 000C 3H[1] 3L[1] 0x0004 0008 2H[1] 2L[1] 0x0004 0004 3H[0] 3L[0] 0x0004 0000 2H[0] 2L[0] 2H[31] 2L[31] 3H[31] 3L[31] Memory Array 2H Memory Array 2L Memory Array 3H Memory Array 3L 2H[0] 2L[0] 3H[0] 3L[0] 0x0003 FFFF Logical Block 0 (256 Kbytes) Flash Physical Block 0 Configuration Field (0x0000_0400– 0x0000_0417) 1 Flash Physical Block 3 0x0000 000C 1H[1] 1L[1] 0x0000 0008 0H[1] 0L[1] 0x0000 0004 1H[1] 1L[1] 0x0000 0000 0H[0] 0L[0] Flash Physical Block 1 0H[31] 0L[31] 1H[31] 1L[31] Memory Array 0H Memory Array 0L Memory Array 1H Memory Array 1L 0H[0] 0L[0] 1H[0] 1L[0] The MCF5281 and MCF5214 support only Logical Block 0. Each memory array = 64 Kbytes (16 bits wide × 32K) Each physical block = 128 Kbytes (32 bits wide × 32K) Figure 6-2. CFM Array Memory Map The CFM module has hardware interlocks to protect data from accidental corruption. The <<BLOCK NAME>> memory array is logically divided into 16-Kbyte sectors for the purpose of data protection and access control. A flexible scheme allows the protection of any combination of logical sectors (see Section 6.3.4.4, “CFM Protection Register (CFMPROT)”). A similar mechanism is available to control supervisor/user and program/data space access to these sectors. 6-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.3 ColdFire Flash Module (CFM) CFM Configuration Field The CFM configuration field comprises 24 bytes of reserved array memory space that determines the module protection and access restrictions out of reset. Data to secure the Flash from unauthorized access is also stored in the CFM configuration field. Table 6-1 describes each byte used in this field. Table 6-1. CFM Configuration Field Address Offset (from array base address) Size in Bytes 0x0000_0400–0x0000_0407 8 Back door comparison key 0x0000_0408–0x0000_040B 4 Flash program/erase sector protection Blocks 0H/0L (see Section 6.3.4.4, “CFM Protection Register (CFMPROT)”) 0x0000_040C–0x0000_040F 4 Flash supervisor/user space restrictions Blocks 0H/0L (see Section 6.3.4.5, “CFM Supervisor Access Register (CFMSACC)”) 0x0000_0410–0x0000_0413 4 Flash program/data space restrictions Blocks 0H/0L (see Section 6.3.4.6, “CFM Data Access Register (CFMDACC)”) 0x0000_0414–0x0000_0417 4 Flash security longword (see Section 6.3.4.3, “CFM Security Register (CFMSEC)”) 6.3.2 Description Flash Base Address Register (FLASHBAR) The configuration information in the Flash base address register (FLASHBAR) controls the operation of the Flash module. • The FLASHBAR holds the base address of the Flash. The MOVEC instruction provides write-only access to this register. • The FLASHBAR can be read or written from the debug module in a similar manner. • All undefined bits in the register are reserved. These bits are ignored during writes to the FLASHBAR, and return zeroes when read from the debug module. • The back door enable bit, FLASHBAR[BDE], is cleared at reset, disabling back door access to the Flash. • The FLASHBAR valid bit is programmed according to the chip mode selected at reset (see Chapter 27, “Chip Configuration Module (CCM)” for more details). All other bits are unaffected. The FLASHBAR register contains several control fields. These fields are shown in Figure 6-3 NOTE The default value of the FLASHBAR is determined by the chip configuration selected at reset (see Chapter 27, “Chip Configuration Module (CCM)” for more information). If external boot mode is used, then the FLASHBAR located in the processor’s CPU space will be invalid and it must be initialized with the valid bit set before the CPU (or modules) can access the on-chip Flash. Freescale Semiconductor 6-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.3.1 NOTE Flash accesses (reads/writes) by a bus master other than the core, (DMA controller or Fast Ethernet Controller), or writes to Flash by the core during programming must use the backdoor Flash address of IPSBAR plus an offset of 0x0400_0000. For example, for a DMA transfer from the first location of Flash when IPSBAR is still at its default location of 0x4000_0000, the source register would be loaded with 0x4400_0000. Backdoor access to Flash for reads can be made by the bus master, but it takes 2 cycles longer than a direct read of the Flash if using its FLASHBAR address. NOTE The Flash is marked as valid on reset based on the RCON (reset configuration) pin state. Flash space is valid on reset when booting in single chip mode (RCON pin asserted and D[26]/D[17]/D[16] set to 110), or when booting internally in master mode (RCON asserted and D[26]/D[17]/D[16] are set to 111 and D[18] and D[19] are set to 00). See Chapter 27, “Chip Configuration Module (CCM)” for more details. When the default reset configuration is not overriden, the device (by default) boots in single chip mode and the Flash space will be marked as valid at address 0x0. The Flash configuration field is checked during the reset sequence to see if the Flash is secured. If it is the part will always boot from internal Flash, since it will be marked as valid, regardless of what is done for chip configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 Reset R/W 15 9 — Address 8 WP Reset R/W — 0000_0000_0000_0000 R/W Field 16 7 6 — 5 4 3 2 1 0 C/I SC SD UC UD V 0000_0001_0010_000 R See Note R/W CPU + 0xC04 Note: The reset value for the valid bit is determined by the chip mode selected at reset (see Chapter 27, “Chip Configuration Module (CCM)”). Figure 6-3. Flash Base Address Register (FLASHBAR) 6-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Flash Module (CFM) ColdFire Flash Module (CFM) Bits Name 31–19 BA[31:18] 18–9 — 8 WP 7–6 — 5–1 Description Base address field. Defines the 0-modulo-512K base address of the Flash module. By programming this field, the Flash may be located on any 512Kbyte boundary within the processor’s four gigabyte address space. Reserved, should be cleared. Write protect. Read only. Allows only read accesses to the Flash. This bit is always set and any attempted write access will generate an access error exception to the ColdFire processor core. 0 Allows read and write accesses to the Flash module 1 Allows only read accesses to the Flash module Reserved, should be cleared. C/I, SC, SD, UC, Address space masks (ASn). UD These five bit fields allow certain types of accesses to be “masked,” or inhibited from accessing the Flash module. The address space mask bits are: C/I SC SD UC UD CPU space/interrupt acknowledge cycle mask Supervisor code address space mask Supervisor data address space mask User code address space mask User data address space mask For each address space bit: 0 An access to the Flash module can occur for this address space 1 Disable this address space from the Flash module. If a reference using this address space is made, it is inhibited from accessing the Flash module, and is processed like any other non-Flash reference. These bits are useful for power management as detailed in Chapter 7, “Power Management.” 0 6.3.3 V Valid. When set, this bit enables the Flash module; otherwise, the module is disabled. 0 Contents of FLASHBAR are not valid 1 Contents of FLASHBAR are valid CFM Registers The CFM module also contains a set of control and status registers. The memory map for these registers and their accessibility in supervisor and user modes is shown in Table 6-3. Table 6-3. CFM Register Address Map IPSBAR Offset 0x1D_0000 Bits 31–24 Bits 15–8 Bits 7–0 Access1 CFMCLKD Reserved2 S Bits 23–16 CFMMCR 2 0x1D_0004 Reserved 0x1D_0008 CFMSEC S S 0x1D_000C Reserved 2 S 0x1D_0010 CFMPROT S Freescale Semiconductor 6-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 6-2. FLASHBAR Field Descriptions ColdFire Flash Module (CFM) IPSBAR Offset Bits 31–24 Bits 23–16 Bits 15–8 Access1 Bits 7–0 0x1D_0014 CFMSACC S 0x1D_0018 CFMDACC S 0x1D_001C 2 S Reserved 0x1D_0020 CFMUSTAT Reserved2 S 0x1D_0024 CFMCMD Reserved2 S 1 S = Supervisor access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. 6.3.4 Register Descriptions The Flash registers are described in this subsection. 6.3.4.1 CFM Configuration Register (CFMCR) The CFMCR is used to configure and control the operation of the CFM array. 15 Field 11 — 10 9 8 7 6 5 4 LOCK PVIE AEIE CBEIE CCIE KEYACC Reset 0 — 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1D_0000 Figure 6-4. CFM Module Configuration Register (CFMCR) Bits 10 -5 in the CFMCR register are readable and writable with restrictions. Table 6-4. CFMCR Field Descriptions 6-8 Bits Name Description 15–11 — 10 LOCK Write lock control. The LOCK bit is always readable and is set once. 1 CFMPROT, CMFSACC, and CFMDACC register are write-locked. 0 CFMPROT, CMFSACC, and CFMDACC register are writable. 9 PVIE Protection violation interrupt enable. The PVIE bit is readable and writable. The PVIE bit enables an interrupt in case the protection violation flag, PVIOL, is set. 1 An interrupt will be requested whenever the PVIOL flag is set. 0 PVIOL interrupts disabled. 8 AEIE Access error interrupt enable. The AEIE bit is readable and writable. The AEIE bit enables an interrupt in case the access error flag, ACCERR, is set. 1 An interrupt will be requested whenever the ACCERR flag is set. 0 ACCERR interrupts disabled. Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 6-3. CFM Register Address Map ColdFire Flash Module (CFM) Bits Name Description 7 CBEIE Command buffer empty interrupt enable. The CBEIE bit is readable and writable. CBEIE enables an interrupt request when the command buffer for the Flash physical blocks is empty. 1 Request an interrupt whenever the CBEIF flag is set. 0 Command buffer empty interrupts disabled 6 CCIE 5 KEYACC 4–0 — 6.3.4.2 Command complete interrupt enable. The CCIE bit is readable and writable. CCIE enables an interrupt when the command executing for the Flash is complete. 1 Request an interrupt whenever the CCIF flag is set. 0 Command complete interrupts disabled Enable security key writing. The KEYACC bit is readable and only writable if the KEYEN bit in the CFMSEC register is set. 1 Writes to the Flash array are interpreted as keys to open the back door. 0 Writes to the Flash array are interpreted as the start of a program, erase, or verify sequence. Reserved, should be cleared. CFM Clock Divider Register (CFMCLKD) The CFMCLKD is used to set the frequency of the clock used for timed events in program and erase algorithms. Field 7 6 DIVLD PRDIV8 Reset 5 0 DIV 0000_0000 R/W R Address R/W IPSBAR + 0x1D_0002 Figure 6-5. CFM Clock Divider Register (CFMCLKD) All bits in CFMCLKD are readable. Bit 7 is a read-only status bit, while bits 6–0 can only be written once. Table 6-5. CFMCLKD Field Descriptions Bits Name 7 DIVLD 6 PRDIV8 5–0 DIV Freescale Semiconductor Description Clock divider loaded 1 CFMCLKD has been written since the last reset. 0 CFMCLKD has not been written. Enable prescaler divide by 8 1 Enables a prescaler that divides the CFM clock by 8 before it enters the CFMCLKD divider. 0 The CFM clock is fed directly into the CFMCLKD divider. Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the CFM input clock down to a frequency between 150 kHz and 200 kHz. The frequency range of the CFM clock is 150 kHz to 102.4 MHz. 6-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 6-4. CFMCR Field Descriptions NOTE CFMCLKD must be written with an appropriate value before programming or erasing the Flash array. Refer to Section 6.4.3.1, “Setting the CFMCLKD Register.” 6.3.4.3 CFM Security Register (CFMSEC) The CFMSEC controls the Flash security features. NOTE Enabling Flash security will disable BDM communications. NOTE When Flash security is enabled, the chip will boot in single-chip mode regardless of the external reset configuration. 31 30 29 16 Field KEYEN SECSTAT Reset — See Note R/W R 15 0 Field SEC Reset See Note R/W R Address IPSBAR + 0x1D_0008 Note: The SECSTAT bit reset value is determined by the security state of the Flash. All other bits in the register are loaded at reset from the Flash Security longword stored at the array base address + 0x0000_0414. Figure 6-6. CFM Security Register (CFMSEC) Table 6-6. CFMSEC Field Descriptions 6-10 Bits Name 31 KEYEN 30 SECSTAT Description Enable back door key to security 1 Back door to Flash is enabled. 0 Back door to Flash is disabled. Flash security status 1 Flash security is enabled 0 Flash security is disabled Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Flash Module (CFM) ColdFire Flash Module (CFM) Bits Name 29–16 — 15–0 SEC[15:0] Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 6-6. CFMSEC Field Descriptions Description Reserved. Should be cleared. Security field. The SEC bits define the security state of the device; see below. 1 SEC[15:0] Description 0x4AC8 Flash secured1 All other combinations Flash unsecured The 0x4AC8 value was chosen because it represents the ColdFire Halt instruction, making it unlikely that compiled code accidentally programmed at the security longword in the Flash configuration field location would unintentionally secure the device. The security features of the CFM are described in Section 6.5, “Flash Security Operation.” Freescale Semiconductor 6-11 ColdFire Flash Module (CFM) CFM Protection Register (CFMPROT) The CFMPROT specifies which Flash logical sectors are protected from program and erase operations. 31 16 Field PROT Reset See Note R/W R/W 15 0 Field PROT Reset See Note R/W R/W Address IPSBAR + 0x1D_0010 Note: The CFMPROT register is loaded at reset from the Flash Program/Erase Sector Protection longword stored at the array base address + 0x0000_0400. Figure 6-7. CFM Protection Register (CFMPROT) The CFMPROT register is always readable and only writeable when LOCK = 0. To change which logical sectors are protected on a temporary basis, write CFMPROT with a new value after the LOCK bit in CFMCR has been cleared. To change the value of CFMPROT that will be loaded on reset, the protection byte in the Flash configuration field must first be temporarily unprotected using the method just described before reprogramming the protection bytes. Then the Flash Protection longword at offset 0x1D_0400 must be written with the desired value. Table 6-7. CFMPROT Field Descriptions Bits Name 31–0 PROT[31:0] Description Sector protection. Each Flash logical sector can be protected from program and erase operations by setting its corresponding PROT bit. 1 Logical sector is protected. 0 Logical sector is not protected. The CFMPROT controls the protection of thirty-two 16-Kbyte Flash logical sectors in the 512-Kbyte Flash array. Figure 6-8 shows the association between each bit in the CFMPROT and its corresponding logical sector. NOTE Since the MCF5281 and MCF5214 devices contain a 256-Kbyte Flash, only CFMPROT[15:0] is used. 6-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.3.4.4 ColdFire Flash Module (CFM) SECTOR 31 PROTECT[31] (ARRAY_BASE + 0x0007_C000) • • • PROTECT[2] } 16Kbyte Sector SECTOR 2 Protected Flash Logical Sectors as defined by CFMPROT register (ARRAY_BASE + 0x0000_8000) SECTOR 1 (ARRAY_BASE + 0x0000_4000) SECTOR 0 (ARRAY_BASE + 0x0000_0000) Figure 6-8. CFMPROT Protection Diagram 6.3.4.5 CFM Supervisor Access Register (CFMSACC) The CFMSACC specifies the supervisor/user access permissions of Flash logical sectors. 31 16 Field SUPV Reset See Note R/W R/W 15 0 Field SUPV Reset See Note R/W R/W Address IPSBAR + 0x1D_0014 Note: The CFMPROT register is loaded at reset from the Flash Supervisor/user Space Restrictions longword stored at the array base address + 0x0000_040C. Figure 6-9. CFM Supervisor Access Register (CFMSACC) Freescale Semiconductor 6-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 (ARRAY_BASE + 0x0007_FFFF) ColdFire Flash Module (CFM) Bits Name Description 31–0 SUPV[31:0] Supervisor address space assignment. The SUPV[31:0] bits are always readable and only writable when LOCK = 0. Each Flash logical sector can be mapped into supervisor or unrestricted address space. CFMSACC uses the same correspondence between logical sectors and register bits as does CFMPROT. See Figure 6-8 for details. When a logical sector is mapped into supervisor address space, only CPU supervisor accesses will be allowed. A CPU user access to a location in supervisor address space will result in a cycle termination transfer error. When a logical sector is mapped into unrestricted address space both supervisor and user accesses are allowed. 1 Logical sector is mapped in supervisor address space. 0 Logical sector is mapped in unrestricted address space. 6.3.4.6 CFM Data Access Register (CFMDACC) The CFMDACC specifies the data/program access permissions of Flash logical sectors. 31 16 Field DATA Reset See Note R/W R/W 15 0 Field DATA Reset See Note R/W R/W Address IPSBAR + 0x1D_0018 Note: The CFMPROT register is loaded at reset from the Flash Program/Data Space Restrictions longword stored at the array base address + 0x0000_0410. Figure 6-10. CFM Data Access Register (CFMDACC) Table 6-9. CFMDACC Field Descriptions 6-14 Bits Name Description 31–0 DATA[31:0] Data address space assignment. The DATA[31:0] bits are always readable and only writable when LOCK = 0. Each Flash logical sector can be mapped into data or both data and program address space. CFMDACC uses the same correspondence between logical sectors and register bits as does CFMPROT. See Figure 6-8 for details. When a logical sector is mapped into data address space, only CPU data accesses will be allowed. A CPU program access to a location in data address space will result in a cycle termination transfer error. When an array sector is mapped into both data and program address space both data and program accesses are allowed. 1 Logical sector is mapped in data address space. 0 Logical sector is mapped in data and program address space. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 6-8. CFMSACC Field Descriptions ColdFire Flash Module (CFM) CFM User Status Register (CFMUSTAT) The CFMUSTAT reports Flash state machine command status, array access errors, protection violations, and blank check status. Field 7 6 CBEIF CCIF Reset 5 1 PVIOL ACCERR — BLANK 0 — 1100_0000 R/W R/W Address R R/W IPSBAR + 0x1D_0020 Figure 6-11. CFM User Status Register (CFMUSTAT) NOTE Only one CFMUSTAT bit should be cleared at a time. Table 6-10. CFMUSTAT Field Descriptions Bits Name Description 7 CBEIF Command buffer empty interrupt flag. The CBEIF flag indicates that the command buffer for the interleaved Flash physical blocks is empty and that a new command sequence can be started. Clear CBEIF by writing it to 1. Writing a 0 to CBEIF has no effect but can be used to abort a command sequence. The CBEIF bit can trigger an interrupt request if the CBEIE bit is set in CFMMCR. While CBEIF is clear, the CFMCMD register is not writable. 1 Command buffer is ready to accept a new command. 0 Command buffer is full. 6 CCIF Command complete interrupt flag. The CCIF flag indicates that no commands are pending for the Flash physical blocks. CCIF is set and cleared automatically upon start and completion of a command. Writing to CCIF has no effect. The CCIF bit can trigger an interrupt request if the CCIE bit is set in CFMCR. 1 All commands are completed 0 Command in progress 5 PVIOL Protection violation flag. The PVIOL flag indicates an attempt was made to initiate a program or erase operation in a Flash logical sector denoted as protected by CFMPROT. Clear PVIOL by writing it to 1. Writing a 0 to PVIOL has no effect. While PVIOL is set in any this register, it is not possible to launch another command. 1 A protection violation has occurred 0 No failure 4 ACCERR Access error flag. The ACCERR flag indicates an illegal access to the CFM array or registers caused by a bad program or erase sequence. ACCERR is cleared by writing it to 1. Writing a 0 to ACCERR has no effect. While ACCERR is set in this register, it is not possible to launch another command. See Section 6.4.3.4, “Flash User Mode Illegal Operations,” for details on what sets the ACCERR flag. 1 Access error has occurred 0 No failure 3 — Freescale Semiconductor Reserved, should be cleared. 6-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.3.4.7 ColdFire Flash Module (CFM) Bits Name Description 2 BLANK Erase Verified Flag. The BLANK flag indicates that the erase verify command (RDARY1) has checked the two interleaved Flash physical blocks and found them to be blank. Clear BLANK by writing it to 1. Writing a 0 has no effect. 1 Flash physical blocks verify as erased. 0 If an erase verify command has been requested, and the CCIF flag is set, then the selected Flash physical blocks are not blank. 1–0 — 6.3.4.8 Reserved, should be cleared. CFM Command Register (CFMCMD) The CFMCMD is the register to which Flash program, erase, and verify commands are written. 7 Field 6 0 — CMD Reset 0000_0000 R/W R/W Address IPSBAR + 0x1D_0024 Figure 6-12. CFM Command Register (CFMCMD) Table 6-11. CFMCMD Field Descriptions Bits Name 7 — 6–0 CMD[6:0] Description Reserved, should be cleared. Command. Valid Flash user mode commands are shown in Table 6-12. Writing a command in user mode other than those listed in Table 6-12 will set the ACCERR flag in CFMUSTAT. CFMCMD is readable and writable in all modes. Writes to bit 7 have no effect and reads return 0. Table 6-12. CFMCMD User Mode Commands 6.4 Command Name Description 0x05 RDARY1 Erase verify (all 1s) 0x20 PGM Longword program 0x40 PGERS Page erase 0x41 MASERS Mass erase 0x06 PGERSVER Page erase verify CFM Operation The CFM registers, subject to the restrictions previously noted, can generally be read and written (see Section 6.3.4, “Register Descriptions” for details). Reads of the CFM array occur normally and writes behave according to the setting of the KEYACC bit in CFMCR. Program, erase, and verify operations are 6-16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 6-10. CFMUSTAT Field Descriptions initiated by the CPU. Special cases of user mode apply when the CPU is in low-power or debug modes and when the MCU boots in master mode or emulation mode. 6.4.1 Read Operations A valid read operation occurs whenever a transfer request is initiated by the ColdFire core, the address is equal to an address within the valid range of the CFM memory space, and the read/write control indicates a read cycle. In order to reduce power at low system clock frequencies, the sense amplifier timeout (SATO) block minimizes the time during which the sense amplifiers are enabled for read operations. The sense amplifier enable signals to the Flash timeout after approximately 50 ns. 6.4.2 Write Operations A valid write operation occurs whenever a transfer request is initiated by the ColdFire core, the address is equal to an address within the valid range of the CFM memory space, and the read/write control indicates a write cycle. The action taken on a valid CFM array write depends on the subsequent user command issued as part of a valid command sequence. Only aligned 32-bit write operations are allowed to the CFM array. Byte and word write operations will result in a cycle termination transfer error. 6.4.3 Program and Erase Operations Read and write operations are both used for the program and erase algorithms described in this subsection. These algorithms are controlled by a state machine whose timebase is derived from the CFM module clock via a programmable counter. The command register and associated address and data buffers operate as a two stage FIFO so that a new command along with the necessary address and data can be stored while the previous command is still in progress. This pipelining speeds when programming more than one longword on a specific row, as the charge pumps can be kept on in between two programming commands, thus saving the overhead needed to set up the charge pumps. Buffer empty and command completion are indicated by flags in the CFM user status register. Interrupts will be requested if enabled. 6.4.3.1 Setting the CFMCLKD Register Prior to issuing any program or erase commands, CFMCLKD must be written to set the Flash state machine clock (FCLK). The CFM module runs at the system clock frequency ÷ 2, but FCLK must be divided down from this frequency to a frequency between 150 kHz and 200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0] bits in CFMCLKD: 1. If fSYS ÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0. 2. Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result and discard any fraction. Do not round the result. DIV[5:0] = fSYS 2 x 200kHz x (1 + (PRDIV8 x 7)) 3. Thus the Flash state machine clock will be: Freescale Semiconductor 6-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Flash Module (CFM) fSYS fCLK = 2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7)) Consider the following example for fSYS = 66 MHz: DIV[5:0] = = fSYS 2 x 200kHz x (1 + (PRDIV8 x 7)) 66 MHz 400 kHz x (1 + (1 x 7)) = 20 fSYS fCLK = 2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7)) = 66 MHz 2 x (20 + 1) x (1 + (1 x 7)) = 196.43 kHz So, for fSYS = 66 MHz, writing 0x54 to CFMCLKD will set fCLK to 196.43 kHz which is a valid frequency for the timing of program and erase operations. WARNING For proper program and erase operations, it is critical to set fCLK between 150 kHz and 200 kHz. Array damage due to overstress can occur when fCLK is less than 150 kHz. Incomplete programming and erasure can occur when fCLK is greater than 200 kHz. NOTE Command execution time increases proportionally with the period of fCLK. When CFMCLKD is written, the DIVLD bit is set automatically. If DIVLD is 0, CFMCLKD has not been written since the last reset. Program and erase commands will not execute if this register has not been written (see Section 6.4.3.4, “Flash User Mode Illegal Operations”). 6.4.3.2 Program, Erase, and Verify Sequences A command state machine is used to supervise the write sequencing of program, erase, and verify commands. To prepare for a command, the CFMUSTAT[CBEIF] flag should be tested to ensure that the address, data, and command buffers are empty. If CBEIF is set, the command write sequence can be started. This three-step command write sequence must be strictly followed. No intermediate writes to the CFM module are permitted between these three steps. The command write sequence is: 1. Write the 32-bit longword to be programmed to its location in the CFM array. The address and data will be stored in internal buffers. All address bits are valid for program commands. The value of the data written for verify and erase commands is ignored. For mass erase or verify, the address can be any location in the CFM array. For page erase, address bits [9:0] are ignored. 6-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Flash Module (CFM) NOTE The page erase command operates simultaneously on adjacent erase pages in two interleaved Flash physical blocks. Thus, a single erase page is effectively 2 Kbyte. 2. Write the program, erase, or verify command to CFMCMD, the command buffer. See Section 6.4.3.3, “Flash Valid Commands.” 3. Launch the command by writing a 1 to the CBEIF flag. This clears CBEIF. When command execution is complete, the Flash state machine sets the CCIF flag. The CBEIF flag is also set again, indicating that the address, data, and command buffers are ready for a new command sequence to begin. The Flash state machine flags errors in command write sequences by means of the ACCERR and PVIOL flags in the CFMUSTAT register. An erroneous command write sequence self-aborts and sets the appropriate flag. The ACCERR or PVIOL flags must be cleared before commencing another command write sequence. NOTE By writing a 0 to CBEIF, a command sequence can be aborted after the longword write to the CFM array or the command write to the CFMCMD and before the command is launched. The ACCERR flag will be set on aborted commands and must be cleared before a new command write sequence. A summary of the programming algorithm is shown in Figure 6-13. The flow is similar for the erase and verify algorithms with the exceptions noted in step 1 above. 6.4.3.3 Flash Valid Commands Table 6-13 summarizes the valid Flash user commands. Table 6-13. Flash User Commands CFMCMD Meaning Description 0x05 Erase verify Verify that all 256 Kbytes of Flash from two interleaving physical blocks are erased. If both blocks are erased, the BLANK bit will be set in the CFMUSTAT register upon command completion. 0x20 Program 0x40 Page erase Erase 2 Kbyte of Flash. Two 1024-byte pages from interleaving physical blocks are erased in this operation. 0x41 Mass erase Erase all 256 Kbytes of Flash from two interleaving physical blocks. A mass erase is only possible when no PROTECT bits are set for that block. 0x06 Page erase verify Verify that the two 1024-byte pages are erased. If both pages are erased, the BLANK bit will be set in the CFMUSTAT register upon command completion. Freescale Semiconductor Program a 32-bit longword. 6-19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Flash Module (CFM) START READ CFMCLKD CLOCK REGISTER WRITTEN CHECK NO DIVLD SET? YES WRITE CFMCLKD READ CFMUSTAT CBEIF SET? NO YES 1. WRITE PROGRAM DATA TO ARRAY ADDRESS 2. WRITE PROGRAM COMMAND 0x20 TO CFMCMD NOTE: COMMAND SEQUENCE ABORTED BY WRITING 0x00 TO CFMUSTAT 3. WRITE 0x80 TO CLEAR CFMUSTAT CBEIF BIT NOTE: COMMAND SEQUENCE ABORTED BY WRITING 0x00 TO CFMUSTAT READ CFMUSTAT PVIOL SET? YES WRITE 0x20 TO CLEAR CFMUSTAT PVIOL BIT ACCERR SET? YES WRITE 0x10 TO CLEAR CFMUSTAT ACCERR BIT PROTECTION VIOLATION CHECK NO ACCESS ERROR CHECK YES NO ADDRESS, DATA, COMMAND BUFFER EMPTY CHECK CBEIF SET? YES NEXT WRITE? NO NO READ CFMUSTAT BIT POLLING FOR COMMAND COMPLETION CHECK CCIF SET? NO YES EXIT Figure 6-13. Example Program Algorithm 6-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Flash Module (CFM) ColdFire Flash Module (CFM) Flash User Mode Illegal Operations The ACCERR flag will be set during a command write sequence if any of the illegal operations below are performed. Such operations will cause the command sequence to immediately abort. 1. Writing to the CFM array before initializing CFMCLKD. 2. Writing to the CFM array while in emulation mode. 3. Writing a byte or a word to the CFM array. Only 32-bit longword programming is allowed. 4. Writing to the CFM array while CBEIF is not set. 5. Writing an invalid user command to the CFMCMD. 6. Writing to any CFM other than CFMCMD after writing a longword to the CFM array. 7. Writing a second command to CFMCMD before executing the previously written command. 8. Writing to any CFM register other than CFMUSTAT (to clear CBEIF) after writing to the command register. 9. Entering stop mode while a program or erase command is in progress. 10. Aborting a command sequence by writing a 0 to CBEIF after the longword write to the CFM array or after writing a command to CFMCMD and before launching it. The PVIOL flag will be set during a command write sequence after the longword write to the CFM array if any of the illegal operations below are performed. Such operations will cause the command sequence to immediately abort. 1. Writing to an address in a protected area of the CFM array. 2. Writing a mass erase command to CFMCMD while any logical sector is protected (see Section 6.3.4.4, “CFM Protection Register (CFMPROT)”). If a Flash physical block is read during a program or erase operation on that block (CFMUSTAT bit CCIF = 0), the read will return non-valid data and the ACCERR flag will not be set. 6.4.4 Stop Mode If a command is active (CCIF = 0) when the MCU enters stop mode, the command sequence monitor performs the following: 1. The command in progress aborts 2. The Flash high voltage circuitry switches off and any pending command (CBEIF = 0) does not executed when the MCU exits stop mode. 3. The CCIF and ACCERR flags are set if a command is active when the MCU enters stop mode. NOTE The state of any longword(s) being programmed or any erase pages/physical blocks being erased is not guaranteed if the MCU enters stop mode with a command in progress. WARNING Active commands are immediately aborted when the MCU enters stop mode. Do not execute the STOP instruction during program and erase operations. Freescale Semiconductor 6-21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.4.3.4 ColdFire Flash Module (CFM) Master Mode If the MCU is booted in master mode with an external memory selected as the boot device, the CFM will not respond to the first transfer request out of reset. This will allow the external boot device to provide the reset vector and terminate the bus cycle. 6.5 Flash Security Operation The CFM array provides security information to the integration module and the rest of the MCU. A longword in the Flash configuration field stores this information. This longword is read automatically after each reset and is stored in the CFMSEC register. NOTE Enabling Flash security will disable BDM communications. NOTE When Flash security is enabled, the chip will boot in single chip mode regardless of the external reset configuration. In user mode, security can be bypassed via a back door access scheme using an 8-byte long key. Upon successful completion of the back door access sequence, the module output signal and status bit indicating that the chip is secure are cleared. The CFM may be unsecured via one of two methods: 1. Executing a back door access scheme. 2. Passing an erase verify check. 6-22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.4.5 ColdFire Flash Module (CFM) Back Door Access If the KEYEN bit is set, security can be bypassed by: 1. Setting the KEYACC bit in the CFM configuration register (CFMMCR). 2. Writing the correct 8-byte back door comparison key to the CFM array at addresses 0x0000_0400 to 0x0000_0407. This operation must consist of two 32-bit writes to address 0x0000_0400 and 0x0000_0404 in that order. The two back door write cycles can be separated by any number of bus cycles. 3. Clearing the KEYACC bit. 4. If all 8 bytes written match the array contents at addresses 0x0000_0400 to 0x0000_0407, then security is bypassed until the next reset. NOTE The security of the Flash as defined by the Flash security longword at address 0x0000_0414 is not changed by the back door method of unsecuring the device. After the next reset the device is again secured and the same back door key remains in effect unless changed by program or erase operations. The back door method of unsecuring the device has no effect on the program and erase protections defined by the CFM protection register (CFMPROT). 6.5.2 Erase Verify Check Security can be disabled by verifying that the CFM array is blank. If required, the mass erase command can be executed for each pair of Flash physical blocks that comprise the array. The erase verify command must then be executed for all Flash physical blocks within the array. The CFM will be unsecured if the erase verify command determines that the entire array is blank. After the next reset, the security state of the CFM will be determined by the Flash security longword, which, after being erased, will read 0xffff_ffff, thus unsecuring the module. 6.6 Reset The CFM array is not accessible for any operations via the address and data buses during reset. If a reset occurs while any command is in progress that command will immediately abort. The state of any longword being programmed or any erase pages/physical blocks being erased is not guaranteed. 6.7 Interrupts The CFM module can request an interrupt when all commands are completed or when the address, data, and command buffers are empty. Table 6-14 shows the CFM interrupt mechanism. Table 6-14. CFM Interrupt Sources Interrupt Source Command, data and address buffers empty Freescale Semiconductor Interrupt Flag Local Enable CBEIF (CFMUSTAT) CBEIE (CFMCR) 6-23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 6.5.1 Interrupt Source 6-24 Interrupt Flag Local Enable All commands are completed CCIF (CFMUSTAT) CCIE (CFMCR) Access error ACCERR (CFMUSTAT) AEIE (CFMCR) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 ColdFire Flash Module (CFM) Table 6-14. CFM Interrupt Sources (continued) Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 7 Power Management The power management module (PMM) controls the device’s low-power operation. 7.1 Features The following features support low-power operation. • Four modes of operation: — Run — Wait — Doze — Stop • Ability to shut down most peripherals independently • Ability to shut down the external CLKOUT pin 7.2 Memory Map and Registers This subsection provides a description of the memory map and registers. 7.2.1 Programming Model The PMM programming model consists of one register: • The low-power control register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls clock activity in this low-power mode. Freescale Semiconductor 7-1 Power Management Memory Map Table 7-1. Chip Configuration Module Memory Map IPSBAR Offset Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0 Access1 0x0000_0010 Core Reset Status Register (CRSR)2 Core Watchdog Control Register (CWCR) Low-Power Interrupt Control Register (LPICR) Core Watchdog Service Register (CWSR) S 0x0011_0004 Chip Configuration Register (CCR)3 Reserved Low-Power Control Register (LPCR) S 1 S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 The CRSR, CWCR, and CWSR are described in the System Integration Module. They are shown here only to warn against accidental writes to these registers when accessing the LPICR. 3 The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this register when accessing the LPCR. 7.2.3 Register Descriptions The following subsection describes the PMM registers. 7.2.3.1 Low-Power Interrupt Control Register (LPICR) Implementation of low-power stop mode and exit from a low-power mode via an interrupt require communication between the CPU and logic associated with the interrupt controller. The LPICR is an 8-bit register that enables entry into low-power stop mode, and includes the setting of the interrupt level needed to exit a low-power mode. NOTE The setting of the low-power mode select (LPMD) field in the power management module’s low-power control register (LPCR) determines which low-power mode the device enters when a STOP instruction is issued. If this field is set to enter stop mode, then the ENBSTOP bit in the LPICR must also be set. Following is the sequence of operations needed to enable this functionality: 1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired low-power mode) and loading the appropriate interrupt priority level. 2. At the appropriate time, the processor executes the privileged STOP instruction. Once the processor has stopped execution, it asserts a specific Processor Status (PST) encoding. Issuing the STOP instruction when the LPICR[ENBSTOP] bit is set causes the SCM to enter stop mode. 3. The entry into a low-power mode is processed by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processor core) are disabled. 4. After entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. The device waits for an event to generate an interrupt request with a priority level greater than the value programmed in LPICR[XLPM_IPL[2:0]]. 7-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.2.2 Power Management Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NOTE Only fixed (external) interrupt can bring a device out of stop mode. To exit from other low-power modes, such as doze or wait, either fixed or programmable interrupts may be used; however, the module generating the interrupt must be enabled in that particular low-power mode. 5. Once an appropriately-high interrupt request level arrives, the interrupt controller signals its presence, and the SIM responds by asserting the request to exit low-power mode. 6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks. 7. With the processor clocks enabled, the core processes the pending interrupt request. 7 6 Field ENBSTOP Reset 1/0 4 3 0 XLPM_IPL 0 1/0 — 0 R/W Undefined R/W Address IPSBAR + 0x012 Figure 7-1. Low-Power Interrupt Control Register (LPICR) Table 7-2. LPICR Field Descriptions Bits Name Description 7 ENBSTOP Enable low-power stop mode. 0 Low-power stop mode disabled 1 Low-power stop mode enabled. Once the core is stopped and the signal to enter stop mode is asserted, processor clocks can be disabled. 6–4 XLPM_IPL Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power mode.Refer to Table 7-3. 3–0 — Reserved, should be cleared. Table 7-3. XLPM_IPL Settings XLPM_IPL[2:0] Interrupts Level Needed to Exit Low-Power Mode 000 Any interrupt request exits low-power mode 001 Interrupt request levels [2-7] exit low-power mode 010 Interrupt request levels [3-7] exit low-power mode 011 Interrupt request levels [4-7] exit low-power mode 100 Interrupt request levels [5-7] exit low-power mode 101 Interrupt request levels [6-7] exit low-power mode 11x Interrupt request level [7] exits low-power mode Freescale Semiconductor 7-3 Power Management Low-Power Control Register (LPCR) The LPCR controls chip operation and module operation during low-power modes. 7 Field 6 LPMD 5 — Reset 4 3 STPMD 2 1 0 — LVDSE — 0000_0010 R/W R/W Address IPSBAR + 0x0011_0007 Figure 7-2. Low-Power Control Register (LPCR) Table 7-4. LPCR Field Descriptions Bits Name Description 7–6 LPMD Low-power mode select. Used to select the low-power mode the chip enters once the ColdFire CPU executes the STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD[1:0] bits are readable and writable in all modes. Table 7-5 illustrates the four different power modes that can be configured with the LPMD bit field. 5 — 4–3 STPMD 2 — 1 LVDSE 0 — Reserved, should be cleared. PLL/CLKOUT stop mode. Controls PLL and CLKOUT operation in stop mode as shown in Table 7-6 Reserved, should be cleared. LDV standby enable. Controls whether the PMM enters VREG Standby Mode (LVD disabled) or VREG Pseudo-Standby (LVD enabled) mode when the PMM receives a power down request. This bit has no effect if the RCR[LVDE] bit is a logic 0. 1 VREG Pseudo-Standby mode (LVD enabled on power down request). 0 VREG Standby mode (LVD disabled on power down request). Reserved, should be cleared. Table 7-5. Low-Power Modes 7-4 LPMD[1:0] Mode 11 STOP 10 WAIT 01 DOZE 00 RUN Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.2.3.2 Power Management Operation During Stop Mode STPMD[1:0] System Clocks CLKOUT PLL OSC PMM 00 Disabled Enabled Enabled Enabled Enabled 01 Disabled Disabled Enabled Enabled Enabled 10 Disabled Disabled Disabled Enabled Enabled 11 Disabled Disabled Disabled Disabled Low-Power Option NOTE If LPCR[LPMD] is cleared, then the device stops executing code upon issue of a STOP instruction. However, no clocks are disabled. 7.3 Functional Description The functions and characteristics of the low-power modes, and how each module is affected by, or affects, these modes are discussed in this section. 7.3.1 Low-Power Modes The system enters a low-power mode by executing a STOP instruction. Which mode the device actually enters (either stop, wait, or doze) depends on what is programmed in LPCR[LPMD]. Entry into any of these modes idles the CPU with no cycles active, powers down the system and stops all internal clocks appropriately. During stop mode, the system clock is stopped low. For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is issued. A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events consist of any of these conditions: • Any type of reset • Any valid, enabled interrupt request The latter method of exiting from low-power mode, by a valid and enabled interrupt request, requires several things: • An interrupt request whose priority is higher than the value programmed in the XLPM_IPL field of the LPICR • An interrupt request whose priority higher than the value programmed in the interrupt priority mask (I) field of the core’s status register • An interrupt request from a source which is not masked in the interrupt controller’s interrupt mask register • An interrupt request which has been enabled at the module of the interrupt’s origin 7.3.1.1 Run Mode Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency. Freescale Semiconductor 7-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 7-6. PLL/CLKOUT Stop Mode Operation Power Management Wait Mode Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode. 7.3.1.3 Doze Mode Doze mode affects the CPU in the same manner as wait mode, except that each peripheral defines individual operational characteristics in doze mode. Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode. Peripherals which are stopped will restart operation on exit from doze mode as defined for each peripheral. 7.3.1.4 Stop Mode Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks to the system are stopped and the peripherals cease operation. Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation. The following subsections specify the operation of each module while in and when exiting low-power modes. NOTE Entering stop mode will disable the SDRAMC including the refresh counter. If SDRAM is used, then code is required to insure proper entry and exit from stop mode. See Section 7.3.2.5, “SDRAM Controller (SDRAMC)” for more information. 7.3.1.5 Peripheral Shut Down Most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description for further details). A peripheral may be disabled at any time and will remain disabled during any low-power mode of operation. 7.3.2 7.3.2.1 Peripheral Behavior in Low-Power Modes ColdFire Core The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 7.3.2.2 Static Random-Access Memory (SRAM) SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 7-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.3.1.2 Power Management Flash The Flash module is in a low-power state if not being accessed. No recovery time is required after exit from any low-power mode. The MCF5280 does not have a Flash module. 7.3.2.4 System Control Module (SCM) The SCM’s core Watchdog timer can bring the device out of all low-power modes except stop mode. In stop mode, all clocks stop, and the core Watchdog does not operate. When enabled, the core Watchdog can bring the device out of low-power mode in one of two ways. If the core Watchdog reset/interrupt select (CSRI) bit is set, then a core Watchdog timeout will cause a reset of the device. If the CSRI bit is cleared, then a core Watchdog interrupt may be enabled and upon watchdog timeout, can bring the device out of low-power mode. This system setup must meet the conditions specified in Section 7.3.1, “Low-Power Modes” for the core Watchdog interrupt to bring the part out of low-power mode. 7.3.2.5 SDRAM Controller (SDRAMC) SDRAMC operation is unaffected by either the wait or doze modes; however, the SDRAMC is disabled by stop mode. Since all clocks to the SDRAMC are disabled by stop mode, the SDRAMC will not generate refresh cycles. To prevent loss of data the SDRAM should be placed in self-refresh mode by setting DCR[IS] before entering stop mode. The SDRAM self-refresh mode allows the SDRAM to enter a low-power state where internal refresh operations are used to maintain the integrity of the data stored in the SDRAM. When stop mode is exited clearing the DCR[IS] bit will cause the SDRAM to exit the self-refresh mode and allow bus cycles to the SDRAM to resume. NOTE The SDRAM is inaccessible while in the self-refresh mode. Therefore, if stop mode is used the vector table and any interrupt handlers that could wake the processor should not be stored in or attempt to access SDRAM. 7.3.2.6 Chip Select Module In wait and doze modes, the chip select module continues operation but does not generate interrupts; therefore it cannot bring a device out of a low-power mode. This module is stopped in stop mode. 7.3.2.7 DMA Controller (DMAC0–DMA3) In wait and doze modes, the DMA controller is capable of bringing the device out of a low-power mode by generating an interrupt either upon completion of a transfer or upon an error condition. The completion of transfer interrupt is generated when DMA interrupts are enabled by the setting of the DCR[INT] bit, and an interrupt is generated when the DSR[DONE] bit is set. The interrupt upon error condition is generated when the DCR[INT] bit is set, and an interrupt is generated when either the CE, BES or BED bit in the DSR becomes set. The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode. Freescale Semiconductor 7-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.3.2.3 Power Management UART Modules (UART0, UART1, and UART2) In wait and doze modes, the UART may generate an interrupt to exit the low-power modes. • Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions. • The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode. In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and external pins. During this mode, the UART clocks are shut down. Coming out of stop mode returns the UARTs to operation from the state prior to the low-power mode entry. 7.3.2.9 I2C Module When the I2C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in stop mode, the I2C module is operable and may generate an interrupt to bring the device out of a low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The setting of I2SR[IIF] signifies either the completion of one byte transfer or the reception of a calling address matching its own specified address when in slave receive mode. In stop mode, the I2C Module stops immediately and freezes operation, register values, and external pins. Upon exiting stop mode, the I2C resumes operation unless stop mode was exited by reset. 7.3.2.10 Queued Serial Peripheral Interface (QSPI) In wait and doze modes, the queued serial peripheral interface (QSPI) may generate an interrupt to exit the low-power modes. • Clearing the QSPI enable bit (SPE) disables the QSPI function. • The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode. In stop mode, the QSPI stops immediately and freezes operation, register values, state machines, and external pins. During this mode, the QSPI clocks are shut down. Coming out of stop mode returns the QSPI to operation from the state prior to the low-power mode entry. 7.3.2.11 DMA Timers (DMAT0–DMAT3) In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode. This interrupt can be generated when the DMA Timer is in either input capture mode or reference compare mode. In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has a non-zero value and the DMA enable (DMAEN) bit of the DMA timer extended mode register (DTXMR) is cleared, an interrupt is issued upon a captured input. In reference compare mode, where the output reference request interrupt enable (ORRI) bit of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the reference value. DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset. 7-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.3.2.8 Power Management Interrupt Controllers (INTC0, INTC1) The interrupt controller is not affected by any of the low-power modes. All logic between the input sources and generating the interrupt to the processor will be combinational to allow the ability to wake up the CPU processor during low-power stop mode when all system clocks are stopped. An interrupt request will cause the CPU to exit a low-power mode only if that interrupt’s priority level is at or above the level programmed in the interrupt priority mask field of the CPU’s status register (SR). The interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module from which the interrupt request would originate. 7.3.2.13 Fast Ethernet Controller (FEC) In wait and doze modes, the FEC may generate an interrupt to exit the low-power modes. • Clearing the ECNTRL[ETHER_EN] bit disables the FEC function. • The FEC is unaffected by wait mode and may generate an interrupt to exit this mode. In stop mode, the FEC stops immediately and freezes operation, register values, state machines, and external pins. During this mode, the FEC clocks are shut down. Coming out of stop mode returns the FEC to operation from the state prior to the low-power mode entry. The MCF5214 and MCF5216 do not contain an FEC. 7.3.2.14 I/O Ports The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power current draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is exited by a reset, the state of the I/O pins will revert to their default direction settings. 7.3.2.15 Reset Controller A power-on reset (POR) will always cause a chip reset and exit from any low-power mode. In wait and doze modes, asserting the external RSTI pin for at least four clocks will cause an external reset that will reset the chip and exit any low-power modes. In stop mode, the RSTI pin synchronization is disabled and asserting the external RSTI pin will asynchronously generate an internal reset and exit any low-power modes. Registers will lose current values and must be reconfigured from reset state if needed. If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE) bits in the synthesizer control register are set, then any loss-of-clock or loss-of-lock will reset the chip and exit any low-power modes. If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout may generate a reset to exit these low-power modes. When the CPU is inactive, a software reset cannot be generated to exit any low-power mode. 7.3.2.16 Chip Configuration Module The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is exited by a reset, chip configuration may be executed if configured to do so. Freescale Semiconductor 7-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.3.2.12 Power Management Clock Module In wait and doze modes, the clocks to the CPU, Flash, and SRAM will be stopped and the system clocks to the peripherals are enabled. Each module may disable the module clocks locally at the module level. In stop mode, all clocks to the system will be stopped. During stop mode, there are several options for enabling/disabling the PLL and/or crystal oscillator (OSC); each of these options requires a compromise between wakeup recovery time and stop mode power. The PLL may be disabled during stop mode. A wakeup time of up to 200 μs is required for the PLL to re-lock. The OSC may also be disabled during stop mode. The time required for the OSC to restart is dependent upon the startup time of the crystal used. Power consumption can be reduced in stop mode by disabling either or both of these functions via the SYNCR[STMPD] bits. The external CLKOUT signal may be enabled during low-power stop (if the PLL is still enabled) to support systems using this signal as the clock source. The system clocks may be enabled during wakeup from stop mode without waiting for the PLL to lock. This eliminates the wakeup recovery time, but at the risk of sending a potentially unstable clock to the system. It is recommended, if this option is used, that the PLL frequency divider is set so that the targeted system frequency is no more than half the maximum allowed. This will allow for any frequency overshoot of the PLL while still keeping the system clock within specification. In external clock mode, there are no wait times for the OSC startup or PLL lock. During wakeup from stop mode, the Flash clock will always clock through 16 cycles before the system clocks are enabled. This allows the Flash module time to recover from the low-power mode. Thus, software may immediately continue to fetch instructions from the Flash memory. The external CLKOUT output pin may be disabled in the low state to lower power consumption via the DISCLK bit in the SYNCR. The external CLKOUT pin function is enabled by default at reset. 7.3.2.18 Edge Port In wait and doze modes, the edge port continues to operate normally and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes. In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit the stop mode. 7.3.2.19 Watchdog Timer In stop mode (or in wait/doze mode, if so programmed), the watchdog ceases operation and freezes at the current value. When exiting these modes, the watchdog resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation. When not stopped, the watchdog may generate a reset to exit the low-power modes. 7.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3) In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation. When not stopped, the PIT may generate an interrupt to exit the low-power modes. 7-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.3.2.17 Power Management Queued Analog-to-Digital Converter (QADC) Setting the queued analog-to-digital converter (QADC) stop bit (QSTOP) will disable the QADC. The QADC is unaffected by either wait or doze mode and may generate an interrupt to exit these modes. Low-power stop mode (or setting the QSTOP bit), immediately freezes operation, register values, state machines, and external pins. This stops the clock signals to the digital electronics of the module and eliminates the quiescent current draw of the analog electronics. Any conversion sequences in progress are stopped. Exit from low-power stop mode (or clearing the QSTOP bit), returns the QADC to operation from the state prior to stop mode entry, but any conversions in progress are undefined and the QADC requires recovery time to stabilize the analog circuits before new conversions can be performed. 7.3.2.22 General Purpose Timers (GPTA and GPTB) When not stopped, the General Purpose Timers may generate an interrupt to exit the low-power modes. Clearing the timer enable bit (TE) in the GPT system control register 1 (GPTSCR1) or the pulse accumulator enable bit (PAE) in the GPT pulse accumulator control register (GPTPACTL) disables timer functions. Timer and pulse accumulator registers are still accessible by the CPU and BDM interface, but the remaining functions of the timer are disabled. The timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. In stop mode, the General Purpose Timers stop immediately and freeze their operation, register values, state machines, and external pins. Upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset. 7.3.2.23 FlexCAN When enabled, the FlexCAN module is capable of generating interrupts and bringing the device out of a low-power mode. The module has 35 interrupt sources (32 sources due to message buffers and 3 sources due to Bus-off, Error and Wake-up). When in stop mode, a recessive to dominant transition on the CAN bus causes the WAKE-INT bit in the error & status register to be set. This event can cause a CPU interrupt if the WAKE-MASK bit in module configuration register (MCR) is set. When setting stop mode in the FlexCAN (by setting the MCR[STOP] bit), the FlexCAN checks for the CAN bus to be either idle or waits for the third bit of intermission and checks to see if it is recessive. When this condition exists, the FlexCAN waits for all internal activity other than in the CAN bus interface to complete and then the following occurs: • The FlexCAN shuts down its clocks, stopping most of the internal circuits, to achieve maximum possible power saving. • The internal bus interface logic continues operation, enabling CPU to access the MCR register. • The FlexCAN ignores its Rx input pin, and drives its Tx pins as recessive. • FlexCAN loses synchronization with the CAN bus, and STOP_ACK and NOT_RDY bits in MCR register are set. Exiting stop mode is done in one of the following ways: • Reset the FlexCAN (either by hard reset or by asserting the SOFT_RST bit in MCR). • Clearing the STOP bit in the MCR. Freescale Semiconductor 7-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 7.3.2.21 • Self-wake mechanism. If the SELF-WAKE bit in the MCR is set at the time the FlexCAN enters stop mode, then upon detection of recessive to dominant transition on the CAN bus, the FlexCAN resets the STOP bit in the MCR and resumes its clocks. Recommendations for, and features of, FlexCAN’s stop mode operation are as follows: • Upon stop/self-wake mode entry, the FlexCAN tries to receive the frame that caused it to wake; that is, it assumes that the dominant bit detected is a start-of-frame bit. It does not arbitrate for the CAN bus then. • Before asserting stop Mode, the CPU should disable all interrupts in the FlexCAN, otherwise it may be interrupted while in stop mode upon a non-wake-up condition. If desired, the WAKE-MASK bit should be set to enable the WAKE-INT. • If stop mode is asserted while the FlexCAN is BUSOFF (see error and status register), then the FlexCAN enters stop mode and stops counting the synchronization sequence; it continues this count once stop mode is exited. • The correct flow to enter stop mode with SELF-WAKE: — assert SELF-WAKE at the same time as STOP. — wait for STOP_ACK bit to be set. • The correct flow to negate STOP with SELF-WAKE: — negate SELF-WAKE at the same time as STOP. — wait for STOP_ACK negation. • SELF-WAKE should be set only when the MCR[STOP] bit is negated and the FlexCAN is ready; that is, the NOT_RDY bit in the MCR is negated. • If STOP and SELF_WAKE are set and if a recessive to dominant edge immediately follows on the CAN bus, the STOP_ACK bit in the MCR may never be set, and the STOP bit in the MCR is reset. • If the user does not want to have old frames sent when the FlexCAN is awakened (STOP with Self-Wake), the user should disable all Tx sources, including remote-response, before stop mode entry. • If halt mode is active at the time the STOP bit is set, then the FlexCAN assumes that halt mode should be exited; hence it tries to synchronize to the CAN bus (11 consecutive recessive bits), and only then does it search for the correct conditions to stop. • Trying to stop the FlexCAN immediately after reset is allowed only after basic initialization has been performed. If stop with self-wake is activated, and the FlexCAN operates with single system clock per time-quanta, then there are extreme cases in which FlexCAN's wake-up upon recessive to dominant edge may not conform to the standard CAN protocol, in the sense that the FlexCAN synchronization is shifted one time quanta from the required timing. This shift lasts until the next recessive to dominant edge, which re-synchronizes the FlexCAN back to conform to the protocol. The same holds for auto-power save mode upon wake-up by recessive to dominant edge. The auto-power save mode in the FlexCAN is intended to enable NORMAL operation with optimized power saving. Upon setting the AUTO POWER SAVE bit in the MCR register, the FlexCAN looks for a set of conditions in which there is no need for clocks to run. If all these conditions are met, then the FlexCAN stops its clocks, thus saving power. While its clocks are stopped, if any of the conditions below is not met, the FlexCAN resumes its clocks. It then continues to monitor the conditions and stops/resumes its clocks appropriately. The following are conditions for the automatic shut-off of FlexCAN clocks: • No Rx/Tx frame in progress. • No moving of Rx/Tx frames between SMB and MB and no Tx frame is pending for transmission in any MB. 7-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Power Management • • No host access to the FlexCAN module. The FlexCAN is neither in halt mode (MCR bit 8), in stop mode (MCT bit 15), nor in BUSOFF. 7.3.2.24 ColdFire Flash Module The ColdFire Flash Control Module is capable of generating interrupts by the setting of the CBEIF or CCIF bits in the CFMUSTAT. These interrupt sources, however, should not occur when the device is in a low-power mode as long as no Flash operation was in progress when the low-power mode was entered. When performing a program or erase operation on the Flash, if a command is active (CCIF = 0) when the MCU enters a low-power mode, the command sequence monitor will perform the following: 1. The command in progress will be aborted. 2. The Flash high voltage circuitry will be switched off and any pending command (CBEIF = 0) will not be executed when the MCU exits low-power mode. 3. The CCIF and ACCERR flags will be set if a command is active when the MCU enters low-power mode. NOTE The state of any longword(s) being programmed, or any erase pages/physical blocks being erased, is not guaranteed if the MCU enters stop mode with a command in progress. Active commands are immediately aborted when the MCU enters stop mode. Do not execute the STOP instruction during program and erase operations. 7.3.2.25 BDM Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to exit any low-power mode. 7.3.2.26 JTAG The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode. Toggling TCLK during any low-power mode will increase the system current consumption. 7.3.3 Summary of Peripheral State During Low-Power Modes The functionality of each of the peripherals and CPU during the various low-power modes is summarized in Table 7-7. The status of each peripheral during a given mode refers to the condition the peripheral automatically assumes when the STOP instruction is executed and the LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be disabled by programming its dedicated control bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the CPU into run mode. Freescale Semiconductor 7-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Power Management Power Management Peripheral Status1 / Wakeup Capability Module Wait Mode Doze Mode Stop Mode CPU Stopped No Stopped No Stopped No SRAM Stopped No Stopped No Stopped No Flash Stopped No Stopped No Stopped No Flash Control Module Enabled Yes2 Enabled Yes2 Stopped No System Integration Module Enabled Yes 3 Enabled Yes 3 Stopped No SDRAM Controller Enabled No Enabled No Stopped No Chip Select Module Enabled No Enabled No Stopped No DMA Controller Enabled Yes Enabled Yes Stopped No UART0, UART1 and UART2 Enabled Yes2 Enabled Yes2 Stopped No I2C Module Enabled Yes2 Enabled Yes2 Stopped No QSPI Enabled Yes2 Enabled Yes2 Stopped No DMA Timers Enabled Yes2 Enabled Yes2 Stopped No Interrupt controller Enabled Yes2 Enabled Yes2 Enabled Yes2 Fast Ethernet Controller Enabled Yes2 Enabled Yes2 Stopped No I/O Ports Enabled No Enabled No Enabled No Reset Controller Enabled Yes3 Enabled Yes3 Enabled Yes3 Chip Configuration Module Enabled No Enabled No Stopped No Power Management Enabled No Enabled No Stopped No Clock Module Enabled Yes2 Enabled Yes2 Program Yes2 Edge port Enabled Yes2 Enabled Yes2 Stopped Yes2 Watchdog timer Program Yes 3 Program Yes 3 Stopped No Programmable Interrupt Timers Enabled Yes2 Program Yes2 Stopped No QADC Enabled Yes2 Program Yes2 Stopped No General Purpose Timers Enabled Yes2 Enabled Yes2 Stopped No FlexCAN Enabled Yes2 Enabled Yes2 Stopped No BDM Enabled Yes4 Enabled Yes4 Enabled Yes4 JTAG Enabled No Enabled No Enabled No 1 “Program” Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the peripheral register map. 2 These modules can generate a interrupt which will exit a low-power mode. The CPU will begin to service the interrupt exception after wakeup. 3 These modules can generate a reset which will exit any low-power mode. 7-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 7-7. CPU and Peripherals in Low-Power Modes 4 The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. Freescale Semiconductor 7-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Power Management Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Power Management 7-16 Freescale Semiconductor This section details the functionality of the System Control Module (SCM) which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit core watchdog timer (CWT), and the system control registers and logic. Specifically, the system control includes the internal peripheral system (IPS) base address register (IPSBAR), the processor’s dual-port RAM base address register (RAMBAR), and system control registers that include the core watchdog timer control. 8.1 Overview The SCM provides the control and status for a variety of functions including base addressing and address space masking for both the IPS peripherals and resources (IPSBAR) and the ColdFire core memory spaces (RAMBAR). The CPU core supports two memory banks, one for the internal SRAM and the other for the internal Flash. The SACU provides the mechanism needed to implement secure bus transactions to the system address space. The programming model for the system bus arbitration resides in the SCM. The SCM sources the necessary control signals to the arbiter for bus master management. The CWT provides a means of preventing system lockup due to uncontrolled software loops via a special software service sequence. If periodic software servicing action does not occur, the CWT times out with a programmed response (interrupt) to allow recovery or corrective action to be taken. 8.2 Features The SCM includes these distinctive features: • IPS base address register (IPSBAR) — Base address location for 1-Gbyte peripheral space — User control bits • Processor-local memory base address register (RAMBAR) • System control registers — Core reset status register (CRSR) indicates type of last reset — Core watchdog control register (CWCR) for watchdog timer control — Core watchdog service register (CWSR) to service watchdog timer • System bus master arbitration programming model (MPARK) • System access control unit (SACU) programming model — Master privilege register (MPR) — Peripheral access control registers (PACRs) — Grouped peripheral access control registers (GPACR0, GPACR1) Freescale Semiconductor 8-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 8 System Control Module (SCM) System Control Module (SCM) Memory Map and Register Definition The memory map for the SCM registers is shown in Table 8-1. All the registers in the SCM are memory-mapped as offsets within the 1 Gbyte IPS address space and accesses are controlled to these registers by the control definitions programmed into the SACU. Table 8-1. SCM Register Map IPSBAR Offset [31:24] [23:16] 0x00_0000 IPSBAR 0x00_0004 — 0x00_0008 RAMBAR 0x00_000C — 0x00_0010 CRSR CWCR 0x00_0018 8.4.1 LPICR1 CWSR MPARK MPR — 0x00_0024 PACR0 PACR1 PACR2 PACR3 0x00_0028 PACR4 — PACR5 PACR6 0x00_002c PACR7 — PACR8 — 0x00_0030 GPACR0 GPACR1 — — 0x00_0034 — — — — 0x00_0038 — — — — 0x00_003C — — — — 1 8.4 [7:0] — 0x00_001C 0x00_0020 [15:8] The LPICR is described in Chapter 7, “Power Management." Register Descriptions Internal Peripheral System Base Address Register (IPSBAR) The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the on-chip peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal modules can be moved by loading a different value into the IPSBAR at a later time. NOTE Accessing reserved IPSBAR memory space could result in an unterminated bus cycle that causes the core to hang. Only a hard reset will allow the core to recover from this state. Therefore, all bus accesses to IPSBAR space should fall within a module’s memory map space. If an address “hits” in overlapping memory regions, the following priority is used to determine what memory is accessed: 1. IPSBAR 2. RAMBAR 3. Cache 4. SDRAM 8-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 8.3 System Control Module (SCM) NOTE This is the list of memory access priorities when viewed from the processor core. See Figure 8-1 and Table 8-2 for descriptions of the bits in IPSBAR. 31 30 29 16 Field BA31 BA30 Reset 0 — 1 — R/W R/W 15 1 0 Field — V Reset — 1 R/W R/W Address IPSBAR + 0x000 Figure 8-1. IPS Base Address Register (IPSBAR) Table 8-2. IPSBAR Field Description Bits Name Description 31–30 BA Base address. Defines the base address of the 1-Gbyte internal peripheral space. This is the starting address for the IPS registers when the valid bit is set. 29–1 — Reserved, should be cleared. 0 V Valid. Enables/disables the IPS Base address region. V is set at reset. 0 IPS Base address is not valid. 1 IPS Base address is valid. 8.4.2 Memory Base Address Register (RAMBAR) The processor supports dual-ported local SRAM memory. This processor-local memory can be accessed directly by the core and/or other system bus masters. Since this memory provides single-cycle accesses at processor speed, it is ideal for applications where double-buffer schemes can be used to maximize system-level performance. For example, a DMA channel in a typical double-buffer (also known as a ping-pong scheme) application may load data into one portion of the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM. Once the processor completes the data calculations, it begins processing the just-loaded buffer while the DMA moves out the just-calculated data from the other buffer, and reloads the next data block into the just-freed memory region. The process repeats with the processor and the DMA “ping-ponging” between alternate regions of the dual-ported SRAM. The processor design implements the dual-ported SRAM in the memory space defined by the RAMBAR register. There are two physical copies of the RAMBAR register: one located in the processor core and accessible only via the privileged MOVEC instruction at CPU space address 0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this memory are controlled by the processor-local copy of the RAMBAR, while module accesses are enabled by the SCM's RAMBAR. Freescale Semiconductor 8-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 5. Chip Selects The physical base address programmed in both copies of the RAMBAR is typically the same value; however, they can be programmed to different values. By definition, the base address must be a 0-modulo-size value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Reset 0000_0000_0000_0000 R/W R/W 15 Field 10 — 9 8 0 BDE Reset — 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x008 Figure 8-2. Memory Base Address Register (RAMBAR) Table 8-3. RAMBAR Field Description Bits Name Description 31–16 BA Base address. Defines the memory module's base address on a 64-Kbyte boundary corresponding to the physical array location within the 4 Gbyte address space supported by ColdFire. 15–10 — Reserved, should be cleared. 9 BDE 8–0 — Back door enable. Qualifies the module accesses to the memory. 0 Disables module accesses to the memory. 1 Enables module accesses to the memory. NOTE: The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to the SRAM. For more information, see Section 5.3.1, “SRAM Base Address Register (RAMBAR).” Reserved, should be cleared. The SRAM modules are configured through the RAMBAR shown in Figure 8-2. • RAMBAR specifies the base address of the SRAM. • All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and return zeros when read. • The back door enable bit, RAMBAR[BDE], is cleared at reset, disabling the module access to the SRAM. NOTE The RAMBAR default value of 0x0000_0000 is invalid. The RAMBAR located in the processor’s CPU space must be initialized with the valid bit set before the CPU (or modules) can access the on-chip SRAM (see Chapter 5, “Static RAM (SRAM)” for more information. For details on the processor's view of the local SRAM memories, see Section 5.3.1, “SRAM Base Address Register (RAMBAR).” 8-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 System Control Module (SCM) System Control Module (SCM) Core Reset Status Register (CRSR) The CRSR contains a bit for two of the reset sources to the CPU. A bit set to 1 indicates the last type of reset that occurred. The CRSR is updated by the control logic when the reset is complete. Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent reset. To clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect. NOTE The reset status register (RSR) in the reset controller module (see Chapter 29, “Reset Controller Module”) provides indication of all reset sources except the core watchdog timer. 7 Field 6 5 4 0 EXT Reset — See Note R/W R/W Address IPSBAR + 0x010 Note: The reset value of EXT and CWDR depend on the last reset source. All other bits are initialized to zero. Figure 8-3. Core Reset Status Register (CRSR) Table 8-4. CRSR Field Descriptions Bits Name Description 7 EXT External reset. 1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the processor core to initiate reset exception processing. All registers are forced to their initial state. 6-0 — 8.4.4 Reserved. Core Watchdog Control Register (CWCR) The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE]. By default it is disabled. If enabled, the watchdog timer requires the periodic execution of a core watchdog servicing sequence. If this periodic servicing action does not occur, the timer times out, resulting in a watchdog timer interrupt. If the timer times out and the core watchdog transfer acknowledge enable bit (CWCR[CWTA]) is set, a watchdog timer interrupt is asserted. If a core watchdog timer interrupt acknowledge cycle has not occurred after another timeout, CWT TA is asserted in an attempt to allow the interrupt acknowledge cycle to proceed by terminating the bus cycle. The setting of CWCR[CWTAVAL] indicates that the watchdog timer TA was asserted. NOTE The core watchdog timer is available to provide compatibility with the watchdog timer implemented on previous ColdFire devices. However, there is a second watchdog timer available that has new features. See Chapter 18, “Watchdog Timer Module” for more information. Freescale Semiconductor 8-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 8.4.3 When the core watchdog timer times out and CWCR[CWRI] is programmed for a software reset, an internal reset is asserted and CRSR[CWDR] is set. To prevent the core watchdog timer from interrupting or resetting, the CWSR must be serviced by performing the following sequence: 1. Write 0x55 to CWSR. 2. Write 0xAA to the CWSR. Both writes must occur in order before the time-out, but any number of instructions can be executed between the two writes. This order allows interrupts and exceptions to occur, if necessary, between the two writes. Caution should be exercised when changing CWCR values after the software watchdog timer has been enabled with the setting of CWCR[CWE], because it is difficult to determine the state of the core watchdog timer while it is running. The countdown value is constantly compared with the time-out period specified by CWCR[CWT]. The following steps must be taken to change CWT: 1. Disable the core watchdog timer by clearing CWCR[CWE]. 2. Reset the counter by writing 0x55 and then 0xAA to CWSR. 3. Update CWCR[CWT]. 4. Re-enable the core watchdog timer by setting CWCR[CWE]. This step can be performed in step 3. The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer transfer acknowledge. The register can be read at any time, but can be written only if the CWT is not pending. At system reset, the software watchdog timer is disabled. Field 7 6 5 CWE CWRI Reset 3 CWT[2:0] 2 1 0 CWTA CWTAVAL CWTIC 0000_0000 R/W R/W Address IPSBAR + 0x011 Figure 8-4. Core Watchdog Control Register (CWCR) Table 8-5. CWCR Field Description 8-6 Bits Name Description 7 CWE Core watchdog enable. 0 SWT disabled. 1 SWT enabled. 6 CWRI Core watchdog reset/interrupt select. 0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is programmed in the interrupt control register 8 (ICR8) of INTC0. 1 Reserved; do not use. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 System Control Module (SCM) System Control Module (SCM) 5–3 2 1 0 8.4.5 CWT[2:0] CWTA Core watchdog timing delay. These bits select the timeout period for the CWT. At system reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is disabled (CWCR[CWE] = 0). CWT CWT Time-Out Period CWT CWT Time-Out Period 000 29 Bus clock frequency 100 219 Bus clock frequency 001 211 Bus clock frequency 101 223 Bus clock frequency 010 213 Bus clock frequency 110 227 Bus clock frequency 011 215 Bus clock frequency 111 231 Bus clock frequency Core watchdog transfer acknowledge enable. 0 CWTA Transfer acknowledge disabled. 1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the unacknowledged assertion of the CWT interrupt, the transfer acknowledge asserts, which allows CWT to terminate a bus cycle and allow the interrupt acknowledge to occur. CWTAVAL Core watchdog transfer acknowledge valid. 0 CWTA Transfer Acknowledge has not occurred. 1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit. CWTIF Core watchdog timer interrupt flag. 0 CWT interrupt has not occurred 1 CWT interrupt has occurred. Write a 1 to clear the interrupt request. Core Watchdog Service Register (CWSR) The software watchdog service sequence must be performed using the CWSR as a data register to prevent a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55 followed by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but any number of instructions or accesses to the CWSR can be executed between the two writes. If the CWT has already timed out, writing to this register has no effect in negating the CWT interrupt. Figure 8-5 illustrates the CWSR. At system reset, the contents of CWSR are uninitialized. 7 0 Field CWSR[7:0] Reset Uninitialized R/W R/W Address IPSBAR + 0x013 Figure 8-5. Core Watchdog Service Register (CWSR) 8.5 Internal Bus Arbitration The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic that controls which of up to four MBus masters (M0–M3 in Figure 8-6) has access to the external buses. The function of the arbitration logic is described in this section. Freescale Semiconductor 8-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 8-5. CWCR Field Description (continued) “back door” to SRAM and Flash SRAM1 MPARK RAMBAR CPU M0 DMA M2 Internal Bus Master M1 EIM MARB Internal Modules FEC SDRAMC *Not used on MCF5214/16 M3 Figure 8-6. Arbiter Module Functions 8.5.1 Overview The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the following attributes: • The master pointed to by the current arbitration pointer may get on the bus with zero latency if the address phase is available. All other requesters face at least a one cycle arbitration pipeline delay in order to meet bus timing constraints on address phase hold. • If a requester will get an immediate address phase (that is, it is pointed to by the current arbitration pointer and the bus address phase is available), it will be the current bus master and is ignored by arbitration. All remaining requesting ports are evaluated by the arbitration algorithm to determine the next-state arbitration pointer. • There are two arbitration algorithms, fixed and round-robin. Fixed arbitration sets the next-state arbitration pointer to the highest priority requester. Round-robin arbitration sets the next-state arbitration pointer to the highest priority requester (calculated by adding a requester's fixed priority to the current bus master’s fixed priority and then taking this sum modulo the number of possible bus masters). • The default priority is FEC (M3) > DMA (M2) > internal master (M1) > CPU (M0), where M3 is the highest and M0 the lowest priority. M3 is not used for the MCF5216 and MCF5214. • There are two actions for an idle arbitration cycle, either leave the current arbitration pointer as is or set it to the lowest priority requester. • The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm to round-robin if any requester has been held for longer than a specified cycle count. 8-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 System Control Module (SCM) System Control Module (SCM) Arbitration Algorithms There are two modes of arbitration: fixed and round-robin. This section discusses the differences between them. 8.5.2.1 Round-Robin Mode Round-robin arbitration is the default mode after reset. This scheme cycles through the sequence of masters as specified by MPARK[Mn_PRTY] bits. Upon completion of a transfer, the master is given the lowest priority and the priority for all other masters is increased by one. M3 = 11 M2 =01 M1 = 10 M0 = 00 next +1 M3 = 00 M2 =10 M1 = 11 M0 = 01 next +2 M3 = 01 M2 =11 M1 = 00 M0 = 10 next +3 M3 = 10 M2 =00 M1 = 01 M0 = 11 If no masters are requesting, the arbitration unit must “park”, pointing at one of the masters. There are two possibilities, park the arbitration unit on the last active master, or park pointing to the highest priority master. Setting MPARK[PRK_LAST] causes the arbitration pointer to be parked on the highest priority master. In round-robin mode, programming the timeout enable and lockout bits MPARK[13,11:8] will have no effect on the arbitration. 8.5.2.2 Fixed Mode In fixed arbitration the master with highest priority (as specified by the MPARK[Mn_PRTY] bits) will win the bus. That master will relinquish the bus when all transfers to that master are complete. If MPARK[TIMEOUT] is set, a counter will increment for each master for every cycle it is denied access. When a counter reaches the limit set by MPARK[LCKOUT_TIME], the arbitration algorithm will be changed to round-robin arbitration mode until all locks are cleared. The arbitration will then return to fixed mode and the highest priority master will be granted the bus. As in round-robin mode, if no masters are requesting, the arbitration pointer will park on the highest priority master if MPARK[PRK_LAST] is set, or will park on the master which last requested the bus if cleared. 8.5.3 Bus Master Park Register (MPARK) The MPARK controls the operation of the system bus arbitration module. The platform bus master connections are defined as: • Master 3 (M3): Fast Ethernet Controller (Not used for the MCF5216 and MCF5214) • Master 2 (M2): 4-channel DMA • Master 1 (M1): Internal Bus Master (not used in normal user operation) • Master 0 (M0): V2 ColdFire Core Freescale Semiconductor 8-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 8.5.2 31 26 Field — 25 23 22 21 20 19 18 17 16 M2_P_EN BCR24BIT M3_PRTY M2_PRTY M0_PRTY M1_PRTY Reset 0011_0000_1110_0001 R/W Field 24 R/W 15 14 — FIXED Reset 13 12 TIMEOUT PRKLAST 11 8 7 LCKOUT_TIME 0 — 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x01C Figure 8-7. Default Bus Master Park Register (MPARK) Table 8-6. MPARK Field Description 8-10 Bits Name Description 31–26 — 25 M2_P_EN DMA bandwith control enable 0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests. 1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests. 24 BCR24BIT Enables the use of 24 bit byte count registers in the DMA module 0 DMA BCRs function as 16 bit counters. 1 DMA BCRs function as 24 bit counters. 23–22 M3_PRTY Master priority level for master 3 (Fast Ethernet Controller) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority Note: Reserved on the MCF5214 and MCF5216 21–20 M2_PRTY Master priority level for master 2 (DMA Controller) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 19–18 M0_PRTY Master priority level for master 0 (ColdFire Core) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 17–16 M1_PRTY Master priority level for master 1 (Not used in user mode) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 15 — Reserved, should be cleared. Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 System Control Module (SCM) System Control Module (SCM) Bits Name 14 FIXED 13 TIMEOUT Timeout Enable 0 disable count for when a master is locked out by other masters. 1 enable count for when a master is locked out by other masters and allow access when LCKOUT_TIME is reached. 12 PRKLAST Park on the last active master or highest priority master if no masters are active 0 park on last active master 1 park on highest priority master 11–8 7–0 Description Fixed or round robin arbitration 0 round robin arbitration 1 fixed arbitration LCKOUT_TIME Lock-out Time. Lock-out time for a master being denied the bus. The lock out time is defined as 2^ LCKOUT_TIME[3:0]. — Reserved, should be cleared. The initial state of the master priorities is M3 > M2 > M1 > M0. System software should guarantee that the programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities. NOTE The M1_PRTY field should not be set for a priority higher than third (default). 8.6 System Access Control Unit (SACU) This section details the functionality of the System Access Control Unit (SACU) which provides the mechanism needed to implement secure bus transactions to the address space mapped to the internal modules. 8.6.1 Overview The SACU supports the traditional model of two privilege levels: supervisor and user. Typically, memory references with the supervisor attribute have total accessibility to all the resources in the system, while user mode references cannot access system control and configuration registers. In many systems, the operating system executes in supervisor mode, while application software executes in user mode. The SACU further partitions the access control functions into two parts: one control register defines the privilege level associated with each bus master, and another set of control registers define the access levels associated with the peripheral modules and the memory space. The SACU’s programming model is physically implemented as part of the System Control Module (SCM) with the actual access control logic included as part of the arbitration controller. Each bus transaction targeted for the IPS space is first checked to see if its privilege rights allow access to the given memory space. If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an exception, and the targeted module not accessed. Freescale Semiconductor 8-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 8-6. MPARK Field Description (continued) System Control Module (SCM) Features Each bus transfer can be classified by its privilege level and the reference type. The complete set of access types includes: • Supervisor instruction fetch • Supervisor operand read • Supervisor operand write • User instruction fetch • User operand read • User operand write Instruction fetch accesses are associated with the execute attribute. It should be noted that while the bus does not implement the concept of reference type (code versus data) and only supports the user/supervisor privilege level, the reference type attribute is supported by the system bus. Accordingly, the access checking associated with both privilege level and reference type is performed in the IPS controller using the attributes associated with the reference from the system bus. The SACU partitions the access control mechanisms into three distinct functions: • Master privilege register (MPR) — Allows each bus master to be assigned a privilege level: – Disable the master’s user/supervisor attribute and force to user mode access – Enable the master’s user/supervisor attribute — The reset state provides supervisor privilege to the processor core (bus master 0). — Input signals allow the non-core bus masters to have their user/supervisor attribute enabled at reset. This is intended to support the concept of a trusted bus master, and also controls the ability of a bus master to modify the register state of any of the SACU control registers; that is, only trusted masters can modify the control registers. • Peripheral access control registers (PACRs) — Nine 8-bit registers control access to 17 of the on-chip peripheral modules. — Provides read/write access rights, supervisor/user privilege levels — Reset state provides supervisor-only read/write access to these modules — Grouped peripheral access control registers (GPACR0, GPACR1) — One single register (GPACR0) controls access to 14 of the on-chip peripheral modules — One register (GPACR1) controls access for IPS reads and writes to the Flash module — Provide read/write/execute access rights, supervisor/user privilege levels — Reset state provides supervisor-only read/write access to each of these peripheral spaces 8.6.3 Memory Map/Register Definition The memory map for the SACU program-visible registers within the System Control Module (SCM) is shown in Figure 8-7. The MPR, PACR, and GPACRs are 8 bits in width. 8-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 8.6.2 System Control Module (SCM) IPSBA R Offset [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] — — — — — — 0x020 MPR 0x024 PACR0 PACR1 PACR2 PACR3 0x028 PACR4 — PACR5 PACR6 0x02c PACR7 — PACR8 — 0x030 GPACR0 GPACR1 — — 0x034 — — — — 0x038 — — — — 0x03C — — — — 8.6.3.1 Master Privilege Register (MPR) The MPR specifies the access privilege level associated with each bus master in the platform. The register provides one bit per bus master, where bit 3 corresponds to master 3 (Fast Ethernet Controller, not used on MCF5216 and MCF5214), bit 2 to master 2 (DMA Controller), bit 1 to master 1 (internal bus master), and bit 0 to master 0 (ColdFire core). 7 Field 0 — Reset MPR[3:0] 0000_0011 R/W R/W Address IPSBAR + 0x020 Figure 8-8. Master Privilege Register (MPR) Table 8-8. MPR[n] Field Descriptions Bits Name 7–4 — 3–0 MPR Description Reserved. Should be cleared. Each 1-bit field defines the access privilege level of the given bus master n. 0 All bus master accesses are in user mode. 1 All bus master accesses use the sourced user/supervisor attribute. Only trusted bus masters can modify the access control registers. If a non-trusted bus master attempts to write any of the SACU control registers, the access is aborted with an error termination and the registers remain unaffected. The processor core is connected to bus master 0 and is always treated as a trusted bus master. Accordingly, MPR[0] is forced to 1 at reset. 8.6.3.2 Peripheral Access Control Registers (PACR0–PACR8) Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single PACR defines the access level for each of the two modules. These modules only support operand reads Freescale Semiconductor 8-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 8-7. SACU Register Memory Map and writes. Each PACR follows the format illustrated in Figure 8-9. For a list of PACRs and the modules that they control, refer to Table 8-11. 7 Field 6 4 LOCK1 3 ACCESS_CTRL1 Reset 2 LOCK0 0 ACCESS_CTRL0 0000_0000 R/W R/W Address IPSBAR + 0x24 + Offset Figure 8-9. Peripheral Access Control Register (PACRn) Table 8-9. PACR Field Descriptions Bits Name Description 7 LOCK1 This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to the PACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag. 6–4 ACCESS_CTRL1 This 3-bit field defines the access control for the given platform peripheral. The encodings for this field are shown in Table 8-10. 3 LOCK0 This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to the PACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag. 2–0 ACCESS_CTRL0 This 3-bit field defines the access control for the given platform peripheral. The encodings for this field are shown in Table 8-10. Table 8-10. PACR ACCESSCTRL Bit Encodings Bits Supervisor Mode User Mode 000 Read/Write No Access 001 Read No Access 010 Read Read 011 Read No Access 100 Read/Write Read/Write 101 Read/Write Read 110 Read/Write Read/Write 111 No Access No Access Table 8-11. Peripheral Access Control Registers (PACRs) Modules Controlled IPSBAR Offset 8-14 Name ACCESS_CTRL1 ACCESS_CTRL0 0x024 PACR0 SCM SDRAMC 0x025 PACR1 EIM DMA 0x026 PACR2 UART0 UART1 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 System Control Module (SCM) System Control Module (SCM) Modules Controlled IPSBAR Offset Name ACCESS_CTRL1 ACCESS_CTRL0 PACR3 UART2 — 0x028 PACR4 2 I C QSPI 0x029 — — — 0x02a PACR5 DTIM0 DTIM1 0x02b PACR6 DTIM2 DTIM3 0x02c PACR7 INTC0 INTC1 0x02d — — — 0x02e PACR8 FEC0 — 0x027 At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. If an instruction fetch access to any of these peripheral modules is attempted, the IPS bus cycle is immediately terminated with an error. 8.6.3.3 Grouped Peripheral Access Control Registers (GPACR0 & GPACR1) The on-chip peripheral space starting at IPSBAR is subdivided into sixteen 64-Mbyte regions. Each of the first two regions has a unique access control register associated with it. The other fourteen regions are in reserved space; the access control registers for these regions are not implemented. Bits [29:26] of the address select the specific GPACRn to be used for a given reference within the IPS address space. These access control registers are 8 bits in width so that read, write, and execute attributes may be assigned to the given IPS region. NOTE The access control for modules with memory space protected by PACR0–PACR8 are determined by the PACR0–PACR8 settings. The access control is not affected by GPACR0, even though the modules are mapped in its 64-Mbyte address space. Field 7 6–4 LOCK — Reset Read/Write Address 3 0 ACCESS_CTRL 0000_0000 R/W R R/W IPSBAR + 0x030, IPSBAR + 0x31 Figure 8-10. Grouped Peripheral Access Control Register (GPACR) Freescale Semiconductor 8-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 8-11. Peripheral Access Control Registers (PACRs) (continued) System Control Module (SCM) Bits Name Description 7 LOCK This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the GPACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag. 6–4 — 3–0 Reserved, should be cleared. ACCESS_CTRL This 4-bit field defines the access control for the given memory region. The encodings for this field are shown in Table 8-13. At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. Bit encodings for the ACCESS_CTRL field in the GPACR are shown in Table 8-13. Table 8-14 shows the memory space protected by the GPACRs and the modules mapped to these spaces. Table 8-13. GPACR ACCESS_CTRL Bit Encodings Bits 8-16 Supervisor Mode User Mode 0000 Read / Write No Access 0001 Read No Access 0010 Read Read 0011 Read No Access 0100 Read / Write Read / Write 0101 Read / Write Read 0110 Read / Write Read / Write 0111 No Access No Access 1000 Read / Write / Execute No Access 1001 Read / Execute No Access 1010 Read / Execute Read / Execute 1011 Execute No Access 1100 Read / Write / Execute Read / Write / Execute 1101 Read / Write / Execute Read / Execute 1110 Read / Write Read 1111 Read / Write / Execute Execute Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 8-12. GPACR Field Descriptions System Control Module (SCM) Register Space Protected (IPSBAR Offset) Modules Protected GPACR0 0x0000_0000– 0x03FF_FFFF Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) GPACR1 0x0400_0000– 0x07FF_FFFF CFM (Flash module’s backdoor access for programming or access by a bus master other than the core) Note: Reserved for the MCF5280 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 8-14. GPACR Address Space 8-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 System Control Module (SCM) 8-18 Freescale Semiconductor The clock module configures the device for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly. The clock module contains: • Crystal amplifier and oscillator (OSC) • Phase-locked loop (PLL) • Reduced frequency divider (RFD) • Status and control registers • Control logic 9.1 Features Features of the clock module include: • 2- to 10-MHz reference crystal oscillator • Support for low-power modes • Separate clock out signal 9.2 Modes of Operation The clock module can be operated in normal PLL mode (default), 1:1 PLL mode, or external clock mode. 9.2.1 Normal PLL Mode In normal PLL mode, the PLL is fully programmable. It can synthesize frequencies ranging from 2x to 9x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the PLL. The PLL reference can be either a crystal oscillator or an external clock. 9.2.2 1:1 PLL Mode In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency. The post divider is not active. 9.2.3 External Clock Mode In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting operating frequency is equal to the external clock frequency. Freescale Semiconductor 9-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 9 Clock Module Clock Module Low-power Mode Operation This subsection describes the operation of the clock module in low-power and halted modes of operation. Low-power modes are described in Chapter 7, “Power Management.” Table 9-1 shows the clock module operation in low-power modes. Table 9-1. Clock Module Operation in Low-power Modes Low-power Mode Clock Operation Mode Exit Wait Clocks sent to peripheral modules only Exit not caused by clock module, but normal clocking resumes upon mode exit Doze Clocks sent to peripheral modules only Exit not caused by clock module, but normal clocking resumes upon mode exit Stop All system clocks disabled Exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit Halted Normal Exit not caused by clock module During wakeup from a low-power mode, the Flash clock always clocks through at least 16 cycles before the CPU clocks are enabled. This allows the Flash module time to recover from the low-power mode, and software can immediately resume fetching instructions from memory. In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the CPU, Flash, and SRAM are stopped. Each module can disable its clock locally at the module level. In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time. The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator can also be disabled during stop mode, but requires a wakeup period to restart. When the PLL is enabled in stop mode (STPMD[1:0]), the external CLKOUT signal can support systems using CLKOUT as the clock source. There is also a fast wakeup option for quickly enabling the system clocks during stop recovery. This eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system. To prevent a non-locked PLL frequency overshoot when using the fast wakeup option, change the RFD divisor to the current RFD value plus one before entering stop mode. In external clock mode, there are no wakeup periods for oscillator startup or PLL lock. 9.4 Block Diagram Figure shows a block diagram of the entire clock module. The PLL block in this diagram is expanded in detail in Figure 9-2. 9-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 9.3 CLKMOD[1:0] EXTAL XTAL EXTERNAL CLOCK PLLREF STOP MODE PLLSEL PLLMODE Freescale Semiconductor RSTOUT MFD LOCEN CLKGEN CLKOUT PLLMODE LOCKS REFERENCE CLOCK LOCK PLL LOCS OSC RFD[2:0] TO RESET MODULE LOLRE LOCRE STPMD[1:0] PLL CLOCK OUT SCALED PLL CLOCK OUT INTERNAL CLOCK CLKOUT DISCLK INTERNAL CLOCKS STOP MODE LOCK FWKUP Figure 9-1. Clock Module Block Diagram Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Clock Module . 9-3 CLKMOD[1:0] RSTOUT STPMD LOCKS LOCK DETECT LOCK LOLRE TO RESET MODULE PLLMODE LOCEN LOCRE LOSS OF CLOCK DETECT REFERENCE CLOCK LOCS PHASE AND FREQUENCY DETECT CHARGE PUMP FILTER VCO RFD[2:0] SCALED PLL CLOCK OUT PLLSEL DISCLK MDF[2:0] CLKOUT ÷ MFD (4–18) PLL CLOCK OUT Figure 9-2. PLL Block Diagram 9.5 Signal Descriptions The clock module signals are summarized in Table 9-2 and a brief description follows. For more detailed information, refer to Chapter 14, “Signal Descriptions.” Table 9-2. Signal Properties Name 9.5.1 Function EXTAL Oscillator or clock input XTAL Oscillator output CLKOUT System clock output CLKMOD[1:0] Clock mode select inputs RSTOUT Reset signal from reset controller EXTAL This input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. 9-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Clock Module Clock Module XTAL Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 9.5.2 This output is an internal oscillator connection to the external crystal. 9.5.3 CLKOUT This output reflects the internal system clock. 9.5.4 CLKMOD[1:0] These inputs are used to select the clock mode during chip configuration. 9.5.5 RSTOUT The RSTOUT pin is asserted by one of the following: • Internal system reset signal • FRCRSTOUT bit in the reset control status register (RCR); see Section 29.4.1, “Reset Control Register (RCR).” 9.6 Memory Map and Registers The clock module programming model consists of these registers: • Synthesizer control register (SYNCR), which defines clock operation • Synthesizer status register (SYNSR), which reflects clock status 9.6.1 Module Memory Map Table 9-3. Clock Module Memory Map 1 IPSBAR Offset Register Name Access1 0x0012_0000 Synthesizer Control Register (SYNCR) S 0x0012_0002 Synthesizer Status Register (SYNSR) S S = CPU supervisor mode access only. Freescale Semiconductor 9-5 Clock Module Register Descriptions This subsection provides a description of the clock module registers. 9.6.2.1 Synthesizer Control Register (SYNCR) Field 15 14 13 12 11 10 9 8 LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0 Reset 0010_0001 R/W Field R/W 7 6 5 4 3 2 1 0 LOCEN DISCLK FWKUP — STPMD1 STPMD0 — — Reset 0000_0000 R/W R/W Address R R/W R IPSBAR + 0x0012_0000 Figure 9-3. Synthesizer Control Register (SYNCR) Table 9-4. SYNCR Field Descriptions 9-6 Bit(s) Name Description 15 LOLRE Loss of lock reset enable. Determines how the system handles a loss of lock indication. When operating in normal mode or 1:1 PLL mode, the PLL must be locked before setting the LOLRE bit. Otherwise reset is immediately asserted. To prevent an immediate reset, the LOLRE bit must be cleared before writing the MFD[2:0] bits or entering stop mode with the PLL disabled. 1 Reset on loss of lock 0 No reset on loss of lock Note: In external clock mode, the LOLRE bit has no effect. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 9.6.2 Clock Module Bit(s) Name Description 14–12 MFD Multiplication Factor Divider. Contain the binary value of the divider in the PLL feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one. Note: In external clock mode, the MFD[2:0] bits have no effect. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 9-4. SYNCR Field Descriptions (continued) (( The following table illustrates the system frequency multiplier of the reference frequency1 in normal PLL mode. MFD[2:0] 0002 (4x) 001 (6x) 000 (÷ 1) 4 6 8 10 12 14 16 18 2)3 2 3 4 5 6 7 8 9 010 (÷ 4) 1 3/2 2 5/2 3 7/2 4 9/2 011 (÷ 8) 1/2 3/4 1 5/4 3/2 7/4 2 9/4 100 (÷ 16) 1/4 3/8 1/2 5/8 3/4 7/8 1 9/8 101 (÷ 32) 1/8 3/16 1/4 5/16 3/8 7/16 1/2 9/16 110 (÷ 64) 1/16 3/32 1/8 5/32 3/16 7/32 1/4 9/32 111 (÷ 128) 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64 RFD[2:0] 001 (÷ 1 010 011 100 101 110 111 (8x)(3) (10x) (12x) (14x) (16x) (18x) f ref × 2 ( MFD + 2 ) - ; f ref × 2 ( MFD + 2 ) ≤ f sys ( max ) ; f sys ≤ f sys ( max ) , f sys = --------------------------------------------RFD 2 where fsys(max) is the maximum system frequency for the particular MCF5282 device (66 MHz or 80 MHz). 2 MFD = 000 not valid for f ref < 3 MHz 3 Default value out of reset 11 LOCRE 10–8 RFD Freescale Semiconductor Loss-of-clock reset enable. Determines how the system handles a loss-of-clock condition. When the LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in SYNSR indicates a loss-of-clock condition, setting the LOCRE bit causes an immediate reset. To prevent an immediate reset, the LOCRE bit must be cleared before entering stop mode with the PLL disabled. 1 Reset on loss-of-clock 0 No reset on loss-of-clock Note: In external clock mode, the LOCRE bit has no effect. Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL frequency divisor. See table in MFD bit description. Changing RFD[2:0] does not affect the PLL or cause a relock delay. Changes in clock frequency are synchronized to the next falling edge of the current system clock. To avoid surpassing the allowable system operating frequency, write to RFD[2:0] only when the LOCK bit is set. 9-7 Clock Module Bit(s) Name 7 LOCEN Enables the loss-of-clock function. LOCEN does not affect the loss of lock function. 1 Loss-of-clock function enabled 0 Loss-of-clock function disabled Note: In external clock mode, the LOCEN bit has no effect. 6 DISCLK Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit holds CLKOUT low. 1 CLKOUT disabled 0 CLKOUT enabled 5 FWKUP Fast wakeup determines when the system clocks are enabled during wakeup from stop mode. 1 System clocks enabled on wakeup regardless of PLL lock status 0 System clocks enabled only when PLL is locked or operating normally Note: When FWKUP = 0, if the PLL or oscillator is enabled and unintentionally lost in stop mode, the PLL wakes up in self-clocked mode or reference clock mode depending on the clock that was lost. In external clock mode, the FWKUP bit has no effect on the wakeup sequence. 4 — 3–2 STPMD Description Reserved, should be cleared. Control PLL and CLKOUT operation in stop mode. The following table illustrates STPMD operation in stop mode. STPMD[1:0] 1–0 9.6.2.2 — Operation During Stop Mode System Clocks PLL OSC CLKOUT 00 Disabled Enabled Enabled Enabled 01 Disabled Enabled Enabled Disabled 10 Disabled Disabled Enabled Disabled 11 Disabled Disabled Disabled Disabled Reserved, should be cleared. Synthesizer Status Register (SYNSR) The SYNSR is a read-only register that can be read at any time. Writing to the SYNSR has no effect and terminates the cycle normally. 7 6 Field PLLMODE PLLSEL Reset See note 1 5 4 3 2 PLLREF LOCKS LOCK LOCS See note 2 R/W Address 1 0 — 000 R IPSBAR + 0x0012_0002 Note: 1. Reset state determined during reset configuration. 2. See the LOCKS and LOCK bit descriptions. Figure 9-4. Synthesizer Status Register (SYNSR) 9-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 9-4. SYNCR Field Descriptions (continued) Clock Module Bit(s) Name Description 7 PLLMODE Clock mode bit. The PLLMODE bit is configured at reset and reflects the clock mode as shown in Table 9-6. 1 PLL clock mode 0 External clock mode 6 PLLSEL PLL select. Configured at reset and reflects the PLL mode as shown in Table 9-6. 1 Normal PLL mode 0 1:1 PLL mode 5 PLLREF PLL reference. Configured at reset and reflects the PLL reference source in normal PLL mode as shown in Table 9-6. 1 Crystal clock reference 0 External clock reference 4 LOCKS Sticky indication of PLL lock status. 1 No unintentional PLL loss of lock since last system reset or MFD change 0 PLL loss of lock since last system reset or MFD change or currently not locked due to exit from STOP with FWKUP set The lock detect function sets the LOCKS bit when the PLL achieves lock after: • A system reset • A write to SYNCR that changes the MFD[2:0] bits When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains cleared until one of the two listed events occurs. In stop mode, if the PLL is intentionally disabled, then the LOCKS bit reflects the value prior to entering stop mode. However, if FWKUP is set, then LOCKS is cleared until the PLL regains lock. Once lock is regained, the LOCKS bit reflects the value prior to entering stop mode. Furthermore, reading the LOCKS bit at the same time that the PLL loses lock does not return the current loss of lock condition. In external clock mode, LOCKS remains cleared after reset. In normal PLL mode and 1:1 PLL mode, LOCKS is set after reset. 3 LOCK Set when the PLL is locked. PLL lock occurs when the synthesized frequency is within approximately 0.75 percent of the programmed frequency. The PLL loses lock when a frequency deviation of greater than approximately 1.5 percent occurs. Reading the LOCK flag at the same time that the PLL loses lock or acquires lock does not return the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset. If operating in external clock mode, LOCK remains cleared after reset. 1 PLL locked 0 PLL not locked Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 9-5. SYNSR Field Descriptions 9-9 Clock Module Bit(s) Name Description 2 LOCS Sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal PLL and 1:1 PLL modes. LOCS = 0 when the system clocks are operating normally. LOCS = 1 when system clocks have failed due to a reference failure or PLL failure. After entering stop mode with FWKUP set and the PLL and oscillator intentionally disabled (STPMD[1:0] = 11), the PLL exits stop mode in the SCM while the oscillator starts up. During this time, LOCS is temporarily set regardless of LOCEN. It is cleared once the oscillator comes up and the PLL is attempting to lock. If a read of the LOCS flag and a loss-of-clock condition occur simultaneously, the flag does not reflect the current loss-of-clock condition. A loss-of-clock condition can be detected only if LOCEN = 1 or the oscillator has not yet returned from exit from stop mode with FWKUP = 1. 1 Loss-of-clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with FWKUP = 1 0 Loss-of-clock not detected since exiting reset Note: The LOCS flag is always 0 in external clock mode. 1–0 — Reserved, should be cleared. Table 9-6. System Clock Modes PLLMODE:PLLSEL:PLLREF 9.7 Clock Mode 000 External clock mode 100 1:1 PLL mode 110 Normal PLL mode with external clock reference 111 Normal PLL mode with crystal reference Functional Description This subsection provides a functional description of the clock module. 9.7.1 System Clock Modes The system clock source is determined during reset (see Table 27-8). The values of CLKMOD[1:0] are latched during reset and are of no importance after reset is negated. If CLKMOD1 or CLKMOD0 is changed during a reset other than power-on reset, the internal clocks may glitch as the system clock source is changed between external clock mode and PLL clock mode. Whenever CLKMOD1 or CLKMOD0 is changed in reset, an immediate loss-of-lock condition occurs. Table 9-7 shows the clockout frequency to clockin frequency relationships for the possible system clock modes. Table 9-7. Clock Out and Clock In Relationships PLL Options1 System Clock Mode 9-10 Normal PLL clock mode fsys = fref × 2(MFD + 2)/2RFD 1:1 PLL clock mode fsys = fref External clock mode fsys = fref Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 9-5. SYNSR Field Descriptions (continued) 1 fref = input reference frequency fsys = CLKOUT frequency MFD ranges from 0 to 7. RFD ranges from 0 to 7. CAUTION XTAL must be tied low in external clock mode when reset is asserted. If it is not, clocks could be suspended indefinitely. The external clock is divided by two internally to produce the system clocks. 9.7.2 Clock Operation During Reset In external clock mode, the system is static and does not recognize reset until a clock is applied to EXTAL. In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference clock to the PLL begins operating within the limits given in the electrical specifications. If a PLL failure causes a reset, the system enters reset using the reference clock. Then the system clock source changes to the PLL operating in SCM. If SCM is not functional, the system becomes static. Alternately, if the LOCEN bit in SYNCR is cleared when the PLL fails, the system becomes static. If external reset is asserted, the system cannot enter reset unless the PLL is capable of operating in SCM. 9.7.3 System Clock Generation In normal PLL clock mode, the default system frequency is two times the reference frequency after reset. The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency multiplier. When programming the PLL, do not exceed the maximum system clock frequency listed in the electrical specifications. Use this procedure to accommodate the frequency overshoot that occurs when the MFD bits are changed: 1. Determine the appropriate value for the MFD and RFD fields in the SYNCR. The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an RFD factor to provide the required frequency. 2. Write a value of RFD (from step 1) + 1 to the RFD field of the SYNCR. 3. Write the MFD value from step 1 to the SYNCR. 4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value from step 1 to the RFD field of the SYNCR. This changes the system clocks frequency to the required frequency. NOTE Keep the maximum system clock frequency below the limit given in the Electrical Characteristics. 9.7.4 PLL Operation In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference clock frequency by 2x to 9x, provided that the system clock frequency remains within the range listed in electrical specifications. For example, if the reference frequency is 2 MHz, the PLL can synthesize frequencies of 4 MHz to 18 MHz. In addition, the RFD can reduce the system frequency by dividing the output of the PLL. Freescale Semiconductor 9-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Clock Module The RFD is not in the feedback loop of the PLL, so changing the RFD divisor does not affect PLL operation. Figure 9-5 shows the external support circuitry for the crystal oscillator with example component values. Actual component values depend on crystal specifications. The following subsections describe each major block of the PLL. Refer to Figure to see how these functional sub-blocks interact. C2 C1 VSS EXTAL XTAL ON-CHIP 8-MHz CRYSTAL CONFIGURATIO C1 = C2 = 16 pF RF = 1 MΩ RS = 470 Ω VSSSYN RS RF Figure 9-5. Crystal Oscillator Example 9.7.4.1 Phase and Frequency Detector (PFD) The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the reference and feedback clocks. The reference clock comes from either the crystal oscillator or an external clock source. 9-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Clock Module The feedback clock comes from one of the following: • CLKOUT in 1:1 PLL mode • VCO output divided by two if CLKOUT is disabled in 1:1 PLL mode • VCO output divided by the MFD in normal PLL mode When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference clock, the PFD pulses the UP signal. If the falling edge of the feedback clock leads the falling edge of the reference clock, the PFD pulses the DOWN signal. The width of these pulses relative to the reference clock depends on how much the two clocks lead or lag each other. Once phase lock is achieved, the PFD continues to pulse the UP and DOWN signals for very short durations during each reference clock cycle. These short pulses continually update the PLL and prevent the frequency drift phenomenon known as dead-banding. 9.7.4.2 Charge Pump/Loop Filter In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current magnitude of the charge pump varies with the MFD as shown in Table 9-8. Table 9-8. Charge Pump Current and MFD in Normal Mode Operation Charge Pump Current MFD 1X 0 ≤ MFD < 2 2X 2 ≤ MFD < 6 4X 6 ≤ MFD The UP and DOWN signals from the PFD control whether the charge pump applies or removes charge, respectively, from the loop filter. The filter is integrated on the chip. 9.7.4.3 Voltage Control Output (VCO) The voltage across the loop filter controls the frequency of the VCO output. The frequency-to-voltage relationship (VCO gain) is positive, and the output frequency is four times the target system frequency. 9.7.4.4 Multiplication Factor Divider (MFD) When the PLL is not in 1:1 PLL mode, the MFD divides the output of the VCO and feeds it back to the PFD. The PFD controls the VCO frequency via the charge pump and loop filter such that the reference and feedback clocks have the same frequency and phase. Thus, the frequency of the input to the MFD, which is also the output of the VCO, is the reference frequency multiplied by the same amount that the MFD divides by. For example, if the MFD divides the VCO frequency by six, the PLL is frequency locked when the VCO frequency is six times the reference frequency. The presence of the MFD in the loop allows the PLL to perform frequency multiplication, or synthesis. In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is one. 9.7.4.5 PLL Lock Detection The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship, but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock flag, LOCKS, is also provided. Freescale Semiconductor 9-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Clock Module The lock detect function uses two counters. One is clocked by the reference and the other is clocked by the PLL feedback. When the reference counter has counted N cycles, its count is compared to that of the feedback counter. If the feedback counter has also counted N cycles, the process is repeated for N + K counts. Then, if the two counters still match, the lock criteria is relaxed by 1/2 and the system is notified that the PLL has achieved frequency lock. After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare process. If the counters do not match at any comparison time, then the LOCK flag is cleared to indicate that the PLL has lost lock. At this point, the lock criteria is tightened and the lock detect process is repeated. The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to lock. Alternating between tight and relaxed lock criteria prevents the lock detect function from randomly toggling between locked and non-locked status due to phase sensitivities. Figure 9-6 shows the sequence for detecting locked and non-locked conditions. In external clock mode, the PLL is disabled and cannot lock. Start with Tight Lock Criteria Loss of Lock Detected Set Tight Lock Criteria and Notify System of Loss of Lock Condition Reference Count Reference Count ≠ Feedback Count ≠ Feedback Count Count N Reference Cycles and Compare Number of Feedback Cycles Elapsed Reference Count = Feedback Count = N In Same Count/Compare Sequence Lock Detected. Set Relaxed Lock Condition and Notify System of Lock Condition Count N + K Reference Cycles and Compare Number of Feedback Cycles Elapsed Reference Count = Feedback Count = N + K IN Same Count/Compare Sequence Figure 9-6. Lock Detect Sequence 9.7.4.6 PLL Loss of Lock Conditions Once the PLL acquires lock after reset, the LOCK and LOCKS flags are set. If the MFD is changed, or if an unexpected loss of lock condition occurs, the LOCK and LOCKS flags are negated. While the PLL is in the non-locked condition, the system clocks continue to be sourced from the PLL as the PLL attempts to relock. Consequently, during the relocking process, the system clocks frequency is not well defined and may exceed the maximum system frequency, violating the system clock timing specifications. However, once the PLL has relocked, the LOCK flag is set. The LOCKS flag remains cleared if the loss of lock is unexpected. The LOCKS flag is set when the loss of lock is caused by changing MFD. If the PLL is intentionally disabled during stop mode, then after exit from stop mode, the LOCKS flag reflects the value prior to entering stop mode once lock is regained. 9-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Clock Module Clock Module PLL Loss of Lock Reset If the LOLRE bit in the SYNCR is set, a loss of lock condition asserts reset. Reset reinitializes the LOCK and LOCKS flags. Therefore, software must read the LOL bit in the reset status register (RSR) to determine if a loss of lock caused the reset. See Section 29.4.2, “Reset Status Register (RSR).” To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock. In external clock mode, the PLL cannot lock. Therefore, a loss of lock condition cannot occur, and the LOLRE bit has no effect. 9.7.4.8 Loss of Clock Detection The LOCEN bit in the SYNCR enables the loss of clock detection circuit to monitor the input clocks to the phase and frequency detector (PFD). When either the reference or feedback clock frequency falls below the minimum frequency, the loss of clock circuit sets the sticky LOCS flag in the SYNSR. NOTE In external clock mode, the loss of clock circuit is disabled. 9.7.4.9 Loss of Clock Reset The clock module can assert a reset when a loss of clock or loss of lock occurs. When a loss-of-clock condition is recognized, reset is asserted if the LOCRE bit in SYNCR is set. The LOCS bit in SYNSR is cleared after reset. Therefore, the LOC bit must be read in RSR to determine that a loss of clock condition occurred. LOCRE has no effect in external clock mode. To exit reset in PLL mode, the reference must be present, and the PLL must acquire lock. Reset initializes the clock module registers to a known startup state as described in Section 9.6, “Memory Map and Registers.” 9.7.4.10 Alternate Clock Selection Depending on which clock source fails, the loss-of-clock circuit switches the system clocks source to the remaining operational clock. The alternate clock source generates the system clocks until reset is asserted. As Table 9-9 shows, if the reference fails, the PLL goes out of lock and into self-clocked mode (SCM). The PLL remains in SCM until the next reset. When the PLL is operating in SCM, the system frequency depends on the value in the RFD field. The SCM system frequency stated in electrical specifications assumes that the RFD has been programmed to binary 000. If the loss-of-clock condition is due to PLL failure, the PLL reference becomes the system clocks source until the next reset, even if the PLL regains and relocks. Table 9-9. Loss of Clock Summary 1 Clock Mode System Clock Source Before Failure Reference Failure Alternate Clock Selected by LOC Circuit1 Until Reset PLL Failure Alternate Clock Selected by LOC Circuit Until Reset PLL PLL PLL self-clocked mode PLL reference External External clock None NA The LOC circuit monitors the reference and feedback inputs to the PFD. See Figure 9-5. Freescale Semiconductor 9-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 9.7.4.7 A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may be simultaneous, or the PLL may fail first. In either case, the reference clock failure takes priority and the PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. Both the reference and the PLL must be functioning properly to exit reset. 9.7.4.11 Loss of Clock in Stop Mode Table 9-10 shows the resulting actions for a loss of clock in Stop Mode when the device is being clocked by the various clocking methods. EXT NRM NRM 9-16 X X X X X X — — MODE Out EXT Lose reference clock Stuck 0 0 0 Off Off 0 Lose lock, f.b. clock, reference clock Regain NRM No regain Stuck X 0 0 Off Off 1 Lose lock, f.b. clock, reference clock 0 0 — ‘LK — 1 LOCS PLL Action During Stop LOCK Expected PLL Action at Stop LOCKSS FWKUP OSC MODE In LOCEN LOCRE LOLRE PLL Table 9-10. Stop Mode Operation (Sheet 1 of 5) Comments 0 — ‘LC — — — Regain clocks, but SCM–> don’t regain lock unstable NRM 0–>‘L K 0–> 1 1–>‘L C Block LOCS and LOCKS until clock and lock respectively regain; enter SCM regardless of LOCEN bit until reference regained No reference clock regain SCM–> 0–> 0–> 1–> Block LOCS and LOCKS until clock and lock respectively regain; enter SCM regardless of LOCEN bit No f.b. clock regain Stuck — — — Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Clock Module Clock Module NRM NRM 0 0 0 Off On 0 Lose lock 0 0 0 Off On 1 Lose lock 0 0 0 On On 0 NRM Lose reference clock or no lock regain Stuck Lose reference clock, regain NRM ‘LK 1 ‘LC Block LOCKS from being cleared No lock regain Unstable NRM 0–>‘L K 0–> 1 ‘LC Block LOCKS until lock regained Lose reference clock or no f.b. clock regain Stuck — — Lose reference clock, regain Unstable NRM 0–>‘L K 0–> 1 ‘LC NRM ‘LK 1 ‘LC — — Lose lock or clock Stuck NRM NRM 0 0 0 On On 1 X X 1 Off X Freescale Semiconductor — — ‘LC — 0 1 ‘LC Lose clock and lock, regain NRM 0 1 ‘LC NRM ‘LK 1 ‘LC Lose lock Unstable NRM 0 0–> 1 ‘LC Lose lock, regain NRM 0 1 ‘LC Lose clock Stuck — — 0 0–> 1 ‘LC Lose clock, regain NRM with lock 0 1 ‘LC RESET — — LOCS not set because LOCEN = 0 — Lose clock, regain Unstable without lock NRM RESET LOCS not set because LOCEN = 0 — NRM — Block LOCKS from being cleared — Lose lock, regain — X Lose lock, f.b. clock, reference clock — 1 Comments Regain — ‘LK LOCS MODE Out LOCK PLL Action During Stop LOCKSS FWKUP Expected PLL Action at Stop Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NRM OSC MODE In LOCEN LOCRE LOLRE PLL Table 9-10. Stop Mode Operation (Sheet 2 of 5) — Reset immediately 9-17 Clock Module — NRM ‘LK Lose lock or clock RESET NRM NRM NRM NRM NRM 9-18 1 0 0 Off Off 0 Lose lock, f.b. clock, reference clock 1 0 0 Off On 0 Lose lock, f.b. clock 1 0 0 Off On 1 Lose lock, f.b. clock 1 0 0 On On 0 1 0 0 On On 1 — — — ‘LC — — No regain Stuck Regain NRM No f.b. clock or lock regain Stuck Lose reference clock SCM 0 0 1 Wakeup without lock Regain f.b. clock Unstable NRM 0–>‘L K 0–> 1 ‘LC REF mode not entered during stop No f.b. clock regain Stuck — — Lose reference clock SCM 0 0 1 NRM ‘LK 1 ‘LC Lose reference clock SCM 0 0 1 Wakeup without lock Lose f.b. clock REF 0 X 1 Wakeup without lock Lose lock Stuck Lose lock, regain NRM 0 1 ‘LC — NRM ‘LK 1 ‘LC Lose reference clock SCM 0 0 1 Wakeup without lock Lose f.b. clock REF 0 X 1 Wakeup without lock Lose lock Unstable NRM 0 0–> 1 ‘LC ‘LK — — ‘LC Reset immediately NRM — 1 Comments Regain — ‘LK 1 LOCS — MODE Out LOCK PLL Action During Stop LOCKSS FWKUP 0 0 1 On On X Expected PLL Action at Stop — 1 REF not entered during stop; SCM entered during stop only during oscillator startup — ‘LC — REF mode not entered during stop — — — Wakeup without lock — Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NRM OSC MODE In LOCEN LOCRE LOLRE PLL Table 9-10. Stop Mode Operation (Sheet 3 of 5) Clock Module NRM 1 1 X Off X NRM 1 1 0 On On 0 NRM NRM — X Lose lock, f.b. clock, reference clock 1 1 0 On On 1 1 1 1 On On X — — — NRM 1 0 0 X X X — 1 ‘LC — — — Reset immediately RESET — — — Reset immediately RESET — NRM ‘LK 1 ‘LC Lose clock RESET — — — Lose lock Stuck — — — Lose lock, regain NRM 0 1 ‘LC — NRM ‘LK 1 ‘LC Lose clock RESET Lose lock Unstable NRM 0 0–> 1 ‘LC Lose lock, regain NRM 0 1 ‘LC — NRM ‘LK 1 ‘LC — — — 0 X 1 — REF Lose reference clock Stuck — — — — — 1 0 0 Off X 0 PLL disabled Regain SCM SCM 0 0 1 SCM 1 0 0 Off X 1 PLL disabled Regain SCM SCM 0 0 1 SCM 1 0 0 On On 0 SCM 0 0 1 — Lose reference clock Freescale Semiconductor SCM Reset immediately Reset immediately Reset immediately — SCM — Comments Lose lock or clock RESET Lose clock or lock RESET REF ‘LK LOCS — MODE Out LOCK PLL Action During Stop LOCKSS FWKUP 1 0 1 On On X Expected PLL Action at Stop Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NRM OSC MODE In LOCEN LOCRE LOLRE PLL Table 9-10. Stop Mode Operation (Sheet 4 of 5) Wakeup without lock Wakeup without lock 9-19 Clock Module — Lose reference clock SCM 0 0 LOCS — MODE Out LOCK PLL Action During Stop LOCKSS FWKUP 1 0 0 On On 1 Expected PLL Action at Stop Comments 1 SCM Note: PLL = PLL enabled during STOP mode. PLL = On when STPMD[1:0] = 00 or 01 OSC = Oscillator enabled during STOP mode. Oscillator is on when STPMD[1:0] = 00, 01, or 10 MODES NRM = normal PLL crystal clock reference or normal PLL external reference or PLL 1:1 mode. During PLL 1:1 or normal external reference mode, the oscillator is never enabled. Therefore, during these modes, refer to the OSC = On case regardless of STPMD values. EXT=external clock mode REF=PLL reference mode due to losing PLL clock or lock from NRM mode SCM=PLL self-clocked mode due to losing reference clock from NRM mode RESET= immediate reset LOCKS ‘LK= expecting previous value of LOCKS before entering stop 0–>‘LK= current value is 0 until lock is regained which then will be the previous value before entering stop 0–> = current value is 0 until lock is regained but lock is never expected to regain LOCS ‘LC=expecting previous value of LOCS before entering stop 1–>‘LC= current value is 1 until clock is regained which then will be the previous value before entering stop 1–> =current value is 1 until clock is regained but CLK is never expected to regain 9-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 SCM OSC MODE In LOCEN LOCRE LOLRE PLL Table 9-10. Stop Mode Operation (Sheet 5 of 5) This section details the functionality for the interrupt controllers (INTC0, INTC1). The general features of each interrupt controller include: • 63 interrupt sources, organized as: — 56 fully-programmable interrupt sources — 7 fixed-level interrupt sources • Each of the 63 sources has a unique interrupt control register (ICRnx) to define the software-assigned levels and priorities within the level • Unique vector number for each interrupt source • Ability to mask any individual interrupt source, plus global mask-all capability • Supports both hardware and software interrupt acknowledge cycles • “Wake-up” signal from low-power stop modes The 56 fully-programmable and seven fixed-level interrupt sources for each of the two interrupt controllers handle the complete set of interrupt sources from all of the modules on the device. This section describes how the interrupt sources are mapped to the interrupt controller logic and how interrupts are serviced. 10.1 68K/ColdFire Interrupt Architecture Overview Before continuing with the specifics of the interrupt controllers, a brief review of the interrupt architecture of the 68K/ColdFire family is appropriate. The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If the priority level is greater than the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For correct operation, the ColdFire requires that, once asserted, the interrupt source remain asserted until explicitly disabled by the interrupt service routine. During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a special encoding of the transfer type and transfer modifier attributes to distinguish this data fetch from a “normal” memory access. The fetched data provides an index into the exception vector table which contains 256 addresses, each pointing to the beginning of a specific exception service routine. In particular, vectors 64 - 255 of the exception vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for the processor to handle reset, error conditions (access, address), arithmetic faults, system calls, etc. Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in memory. For ColdFire, all exception stack frames are 2 longwords in length, and contain 32 bits of vector and status register data, along with the 32-bit program counter value of the instruction that was interrupted (see Freescale Semiconductor 10-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 10 Interrupt Controller Modules Section 2.3.3.1, “Exception Stack Frame Definition” for more information on the stack frame format). After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine. After the status register is stored in the exception stack frame, the SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and all lower values while in the service routine. For many peripheral devices, the processing of the IACK cycle directly negates the interrupt request, while other devices require that request to be explicitly negated during the processing of the service routine. For this device, the processing of the interrupt acknowledge cycle is fundamentally different than previous 68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by the interrupt controller, so the requesting peripheral device is not accessed during the IACK. As a result, the interrupt request must be explicitly cleared in the peripheral during the interrupt service routine. For more information, see Section 10.1.1.3, “Interrupt Vector Determination.” Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the service routine is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR, interrupts can be safely disabled, if required. During the execution of the service routine, the appropriate actions must be performed on the peripheral to negate the interrupt request. For more information on exception processing, see the ColdFire Programmer’s Reference Manual at http://www.freescale.com/coldfire. 10.1.1 Interrupt Controller Theory of Operation To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt sources are organized as 7 levels, with each level supporting up to 9 prioritized requests. Consider the interrupt priority structure shown in Table 10-1, which orders the interrupt levels/priorities from highest to lowest. Table 10-1. Interrupt Priority Scheme Interrupt Level ICR[IL] Priority ICR[IP] Supported Interrupt Sources 7 6 #8–63 5 4 7 — (Mid-point) #7 (IRQ7) 3 2 #8–63 1 0 10-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Interrupt Controller Modules Interrupt Controller Modules Interrupt Level ICR[IL] 6 5 4 3 2 1 Priority ICR[IP] Supported Interrupt Sources 7–4 #8–63 — (Mid-point) #6 (IRQ6) 3–0 #8–63 7–4 #8–63 — (Mid-point) #5 (IRQ5) 3–0 #8–63 7–4 #8–63 — (Mid-point) #4 (IRQ4) 3–0 #8–63 7–4 #8–63 — (Mid-point) #3 (IRQ3) 3–0 #8–63 7–4 #8–63 — (Mid-point) #2 (IRQ2) 3–0 #8–63 7–4 #8–63 — (Mid-point) #1 (IRQ1) 3–0 #8–63 The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source 1–7 (from the Edgeport module) are fixed at the corresponding level’s midpoint priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single interrupt level. The “fixed” interrupt source is hardwired to the given level, and represents the mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in the 8-bit interrupt control register (ICRnx). The operation of the interrupt controller can be broadly partitioned into three activities: • Recognition • Prioritization • Vector Determination during IACK 10.1.1.1 Interrupt Recognition The interrupt controller continuously examines the request sources and the interrupt mask register to determine if there are active requests. This is the recognition phase. Freescale Semiconductor 10-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-1. Interrupt Priority Scheme (continued) Interrupt Controller Modules Interrupt Prioritization As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. The decoded priority levels from all the interrupt controllers are logically summed together and the highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the processor core during this prioritization phase. 10.1.1.3 Interrupt Vector Determination Once the core has sampled for pending interrupts and begun interrupt exception processing, it generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by the processor, and routed to the appropriate interrupt controller. Next, the interrupt controller extracts the level being acknowledged from address bits[4:2], and then determines the highest priority interrupt request active for that level, and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is formed using the following algorithm: For INTC0, vector_number = 64 + interrupt source number For INTC1, vector_number = 128 + interrupt source number Recall vector_numbers 0 - 63 are reserved for the ColdFire processor and its internal exceptions. Thus, the following mapping of bit positions to vector numbers applies for the INTC0: if interrupt source 1 is active and acknowledged, then vector_number = 65 if interrupt source 2 is active and acknowledged, then vector_number = 66 if interrupt source 8 is active and acknowledged, then vector_number = 72 if interrupt source 9 is active and acknowledged, then vector_number = 73 ... ... if interrupt source 62 is active and acknowledged, then vector_number = 126 The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector number. If there is no active interrupt source for the given level, a special “spurious interrupt” vector (vector_number = 24) is returned and it is the responsibility of the service routine to handle this error situation. Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since the interrupt controller completely services the acknowledge. This means the interrupt source must be explicitly disabled in the interrupt service routine. This design provides unique vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device. Vector numbers 64-71, and 91-255 are unused. 10.2 Memory Map The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In the following discussion, there are a number of program-visible registers greater than 32 bits in size. For these control fields, the physical register is partitioned into two 32-bit values: a register “high” (the upper longword) and a register “low” (the lower longword). The nomenclature <reg_name>H and <reg_name>L is used to reference these values. 10-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 10.1.1.2 The registers and their locations are defined in Table 10-3. The offsets listed start from the base address for each interrupt controller. The base addresses for the interrupt controllers are listed below: Table 10-2. Interrupt Controller Base Addresses 1 Interrupt Controller Number Base Address INTC0 IPSBAR + 0xC00 INTC1 IPSBAR + 0xD00 Global IACK Registers Space1 IPSBAR + 0xF00 This address space only contains the L1ACK-L7IACK registers. See Section 10.3.7, “Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)" for more information Table 10-3. Interrupt Controller Memory Map Module Offset Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] 0x00 Interrupt Pending Register High (IPRH), [63:32] 0x04 Interrupt Pending Register Low (IPRL), [31:1] 0x08 Interrupt Mask Register High (IMRH), [63:32] 0x0c Interrupt Mask Register Low (IMRL), [31:0] 0x10 Interrupt Force Register High (INTFRCH), [63:32] 0x14 Interrupt Force Register Low (INTFRCL), [31:1] 0x18 IRLR[7:1] IACKLPR[7:0] 0x1C–0x3C Reserved Reserved 0x40 Reserved ICR01 ICR02 ICR03 0x44 ICR04 ICR05 ICR06 ICR07 0x48 ICR08 ICR09 ICR10 ICR11 0x4C ICR12 ICR13 ICR14 ICR15 0x50 ICR16 ICR17 ICR18 ICR19 0x54 ICR20 ICR21 ICR22 ICR23 0x58 ICR24 ICR25 ICR26 ICR27 0x5C ICR28 ICR29 ICR30 ICR31 0x60 ICR32 ICR33 ICR34 ICR35 0x64 ICR36 ICR37 ICR38 ICR39 0x68 ICR40 ICR41 ICR42 ICR43 0x6C ICR44 ICR45 ICR46 ICR47 0x70 ICR48 ICR49 ICR50 ICR51 0x74 ICR52 ICR53 ICR54 ICR55 0x78 ICR56 ICR57 ICR58 ICR59 0x7C ICR60 ICR61 ICR62 ICR63 Freescale Semiconductor 10-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Interrupt Controller Modules Interrupt Controller Modules Module Offset Bits[31:24] Bits[23:16] 0x80–0xDC 10.3 Bits[15:8] Bits[7:0] Reserved 0xE0 SWIACK Reserved 0xE4 L1IACK Reserved 0xE8 L2IACK Reserved 0xEC L3IACK Reserved 0xF0 L4IACK Reserved 0xF4 L5IACK Reserved 0xF8 L6IACK Reserved 0xFC L7IACK Reserved Register Descriptions 10.3.1 Interrupt Pending Registers (IPRHn, IPRLn) The IPRHn and IPRLn registers, Figure 10-1 and Figure 10-2, are each 32 bits in size, and provide a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. The state of the interrupt mask register does not affect the IPRn. The IPRn is cleared by reset. The IPRn is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and reads as a zero. 31 16 Field INT[63:48] Reset 0000_0000_0000_0000 R/W R 15 0 Field INT[47:32] Reset 0000_0000_0000_0000 R/W R IPSBAR + 0xC00, 0xD00 Figure 10-1. Interrupt Pending Register High (IPRHn) 10-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-3. Interrupt Controller Memory Map (continued) Interrupt Controller Modules Bits Name 31–0 INT Description Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRHn samples the signal generated by the interrupting source. The corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set. 0 The corresponding interrupt source does not have an interrupt pending 1 The corresponding interrupt source has an interrupt pending . 31 16 Field INT[31:16] Reset 0000_0000_0000_0000 R/W R 15 1 Field INT[16:1] Reset 0000_0000_0000_0000 R/W R 0 — IPSBAR + 0xC04, 0xD04 Figure 10-2. Interrupt Pending Register Low (IPRLn) Table 10-5. IPRLn Field Descriptions Bits Name 31–1 INT 0 — 10.3.2 Description Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRLn samples the signal generated by the interrupting source. The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set. 0 The corresponding interrupt source does not have an interrupt pending 1 The corresponding interrupt source has an interrupt pending Reserved, should be cleared. Interrupt Mask Register (IMRHn, IMRLn) The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request). The IMRn is set to all ones by reset, disabling all interrupt requests. The IMRn can be read and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability. Freescale Semiconductor 10-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-4. IPRHn Field Descriptions Interrupt Controller Modules 31 16 Field INT_MASK[63:48] Reset 1111_1111_1111_1111 R/W R/W 15 0 Field INT_MASK[47:32] Reset 1111_1111_1111_1111 R/W R/W IPSBAR + 0xC08, 0xD08 Figure 10-3. Interrupt Mask Register High (IMRHn) Table 10-6. IMRHn Field Descriptions Bits Name Description 31–0 INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set. 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked . 31 16 Field INT_MASK[31:16] Reset 1111_1111_1111_1111 R/W R/W 15 Field 1 INT_MASK[16:1] Reset 1111_1111_1111_1111 R/W R/W 0 MASKALL IPSBAR + 0xC0C, 0xD0C Figure 10-4. Interrupt Mask Register Low (IMRLn) 10-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 . Interrupt Controller Modules Bits Name Description 31–1 INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set. 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked 0 MASKALL Mask all interrupts. Setting this bit will force the other 63 bits of the IMRHn and IMRLn to ones, disabling all interrupt sources, and providing a global mask-all capability. NOTE If an interrupt source is being masked in the interrupt controller mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the status register (SR[I]) is set to a value lower than the interrupt’s level, a spurious interrupt may occur. This is because by the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious interrupt is generated because the CPU cannot determine the interrupt source. To avoid this situation for interrupts sources with levels 1-6, first write a higher level interrupt mask to the status register, before setting the mask in the IMR or the module’s interrupt mask register. After the mask is set, return the interrupt mask in the status register to its previous value. Since level seven interrupts cannot be disabled in the status register prior to masking, use of the IMR or module interrupt mask registers to disable level seven interrupts is not recommended. 10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism to allow software generation of interrupts for each possible source for functional or debug purposes. The system design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRCn register. The assertion of an interrupt request via the INTFRCn register is not affected by the interrupt mask register. The INTFRCn register is cleared by reset. Freescale Semiconductor 10-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-7. IMRLn Field Descriptions 31 16 Field INTFRCH[63:48] Reset 0000_0000_0000_0000 R/W R/W 15 0 Field INTFRCH[47:32] Reset 0000_0000_0000_0000 R/W R/W IPSBAR + 0xC10, 0xD10 Figure 10-5. Interrupt Force Register High (INTFRCHn) Table 10-8. INTFRCHn Field Descriptions Bits 31–0 Name Description INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source . 31 16 Field INTFRCL[31:16] Reset 0000_0000_0000_0000 R/W R/W 15 1 Field INTFRCL[16:1] Reset 0000_0000_0000_0000 R/W R/W 0 — IPSBAR + 0xC14, 0xD14 Figure 10-6. Interrupt Force Register Low (INTFRCLn) Table 10-9. INTFRCLn Field Descriptions Bits 31–1 0 10-10 Name Description INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source — Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Interrupt Controller Modules Interrupt Controller Modules Interrupt Request Level Register (IRLRn) This 7-bit register is updated each machine cycle and represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This register output is combined with similar outputs from INTC1 and eventually encoded into the 3-bit priority interrupt level driven to the processor core. 7 2 Field 1 IRQ[7:1] Reset 0 — 0000_0000 R/W R Address IPSBAR + 0xC18, 0xD18 Figure 10-7. Interrupt Request Level Register (IRLRn) Table 10-10. IRQn Field Descriptions Bits Name 7–1 IRQ 0 — 10.3.5 Description Interrupt requests. Represents the prioritized active interrupts for each level. 0 There are no active interrupts at this level 1 There is an active interrupt at this level Reserved Interrupt Acknowledge Level and Priority Register (IACKLPRn) Each time an IACK is performed, the interrupt controller responds with the vector number of the highest priority source within the level being acknowledged. In addition to providing the vector number directly for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level and priority being acknowledged. This register provides the association between the acknowledged “physical” interrupt request number and the programmed interrupt level/priority. The contents of this read-only register are described in Figure 10-8 and Table 10-11. 7 Field Reset R/W Address — 6 4 3 LEVEL 0 PRI 0000_0000 R IPSBAR + 0xC19, 0xD19 Figure 10-8. IACK Level and Priority Register (IACKLPRn) Table 10-11. IACKLPRn Field Descriptions Bits Name 7 — Description Reserved Freescale Semiconductor 10-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 10.3.4 Interrupt Controller Modules Bits Name 6–4 LEVEL 3–0 PRI 10.3.6 Description Interrupt level. Represents the interrupt level currently being acknowledged. Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being acknowledged. 0 Priority 0 1 Priority 1 2 Priority 2 3 Priority 3 4 Priority 4 5 Priority 5 6 Priority 6 7 Priority 7 8 Mid-Point Priority associated with the fixed level interrupts only Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)) Each ICRnx specifies the interrupt level (1-7) and the priority within the level (0-7). All ICRnx registers can be read, but only ICRn8 to ICRn63 can be written. It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping level and priority definitions. Failure to program the ICRnx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state. 7 Field 6 5 — Address 2 IL Reset R/W 3 0 IP 0000_0000 R/W (Read only for ICRn1-ICRn7) See Table 10-2 and Table 10-3 for register offsets Note: It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping level and priority definitions. Failure to program the ICRnx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state. Figure 10-9. Interrupt Control Register (ICRnx) Table 10-12. ICRnx Field Descriptions 10-12 Bits Name Description 7–6 — Reserved, should be cleared. 5–3 IL Interrupt level. Indicates the interrupt level assigned to each interrupt input. 2–0 IP Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level assignment. 000b represents the lowest priority and 111b represents the highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the level, and the IP field will always read as 000b. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-11. IACKLPRn Field Descriptions (continued) Interrupt Controller Modules Interrupt Sources Table 10-13 and Table 10-14 list the interrupt sources for each interrupt request line for INTC0 and INTC1. Table 10-13. Interrupt Source Assignment for INTC0 Source Module Flag Source Description Flag Clearing Mechanism 1 EPORT EPF1 Edge port flag 1 Write EPF1 = 1 2 EPF2 Edge port flag 2 Write EPF2 = 1 3 EPF3 Edge port flag 3 Write EPF3 = 1 4 EPF4 Edge port flag 4 Write EPF4 = 1 5 EPF5 Edge port flag 5 Write EPF5 = 1 6 EPF6 Edge port flag 6 Write EPF6 = 1 7 EPF7 Edge port flag 7 Write EPF7 = 1 Cleared when service complete 8 SCM SWT1 Software watchdog timeout 9 DMA DONE DMA Channel 0 transfer complete Write DONE = 1 10 DONE DMA Channel 1 transfer complete Write DONE = 1 11 DONE DMA Channel 2 transfer complete Write DONE = 1 12 DONE DMA Channel 3 transfer complete Write DONE = 1 13 UART0 Multiple UART0 interrupt Cleared when service complete 14 UART1 Multiple UART1 interrupt Cleared when service complete 15 UART2 Multiple UART2 interrupt Cleared when service complete 16 Not used 17 I 2C IIF 18 QSPI Multiple 19 DTIM0 CAP/REF DTIM0 capture/reference event Write CAP = 1 or REF = 1 20 DTIM1 CAP/REF DTIM1 capture/reference event Write CAP = 1 or REF = 1 21 DTIM2 CAP/REF DTIM2 capture/reference event Write CAP = 1 or REF = 1 22 DTIM3 CAP/REF DTIM3 capture/reference event Write CAP = 1 or REF = 1 Freescale Semiconductor I2C interrupt QSPI interrupt Write IIF = 0 See QIR description 10-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 10.3.6.1 Interrupt Controller Modules Source Module Flag 23 FEC X_INTF Transmit frame interrupt Write X_INTF = 1 24 Note: Not used on MCF5214 & MCF5216 X_INTB Transmit buffer interrupt Write X_INTB = 1 UN Transmit FIFO underrun Write UN = 1 RL Collision retry limit Write RL = 1 R_INTF Receive frame interrupt Write R_INTF = 1 28 R_INTB Receive buffer interrupt Write R_INTB = 1 29 MII MII interrupt Write MII = 1 30 LC Late collision Write LC = 1 31 HBERR Heartbeat error Write HBERR = 1 32 GRA Graceful stop complete Write GRA = 1 33 EBERR Ethernet bus error Write EBERR = 1 34 BABT Babbling transmit error Write BABT = 1 35 BABR Babbling receive error Write BABR = 1 25 26 27 Flag Clearing Mechanism 36 PMM LVDF LVD Write LVDF = 1 37 QADC CF1 Queue 1 conversion complete Write CF1 = 0 after reading CF1 = 1 38 CF2 Queue 2 conversion complete Write CF2 = 0 after reading CF2 = 1 39 PF1 Queue 1 conversion pause Write PF1 = 0 after reading PF1 = 1 40 PF2 Queue 2 conversion pause Write PF2 = 0 after reading PF2 = 1 TOF Timer overflow Write TOF = 1 or access TIMCNTH/L if TFFCA = 1 42 PAIF Pulse accumulator input Write PAIF = 1 or access PAC if TFFCA = 1 43 PAOVF Pulse accumulator overflow Write PAOVF = 1 or access PAC if TFFCA = 1 44 C0F Timer channel 0 Write C0F = 1 or access IC/OC if TFFCA = 1 45 C1F Timer channel 1 Write C1F = 1 or access IC/OC if TFFCA = 1 46 C2F Timer channel 2 Write C2F = 1 or access IC/OC if TFFCA = 1 47 C3F Timer channel 3 Write C3F = 1 or access IC/OC if TFFCA = 1 TOF Timer overflow Write TOF = 1 or access TIMCNTH/L if TFFCA = 1 49 PAIF Pulse accumulator input Write PAIF = 1 or access PAC if TFFCA = 1 50 PAOVF Pulse accumulator overflow Write PAOVF = 1 or access PAC if TFFCA = 1 51 C0F Timer channel 0 Write C0F = 1 or access IC/OC if TFFCA = 1 52 C1F Timer channel 1 Write C1F = 1 or access IC/OC if TFFCA = 1 53 C2F Timer channel 2 Write C2F = 1 or access IC/OC if TFFCA = 1 54 C3F Timer channel 3 Write C3F = 1 or access IC/OC if TFFCA = 1 PIF PIT interrupt flag Write PIF = 1 of write PMR 41 48 55 10-14 Source Description GPTA GPTB PIT0 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-13. Interrupt Source Assignment for INTC0 (continued) Interrupt Controller Modules Source Module Flag 56 PIT1 PIF PIT interrupt flag Write PIF = 1 of write PMR 57 PIT2 PIF PIT interrupt flag Write PIF = 1 of write PMR 58 PIT3 PIF PIT interrupt flag Write PIF = 1 of write PMR 59 CFM CBEIF SGFM buffer empty Write CBEIF = 1 60 CFM CCIF SGFM command complete Cleared automatically 61 CFM PVIF Protection violation Cleared automatically 62 CFM AEIF Access error Cleared automatically 63 Freescale Semiconductor Source Description Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-13. Interrupt Source Assignment for INTC0 (continued) Flag Clearing Mechanism Not Used 10-15 Interrupt Controller Modules Source Module Flag Source Description 1-7 8 Flag Clearing Mechanism Not Used BUF0I Message buffer 0 interrupt Write BUF0I = 1 after reading BUF0I = 1 BUF1I Message buffer 1 interrupt Write BUF1I = 1 after reading BUF1I = 1 10 BUF2I Message buffer 2 interrupt Write BUF2I = 1 after reading BUF2I = 1 11 BUF3I Message buffer 3 interrupt Write BUF3I = 1 after reading BUF3I = 1 12 BUF4I Message buffer 4 interrupt Write BUF4I = 1 after reading BUF4I = 1 13 BUF5I Message buffer 5 interrupt Write BUF5I = 1 after reading BUF5I = 1 14 BUF6I Message buffer 6 interrupt Write BUF6I = 1 after reading BUF6I = 1 15 BUF7I Message buffer 7 interrupt Write BUF7I = 1 after reading BUF7I = 1 16 BUF8I Message buffer 8 interrupt Write BUF8I = 1 after reading BUF8I = 1 17 BUF9I Message buffer 9 interrupt Write BUF9I = 1 after reading BUF9I = 1 18 BUF10I Message buffer 10 interrupt Write BUF10I = 1 after reading BUF10I = 1 19 BUF11I Message buffer 11 interrupt Write BUF11I = 1 after reading BUF11I = 1 20 BUF12I Message buffer 12 interrupt Write BUF12I = 1 after reading BUF12I = 1 21 BUF13I Message buffer 13 interrupt Write BUF13I = 1 after reading BUF13I = 1 22 BUF14I Message buffer 14 interrupt Write BUF14I = 1 after reading BUF14I = 1 23 BUF15I Message buffer 15 interrupt Write BUF15I = 1 after reading BUF15I = 1 24 ERR_INT Error interrupt Write ERR_INT = 1 after reading ERR_INT = 1 25 BOFF_INT Bus-off interrupt Write BOFF_INT = 1 after reading BOFF_INT = 1 26 WAKE_INT Wake-up interrupt Write WAKE_INT = 1 after reading WAKE_INT = 1 9 27-63 10.3.7 FLEX CAN Not used Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt controller’s actions are very similar. First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK arrives in the interrupt controller, the controller examines all the currently-active level n interrupt requests, determines the highest priority within the level, and then responds with the unique vector number corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved later. This interrupt controller design also supports the concept of a software IACK. A software IACK is a useful concept that allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt exception processing (including machine state save/restore functions) can be minimized. In general, the software IACK is performed near the end of an interrupt 10-16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 10-14. Interrupt Source Assignment for INTC1 service routine, and if there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to the appropriate service routine, but without taking another interrupt exception. When the interrupt controller receives a software IACK read, it returns the vector number associated with the highest level, highest priority unmasked interrupt source for that interrupt controller. The IACKLPR register is also loaded as the software IACK is performed. If there are no active sources, the interrupt controller returns an all-zero vector as the operand. For this situation, the IACKLPR register is also cleared. In addition to the IACK registers within each interrupt controller, there are global LnIACK registers. A read from one of the global LnIACK registers returns the vector for the highest priority unmasked interrupt within a level for all interrupt controllers. There is no global SWIACK register. However, reading the SWIACK register from each interrupt controller returns the vector number of the highest priority unmasked request within that controller. 7 6 4 3 Field VECTOR Reset 0000_0000 R/W Address 0 R See Table 10-2 and Table 10-3 for register offsets Figure 10-10. Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) Table 10-15. SWIACK and L1IACK-L7IACK Field Descriptions Bits 7–0 10.4 Name Description VECTOR Vector number. A read from the SWIACK register returns the vector number associated with the highest level, highest priority unmasked interrupt source. A read from one of the LnACK registers returns the highest priority unmasked interrupt source within the level. Prioritization Between Interrupt Controllers The interrupt controllers have a fixed priority, where INTC0 has the highest priority, and INTC1 has the lowest priority. If both interrupt controllers have active interrupts at the same level and priority, then the INTC0 interrupt will be serviced first. If INTC1 has an active interrupt that has a higher level or priority than the highest INTC0 interrupt, then the INTC1 interrupt will be serviced first. 10.5 Low-Power Wakeup Operation The System Control Module (SCM) contains an 8-bit low-power interrupt control register (LPICR) used explicitly for controlling the low-power stop mode. This register must explicitly be programmed by software to enter low-power mode. Each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to exit from the low-power stop mode. This special mode of operation works as follows: • First, LPICR[6:4] is loaded with the mask level that will be specified while the core is in stop mode. LPICR[7] must be set to enable this mode of operation. Freescale Semiconductor 10-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Interrupt Controller Modules NOTE The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value used by the interrupt controller must be in the range of 0–6. • Second, the processor executes a STOP instruction which places it in stop mode. Once the processor is stopped, each interrupt controller enables a special logic path which evaluates the incoming interrupt sources in a purely combinatorial path; that is, there are no clocked storage elements. If an active interrupt request is asserted and the resulting interrupt level is greater than the mask value contained in LPICR[6:4], then each interrupt controller asserts the wake-up output signal, which is routed to the SCM where it is combined with the wakeup signals from the other interrupt controller and then to the PLL module to re-enable the device’s clock trees and resume processing. • 10-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Interrupt Controller Modules 11.1 Introduction The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1. Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin. See Figure 11-1. Stop Mode EPPAR[2n, 2n + 1] Edge Detect Logic EPFR[n] D0 Q D0 D1 Q IPBUS D1 To Interrupt Controller EPPDR[n] Synchronizer Rising Edge of System Clock EPIER[n] IRQx PIN EPDR[n] EPDDR[n] Figure 11-1. EPORT Block Diagram 11.2 Low-Power Mode Operation This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 7, “Power Management.” Table 11-1 shows EPORT module operation in low-power modes, and describes how this module may exit from each mode. NOTE The low-power interrupt control register (LPICR) in the System Control Module specifies the interrupt level at or above which is needed to bring the device out of a low-power mode. Freescale Semiconductor 11-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 11 Edge Port Module (EPORT) Edge Port Module (EPORT) Low-power Mode EPORT Operation Mode Exit Wait Normal Any IRQx Interrupt at or above level in LPICR Doze Normal Any IRQx Interrupt at or above level in LPICR Stop Level-sensing Only Any IRQx Interrupt set for level-sensing at or above level in LPICR In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may be configured to exit the low-power modes by generating an interrupt request on either a selected edge or a low level on an external pin. In stop mode, there are no clocks available to perform the edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode. NOTE The input pin synchronizer is bypassed for the level-detect logic since no clocks are available. 11.3 Interrupt/General-Purpose I/O Pin Descriptions All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals. When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset. 11-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 11-1. Edge Port Module Operation in Low-power Modes Edge Port Module (EPORT) Memory Map and Registers This subsection describes the memory map and register structure. 11.4.1 Memory Map Refer to Table 11-2 for a description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of 0x0013_0000. Table 11-2. Edge Port Module Memory Map IPSBAR Offset Bits 15–8 0x0013_0000 Access1 Bits 7–0 EPORT Pin Assignment Register (EPPAR) S 0x0013_0002 EPORT Data Direction Register (EPDDR) EPORT Interrupt Enable Register (EPIER) 0x0013_0004 EPORT Data Register (EPDR) 0x0013_0006 S EPORT Pin Data Register (EPPDR) EPORT Flag Register (EPFR) Reserved S/U 2 S/U 1 S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 Writing to reserved address locations has no effect, and reading returns 0s. 11.4.2 Registers The EPORT programming model consists of these registers: • The EPORT pin assignment register (EPPAR) controls the function of each pin individually. • The EPORT data direction register (EPDDR) controls the direction of each one of the pins individually. • The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin individually. • The EPORT data register (EPDR) holds the data to be driven to the pins. • The EPORT pin data register (EPPDR) reflects the current state of the pins. • The EPORT flag register (EPFR) individually latches EPORT edge events. 11.4.2.1 EPORT Pin Assignment Register (EPPAR) 15 Field 14 EPPA7 Reset R/W Address 13 12 EPPA6 11 10 EPPA5 9 8 EPPA4 7 6 EPPA3 5 4 EPPA2 3 2 EPPA1 1 0 — 0000_0000_0000_0000 R/W R IPSBAR + 0x0013_0000, 0x0013_0001 Figure 11-2. EPORT Pin Assignment Register (EPPAR) Freescale Semiconductor 11-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 11.4 Edge Port Module (EPORT) Bit(s) Name Description 15–2 EPPAx EPORT pin assignment select fields. The read/write EPPAx fields configure EPORT pins for level detection and rising and/or falling edge detection. Pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a valid interrupt request. Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected to bring the device out of stop mode with an IRQx interrupt. Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin configured for edge detection can trigger an interrupt regardless of its configuration as input or output. Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR functionality is independent of the selected pin direction. Reset clears the EPPAx fields. 00 Pin IRQx level-sensitive 01 Pin IRQx rising edge triggered 10 Pin IRQx falling edge triggered 11 Pin IRQx both falling edge and rising edge triggered 1–0 — 11.4.2.2 Reserved, should be cleared. EPORT Data Direction Register (EPDDR) Field 7 6 5 4 EPDD7 EPDD6 EPDD5 EPDD4 Reset R/W Address 3 2 1 0 EPDD3 EPDD2 EPDD1 — 0000_0000 R/W R IPSBAR + 0x0013_0002 Figure 11-3. EPORT Data Direction Register (EPDDR) Table 11-4. EPDD Field Descriptions 11-4 Bit(s) Name Description 7–1 EPDDx Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears EPDD7-EPDD1. To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear. Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output. 1 Corresponding EPORT pin configured as output 0 Corresponding EPORT pin configured as input 0 — Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 11-3. EPPAR Field Descriptions Edge Port Module (EPORT) Edge Port Interrupt Enable Register (EPIER) Field 7 6 5 4 3 2 1 0 EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 — Reset Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 11.4.2.3 0000_0000 R/W R/W Address R IPSBAR + 0x0013_0003 Figure 11-4. EPORT Port Interrupt Enable Register (EPIER) Table 11-5. EPIER Field Descriptions Bit(s) Name Description 7–1 EPIEx Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT generates an interrupt request when: • The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set. • The corresponding pin level is low and the pin is configured for level-sensitive operation. Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin. Reset clears EPIE7-EPIE1. 1 Interrupt requests from corresponding EPORT pin enabled 0 Interrupt requests from corresponding EPORT pin disabled 0 — 11.4.2.4 Reserved, should be cleared. Edge Port Data Register (EPDR) Field Reset R/W Address 7 6 5 4 3 2 1 0 EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 — 1111_1111 R/W R IPSBAR + 0x0013_0004 Figure 11-5. EPORT Port Data Register (EPDR) Table 11-6. EPDR Field Descriptions Bit(s) Name Description 7–1 EPDx Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets EPD7-EPD1. 0 — Freescale Semiconductor Reserved, should be cleared. 11-5 Edge Port Module (EPORT) Edge Port Pin Data Register (EPPDR) Field 7 6 5 4 EPPD7 EPPD6 EPPD5 EPPD4 Reset 3 2 1 0 EPPD3 EPPD2 EPPD1 Current pin state R/W — 0 R Address IPSBAR + 0x0013_0005 Figure 11-6. EPORT Port Pin Data Register (EPPDR) Table 11-7. EPPDR Field Descriptions Bit(s) Name Description 7–1 EPPDx Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins IRQ7–IRQ1. Writing to EPPDR has no effect, and the write cycle terminates normally. Reset does not affect EPPDR. 0 — 11.4.2.6 Reserved, should be cleared. Edge Port Flag Register (EPFR) Field Reset R/W Address 7 6 5 4 3 2 1 0 EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 — 0000_0000 R/W R IPSBAR + 0x0013_0006 Figure 11-7. EPORT Port Flag Register (EPFR) Table 11-8. EPFR Field Descriptions 11-6 Bit(s) Name Description 7–1 EPFx Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates that the selected edge has been detected. Reset clears EPF7-EPF1. Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARx = 00), pin transitions do not affect this register. 1 Selected edge for IRQx pin has been detected. 0 Selected edge for IRQx pin has not been detected. 0 — Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 11.4.2.5 This chapter describes the chip select module, including the operation and programming model of the chip select registers, which include the chip select address, mask, and control registers. NOTE Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus. 12.1 Overview The following list summarizes the key chip select features: • Up to seven independent, user-programmable chip select signals (CS[6:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, Flash, and peripherals • Address masking for 64-Kbyte to 4-Gbyte memory block sizes 12.2 Chip Select Module Signals Table 12-1 lists signals used by the chip select module. Table 12-1. Chip Select Module Signals Signal Chip Selects (CS[6:0]) Description Each CSn can be independently programmed for an address location as well as for masking, port size, read/write burst capability, wait-state generation, and internal/external termination. Only CS0 is initialized at reset and may act as an external boot chip select to allow boot ROM to be at an external address space. Port size for CS0 is configured by the logic levels of D[19:18] when RSTO negates and RCON is asserted. Output Enable Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the (OE) current address decode. Byte Strobes BS[3:0] These signals are individually programmed through the byte-enable mode bit, CSCRn[BEM], described in Section 12.4.1.3, “Chip Select Control Registers (CSCR0–CSCR6)”. These generated signals provide byte data select signals, which are decoded from the transfer size, A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed, as Table 12-2 shows. Table 12-2 shows the interaction of the byte-enable/byte-write enables with related signals. Freescale Semiconductor 12-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 12 Chip Select Module Chip Select Module Transfer Size Byte Port Size 8-bit BS0 D[31:24] D[23:16] D[15:8] D[7:0] 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 32-bit 0 0 0 0 1 1 1 0 1 1 0 0 8-bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 32-bit 0 0 0 0 0 0 8-bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 8-bit 16-bit 16-bit 32-bit 12-2 BS1 0 16-bit Line BS2 1 32-bit Longword BS3 A0 0 16-bit Word A1 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 12-2. Byte Enables/Byte Write Enable Signal Settings Chip Select Module Chip Select Operation Each chip select has a dedicated set of registers for configuration and control. • Chip select address registers (CSARn) control the base address of the chip select. See Section 12.4.1.1, “Chip Select Address Registers (CSAR0–CSAR6)”. • Chip select mask registers (CSMRn) provide 16-bit address masking and access control. See Section 12.4.1.2, “Chip Select Mask Registers (CSMR0–CSMR6)”. • Chip select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, and automatic acknowledge generation features. See Section 12.4.1.3, “Chip Select Control Registers (CSCR0–CSCR6)”. CS0 is a global chip select after reset and provides relocatable boot ROM capability. 12.3.1 General Chip Select Operation When a bus cycle is initiated, the device first compares its address with the base address and mask configurations programmed for chip selects 0–6 (configured in CSCR0–CSCR6) and DRAM blocks 0 and 1 (configured in DACR0 and DACR1). If the driven address matches a programmed chip select or DRAM block, the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed in the respective configuration register. Otherwise, the following occurs: • If the address and attributes do not match in CSAR or DACR, the device runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. • Should an address and attribute match in multiple CSCRs, the matching chip select signals are driven; however, the chip select signals are driven during an external burst-inhibited bus cycle with external termination on a 32-bit port. • If the address and attribute match both DACRs or a DACR and a CSAR, the operation is undefined. Table 12-3 shows the type of access as a function of match in the CSARs and DACRs. Table 12-3. Accesses by Matches in CSARs and DACRs 12.3.1.1 Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSAR Multiple 0 External, burst-inhibited, 32-bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined 8-, 16-, and 32-Bit Port Sizing Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 12.4.1.3, “Chip Select Control Registers (CSCR0–CSCR6)” for more information. Figure 12-1 shows the correspondence Freescale Semiconductor 12-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 12.3 between the data bus and the external byte strobe control lines (BS[3:0]). Note that all byte lanes are driven, although the state of unused byte lanes is undefined. External data bus BS3 BS2 BS1 BS0 D[31:24] D[23:16] D[15:8] D[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 0 Byte 2 Byte 1 Byte 3 Driven, undefined 32-bit port memory 16-bit port memory 8-bit port memory Byte 0 Byte 1 Byte 2 Byte 3 Driven, undefined Figure 12-1. Connections for External Memory Port Sizes 12.3.1.2 External Boot Chip Select Operation CS0, the external boot chip select, allows address decoding for boot ROM before system initialization. Its operation differs from other external chip select outputs after system reset. After system reset, CS0 is asserted for every external access. No other chip select can be used until the valid bit, CSMR0[V], is set, at which point CS0 functions as configured and CS[6:1] can be used. At reset, the port size function of the external boot chip select is determined by the logic levels of the inputs on D[19:18]. Table 12-4 and Table 12-4 list the various reset encodings for the configuration signals multiplexed with D[19:18]. Table 12-4. D[19:18] External Boot Chip Select Configuration D[19:18] Boot Device/Data Port Size 00 Internal (32-bit) 01 External (16-bit) 10 External (8-bit) 11 External (32-bit) Provided the required address range is in the chip select address register (CSAR0), CS0 can be programmed to continue decoding for a range of addresses after the CSMR0[V] is set, after which the external boot chip select can be restored only by a system reset. 12.4 Chip Select Registers Table 12-5 shows the chip select register memory map. Reading reserved locations returns zeros. 12-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chip Select Module Chip Select Module IPSBAR Offset 0x00_0080 [31:24] [23:16] Chip select address register—bank 0 (CSAR0) [p. 12-6] 0x00_0084 [15:8] [7:0] Reserved1 Chip select mask register—bank 0 (CSMR0) [p. 12-6] 0x00_0088 Reserved1 Chip select control register—bank 0 (CSCR0) [p. 12-7] 0x00_008C Chip select address register—bank 1 (CSAR1) [p. 12-6] Reserved1 0x00_0090 Chip select mask register—bank 1 (CSMR1) [p. 12-6] 0x00_0094 Reserved1 Chip select control register—bank 1 (CSCR1) [p. 12-7] 0x00_0098 Chip select address register—bank 2 (CSAR2) [p. 12-6] Reserved1 0x00_009C Chip select mask register—bank 2 (CSMR2) [p. 12-6] 0x00_00A0 Reserved1 Chip select control register—bank 2 (CSCR2) [p. 12-7] 0x00_00A4 Chip select address register—bank 3 (CSAR3) [p. 12-6] Reserved1 0x00_00A8 Chip select mask register—bank 3 (CSMR3) [p. 12-6] 0x00_00AC Reserved1 Chip select control register—bank 3 (CSCR3) [p. 12-7] 0x00_00B0 Chip select address register—bank 4 (CSAR4) [p. 12-6] Reserved1 0x00_00B4 Chip select mask register—bank 4 (CSMR4) [p. 12-6] 0x00_00B8 Reserved1 Chip select control register—bank 4 (CSCR4) [p. 12-7] 0x00_00BC Chip select address register—bank 5 (CSAR5) [p. 12-6] Reserved1 0x00_00C0 Chip select mask register—bank 5 (CSMR5) [p. 12-6] 0x00_00C4 Reserved1 Chip select control register—bank 5 (CSCR5) [p. 12-7] 0x00_00C8 Chip select address register—bank 6 (CSAR6) [p. 12-6] Reserved1 0x00_00CC 0x00_00D0 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 12-5. Chip Select Registers Chip select mask register—bank 6 (CSMR6) [p. 12-6] Reserved1 Chip select control register—bank 6 (CSCR6) [p. 12-7] Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. Freescale Semiconductor 12-5 Chip Select Module Chip Select Module Registers The chip select module is programmed through the chip select address registers (CSAR0–CSAR6), chip select mask registers (CSMR0–CSMR6), and the chip select control registers (CSCR0–CSCR6). 12.4.1.1 Chip Select Address Registers (CSAR0–CSAR6) The CSARs, Figure 12-2, specify the chip select base addresses. 15 0 Field BA Reset Uninitialized R/W Address R/W 0x080 (CSAR0); 0x08C (CSAR1); 0x098 (CSAR2); 0x0A4 (CSAR3); 0x0B0 (CSAR4); 0x0BC (CSAR5); 0x0C8 (CSAR6) Figure 12-2. Chip Select Address Registers (CSARn) Table 12-6 describes CSAR[BA]. Table 12-6. CSARn Field Description Bits Name Description 15–0 BA Base address. Defines the base address for memory dedicated to chip select CS[6:0]. BA is compared to bits 31–16 on the internal address bus to determine if chip select memory is being accessed. 12.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6) The CSMRs, Figure 12-3, are used to specify the address mask and allowable access types for the respective chip selects. . 31 Field 16 15 9 BAM Reset — 8 7 6 5 4 3 2 1 0 WP — AM C/I SC SD UC UD V Unitialized 0 R/W R/W Addr 0x084 (CSMR0); 0x090 (CSMR1); 0x09C (CSMR2); 0x0A8 (CSMR3); 0x0B4 (CSMR4); 0x0C0 (CSMR5); 0x0CC (CSMR6) Figure 12-3. Chip Select Mask Registers (CSMRn) Table 12-7 describes CSMR fields. 12-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 12.4.1 Chip Select Module Bits Name Description 31–16 BAM Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode. 0 Corresponding address bit is used in chip select decode. 1 Corresponding address bit is a don’t care in chip select decode. The block size for CS[6:0] is 2n where n = (number of bits set in respective CSMR[BAM]) + 16. So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0001, CS0 addresses a 128-Kbyte (217 byte) range from 0x0000–0x1_FFFF. Likewise, for CS0 to access 32 Mbytes (225 bytes) of address space starting at location 0x0000, and for CS1 to access 16 Mbytes (224 bytes) of address space starting after the CS0 space, then CSAR0 = 0x0000, CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and CSMR1[BAM] = 0x00FF. 8 WP Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate chip select not being selected. No exception occurs. 0 Both read and write accesses are allowed. 1 Only read accesses are allowed. 7 — Reserved, should be cleared. 6 AM Alternate master. When AM = 0 during a DMA access, SC, SD, UC, and UD are don’t cares in the chip select decode. 5–1 C/I, SC, SD, UC, UD Address space mask bits. These bits determine whether the specified accesses can occur to the address space defined by the BAM for this chip select. C/I CPU space and interrupt acknowledge cycle mask SC Supervisor code address space mask SD Supervisor data address space mask UC User code address space mask UD User data address space mask 0 The address space assigned to this chip select is available to the specified access type. 1 The address space assigned to this chip select is not available (masked) to the specified access type. If this address space is accessed, chip select is not activated and a regular external bus cycle occurs. Note that if AM = 0, SC, SD, UC, and UD are ignored in the chip select decode on DMA access. 0 V Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip selects do not assert until V is set (except for CS0, which acts as the global chip select). Reset clears each CSMRn[V]. 0 Chip select invalid 1 Chip select valid 12.4.1.3 Chip Select Control Registers (CSCR0–CSCR6) Each CSCR, shown in Figure 12-4, controls the auto-acknowledge, port size, burst capability, and activation of each chip select. Note that to support the external boot chip select, CS0, the CSCR0 reset values differ from the other CSCRs. CS0 allows address decoding for boot ROM before system initialization. Freescale Semiconductor 12-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 12-7. CSMRn Field Descriptions 15 14 13 10 9 Field — WS — Reset: CSCR0 — 11_11 — Reset: Other CSCRs 7 6 5 4 3 2 AA PS1 PS0 BEM BSTR BSTW 1 D19 D18 — 0 — — Uninitialized R/W Address 8 R/W 0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3); 0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6) Figure 12-4. Chip Select Control Registers (CSCRn) Table 12-8 describes CSCRn fields. Table 12-8. CSCRn Field Descriptions 12-8 Bits Name Description 15–14 — 13–10 WS 9 — Reserved, should be cleared. 8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip select address. 0 No internal TA is asserted. Cycle is terminated externally. 1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the external system asserts an external TA before the wait-state countdown asserts the internal TA, the cycle is terminated. Burst cycles increment the address bus between each internal termination. 7–6 PS Port size. Specifies the width of the data associated with each chip select. It determines where data is driven during write cycles and where data is sampled during read cycles. See Section 12.3.1.1, “8-, 16-, and 32-Bit Port Sizing”. 00 32-bit port size. Valid data sampled and driven on D[31:0] 01 8-bit port size. Valid data sampled and driven on D[31:24] 1x 16-bit port size. Valid data sampled and driven on D[31:16] 5 BEM Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable in support of these SRAMs. 0 BS is not asserted for read. BS is asserted for data write only. 1 BS is asserted for read and write accesses. 4 BSTR Burst read enable. Specifies whether burst reads are used for memory associated with each CSn. 0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. Reserved, should be cleared. Wait states. The number of wait states inserted before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, TA must be asserted by the external system regardless of the number of wait states generated. In that case, the external transfer acknowledge ends the cycle. An external TA supercedes the generation of an internal TA. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chip Select Module Chip Select Module Bits 3 2–0 Name Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 12-8. CSCRn Field Descriptions (continued) Description BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CSn. 0 Break data larger than the specified port size into individual port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports. — Reserved, should be cleared. Freescale Semiconductor 12-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chip Select Module 12-10 Freescale Semiconductor This chapter describes data-transfer operations, error conditions, and reset operations. Chapter 15, “Synchronous DRAM Controller Module,” describes DRAM cycles. NOTE Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus. 13.1 Features The following list summarizes bus operation features: • Up to 24 bits of address and 32 bits of data • Access 8-, 16-, and 32-bit data port sizes • Generates byte, word, longword, and line-size transfers • Burst and burst-inhibited transfer support • Optional internal termination for external bus cycles 13.2 Bus and Control Signals Table 13-1 summarizes the bus signals described in Chapter 14, “Signal Descriptions”. Table 13-1. ColdFire Bus Signal Summary Signal Name A[23:0] I/O CLKOUT Edge Address bus O Rising Byte selects O Falling Chip selects O Falling Data bus I/O Rising Output enable O Falling Read/write O Rising Transfer size O Rising TA Transfer acknowledge I Rising TIP Transfer in progress O Rising TS Transfer start O Rising BS 1 CS[6:0] 1 D[31:0] OE 1 R/W SIZ[1:0] 1 Description These signals change after the falling edge. In the Electrical Specifications, these signals are specified off of the rising edge because CLKIN is squared up internally. Freescale Semiconductor 13-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 13 External Interface Module (EIM) External Interface Module (EIM) Bus Characteristics The device uses its system clock to generate CLKOUT. Therefore, the external bus operates at the same speed as the bus clock rate, where all bus operations are synchronous to the rising edge of CLKOUT, and some of the bus control signals (BS, OE, and CSn,) are synchronous to the falling edge, shown in Figure 13-1. Bus characteristics may differ somewhat for interfacing with external DRAM. CLKOUT tho tvo Rising-Edge Signals tvo tho Falling-Edge Signals tsi thi Inputs tvo = Propagation delay of signal relative to CLKOUT edge tho = Output hold time relative to CLKOUT edge tsi = Required input setup time relative to CLKOUT edge thi = Required input hold time relative to CLKOUT edge Figure 13-1. Signal Relationship to CLKOUT for Non-DRAM Access 13.4 Data Transfer Operation Data transfers between the processor and other devices involve the following signals: • Address bus (A[23:0]) • Data bus (D[31:0]) • Control signals (TS and TA) • CSn, OE, BS • Attribute signals (R/W, SIZ, and TIP) The address bus, write data, TS, and all attribute signals change on the rising edge of CLKOUT. Read data is latched into the processor on the rising edge of CLKOUT. The bus supports byte, word, and longword operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. Aspects of the transfer, such as the port size, the number of wait states for the external slave being accessed, and whether internal transfer termination is enabled, can be programmed in the chip-select control registers (CSCRs) and the DRAM control registers (DACRs). Figure 13-2 shows the byte lanes that external memory should be connected to and the sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit memory should be connected to D[31:24] (BS3). A longword transfer takes four transfers on D[31:24], starting with the MSB and going to the LSB. 13-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 13.3 Byte Enable BS3 BS2 BS1 BS0 D[31:24] D[23:16] D[15:8] D[7:0] 32-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 16-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 Processor External Data Bus 8-Bit Port Memory Driven with indeterminate values Byte 0 Byte 1 Byte 2 Driven with indeterminate values Byte 3 Figure 13-2. Connections for External Memory Port Sizes The timing relationship of chip selects (CS[7:0]), byte selects (BS[3:0]), and output enable (OE) with respect to CLKOUT is similar in that all transitions occur during the low phase of CLKOUT. However, due to differences in on-chip signal routing, signals may not assert simultaneously. CLKOUT CS[7:0] BS[3:0] OE Figure 13-3. Chip-Select Module Output Timing Diagram 13.4.1 Bus Cycle Execution When a bus cycle is initiated, the device first compares the address of that bus cycle with the base address and mask configurations programmed for chip selects 0–7 (configured in CSCR0–CSCR7) and DRAM block 0 and 1 address and control registers (configured in DACR0 and DACR1). If the driven address compares with one of the programmed chip selects or DRAM blocks, the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed by the user in the respective configuration register. Otherwise, the following occurs: • If the address and attributes do not match in CSCR or DACR, the processor runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. • Should an address and attribute match in multiple CSCRs, the matching chip-select signals are driven; however, the processor runs an external burst-inhibited bus cycle with external termination on a 32-bit port. • Should an address and attribute match both DACRs or a DACR and a CSCR, the operation is undefined. Table 13-2 shows the type of access as a function of match in the CSCRs and DACRs. Freescale Semiconductor 13-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 External Interface Module (EIM) External Interface Module (EIM) Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSCR Multiple 0 External, burst-inhibited, 32-bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined Basic operation of the bus is a three-clock bus cycle: 1. During the first clock, the address, attributes, and TS are driven. 2. Data and TA are sampled during the second clock of a bus-read cycle. During a read, the external device provides data and is sampled at the rising edge at the end of the second bus clock. This data is concurrent with TA, which is also sampled at the rising edge of the clock. During a write, the ColdFire device drives data from the rising clock edge at the end of the first clock to the rising clock edge at the end of the bus cycle. Wait states can be added between the first and second clocks by delaying the assertion of TA. TA can be configured to be generated internally through the CSCRs. If TA is not generated internally, the system must provide it externally. 3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes and write data. Figure 13-6 and Figure 13-8 show the basic read and write operations. 13.4.2 Data Transfer Cycle States The data transfer operation is controlled by an on-chip state machine. Each bus clock cycle is divided into two states. Even states occur when CLKOUT is high and odd states occur when CLKOUT is low. The state transition diagram for basic and fast termination read and write cycles are shown in Figure 13-4. 13-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 13-2. Accesses by Matches in CSCRs and DACRs External Interface Module (EIM) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Next Cycle S0 S5 S1 Basic Read/Write Fast Termination S4 S2 Wait States S3 Figure 13-4. Data Transfer State Transition Diagram Table 13-3 describes the states as they appear in subsequent timing diagrams. Table 13-3. Bus Cycle States State Cycle CLKOUT Description S0 All High The read or write cycle is initiated in S0. On the rising edge of CLKOUT, the device places a valid address on the address bus and drives R/W high for a read and low for a write, if it is not already in the appropriate state. The processor asserts TIP, SIZ[1:0], and TS on the rising edge of CLKOUT. S1 All Low The appropriate CSn, BS, and OE signals assert on the CLKOUT falling edge. S2 S3 Fast Termination TA must be asserted during S1. Data is made available by the external device and is sampled on the rising edge of CLKOUT with TA asserted. Read/write High (skipped fast termination) TS is negated on the rising edge of CLKOUT in S2. Write The data bus is driven out of high impedance as data is placed on the bus on the rising edge of CLKOUT. Read/write (skipped for fast termination) Low Read S4 All Read (including fast-terminati on) Freescale Semiconductor The processor waits for TA assertion. If TA is not sampled as asserted before the rising edge of CLKOUT at the end of the first clock cycle, the processor inserts wait states (full clock cycles) until TA is sampled as asserted. Data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted. High The external device should negate TA. The external device can stop driving data after the rising edge of CLKOUT. However data could be driven through the end of S5. 13-5 External Interface Module (EIM) State S5 Cycle S5 CLKOUT Low Description CS, BS, and OE are negated on the CLKOUT falling edge of S5. The processor stops driving address lines and R/W on the rising edge of CLKOUT, terminating the read or write cycle. At the same time, the processor negates TIP, and SIZ[1:0] on the rising edge of CLKOUT. Note that the rising edge of CLKOUT may be the start of S0 for the next access cycle. Read The external device stops driving data between S4 and S5. Write The data bus returns to high impedance on the rising edge of CLKOUT. The rising edge of CLKOUT may be the start of S0 for the next access. NOTE An external device has at most two CLKOUT cycles after the start of S4 to three-state the data bus. This applies to basic read cycles, fast termination cycles, and the last transfer of a burst. 13.4.3 Read Cycle During a read cycle, the device receives data from memory or from a peripheral device. Figure 13-5 is a read cycle flowchart. External device ColdFire processor 1. Set R/W to read 2. Place address on A[31:0] 3. Assert TIP, and SIZ[1:0] 4. Assert TS 5. Negate TS 1. 1. 1. Decode address and select the appropriate slave device. 2. Drive data on D[31:0] 3. Assert TA 1. Negate TA. 2. Stop driving D[31:0] Sample TA low and latch data Start next cycle Figure 13-5. Read Cycle Flowchart The read cycle timing diagram is shown in Figure 13-6. NOTE In the following timing diagrams, TA waveforms apply for chip selects programmed to enable either internal or external termination. TA assertion should look the same in either case. 13-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 13-3. Bus Cycle States (continued) External Interface Module (EIM) S1 S2 S3 S4 S5 CLKOUT R/W A[31:0], SIZ[1:0] TIP TS CSn, BSn, OE Read D[31:0] TA Figure 13-6. Basic Read Bus Cycle Note the following characteristics of a basic read: • In S3, data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted. • In S4, the external device can stop driving data after the rising edge of CLKOUT. However data could be driven up to S5. • For a read cycle, the external device stops driving data between S4 and S5. States are described in Table 13-3. 13.4.4 Write Cycle During a write cycle, the processor sends data to the memory or to a peripheral device. The write cycle flowchart is shown in Figure 13-7. External Device ColdFire processor 1. Set R/W to write 2. Place address on A[31:0] 3. Assert TIP and SIZ[1:0] 4. Assert TS 5. Place data on D[31:0] 6. Negate TS 1. Sample TA low 2. Stop driving data from D[31:0] 1. Start next cycle 1. Decode address 2. Store data on D[31:0] 3. Assert TA 1. Negate TA Figure 13-7. Write Cycle Flowchart Freescale Semiconductor 13-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 S0 External Interface Module (EIM) S0 S1 S2 S3 S4 S5 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn Write D[31:0] TA Figure 13-8. Basic Write Bus Cycle Table 13-3 describes the six states of a basic write cycle. 13.4.5 Fast Termination Cycles Two clock cycle transfers are supported on the external bus. In most cases, this is impractical to use in a system because the termination must take place in the same half-clock during which TS is asserted. As this is atypical, it is not referred to as the zero-wait-state case but is called the fast-termination case. Fast termination cycles occur when the external device or memory asserts TA less than one clock after TS is asserted. This means that the processor samples TA on the rising edge of the second cycle of the bus transfer. Figure 13-9 shows a read cycle with fast termination. Note that fast termination cannot be used with internal termination. S0 S1 S4 S5 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE D[31:0] Read TA Figure 13-9. Read Cycle with Fast Termination Figure 13-10 shows a write cycle with fast termination. 13-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 The write cycle timing diagram is shown in Figure 13-8. External Interface Module (EIM) S1 S4 S5 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn D[31:0] Write TA Figure 13-10. Write Cycle with Fast Termination 13.4.6 Back-to-Back Bus Cycles The processor runs back-to-back bus cycles whenever possible. For example, when a longword read is started on a word-size bus, the processor performs two back-to-back word read accesses. Back-to-back accesses are distinguished by the continuous assertion of TIP throughout the cycle. Figure 13-11 shows a read back-to-back with a write. S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn OE D[31:0] Read Write TA Figure 13-11. Back-to-Back Bus Cycles Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable. Freescale Semiconductor 13-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 S0 External Interface Module (EIM) Burst Cycles The processor can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to. For example, a word transfer to an 8-bit port would take a 2-byte burst cycle. A line transfer to a 32-bit port would take a 4-longword burst cycle. The external bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize DMA transfers. A user can add wait states by delaying termination of the cycle. The initiation of a burst cycle is encoded on the size pins. For burst transfers to smaller port sizes, SIZ[1:0] indicates the size of the entire transfer. For example, if the processor writes a longword to an 8-bit port, SIZ[1:0] = 00 for the first byte transfer and does not change. The CSCRs can be used to enable bursting for reads, writes, or both. Processor memory space can be declared burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW]. A line access to a burst-inhibited region first accesses the processor bus encoded as a line access. The SIZ[1:0] encoding does not exceed the programmed port size. The address changes if internal termination is used but does not change if external termination is used, as shown in Figure 13-12 and Figure 13-13. 13.4.7.1 Line Transfers A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transfers on multiple address boundaries. Table 13-4 shows allowable patterns for line accesses. Table 13-4. Allowable Line Access Patterns 13.4.7.2 A[3:2] Longword Accesses 00 0–4–8–C 01 4–8–C–0 10 8–C–0–4 11 C–0–4–8 Line Read Bus Cycles Figure 13-12 and Figure 13-13 show a line access read with zero wait states. The access starts like a basic read bus cycle with the first data transfer sampled on the rising edge of S4, but the next pipelined burst data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined data burst is single cycle until the last one, which can be held for up to two CLKOUT cycles after TA is asserted. Note that CSn are asserted throughout the burst transfer. This example shows the timing for external termination, which differs from the internal termination example in Figure 13-13 only in that the address lines change only at the beginning (assertion of TS and TIP) and end (negation of TIP) of the transfer. 13-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 13.4.7 External Interface Module (EIM) S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE Read Read D[31:0] Read Read TA Figure 13-12. Line Read Burst (2-1-1-1), External Termination Figure 13-13 shows timing when internal termination is used. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 CLKOUT A[31:0] A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE D[31:0] Read Read Read Read TA Figure 13-13. Line Read Burst (2-1-1-1), Internal Termination Figure 13-14 shows a line access read with one wait state programmed in CSCRn to give the peripheral or memory more time to return read data. This figure follows the same execution as a zero-wait state read burst with the exception of an added wait state. Freescale Semiconductor 13-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 S0 External Interface Module (EIM) WS S0 S1 S2 S3 S4 S5 WS S6 S7 WS S8 S9 WS S10 S12 S13 S11 CLKOUT A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE Read D[31:0] Read Read Read TA Figure 13-14. Line Read Burst (3-2-2-2), External Termination Figure 13-15 shows a burst-inhibited line read access with fast termination. The external device executes a basic read cycle while determining that a line is being transferred. The external device uses fast termination for subsequent transfers. S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 S6 S7 CLKOUT A[31:0] A[3:2] = 00 A[3:2] = 01 R/W TIP SIZ[1:0] Line Longword TS CSn, BSn, OE D[31:0] Read Read Read Read Fast Fast Fast TA Basic Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination 13.4.7.3 Line Write Bus Cycles Figure 13-16 shows a line access write with zero wait states. It begins like a basic write bus cycle with data driven one clock after TS. The next pipelined burst data is driven a cycle after the write data is registered (on the rising edge of S6). Each subsequent burst takes a single cycle. Note that as with the line read example in Figure 13-12, CSn remain asserted throughout the burst transfer. This example shows the behavior of the address lines for both internal and external termination. Note that when external termination is used, the address lines change with SIZ[1:0]. 13-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 . S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 CLKOUT A[31:0] Internal Termination A[31:0] External Termination SIZ[1:0] R/W, TIP TS CSn, OE, BSn Write D[31:0] Write Write Write TA Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination Figure 13-17 shows a line burst write with one wait-state insertion. S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10S11 CLKOUT A[31:0] R/W, TIP SIZ[1:0] TS CSn, OE, BSn D[31:0] Write Write Write Write TA Figure 13-17. Line Write Burst (3-2-2-2) with One Wait State Figure 13-18 shows a burst-inhibited line write. The external device executes a basic write cycle while determining that a line is being transferred. The external device uses fast termination to end each subsequent transfer. Freescale Semiconductor 13-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 External Interface Module (EIM) S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 CLKOUT A[31:0] A[3:2] = 00 A[3:2] = 01 R/W, TIP SIZ[1:0] Line Longword TS CSn OE, BSn D[31:0] Write Write Write Write TA Basic Fast Fast Fast Figure 13-18. Line Write Burst-Inhibited 13.5 Misaligned Operands Because operands can reside at any byte boundary, unlike opcodes, they are allowed to be misaligned. A byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a longword is misaligned at an address not a multiple of four. Although the processor enforces no alignment restrictions for data operands (including program counter (PC) relative data addressing), additional bus cycles are required for misaligned operands. Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address error exception. The processor converts misaligned, cache-inhibited operand accesses to multiple aligned accesses. Figure 13-19 shows the transfer of a longword operand from a byte address to a 32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device supplies the byte and acknowledges the data transfer. When the processor starts the second cycle, SIZ[1:0] specify a word transfer with a byte offset of 0x2. The next two bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the port supplies the final byte, and the operation is complete. 31 24 23 16 15 87 A[2:0] 0 Transfer 1 — Byte 0 — — 001 Transfer 2 — — Byte 1 Byte 2 010 Transfer 3 Byte 3 — — — 100 Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port) If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the cache. The example in Figure 13-20 differs from that in Figure 13-19 in that the operand is word-sized and the transfer takes only two bus cycles. 13-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 External Interface Module (EIM) 31 Freescale Semiconductor 24 23 16 15 87 0 Transfer 1 — — — Byte 0 001 Transfer 2 Byte 1 — — — 100 Figure 13-20. Example of a Misaligned Word Transfer (32-Bit Port) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 External Interface Module (EIM) A[2:0] 13-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 External Interface Module (EIM) 13-16 Freescale Semiconductor This chapter describes the processor’s external signals. It includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used. Chapter 13, “External Interface Module (EIM),” describes how these signals interact. NOTE The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals. The term ‘asserted’ indicates that a signal is active, independent of the voltage level. The term ‘negated’ indicates that a signal is inactive. Active-low signals, such as SRAS and TA, are indicated with an overbar. 14.1 Overview Figure 14-1 shows the block diagram with the signal interface. Freescale Semiconductor 14-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 14 Signal Descriptions RCON Reset Controller RSTO JTAG Port TDI/DSI TRST/DSCLK TEA 4 JTAG_EN TEST RSTI TCLK TMS/BKPT PST[3:0] CLKMOD1 TDO/DSO Power Management Chip Configuration CLKMOD0 TA TS BS[3:0] 4 OE SIZ[1:0] 2 External Interface Module Test Controller Debug Module Ports Module DDATA[3:0] 4 ColdFire V2 Core R/W Flash Module VDDF TIP 64K SRAM 32 Note: Not present on MCF5280 24 DIV D[31:0] VSTBY EMAC A[23:0] 2-Kbyte D-Cache/I-Cache Edgeport IRQ[7:1] Interrupt Controller 0 Interrupt Controller 1 SDRAM_CS[1:0] 2 DMA Controller Chip Selects Internal Bus Arbiter 7 System Control Module (SCM) CS[6:0] DRAMW SRAS SCAS DRAM Controller SCKE UART0 Serial I/O CLKOUT DMA Timer Modules (DTIM0– DTIM3) ETXCLK I2C Module Watchdog Timer 4 XTAL Clock Module (PLL) UART2 Serial I/O 4 EXTAL UART1 Serial I/O ERXCLK ERXDV ERXD0 ECRS ETXD[3:1] ETXER SCL SDA DTOUT[3:0] DTIN[3:0] UTxD2 URxD2 URTS1 UCTS1 URTS0 UCTS0 UTxD1 URxD1 UTxD0 ECOL URxD0 ETXEN ETXDO FEC Note: Not present on MCF5214 and MCF5216 General Purpose Timer A QADC ERXD[3:1] General Purpose Timer B QSPI FlexCAN PIT Timers (PIT0– PIT3) CANRX CANTX QSPI_CLK QSPI_CS[3:0] QSPI_DIN QSPI_DOUT 4 GPTB[3:0] SYNCB SYNCA AN56/TRIG2 AN55/TRIG1 AN53/MA1 AN3/ANZ AN52/MA0 AN2/ANY AN1/ANX VREFL AN0/ANW EMDC VREFH EMDIO GPTA[3:0] 4 ERXER Figure 14-1. MCF5282 Block Diagram with Signal Interfaces 14-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Signal Descriptions Signal Descriptions Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-1 lists the external signals grouped by functionality. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality. Table 14-1. MCF5282 Signal Description Signal Name Abbreviation Function I/O Page External Memory Interface Address A[23:0] Define the address of external byte, word, longword, and 16-byte burst accesses. I/O 14-19 Data D[31:0] Data bus. Provide the general purpose data path between the MCU and all other devices. I/O 14-19 Byte strobes BS[3:0] Define the byte lane of data on the data bus. I/O 14-19 Output enable OE Indicates when an external device can drive data on the bus. O 14-19 Transfer acknowledge TA Indicates that the external data transfer is complete and should be asserted for one clock. I 14-19 Transfer error acknowledge TEA Indicates that an error condition exists for the bus transfer. I 14-20 Read/Write R/W Indicates the direction of the data transfer on the bus. I/O 14-20 Transfer size SIZ[1:0] Specify the data access size of the current external bus reference. O 14-20 Transfer start TS Asserted during the first CLKOUT cycle of a transfer when address and attributes are valid. O 14-20 Transfer in progress TIP Asserted to indicate that a bus transfer is in progress. Negated during idle bus cycles. O 14-21 Chip selects CS[6:0] Programmed for a base address location and for masking addresses, port size and burst capability indication, wait state generation, and internal/external termination. O 14-21 SDRAM Controller Signals SDRAM row address strobe SRAS SDRAM synchronous row address strobe. O 14-21 SDRAM column address strobe SCAS SDRAM synchronous column address strobe. O 14-21 Freescale Semiconductor 14-3 Signal Descriptions Signal Name Abbreviation Function I/O Page SDRAM write enable DRAMW Asserted to signify that a DRAM write cycle is underway. Negated to indicate a read cycle. O 14-21 SDRAM bank selects SDRAM_CS[1:0] Interface to the chip-select lines of the SDRAMs within a memory block. O 14-21 SDRAM clock enable SCKE SDRAM clock enable. O 14-22 Clock and Reset Signals Reset in RSTI Asserted to enter reset exception processing. I 14-22 Reset out RSTO Automatically asserted with RSTI. Negation indicates that the PLL has regained its lock. O 14-22 EXTAL EXTAL Driven by an external clock except when used as a connection to the external crystal. I 14-22 XTAL XTAL Internal oscillator connection to the external crystal. O 14-22 Clock output CLKOUT Reflects the system clock. O 14-22 Chip Configuration Module Clock mode CLKMOD[1:0] Clock mode select I 14-22 Reset configuration RCON Reset configuration select I 14-22 I 14-23 Transfers control information between the external PHY and the media access controller. I/O 14-23 Management data clock EMDC Provides a timing reference to the PHY for data transfers on the EMDIO signal. O 14-23 Transmit clock ETXCLK Provides a timing reference for ETXEN, ETXD[3:0], and ETXER. I 14-23 Transmit enable ETXEN Indicates when valid nibbles are present on the MII. O 14-23 Transmit data 0 ETXD0 Serial output Ethernet data. O 14-23 Collision ECOL Asserted to indicate a collision. I 14-24 Receive clock ERXCLK Provides a timing reference for ERXDV, ERXD[3:0], and ERXER. I 14-24 External Interrupt Signals External interrupts IRQ[7:1] External interrupt sources. Ethernet Module Signals (not available on MCF5214 and MCF5216) Management data 14-4 EMDIO Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-1. MCF5282 Signal Description (continued) Signal Descriptions Signal Name Abbreviation Function I/O Page Receive data valid ERXDV Asserted to indicate that the PHY has valid nibbles present on the MII. I 14-24 Receive data 0 ERXD0 Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted). I 14-24 Carrier receive sense ECRS Asserted to indicate that the transmit or receive medium is not idle. I 14-24 Transmit data ETXD[3:1] Contain the serial output Ethernet data. O 14-24 Transmit error ETXER Asserted (for one or more E_TXCLKs while ETXEN is also asserted) to cause the PHY to send one or more illegal symbols. O 14-24 Receive data ERXD[3:1] Contain the Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted in MII mode). I 14-24 Receive error ERXER Indicates (when asserted with ERXDV) that the PHY has detected an error in the current frame. I 14-25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-1. MCF5282 Signal Description (continued) Queued Serial Peripheral Interface (QSPI) Signals QSPI synchronous serial data output QSPI_DOUT Provides serial data from the QSPI. O 14-25 QSPI synchronous serial data input QSPI_DIN Provides serial data to the QSPI. I 14-25 QSPI serial clock QSPI_CLK Provides the serial clock from the QSPI. O 14-25 QSPI chip selects QSPI_CS[3:0] Provide QSPI peripheral chip selects. O 14-25 FlexCAN Signals FlexCAN transmit CANTX Controller area network transmit data. O 14-25 FlexCAN transmit CANRX Controller area network transmit data. I 14-25 I/O 14-26 I/O 14-26 I2C Signals Serial clock Serial data SCL SDA Clock signal for the I2C interface. Data input/output for the I2C interface. UART Signals Transmit serial data output UTXD[2:0] Transmitter serial data outputs. O 14-26 Receive serial data input URXD[2:0] Receiver serial data inputs. I 14-26 Freescale Semiconductor 14-5 Signal Descriptions Signal Name Abbreviation Function I/O Page Clear-to-send UCTS[1:0] Signals UART that it can begin data transmission. I 14-26 Request to send URTS[1:0] Automatic UART request to send outputs. O 14-27 General Purpose Timer Signals GPTA GPTA[3:0] Provide the external interface to the timer A functions. I/O 14-27 GPTB GPTB[3:0] Provide the external interface to the timer B functions. I/O 14-27 External clock input SYNCA/SYNCB Clear the timer’s clock, providing a means of synchronization to externally clocked or timed events. I 14-27 DMA Timer Signals DMA timer input DTIN[3:0] Clock the event counter or provide a trigger to timer value capture logic. I/O 14-27 DMA timer output DTOUT[3:0] Pulse or toggle on timer events. I/O 14-27 I 14-28 I/O 14-29 I 14-29 Analog-to-Digital Converter (QADC) Signals QADC analog input AN[0:3]/AN[W:Z] Direct analog input ANn, or multiplexed input ANx. QADC analog input AN[52:53]/MA[0:1] Direct analog input ANn, or multiplexed output MAn. MAn selects the output of the external multiplexer. QADC analog input AN[55:56]/ TRIG[1:2] Direct analog input ANn, or input TRIGn. TRIGn causes one of the two queues to execute. Debug Support Signals 14-6 JTAG_EN JTAG_EN Selects between multiplexed debug module and JTAG signals at reset. I 14-29 Development serial clock/Test reset DSCLK/TRST Development serial clock for the serial interface to debug module (DSCLK). Asynchronously resets the internal JTAG controller to the test logic reset state (TRST). I 14-30 Breakpoint/ Test mode select BKPT/TMS Signals a hardware breakpoint in debug mode (BKPT). Provides information that determines JTAG test operation mode (TMS). I 14-30 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-1. MCF5282 Signal Description (continued) Signal Descriptions Signal Name Abbreviation Function I/O Page Development serial input/Test data DSI/TDI Provides single-bit communication for debug module commands (DSI). Provides serial data port for loading JTAG boundary scan, bypass, and instruction registers (TDI). I 14-30 Development serial output/Test data DSO/TDO Provides single-bit communication for debug module responses (DSO). Provides serial data port for outputting JTAG logic data (TDO). O 14-30 Test clock TCLK JTAG test logic clock. I 14-30 Debug data DDATA[3:0] Display captured processor addresses, data, and breakpoint status. O 14-31 Processor status outputs PST[3:0] Indicate core status. O 14-31 I 14-31 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-1. MCF5282 Signal Description (continued) Test Signals Test TEST Reserved, should be connected to VSS. Power and Reference Signals QADC analog reference VRH, VRL High (VRH) and low (VRL) reference potentials for the analog converter. Ground 14-32 QADC analog supply VDDA, VSSA Isolate the QADC analog circuitry from digital power supply noise. I 14-32 PLL analog supply VDDPLL, VSSPLL Isolate the PLL analog circuitry from digital power supply noise. I 14-32 QADC positive supply VDDH Supplies positive power to the ESD structures in the QADC pads. I 14-32 Flash erase/program power VPP Used for Flash stress testing. I 14-32 Flash array power and ground VDDF, VSSF Supply power and ground to Flash array. I 14-32 Standby power VSTBY Provides standby voltage to RAM array if VDD is lost. I 14-32 Positive supply VDD Supplies positive power to the core logic and I/O pads. I 14-32 Ground VSS Negative supply. 14-32 Table 14-2 lists signals in alphabetical order by abbreviated name. Freescale Semiconductor 14-7 Signal Descriptions Abbreviation 14-8 Function I/O A[23:0] Define the address of external byte, word, longword, and 16-byte burst accesses. I/O AN[0:3]/AN[W:Z] Direct analog input ANn, or multiplexed input ANx. AN[52:53]/MA[0:1] Direct analog input ANn, or multiplexed output MAn. MAn selects the output of the external multiplexer. AN[55:56]/ TRIG[1:2] Direct analog input ANn, or input TRIGn. TRIGn causes one of the two queues to execute. I Breakpoint/ Test mode select Signals a hardware breakpoint in debug mode (BKPT). Provides information that determines JTAG test operation mode (TMS). I BS[3:0] Define the byte lane of data on the data bus. CANRX Controller area network transmit data. I CANTX Controller area network transmit data. O CLKMOD[1:0] Clock mode select I CLKOUT Reflects the system clock. O CS[6:0] Programmed for a base address location and for masking addresses, port size and burst capability indication, wait state generation, and internal/external termination. O D[31:0] Data bus. Provide the general purpose data path between the MCU and all other devices. I/O DDATA[3:0] Display captured processor addresses, data, and breakpoint status. O DSO/TDO Provides single-bit communication for debug module responses (DSO). Provides serial data port for outputting JTAG logic data (TDO). O DSI/TDI Development serial clock for the serial interface to debug module (DSCLK). Asynchronously resets the internal JTAG controller to the test logic reset state (TRST). I DSCLK/TRST Provides single-bit communication for debug module commands (DSI). Provides serial data port for loading JTAG boundary scan, bypass, and instruction registers (TDI). I DRAMW Asserted to signify that a DRAM write cycle is underway. Negated to indicate a read cycle. O DTIN[3:0] Clock the event counter or provide a trigger to timer value capture logic. I/O DTOUT[3:0] Pulse or toggle on timer events. I/O ECOL Asserted to indicate a collision. Note: Not available on MCF5214 and MCF5216 I ECRS Asserted to indicate that the transmit or receive medium is not idle. Note: Not available on MCF5214 and MCF5216 I I I/O I/O Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-2. MCF5282 Alphabetical Signal Index Signal Descriptions Abbreviation Function I/O EMDC Provides a timing reference to the PHY for data transfers on the EMDIO signal. Note: Not available on MCF5214 and MCF5216 O EMDIO Transfers control information between the external PHY and the media access controller. Note: Not available on MCF5214 and MCF5216 I/O ERXCLK Provides a timing reference for ERXDV, ERXD[3:0], and ERXER. Note: Not available on MCF5214 and MCF5216 I ERXD[3:1] Contain the Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted in MII mode). Note: Not available on MCF5214 and MCF5216 I ERXD0 Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted). Note: Not available on MCF5214 and MCF5216 I ERXDV Asserted to indicate that the PHY has valid nibbles present on the MII. Note: Not available on MCF5214 and MCF5216 I ERXER Indicates (when asserted with ERXDV) that the PHY has detected an error in the current frame. Note: Not available on MCF5214 and MCF5216 I ETXCLK Provides a timing reference for ETXEN, ETXD[3:0], and ETXER. Note: Not available on MCF5214 and MCF5216 I ETXD[3:1] Contain the serial output Ethernet data. Note: Not available on MCF5214 and MCF5216 O ETXD0 Serial output Ethernet data. Note: Not available on MCF5214 and MCF5216 O ETXEN Indicates when valid nibbles are present on the MII. Note: Not available on MCF5214 and MCF5216 O ETXER Asserted (for one or more E_TXCLKs while ETXEN is also asserted) to cause the PHY to send one or more illegal symbols. Note: Not available on MCF5214 and MCF5216 O EXTAL Driven by an external clock except when used as a connection to the external crystal. I VDDF, VSSF Supply power and ground to Flash array. I VPP Used for Flash stress testing. I GPTA[3:0] Provide the external interface to the timer A functions. I/O GPTB[3:0] Provide the external interface to the timer B functions. I/O Ground Negative supply. IRQ[7:1] External interrupt sources. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-2. MCF5282 Alphabetical Signal Index (continued) I 14-9 Signal Descriptions Abbreviation 14-10 Function I/O JTAG_EN Selects between multiplexed debug module and JTAG signals at reset. I OE Indicates when an external device can drive data on the bus. O VDDPLL Isolate the PLL analog circuitry from digital power supply noise. I VDD Supplies positive power to the core logic and I/O pads. I PST[3:0] Indicate core status. O VRH, VRL High (VRH) and low (VRL) reference potentials for the analog converter. I VDDA, VSSA Isolate the QADC analog circuitry from digital power supply noise. I QADC analog supply Supplies positive power to the ESD structures in the QADC pads. I QSPI_CLK Provides the serial clock from the QSPI. O QSPI_CS[3:0] Provide QSPI peripheral chip selects. O QSPI_DIN Provides serial data to the QSPI. I QSPI_DOUT Provides serial data from the QSPI. O R/W Indicates the direction of the data transfer on the bus. I/O RCON Reset configuration select. I RSTI Asserted to enter reset exception processing. I RSTO Automatically asserted with RSTI. Negation indicates that the PLL has regained its lock. O SCAS SDRAM synchronous column address strobe. O SCKE SDRAM clock enable. O I2C SCL Clock signal for the interface. I/O SDA Data input/output for the I2C interface. I/O SDRAM_CS[1:0] Interface to the chip-select lines of the SDRAMs within a memory block. O SIZ[1:0] Specify the data access size of the current external bus reference. O SRAS SDRAM synchronous row address strobe. O VSTBY Provides standby voltage to RAM array if VDD is lost. I SYNCA/SYNCB Clear the timer’s clock, providing a means of synchronization to externally clocked or timed events. I TA Indicates that the external data transfer is complete and should be asserted for one CLKOUT cycle. I TEA Indicates that an error condition exists for the bus transfer. I Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-2. MCF5282 Alphabetical Signal Index (continued) Signal Descriptions Abbreviation Function I/O TEST Reserved, should be connected to VSS. I TCK JTAG test logic clock. I TIP Asserted to indicate that a bus transfer is in progress. Negated during idle bus cycles. O TS Asserted during the first CLKOUT cycle of a transfer when address and attributes are valid. O UCTS[1:0] Signals UART that it can begin data transmission. I URTS[1:0] Automatic UART request to send outputs. O URXD[2:0] Receiver serial data inputs. I UTXD[2:0] Transmitter serial data outputs. O XTAL Internal oscillator connection to the external crystal. O Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function Pin Functions MAPBGA Pin Description Primary2 Secondary Tertiary Primary I/O Internal Pull-up1 Reset R11 RSTI — — Reset in I Yes P11 RSTO — — Reset out O — Clock T8 EXTAL — — External clock/crystal in I — R8 XTAL — — Crystal drive O — N7 CLKOUT — — Clock out O — Chip Configuration/Mode Selection R14 CLKMOD0 — — Clock mode select I Yes T14 CLKMOD1 — — Clock mode select I Yes T11 RCON — — Reset configuration enable I Yes H1 D26 PA2 — Chip mode I/O — K2 D17 PB1 — Chip mode I/O — K3 D16 PB0 — Chip mode I/O — J4 D19 PB3 — Boot device/data port size I/O — K1 D18 PB2 — Boot device/data port size I/O — J2 D21 PB5 — Output pad drive strength I/O — Freescale Semiconductor 14-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-2. MCF5282 Alphabetical Signal Index (continued) Signal Descriptions Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Primary I/O Internal Pull-up1 External Memory Interface and Ports C6:B6:A5 A[23:21] PF[7:5] CS[6:4] Address bus O Yes C4:B4:A4:B3:A3 A[20:16] PF[4:0] — Address bus O Yes A2:B1:B2:C1: C2:C3:D1:D2 A[15:8] PG[7:0] — Address bus O Yes D3:D4:E1:E2: E3:E4:F1:F2 A[7:0] PH[7:0] — Address bus O Yes F3:G1:G2:G3: G4:H1:H2:H3 D[31:24] PA[7:0] — Data bus I/O — H4:J1:J2:J3: J4:K1:K2:K3 D[23:16] PB[7:0] — Data bus I/O — L1:L2:L3:L4: M1:M2:M3:M4 D[15:8] PC[7:0] — Data bus I/O — N1:N2:N3:P1: N5:T6:R6:P6 D[7:0] PD[7:0] — Data bus I/O — P14:T15:R15:R16 BS[3:0] PJ[7:4] — Byte strobe I/O Yes N16 OE PE7 — Output enable I/O — P16 TA PE6 — Transfer acknowledge I/O Yes P15 TEA PE5 — Transfer error acknowledge I/O Yes N15 R/W PE4 — Read/write I/O Yes N14 SIZ1 PE3 SYNCA Transfer size I/O Yes3 M16 SIZ0 PE2 SYNCB Transfer size I/O Yes4 M15 TS PE1 SYNCA Transfer start I/O Yes M14 TIP PE0 SYNCB Transfer in progress I/O Yes Chip Selects L16:L15:L14:L13 CS[3:0] PJ[3:0] — Chip selects 3-0 I/O Yes C6:B6:A5 A[23:21] PF[7:5] CS[6:4] Chip selects 6-4 O Yes SDRAM Controller 14-12 H15 SRAS PSD5 — SDRAM row address strobe I/O — H16 SCAS PSD4 — SDRAM column address strobe I/O — G15 DRAMW PSD3 — SDRAM write enable I/O — H13:G16 SDRAM_CS[1:0] PSD[2:1] — SDRAM chip selects I/O — H14 SCKE PSD0 — SDRAM clock enable I/O — Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Signal Descriptions Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Primary I/O Internal Pull-up1 I/O — External Interrupts Port B15:B16:C14:C15: C16: D14:D15 IRQ[7:1] PNQ[7:1] — External interrupt request Ethernet For MCF5280, MCF5281 and MCF5282 only C10 EMDIO PAS5 URXD2 Management channel serial data I/O — B10 EMDC PAS4 UTXD2 Management channel clock I/O — A8 ETXCLK PEH7 — MAC Transmit clock I/O — D6 ETXEN PEH6 — MAC Transmit enable I/O — D7 ETXD0 PEH5 — MAC Transmit data I/O — B11 ECOL PEH4 — MAC Collision I/O — A10 ERXCLK PEH3 — MAC Receive clock I/O — C8 ERXDV PEH2 — MAC Receive enable I/O — D9 ERXD0 PEH1 — MAC Receive data I/O — A11 ECRS PEH0 — MAC Carrier sense I/O — A7:B7:C7 ETXD[3:1] PEL[7:5] — MAC Transmit data I/O — D10 ETXER PEL4 — MAC Transmit error I/O — A9:B9:C9 ERXD[3:1] PEL[3:1] — MAC Receive data I/O — B8 ERXER PEL0 — MAC Receive error I/O — GPIO For MCF5214 and MCF5216 only C10 PAS5 URXD2 — GPIO/serial data I/O — B10 NC — — No connect — — A8 PEL0 — — GPIO I/O — D6 NC — — No connect — — D7 NC — — No connect — — B11 NC — — No connect — — A10 PAS4 UTXD2 — GPIO/serial data I/O — C8 NC — — No connect — — D9 NC — — No connect — — A11 NC — — No connect — — Freescale Semiconductor 14-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Signal Descriptions Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Primary I/O Internal Pull-up1 A7:B7:C7 PEL[7:5] — — GPIO I/O — D10 PEL4 — — GPIO I/O — A9:B9:C9 PEL[3:1] — — GPIO I/O — B8 NC — — No connect — — FlexCAN D16 CANRX PAS3 URXD2 FlexCAN Receive data I/O — E13 CANTX PAS2 UTXD2 FlexCAN Transmit data I/O — I2C E14 SDA PAS1 URXD2 I2C Serial data I/O Yes5 E15 SCL PAS0 UTXD2 I2C Serial clock I/O Yes6 QSPI F13 QSPI_DOUT PQS0 — QSPI data out I/O — E16 QSPI_DIN PQS1 — QSPI data in I/O — F14 QSPI_CLK PQS2 — QSPI clock I/O — G14:G13:F16:F15 QSPI_CS[3:0] PQS[6:3] — QSPI chip select I/O — UARTs 14-14 R7 URXD1 PUA3 — U1 receive data I/O — P7 UTXD1 PUA2 — U1 transmit data I/O — N6 URXD0 PUA1 — U0 receive data I/O — T7 UTXD0 PUA0 — U0 transmit data I/O — D16 CANRX PAS3 URXD2 U2 receive data I/O — E13 CANTX PAS2 UTXD2 U2 transmit data I/O — E14 SDA PAS1 URXD2 U2 receive data I/O Yes5 E15 SCL PAS0 UTXD2 U2 transmit data I/O Yes6 K16 DTIN3 PTC3 URTS1/ URTS0 U1/U0 Request to Send I/O — K15 DTOUT3 PTC2 URTS1/ URTS0 U1/U0 Request to Send I/O — K14 DTIN2 PTC1 UCTS1/ UCTS0 U1/U0 Clear to Send I/O — K13 DTOUT2 PTC0 UCTS1/ UCTS0 U1/U0 Clear to Send I/O — Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Signal Descriptions Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Primary I/O Internal Pull-up1 J16 DTIN1 PTD3 URTS1/ URTS0 U1/U0 Request to Send I/O — J15 DTOUT1 PTD2 URTS1/ URTS0 U1/U0 Request to Send I/O — J14 DTIN0 PTD1 UCTS1/ UCTS0 U1/U0 Clear to Send I/O — J13 DTOUT0 PTD0 UCTS1/ UCTS0 U1/U0 Clear to Send I/O — Note: The below two pins are for the MCF5280, MCF5281, and MCF5282 only. C10 EMDIO PAS5 URXD2 U2 receive data I/O — B10 EMDC PAS4 UTXD2 U2 transmit data I/O — Note: The below two pins are for the MCF5214 and MCF5216 only. C10 PAS5 URXD2 — U2 receive data I/O — B10 NC — — No connect I/O — General Purpose Timers T13:R13:P13:N13 GPTA[3:0] PTA[3:0] — Timer A IC/OC/PAI I/O Yes T12:R12:P12:N12 GPTB[3:0] PTB[3:0] — Timer B IC/OC/PAI I/O Yes N14 SIZ1 PE3 SYNCA Timer A synchronization input I/O Yes3 M16 SIZ0 PE2 SYNCB Timer B synchronization input I/O Yes4 M15 TS PE1 SYNCA Timer A synchronization input I/O Yes M14 TIP PE0 SYNCB Timer B synchronization input I/O Yes DMA Timers K16 DTIN3 PTC3 URTS1/ URTS0 Timer 3 in I/O — K15 DTOUT3 PTC2 URTS1/ URTS0 Timer 3 out I/O — K14 DTIN2 PTC1 UCTS1/ UCTS0 Timer 2 in I/O — K13 DTOUT2 PTC0 UCTS1/ UCTS0 Timer 2 out I/O — J16 DTIN1 PTD3 URTS1/ URTS0 Timer 1 in I/O — J15 DTOUT1 PTD2 URTS1/ URTS0 Timer 1 out I/O — Freescale Semiconductor 14-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Signal Descriptions Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Primary I/O Internal Pull-up1 J14 DTIN0 PTD1 UCTS1/ UCTS0 Timer 0 in I/O — J13 DTOUT0 PTD0 UCTS1/ UCTS0 Timer 0 out I/O — Queued Analog-to-Digital Converter (QADC) T3 AN0 PQB0 ANW Analog channel 0 I/O — R2 AN1 PQB1 ANX Analog channel 1 I/O — T2 AN2 PQB2 ANY Analog channel 2 I/O — R1 AN3 PQB3 ANZ Analog channel 3 I/O — R4 AN52 PQA0 MA0 Analog channel 52 I/O — T4 AN53 PQA1 MA1 Analog channel 53 I/O — P3 AN55 PQA3 ETRIG1 Analog channel 55 I/O — R3 AN56 PQA4 ETRIG2 Analog channel 56 I/O — P4 VRH — — High analog reference I — T5 VRL — — Low analog reference I — Debug and JTAG Test Port Control R9 JTAG_EN — — JTAG Enable I — P9 DSCLK TRST — Debug clock / TAP reset I Yes7 T9 TCLK — — TAP clock I Yes7 P10 BKPT TMS — Breakpoint/TAP test mode select I Yes7 R10 DSI TDI — Debug data in / TAP data in I Yes7 T10 DSO TDO — Debug data out / TAP data out O — C12:D12:A13:B13 DDATA[3:0] PDD[7:4] — Debug data I/O — C13:A14:B14:A15 PST[3:0] PDD[3:0] — Processor status data I/O — I — Test N10 TEST — Test mode pin Power Supplies 14-16 R5 VDDA — — Analog positive supply I — P5:T1 VSSA — — Analog ground I — P2 VDDH — — ESD positive supply I — N8 VDDPLL — — PLL positive supply I — Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Signal Descriptions Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Primary I/O Internal Pull-up1 P8 VSSPLL — — PLL ground I — A6:C11 VPP — — Flash (stress) programming voltage I — A12:C5:D5:D11 VDDF — — Flash positive supply I — B5:B12: VSSF — — Flash module ground I — N11 VSTBY — — Standby power I — E6-E11:F5:F7-F10: F12:G5:G6:G11: G12:H5:H6:H11: H12:J5:J6:J11:J12: K5:K6:K11:K12:L5: L7-L10:L12: M6-M11 VDD — — Positive supply I — A1:A16:E5:E12:F6: F11:G7-G10:H7-H10 :J7-J10:K7-K10:L6: L11:M5:M12:T16 VSS — — Ground I — 1 2 3 4 5 6 7 Pull-ups are not active when GPIO functions are selected for the pins. The primary functionality of a pin is not necessarily its default functionality. Pins that have GPIO functionality will default to GPIO inputs. Pull-up is active only with the SYNCA function. Pull-up is active only with the SYNCB function. Pull-up is active only with the SDA function. Pull-up is active only with SCL function. Pull-up is active when JTAG_EN is driven high. 14.1.1 Single-Chip Mode In single-chip mode, signals default to GPIO inputs after a system reset. Table 14-4 is a listing of signals that do not default to a GPIO function. Table 14-4. Pin Reset States at Reset (Single-Chip Mode) Signal Reset I/O Clock and Reset Signals Freescale Semiconductor RSTI — I RSTO Low O EXTAL — I XTAL XTAL O CLKOUT CLKOUT O 14-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued) Signal Descriptions Signal Reset I/O Debug Support Signals 14.1.2 JTAG_EN — I DSCLK/TRST — I BKPT/TMS — I DSI/TDI — I DSO/TDO High O TCLK — I DDATA[3:0] DDATA{3:0] O PST[3:0] PST[3:0] O External Boot Mode When booting from external memory, the address bus, data bus, and bus control signals will default to their bus functionalities as shown in Table 14-5. As in single-chip mode, the signals listed in Table 14-4 will operate as described above. All other signals will default to GPIO inputs. Table 14-5. Default Signal Functions After System Reset (External Boot Mode) Signal 14.2 Reset I/O A[23:0] A[23:0] O D[31:0] — I/O BS[3:0] High O OE High O TA — I TEA — I R/W High O SIZ[1:0] High O TS High O TIP High O CS[6:0] High O External Signals The following sections describe the external signals on the device. 14.2.1 External Interface Module (EIM) Signals These signals are used for doing transactions on the external bus. 14-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 14-4. Pin Reset States at Reset (Single-Chip Mode) (continued) Signal Descriptions Address Bus (A[23:0]) The 24 dedicated address signals, A[23:0], define the address of external byte, word, longword and 16-byte burst accesses. These three-state outputs are the 24 lsbs of the internal 32-bit address bus. The address lines also serve as the SDRAM addressing, providing multiplexed row and column address signals. These pins are configured for GPIO ports F, G and H in single-chip mode. The A[23:21] pins can also be configured for CS[6:4]. 14.2.1.2 Data Bus (D[31:0]) These three-state bidirectional signals provide the general purpose data path between the MCU and all other devices. Data is sampled by the processor on the rising CLKOUT edge. The data bus port width and wait states are initially defined for the external boot chip select, CS0, by D[19:18] during chip configuration at reset. The port width for each chip select and SDRAM bank is programmable. The data bus uses a default configuration if none of the chip selects or SDRAM bank match the address decode. The default configuration is a 32-bit port with external termination and burst-inhibited transfers. The data bus can transfer byte, word, or longword data widths. All 32 data bus signals are driven during writes, regardless of port width and operand size. D[26:24, 21, 19:16] are used during chip configuration as inputs to configure the functions as described in Chapter 27, “Chip Configuration Module (CCM).” These pins are configured as GPIO ports A, B, C and D in single-chip mode. 14.2.1.3 Byte Strobes (BS[3:0]) The byte strobes (BS[3:0]) define the byte lane of data on the data bus. During accesses, these outputs act as the byte select signals that indicate valid data is to be latched or driven onto a byte lane when driven low. For SRAM or Flash devices, the BS[3:0] outputs should be connected to individual byte strobe signals. For SDRAM devices, the BS[3:0] should be connected to individual SDRAM DQM signals. Note that most SDRAMs associate DQM3 with the MSB, in which case BS3 is connected to the SDRAM's DQM3 input. These pins can also be configured as GPIO PJ[7:4]. 14.2.1.4 Output Enable (OE) This output signal indicates when an external device can drive data during external read cycles. This pin can also be configured as GPIO PE7. 14.2.1.5 Transfer Acknowledge (TA) This signal indicates that the external data transfer is complete. During a read cycle, when the processor recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the processor recognizes TA, the bus cycle is terminated. If all bus cycles support fast termination, TA can be tied low. This pin can also be configured as GPIO PE6. Freescale Semiconductor 14-19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.1.1 Signal Descriptions Transfer Error Acknowledge (TEA) This signal indicates an error condition exists for the bus transfer. The bus cycle is terminated and the CPU begins execution of the access error exception. This signal is an input in master mode. This pin can also be configured as GPIO PE5. 14.2.1.7 Read/Write (R/W) This output signal indicates the direction of the data transfer on the bus. A logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device. This pin can also be configured as GPIO PE4. 14.2.1.8 Transfer Size(SIZ[1:0]) When the device is in normal mode, static bus sizing lets the programmer change data bus width between 8, 16, and 32 bits for each chip select. The SIZ[1:0] outputs specify the data access size of the current external bus reference as shown in Table 14-6. Table 14-6. Transfer Size Encoding SIZ[1:0] Transfer Size 00 Longword 01 Byte 10 Word 11 16-byte line Note that for misaligned transfers, SIZ[1:0] indicate the size of each transfer. For example, if a longword access occurs at a misaligned offset of 0x1, a byte is transferred first (SIZ[1:0] = 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is transferred at offset 0x4 (SIZ[1:0] = 01). For aligned transfers larger than the port size, SIZ[1:0] behaves as follows: • If bursting is used, SIZ[1:0] stays at the size of transfer. • If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows the port size. For burst-inhibited transfers, SIZ[1:0] changes with each TS assertion to reflect the next transfer size. For transfers to port sizes smaller than the transfer size, SIZ[1:0] indicates the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers. For example, for a longword write to an 8-bit port, SIZ[1:0] = 00 for the first byte transfer and 01 for the next three. These pins can also be configured as GPIO PE[3:2] or SYNCA, SYNCB. 14.2.1.9 Transfer Start (TS) The device asserts TS during the first CLKOUT cycle of a transfer when address and attributes (TIP, R/W, and SIZ[1:0]) are valid. TS is negated in the following CLKOUT cycle. This pin can also be configured as GPIO PE1 or SYNCA. 14-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.1.6 Signal Descriptions The TIP output is asserted indicating a bus transfer is in progress. It is negated during idle bus cycles. Note that TIP is held asserted on back-to-back cycles. NOTE TIP is not asserted during SDRAM accesses. This pin can also be configured as GPIO PE0 or SYNCB. 14.2.1.11 Chip Selects (CS[6:0]) Each chip select can be programmed for a base address location and for masking addresses, port size and burst-capability indication, wait-state generation, and internal/external termination. Reset clears all chip select programming; CS0 is the only chip select initialized out of reset. CS0 is also unique because it can function at reset as a global chip select that allows boot ROM to be selected at any defined address space. The port size for boot CS0 is set during chip configuration by the levels on D[19:18] on the rising edge of RSTI, as described in Chapter 27, “Chip Configuration Module (CCM).” The chip-select implementation is described in Chapter 12, “Chip Select Module.” These pins can also be configured as A[23:21] and GPIO PJ[3:0]. 14.2.2 SDRAM Controller Signals These signals are used for SDRAM accesses. 14.2.2.1 SDRAM Row Address Strobe (SRAS) This output is the SDRAM synchronous row address strobe. This pin is configured as GPIO PSD5 in single-chip mode. 14.2.2.2 SDRAM Column Address Strobe (SCAS) This output is the SDRAM synchronous column address strobe. This pin is configured as GPIO PSD4 in single-chip mode. 14.2.2.3 SDRAM Write Enable (DRAMW) The DRAM write signal (DRAMW) is asserted to signify that a DRAM write cycle is underway. A read cycle is indicated by the negation of DRAMW. This pin is configured as GPIO PSD3 in single-chip mode. 14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0]) These signals interface to the chip-select lines of the SDRAMs within a memory block. Thus, there is one SDRAM_CS line for each memory block (the processor supports two SDRAM memory blocks). These pins is configured as GPIO PSD[2:1] in single-chip mode. Freescale Semiconductor 14-21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.1.10 Transfer In Progress (TIP) Signal Descriptions SDRAM Clock Enable (SCKE) This output is the SDRAM clock enable. This pin is configured as GPIO PSD0 in single-chip mode. 14.2.3 Clock and Reset Signals The clock and reset signals configure the device and provide interface signals to the external system. 14.2.3.1 Reset In (RSTI) Asserting RSTI causes the device to enter reset exception processing. When RSTI is recognized the address bus, data bus, SIZ, R/W, AS, and TS are three-stated. RSTO is asserted automatically when RSTI is asserted. 14.2.3.2 Reset Out (RSTO) After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the PLL regains its lock, RSTO negates again. This signal can be used to reset external devices. 14.2.3.3 EXTAL This input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. 14.2.3.4 XTAL This output is an internal oscillator connection to the external crystal. 14.2.3.5 Clock Output (CLKOUT) The internal PLL generates CLKOUT. This output reflects the internal system clock. 14.2.4 14.2.4.1 Chip Configuration Signals RCON If the external RCON signal is asserted, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins (see Section 27.6, “Functional Description”). The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration. 14.2.4.2 CLKMOD[1:0] The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. 14-22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.2.5 Signal Descriptions 14.2.5.1 External Interrupt Signals External Interrupts (IRQ[7:1]) These inputs are the external interrupt sources. See Chapter 11, “Edge Port Module (EPORT)” for more information on these interrupt sources and their corresponding registers. These pins are configured as GPIO PNQ[7:1] in single-chip mode. 14.2.6 Ethernet Module Signals The following signals are used by the Ethernet module for data and clock signals. NOTE These signals are not available on the MCF5214 and MCF5216. 14.2.6.1 Management Data (EMDIO) The bidirectional EMDIO signal transfers control information between the external PHY and the media-access controller. Data is synchronous to EMDC and applies to MII mode operation. This signal is an input after reset. When the FEC is operated in 10 Mbps 7-wire interface mode, this signal should be connected to VSS. This pin can also be configured as GPIO PAS5 or URXD2. 14.2.6.2 Management Data Clock (EMDC) EMDC is an output clock which provides a timing reference to the PHY for data transfers on the EMDIO signal and applies to MII mode operation. This pin can also be configured as GPIO PAS4 or UTXD2. 14.2.6.3 Transmit Clock (ETXCLK) This is an input clock which provides a timing reference for ETXEN, ETXD[3:0] and ETXER. This pin can also be configured as GPIO PEH7. 14.2.6.4 Transmit Enable (ETXEN) The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first ETXCLK following the final nibble of the frame. This pin can also be configured as GPIO PEH6. 14.2.6.5 Transmit Data 0 (ETXD0) ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode data in conjunction with ETXD[3:1]. This pin can also be configured as GPIO PEH5. Freescale Semiconductor 14-23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.5 Signal Descriptions Collision (ECOL) The ECOL input is asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. This pin can also be configured as GPIO PEH4. 14.2.6.7 Receive Clock (ERXCLK) The receive clock (ERXCLK) input provides a timing reference for ERXDV, ERXD[3:0], and ERXER. This pin can also be configured as GPIO PEH3. 14.2.6.8 Receive Data Valid (ERXDV) Asserting the receive data valid (ERXDV) input indicates that the PHY has valid nibbles present on the MII. ERXDV should remain asserted from the first recovered nibble of the frame through to the last nibble. Assertion of ERXDV must start no later than the SFD and exclude any EOF. This pin can also be configured as GPIO PEH2. 14.2.6.9 Receive Data 0 (ERXD0) ERXD0 is the Ethernet input data transferred from the PHY to the media-access controller when ErXDV is asserted. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode Ethernet data in conjunction with ERXD[3:1]. This pin can also be configured as GPIO PEH1. 14.2.6.10 Carrier Receive Sense (ECRS) ECRS is an input signal which, when asserted, signals that transmit or receive medium is not idle, and applies to MII mode operation. This pin can also be configured as GPIO PEH0. 14.2.6.11 Transmit Data 1–3 (ETXD[3:1]) These pins contain the serial output Ethernet data and are valid only during assertion of ETXEN in MII mode. These pins can also be configured as GPIO PEL[7:5]. 14.2.6.12 Transmit Error (ETXER) When the ETXER output is asserted for one or more E_TXCLKs while ETXEN is also asserted, the PHY sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated, and applies to MII mode operation. These pins can also be configured as GPIO PEL4. 14.2.6.13 Receive Data 1–3 (ERXD[3:1]) These pins contain the Ethernet input data transferred from the PHY to the media-access controller when ERXDV is asserted in MII mode operation. These pins can also be configured as GPIO PEL[3:1]. 14-24 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.6.6 Signal Descriptions ERXER is an input signal which when asserted along with ERXDV signals that the PHY has detected an error in the current frame. When ERXDV is not asserted ERXER has no effect, and applies to MII mode operation. These pins can also be configured as GPIO PEL0. 14.2.7 14.2.7.1 Queued Serial Peripheral Interface (QSPI) Signals QSPI Synchronous Serial Output (QSPI_DOUT) The QSPI_DOUT output provides the serial data from the QSPI and can be programmed to be driven on the rising or falling edge of QSPICLK. Each byte is sent msb first. This pin can also be configured as GPIO PQS0. 14.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN) The QSPI_DIN input provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPICLK. Each byte is written to RAM lsb first. This pin can also be configured as GPIO PQS1. 14.2.7.3 QSPI Serial Clock (QSPI_CLK) The QSPI serial clock (QSPI_CLK) provides the serial clock from the QSPI. The polarity and phase of QSPI_CLK are programmable. The output frequency is programmed according to the following formula, in which n can be any value between 2 and 255: QSPI_CLK = CLKOUT/(2n). This pin can also be configured as GPIO PQS2. 14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0]) The synchronous peripheral chip selects (QSPI_CS[3:0]) outputs provide QSPI peripheral chip selects that can be programmed to be active high or low. This pin can also be configured as GPIO PQS[6:3]. 14.2.8 14.2.8.1 FlexCAN Signals FlexCAN Transmit (CANTX) Controller Area Network Transmit data output. This pin can also be configured as GPIO PAS2. 14.2.8.2 FlexCAN Receive (CANRX) Controller Area Network Transmit data input. This pin can also be configured as GPIO PAS3. Freescale Semiconductor 14-25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.6.14 Receive Error (ERXER) Signal Descriptions I2C Signals The I2C module acts as a two-wire, bidirectional serial interface between the processor and peripherals with an I2C interface (such as LCD controller, A-to-D converter, or D-to-A converter). Devices connected to the I2C must have open-drain or open-collector outputs. 14.2.9.1 Serial Clock (SCL) This bidirectional open-drain signal is the clock signal for the I2C interface. Either it is driven by the I2C module when the bus is in the master mode or it becomes the clock input when the I2C is in the slave mode. This pin can also be configured as GPIO PAS0 or UTXD2. 14.2.9.2 Serial Data (SDA) This bidirectional open-drain signal is the data input/output for the I2C interface. This pin can also be configured as GPIO PAS1 or URXD2. 14.2.10 UART Module Signals The signals in the following sections are used to transfer serial data between three UART modules and external peripherals. 14.2.10.1 Transmit Serial Data Output (UTXD[2:0]) UTXD[2:0] are the transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, lsb first, on this pin at the falling edge of the serial clock source. The UTXD[1:0] pins can be configured as GPIO ports PUA2 and PUA0. The UTXD2 output is offered on 3 pins and is a secondary function of the EMDC/ GPIO port PAS4 pin, CANTX/GPIO port PAS2 pin, and SCL/GPIO port PAS0 pin. 14.2.10.2 Receive Serial Data Input (URXD[2:0]) URXD[2:0] are the receiver serial data inputs for the UART modules. Data received on these pins is sampled on the rising edge of the serial clock source lsb first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it. The URXD[1:0] pins can be configured as GPIO ports PUA3 and PUA1. The URXD2 input is offered on 3 pins and is a secondary function of the EMDIO/GPIO port PAS5 pin, CANRX/GPIO port PAS3 pin, and SDA/GPIO port PAS1 pin. 14.2.10.3 Clear-to-Send (UCTS[1:0]) The UCTS[1:0] signals are the clear-to-send (CTS) inputs, indicating to the UART modules that they can begin data transmission. The UCTS[1:0] inputs are each offered as secondary functions on four pins--DTIN2, DTOUT2, DTIN0 and DTOUT0. 14-26 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.9 Signal Descriptions The URTS[1:0] signals are automatic request to send outputs from the UART modules. URTS[1:0] can also be configured to be asserted and negated as a function of the Rx FIFO level. The URTS[1:0] outputs are each offered as secondary functions on four pins: DTIN3, DTOUT3, DTIN1 and DTOUT1. 14.2.11 General Purpose Timer Signals These pins provide the external interface to the general purpose timer functions. 14.2.11.1 GPTA[3:0] These pins provide the external interface to the timer A functions. These pins can also be configured as GPIO PTA[3:0]. 14.2.11.2 GPTB[3:0] These pins provide the external interface to the timer B functions. These pins can also be configured as GPIO PTB[3:0]. 14.2.11.3 External Clock Input (SYNCA/SYNCB) These pins are used to clear the clock for each of the two timers, and are provided as a means of synchronization to externally clocked or timed events. 14.2.12 DMA Timer Signals This section describes the signals of the four DMA timer modules. 14.2.12.1 DMA Timer 0 Input (DTIN0) The DMA timer 0 input (DTIN0) can be programmed to cause events to occur in DMA timer 0. It can either clock the event counter or provide a trigger to the timer value capture logic. This pin can also be configured as GPIO PTD1, secondary function UCTS1, or secondary function UCTS0. 14.2.12.2 DMA Timer 0 Output (DTOUT0) The programmable DMA timer output (DTOUT0) pulse or toggle on various timer events. This pin can also be configured as GPIO PTD0, secondary function UCTS1, or secondary function UCTS0. 14.2.12.3 DMA Timer 1 Input (DTIN1) The DMA timer 1 input (DTIN1) can be programmed to cause events to occur in DMA timer 1. This can either clock the event counter or provide a trigger to the timer value capture logic. Freescale Semiconductor 14-27 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.10.4 Request-to-Send (URTS[1:0]) Signal Descriptions 14.2.12.4 DMA Timer 1 Output (DTOUT1) The programmable DMA timer output (DTOUT1) pulse or toggle on various timer events. This pin can also be configured as GPIO PTD2, secondary function URTS1, or secondary function URTS0. 14.2.12.5 DMA Timer 2 Input (DTIN2) The DMA timer 2 input (DTIN2) can be programmed to cause events to occur in DMA timer 2. It can either clock the event counter or provide a trigger to the timer value capture logic. This pin can also be configured as GPIO PTC1, secondary function UCTS1, or secondary function UCTS0. 14.2.12.6 DMA Timer 2 Output (DTOUT2) The programmable DMA timer output (DTOUT2) pulse or toggle on various timer events. This pin can also be configured as GPIO PTC0, secondary function UCTS1, or secondary function UCTS0. 14.2.12.7 DMA Timer 3 Input (DTIN3) The DMA timer 3 input (DTIN3) can be programmed as an input that causes events to occur in DMA timer 3. This can either clock the event counter or provide a trigger to the timer value capture logic. This pin can also be configured as GPIO PTC3, secondary function URTS1, or secondary function URTS0. 14.2.12.8 DMA Timer 3 Output (DTOUT3) The programmable DMA timer output (DTOUT0) pulse or toggle on various timer events. This pin can also be configured as GPIO PTC2, secondary function URTS1, or secondary function URTS0. 14.2.13 Analog-to-Digital Converter Signals These pins provide the analog inputs to the QADC. The PQA and PQB pins may also be used as general purpose digital I/O. 14.2.13.1 QADC Analog Input (AN0/ANW) This PQB signal is the direct analog input AN0. When using external multiplexing this pin can also be configured as multiplexed input ANW. This pin can also be configured as GPIO PQB0. 14.2.13.2 QADC Analog Input (AN1/ANX) This PQB signal is the direct analog input AN1. When using external multiplexing this pin can also be configured as multiplexed input ANX. This pin can also be configured as GPIO PQB1. 14-28 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 This pin can also be configured as GPIO PTD3, secondary function URTS1, or secondary function URTS0. Signal Descriptions This PQB signal is the direct analog input AN2. When using external multiplexing this pin can also be configured as multiplexed input ANY. This pin can also be configured as GPIO PQB2. 14.2.13.4 QADC Analog Input (AN3/ANZ) This PQB signal is the direct analog input AN3. When using external multiplexing this pin can also be configured as multiplexed input ANZ. This pin can also be configured as GPIO PQB3. 14.2.13.5 QADC Analog Input (AN52/MA0) This PQA signal is the direct analog input AN52. When using external multiplexing this pin can also be configured as an output signal, MA0, to select the output of the external multiplexer. This pin can also be configured as GPIO PQA0. 14.2.13.6 QADC Analog Input (AN53/MA1) This PQA signal is the direct analog input AN53. When using external multiplexing this pin can also be configured as an output signal, MA1, to select the output of the external multiplexer. This pin can also be configured as GPIO PQA1. 14.2.13.7 QADC Analog Input (AN55/TRIG1) This PQA signal is the direct analog input AN55. This pin can also be configured as an input signal, TRIG1, to trigger the execution of one of the two queues. This pin can also be configured as GPIO PQA3. 14.2.13.8 QADC Analog Input (AN56/TRIG2) This PQA signal is the direct analog input AN56. This pin can also be configured as an input signal, TRIG2, to trigger the execution of one of the two queues. This pin can also be configured as GPIO PQA4. 14.2.14 Debug Support Signals These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM logic. 14.2.14.1 JTAG_EN This input signal is used to select between multiplexed debug module and JTAG signals at reset. If JTAG_EN is low, the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode. Freescale Semiconductor 14-29 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.13.3 QADC Analog Input (AN2/ANY) Signal Descriptions Debug mode operation: DSCLK is selected. DSCLK is the development serial clock for the serial interface to the debug module. The maximum DSCLK frequency is 1/5 CLKIN. JTAG mode operation: TRST is selected. TRST asynchronously resets the internal JTAG controller to the test logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this occurs, JTAG logic is benign and does not interfere with normal device functionality. Although TRST is asynchronous, Freescale recommends that it makes an asserted-to-negated transition only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to a logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to VDD. Tying TRST to ground places the JTAG controller in test logic reset state immediately. Tying it to VDD causes the JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks. 14.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS) Debug mode operation: If JTAG_EN is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug mode. JTAG mode operation: TMS is selected. The TMS input provides information to determine the JTAG test operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current state or advances to the next state. This directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up resistor so that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be tied to VDD. 14.2.14.4 Development Serial Input/Test Data (DSI/TDI) Debug mode operation: If JTAG_EN is low, DSI is selected. DSI provides the single-bit communication for debug module commands. JTAG mode operation: TDI is selected. TDI provides the serial data port for loading the various JTAG boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG controller state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge. TDI has an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it should be tied to VDD. 14.2.14.5 Development Serial Output/Test Data (DSO/TDO) Debug mode operation: DSO is selected. DSO provides single-bit communication for debug module responses. JTAG mode operation: TDO is selected. The TDO output provides the serial data port for outputting data from JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in the instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test data, it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices having JTAG. 14.2.14.6 Test Clock (TCLK) TCK is the dedicated JTAG test logic clock independent of the processor clock. Various JTAG operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground. 14-30 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST) Signal Descriptions Debug data signals (DDATA[3:0]) display captured processor addresses, data and breakpoint status. These pins can also be configured as GPIO PDD[7:4]. 14.2.14.8 Processor Status Outputs (PST[3:0]) PST[3:0] outputs indicate core status, as shown below in Table 14-7. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. These pins can also be configured as GPIO PDD[3:0]. Table 14-7. Processor Status Encoding PST[3:0] Definition 0000 Continue execution 0001 Begin execution of an instruction 0010 Reserved 0011 Entry into user mode 0100 Begin execution of PULSE and WDDATA instruction 0101 Begin execution of taken branch 0110 Reserved 0111 Begin execution of RTE instruction 1000 Begin one-byte transfer on DDATA 1001 Begin two-byte transfer on DDATA 1010 Begin three-byte transfer on DDATA 1011 Begin four-byte transfer on DDATA 1100 Exception Processing 1101 Emulator-Mode Exception Processing 1110 Processor is stopped 1111 Processor is halted 14.2.15 Test Signals 14.2.15.1 Test (TEST) This input signal is reserved for factory testing only and should be connected to VSS to prevent unintentional activation of test functions. Freescale Semiconductor 14-31 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.14.7 Debug Data (DDATA[3:0]) Signal Descriptions These signals provide system power, ground and references to the device. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 14.2.16.1 QADC Analog Reference (VRH, VRL) These signals serve as the high (VRH) and low (VRL) reference potentials for the analog converter in the QADC. 14.2.16.2 QADC Analog Supply (VDDA, VSSA) These are dedicated power supply signals to isolate the sensitive QADC analog circuitry from the normal levels of noise present on the digital power supply. 14.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL) These are dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply. 14.2.16.4 QADC Positive Supply (VDDH) This pin supplies positive power to the ESD structures in the QADC pads. 14.2.16.5 Power for Flash Erase/Program (VPP) This pin is used for Flash stress testing and can be left unconnected in normal device operation. 14.2.16.6 Power and Ground for Flash Array (VDDF, VSSF) These signals supply a power and ground to the Flash array. 14.2.16.7 Standby Power (VSTBY) This pin is used to provide standby voltage to the RAM array if VDD is lost. 14.2.16.8 Positive Supply (VDD) This pin supplies positive power to the core logic and I/O pads. 14.2.16.9 Ground (VSS) This pin is the negative supply (ground) to the chip. 14-32 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 14.2.16 Power and Reference Signals This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations. It also includes extensive examples that the designer can follow to better understand how to configure the DRAM controller for synchronous operations. 15.1 Overview The synchronous DRAM controller module provides glueless integration of SDRAM with the ColdFire product. The key features of the DRAM controller include the following: • Support for two independent blocks of SDRAM • Interface to standard SDRAM components • Programmable SRAS, SCAS, and refresh timing • Support for 8-, 16-, and 32-bit wide SDRAM blocks 15.1.1 Definitions The following terminology is used in this chapter: • SDRAM block: Any group of DRAM memories selected by one of the SRAS[1:0] signals. Thus, the processor can support two independent memory blocks. The base address of each block is programmed in the DRAM address and control registers (DACR0 and DACR1). • SDRAM: RAMs that operate like asynchronous DRAMs but with a synchronous clock, a pipelined, multiple-bank architecture, and a faster speed. • SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM component might be configured as four 512K x 32 banks. Banks are selected through the SDRAM component’s bank select lines. 15.1.2 Block Diagram and Major Components The basic components of the SDRAM controller are shown in Figure 15-1. Freescale Semiconductor 15-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 15 Synchronous DRAM Controller Module DRAM Controller Module D[31:0] internal Q[31:0] internal Data Generation A[23:0] Address Multiplexing Internal Bus Control Logic and State Machine Memory Block 0 Hit Logic DRAM Address/Control Register 0 (DACR0) DRAM Control Register (DCR) Memory Block 1 Hit Logic DRAM Address/Control Register 1 (DACR1) D[31:0] D[31:0] A[23:0] SCAS SRAS SCKE SDRAM_CS[1:0] DRAMW BS[3:0] Refresh Counter Figure 15-1. Synchronous DRAM Controller Block Diagram The DRAM controller’s major components are as follows: • DRAM address and control registers (DACR0 and DACR1)—The DRAM controller consists of two configuration register units, one for each supported memory block. DACR0 is accessed at IPSBAR + 0x048; DACR1 is accessed at IPSBAR + 0x050. The register information is passed on to the hit logic. • Control logic and state machine—Generates all SDRAM signals, taking hit information and bus-cycle characteristic data from the block logic in order to generate SDRAM accesses. Handles refresh requests from the refresh counter. — DRAM control register (DCR)—Contains data to control refresh operation of the DRAM controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC]. — Refresh counter—Determines when refresh should occur; controlled by the value of DCR[RC]. It generates a refresh request to the control block. • Hit logic—Compares address and attribute signals of a current SDRAM bus cycle to both DACRs to determine if an SDRAM block is being accessed. Hits are passed to the control logic along with characteristics of the bus cycle to be generated. • Address multiplexing—Multiplexes addresses to allow column and row addresses to share pins. This allows glueless interface to SDRAMs. • Data Generation—Controls the data input and data output transmission between the on-platform and off-platform data buses. 15-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Synchronous DRAM Controller Module Synchronous DRAM Controller Module SDRAM Controller Operation By running synchronously with the system clock, SDRAM can (after an initial latency period) be accessed on every clock; 5-1-1-1 is a typical burst rate to the SDRAM. Unlike the MCF5272, this processor does not have an independent SDRAM clock signal. For this processor, the timing of the SDRAM controller is controlled by the CLKOUT signal. Note that because the processor cannot have more than one page open at a time, it does not support interleaving. SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not only must they manage addresses and data, but they must send special commands for such functions as precharge, read, write, burst, auto-refresh, and various combinations of these functions. Table 15-1 lists common SDRAM commands. Table 15-1. SDRAM Commands Command Definition ACTV Activate. Executed before READ or WRITE executes; SDRAM registers and decodes row address. MRS Mode register set. NOP No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; SDRAM_CS[1:0] asserted. PALL Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is opened. READ Read access. SDRAM registers column address and decodes that a read access is occurring. REF Refresh. Refreshes internal bank rows of an SDRAM component. SELF Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode. SELFX Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared. WRITE Write access. SDRAM registers column address and decodes that a write access is occurring. SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data pipelines and commands to initiate special actions. Commands are issued to memory using specific encodings on address and control pins. Soon after system reset, a command must be sent to the SDRAM mode register to configure SDRAM operating parameters. Freescale Semiconductor 15-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.2 Synchronous DRAM Controller Module DRAM Controller Signals Table 15-2 describes the behavior of DRAM signals in synchronous mode. Table 15-2. Synchronous DRAM Signal Connections Signal Description SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SRAS should be connected to the corresponding SDRAM SRAS. SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SCAS should be connected to the corresponding SDRAM SCAS. DRAMW DRAM read/write. Asserted for write operations and negated for read operations. SDRAM_CS[1:0 Row address strobe. Select each memory block of SDRAMs connected to the processor. One ] SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals. SCKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode in which operations are suspended or capable of entering self-refresh mode. SCKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SCKE to provide command-bit functionality. BS[3:0] Column address strobe. BS[3:0] function as byte enables to the SDRAMs. They connect to the BS signals (or mask qualifiers) of the SDRAMs. 15.2.2 Memory Map for SDRAMC Registers The DRAM controller registers memory map is shown in Table 15-3. Table 15-3. DRAM Controller Registers IPSBAR Offset 0x040 [31:24] [23:16] [15:8] DRAM control register (DCR) [p. 15-4] [7:0] — 0x044 — 0x048 DRAM address and control register 0 (DACR0) [p. 15-6] 0x04C DRAM mask register block 0 (DMR0) [p. 15-8] 0x050 DRAM address and control register 1 (DACR1) [p. 15-6] 0x054 DRAM mask register block 1 (DMR1) [p. 15-8] 15.2.2.1 DRAM Control Register (DCR) The DCR, shown in Figure 15-2, controls refresh logic. 15-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.2.1 Synchronous DRAM Controller Module Field 14 — 13 12 11 NAM COC 10 IS Reset 9 8 0 RTIM Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15 RC Uninitialized R/W R/W Addr IPSBAR + 0x040 Figure 15-2. DRAM Control Register (DCR) Table 15-4 describes DCR fields. Table 15-4. DCR Field Descriptions Bits Name 15-14 — 13 NAM No address multiplexing. Some implementations require external multiplexing. For example, when linear addressing is required, the SDRAM should not multiplex addresses on SDRAM accesses. 0 The SDRAM controller multiplexes the external address bus to provide column addresses. 1 The SDRAM controller does not multiplex the external address bus to provide column addresses. 12 COC Command on SDRAM clock enable (SCKE). Implementations that use external multiplexing (NAM = 1) must support command information to be multiplexed onto the SDRAM address bus. 0 SCKE functions as a clock enable; self-refresh is initiated by the SDRAM controller through DCR[IS]. 1 SCKE drives command information. Because SCKE is not a clock enable, self-refresh cannot be used (setting DCR[IS]). Thus, external logic must be used if this functionality is desired. External multiplexing is also responsible for putting the command information on the proper address bit. 11 IS Initiate self-refresh command. 0 Take no action or issue a SELFX command to exit self refresh. 1 If DCR[COC] = 0, the SDRAM controller sends a SELF command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared. When IS is cleared, the controller sends a SELFX command for the SDRAMs to exit self-refresh. The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period. 10–9 8–0 Description Reserved, should be cleared. RTIM Refresh timing. Determines the timing operation of auto-refresh in the SDRAM controller. Specifically, it determines the number of bus clocks inserted between a REF command and the next possible ACTV command. This same timing is used for both memory blocks controlled by the SDRAM controller. This corresponds to tRC in the SDRAM specifications. 00 3 clocks 01 6 clocks 1x 9 clocks RC Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is (RC + 1) x 16. Refresh can range from 16–8192 bus clocks to accommodate both standard and low-power SDRAMs with bus clock operation from less than 2 MHz to greater than 50 MHz. The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 ms of refresh every 15.625 µs for each row (1031 bus clocks at 66 MHz). This operation is the same as in asynchronous mode. # of bus clocks = 1031 = (RC field + 1) x 16 RC = (1031 bus clocks/16) -1 = 63.44, which rounds to 63; therefore, RC = 0x3F. Freescale Semiconductor 15-5 Synchronous DRAM Controller Module DRAM Address and Control Registers (DACR0/DACR1) The DACRn registers, shown in Figure 15-3, contain the base address compare value and the control bits for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also controlled by bits in DACRn. 31 Field 18 17 16 15 14 13 12 11 10 9 BA Reset — RE — CASL — Uninitialized 0 R/W 8 CBM 7 6 5 4 3 — IMRS PS IP Uninitialized 0 2 0 — Uninitialized R/W Address IPSBAR+0x048 (DACR0); 0x050 (DACR1) Figure 15-3. DRAM Address and Control Register (DACRn) Table 15-5 describes DACRn fields. Table 15-5. DACRn Field Descriptions Bit Name 31–18 BA Base address register. With DCMR[BAM], determines the address range in which the associated DRAM block is located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the same as in asynchronous operation. 17–16 — Reserved, should be cleared. 15 RE Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM block. 0 Do not refresh associated DRAM block 1 Refresh associated DRAM block 14 — Reserved, should be cleared. 13–12 Description CASL CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature: Number of Bus Clocks Parameter CASL= 00 CASL = 01 CASL= 10 CASL= 11 11 15-6 — tRCD—SRAS assertion to SCAS assertion 1 2 3 3 tCASL—SCAS assertion to data out 1 2 3 3 tRAS—ACTV command to precharge command 2 4 6 6 tRP—Precharge command to ACTV command 1 2 3 3 tRWL,tRDL—Last data input to precharge command 1 1 1 1 tEP—Last data out to precharge command 1 1 1 1 Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.2.2.2 Synchronous DRAM Controller Module Bit Name 10–8 CBM Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 15-5. DACRn Field Descriptions (continued) Description Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and bank select lines to correspond to different addresses, these resources are programmable. CBM determines the addresses onto which these functions are multiplexed. Note: It is important to set CBM according to the location of the command bit. CBM Command Bit Bank Select Bits 000 17 18 and up 001 18 19 and up 010 19 20 and up 011 20 21 and up 100 21 22 and up 101 22 23 and up 110 23 24 and up 111 24 25 and up This encoding and the address multiplexing scheme handle common SDRAM organizations. Bank select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits. 7 6 — Reserved, should be cleared. IMRS Initiate mode register set (MRS) command. Setting IMRS generates a MRS command to the associated SDRAMs. In initialization, IMRS should be set only after all DRAM controller registers are initialized and PALL and REFRESH commands have been issued. After IMRS is set, the next access to an SDRAM block programs the SDRAM’s mode register. Thus, the address of the access should be programmed to place the correct mode information on the SDRAM address pins. Because the SDRAM does not register this information, it doesn’t matter if the IMRS access is a read or a write or what, if any, data is put onto the data bus. The DRAM controller clears IMRS after the MRS command finishes. 0 Take no action 1 Initiate MRS command 5–4 PS Port size. Indicates the port size of the associated block of SDRAM, which allows for dynamic sizing of associated SDRAM accesses. PS functions the same in asynchronous operation. 00 32-bit port 01 8-bit port 1x 16-bit port 3 IP Initiate precharge all (PALL) command. The DRAM controller clears IP after the PALL command is finished. Accesses via IP should be no wider than the port size programmed in PS. 0 Take no action. 1 A PALL command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the PALL command to the SDRAM block. 2–0 — Reserved, should be cleared. Freescale Semiconductor 15-7 Synchronous DRAM Controller Module DRAM Controller Mask Registers (DMR0/DMR1) The DMRn, Figure 15-4, includes mask bits for the base address and for address attributes. 31 18 17 Field 9 BAM — Reset 8 7 6 5 4 3 2 1 0 WP — C/I AM SC SD UC UD V Uninitialized 0 R/W R/W Addr IPSBAR + 0x04C (DMR0), 0x054 (DMR1) Figure 15-4. DRAM Controller Mask Registers (DMRn) Table 15-6 describes DMRn fields. Table 15-6. DMRn Field Descriptions Bits Name 31–18 BAM 17–9 — 8 WP 7 — 6–1 AMx Description Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various DRAM sizes. Mask bits need not be contiguous (see Section 15.3, “SDRAM Example.”) 0 The associated address bit is used in decoding the DRAM hit to a memory block. 1 The associated address bit is not used in the DRAM hit decode. Reserved, should be cleared. Write protect. Determines whether the associated block of DRAM is write protected. 0 Allow write accesses 1 Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs. Reserved, should be cleared. Address modifier masks. Determine which accesses can occur in a given DRAM block. 0 Allow access type to hit in DRAM 1 Do not allow access type to hit in DRAM Bit 0 15-8 V Associated Access Type Access Definition C/I CPU space/interrupt acknowledge MOVEC instruction or interrupt acknowledge cycle AM Alternate master DMA master SC Supervisor code Any supervisor-only instruction access SD Supervisor data Any data fetched during the instruction access UC User code Any user instruction UD User data Any user data Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded. 0 Do not decode DRAM accesses. 1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.2.2.3 Synchronous DRAM Controller Module General Synchronous Operation Guidelines To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller provides SDRAM control signals as well as a multiplexed row address and column address to the SDRAM. 15.2.3.1 Address Multiplexing Table 15-7 shows the generic address multiplexing scheme for SDRAM configurations. All possible address connection configurations can be derived from this table. NOTE Because the processor has 24 extermal address lines, the maximum SDRAM address size is 128 Mbits. The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the ColdFire processor to the SDRAM. To use the tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the processor, which is not necessarily the SDRAM port size. For example, if two 1M x 16-bit SDRAMs together form a 1M x 32-bit memory, the port size is 32 bits. Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected. Table 15-7. Generic Address Multiplexing Scheme Address Pin Row Address Column Address 17 17 0 8-bit port only 16 16 1 8- and 16-bit ports only 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 17 17 16 32-bit port only 18 18 17 16-bit port only or 32-bit port with only 8 column address lines 19 19 18 16-bit port only when at least 9 column address lines are used 20 20 19 21 21 20 22 22 21 23 23 22 Freescale Semiconductor Notes Relating to Port Sizes 15-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.2.3 Table 15-8. Processor to SDRAM Interface (8-Bit Port, 9-Column Address Lines) Process A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 or Pins Row 17 16 15 14 13 12 11 10 9 Column 0 1 2 3 4 5 6 7 8 SDRAM Pins 18 19 20 21 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Table 15-9. Processor to SDRAM Interface (8-Bit Port,10-Column Address Lines) Process A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 or Pins Row 17 16 15 14 13 12 11 10 9 19 Column 0 1 2 3 4 5 6 7 8 18 SDRAM Pins 20 21 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Table 15-10. Processor to SDRAM Interface (8-Bit Port,11-Column Address Lines) Processo A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 r Pins Row 17 16 15 14 13 12 11 10 9 19 21 Column 0 1 2 3 4 5 6 7 8 18 20 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 22 23 A9 A10 A11 A12 Table 15-11. Processor to SDRAM Interface (8-Bit Port,12-Column Address Lines) Processor A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 Pins Row 17 16 15 14 13 12 11 10 9 19 21 23 Column 0 1 2 3 4 5 6 7 8 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Table 15-12. Processor to SDRAM Interface (8-Bit Port,13-Column Address Lines) Process or Pins 15-10 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 Row 17 16 15 14 13 12 11 10 9 19 21 23 Column 0 1 2 3 4 5 6 7 8 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Synchronous DRAM Controller Module Synchronous DRAM Controller Module Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 15-13. Processor to SDRAM Interface (16-Bit Port, 8-Column Address Lines) Process A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 or Pins Row 16 15 14 13 12 11 10 9 Column 1 2 3 4 5 6 7 8 SDRAM Pins 17 18 19 20 21 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Table 15-14. Processor to SDRAM Interface (16-Bit Port, 9-Column Address Lines) Processo A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 r Pins Row 16 15 14 13 12 11 10 9 18 Column 1 2 3 4 5 6 7 8 17 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 19 20 21 22 23 A9 A10 A11 A12 A13 Table 15-15. Processor to SDRAM Interface (16-Bit Port, 10-Column Address Lines) Processo A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 r Pins Row 16 15 14 13 12 11 10 9 18 20 21 22 23 Column 1 2 3 4 5 6 7 8 17 19 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Table 15-16. Processor to SDRAM Interface (16-Bit Port, 11-Column Address Lines) Processo A16 A15 A14 A13 A12 A11 A10 r Pins A9 A18 A20 A22 A23 Row 16 15 14 13 12 11 10 9 18 20 22 Column 1 2 3 4 5 6 7 8 17 19 21 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 23 A10 A11 Table 15-17. Processor to SDRAM Interface (16-Bit Port, 12-Column Address Lines) Processor A16 Pins A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 Row 16 15 14 13 12 11 10 9 18 20 22 Column 1 2 3 4 5 6 7 8 17 19 21 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Freescale Semiconductor 15-11 Synchronous DRAM Controller Module Processo A16 r Pins A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 Row 16 15 14 13 12 11 10 9 18 20 22 Column 1 2 3 4 5 6 7 8 17 19 21 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Table 15-19. Processor to SDRAM Interface (32-Bit Port, 8-Column Address Lines) Processo A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 r Pins Row 15 14 13 12 11 10 9 17 Column 2 3 4 5 6 7 8 16 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 18 19 20 21 22 23 A7 A8 A9 A10 A11 A12 A13 Table 15-20. Processor to SDRAM Interface (32-Bit Port, 9-Column Address Lines) Processor A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 Pins Row 15 14 13 12 11 10 9 17 19 20 Column 2 3 4 5 6 7 8 16 18 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 21 22 23 A9 A10 A11 A12 Table 15-21. Processor to SDRAM Interface (32-Bit Port, 10-Column Address Lines) Processor A15 A14 A13 A12 A11 A10 Pins A9 A17 A19 A21 A22 A23 Row 15 14 13 12 11 10 9 17 19 21 Column 2 3 4 5 6 7 8 16 18 20 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 22 23 A10 A11 Table 15-22. Processor to SDRAM Interface (32-Bit Port, 11-Column Address Lines) Processor Pins 15-12 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 15-18. Processor to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) Synchronous DRAM Controller Module Processor Pins 15.2.3.2 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 SDRAM Byte Strobe Connections Figure 15-5 shows SDRAM connections for port sizes of 32, 16, or 8 bits. Byte Enable BS3 BS2 BS1 BS0 Processor External Data Bus D[31:24] D[23:16] D[15:8] D[7:0] 32-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 16-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 8-Bit Port Memory Driven with indeterminate values Byte 0 Byte 1 Driven with indeterminate values Byte 2 Byte 3 Figure 15-5. Connections for External Memory Port Sizes 15.2.3.3 Interfacing Example The tables in the previous section can be used to configure the interface in the following example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns), use the connections shown in Table 15-24. Table 15-24. SDRAM Hardware Connections SDRAM Pins A0 Processor Pins A15 15.2.3.4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 Burst Page Mode SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SCAS is issued, the SDRAM accepts a new address and asserts SCAS every CLKOUT for as long as accesses occur in that page. In burst page mode, there are multiple read or write operations for every ACTV command in the SDRAM if the requested transfer size exceeds the port size of the associated SDRAM. The primary cycle of the transfer generates the ACTV and READ or WRITE commands; secondary cycles generate only READ or WRITE commands. As soon as the transfer completes, the PALL command is generated to prepare for the next access. Freescale Semiconductor 15-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 15-23. Processor to SDRAM Interface (32-Bit Port, 12-Column Address Lines) Note that in synchronous operation, burst mode and address incrementing during burst cycles are controlled by the DRAM controller. Thus, instead of the SDRAM enabling its internal burst incrementing capability, the processor controls this function. This means that the burst function that is enabled in the mode register of SDRAMs must be disabled when interfacing to the processor. Figure 15-6 shows a burst read operation. In this example, DACR[CASL] = 01 for an SRAS-to-SCAS delay (tRCD) of 2 system clock cycles. Because tRCD is equal to the read CAS latency (SCAS assertion to data out), this value is also 2 system clock cycles. Notice that NOPs are executed until the last data is read. A PALL command is executed one cycle after the last data transfer. CLKOUT A[23:0] Row Column Column Column Column SRAS tRCD = 2 SCAS tEP DRAMW tCASL = 2 D[31:0] SDRAM_CS[0] or [1] BS[3:0] ACTV NOP READ READ READ READ NOP NOP PALL Figure 15-6. Burst Read SDRAM Access Figure 15-7 shows the burst write operation. In this example, DACR[CASL] = 01, which creates an SRAS-to-SCAS delay (tRCD) of 2 system clock cycles. Note that data is available upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read cycle with the same tRCD. The next bus cycle is initiated sooner, but cannot begin an SDRAM cycle until the precharge-to-ACTV delay completes. 15-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Synchronous DRAM Controller Module CLKOUT A[23:0] Row Column Column Column Column SRAS tRP SCAS tCASL = 2 tRWL DRAMW D[31:0] SDRAM_CS[0] or [1] BS[3:0] ACTV NOP WRITE WRITE WRITE WRITE NOP PALL Figure 15-7. Burst Write SDRAM Access Accesses in synchronous burst page mode always cause the following sequence: 1. ACTV command 2. NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no NOP commands). 3. Required number of READ or WRITE commands to service the transfer size with the given port size. 4. Some transfers need more NOP commands to assure the ACTV-to-precharge delay. 5. PALL command 6. Required number of idle clocks inserted to assure precharge-to-ACTV delay. 15.2.3.5 Auto-Refresh Operation The DRAM controller is equipped with a refresh counter and control. This logic is responsible for providing timing and control to refresh the SDRAM without user interaction. Once the refresh counter is set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh request flag is set and the counter begins counting down again. The DRAM controller completes any active burst operation and then performs a PALL operation. The DRAM controller then initiates a refresh cycle and clears the refresh request flag. This refresh cycle includes a delay from any precharge to the auto-refresh command, the auto-refresh command, and then a delay until any ACTV command is allowed. Any SDRAM access initiated during the auto-refresh cycle is delayed until the cycle is completed. Freescale Semiconductor 15-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Synchronous DRAM Controller Module Figure 15-8 shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh request becomes active. The request is delayed by the precharge to ACTV delay programmed into the active SDRAM bank by the CAS bits. The REF command is then generated and the delay required by DCR[RTIM] is inserted before the next ACTV command is generated. In this example, the next bus cycle is initiated, but does not generate an SDRAM access until TRC is finished. Because both chip selects are active during the REF command, it is passed to both blocks of external SDRAM. CLKOUT A[23:0] SRAS tRC = 6 tRCD = 2 SCAS DRAMW SDRAM_CS[0] or [1] REF PALL ACTV Figure 15-8. Auto-Refresh Operation 15.2.3.6 Self-Refresh Operation Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS]. When IS is set, the SELF command is sent to the SDRAM. When IS is cleared, the SELFX command is sent to the DRAM controller. Figure 15-9 shows the self-refresh operation. 15-16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Synchronous DRAM Controller Module CLKOUT SRAS SCAS tRCD = 2 tRC = 6 DRAMW SDRAM_CS[0] or [1] SCKE (DCR[COC] = 0) PALL SELF SELFX SelfRefresh Active First Possible ACTV Figure 15-9. Self-Refresh Operation 15.2.4 Initialization Sequence Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports this sequence with the following procedure: 1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any action is taken on the SDRAMs. This is normally around 100 µs. 2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable PALL or REF commands. 3. Issue a PALL command to the SDRAMs by setting DACR[IP] and accessing a SDRAM location. Wait the time (determined by tRP) before any other execution. 4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur. 5. Before issuing the MRS command, determine if the DMR mask bits need to be modified to allow the MRS to execute properly 6. Issue the MRS command by setting DACR[IMRS] and accessing a location in the SDRAM. Note that mode register settings are driven on the SDRAM address bus, so care must be taken to change DMR[BAM] if the mode register configuration does not fall in the address range determined by the address mask bits. After the mode register is set, DMR mask bits can be restored to their desired configuration. Freescale Semiconductor 15-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Synchronous DRAM Controller Module Synchronous DRAM Controller Module Mode Register Settings It is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency, through the SDRAM component’s mode register. CAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates at a CAS latency of 1, 2, or 3. Although the DRAM controller supports bursting operations, it does not use the bursting features of the SDRAMs. Because the processor can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a fixed burst length in the SDRAMs mode register becomes problematic. Therefore, the processor DRAM controller generates the burst cycles rather than the SDRAM device. Because the processor generates a new address and a READ or WRITE command for each transfer within the burst, the SDRAM mode register should be set either not to burst or to a burst length of one. This allows bursting to be controlled by the processor. The SDRAM mode register is written by setting the associated block’s DACR[IMRS]. First, the base address and mask registers must be set to the appropriate configuration to allow the mode register to be set. Note that improperly set DMR mask bits may prevent access to the mode register address. Thus, the user should determine the mapping of the mode register address to the processor address bits to find out if an access is blocked. If the DMR setting prohibits mode register access, the DMR should be reconfigured to enable the access and then set to its necessary configuration after the MRS command executes. The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the SDRAM address space generates the MRS command to that SDRAM. The address of the access should be selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed for the MRS command. The MRS access can be a read or write. The important thing is that the address output of that access needs the correct mode programming information on the correct address bits. Figure 15-10 shows the MRS command, which occurs in the first clock of the bus cycle. CLKOUT A[23:0] SRAS, SCAS DRAMW D[31:0] SD_CS[1] or [0] MRS Figure 15-10. Mode Register Set (MRS) Command 15.3 SDRAM Example This example interfaces a 512K x 32-bit x 4 bank SDRAM component to processor operating at 40 MHz. Table 15-25 lists design specifications for this example. 15-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.2.4.1 Synchronous DRAM Controller Module Parameter Speed grade (-8E) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 15-25. SDRAM Example Specifications Specification 40 MHz (25-ns period) 10 rows, 8 columns Two bank-select lines to access four internal banks ACTV-to-read/write delay (tRCD) Period between auto-refresh and ACTV command (tRC) ACTV command to precharge command (tRAS) 20 ns (min.) 70 ns 48 ns (min.) Precharge command to ACTV command (tRP) 20 ns (min.) Last data input to PALL command (tRWL) 1 bus clock (25 ns) Auto-refresh period for 4096 rows (tREF) 64 mS Freescale Semiconductor 15-19 Synchronous DRAM Controller Module SDRAM Interface Configuration To interface this component to the DRAM controller, use the connection table that corresponds to a 32-bit port size with 8 columns (Table 15-24). Two pins select one of four banks when the part is functional. Table 15-26 shows the proper hardware connections. Table 15-26. SDRAM Hardware Connections Processor Pins A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 SDRAM Pins A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1 15.3.2 A0 DCR Initialization At power-up, the DCR has the following configuration if synchronous operation and SDRAM address multiplexing are desired. Field 15 14 — — 13 12 11 NAM COC IS Setting 10 9 8 0 RTIM RC 0000_0000_0010_0110 (hex) 0026 Figure 15-11. Initialization Values for DCR This configuration results in a value of 0x0026 for DCR, as shown in Table 15-27. Table 15-27. DCR Initialization Values Bits Name Setting 15 — 0 Reserved. 14 — 0 Reserved. 13 NAM 0 Indicating SDRAM controller multiplexes address lines internally 12 COC 0 SCKE is used as clock enable instead of command bit because user is not multiplexing address lines externally and requires external command feed. 11 IS 0 At power-up, allowing power self-refresh state is not appropriate because registers are being set up. 10–9 RTIM 00 Because tRC value is 70 ns, indicating a 3-clock refresh-to-ACTV timing. 8–0 RC 0x26 15.3.3 Description Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every 15.625 µs for each row, or 625 bus clocks at 40 MHz. Because DCR[RC] is incremented by 1 and multiplied by 16, RC = (625 bus clocks/16) -1 = 38.06 = 0x38 DACR Initialization As shown in Figure 15-12, the SDRAM is programmed to access only the second 512-Kbyte block of each 1-Mbyte partition in the SDRAM (each 16 Mbytes). The starting address of the SDRAM is 0xFF88_0000. Continuous page mode feature is used. 15-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.3.1 Accessible Memory SDRAM Component Bank 0 Bank 1 512 Kbyte Bank 2 512 Kbyte 1 Mbyte Bank 3 512 Kbyte 1 Mbyte 1 Mbyte 512 Kbyte 512 Kbyte 1 Mbyte 512 Kbyte 512 Kbyte 512 Kbyte Figure 15-12. SDRAM Configuration The DACRs should be programmed as shown in Figure 15-13. 31 18 Field BA Setting 16 — 1111_1111_1000_10xx (hex) Field 17 F 15 14 RE — F 13 12 11 CASL — Setting 8 10 8 CBM 7 6 — IMRS 8 5 4 PS 3 IP 2 1 0 — 0000_x011_x000_0000 (hex) 0300 Figure 15-13. DACR Register Configuration This configuration results in a value of DACR0 = 0xFF88_0300, as described in Table 15-28. DACR1 initialization is not needed because there is only one block. Subsequently, DACR1[RE,IMRS,IP] should be cleared; everything else is a don’t care. Table 15-28. DACR Initialization Values Bits Name 31–18 BA 17–16 — 15 RE 14 — 13–12 CASL 11 — 10–8 CBM 7 — 6 IMRS 0 Indicates MRS command has not been initiated. 5–4 PS 00 32-bit port. Freescale Semiconductor Setting Description 1111_1111_ Base address. So DACR0[31–16] = 0xFF88, placing the starting 1000_10 address of the SDRAM accessible memory at 0xFF88_0000. Reserved. Don’t care. 0 Keeps auto-refresh disabled because registers are being set up at this time. Reserved. Don’t care. 00 Indicates a delay of data 1 cycle after SCAS is asserted Reserved. Don’t care. 011 Command bit is pin 20 and bank selects are 21 and up. Reserved. Don’t care. 15-21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Synchronous DRAM Controller Module Synchronous DRAM Controller Module 15.3.4 Bits Name Setting 3 IP 0 2–0 — Description Indicates precharge has not been initiated. Reserved. Don’t care. DMR Initialization Again, in this example only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank. In addition, the SDRAM component is mapped only to readable and writable supervisor and user data. The DMRs have the following configuration. 31 18 Field 17 BAM Setting 16 — 0000_0000_0111_01xx (hex) 0 074 15 9 Field — Setting 8 7 6 5 4 3 2 1 0 WP — C/I AM SC SD UC UD V xxxx_xxx0_x111_0101 (hex) 0075 Figure 15-14. DMR0 Register With this configuration, the DMR0 = 0x0074_0075, as described in Table 15-29. Table 15-29. DMR0 Initialization Values Bits Name 31–18 BAM 17–16 — Reserved. Don’t care. 15–9 — Reserved. Don’t care. 8 WP 7 — 6 C/I 1 Disable CPU space access. 5 AM 1 Disable alternate master access. 4 SC 1 Disable supervisor code accesses. 3 SD 0 Enable supervisor data accesses. 2 UC 1 Disable user code accesses. 1 UD 0 Enable user data accesses. 0 V 1 Enable accesses. 15-22 Setting Description With bits 17 and 16 as don’t cares, BAM = 0x0074, which leaves bank select bits and upper 512K select bits unmasked. Note that bits 22 and 21 are set because they are used as bank selects; bit 20 is set because it controls the 1-Mbyte boundary address. 0 Allow reads and writes Reserved. Don’t care. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 15-28. DACR Initialization Values (continued) Synchronous DRAM Controller Module Mode Register Initialization When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding processor address pins must be determined while being aware of masking requirements. Table 15-30 lists the desired initialization setting: Table 15-30. Mode Register Initialization Processor Pins SDRAM Pins Mode Register Initialization A20 A10 Reserved X A19 A9 WB 0 A18 A8 Opmode 0 A17 A7 Opmode 0 A9 A6 CASL 0 A10 A5 CASL 0 A11 A4 CASL 1 A12 A3 BT 0 A13 A2 BL 0 A14 A1 BL 0 A15 A0 BL 0 Next, this information is mapped to an address to determine the hexadecimal value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 Field Setting xxxx_xxxx_xxxx_000x (hex) 0000 15 14 13 12 11 10 9 8 7 6 Field V Setting 0000_100x_xxxx_xxxx (hex) 0800 Table 15-31. Mode Register Mapping to A[31:0] Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register bit is set, DMR0[19] must be set to enable masking. 15.3.6 Initialization Code The following assembly code initializes the SDRAM example. Freescale Semiconductor 15-23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 15.3.5 Synchronous DRAM Controller Module move.w move.w move.l move.l move.l move.l #0x0026, d0//Initialize DCR d0, DCR #0xFF880300, d0 //Initialize DACR0 d0, DACR0 #0x00740075, d0//Initialize DMR0 d0, DMR0 Precharge Sequence: move.l move.l move.l move.l #0xFF880308, d0//Set DACR0[IP] d0, DACR0 #0xBEADDEED, d0//Write and value to memory location to init. precharge d0, 0xFF880000 Refresh Sequence: move.l move.l #0xFF888300, d0//Enable refresh bit in DACR0 d0, DACR0 Mode Register Initialization Sequence: move.l move.l move.l move.l move.l move.l 15-24 #0x00600075, d0//Mask bit 19 of address d0, DMR0 #0xFF888340, d0//Enable DACR0[IMRS]; DACR0[RE] remains set d0, DACR0 #0x00000000, d0//Access SDRAM address to initialize mode register d0, 0xFF800800 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Power-Up Sequence: This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. NOTE The designation “n” is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels: DMA0, DMA1, DMA2 or DMA3. 16.1 Overview The DMA controller module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module, shown in Figure 16-1, provides four channels that allow byte, word, longword, or 16-byte burst data transfers. Each channel has a dedicated source address register (SARn), destination address register (DARn), byte count register (BCRn), control register (DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART, SDRAM controller, and GPIOs. Channel 0 Channel 1 Channel 2 Channel 3 Internal Bus External Requests SAR0 SAR1 SAR2 SAR3 DAR0 DAR1 DAR2 DAR3 BCR0 BCR1 BCR2 BCR3 DCR0 DCR1 DCR2 DCR3 DSR0 DSR1 DSR2 DSR3 Channel Requests Interrupts Channel Attributes Channel Enables System Bus Address MUX MUX Control System Bus Size Current Master Attributes Arbitration/ Control Data Path Read Data Bus Data Path Control Write Data Bus Bus Interface Registered Bus Signals Figure 16-1. DMA Signal Diagram Freescale Semiconductor 16-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 16 DMA Controller Module NOTE Throughout this chapter “external request” and DREQ are used to refer to a DMA request from one of the on-chip UARTS or DMA timers. For details on the connections associated with DMA request inputs, see Section 16.2, “DMA Request Control (DMAREQC).” 16.1.1 DMA Module Features The DMA controller module features are as follows: • Four independently programmable DMA controller channels • Auto-alignment feature for source or destination accesses • Dual-address transfers • Channel arbitration on transfer boundaries • Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer • Continuous-mode or cycle-steal transfers • Independent transfer widths for source and destination • Independent source and destination address registers 16.2 DMA Request Control (DMAREQC) The DMAREQC register provides a software-controlled connection matrix for DMA requests. It logically routes DMA requests from the DMA timers and UARTs to the four channels of the DMA controller. Writing to this register determines the exact routing of the DMA request to the four channels of the DMA modules. If DCRn[EEXT] is set and the channel is idle, the assertion of the appropriate DREQn activates channel n. 31 20 Field 19 — — Reset 0000_0000_0000_0000 R/W R/W 15 Field 12 DMAC3 11 16 8 7 DMAC2 4 3 DMAC1 Reset 0000_0000_0000_0000 R/W R/W 0 DMAC0 IPSBAR + 0x014 Figure 16-2. DMA Request Control Register (DMAREQC) Table 16-1. DMAREQC Field Description Bits 16-2 Name Description Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 DMA Controller Module DMA Controller Module 31–16 — 15–0 DMACn Reserved. Should be cleared. DMA Channel n. Each four bit field defines the logical connection between the DMA requestors and that DMA channel. There are seven possible requesters (4 DMA Timers and 3 UARTs). Any request can be routed to any of the DMA channels. Effectively, the DMAREQC provides a software-controlled routing matrix of the 7 DMA request signals to the 4 channels of the DMA module. DMAC3 controls DMA channel 3. DMAC2 controls DMA channel 2. DMAC1 controls DMA channel 1. DMAC0 controls DMA channel 0. 1000 UART0. 1001 UART1. 1010 UART2. 0100 DMA Timer 0. 0101 DMA Timer 1. 0110 DMA Timer 2. 0111 DMA Timer 3. All other values are reserved and will not generate a DMA request. Freescale Semiconductor 16-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 16-1. DMAREQC Field Description (continued) DMA Controller Module DMA Transfer Overview The DMA module can transfer data faster than the ColdFire core. The term “direct memory access” refers to a fast method of moving data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four channels at once. The processor generates DMA requests internally by setting DCR[START]; the UART modules and DMA timers can generate a DMA request by asserting internal DREQ signals. The processor can program bus bandwidth for each channel. The channels support cycle-steal and continuous transfer modes; see Section 16.5.1, “Transfer Requests (Cycle-Steal and Continuous Modes).” The DMA controller supports dual-address transfers. The DMA channels support up to 32 data bits. • Dual-address transfers—A dual-address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by asserting DREQ. Two types of transfer can occur: a read from a source device or a write to a destination device. See Figure 16-3 for more information. Control and Data Memory/ Peripheral DMA Control and Data Memory/ Peripheral Figure 16-3. Dual-Address Transfer Any operation involving the DMA module follows the same three steps: 1. Channel initialization—Channel registers are loaded with control information, address pointers, and a byte-transfer count. 2. Data transfer—The DMA accepts requests for operand transfers and provides addressing and bus control for the transfers. 3. Channel termination—Occurs after the operation is finished, either successfully or due to an error. The channel indicates the operation status in the channel’s DSR, described in Section 16.4.5, “DMA Status Registers (DSR0–DSR3).” 16.4 DMA Controller Module Programming Model This section describes each internal register and its bit assignment. Note that modifying DMA control registers during a DMA transfer can result in undefined operation. Table 16-2 shows the mapping of DMA controller registers. Note the differences for the byte count registers depending on the value of MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master Park Register (MPARK)” for further information. 16-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 16.3 DMA Controller Module DMA IPSBAR Channel Offset 0 Destination address register 0 (DAR0) [p. 16-6] 0x108 DMA control register 0 (DCR0) [p. 16-7] Byte count register 0 (BCR24BIT = 0) 1 Reserved 0x10C Reserved Byte count register 0 (BCR24BIT = 1) 1 (BCR0) [p. 16-7] 0x110 DMA status register 0 (DSR0) [p. 16-10] Reserved 0x140 Source address register 1 (SAR1) [p. 16-5] 0x144 Destination address register 1 (DAR1) [p. 16-6] 0x148 DMA control register 1 (DCR1) [p. 16-7] Byte count register 1 (BCR24BIT = 0) 1 Reserved 0x14C Reserved Byte count register 1 (BCR24BIT = 1) 1 (BCR1) [p. 16-7] 0x150 DMA status register 1 (DSR1) [p. 16-10] Reserved 0x180 Source address register 2 (SAR2) [p. 16-5] 0x184 Destination address register 2 (DAR2) [p. 16-6] 0x188 DMA control register 2 (DCR2) [p. 16-7] Byte count register 2 (BCR24BIT = 0) 1 Reserved 0x18C Reserved Byte count register 2 (BCR24BIT = 1) 1 (BCR2) [p. 16-7] 0x190 DMA status register 2 (DSR2) [p. 16-10] Reserved 0x1C0 Source address register 3 (SAR3) [p. 16-5] 0x1C4 Destination address register 3 (DAR3) [p. 16-6] 0x1C8 DMA control register 3 (DCR3) [p. 16-7] 0x1CC 1 [7:0] 0x104 0x18C 3 [15:8] Source address register 0 (SAR0) [p. 16-5] 0x14C 2 [23:16] 0x100 0x10C 1 [31:24] Byte count register 3 (BCR24BIT = 0)1 Reserved 0x1CC Reserved Byte count register 3 (BCR24BIT = 1)1 (BCR3) [p. 16-7] 0x1D0 DMA status register 3 (DSR3) [p. 16-10] Reserved The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was later reimplemented as a right-justified 24-bit BCR. The operation of the DMA and the interpretation of the BCR is controlled by the MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master Park Register (MPARK)" for more details. 16.4.1 Source Address Registers (SAR0–SAR3) SARn, shown in Figure 16-4, contains the address from which the DMA controller requests data. Freescale Semiconductor 16-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 16-2. Memory Map for DMA Controller Module Registers 31 0 Field SAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x100, 0x140, 0x180, 0x1C0 Figure 16-4. Source Address Registers (SARn) NOTE The backdoor enable bit must be set in both the core and SCM in order to enable backdoor accesses from the DMA to SRAM. See Section 8.4.2, “Memory Base Address Register (RAMBAR)” for more details. NOTE Flash accesses (reads/writes) by a bus master other than the core (DMA controller or Fast Ethernet Controller), or writes to Flash by the core during programming, must use the backdoor Flash address of IPSBAR plus an offset of 0x0400_0000. For example, for a DMA transfer from the first Flash location when IPSBAR is still at its default location of 0x4000_0000, the source register would be loaded with 0x4400_0000. Backdoor Flash read accesses can be made with the bus master, but it takes two cycles longer than a direct read of the Flash when using the FLASHBAR address. 16.4.2 Destination Address Registers (DAR0–DAR3) DARn, shown in Figure 16-5, holds the address to which the DMA controller sends data. 31 0 Field DAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W Address R/W IPSBAR + 0x104, 0x144, 0x184, 0x1C4 Figure 16-5. Destination Address Registers (DARn) NOTE The DMA does not maintain coherency with the cache. Therefore, DMAs should not transfer data to cacheable memory unless software is used to maintain the cache coherency. NOTE The DMA should not be used to write data to the UART transmit FIFO in cycle steal mode. When the UART interrupt is used as a DMA request it does not negate fast enough to get a single transfer. The UART transmit FIFO only has one entry so the data from the second byte would be lost. 16-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 DMA Controller Module DMA Controller Module Byte Count Registers (BCR0–BCR3) BCRn, shown in Figure 16-6 and Figure 16-7, hold the number of bytes yet to be transferred for a given block. The offset within the memory map is based on the value of MPARK[BCR24BIT]. BCRn decrements on the successful completion of the address transfer of a write transfer. BCRn decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively. Figure 16-6 shows BCRn for BCR24BIT = 1. 31 24 23 0 Field — BCR Reset — 0000_0000_0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC Figure 16-6. Byte Count Registers (BCRn)—BCR24BIT = 1 Figure 16-7 shows BCRn for BCR24BIT = 0. 15 0 Field BCR Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC Figure 16-7. Byte Count Registers (BCRn)—BCR24BIT = 0 DSRn[DONE], shown in Figure 16-9, is set when the block transfer is complete. When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs. See Section 16.4.5, “DMA Status Registers (DSR0–DSR3).” 16.4.4 DMA Control Registers (DCR0–DCR3) DCRn, shown in Figure 16-8, is used for configuring the DMA controller module. Note that DCRn[AT] is available only if MPARK[BCR24BIT] is set. See Section 8.5.3, “Bus Master Park Register (MPARK)” for more information. Freescale Semiconductor 16-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 16.4.3 DMA Controller Module 30 Field INT EEXT 29 28 CS AA Reset 27 25 BWC 23 22 — — SINC 21 20 SSIZE 19 DINC 18 17 DSIZE 16 START 0000_0000_0000_0000 R/W R/W 15 Field AT Reset 24 14 0 1 — N/A 0 R/W R/W Address IPSBAR + 0x108, 0x148, 0x188, 0x1C8 Figure 16-8. DMA Control Registers (DCRn) 1 Available only if BCR24BIT = 1, otherwise reserved. Table 16-3 describes DCRn fields. Table 16-3. DCRn Field Descriptions 16-8 Bits Name Description 31 INT 30 EEXT Enable external request. Care should be taken because a collision can occur between the START bit and DREQ when EEXT = 1. 0 External request is ignored. 1 Enables external request to initiate transfer. The internal request (initiated by setting the START bit) is always enabled. 29 CS Cycle steal. 0 DMA continuously makes read/write transfers until the BCR decrements to 0. 1 Forces a single read/write transfer per request. The request may be internal by setting the START bit, or external by asserting DREQ. 28 AA Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size. See Section 16.5.4.1, “Auto-Alignment.” 0 Auto-align disabled 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition. 0 No interrupt is generated. 1 Internal interrupt signal is enabled. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 31 DMA Controller Module Bits Name Description 27–25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a multiple of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is 001 (512 bytes or value of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of 0x0E00, 0x0C00, 0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200. If BCR24BIT is 0, BWC is 110, and BCR is 33000, the bus is released after 232 bytes because the BCR is at 32768, a multiple of 16384. Encoding 000 BCR24BIT = 0 BCR24BIT = 1 DMA has priority and does not negate its request until transfer completes. 001 512 16384 010 1024 32768 011 2048 65536 100 4096 131072 101 8192 262144 110 16384 524288 111 32768 1048576 24–23 — 22 SINC Source increment. Controls whether a source address increments after each successful transfer. 0 No change to SAR after a successful transfer. 1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size. 21–20 SSIZE Source size. Determines the data size of the source bus cycle for the DMA control module. 00 Longword 01 Byte 10 Word 11 Line (16-byte burst) 19 DINC Destination increment. Controls whether a destination address increments after each successful transfer. 0 No change to the DAR after a successful transfer. 1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer. 18–17 16 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 16-3. DCRn Field Descriptions (continued) Reserved, should be cleared. DSIZE Destination size. Determines the data size of the destination bus cycle for the DMA controller. 00 Longword 01 Byte 10 Word 11 Line (16-byte burst) START Start transfer. 0 DMA inactive 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0. Freescale Semiconductor 16-9 DMA Controller Module Bits Name Description 15 AT AT is available only if MPARK[BCR24BIT] = 1. DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer or only the final transfer. 0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the result of an external request. 1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information is displayed for both the read and write cycles. 14–0 — Reserved, should be cleared. 16.4.5 DMA Status Registers (DSR0–DSR3) In response to an event, the DMA controller writes to the appropriate DSRn bit, Figure 16-9. Only a write to DSRn[DONE] results in action. Field 7 6 5 4 3 2 1 0 — CE BES BED — REQ BSY DONE Reset 0000_0000 R/W R/W Address IPSBAR + 0x110, 0x150, 0x190, 0x1D0 Figure 16-9. DMA Status Registers (DSRn) Table 16-4 describes DSRn fields. Table 16-4. DSRn Field Descriptions 16-10 Bits Name Description 7 — Reserved, should be cleared. 6 CE Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE]. 0 No configuration error exists. 1 A configuration error has occurred. 5 BES Bus error on source 0 No bus error occurred. 1 The DMA channel terminated with a bus error during the read portion of a transfer. 4 BED Bus error on destination 0 No bus error occurred. 1 The DMA channel terminated with a bus error during the write portion of a transfer. 3 — 2 REQ Reserved, should be cleared. Request 0 No request is pending or the channel is currently active. Cleared when the channel is selected. 1 The DMA channel has a transfer remaining and the channel is not selected. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 16-3. DCRn Field Descriptions (continued) DMA Controller Module Bits Name 1 BSY 0 DONE 16.5 Description Busy 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. 1 BSY is set the first time the channel is enabled after a transfer is initiated. Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE before reprogramming the DMA. 0 Writing or reading a 0 has no effect. 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt handler to clear the DMA interrupt and error bits. DMA Controller Module Functional Description In the following discussion, the term “DMA request” implies that DCRn[START] or DCRn[EEXT] is set, followed by assertion of DREQn. The START bit is cleared when the channel begins an internal access. Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE,DSIZE] are consistent with the source and destination addresses. If they are not consistent, the configuration error bit, DSRn[CE], is set. If misalignment is detected, no transfer occurs, DSRn[CE] is set, and, depending on the DCR configuration, an interrupt event is issued. Note that if the auto-align bit, DCRn[AA], is set, error checking is performed on the appropriate registers. A read/write transfer reads bytes from the source address and writes them to the destination address. The number of bytes is the larger of the sizes specified by DCRn[SSIZE] and DCRn[DSIZE]. See Section 16.4.4, “DMA Control Registers (DCR0–DCR3).” Source and destination address registers (SARn and DARn) can be programmed in the DCRn to increment at the completion of a successful transfer. 16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) The DMA channel supports internal and external requests. A request is issued by setting DCRn[START] or by asserting DREQn. Setting DCRn[EEXT] enables recognition of external DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for either internal or external requests. • Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination occurs for each request. If DCRn[EEXT] is set, a request can be either internal or external. An internal request is selected by setting DCRn[START]. An external request is initiated by asserting DREQn while DCRn[EEXT] is set. Note that multiple transfers will occur if DREQn is continuously asserted. • Continuous mode (DCRn[CS] = 0)—After an internal or external request, the DMA continuously transfers data until BCRn reaches zero or a multiple of DCRn[BWC] or until DSRn[DONE] is set. If BCRn is a multiple of BWC, the DMA request signal is negated until the bus cycle terminates to allow the internal arbiter to switch masters. DCRn[BWC] = 000 specifies the maximum transfer rate; other values specify a transfer rate limit. The DMA performs the specified number of transfers, then relinquishes bus control. The DMA negates its internal bus request on the last transfer before BCRn reaches a multiple of the boundary specified in BWC. On completion, the DMA reasserts its bus request to regain mastership at the earliest opportunity. The DMA loses bus control for a minimum of one bus cycle. Freescale Semiconductor 16-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 16-4. DSRn Field Descriptions (continued) DMA Controller Module Data Transfer Modes Each channel supports dual-address transfers, described in the next section. 16.5.2.1 Dual-Address Transfers Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence during a DMA request. If no error condition exists, DSRn[REQ] is set. • Dual-address read—The DMA controller drives the SARn value onto the internal address bus. If DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles complete (multiple reads if the destination size is larger than the source), the DMA initiates the write portion of the transfer. If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop. • Dual-address write—The DMA controller drives the DARn value onto the address bus. If DCRn[DINC] is set, DARn increments by the appropriate number of bytes at the completion of a successful write cycle. BCRn decrements by the appropriate number of bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than zero, another read/write transfer is initiated. If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop. 16.5.3 Channel Initialization and Startup Before a block transfer starts, channel registers must be initialized with information describing configuration, request-generation method, and the data block. 16.5.3.1 Channel Prioritization The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel 3 having the lowest) or in an order determined by DCRn[BWC]. If the BWC encoding for a DMA channel is 000, that channel has priority only over the channel immediately preceding it. For example, if DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming DCR2[BWC] ≠ 000) but not over DMA channel 1. If DCR0[BWC] = DCR1[BWC] = 000, DMA0 still has priority over DMA1. In this case, DCR1[BWC] = 000 does not affect prioritization. Simultaneous external requests are prioritized either in ascending order or in an order determined by each channel’s DCRn[BWC] bits. 16.5.3.2 Programming the DMA Controller Module Note the following general guidelines for programming the DMA: • No mechanism exists within the DMA module itself to prevent writes to control registers during DMA accesses. • If the DCRn[BWC] value of sequential channels are equal, the channels are prioritized in ascending order. The SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to either a 16-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 16.5.2 peripheral device or memory, the source address is the starting address of the data block. This can be any aligned byte address. The DARn should contain the destination (write) address. If the transfer is from a peripheral device to memory, or from memory to memory, the DARn is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, DARn is loaded with the address of the peripheral data register. This address can be any aligned byte address. SARn and DARn change after each cycle depending on DCRn[SSIZE,DSIZE, SINC,DINC] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer. BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup. As soon as the channel has been initialized, it is started by writing a one to DCRn[START] or asserting DREQn, depending on the status of DCRn[EEXT]. Programming the channel for internal requests causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, DREQn must be asserted before the channel requests the bus. Changes to DCRn are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel. 16.5.4 Data Transfer This section describes auto-alignment and bandwidth control for DMA transfers. 16.5.4.1 Auto-Alignment Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCRn[AA] must be set. The source is auto-aligned if DCRn[SSIZE] indicates a transfer size larger than DCRn[DSIZE]. Source alignment takes precedence over the destination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. The address register chosen for alignment increments regardless of the increment value. Configuration error checking is performed on registers not chosen for alignment. If BCRn is greater than 16, the address determines transfer size. Bytes, words, or longwords are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size. If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. For example, AA = 1, SARn = 0x0001, BCRn = 0x00F0, SSIZE = 00 (longword), and DSIZE = 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers. The access sequence is as follows: 1. Read byte from 0x0001—write 1 byte, increment SARn. 2. Read word from 0x0002—write 2 bytes, increment SARn. 3. Read longword from 0x0004—write 4 bytes, increment SARn. 4. Repeat longwords until SARn = 0x00F0. 5. Read byte from 0x00F0—write byte, increment SARn. Freescale Semiconductor 16-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 DMA Controller Module If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. 16.5.4.2 Bandwidth Control Bandwidth control makes it possible to force the DMA off the bus to allow access to another device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending, the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, DCRn[AA] = 1, the BCRn may skip over the programmed boundary, in which case, the DMA bus request is not negated. If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus. See Section 8.5.3, “Bus Master Park Register (MPARK).” 16.5.5 Termination An unsuccessful transfer can terminate for one of the following reasons: • Error conditions—When the processor encounters a read or write cycle that terminates with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write before the transfer is halted. If the error occurred in a write cycle, data in the internal holding register is lost. • Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal. The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits. • 16-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 DMA Controller Module 17.1 Introduction This chapter provides a feature-set overview, a functional block diagram, and transceiver connection information for the 10 and 100 Mbps MII (media independent interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included. NOTE The MCF5214 and MCF5216 do NOT contain an FEC module. 17.1.1 Overview The Ethernet media access controller (MAC) supports 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface. NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 26, “General Purpose I/O Module”) prior to configuring the FEC. 17.1.2 Block Diagram Figure 17-1 shows the block diagram of the FEC. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. Freescale Semiconductor 17-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 17 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) Crossbar Switch Master Bus Internal Bus Interface MIB Counter RAM Bus Controller Control/Status Registers FIFO RAM FEC DMA FIFO Controller RAM Interface Descriptor Controller (RISC + microcode) FEC Bus MII MDO MDEN Transmit Receive MDI I/O PAD FEC_MDIO FEC_MDC FEC_TXEN FEC_TXD[3:0] FEC_TXER FEC_TXCLK FEC_CRS FEC_COL FEC_RXCLK FEC_RXDV FEC_RXD[3:0] FEC_RXER MII/7-Wire data option Figure 17-1. FEC Block Diagram The descriptor controller is a RISC-based controller providing these functions in the FEC: • Initialization (those internal registers not initialized by you or hardware) • High level control of the DMA channels (initiating DMA transfers) • Interpreting buffer descriptors • Address recognition for receive frames • Random number generation for transmit collision backoff timer NOTE DMA references in this section refer to the FEC’s DMA engine. This DMA engine transfers FEC data only and is not related to the eDMA controller described in Chapter 16, “DMA Controller Module,” nor to the DMA timers described in Chapter 21, “DMA Timers (DTIM0–DTIM3).” The RAM is the focal point of all data flow in the Fast Ethernet controller and divides into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block, and receive data flows from the receive block into the receive FIFO. 17-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Internal Bus You control the FEC by writing into control registers located in each block. The CSR (control and status registers) block provides global control (Ethernet reset and enable) and interrupt managing registers. The MII block provides a serial channel for control/status communication with the external physical layer device (transceiver). This serial channel consists of the FEC_MDC (management data clock) and FEC_MDIO (management data input/output) lines of the MII interface. The FEC DMA block (not to be confused with the device’s eDMA controller) provides multiple channels allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run independently. The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from microcode). The message information block (MIB) maintains counters for a variety of network events and statistics. It is not necessary for operation of the FEC, but provides valuable counters for network management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3 counters. See Section 17.4.1, “MIB Block Counters Memory Map,” for more information. 17.1.3 Features The FEC incorporates the following features: • Support for three different Ethernet physical interfaces: — 100-Mbps IEEE 802.3 MII — 10-Mbps IEEE 802.3 MII — 10-Mbps 7-wire interface (industry standard) • IEEE 802.3 full duplex flow control • Programmable max frame length supports IEEE 802.1 VLAN tags and priority • Support for full-duplex operation (200 Mbps throughput) with a minimum internal bus clock rate of 50 MHz • Support for half-duplex operation (100 Mbps throughput) with a minimum internal bus clock rate of 50 MHz • Retransmission from transmit FIFO following a collision (no processor bus utilization) • Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization) • Address recognition — Frames with broadcast address may be always accepted or always rejected — Exact match for single 48-bit individual (unicast) address — Hash (64-bit hash) check of individual (unicast) addresses — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode Freescale Semiconductor 17-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) Modes of Operation The primary operational modes are described in this section. 17.2.1 Full and Half Duplex Operation Full duplex mode is for use on point-to-point links between switches or end node to switch. Half duplex mode works in connections between an end node and a repeater or between repeaters. TCR[FDEN] controls duplex mode selection. When configured for full duplex mode, flow control may be enabled. Refer to the TCR[RFC_PAUSE,TFC_PAUSE] bits, the RCR[FCE] bit, and Section 17.5.11, “Full Duplex Flow Control,” for more details. 17.2.2 Interface Options The following interface options are supported. A detailed discussion of the interface configurations is provided in Section 17.5.6, “Network Interface Options.” 17.2.2.1 10 Mbps and 100 Mbps MII Interface The IEEE 802.3 standard defines the media independent interface (MII) for 10/100 Mbps operation. The MAC-PHY interface may be configured to operate in MII mode by setting RCR[MII_MODE]. FEC_TXCLK and FEC_RXCLK pins driven by the external transceiver determine the operation speed. The transceiver auto-negotiates the speed or software controls it via the serial management interface (FEC_MDC/FEC_MDIO pins) to the transceiver. Refer to the MMFR and MSCR register descriptions, as well as the section on the MII, for a description of how to read and write registers in the transceiver via this interface. 17.2.2.2 10 Mpbs 7-Wire Interface Operation The FEC supports 7-wire interface used by many 10 Mbps Ethernet transceivers. The RCR[MII_MODE] bit controls this functionality. If this bit is cleared, MII mode is disabled and the 10 Mbps 7-wire mode is enabled. 17.2.3 Address Recognition Options The address options supported are promiscuous, broadcast reject, individual address (hash or exact match), and multicast hash match. Address recognition options are discussed in detail in Section 17.5.9, “Ethernet Address Recognition.” 17.2.4 Internal Loopback Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in Section 17.5.14, “MII Internal and External Loopback.” 17-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.2 Fast Ethernet Controller (FEC) External Signal Description Table 17-1 describes the various FEC signals, as well as indicating which signals work in available modes. Signal Name MII 7-wire Table 17-1. FEC Signal Descriptions FEC_COL X X FEC_CRS X — When asserted, indicates that transmit or receive medium is not idle. FEC_MDC X — Output clock which provides a timing reference to the PHY for data transfers on the FEC_MDIO signal. FEC_MDIO X — Transfers control information between the external PHY and the media-access controller. Data is synchronous to FEC_MDC. This signal is an input after reset. When the FEC is operated in 10Mbps 7-wire interface mode, this signal should be connected to VSS. FEC_RXCLK X X Provides a timing reference for FEC_RXDV, FEC_RXD[3:0], and FEC_RXER. FEC_RXDV X X Asserting the FEC_RXDV input indicates that the PHY has valid nibbles present on the MII. FEC_RXDV should remain asserted from the first recovered nibble of the frame through to the last nibble. Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF. FEC_RXD0 X X This pin contains the Ethernet input data transferred from the PHY to the media-access controller when FEC_RXDV is asserted. FEC_RXD1 X — This pin contains the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted. FEC_RXD[3:2] X — These pins contain the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted. FEC_RXER X — When asserted with FEC_RXDV, indicates that the PHY has detected an error in the current frame. When FEC_RXDV is not asserted FEC_RXER has no effect. FEC_TXCLK X X Input clock which provides a timing reference for FEC_TXEN, FEC_TXD[3:0] and FEC_TXER. FEC_TXD0 X X The serial output Ethernet data and is only valid during the assertion of FEC_TXEN. FEC_TXD1 X — This pin contains the serial output Ethernet data and is valid only during assertion of FEC_TXEN. FEC_TXD[3:2] X — These pins contain the serial output Ethernet data and are valid only during assertion of FEC_TXEN. FEC_TXEN X X FEC_TXER X — When asserted for one or more clock cycles while FEC_TXEN is also asserted, the PHY sends one or more illegal symbols. FEC_TXER has no effect at 10 Mbps or when FEC_TXEN is negated. 17.4 Description Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first FEC_TXCLK following the final nibble of the frame. Memory Map/Register Definition The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The CSRs control operation modes and extract global status information. The descriptors pass data buffers and related buffer information between the hardware and software. Each FEC implementation requires a 1-Kbyte memory map space, which is divided into two sections of 512 bytes each for: Freescale Semiconductor 17-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.3 • • Control/status registers Event/statistic counters held in the MIB block Table 17-2 defines the top level memory map. Table 17-2. Module Memory Map Address Function IPSBAR + 0x1000 – 11FF Control/Status Registers IPSBAR + 0x1200 – 12FF MIB Block Counters Table 17-3 shows the FEC register memory map. Table 17-3. FEC Register Memory Map IPSBAR Offset 17-6 Register Width Access (bits) Reset Value Section/Page 0x1004 Interrupt Event Register (EIR) 32 R/W 0x0000_0000 17.4.2/17-9 0x1008 Interrupt Mask Register (EIMR) 32 R/W 0x0000_0000 17.4.3/17-10 0x1010 Receive Descriptor Active Register (RDAR) 32 R/W 0x0000_0000 17.4.4/17-11 0x1014 Transmit Descriptor Active Register (TDAR) 32 R/W 0x0000_0000 17.4.5/17-12 0x1024 Ethernet Control Register (ECR) 32 R/W 0xF000_0000 17.4.6/17-12 0x1040 MII Management Frame Register (MMFR) 32 R/W Undefined 17.4.7/17-13 0x1044 MII Speed Control Register (MSCR) 32 R/W 0x0000_0000 17.4.8/17-15 0x1064 MIB Control/Status Register (MIBC) 32 R/W 0x0000_0000 17.4.9/17-16 0x1084 Receive Control Register (RCR) 32 R/W 0x05EE_0001 17.4.10/17-16 0x10C4 Transmit Control Register (TCR) 32 R/W 0x0000_0000 17.4.11/17-17 0x10E4 Physical Address Low Register (PALR) 32 R/W Undefined 17.4.12/17-18 0x10E8 Physical Address High Register (PAUR) 32 R/W See Section 17.4.13/17-19 0x10EC Opcode/Pause Duration (OPD) 32 R/W See Section 17.4.14/17-19 0x1118 Descriptor Individual Upper Address Register (IAUR) 32 R/W Undefined 17.4.15/17-20 0x111C Descriptor Individual Lower Address Register (IALR) 32 R/W Undefined 17.4.16/17-20 0x1120 Descriptor Group Upper Address Register (GAUR) 32 R/W Undefined 17.4.17/17-21 0x1124 Descriptor Group Lower Address Register (GALR) 32 R/W Undefined 17.4.18/17-21 0x1144 Transmit FIFO Watermark (TFWR) 32 R/W 0x0000_0000 17.4.19/17-22 0x114C FIFO Receive Bound Register (FRBR) 32 R 0x0000_0600 17.4.20/17-22 0x1150 FIFO Receive FIFO Start Register (FRSR) 32 R 0x0000_0500 17.4.21/17-23 0x1180 Pointer to Receive Descriptor Ring (ERDSR) 32 R/W Undefined 17.4.22/17-23 0x1184 Pointer to Transmit Descriptor Ring (ETDSR) 32 R/W Undefined 17.4.23/17-24 0x1188 Maximum Receive Buffer Size (EMRBR) 32 R/W Undefined 17.4.24/17-24 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) MIB Block Counters Memory Map The MIB counters memory map (Table 17-4) defines the locations in the MIB RAM space where hardware-maintained counters reside. The counters are divided into two groups: • RMON counters include the Ethernet statistics counters defined in RFC 1757 • A counter is included to count truncated frames since only frame lengths up to 2047 bytes are supported The transmit and receive RMON counters are independent, which ensures accurate network statistics when operating in full duplex mode. The included IEEE counters support the mandatory and recommended counter packages defined in Section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The FEC supports IEEE Basic Package objects, but these do not require counters in the MIB block. In addition, some of the recommended package objects supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are also included. Table 17-4. MIB Counters Memory Map IPSBAR Offset Register 0x1200 Count of frames not counted correctly (RMON_T_DROP) 0x1204 RMON Tx packet count (RMON_T_PACKETS) 0x1208 RMON Tx broadcast packets (RMON_T_BC_PKT) 0x120C RMON Tx multicast packets (RMON_T_MC_PKT) 0x1210 RMON Tx packets with CRC/align error (RMON_T_CRC_ALIGN) 0x1214 RMON Tx packets < 64 bytes, good CRC (RMON_T_UNDERSIZE) 0x1218 RMON Tx packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE) 0x121C RMON Tx packets < 64 bytes, bad CRC (RMON_T_FRAG) 0x1220 RMON Tx packets > MAX_FL bytes, bad CRC (RMON_T_JAB) 0x1224 RMON Tx collision count (RMON_T_COL) 0x1228 RMON Tx 64 byte packets (RMON_T_P64) 0x122C RMON Tx 65 to 127 byte packets (RMON_T_P65TO127) 0x1230 RMON Tx 128 to 255 byte packets (RMON_T_P128TO255) 0x1234 RMON Tx 256 to 511 byte packets (RMON_T_P256TO511) 0x1238 RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023) 0x123C RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047) 0x1240 RMON Tx packets with > 2048 bytes (RMON_T_P_GTE2048) 0x1244 RMON Tx Octets (RMON_T_OCTETS) 0x1248 Count of transmitted frames not counted correctly (IEEE_T_DROP) 0x124C Frames transmitted OK (IEEE_T_FRAME_OK) 0x1250 Frames transmitted with single collision (IEEE_T_1COL) Freescale Semiconductor 17-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.4.1 Fast Ethernet Controller (FEC) IPSBAR Offset 17-8 Register 0x1254 Frames transmitted with multiple collisions (IEEE_T_MCOL) 0x1258 Frames transmitted after deferral delay (IEEE_T_DEF) 0x125C Frames transmitted with late collision (IEEE_T_LCOL) 0x1260 Frames transmitted with excessive collisions (IEEE_T_EXCOL) 0x1264 Frames transmitted with Tx FIFO underrun (IEEE_T_MACERR) 0x1268 Frames transmitted with carrier sense error (IEEE_T_CSERR) 0x126C Frames transmitted with SQE error (IEEE_T_SQE) 0x1270 Flow control pause frames transmitted (IEEE_T_FDXFC) 0x1274 Octet count for frames transmitted without error (IEEE_T_OCTETS_OK) 0x1280 Count of received frames not counted correctly (RMON_R_DROP) 0x1284 RMON Rx packet count (RMON_R_PACKETS) 0x1288 RMON Rx broadcast packets (RMON_R_BC_PKT) 0x128C RMON Rx multicast packets (RMON_R_MC_PKT) 0x1290 RMON Rx packets with CRC/Align error (RMON_R_CRC_ALIGN) 0x1294 RMON Rx packets < 64 bytes, good CRC (RMON_R_UNDERSIZE) 0x1298 RMON Rx packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE) 0x129C RMON Rx packets < 64 bytes, bad CRC (RMON_R_FRAG) 0x12A0 RMON Rx packets > MAX_FL bytes, bad CRC (RMON_R_JAB) 0x12A4 Reserved (RMON_R_RESVD_0) 0x12A8 RMON Rx 64 byte packets (RMON_R_P64) 0x12AC RMON Rx 65 to 127 byte packets (RMON_R_P65TO127) 0x12B0 RMON Rx 128 to 255 byte packets (RMON_R_P128TO255) 0x12B4 RMON Rx 256 to 511 byte packets (RMON_R_P256TO511) 0x12B8 RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023) 0x12BC RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047) 0x12C0 RMON Rx packets with > 2048 bytes (RMON_R_P_GTE2048) 0x12C4 RMON Rx octets (RMON_R_OCTETS) 0x12C8 Count of received frames not counted correctly (IEEE_R_DROP) 0x12CC Frames received OK (IEEE_R_FRAME_OK) 0x12D0 Frames received with CRC error (IEEE_R_CRC) 0x12D4 Frames received with alignment error (IEEE_R_ALIGN) 0x12D8 Receive FIFO overflow count (IEEE_R_MACERR) Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-4. MIB Counters Memory Map (continued) Fast Ethernet Controller (FEC) IPSBAR Offset 17.4.2 Register 0x12DC Flow control pause frames received (IEEE_R_FDXFC) 0x12E0 Octet count for frames received without error (IEEE_R_OCTETS_OK) Ethernet Interrupt Event Register (EIR) When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing 0 has no effect. This register is cleared upon hardware reset. These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR, BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN. Some of the error interrupts are independently counted in the MIB block counters: • HBERR - IEEE_T_SQE • BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC) • BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC) • LATE_COL - IEEE_T_LCOL • COL_RETRY_LIM - IEEE_T_EXCOL • XFIFO_UN - IEEE_T_MACERR Software may choose to mask off these interrupts because these errors are visible to network management via the MIB counters. IPSBAR 0x1004 Offset: 31 R R 30 29 28 HB BABR BABT GRA ERR W w1c Reset Access: User read/write 27 26 25 24 23 22 21 20 19 18 17 16 LC RL UN 0 0 0 0 0 0 TXF TXB RXF RXB MII EB ERR w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 17-2. Ethernet Interrupt Event Register (EIR) Freescale Semiconductor 17-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-4. MIB Counters Memory Map (continued) Fast Ethernet Controller (FEC) Field Description 31 Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window HBERR following a transmission. 30 BABR Babbling receive error. Indicates a frame was received with length in excess of RCR[MAX_FL] bytes. 29 BABT Babbling transmit error. Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition is caused by a frame that is too long is placed into the transmit data buffer(s). Truncation does not occur. 28 GRA Graceful stop complete. Indicates the graceful stop is complete. During graceful stop the transmitter is placed into a pause state after completion of the frame currently being transmitted. This bit is set by one of three conditions: 1) A graceful stop initiated by the setting of the TCR[GTS] bit is now complete. 2) A graceful stop initiated by the setting of the TCR[TFC_PAUSE] bit is now complete. 3) A graceful stop initiated by the reception of a valid full duplex flow control pause frame is now complete. Refer to Section 17.5.11, “Full Duplex Flow Control.” 27 TXF Transmit frame interrupt. Indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated. 26 TXB Transmit buffer interrupt. Indicates a transmit buffer descriptor has been updated. 25 RXF Receive frame interrupt. Indicates a frame has been received and the last corresponding buffer descriptor has been updated. 24 RXB Receive buffer interrupt. Indicates a receive buffer descriptor not the last in the frame has been updated. 23 MII MII interrupt. Indicates the MII has completed the data transfer requested. 22 EBERR Ethernet bus error. Indicates a system bus error occurred when a DMA transaction is underway. When the EBERR bit is set, ECR[ETHER_EN] is cleared, halting frame processing by the FEC. When this occurs, software needs to ensure that the FIFO controller and DMA also soft reset. 21 LC Late collision. Indicates a collision occurred beyond the collision window (slot time) in half duplex mode. The frame truncates with a bad CRC and the remainder of the frame is discarded. 20 RL Collision retry limit. Indicates a collision occurred on each of 16 successive attempts to transmit the frame. The frame is discarded without being transmitted and transmission of the next frame commences. This error can only occur in half duplex mode. 19 UN Transmit FIFO underrun. Indicates the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded. 18–0 17.4.3 Reserved, must be cleared. Interrupt Mask Register (EIMR) The EIMR register controls which interrupt events are allowed to generate actual interrupts. All implemented bits in this CSR are read/write. A hardware reset clears this register. If the corresponding bits in the EIR and EIMR registers are set, an interrupt is generated. The interrupt signal remains asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit. 17-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-5. EIR Field Descriptions Fast Ethernet Controller (FEC) 31 Access: User read/write 30 29 28 R 27 HB BABR BABT GRA ERR W Reset R 26 25 24 23 22 LC RL UN 0 0 0 TXF TXB RXF RXB MII EB ERR 0 0 0 0 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 17-3. Ethernet Interrupt Mask Register (EIMR) Table 17-6. EIMR Field Descriptions Field Description 31–19 See Figure 17-3 and Table 17-5 Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set. 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is not masked. 18–0 Reserved, must be cleared. 17.4.4 Receive Descriptor Active Register (RDAR) RDAR is a command register, written by the user, indicating the receive descriptor ring is updated (the driver produced empty receive buffers with the empty bit set). When the register is written, the RDAR bit is set. This is independent of the data actually written by the user. When set, the FEC polls the receive descriptor ring and processes receive frames (provided ECR[ETHER_EN] is also set). After the FEC polls a receive descriptor whose empty bit is not set, FEC clears the RDAR bit and ceases receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors are placed into the receive descriptor ring. The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared. IPSBAR 0x1010 Offset: Access: User read/write 31 30 29 28 27 26 25 R 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 24 RDAR 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-4. Receive Descriptor Active Register (RDAR) Freescale Semiconductor 17-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x1008 Offset: Fast Ethernet Controller (FEC) Field Description 31–25 Reserved, must be cleared. 24 RDAR Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared. 23–0 Reserved, must be cleared. 17.4.5 Transmit Descriptor Active Register (TDAR) The TDAR is a command register which the user writes to indicate the transmit descriptor ring is updated (transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor). When the register is written, the TDAR bit is set. This value is independent of the data actually written by the user. When set, the FEC polls the transmit descriptor ring and processes transmit frames (provided ECR[ETHER_EN] is also set). After the FEC polls a transmit descriptor that is a ready bit not set, FEC clears the TDAR bit and ceases transmit descriptor ring polling until the user sets the bit again, signifying additional descriptors are placed into the transmit descriptor ring. The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set. IPSBAR 0x1014 Offset: Access: User read/write 31 30 29 28 27 26 25 R 0 0 0 0 0 0 0 W 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TDAR Reset 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-5. Transmit Descriptor Active Register (TDAR) Table 17-8. TDAR Field Descriptions Field Description 31–25 Reserved, must be cleared. 24 TDAR Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared. 23–0 Reserved, must be cleared. 17.4.6 Ethernet Control Register (ECR) ECR is a read/write user register, though hardware may alter fields in this register as well. The ECR enables/disables the FEC. 17-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-7. RDAR Field Descriptions Fast Ethernet Controller (FEC) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER RESET _EN W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-6. Ethernet Control Register (ECR) Table 17-9. ECR Field Descriptions Field Description 31–2 Reserved, must be cleared. 1 When this bit is set, FEC is enabled, and reception and transmission are possible. When this bit is cleared, ETHER_EN reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions: • ECR[RESET] is set by software, in which case ETHER_EN is cleared • An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN is cleared 0 RESET 17.4.7 When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC. ECR[ETHER_EN] is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in progress is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The reset sequence takes approximately eight internal bus clock cycles after this bit is set. MII Management Frame Register (MMFR) The MMFR is user-accessible and does not reset to a defined value. The MMFR register is used to communicate with the attached MII compatible PHY device(s), providing read/write access to their MII registers. Performing a write to the MMFR causes a management frame to be sourced unless the MSCR is programmed to 0. If MSCR is cleared while MMFR is written and then MSCR is written with a non-zero value, an MII frame is generated with the data previously written to the MMFR. This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero. IPSBAR 0x1040 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R W ST OP PA RA TA 8 7 6 5 4 3 2 1 0 DATA Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-7. MII Management Frame Register (MMFR) Freescale Semiconductor 17-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x1024 Offset: Fast Ethernet Controller (FEC) Field Description 31–30 ST Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame. 29–28 OP Operation code. 00 Write frame operation, but not MII compliant. 01 Write frame operation for a valid MII management frame. 10 Read frame operation for a valid MII management frame. 11 Read frame operation, but not MII compliant. 27–23 PA PHY address. This field specifies one of up to 32 attached PHY devices. 22–18 RA Register address. This field specifies one of up to 32 registers within the specified PHY device. 17–16 TA Turn around. This field must be programmed to 10 to generate a valid MII management frame. 15–0 DATA Management frame data. This is the field for data to be written to or read from the PHY register. To perform a read or write operation on the MII Management Interface, write the MMFR register. To generate a valid read or write management frame, ST field must be written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame is generated, but does not comply with the IEEE 802.3 MII definition. To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern causes the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time, contents of the MMFR register are altered as the contents are serially shifted and are unpredictable if read by the user. After the write management frame operation completes, the MII interrupt is generated. At this time, contents of the MMFR register match the original value written. To generate an MII management interface read frame (read a PHY register), the user must write {01 10 PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing this pattern causes the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time, contents of the MMFR register are altered as the contents are serially shifted and are unpredictable if read by the user. After the read management frame operation completes, the MII interrupt is generated. At this time, the contents of the MMFR register match the original value written except for the DATA field whose contents are replaced by the value read from the PHY register. If the MMFR register is written while frame generation is in progress, the frame contents are altered. Software must use the MII interrupt to avoid writing to the MMFR register while frame generation is in progress. 17-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-10. MMFR Field Descriptions Fast Ethernet Controller (FEC) MII Speed Control Register (MSCR) The MSCR provides control of the MII clock (FEC_MDC pin) frequency and allows a preamble drop on the MII management frame. IPSBAR 0x1044 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_ PRE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 MII_SPEED 1 0 0 0 0 0 0 0 0 0 Figure 17-8. MII Speed Control Register (MSCR) Table 17-11. MSCR Field Descriptions Field 31–8 7 DIS_PRE Description Reserved, must be cleared. Setting this bit causes the preamble (32 ones) not to be prepended to the MII management frame. The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require it. 6–1 Controls the frequency of the MII management interface clock (FEC_MDC) relative to the internal bus clock. A MII_SPEED value of 0 in this field turns off the FEC_MDC and leaves it in low voltage state. Any non-zero value results in the FEC_MDC frequency of 1/(MII_SPEED × 2) of the internal bus frequency. 0 Reserved, must be cleared. The MII_SPEED field must be programmed with a value to provide an FEC_MDC frequency of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to a non-zero value to source a read or write management frame. After the management frame is complete, the MSCR register may optionally be set to 0 to turn off the FEC_MDC. The FEC_MDC generated has a 50% duty cycle except when MII_SPEED changes during operation (change takes effect following a rising or falling edge of FEC_MDC). If the internal bus clock is 25 MHz, programming this register to 0x0000_0005 results in an FEC_MDC as stated the equation below. 1 25 MHz × ------------ = 2.5 MHz 5×2 Eqn. 17-1 A table showing optimum values for MII_SPEED as a function of internal bus clock frequency is provided below. Table 17-12. Programming Examples for MSCR Internal FEC Clock Frequency MSCR[MII_SPEED] FEC_MDC frequency 25 MHz 0x5 2.50 MHz 33 MHz 0x7 2.36 MHz 40 MHz 0x8 2.50 MHz Freescale Semiconductor 17-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.4.8 Fast Ethernet Controller (FEC) 17.4.9 Internal FEC Clock Frequency MSCR[MII_SPEED] FEC_MDC frequency 50 MHz 0xA 2.50 MHz 66 MHz 0xE 2.36 MHz MIB Control Register (MIBC) The MIBC is a read/write register controlling and observing the state of the MIB block. User software accesses this register if there is a need to disable the MIB block operation. For example, to clear all MIB counters in RAM: 1. Disable the MIB block 2. Clear all the MIB RAM locations 3. Enable the MIB block The MIB_DIS bit is reset to 1. See Table 17-4 for the locations of the MIB counters. IPSBAR 0x1064 Offset: 31 R W Reset Access: User read/write 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIB_ MIB_ IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-9. MIB Control Register (MIBC) Table 17-13. MIBC Field Descriptions Field Description 31 A read/write control bit. If set, the MIB logic halts and not update any MIB counters. MIB_DIS 30 A read-only status bit. If set the MIB block is not currently updating any MIB counters. MIB_IDLE 29–0 Reserved. 17.4.10 Receive Control Register (RCR) RCR controls the operational mode of the receive block and must be written only when ECR[ETHER_EN] is cleared (initialization time). 17-16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-12. Programming Examples for MSCR (continued) Fast Ethernet Controller (FEC) Access: User read/write 31 30 29 28 27 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 26 25 24 23 22 R 0 1 1 19 18 17 16 1 1 0 1 1 1 0 7 6 5 4 3 2 1 0 0 0 W Reset 20 MAX_FL W Reset 21 FCE 0 BC_ MII_ PROM DRT LOOP REJ MODE 0 0 0 0 1 Figure 17-10. Receive Control Register (RCR) Table 17-14. RCR Field Descriptions Field 31–27 26–16 MAX_FL Description Reserved, must be cleared. Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive frames longer than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor. The recommended default value to be programmed is 1518 or 1522 if VLAN tags are supported. 15–6 Reserved, must be cleared. 5 FCE Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter stops transmitting data frames for a given duration. 4 BC_REJ Broadcast frame reject. If asserted, frames with DA (destination address) equal to FFFF_FFFF_FFFF are rejected unless the PROM bit is set. If BC_REJ and PROM are set, frames with broadcast DA are accepted and the M (MISS) is set in the receive buffer descriptor. 3 PROM 2 MII_MODE Promiscuous mode. All frames are accepted regardless of address matching. Media independent interface mode. Selects the external interface mode for transmit and receive blocks. 0 7-wire mode (used only for serial 10 Mbps) 1 MII mode 1 DRT Disable receive on transmit. 0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 Disable reception of frames while transmitting (normally used for half duplex mode). 0 LOOP Internal loopback. If set, transmitted frames are looped back internal to the device and transmit output signals are not asserted. The internal bus clock substitutes for the FEC_TXCLK when LOOP is asserted. DRT must be set to 0 when setting LOOP. 17.4.11 Transmit Control Register (TCR) TCR is read/write and configures the transmit block. This register is cleared at system reset. Bits 2 and 1 must be modified only when ECR[ETHER_EN] is cleared. Freescale Semiconductor 17-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x1084 Offset: Fast Ethernet Controller (FEC) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R W 8 7 6 5 4 3 2 1 0 RFC_ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAUSE TFC_ FDEN HBC GTS PAUSE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-11. Transmit Control Register (TCR) Table 17-15. TCR Field Descriptions Field 31–5 Description Reserved, must be cleared. 4 Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause frame is RFC_PAUSE received and the transmitter pauses for the duration defined in this pause frame. This bit automatically clears when the pause duration is complete. 3 Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC stops TFC_PAUSE transmission of data frames after the current transmission is complete. At this time, GRA interrupt in the EIR register is asserted. With transmission of data frames stopped, MAC transmits a MAC Control PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, the MAC may continue transmitting a MAC Control PAUSE frame. 2 FDEN Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This bit should only be modified when ECR[ETHER_EN] is cleared. 1 HBC Heartbeat control. If set, the heartbeat check performs following end of transmission and the HB bit in the status register is set if the collision input does not assert within the heartbeat window. This bit should only be modified when ECR[ETHER_EN] is cleared. 0 GTS Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently transmitted is complete and GRA interrupt in the EIR register is asserted. If frame transmission is not currently underway, the GRA interrupt is asserted immediately. After transmission finishes, clear GTS to restart. The next frame in the transmit FIFO is then transmitted. If an early collision occurs during transmission when GTS is set, transmission stops after the collision. The frame is transmitted again after GTS is cleared. There may be old frames in the transmit FIFO that transmit when GTS is reasserted. To avoid this, clear ECR[ETHER_EN] following the GRA interrupt. 17.4.12 Physical Address Lower Register (PALR) PALR contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is not reset and you must initialize it. 17-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x10C4 Offset: Fast Ethernet Controller (FEC) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 PADDR1 W Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-12. Physical Address Lower Register (PALR) Table 17-16. PALR Field Descriptions Field Description 31–0 Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact PADDR1 match and the source address field in PAUSE frames. 17.4.13 Physical Address Upper Register (PAUR) PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for transmission of PAUSE frames. The upper 16 bits of this register are not reset and you must initialize it. IPSBAR 0x10E8 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R W 8 7 6 5 4 3 2 1 0 TYPE PADDR2 Reset — — — — — — — — — — — — — — — — 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 Figure 17-13. Physical Address Upper Register (PAUR) Table 17-17. PAUR Field Descriptions Field Description 31–16 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address PADDR2 field in PAUSE frames. 15–0 TYPE Type field in PAUSE frames. These 16 read-only bits are a constant value of 0x8808. 17.4.14 Opcode/Pause Duration Register (OPD) The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode field is a constant value, 0x0001. When another node detects a PAUSE frame, that node pauses transmission for the duration specified in the pause duration field. The lower 16 bits of this register are not reset and you must initialize them. Freescale Semiconductor 17-19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x10E4 Offset: Fast Ethernet Controller (FEC) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R OPCODE 8 7 6 5 4 3 2 1 0 PAUSE_DUR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — — Figure 17-14. Opcode/Pause Duration Register (OPD) Table 17-18. OPD Field Descriptions Field Description 31–16 OPCODE Opcode field used in PAUSE frames. These read-only bits are a constant, 0x0001. 15–0 Pause Duration field used in PAUSE frames. PAUSE_DUR 17.4.15 Descriptor Individual Upper Address Register (IAUR) IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address recognition process uses this table to check for a possible match with the destination address (DA) field of receive frames with an individual DA. This register is not reset and you must initialize it. IPSBAR 0x1118 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R W 8 7 6 5 4 3 2 1 0 IADDR1 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-15. Descriptor Individual Upper Address Register (IAUR) Table 17-19. IAUR Field Descriptions Field Description 31–0 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast IADDR1 address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. 17.4.16 Descriptor Individual Lower Address Register (IALR) IALR contains the lower 32 bits of the 64-bit individual address hash table. The address recognition process uses this table to check for a possible match with the DA field of receive frames with an individual DA. This register is not reset and you must initialize it. 17-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x10EC Offset: Fast Ethernet Controller (FEC) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 IADDR2 W Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-16. Descriptor Individual Lower Address Register (IALR) Table 17-20. IALR Field Descriptions Field Description 31–0 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast IADDR2 address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. 17.4.17 Descriptor Group Upper Address Register (GAUR) GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. You must initialize this register. IPSBAR 0x1120 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 GADDR1 W Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-17. Descriptor Group Upper Address Register (GAUR) Table 17-21. GAUR Field Descriptions Field Description 31–0 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for GADDR1 receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32. 17.4.18 Descriptor Group Lower Address Register (GALR) GALR contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. You must initialize this register. IPSBAR 0x1124 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 GADDR2 W Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-18. Descriptor Group Lower Address Register (GALR) Freescale Semiconductor 17-21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x111C Offset: Fast Ethernet Controller (FEC) Field Description 31–0 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for GADDR2 receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. 17.4.19 Transmit FIFO Watermark Register (TFWR) The TFWR controls the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows you to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value minimizes the risk of transmit FIFO underrun due to contention for the system bus. The byte counts associated with the TFWR field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data DMA channel). IPSBAR 0x1144 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 1 0 TFWR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-19. Transmit FIFO Watermark Register (TFWR) Table 17-23. TFWR Field Descriptions Field 31–2 1–0 TFWR Description Reserved, must be cleared. Number of bytes written to transmit FIFO before transmission of a frame begins 00 64 bytes written 01 64 bytes written 10 128 bytes written 11 192 bytes written 17.4.20 FIFO Receive Bound Register (FRBR) FRBR indicates the upper address bound of the FIFO RAM. Drivers can use this value, along with the FRSR, to appropriately divide the available FIFO RAM between the transmit and receive data paths. IPSBAR 0x114C Offset: Access: User read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 1 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 7 6 5 4 R_BOUND 3 2 W Figure 17-20. FIFO Receive Bound Register (FRBR) 17-22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-22. GALR Field Descriptions Fast Ethernet Controller (FEC) Field Description 31–10 Reserved, read as 0 (except bit 10, which is read as 1). 9–2 Read-only. Highest valid FIFO RAM address. R_BOUND 1–0 Reserved, read as 0. 17.4.21 FIFO Receive Start Register (FRSR) FRSR indicates the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive. Hardware initializes the FRSR register at reset. FRSR only needs to be written to change the default value. IPSBAR 0x1150 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 1 0 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 W 7 6 5 4 R_FSTART 3 2 Figure 17-21. FIFO Receive Start Register (FRSR) Table 17-25. FRSR Field Descriptions Field 31–11 10 Description Reserved, must be cleared. Reserved, must be set. 9–2 Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper R_FSTART operation, ensure that R_FSTART is set to 0x48 or greater. 1–0 Reserved, must be cleared. 17.4.22 Receive Descriptor Ring Start Register (ERDSR) ERDSR points to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). This register is not reset and must be initialized prior to operation. Freescale Semiconductor 17-23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-24. FRBR Field Descriptions Fast Ethernet Controller (FEC) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 R_DES_START W 1 0 0 0 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-22. Ethernet Receive Descriptor Ring Start Register (ERDSR) Table 17-26. ERDSR Field Descriptions Field Description 31–2 Pointer to start of receive buffer descriptor queue. R_DES_START 1–0 Reserved, must be cleared. 17.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR) ETSDR provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). You should write zeros to bits 1 and 0. Hardware ignores non-zero values in these two bit positions. This register is undefined at reset and must be initialized prior to operation. IPSBAR 0x1184 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 X_DES_START W 4 3 2 1 0 0 0 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-23. Transmit Buffer Descriptor Ring Start Register (ETDSR) Table 17-27. ETDSR Field Descriptions Field Description 31–2 Pointer to start of transmit buffer descriptor queue. X_DES_START 1–0 Reserved, must be cleared. 17.4.24 Receive Buffer Size Register (EMRBR) The EMRBR is a user-programmable register that dictates the maximum size of all receive buffers. This value should take into consideration that the receive CRC is always written into the last receive buffer. To allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. To properly align the buffer, EMRBR must be evenly divisible by 16. To ensure this, bits 3–0 are forced low. 17-24 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x1180 Offset: To minimize bus utilization (descriptor fetches), it is recommended that EMRBR be greater than or equal to 256 bytes. The EMRBR register is undefined at reset and must be initialized by the user. IPSBAR 0x1188 Offset: Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 8 7 6 5 R_BUF_SIZE 4 1 0 0 0 0 3 2 0 Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 17-24. Receive Buffer Size Register (EMRBR) Table 17-28. EMRBR Field Descriptions Field Description 31–11 Reserved, must be cleared. 10–4 Maximum size of receive buffer size in bytes. To minimize bus utilization (descriptor fetches), set this field to 256 R_BUF_SIZE bytes (0x10) or larger. 0x10 256 + 15 bytes (minimum size recommended) 0x11 272 + 15 bytes ... 0x7F 2032 + 15 bytes. The FEC writes up to 2047 bytes in the receive buffer. If data larger than 2047 is received, the FEC truncates it and shows 0x7FF in the receive descriptor 3–0 17.5 Reserved, must be cleared. Functional Description This section describes the operation of the FEC, beginning with the buffer descriptors, the hardware and software initialization sequence, then the software (Ethernet driver) interface for transmitting and receiving frames. Following the software initialization and operation sections are sections providing a detailed description of the functions of the FEC. 17.5.1 Buffer Descriptors This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is followed by a detailed description of the receive and transmit descriptor fields. 17.5.1.1 Driver/DMA Operation with Buffer Descriptors The data for the FEC frames resides in one or more memory buffers external to the FEC. Associated with each buffer is a buffer descriptor (BD), which contains a starting address (32-bit aligned pointer), data length, and status/control information (which contains the current state for the buffer). To permit maximum user flexibility, the BDs are also located in external memory and are read by the FEC DMA engine. Freescale Semiconductor 17-25 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Software produces buffers by allocating/initializing memory and initializing buffer descriptors. Setting the RxBD[E] or TxBD[R] bit produces the buffer. Software writing to TDAR or RDAR tells the FEC that a buffer is placed in external memory for the transmit or receive data traffic, respectively. The hardware reads the BDs and consumes the buffers after they have been produced. After the data DMA is complete and the DMA engine writes the buffer descriptor status bits, hardware clears RxBD[E] or TxBD[R] to signal the buffer has been consumed. Software may poll the BDs to detect when the buffers are consumed or may rely on the buffer/frame interrupts. The driver may process these buffers, and they can return to the free list. The ECR[ETHER_EN] bit operates as a reset to the BD/DMA logic. When ECR[ETHER_EN] is cleared, the DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The buffer descriptors are not initialized by hardware during reset. At least one transmit and receive buffer descriptor must be initialized by software before ECR[ETHER_EN] is set. The buffer descriptors operate as two separate rings. ERDSR defines the starting address for receive BDs and ETDSR defines the starting address for transmit BDs. The wrap (W) bit defines the last buffer descriptor in each ring. When W is set, the next descriptor in the ring is at the location pointed to by ERDSR and ETDSR for the receive and transmit rings, respectively. Buffer descriptor rings must start on a 32-bit boundary; however, it is recommended they are made 128-bit aligned. 17.5.1.1.1 Driver/DMA Operation with Transmit BDs Typically, a transmit frame is divided between multiple buffers. An example is to have an application payload in one buffer, TCP header in a second buffer, IP header in a third buffer, and Ethernet/IEEE 802.3 header in a fouth buffer. The Ethernet MAC does not prepend the Ethernet header (destination address, source address, length/type field(s)), so the driver must provide this in one of the transmit buffers. The Ethernet MAC can append the Ethernet CRC to the frame. TxBD[TC], which must be set by the driver, determines whether the MAC or driver appends the CRC. The driver (TxBD software producer) should set up Tx BDs so a complete transmit frame is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized with pointer, length, and control (W, L, TC, ABC) and then the TxBD[R] bit should be set in reverse order (third, second, then first BD) to ensure that the complete frame is ready in memory before the DMA begins. If the TxBDs are set up in order, the DMA controller could DMA the first BD before the second was made available, potentially causing a transmit FIFO underrun. In the FEC, the driver notifies the DMA that new transmit frame(s) are available by writing to TDAR. When this register is written to (data value is not significant) the FEC, RISC tells the DMA to read the next transmit BD in the ring. After started, the RISC + DMA continues to read and interpret transmit BDs in order and DMA the associated buffers until a transmit BD is encountered with the R bit cleared. At this point, the FEC polls this BD one more time. If the R bit is cleared the second time, RISC stops the transmit descriptor read process until software sets up another transmit frame and writes to TDAR. When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R bit, indicating that the hardware consumer is finished with the buffer. 17-26 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) Driver/DMA Operation with Receive BDs Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore, the driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to the EMRBR register. The driver (RxBD software producer) should set up some number of empty buffers for the Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive DMA) consumes these buffers by filling them with data as frames are received and clearing the E bit and writing to the L bit (1 indicates last buffer in frame), the frame status bits (if L is set), and the length field. If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For non-last buffers, the length field in the receive BD is written by the DMA (at the same time the E bit is cleared) with the default receive buffer length value. For end-of-frame buffers, the receive BD is written with L set and information written to the status bits (M, BC, MC, LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher layers. The frame status/length information is written into the receive FIFO following the end of the frame (as a single 32-bit word) by the receive logic. The length field for the end of frame buffer is written with the length of the entire frame, not only the length of the last buffer. For simplicity, the driver may assign a large enough default receive buffer length to contain an entire frame, keeping in mind that a malfunction on the network or out-of-spec implementation could result in giant frames. Frames of 2K (2048) bytes or larger are truncated by the FEC at 2047 bytes so software never sees a receive frame larger than 2047 bytes. Similar to transmit, the FEC polls the receive descriptor ring after the driver sets up receive BDs and writes to the RDAR register. As frames are received, the FEC fills receive buffers and updates the associated BDs, then reads the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E bit cleared, it polls this BD once more. If RxBD[E] is clear a second time, FEC stops reading receive BDs until the driver writes to RDAR. 17.5.1.2 Ethernet Receive Buffer Descriptor (RxBD) In the RxBD, the user initializes the E and W bits in the first longword and the pointer in the second longword. When the buffer has been DMA’d, the Ethernet controller modifies the E, L, M, BC, MC, LG, NO, CR, OV, and TR bits and writes the length of the used portion of the buffer in the first longword. The M, BC, MC, LG, NO, CR, OV, and TR bits in the first longword of the buffer descriptor are only modified by the Ethernet controller when the L bit is set. Offset + 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E RO1 W RO2 L — — M BC MC LG NO — CR OV TR Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer - A[31:16] Offset + 6 Rx Data Buffer Pointer - A[15:0] Figure 17-25. Receive Buffer Descriptor (RxBD) Freescale Semiconductor 17-27 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.5.1.1.2 Fast Ethernet Controller (FEC) Word Field Description Offset + 0 15 E Empty. Written by the FEC (=0) and user (=1). 0 The data buffer associated with this BD is filled with received data, or data reception has aborted due to an error condition. The status and length fields have been updated as required. 1 The data buffer associated with this BD is empty, or reception is currently in progress. Offset + 0 14 RO1 Offset + 0 13 W Offset + 0 12 RO2 Offset + 0 11 L Offset + 0 10–9 Offset + 0 8 M Miss. Written by the FEC. This bit is set by the FEC for frames accepted in promiscuous mode, but flagged as a miss by the internal address recognition. Therefore, while in promiscuous mode, you can use the M-bit to quickly determine whether the frame was destined to this station. This bit is valid only if the L-bit is set and the PROM bit is set. 0 The frame was received because of an address recognition hit. 1 The frame was received because of promiscuous mode. Offset + 0 7 BC Set if the DA is broadcast (FFFF_FFFF_FFFF). Offset + 0 6 MC Set if the DA is multicast and not BC. Offset + 0 5 LG Rx frame length violation. Written by the FEC. A frame length greater than RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive data is not altered in any way unless the length exceeds 2047 bytes. Offset + 0 4 NO Receive non-octet aligned frame. Written by the FEC. A frame that contained a number of bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary generated an error. This bit is valid only if the L-bit is set. If this bit is set, the CR bit is not set. Offset + 0 3 Offset + 0 2 CR Receive CRC error. Written by the FEC. This frame contains a CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set. Offset + 0 1 OV Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and are zero. This bit is valid only if the L-bit is set. Offset + 0 0 TR Set if the receive frame is truncated (frame length > 2047 bytes). If the TR bit is set, the frame must be discarded and the other error bits must be ignored as they may be incorrect. Offset + 2 15–0 Data Length Data length. Written by the FEC. Data length is the number of octets written by the FEC into this BD’s data buffer if L equals 0 (the value is equal to EMRBR), or the length of the frame including CRC if L is set. It is written by the FEC once as the BD is closed. 17-28 Receive software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its value affect hardware. Wrap. Written by user. 0 The next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ERDSR. Receive software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its value affect hardware. Last in frame. Written by the FEC. 0 The buffer is not the last in a frame. 1 The buffer is the last in a frame. Reserved, must be cleared. Reserved, must be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-29. Receive Buffer Descriptor Field Definitions Fast Ethernet Controller (FEC) 1 Word Field Description 0ffset + 4 15–0 A[31:16] RX data buffer pointer, bits [31:16]1 Offset + 6 15–0 A[15:0] RX data buffer pointer, bits [15:0] The receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. The Ethernet controller never modifies this value. NOTE When the software driver sets an E bit in one or more receive descriptors, the driver should follow with a write to RDAR. 17.5.1.3 Ethernet Transmit Buffer Descriptor (TxBD) Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs. The Ethernet controller confirms transmission by clearing the ready bit (TxBD[R]) when DMA of the buffer is complete. In the TxBD, the user initializes the R, W, L, and TC bits and the length (in bytes) in the first longword and the buffer pointer in the second longword. The FEC clears the R bit when the buffer is transferred. Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 17.4.1, “MIB Block Counters Memory Map,” for more details. Offset + 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TO1 W TO2 L TC ABC — — — — — — — — — Offset + 2 Data Length Offset + 4 Tx Data Buffer Pointer - A[31:16] Offset + 6 Tx Data Buffer Pointer - A[15:0] Figure 17-26. Transmit Buffer Descriptor (TxBD) Table 17-30. Transmit Buffer Descriptor Field Definitions Word Field Description Offset + 0 15 R Ready. Written by the FEC and you. 0 The data buffer associated with this BD is not ready for transmission. You are free to manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 The data buffer, prepared for transmission by you, has not been transmitted or currently transmits. You may write no fields of this BD after this bit is set. Offset + 0 14 TO1 Transmit software ownership. This field is reserved for software use. This read/write bit is not modified by hardware nor does its value affect hardware. Freescale Semiconductor 17-29 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-29. Receive Buffer Descriptor Field Definitions (continued) Fast Ethernet Controller (FEC) 1 Word Field Description Offset + 0 13 W Offset + 0 12 TO2 Offset + 0 11 L Last in frame. Written by user. 0 The buffer is not the last in the transmit frame 1 The buffer is the last in the transmit frame Offset + 0 10 TC Transmit CRC. Written by user (only valid if L is set). 0 End transmission immediately after the last data byte 1 Transmit the CRC sequence after the last data byte Offset + 0 9 ABC Append bad CRC. Written by user (only valid if L is set). 0 No effect 1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value) Offset + 0 8–0 Reserved, must be cleared. Offset + 2 15–0 Data Length Offset + 4 15–0 A[31:16] Tx data buffer pointer, bits [31:16]1 Offset + 6 15–0 A[15:0] Tx data buffer pointer, bits [15:0] Wrap. Written by user. 0 The next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ETDSR. Transmit software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware nor does its value affect hardware. Data length, written by user. Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC. The transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller. NOTE After the software driver has set up the buffers for a frame, it should set up the corresponding BDs. The last step in setting up the BDs for a transmit frame is setting the R bit in the first BD for the frame. The driver must follow that with a write to TDAR that triggers the FEC to poll the next BD in the ring. 17.5.2 Initialization Sequence This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC, and what locations you must initialize prior to enabling the FEC. 17.5.2.1 Hardware Controlled Initialization In the FEC, hardware resets registers and control logic that generate interrupts. A hardware reset negates output signals and resets general configuration bits. 17-30 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-30. Transmit Buffer Descriptor Field Definitions (continued) Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a hard reset or software to halt operation). By clearing ECR[ETHER_EN], configuration control registers such as the TCR and RCR are not reset, but the entire data path is reset. Table 17-31. ECR[ETHER_EN] De-Assertion Effect on FEC 17.5.3 Register/Machine Reset Value XMIT block Transmission is aborted (bad CRC appended) RECV block Receive activity is aborted DMA block All DMA activity is terminated RDAR Cleared TDAR Cleared Descriptor Controller block Halt operation User Initialization (Prior to Setting ECR[ETHER_EN]) You need to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values depend on the particular application. The sequence is not important. Table 17-32 defines Ethernet MAC registers requiring initialization. Table 17-32. User Initialization (Before ECR[ETHER_EN]) Description Initialize EIMR Clear EIR (write 0xFFFF_FFFF) TFWR (optional) IALR / IAUR GAUR / GALR PALR / PAUR (only needed for full duplex flow control) OPD (only needed for full duplex flow control) RCR TCR MSCR (optional) Clear MIB_RAM Table 17-33 defines FEC FIFO/DMA registers that require initialization. Table 17-33. FEC User Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR Initialize ETDSR Freescale Semiconductor 17-31 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) Description Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring 17.5.4 Microcontroller Initialization In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted. After the microcontroller initialization sequence is complete, hardware is ready for operation. Table 17-34 shows microcontroller initialization operations. Table 17-34. Microcontroller Initialization Description Initialize BackOff Random Number Seed Activate Receiver Activate Transmitter Clear Transmit FIFO Clear Receive FIFO Initialize Transmit Ring Pointer Initialize Receive Ring Pointer Initialize FIFO Count Registers 17.5.5 User Initialization (After Setting ECR[ETHER_EN]) After setting ECR[ETHER_EN], you can set up the buffer/frame descriptors and write to TDAR and RDAR. Refer to Section 17.5.1, “Buffer Descriptors,” for more details. 17.5.6 Network Interface Options The FEC supports an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps Ethernet. The RCR[MII_MODE] bit select the interface mode. In MII mode (RCR[MII_MODE] set), there are 18 signals defined by the IEEE 802.3 standard and supported by the EMAC. Table 17-35 shows these signals. Table 17-35. MII Mode 17-32 Signal Description EMAC pin Transmit Clock FEC_TXCLK Transmit Enable FEC_TXEN Transmit Data FEC_TXD[3:0] Transmit Error FEC_TXER Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-33. FEC User Initialization (Before ECR[ETHER_EN]) (continued) Fast Ethernet Controller (FEC) Signal Description EMAC pin Collision FEC_COL Carrier Sense FEC_CRS Receive Clock FEC_RXCLK Receive Data Valid FEC_RXDV Receive Data FEC_RXD[3:0] Receive Error FEC_RXER Management Data Clock FEC_MDC Management Data Input/Output FEC_MDIO The 7-wire serial mode interface (RCR[MII_MODE] cleared) is generally referred to as AMD mode. Table 17-36 shows the 7-wire mode connections to the external transceiver. Table 17-36. 7-Wire Mode Configuration 17.5.7 Signal description EMAC Pin Transmit Clock FEC_TXCLK Transmit Enable FEC_TXEN Transmit Data FEC_TXD[0] Collision FEC_COL Receive Clock FEC_RXCLK Receive Data Valid FEC_RXDV Receive Data FEC_RXD[0] FEC Frame Transmission The Ethernet transmitter is designed to work with almost no intervention from software. After ECR[ETHER_EN] is set and data appears in the transmit FIFO, the Ethernet MAC can transmit onto the network. The Ethernet controller transmits bytes least significant bit (lsb) first. When the transmit FIFO fills to the watermark (defined by TFWR), MAC transmit logic asserts FEC_TXEN and starts transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then the frame information from the FIFO. However, the controller defers the transmission if the network is busy (FEC_CRS is asserted). Before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If so, transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See Section 17.5.15.1, “Transmission Errors,” for more details. Freescale Semiconductor 17-33 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-35. MII Mode (continued) If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so they do not have to be retrieved from system memory in case of a collision. This improves bus utilization and latency in case immediate retransmission is necessary. When all the frame data is transmitted, FCS (frame check sequence) or 32-bit cyclic redundancy check (CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC is appended to the frame data regardless of the TC bit value. Following the transmission of the CRC, the Ethernet controller writes the frame status information to the MIB block. Transmit logic automatically pads short frames (if the TC bit in the transmit buffer descriptor for the end of frame buffer is set). Settings in the EIMR determine interrupts generated to the buffer (TXB) and frame (TFINT). The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes, BABT interrupt is asserted. However, the entire frame is transmitted (no truncation). To pause transmission, set TCR[GTS] (graceful transmit stop). The FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues transmission until the current frame finishes or terminates with a collision. After the transmitter has stopped, the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with the next frame. 17.5.7.1 Duplicate Frame Transmission The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being processed internally (as a result of a wrap). As the FEC nears the end of the transmission of one frame, it begins to DMA the data for the next frame. To remain one BD ahead of the DMA, it also fetches the TxBD for the next frame. It is possible that the FEC fetches from memory a BD that has already been processed but not yet written back (it is read a second time with the R bit remains set). In this case, the data is fetched and transmitted again. Using at least three TxBDs fixes this problem for large frames, but not for small frames. To ensure correct operation for large or small frames, one of the following must be true: • The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared. • Every frame uses more than one TxBD and every TxBD but the last is written back immediately after the data is fetched. • The FEC software driver ensures a minimum frame size, n. The minimum number of TxBDs is then (Tx FIFO Size ÷ (n + 4)) rounded up to the nearest integer (though the result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is programmable. 17-34 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) FEC Frame Reception The FEC receiver works with almost no intervention from the host and can perform address recognition, CRC checking, short frame checking, and maximum frame length checking. The Ethernet controller receives serial data lsb first. When the driver enables the FEC receiver by setting ECR[ETHER_EN], it immediately starts processing receive frames. When FEC_RXDV is asserted, the receiver first checks for a valid PA/SFD header. If the PA/SFD is valid, it is stripped and the receiver processes the frame. If a valid PA/SFD is not found, the frame is ignored. In serial mode, the first 16 bit times of RX_D0 following assertion of FEC_RXDV are ignored. Following the first 16 bit times, the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected, the PA/SFD sequence is complete. In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored. After the first 6 bytes of the frame are received, the FEC performs address recognition on the frame. After a collision window (64 bytes) of data is received and if address recognition has not rejected the frame, the receive FIFO signals the frame is accepted and may be passed on to the DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to reject the frame. Therefore, no collision fragments are presented to you except late collisions, which indicate serious LAN problems. During reception, the Ethernet controller checks for various error conditions and after the entire frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the M, BC, MC, LG, NO, CR, OV, and TR status bits, and the frame length. See Section 17.5.15.2, “Reception Errors,” for more details. Receive buffer (RXB) and frame interrupts (RFINT) may be generated if enabled by the EIMR register. A receive error interrupt is a babbling receiver error (BABR). Receive frames are not truncated if they exceed the max frame length (MAX_FL); however, the BABR interrupt occurs and the LG bit in the receive buffer descriptor (RxBD) is set. See Section 17.5.1.2, “Ethernet Receive Buffer Descriptor (RxBD),” for more details. When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame is received and is in memory. The Ethernet controller then waits for a new frame. 17.5.9 Ethernet Address Recognition The FEC filters the received frames based on destination address (DA) type — individual (unicast), group (multicast), or broadcast (all-ones group address). The difference between an individual address and a Freescale Semiconductor 17-35 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.5.8 group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames appears in the figures below. Address recognition is accomplished through the use of the receive block and microcode running on the microcontroller. The flowchart shown in Figure 17-27 illustrates the address recognition decisions made by the receive block, while Figure 17-28 illustrates the decisions made by the microcontroller. If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is cleared, then the frame is accepted unconditionally, as shown in Figure 17-27. Otherwise, if the DA is not a broadcast address, then the microcontroller runs the address recognition subroutine, as shown in Figure 17-28. If the DA is a group (multicast) address and flow control is disabled, then the microcontroller performs a group hash table lookup using the 64-entry hash table programmed in GAUR and GALR. If a hash match occurs, the receiver accepts the frame. If flow control is enabled, the microcontroller does an exact address match check between the DA and the designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines the received frame is a valid PAUSE frame, the frame is rejected. The receiver detects a PAUSE frame with the DA field set to the designated PAUSE DA or the unicast physical address. If the DA is the individual (unicast) address, the microcontroller performs an individual exact match comparison between the DA and 48-bit physical address that you program in the PALR and PAUR registers. If an exact match occurs, the frame is accepted; otherwise, the microcontroller does an individual hash table lookup using the 64-entry hash table programmed in registers, IAUR and IALR. In the case of an individual hash match, the frame is accepted. Again, the receiver accepts or rejects the frame based on PAUSE frame detection, shown in Figure 17-27. If neither a hash match (group or individual) nor an exact match (group or individual) occur, and if promiscuous mode is enabled (RCR[PROM] set), the frame is accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame is rejected. Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and promiscuous mode is enabled, the frame is accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame is rejected. In general, when a frame is rejected, it is flushed from the FIFO. 17-36 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) True Broadcast Addr ? Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Accept/Reject Frame False Receive Address Recognition False Receive Frame Set BC bit in RCV BD True Hash Match ? BC_REJ = 1 ? False True Receive Frame Set MC bit in RCV BD if multicast Exact Match ? True False True Pause Frame ? False Reject Frame Flush from FIFO Notes: BC_REJ - field in RCR register (BroadCast REJect) PROM - field in RCR register (PROMiscous mode) Pause Frame - valid PAUSE frame received PROM = 1 ? True Receive Frame Set M (Miss) bit in Rcv BD Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if broadcast False Reject Frame Flush from FIFO Receive Frame Figure 17-27. Ethernet Address Recognition—Receive Block Decisions Freescale Semiconductor 17-37 Receive Address Recognition Group False Individual False True FCE ? False I/G Address ? Pause Address ? Exact Match ? True Hash Search Individual Table Receive Frame Receive Frame Hash Search Group Table Match ? True False Receive Frame Reject Frame Flush from FIFO True True Match ? False Receive Frame Reject Frame Notes: Flush from FIFO FCE - field in RCR register (flow control enable) I/G - Individual/Group bit in destination address (lsb in first byte received in MAC frame) Figure 17-28. Ethernet Address Recognition—Microcode Decisions 17.5.10 Hash Algorithm The hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bit destination address is mapped into one of 64 bits, represented by 64 bits stored in GAUR, GALR (group address hash match), or IAUR, IALR (individual address hash match). This mapping is performed by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting the six most significant bits of the CRC-encoded result to generate a number between 0 and 63. The msb of the CRC result selects GAUR (msb = 1) or GALR (msb = 0). The five least significant bits of the hash result select the bit within the selected register. If the CRC generator selects a bit set in the hash table, the frame is accepted; otherwise, it is rejected. For example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. 17-38 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1 Eqn. 17-2 Table 17-37 contains example destination addresses and corresponding hash values. Table 17-37. Destination Address to 6-Bit Hash Freescale Semiconductor 48-bit DA 6-bit Hash (in hex) Hash Decimal Value 65FF_FFFF_FFFF 0x0 0 55FF_FFFF_FFFF 0x1 1 15FF_FFFF_FFFF 0x2 2 35FF_FFFF_FFFF 0x3 3 B5FF_FFFF_FFFF 0x4 4 95FF_FFFF_FFFF 0x5 5 D5FF_FFFF_FFFF 0x6 6 F5FF_FFFF_FFFF 0x7 7 DBFF_FFFF_FFFF 0x8 8 FBFF_FFFF_FFFF 0x9 9 BBFF_FFFF_FFFF 0xA 10 8BFF_FFFF_FFFF 0xB 11 0BFF_FFFF_FFFF 0xC 12 3BFF_FFFF_FFFF 0xD 13 7BFF_FFFF_FFFF 0xE 14 5BFF_FFFF_FFFF 0xF 15 27FF_FFFF_FFFF 0x10 16 07FF_FFFF_FFFF 0x11 17 57FF_FFFF_FFFF 0x12 18 77FF_FFFF_FFFF 0x13 19 F7FF_FFFF_FFFF 0x14 20 C7FF_FFFF_FFFF 0x15 21 97FF_FFFF_FFFF 0x16 22 A7FF_FFFF_FFFF 0x17 23 99FF_FFFF_FFFF 0x18 24 B9FF_FFFF_FFFF 0x19 25 F9FF_FFFF_FFFF 0x1A 26 C9FF_FFFF_FFFF 0x1B 27 17-39 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 The user must initialize the hash table registers. Use this CRC32 polynomial to compute the hash: Fast Ethernet Controller (FEC) 17-40 48-bit DA 6-bit Hash (in hex) Hash Decimal Value 59FF_FFFF_FFFF 0x1C 28 79FF_FFFF_FFFF 0x1D 29 29FF_FFFF_FFFF 0x1E 30 19FF_FFFF_FFFF 0x1F 31 D1FF_FFFF_FFFF 0x20 32 F1FF_FFFF_FFFF 0x21 33 B1FF_FFFF_FFFF 0x22 34 91FF_FFFF_FFFF 0x23 35 11FF_FFFF_FFFF 0x24 36 31FF_FFFF_FFFF 0x25 37 71FF_FFFF_FFFF 0x26 38 51FF_FFFF_FFFF 0x27 39 7FFF_FFFF_FFFF 0x28 40 4FFF_FFFF_FFFF 0x29 41 1FFF_FFFF_FFFF 0x2A 42 3FFF_FFFF_FFFF 0x2B 43 BFFF_FFFF_FFFF 0x2C 44 9FFF_FFFF_FFFF 0x2D 45 DFFF_FFFF_FFFF 0x2E 46 EFFF_FFFF_FFFF 0x2F 47 93FF_FFFF_FFFF 0x30 48 B3FF_FFFF_FFFF 0x31 49 F3FF_FFFF_FFFF 0x32 50 D3FF_FFFF_FFFF 0x33 51 53FF_FFFF_FFFF 0x34 52 73FF_FFFF_FFFF 0x35 53 23FF_FFFF_FFFF 0x36 54 13FF_FFFF_FFFF 0x37 55 3DFF_FFFF_FFFF 0x38 56 0DFF_FFFF_FFFF 0x39 57 5DFF_FFFF_FFFF 0x3A 58 7DFF_FFFF_FFFF 0x3B 59 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-37. Destination Address to 6-Bit Hash (continued) Freescale Semiconductor Fast Ethernet Controller (FEC) 48-bit DA 6-bit Hash (in hex) Hash Decimal Value FDFF_FFFF_FFFF 0x3C 60 DDFF_FFFF_FFFF 0x3D 61 9DFF_FFFF_FFFF 0x3E 62 BDFF_FFFF_FFFF 0x3F 63 17.5.11 Full Duplex Flow Control Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration. To enable PAUSE frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] set) with flow control (RCR[FCE] set). The FEC detects a pause frame when the fields of the incoming frame match the pause frame specifications, as shown in Table 17-38. In addition, the receive status associated with the frame should indicate that the frame is valid. Table 17-38. PAUSE Frame Field Specification 48-bit Destination Address 0x0180_C200_0001 or Physical Address 48-bit Source Address Any 16-bit Type 0x8808 16-bit Opcode 0x0001 16-bit PAUSE Duration 0x0000 – 0xFFFF The receiver and microcontroller modules perform PAUSE frame detection. The microcontroller runs an address recognition subroutine to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is set by the FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to increment. The pause timer uses the transmit backoff timer hardware for tracking the appropriate collision backoff time in half-duplex mode. The pause timer increments once every slot time, until OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is cleared allowing MAC data frame transmission to resume. The receive flow control pause status bit (TCR[RFC_PAUSE]) is set while the transmitter pauses due to reception of a pause frame. To transmit a pause frame, the FEC must operate in full-duplex mode and you must set flow control pause (TCR[TFC_PAUSE]). After TCR[TFC_PAUSE] is set, the transmitter sets TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts and the pause frame is transmitted. TCR[TFC_PAUSE,GTS] are then cleared internally. You must specify the desired pause duration in the OPD register. Freescale Semiconductor 17-41 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 17-37. Destination Address to 6-Bit Hash (continued) When the transmitter pauses due to receiver/microcontroller pause frame detection, TCR[TFC_PAUSE] may remain set and cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt is not asserted. 17.5.12 Inter-Packet Gap (IPG) Time The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it is ignored and a collision occurs. The receiver accepts back-to-back frames with a minimum spacing of at least 28 bit times. If an inter-packet gap between receive frames is less than 28 bit times, the receiver may discard the following frame. 17.5.13 Collision Managing If a collision occurs during frame transmission, the Ethernet controller continues the transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the preamble sequence, a JAM pattern is sent after the end of the preamble sequence. If a collision occurs within 512 bit times (one slot time), the retry process is initiated. The transmitter waits a random number of slot times. If a collision occurs after 512 bit times, then no retransmission is performed and the end of frame buffer is closed with a Late Collision (LC) error indication. 17.5.14 MII Internal and External Loopback Internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. Internal and external loopback are configured using combinations of the RCR[LOOP, DRT] and TCR[FDEN] bits. Set FDEN for internal and external loopback. For internal loopback, set RCR[LOOP] and clear RCR[DRT]. FEC_TXEN and FEC_TXER do not assert during internal loopback. During internal loopback, the transmit/receive data rate is higher than in normal operation because the transmit and receive blocks use the internal bus clock instead of the clocks from the external transceiver. This causes an increase in the required system bus bandwidth for transmit and receive data being DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the frames to prevent transmit FIFO underruns and receive FIFO overflows. For external loopback, clear RCR[LOOP] and RCR[DRT], and configure the external transceiver for loopback. 17.5.15 Ethernet Error-Managing Procedure The Ethernet controller reports frame reception and transmission error conditions using the MIB block counters, the FEC RxBDs, and the EIR register. 17-42 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Fast Ethernet Controller (FEC) Fast Ethernet Controller (FEC) 17.5.15.1.1 Transmitter Underrun If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed, and EIR[UN] is set. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next frame. The UN interrupt is asserted if enabled in the EIMR register. 17.5.15.1.2 Retransmission Attempts Limit Expired When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and EIR[RL] is set. The FEC then continues to the next transmit buffer descriptor and begins transmitting the next frame. The RL interrupt is asserted if enabled in the EIMR register. 17.5.15.1.3 Late Collision When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and EIR[LC] is set. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next frame. The LC interrupt is asserted if enabled in the EIMR register. 17.5.15.1.4 Heartbeat Some transceivers have a self-test feature called heartbeat or signal quality error. To signify a good self-test, the transceiver indicates a collision to the FEC within four microseconds after completion of a frame transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error on the network, but is rather an indication that the transceiver continues to function properly. This is the heartbeat condition. If TCR[HBC] is set and the heartbeat condition is not detected by the FEC after a frame transmission, a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets EIR[HB], and generates the HBERR interrupt if it is enabled. 17.5.15.2 Reception Errors 17.5.15.2.1 Overrun Error If the receive block has data to put into the receive FIFO and the receive FIFO is full, FEC sets RxBD[OV]. All subsequent data in the frame is discarded and subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available. At this point the receive frame/status word is written into the FIFO with the OV bit set. The driver must discard this frame. 17.5.15.2.2 Non-Octet Error (Dribbling Bits) The Ethernet controller manages up to seven dribbling bits when the receive frame terminates past an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error, the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, no error is reported. Freescale Semiconductor 17-43 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.5.15.1 Transmission Errors Fast Ethernet Controller (FEC) When a CRC error occurs with no dribble bits, FEC closes the buffer and sets RxBD[CR]. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required. 17.5.15.2.4 Frame Length Violation When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated, and RxBD[LG] is set. The frame is not truncated unless the frame length exceeds 2047 bytes. 17.5.15.2.5 Truncation When the receive frame length exceeds 2047 bytes, frame is truncated and RxBD[TR] is set. 17-44 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 17.5.15.2.3 CRC Error 18.1 Introduction The watchdog timer is a 16-bit timer used to help software recover from runaway code. The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown by servicing the watchdog. 18.2 Low-Power Mode Operation This subsection describes the operation of the watchdog module in low-power modes and halted mode of operation. Low-power modes are described in Chapter 7, “Power Management.” Table 3-1 shows the watchdog module operation in the low-power modes, and shows how this module may facilitate exit from each mode. Table 18-1. Watchdog Module Operation in Low-power Modes Low-power Mode Watchdog Operation Wait Normal if WCR[WAIT] cleared, stopped otherwise Upon Watchdog reset Doze Normal if WCR[DOZE] cleared, stopped otherwise Upon Watchdog reset Stop Stopped Halted Mode Exit No Normal if WCR[HALTED] cleared, Upon Watchdog reset stopped otherwise In wait mode with the watchdog control register’s WAIT bit (WCR[WAIT]) set, watchdog timer operation stops. In wait mode with the WCR[WAIT] bit cleared, the watchdog timer continues to operate normally. In doze mode with the WCR[DOZE] bit set, the watchdog timer module operation stops. In doze mode with the WCR[DOZE] bit cleared, the watchdog timer continues to operate normally. Watchdog timer operation stops in stop mode. When stop mode is exited, the watchdog timer continues to operate in its pre-stop mode state. In halted mode with the WCR[HALTED] bit set, watchdog timer module operation stops. In halted mode with the WCR[HALTED] bit cleared, the watchdog timer continues to operate normally. When halted mode is exited, watchdog timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. Freescale Semiconductor 18-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 18 Watchdog Timer Module Watchdog Timer Module Block Diagram IPBUS 16-bit WCNTR System Clock 16-bit WSR Count = 0 Divide by 8192 16-bit Watchdog Counter EN Reset Load Counter WAIT DOZE 16-bit WMR HALTED IPBUS Figure 18-1. Watchdog Timer Block Diagram 18.4 Signals The watchdog timer module has no off-chip signals. 18.5 Memory Map and Registers This subsection describes the memory map and registers for the watchdog timer. The watchdog timer has a IPSBAR offset for base address of 0x0014_0000. 18.5.1 Memory Map Refer to Table 18-2 for an overview of the watchdog memory map. 18-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 18.3 Watchdog Timer Module IPSBAR Offset 1 18.5.2 Bits 15–8 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 18-2. Watchdog Timer Module Memory Map Access1 Bits 7–0 0x0014_0000 Watchdog Control Register (WCR) S 0x0014_0002 Watchdog Modulus Register (WMR) S 0x0014_0004 Watchdog Count Register (WCNTR) S/U 0x0014_0006 Watchdog Service Register (WSR) S/U S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. Registers The watchdog timer programming model consists of these registers: • Watchdog control register (WCR), which configures watchdog timer operation • Watchdog modulus register (WMR), which determines the timer modulus reload value • Watchdog count register (WCNTR), which provides visibility to the watchdog counter value • Watchdog service register (WSR), which requires a service sequence to prevent reset 18.5.2.1 Watchdog Control Register (WCR) The 16-bit WCR configures watchdog timer operation. 15 14 13 12 11 10 9 8 3 2 1 0 WAIT DOZE HALTED EN Field — Reset 0000_0000 R/W R 7 Field 6 5 — Reset R/W Address 4 0000_1111 R R/W IPSBAR + 0x0014_0000, 0x0014_0001 Figure 18-2. Watchdog Control Register (WCR) Freescale Semiconductor 18-3 Watchdog Timer Module Bit(s) Name 15–4 — 3 WAIT Wait mode bit. Controls the function of the watchdog timer in wait mode. Once written, the WAIT bit is not affected by further writes except in halted mode. Reset sets WAIT. 1 Watchdog timer stopped in wait mode 0 Watchdog timer not affected in wait mode 2 DOZE Doze mode bit. Controls the function of the watchdog timer in doze mode. Once written, the DOZE bit is not affected by further writes except in halted mode. Reset sets DOZE. 1 Watchdog timer stopped in doze mode 0 Watchdog timer not affected in doze mode 1 HALTED Halted mode bit. Controls the function of the watchdog timer in halted mode. Once written, the HALTED bit is not affected by further writes except in halted mode. During halted mode, watchdog timer registers can be written and read normally. When halted mode is exited, timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. If a write-once register is written for the first time in halted mode, the register is still writable when halted mode is exited. 1 Watchdog timer stopped in halted mode 0 Watchdog timer not affected in halted mode Note: Changing the HALTED bit from 1 to 0 during halted mode starts the watchdog timer. Changing the HALTED bit from 0 to 1 during halted mode stops the watchdog timer. 0 EN Watchdog enable bit. Enables the watchdog timer. Once written, the EN bit is not affected by further writes except in halted mode. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state. 1 Watchdog timer enabled 0 Watchdog timer disabled 18.5.2.2 Description Reserved, should be cleared. Watchdog Modulus Register (WMR) Field 15 14 13 12 11 10 9 8 WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8 Reset 1111_1111 R/W Field Reset R/W Address R/W 7 6 5 4 3 2 1 0 WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 1111_1111 R/W IPSBAR + 0x0014_0002, 0x0014_0003 Figure 18-3. Watchdog Modulus Register (WMR) 18-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 18-3. WCR Field Descriptions Watchdog Timer Module Bit(s) Name Description 15–0 WM Watchdog modulus. Contains the modulus that is reloaded into the watchdog counter by a service sequence. Once written, the WM[15:0] field is not affected by further writes except in halted mode. Writing to WMR immediately loads the new modulus value into the watchdog counter. The new value is also used at the next and all subsequent reloads. Reading WMR returns the value in the modulus register. Reset initializes the WM[15:0] field to 0xFFFF. Note: The prescaler counter is reset anytime a new value is loaded into the watchdog counter and also during reset. 18.5.2.3 Watchdog Count Register (WCNTR) Field 15 14 13 12 11 10 9 8 WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8 Reset 1111_1111 R/W Field R 7 6 5 4 3 2 1 0 WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0 Reset 1111_1111 R/W R Address IPSBAR + x0014_0004, 0x0014_0005 Figure 18-4. Watchdog Count Register (WCNTR) Table 18-5. WCNTR Field Descriptions Bit(s) Name Description 15–0 WC Watchdog count field. Reflects the current value in the watchdog counter. Reading the 16-bit WCNTR with two 8-bit reads is not guaranteed to return a coherent value. Writing to WCNTR has no effect, and write cycles are terminated normally. 18.5.2.4 Watchdog Service Register (WSR) When the watchdog timer is enabled, writing 0x5555 and then 0xAAAA to WSR before the watchdog counter times out prevents a reset. If WSR is not serviced before the timeout, the watchdog timer sends a signal to the reset controller module that sets the RSR[WDR] bit and asserts a system reset. Both writes must occur in the order listed before the timeout, but any number of instructions can be executed between the two writes. However, writing any value other than 0x5555 or 0xAAAA to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset. Freescale Semiconductor 18-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 18-4. WMR Field Descriptions Field Field Reset R/W Address 18-6 15 14 13 12 11 10 9 8 WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8 Reset 0000_0000 R/W R/W 7 6 5 4 3 2 1 0 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 0000_0000 R/W IPSBAR + 0x0014_0006, 0x0014_0007 Figure 18-5. Watchdog Service Register (WSR) Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Watchdog Timer Module 19.1 Introduction This chapter describes the operation of the four programmable interrupt timer modules: PIT0–PIT3. 19.1.1 Overview Each PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can count down from the value written in the modulus register or it can be a free-running down-counter. 19.1.2 Block Diagram Internal Bus 16-bit PCNTRn Internal Bus Clock (fsys) Prescaler 16-bit PIT Counter COUNT = 0 PIF To Interrupt Controller Load Counter EN PRE[3:0] PIE OVW RLD DOZE DBG 16-bit PMRn Internal Bus Figure 19-1. PIT Block Diagram 19.1.3 Low-Power Mode Operation This subsection describes the operation of the PIT modules in low-power modes and debug mode of operation. Low-power modes are described in the power management module, Chapter 7, “Power Management.” Table 19-1 shows the PIT module operation in low-power modes and how it can exit from each mode. Freescale Semiconductor 19-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 19 Programmable Interrupt Timers (PIT0–PIT3) NOTE The low-power interrupt control register (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode. Table 19-1. PIT Module Operation in Low-power Modes Low-power Mode PIT Operation Wait Normal Doze Mode Exit N/A Normal if PCSRn[DOZE] cleared, Any interrupt at or above level in LPICR, exit doze stopped otherwise mode if PCSRn[DOZE] is set. Otherwise interrupt assertion has no effect. Stop Stopped Debug Normal if PCSRn[DBG] cleared, stopped otherwise No No. Any interrupt is serviced upon normal exit from debug mode In wait mode, the PIT module continues to operate as in run mode and can be configured to exit the low-power mode by generating an interrupt request. In doze mode with the PCSRn[DOZE] bit set, PIT module operation stops. In doze mode with the PCSRn[DOZE] bit cleared, doze mode does not affect PIT operation. When doze mode is exited, PIT continues operating in the state it was in prior to doze mode. In stop mode, the internal bus clock is absent and PIT module operation stops. In debug mode with the PCSRn[DBG] bit set, PIT module operation stops. In debug mode with the PCSRn[DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is exited, the PIT continues to operate in its pre-debug mode state, but any updates made in debug mode remain. 19.2 Memory Map/Register Definition This section contains a memory map (see Table 19-2) and describes the register structure for PIT0–PIT3. Table 19-2. Programmable Interrupt Timer Modules Memory Map IPSBAR Offset PIT 0 PIT 1 PIT 2 PIT 3 Register Width Access1 (bits) Reset Value Section/Page Supervisor Access Only Registers2 0x15_0000 0x16_0000 0x17_0000 0x18_0000 PIT Control and Status Register (PCSRn) 16 R/W 0x0000 19.2.1/19-3 0x15_0002 0x16_0002 0x17_0002 0x18_0002 PIT Modulus Register (PMRn) 16 R/W 0xFFFF 19.2.2/19-5 19-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Programmable Interrupt Timers (PIT0–PIT3) Programmable Interrupt Timers (PIT0–PIT3) IPSBAR Offset PIT 0 PIT 1 PIT 2 PIT 3 Width Access1 (bits) Register Reset Value Section/Page 0xFFFF 19.2.3/19-5 User/Supervisor Access Registers 0x15_0004 0x16_0004 0x17_0004 0x18_0004 1 2 PIT Count Register (PCNTRn) 16 R Accesses to reserved address locations have no effect and result in a cycle termination transfer error. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 19.2.1 PIT Control and Status Register (PCSRn) The PCSRn registers configure the corresponding timer’s operation. IPSBAR 0x15_0000 (PCSR0) Offset: 0x16_0000 (PCSR1) 0x17_0000 (PCSR2) 0x18_0000 (PCSR3) R Access: Supervisor read/write 15 14 13 12 0 0 0 0 11 10 0 0 0 0 8 0 0 7 0 PRE W Reset 9 0 0 0 6 5 4 DOZE DBG OVW 0 0 0 3 PIE 0 2 PIF w1c 0 1 0 RLD EN 0 0 Figure 19-2. PCSRn Register Freescale Semiconductor 19-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 19-2. Programmable Interrupt Timer Modules Memory Map (continued) Programmable Interrupt Timers (PIT0–PIT3) Field Description 15–12 Reserved, must be cleared. 11–8 PRE Prescaler. The read/write prescaler bits select the internal bus clock divisor to generate the PIT clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the prescaler counter. Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the prescaler counter. 7 PRE Internal Bus Clock Divisor Decimal Equivalent 0000 20 1 0001 21 2 0010 22 4 ... ... ... 1101 213 8192 1110 214 16384 1111 215 32768 Reserved, must be cleared. 6 DOZE Doze Mode Bit. The read/write DOZE bit controls the function of the PIT in doze mode. Reset clears DOZE. 0 PIT function not affected in doze mode 1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in before entering doze mode. 5 DBG Debug mode bit. Controls the function of PIT in halted/debug mode. Reset clears DBG. During debug mode, register read and write accesses function normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain. 0 PIT function not affected in debug mode 1 PIT function stopped in debug mode Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise, changing the DBG bit from 0 to 1 during debug mode stops the PIT timer. 4 OVW Overwrite. Enables writing to PMRn to immediately overwrite the value in the PIT counter. 0 Value in PMRn replaces value in PIT counter when count reaches 0x0000. 1 Writing PMRn immediately replaces value in PIT counter. 3 PIE PIT interrupt enable. This read/write bit enables PIF flag to generate interrupt requests. 0 PIF interrupt requests disabled 1 PIF interrupt requests enabled 2 PIF PIT interrupt flag. This read/write bit is set when PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF. 0 PIT count has not reached 0x0000. 1 PIT count has reached 0x0000. 19-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 19-3. PCSRn Field Descriptions Programmable Interrupt Timers (PIT0–PIT3) Field Description 1 RLD Reload bit. The read/write reload bit enables loading the value of PMRn into PIT counter when the count reaches 0x0000. 0 Counter rolls over to 0xFFFF on count of 0x0000 1 Counter reloaded from PMRn on count of 0x0000 0 EN PIT enable bit. Enables PIT operation. When PIT is disabled, counter and prescaler are held in a stopped state. This bit is read anytime, write anytime. 0 PIT disabled 1 PIT enabled 19.2.2 PIT Modulus Register (PMRn) The 16-bit read/write PMRn contains the timer modulus value loaded into the PIT counter when the count reaches 0x0000 and the PCSRn[RLD] bit is set. When the PCSRn[OVW] bit is set, PMRn is transparent, and the value written to PMRn is immediately loaded into the PIT counter. The prescaler counter is reset (0xFFFF) anytime a new value is loaded into the PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch. Reset initializes PMRn to 0xFFFF. IPSBAR 0x15_0002 (PMR0) Offset: 0x16_0002 (PMR1) 0x17_0002 (PMR2) 0x18_0002 (PMR3) 15 14 13 Access: Supervisor read/write 12 11 10 9 8 R 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 PM W Reset 7 1 1 1 1 1 1 1 1 Figure 19-3. PIT Modulus Register (PMRn) Table 19-4. PMRn Field Descriptions Field Description 15–0 PM Timer modulus. The value of this register is loaded into the PIT counter when the count reaches zero and the PCSRn[RLD] bit is set. However, if PCSRn[OVW] is set, the value written to this field is immediately loaded into the counter. Reading this field returns the value written. 19.2.3 PIT Count Register (PCNTRn) The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally. Freescale Semiconductor 19-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 19-3. PCSRn Field Descriptions (continued) Programmable Interrupt Timers (PIT0–PIT3) 15 14 13 Access: User read only 12 11 10 9 8 R 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 PC W Reset 1 1 1 1 1 1 1 1 Figure 19-4. PIT Count Register (PCNTRn) Table 19-5. PCNTRn Field Descriptions Field Description 15–0 PC Counter value. Reading this field with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally. 19.3 Functional Description This section describes the PIT functional operation. 19.3.1 Set-and-Forget Timer Operation This mode of operation is selected when the RLD bit in the PCSR register is set. When PIT counter reaches a count of 0x0000, PIF flag is set in PCSRn. The value in the modulus register loads into the counter, and the counter begins decrementing toward 0x0000. If the PCSRn[PIE] bit is set, the PIF flag issues an interrupt request to the CPU. When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000. PIT Clock Counter 0x0002 0x0001 Modulus 0x0000 0x0005 0x0005 PIF Figure 19-5. Counter Reloading from the Modulus Latch 19.3.2 Free-Running Timer Operation This mode of operation is selected when the PCSRn[RLD] bit is clear. In this mode, the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement. When the counter reaches a count of 0x0000, PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is set, PIF flag issues an interrupt request to the CPU. 19-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x15_0004 (PCNTR0) Offset: 0x16_0004 (PCNTR1) 0x17_0004 (PCNTR2) 0x18_0004 (PCNTR3) When the PCSRn[OVW] bit is set, counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000. PIT CLOCK COUNTER 0x0002 0x0001 MODULUS 0x0000 0xFFFF 0x0005 PIF Figure 19-6. Counter in Free-Running Mode 19.3.3 Timeout Specifications The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the internal bus clock period as selected by the PCSRn[PRE] bits. The PMRn[PM] bits select the timeout period. Timeout period 19.3.4 = 2 PCSRn[PRE] × (PMRn[PM] + 1) -----------------------------------------------------------------------f sys Eqn. 19-1 Interrupt Operation Table 19-6 shows the interrupt request generated by the PIT. Table 19-6. PIT Interrupt Requests Interrupt Request Flag Enable Bit Timeout PIF PIE The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. Freescale Semiconductor 19-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Programmable Interrupt Timers (PIT0–PIT3) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Programmable Interrupt Timers (PIT0–PIT3) 19-8 Freescale Semiconductor The processor has two 4-channel general purpose timer modules (GPTA and GPTB). Each consists of a 16-bit counter driven by a 7-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. Each of the four timer channels can be configured for input capture, which can capture the time of a selected transition edge, or for output compare, which can generate output waveforms and timer software delays. These functions allow simultaneous input waveform measurements and output waveform generation. Additionally, one of the channels, channel 3, can be configured as a 16-bit pulse accumulator that can operate as a simple event counter or as a gated time accumulator. The pulse accumulator uses the GPT channel 3 input/output pin in either event mode or gated time accumulation mode. 20.1 Features Features of the general-purpose timer include: • Four 16-bit input capture/output compare channels • 16-bit architecture • Programmable prescaler • Pulse widths variable from microseconds to seconds • Single 16-bit pulse accumulator • Toggle-on-overflow feature for pulse-width modulator (PWM) generation • External timer clock input (SYNCA/SYNCB) Freescale Semiconductor 20-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 20 General Purpose Timer Modules (GPTA and GPTB) General Purpose Timer Modules (GPTA and GPTB) Block Diagram CLK[1:0] System Clock SYNCx Pin PR[2:0] PACLK PACLK/256 PACLK/65536 Divide by 2 MUX Channel 3 Output Compare X Prescaler TCRE CxI GPTCNTH:GPTCNTL CxF Clear Counter 16-Bit Counter TOF Interrupt Logic TOI TE Interrupt Request Channel 0 16-Bit Comparator Edge Detect C0F IOS0 CH. 0 Capture PT0 LOGIC GPTC0H:GPTC0L 16-Bit Latch EDG0A OM:OL0 EDG0B TOV0 CH. 0 Compare GPTx0 Pin CHANNEL 1 16-Bit Comparator Edge Detect C1F IOS1 CH. 1 Capture GPTC1H:GPTC1L 16-Bit Latch EDG1A OM:OL1 EDG1B TOV1 PT1 LOGIC CH. 1 Compare GPTx1 Pin Channel 2 Channel3 16-Bit Comparator Edge Detect C3F IOS3 PT3 LOGIC GPTC3H:GPTC3L 16-Bit Latch EDG3A OM:OL3 EDG3B TOV3 PEDGE PAOVF GPTPACNTH:GPTPACNTL PACLK/256 Interrupt Request Interrupt Logic GPTx3 Pin PAIF MUX PACLK CH. 3 Compare EDGE DETECT PAE 16-Bit Counter PACLK/65536 CH.3 Capture PA Input Divide-by-64 Divide by 2 System Clock PAMOD PAOVI PAI PAOVF PAIF Figure 20-1. GPT Block Diagram 20-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.2 General Purpose Timer Modules (GPTA and GPTB) Low-Power Mode Operation This subsection describes the operation of the general purpose time module in low-power modes and halted mode of operation. Low-power modes are described in the Power Management Module. Table 3-1 shows the general purpose timer module operation in the low-power modes, and shows how this module may facilitate exit from each mode. Table 20-1. Watchdog Module Operation in Low-power Modes Low-power Mode Watchdog Operation Mode Exit Wait Normal No Doze Normal No Stop Stopped No Halted Normal No General purpose timer operation stops in stop mode. When stop mode is exited, the general purpose timer continues to operate in its pre-stop mode state. 20.4 Signal Description Table 20-2 provides an overview of the signal properties. NOTE Throughout this section, an “n” in the pin name, as in “GPTn0,” designates GPTA or GPTB. Table 20-2. Signal Properties 1 20.4.1 Pin Name GPTPORT Register Bit GPTn0 PORTTn0 GPTn1 Function Reset State Pull-up GPTn channel 0 IC/OC pin Input Active PORTTn1 GPTn channel 1 IC/OC pin Input Active GPTn2 PORTTn2 GPTn channel 2 IC/OC pin Input Active GPTn3 PORTTn3 GPTn channel 3 IC/OC or PA pin Input Active SYNCn PORTE[3:0]1 GPTn counter synchronization Input Active SYNCA is available on either PORTE3 or PORTE1; SYNCB is available on either PORTE2 or PORTE0. GPTn[2:0] The GPTn[2:0] pins are for channel 2–0 input capture and output compare functions. These pins are available for general-purpose input/output (I/O) when not configured for timer functions. 20.4.2 GPTn3 The GPTn3 pin is for channel 3 input capture and output compare functions or for the pulse accumulator input. This pin is available for general-purpose I/O when not configured for timer functions. Freescale Semiconductor 20-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.3 General Purpose Timer Modules (GPTA and GPTB) SYNCn The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with externally-timed or clocked events. A high signal on this pin clears the counter. 20.5 Memory Map and Registers See Table 20-3 for a memory map of the two GPT modules. GPTA has a base address of IPSBAR + 0x1A_0000. GPTB has a base address of IPSBAR + 0x1B_0000. NOTE Reading reserved or unimplemented locations returns zeroes. Writing to reserved or unimplemented locations has no effect. Table 20-3. GPT Modules Memory Map IPSBAR Offset 20-4 Bits 7–0 Access1 GPTA GPTB 0x1A_0000 0x1B_0000 GPT IC/OC Select Register (GPTIOS) S 0x1A_0001 0x1B_0001 GPT Compare Force Register (GPTCFORC) S 0x1A_0002 0x1B_0002 GPT Output Compare 3 Mask Register (GPTOC3M) S 0x1A_0003 0x1B_0003 GPT Output Compare 3 Data Register (GPTOC3D) S 0x1A_0004 0x1B_0004 GPT Counter Register (GPTCNT) S 0x1A_0006 0x1B_0006 GPT System Control Register 1 (GPTSCR1) S 0x1A_0007 0x1B_0007 Reserved2 — 0x1A_0008 0x1B_0008 GPT Toggle-on-Overflow Register (GPTTOV) S 0x1A_0009 0x1B_0009 GPT Control Register 1 (GPTCTL1) S 0x1A_000A 0x1B_000a Reserved(2) — 0x1A_000B 0x1B_000b GPT Control Register 2 (GPTCTL2) S 0x1A_000C 0x1B_000c GPT Interrupt Enable Register (GPTIE) S 0x1A_000D 0x1B_000d GPT System Control Register 2 (GPTSCR2) S 0x1A_000E 0x1B_000e GPT Flag Register 1 (GPTFLG1) S 0x1A_000F 0x1B_000f GPT Flag Register 2 (GPTFLG2) S 0x1A_0010 0x1B_0010 GPT Channel 0 Register High (GPTC0H) S 0x1A_0011 0x1Bb_0011 GPT Channel 0 Register Low (GPTC0L) S 0x1A_0012 0x1B_0012 GPT Channel 1 Register High (GPTC1H) S 0x1A_0013 0x1B_0013 GPT Channel 1 Register Low (GPTC1L) S 0x1A_0014 0x1B_0014 GPT Channel 2 Register High (GPTC2H) S 0x1A_0015 0x1B_0015 GPT Channel 2 Register Low (GPTC2L) S 0x1A_0016 0x1B_0016 GPT Channel 3 Register High (GPTC3H) S Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.4.3 General Purpose Timer Modules (GPTA and GPTB) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-3. GPT Modules Memory Map (continued) IPSBAR Offset 1 2 Bits 7–0 Access1 GPTA GPTB 0x1A_0017 0x1B_0017 GPT Channel 3 Register Low (GPTC3L) S 0x1A_0018 0x1B_0018 Pulse Accumulator Control Register (GPTPACTL) S 0x1A_0019 0x1B_0019 Pulse Accumulator Flag Register (GPTPAFLG) S 0x1A_001A 0x1B_001A Pulse Accumulator Counter Register High (GPTPACNTH) S 0x1A_001B 0x1B_001B Pulse Accumulator Counter Register Low (GPTPACNTL) S (2) 0x1A_001C 0x1B_001C Reserved — 0x1A_001D 0x1B_001D GPT Port Data Register (GPTPORT) S 0x1A_001E 0x1B_001E GPT Port Data Direction Register (GPTDDR) S 0x1A_001F 0x1B_001F GPT Test Register (GPTTST) S S = CPU supervisor mode access only. Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. 20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS) 7 Field Reset 4 0 IOS 0000_0000 R/W Address 3 — R/W IPSBAR + 0x401A_0000, 0x401B_0000 Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS) Table 20-4. GPTIOS Field Descriptions Bit(s) Name 7–4 — 3–0 IOS Freescale Semiconductor Description Reserved, should be cleared. I/O select. The IOS[3:0] bits enable input capture or output compare operation for the corresponding timer channels. These bits are read anytime (always read 0x00), write anytime. 1 Output compare enabled 0 Input capture enabled 20-5 General Purpose Timer Modules (GPTA and GPTB) GPT Compare Force Register (GPCFORC) 7 Field 4 3 — Reset 0 FOC 0000_0000 R/W R/W Address IPSBAR + 0x1A_00001, 0x1B_0001 Figure 20-3. GPT Input Compare Force Register (GPCFORC) Table 20-5. GPTCFORC Field Descriptions Bit(s) Name 7–4 — 3–0 FOC Description Reserved, should be cleared. Force output compare.Setting an FOC bit causes an immediate output compare on the corresponding channel. Forcing an output compare does not set the output compare flag. These bits are read anytime, write anytime. 1 Force output compare 0 No effect NOTE A successful channel 3 output compare overrides any compare on channels 2:0. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. 20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M) 7 Field Reset R/W Address 4 3 — 0 OC3M 0000_0000 R/W IPSBAR + 0x1A_0002, 0x1B_0002 Figure 20-4. GPT Output Compare 3 Mask Register (GPTOC3M) 20-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.5.2 General Purpose Timer Modules (GPTA and GPTB) Bit(s) Name 7–4 — 3–0 OC3M 20.5.4 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-6. GPTOC3M Field Descriptions Description Reserved, should be cleared. Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn pin to be an output. OC3Mn makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write anytime. 1 Corresponding PORTTn pin configured as output 0 No effect GPT Output Compare 3 Data Register (GPTOC3D) 7 Field 4 3 — Reset 0 OC3D 0000_0000 R/W R/W Address IPSBAR + 0x1A_0003, 0x1B_0003 Figure 20-5. GPT Output Compare 3 Data Register (GPTOC3D) Table 20-7. GPTOC3D Field Descriptions Bit(s) Name 7–4 — 3–0 OC3D Description Reserved, should be cleared. Output compare 3 data. When a successful channel 3 output compare occurs, these bits transfer to the PORTTn data register if the corresponding OC3Mn bits are set. These bits are read anytime, write anytime. NOTE A successful channel 3 output compare overrides any channel 2:0 compares. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. 20.5.5 GPT Counter Register (GPTCNT) 15 0 Field CNTR Reset 0000_0000_0000_0000 R/W Address Read only IPSBAR + 0x1A_0004, 0x1B_0004 Figure 20-6. GPT Counter Register (GPTCNT) Freescale Semiconductor 20-7 General Purpose Timer Modules (GPTA and GPTB) Bit(s) Name Description 15–0 CNTR Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter, such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. A write to GPTCNT may have an extra cycle on the first count because the write is not synchronized with the prescaler clock. The write occurs at least one cycle before the synchronization of the prescaler clock. These bits are read anytime. They should be written to only in test (special) mode; writing to them has no effect in normal modes. 20.5.6 GPT System Control Register 1 (GPTSCR1) 7 Field 6 GPTEN Reset 5 — 4 TFFCA 0 — 0000_0000 R/W Address 3 R/W IPSBAR + 0x1A_0006, 0x1B_0006 Figure 20-7. GPT System Control Register 1 (GPTSCR1) Table 20-9. GPTSCR1 Field Descriptions 20-8 Bit(s) Name Description 7 GPTEN Enables the general purpose timer. When the timer is disabled, only the registers are accessible. Clearing GPTEN reduces power consumption. These bits are read anytime, write anytime. 1 GPT enabled 0 GPT and GPT counter disabled 6–5 — 4 TFFCA 3–0 — Reserved, should be cleared. Timer fast flag clear all. Enables fast clearing of the main timer interrupt flag registers (GPTFLG1 and GPTFLG2) and the PA flag register (GPTPAFLG). TFFCA eliminates the software overhead of a separate clear sequence. See Figure 20-8. When TFFCA is set: • An input capture read or a write to an output compare channel clears the corresponding channel flag, CxF. • Any access of the GPT count registers (GPTCNTH/L) clears the TOF flag. • Any access of the PA counter registers (GPTPACNT) clears both the PAOVF and PAIF flags in GPTPAFLG. Writing logic 1s to the flags clears them only when TFFCA is clear. 1 Fast flag clearing 0 Normal flag clearing Reserved, should be cleared. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-8. GPTCNT Field Descriptions General Purpose Timer Modules (GPTA and GPTB) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Write GPTFLG1 Register Data Bit n CnF Clear CnF Flag TFFCA Read GPTCn Registers Write GPTCn Registers Figure 20-8. Fast Clear Flag Logic 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV) 7 6 Field 5 4 3 0 — TOV Reset 0000_0000 R/W R/W Address IPSBAR + 0x1A_0008, 0x1B_0008 Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV) Table 20-10. GPTTOV Field Descriptions Bit(s) Name 7–4 — 3–0 TOV 20.5.8 Description Reserved, should be cleared. Toggles the output compare pin on overflow for each channel. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 3 override events. These bits are read anytime, write anytime. 1 Toggle output compare pin on overflow feature enabled 0 Toggle output compare pin on overflow feature disabled GPT Control Register 1 (GPTCTL1) Field Reset R/W Address 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0000_0000 R/W IPSBAR + 0x1A_0009, 0x1B_0009 Figure 20-10. GPT Control Register 1 (GPTCTL1) Freescale Semiconductor 20-9 General Purpose Timer Modules (GPTA and GPTB) Bit(s) Name Description 7–0 OMx/OLx Output mode/output level. Selects the output action to be taken as a result of a successful output compare on each channel. When either OMn or OLn is set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit. These bits are read anytime, write anytime. 00 GPT disconnected from output pin logic 01 Toggle OCn output line 10 Clear OCn output line 11 Set OCn line Note: Channel 3 shares a pin with the pulse accumulator input pin. To use the PAI input, clear both the OM3 and OL3 bits and clear the OC3M3 bit in the output compare 3 mask register. 20.5.9 GPT Control Register 2 (GPTCTL2) 7 Field 6 EDG3B 5 4 3 2 1 EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B Reset 0 EDG0A 0000_0000 R/W R/W Address IPSBAR + 0x1A_000B, 0x1B_000B Figure 20-11. GPT Control Register 2 (GPTCTL2) Table 20-12. GPTLCTL2 Field Descriptions Bit(s) Name 7–0 EDGn[B:A] Description Input capture edge control. Configures the input capture edge detector circuits for each channel. These bits are read anytime, write anytime. 00 Input capture disabled 01 Input capture on rising edges only 10 Input capture on falling edges only 11 Input capture on any edge (rising or falling) 20.5.10 GPT Interrupt Enable Register (GPTIE) 7 Field Reset R/W Address 6 5 4 3 — 0 CI 0000_0000 R/W IPSBAR + 0x1A_000C, 0x1B_000C Figure 20-12. GPT Interrupt Enable Register (GPTIE) 20-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-11. GPTCL1 Field Descriptions General Purpose Timer Modules (GPTA and GPTB) Bit(s) Name 7–4 — Reserved, should be cleared. 3–0 CnI Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each channel. These bits are read anytime, write anytime. 1 Corresponding channel interrupt requests enabled 0 Corresponding channel interrupt requests disabled Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-13. GPTIE Field Descriptions Description 20.5.11 GPT System Control Register 2 (GPTSCR2) Field Reset 7 6 5 4 3 TOI — PUPT RDPT TCRE 0 PR 0000_0000 R/W Address 2 R/W IPSBAR + 0x1A_000D, 0x1B_000D Figure 20-13. GPT System Control Register 2 (GPTSCR2) Table 20-14. GPTSCR2 Field Descriptions Bit(s) Name 7 TOI 6 — 5 PUPT Enables pull-up resistors on the GPT ports when the ports are configured as inputs. 1 Pull-up resistors enabled 0 Pull-up resistors disabled 4 RDPT GPT drive reduction. Reduces the output driver size. 1 Output drive reduction enabled 0 Output drive reduction disabled 3 TCRE Enables a counter reset after a channel 3 compare. 1 Counter reset enabled 0 Counter reset disabled Note: When the GPT channel 3 registers contain 0x0000 and TCRE is set, the GPT counter registers remain at 0x0000 all the time. When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000. Freescale Semiconductor Description Enables timer overflow interrupt requests. 1 Overflow interrupt requests enabled 0 Overflow interrupt requests disabled Reserved, should be cleared. 20-11 General Purpose Timer Modules (GPTA and GPTB) Bit(s) Name Description 2–0 PRn Prescaler bits. Select the prescaler divisor for the GPT counter. 000 Prescaler divisor 1 001 Prescaler divisor 2 010 Prescaler divisor 4 011 Prescaler divisor 8 100 Prescaler divisor 16 101 Prescaler divisor 32 110 Prescaler divisor 64 111 Prescaler divisor 128 Note: The newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled clock when the clock count transitions to 0x0000.) 20.5.12 GPT Flag Register 1 (GPTFLG1) 7 6 Field 5 4 3 — 0 CF Reset 0000_0000 R/W R/W Address IPSBAR + 0x1A_000E, 0x1B_000E Figure 20-14. GPT Flag Register 1 (GPTFLG1) Table 20-15. GPTFLG1 Field Descriptions Bit(s) Name 7–4 — 3–0 CnF Description Reserved, should be cleared. Channel flags. A channel flag is set when an input capture or output compare event occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0 has no effect). Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read or an output compare write clears the corresponding channel flag. When a channel flag is set, it does not inhibit subsequent output compares or input captures. 20.5.13 GPT Flag Register 2 (GPTFLG2) 7 Field Reset R/W Address 6 5 4 3 TOF 0 — 0000_0000 R/W IPSBAR + 0x1A_000F, 0x1B_000F Figure 20-15. GPT Flag Register 2 (GPTFLG2) 20-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-14. GPTSCR2 Field Descriptions (continued) General Purpose Timer Modules (GPTA and GPTB) Bit(s) Name Description 7 TOF Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If the TOI bit in GPTSCR2 is also set, TOF generates an interrupt request. This bit is read anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect). 1 Timer overflow 0 No timer overflow Note: When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000. When TOF is set, it does not inhibit subsequent overflow events. 6–0 — Reserved, should be cleared. Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. 20.5.14 GPT Channel Registers (GPTCn) 15 0 Field CCNT Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1A_0010, 0x1A_0012, 0x1A_0014, 0x1A_0016, 0x1B_0010, 0x1B_0012, 0x1B_0014, 0x1B_0016 Figure 20-16. GPT Channel[0:3] Register (GPTCn) Table 20-17. GPTCn Field Descriptions Bit(s) Name Description 15–0 CCNT When a channel is configured for input capture (IOSn = 0), the GPT channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin. When a channel is configured for output compare (IOSn = 1), the GPT channel registers contain the output compare value. To ensure coherent reading of the GPT counter, such that a timer rollover does not occur between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime (for the output compare channel); writing to the input capture channel has no effect. Freescale Semiconductor 20-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-16. GPTFLG2 Field Descriptions General Purpose Timer Modules (GPTA and GPTB) Field Reset 7 6 — PAE 5 4 3 PAMOD PEDGE 0 CLK PAOVI PAI 0000_0000 R/W R/W Address IPSBAR + 0x1A_0018, 0x1B_0018 Figure 20-17. Pulse Accumulator Control Register (GPTPACTL) Table 20-18. GPTPACTL Field Descriptions 20-14 Bit(s) Name Description 7 — 6 PAE 5 PAMOD Pulse accumulator mode. Selects event counter mode or gated time accumulation mode. 1 Gated time accumulation mode 0 Event counter mode 4 PEDGE Pulse accumulator edge. Selects falling or rising edges on the PAI pin to increment the counter. In event counter mode (PAMOD = 0): 1 Rising PAI edge increments counter 0 Falling PAI edge increments counter In gated time accumulation mode (PAMOD = 1): 1 Low PAI input enables divide-by-64 clock to pulse accumulator and trailing rising edge on PAI sets PAIF flag. 0 High PAI input enables divide-by-64 clock to pulse accumulator and trailing falling edge on PAI sets PAIF flag. Note: The timer prescaler generates the divide-by-64 clock. If the timer is not active, there is no divide-by-64 clock. To operate in gated time accumulation mode: 1. Apply logic 0 to RSTI pin. 2. Initialize registers for pulse accumulator mode test. 3. Apply appropriate level to PAI pin. 4. Enable GPT. 3–2 CLK Select the GPT counter input clock. Changing the CLK bits causes an immediate change in the GPT counter clock input. 00 GPT prescaler clock (When PAE = 0, the GPT prescaler clock is always the GPT counter clock.) 01 PACLK 10 PACLK/256 11 PACLK/65536 Reserved, should be cleared. Enables the pulse accumulator. 1 Pulse accumulator enabled 0 Pulse accumulator disabled Note: The pulse accumulator can operate in event mode even when the GPT enable bit, GPTEN, is clear. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.5.15 Pulse Accumulator Control Register (GPTPACTL) General Purpose Timer Modules (GPTA and GPTB) Bit(s) Name 1 PAOVI 0 PAI Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-18. GPTPACTL Field Descriptions (continued) Description Pulse accumulator overflow interrupt enable. Enables the PAOVF flag to generate interrupt requests. 1 PAOVF interrupt requests enabled 0 PAOVF interrupt requests disabled Pulse accumulator input interrupt enable. Enables the PAIF flag to generate interrupt requests. 1 PAIF interrupt requests enabled 0 PAIF interrupt requests disabled 20.5.16 Pulse Accumulator Flag Register (GPTPAFLG) 7 Field 2 — Reset 1 0 PAOVF PAIF 0000_0000 R/W R/W Address IPSBAR + 0x1A_0019, 0x1B_0019 Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG) Table 20-19. GPTPAFLG Field Descriptions Bit(s) Name Description 7–2 — 1 PAOVF Pulse accumulator overflow flag. Set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the GPTPACTL[PAOVI] bit is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to it. This bit is read anytime, write anytime. (Writing 1 clears the flag; writing 0 has no effect.) 1 Pulse accumulator overflow 0 No pulse accumulator overflow 0 PAIF Pulse accumulator input flag. Set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the PAI bit in GPTPACTL is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to it. 1 Active PAI input 0 No active PAI input Reserved, should be cleared. NOTE When the fast flag clear all enable bit, GPTSCR1[TFFCA], is set, any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG. Freescale Semiconductor 20-15 General Purpose Timer Modules (GPTA and GPTB) 15 0 Field PACNT Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1A_001A, 0x1B_001B Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT) Table 20-20. GPTPACR Field Descriptions Bit(s) Name Description 15–0 PACNT Contains the number of active input edges on the PAI pin since the last reset. Note: Reading the pulse accumulator counter registers immediately after an active edge on the PAI pin may miss the last count since the input first has to be synchronized with the bus clock. To ensure coherent reading of the PA counter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime. 20.5.18 GPT Port Data Register (GPTPORT) 7 Field Reset 6 5 4 — 0 PORTT 0000_0000 R/W Address 3 R/W IPSBAR + 0x1A_001D, 0x1B_001D Figure 20-20. GPT Port Data Register (GPTPORT) Table 20-21. GPTPORT Field Descriptions 20-16 Bit(s) Name 7–4 — 3–0 PORTT Description Reserved, should be cleared. GPT port input capture/output compare data. Data written to GPTPORT is buffered and drives the pins only when they are configured as general-purpose outputs. Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1) reads the latched value. Writing to a pin configured as a GPT output does not change the pin state. These bits are read anytime (read pin state when corresponding PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write anytime. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.5.17 Pulse Accumulator Counter Register (GPTPACNT) General Purpose Timer Modules (GPTA and GPTB) 7 6 5 4 3 0 Field — DDRT GPT Function — IC/OC Pulse Accumulator Function — PAI Reset — 0000_0000 R/W R/W Address IPSBAR + 0x1A_001E, 0x1B_001E Figure 20-21. GPT Port Data Direction Register (GPTDDR) Table 20-22. GPTDDR Field Descriptions Bit(s) Name 7–4 — 3–0 DDRT 20.6 Description Reserved, should be cleared. Control the port logic of PORTTn. Reset clears the PORTTn data direction register, configuring all GPT port pins as inputs. These bits are read anytime, write anytime. 1 Corresponding pin configured as output 0 Corresponding pin configured as input Functional Description The General Purpose Timer (GPT) module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator. 20.6.1 Prescaler The prescaler divides the module clock by 1, 2, 4, 8, 16, 32, 64, or 128. The GPTSCR2[PR] bits select the prescaler divisor. 20.6.2 Input Capture Clearing an I/O select bit, IOSn, configures channel n as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the GPT counter into the GPT channel registers, GPTCn. The minimum pulse width for the input capture input is greater than two module clocks. The input capture function does not force data direction. The GPT port data direction register controls the data direction of an input capture pin. Pin conditions such as rising or falling edges can trigger an input capture only on a pin configured as an input. An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests. Freescale Semiconductor 20-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.5.19 GPT Port Data Direction Register (GPTDDR) General Purpose Timer Modules (GPTA and GPTB) Output Compare Setting an I/O select bit, IOSn, configures channel n as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the GPT counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests. The output mode and level bits, OMn and OLn, select, set, clear, or toggle on output compare. Clearing both OMn and OLn disconnects the pin from the output logic. Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output compare does not set the channel flag. A successful output compare on channel 3 overrides output compares on all other output compare channels. A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port data register, depending on the output compare 3 mask register. The output compare 3 mask register masks the bits in the output compare 3 data register. The GPT counter reset enable bit, TCRE, enables channel 3 output compares to reset the GPT counter. A channel 3 output compare can reset the GPT counter even if the OC3/PAI pin is being used as the pulse accumulator input. An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. Writing to the PORTTn bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. 20.6.4 Pulse Accumulator The pulse accumulator (PA) is a 16-bit counter that can operate in two modes: 1. Event counter mode: counts edges of selected polarity on the pulse accumulator input pin, PAI 2. Gated time accumulation mode: counts pulses from a divide-by-64 clock The PA mode bit, PAMOD, selects the mode of operation. The minimum pulse width for the PAI input is greater than two module clocks. 20.6.5 Event Counter Mode Clearing the PAMOD bit configures the PA for event counter operation. An active edge on the PAI pin increments the PA. The PA edge bit, PEDGE, selects falling edges or rising edges to increment the PA. An active edge on the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to generate interrupt requests. NOTE The PAI input and GPT channel 3 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 3 output mode and output level bits, OM3 and OL3. Also clear the channel 3 output compare 3 mask bit, OC3M3. The PA counter register, GPTPACNT, reflects the number of active input edges on the PAI pin since the last reset. 20-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 20.6.3 The PA overflow flag, PAOVF, is set when the PA rolls over from 0xFFFF to 0x0000. The PA overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. NOTE The PA can operate in event counter mode even when the GPT enable bit, GPTEN, is clear. 20.6.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the PAI pin enables a divide-by-64 clock to drive the PA. The PA edge bit, PEDGE, selects low levels or high levels to enable the divide-by-64 clock. The trailing edge of the active level at the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to generate interrupt requests. NOTE The PAI input and GPT channel 3 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 3 output mode and output level bits, OM3 and OL3. Also clear the channel 3 output compare mask bit, OC3M3. The PA counter register, GPTPACNT, reflects the number of pulses from the divide-by-64 clock since the last reset. NOTE The GPT prescaler generates the divide-by-64 clock. If the timer is not active, there is no divide-by-64 clock. PULSE ACCUMULATOR PAD CHANNEL 3 OUTPUT COMPARE OM3 OL3 OC3M3 Figure 20-22. Channel 3 Output Compare/Pulse Accumulator Logic 20.6.7 General-Purpose I/O Ports An I/O pin used by the timer defaults to general-purpose I/O unless an internal function which uses that pin is enabled. The PORTTn pins can be configured for either an input capture function or an output compare function. The IOSn bits in the GPT IC/OC select register configure the PORTTn pins as either input capture or output compare pins. Freescale Semiconductor 20-19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 General Purpose Timer Modules (GPTA and GPTB) The PORTTn data direction register controls the data direction of an input capture pin. External pin conditions trigger input captures on input capture pins configured as inputs. To configure a pin for input capture: 1. Clear the pin’s IOS bit in GPTIOS. 2. Clear the pin’s DDR bit in PORTTnDDR. 3. Write to GPTCTL2 to select the input edge to detect. PORTTnDDR does not affect the data direction of an output compare pin. The output compare function overrides the data direction register but does not affect the state of the data direction register. To configure a pin for output compare: 1. Set the pin’s IOS bit in GPTIOS. 2. Write the output compare value to GPTCn. 3. Clear the pin’s DDR bit in PORTTnDDR. 4. Write to the OMn/OLn bits in GPTCTL1 to select the output action. Table 20-23 shows how various timer settings affect pin functionality. Table 20-23. GPT Settings and Pin Functions GPTE N DDR1 GPTIOS EDGx [B:A] OMx/ OLx2 OC3Mx 3 Pin Data Dir. Pin Driven by Pin Function Comments 0 0 X4 X X X In Ext. Digital input GPT disabled by GPTEN = 0 0 1 X X X X Out Data reg. Digital output GPT disabled by GPTEN = 0 1 0 0 (IC) 0 (IC disable d) X 0 In Ext. Digital input Input capture disabled by EDGn setting 1 1 0 0 X 0 Out Data reg. Digital output Input capture disabled by EDGn setting 1 0 0 <> 0 X 0 In Ext. IC and digital input Normal settings for input capture 1 1 0 <> 0 X 0 Out Data reg. Digital output Input capture of data driven to output pin by CPU 1 0 0 <> 0 X 1 In Ext. IC and digital input OC3M setting has no effect because IOS = 0 1 1 0 <> 0 X 1 Out Data reg. Digital output OC3M setting has no effect because IOS = 0; input capture of data driven to output pin by CPU 1 0 1 (OC) X(3) 05 0 In Ext. Digital input Output compare takes place but does not affect the pin because of the OMn/OLn setting 1 1 1 X 0 0 Out Data reg. Digital output Output compare takes place but does not affect the pin because of the OMn/OLn setting 1 0 1 X <> 0 0 Out OC action Output compare Pin readable only if DDR = 0(5) 1 1 1 X <> 0 0 Out OC action Output compare Pin driven by OC action(5) 20-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 General Purpose Timer Modules (GPTA and GPTB) General Purpose Timer Modules (GPTA and GPTB) 1 2 3 4 5 6 1 0 1 X X 1 Out OC action/ OC3Dn 1 1 1 X X 1 Out OC action/ OC3Dn Output compare Pin readable only if DDR = 06 (ch 3) Output compare/ OC3Dn (ch 3) Pin driven by channel OC action and OC3Dn via channel 3 OC(6) When DDR set the pin as input (0), reading the data register will return the state of the pin. When DDR set the pin as output (1), reading the data register will return the content of the data latch. Pin conditions such as rising or falling edges can trigger an input capture on a pin configured as an input. OMn/OLn bit pairs select the output action to be taken as a result of a successful output compare. When either OMn or OLn is set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit. Setting an OC3M bit configures the corresponding PORTTn pin to be output. OC3Mn makes the PORTTn pin an output regardless of the data direction bit when the pin is configured for output compare (IOSn = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. X = Don’t care An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. Enabling output compare disables data register drive of the pin. A successful output compare on channel 3 causes an output value determined by OC3Dn value to temporarily override the output compare pin state of any other output compare channel.The next OC action for the specific channel will still be output to the pin. A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port data register, depending on the output compare 3 mask register. 20.7 Reset Reset initializes the GPT registers to a known startup state as described in Section 20.5, “Memory Map and Registers.” 20.8 Interrupts Table 20-24 lists the interrupt requests generated by the timer. Table 20-24. GPT Interrupt Requests Interrupt Request Flag Enable Bit Channel 3 IC/OC C3F C3I Channel 2 IC/OC C2F C2I Channel 1 IC/OC C1F C1I Channel 0 IC/OC C0F C0I PAOVF PAOVI PA input PAIF PAI Timer overflow TOF TOI PA overflow 20.8.1 GPT Channel Interrupts (CnF) A channel flag is set when an input capture or output compare event occurs. Clear a channel flag by writing a 1 to it. Freescale Semiconductor 20-21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 20-23. GPT Settings and Pin Functions (continued) NOTE When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read or an output compare write clears the corresponding channel flag. When a channel flag is set, it does not inhibit subsequent output compares or input captures 20.8.2 Pulse Accumulator Overflow (PAOVF) PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVI bit in GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to this flag. NOTE When the fast flag clear all enable bit, GPTSCR1[TFFCA], is set, any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG. 20.8.3 Pulse Accumulator Input (PAIF) PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the PAI bit in GPTPACTL is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to this flag. NOTE When the fast flag clear all enable bit, GPTSCR1[TFFCA], is set, any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG. 20.8.4 Timer Overflow (TOF) TOF is set when the GPT counter rolls over from 0xFFFF to 0x0000. If the GPTSCR2[TOI] bit is also set, TOF generates an interrupt request. Clear TOF by writing a 1 to this flag. 20-22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 General Purpose Timer Modules (GPTA and GPTB) General Purpose Timer Modules (GPTA and GPTB) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NOTE When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000. When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. Freescale Semiconductor 20-23 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 General Purpose Timer Modules (GPTA and GPTB) 20-24 Freescale Semiconductor 21.1 Introduction This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or DMA triggers. Additionally, programming examples are included. NOTE The designation n appears throughout this section to refer to registers or signals associated with one of the four identical timer modules: DTIM0, DTIM1, DTIM2, or DTIM3. 21.1.1 Overview Each DMA timer module has a separate register set for configuration and control. The timers can be configured to operate from the internal bus clock or from an external clocking source using the DTINn signal. If the internal bus clock is selected, it can be divided by 16 or 1. The selected clock source is routed to an 8-bit programmable prescaler that clocks the actual DMA timer counter register (DTCNn). Using the DTMRn, DTXMRn, DTCRn, and DTRRn registers, the DMA timer may be configured to assert an output signal, generate an interrupt, or request a DMA transfer on a particular event. NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 26, “General Purpose I/O Module”) prior to configuring the DMA Timers. Freescale Semiconductor 21-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 21 DMA Timers (DTIM0–DTIM3) DMA Timers (DTIM0–DTIM3) Internal Bus to/from DMA Timer Registers DMA Timer 0 15 Internal Bus Clock (÷1 or ÷16) DMA Timer Mode Register (DTMRn) Prescaler Mode Bits DMA Timer Clock Generator DTINn 7 0 DMA Timer Extended Mode Register (DTXMRn) Divider clock 31 Capture Detection 0 DMA Timer Counter Register (DTCNn) (contains incrementing value) 31 0 DMA Timer Capture Register (DTCRn) (latches DTCN value when triggered byDTINn) DTOUTn Interrupt Request DMA Request 31 0 DMA Timer Reference Register (DTRRn) (reference value for comparison with DTCN) 0 7 DMA Timer Event Register (DTERn) (indicates capture or when DTCN = DTRRn) Figure 21-1. DMA Timer Block Diagram 21.1.2 Features Each DMA timer module has: • Maximum timeout period of 219,902 seconds at 80 MHz (~61 hours) • 12.5-ns resolution at 80 MHz • Programmable sources for the clock input, including external clock • Programmable prescaler • Input-capture capability with programmable trigger edge on input pin • Programmable mode for the output pin on reference compare • Free run and restart modes • Programmable interrupt or DMA request on input capture or reference-compare 21-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Figure 21-1 is a block diagram of one of the four identical timer modules. DMA Timers (DTIM0–DTIM3) Memory Map/Register Definition The timer module registers, shown in Table 21-1, can be modified at any time. Table 21-1. DMA Timer Module Memory Map IPSBAR Offset DMA Timer 0 DMA Timer 1 DMA Timer 2 DMA Timer 3 Width Access (bits) Register Reset Value Section/Page 0x00_0400 0x00_0440 0x00_0480 0x00_04C0 DMA Timer n Mode Register (DTMRn) 16 R/W 0x0000 21.2.1/21-3 0x00_0402 0x00_0442 0x00_0482 0x00_04C2 DMA Timer n Extended Mode Register (DTXMRn) 8 R/W 0x00 21.2.2/21-5 0x00_0403 0x00_0443 0x00_0483 0x00_04C3 DMA Timer n Event Register (DTERn) 8 R/W 0x00 21.2.3/21-5 0x00_0404 0x00_0444 0x00_0484 0x00_04C4 DMA Timer n Reference Register (DTRRn) 32 R/W 0xFFFF_FFFF 21.2.4/21-7 0x00_0408 0x00_0448 0x00_0488 0x00_04C8 DMA Timer n Capture Register (DTCRn) 32 R/W 0x0000_0000 21.2.5/21-7 0x00_040C 0x00_044C 0x00_048C 0x00_04CC DMA Timer n Counter Register (DTCNn) 32 R 0x0000_0000 21.2.6/21-8 21.2.1 DMA Timer Mode Registers (DTMRn) The DTMRn registers program the prescaler and various timer modes. IPSBAR 0x00_0400 (DTMR0) Offset: 0x00_0440 (DTMR1) 0x00_0480 (DTMR2) 0x00_04C0 (DTMR3) 15 14 13 Access: User read/write 12 R 10 9 8 7 PS W Reset 11 0 0 0 0 6 CE 0 0 0 0 0 5 OM 0 0 4 3 2 ORRI FRR 0 0 1 CLK 0 0 RST 0 0 Figure 21-2. DTMRn Registers Freescale Semiconductor 21-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 21.2 DMA Timers (DTIM0–DTIM3) Field Description 15–8 PS Prescaler value. Divides the clock input (internal bus clock/(16 or 1) or clock on DTINn) 0x00 1 ... 0xFF 256 7–6 CE Capture edge. 00 Disable capture event output. Timer in reference mode. 01 Capture on rising edge only 10 Capture on falling edge only 11 Capture on any edge 5 OM Output mode. 0 Active-low pulse for one internal bus clock cycle (12.5-ns resolution at 80 MHz) 1 Toggle output. 4 ORRI Output reference request, interrupt enable. If ORRI is set when DTERn[REF] is set, a DMA request or an interrupt occurs, depending on the value of DTXMRn[DMAEN] (DMA request if set, interrupt if cleared). 0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture function). 1 Enable DMA request or interrupt upon reaching the reference value. 3 FRR Free run/restart 0 Free run. Timer count continues incrementing after reaching the reference value. 1 Restart. Timer count is reset immediately after reaching the reference value. 2–1 CLK Input clock source for the timer. Avoid setting CLK when RST is already set. Doing so causes CLK to zero (stop counting). 00 Stop count 01 Internal bus clock divided by 1 10 Internal bus clock divided by 16. This clock source is not synchronized with the timer; therefore, successive time-outs may vary slightly. 11 DTINn pin (falling edge) 0 RST Reset timer. Performs a software timer reset similar to an external reset, although other register values can be written while RST is cleared. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless the timer is enabled. 0 Reset timer (software reset) 1 Enable timer 21-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 21-2. DTMRn Field Descriptions DMA Timers (DTIM0–DTIM3) DMA Timer Extended Mode Registers (DTXMRn) The DTXMRn registers program DMA request and increment modes for the timers. IPSBAR 0x00_0402 (DTXMR0) Offset: 0x00_0442 (DTXMR1) 0x00_0482 (DTXMR2) 0x00_04C2 (DTXMR3) 7 R Access: User read/write 6 5 4 3 2 1 0 0 0 0 0 0 DMAEN 0 MODE16 W Reset: 0 0 0 0 0 0 0 0 Figure 21-3. DTXMRn Registers Table 21-3. DTXMRn Field Descriptions Field Description 7 DMA request. Enables DMA request output on counter reference match or capture edge event. DMAEN 0 DMA request disabled 1 DMA request enabled 6–1 Reserved, must be cleared. 0 Selects the increment mode for the timer. Setting MODE16 is intended to exercise the upper bits of the 32-bit timer MODE16 in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s upper 16 bits mirror its lower 16 bits. All 32 bits of the counter remain compared to the reference value. 0 Increment timer by 1 1 Increment timer by 65,537 21.2.3 DMA Timer Event Registers (DTERn) DTERn, shown in Figure 21-4, reports capture or reference events by setting DTERn[CAP] or DTERn[REF]. This reporting happens regardless of the corresponding DMA request or interrupt enable values, DTXMRn[DMAEN] and DTMRn[ORRI,CE]. Writing a 1 to DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value); both bits can be cleared at the same time. If configured to generate an interrupt request, clear REF and CAP early in the interrupt service routine so the timer module can negate the interrupt request signal to the interrupt controller. If configured to generate a DMA request, processing of the DMA data transfer automatically clears the REF and CAP flags via the internal DMA ACK signal. Freescale Semiconductor 21-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 21.2.2 DMA Timers (DTIM0–DTIM3) R Access: User read/write 7 6 5 4 3 2 1 0 0 0 0 0 0 0 REF CAP w1c w1c 0 0 W Reset: 0 0 0 0 0 0 Figure 21-4. DTERn Registers Table 21-4. DTERn Field Descriptions Field Description 7–2 Reserved, must be cleared. 1 REF Output reference event. The counter value (DTCNn) equals DTRRn. Writing a 1 to REF clears the event condition. Writing a 0 has no effect. 0 CAP 21-6 REF DTMRn[ORRI] DTXMRn[DMAEN] 0 X X No event 1 0 0 No request asserted 1 0 1 No request asserted 1 1 0 Interrupt request asserted 1 1 1 DMA request asserted Capture event. The counter value has been latched into DTCRn. Writing a 1 to CAP clears the event condition. Writing a 0 has no effect. CAP DTMRn[CE] DTXMRn [DMAEN] 0 XX X No event 1 00 0 Disable capture event output 1 00 1 Disable capture event output 1 01 0 Capture on rising edge and trigger interrupt 1 01 1 Capture on rising edge and trigger DMA 1 10 0 Capture on falling edge and trigger interrupt 1 10 1 Capture on falling edge and trigger DMA 1 11 0 Capture on any edge and trigger interrupt 1 11 1 Capture on any edge and trigger DMA Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x00_0403 (DTER0) Offset: 0x00_0443 (DTER1) 0x00_0483 (DTER2) 0x00_04C3 (DTER3) DMA Timers (DTIM0–DTIM3) DMA Timer Reference Registers (DTRRn) As part of the output-compare function, each DTRRn contains the reference value compared with the respective free-running timer counter (DTCNn). The reference value is matched when DTCNn equals DTRRn. The prescaler indicates that DTCNn should be incremented again. Therefore, the reference register is matched after DTRRn + 1 time intervals. IPSBAR 0x00_0404 (DTRR0) Offset: 0x00_0444 (DTRR1) 0x00_0484 (DTRR2) 0x00_04C4 (DTRR3) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 REF (32-bit reference value) W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 21-5. DTRRn Registers Table 21-5. DTRRn Field Descriptions Field Description 31–0 REF Reference value compared with the respective free-running timer counter (DTCNn) as part of the output-compare function. 21.2.5 DMA Timer Capture Registers (DTCRn) Each DTCRn latches the corresponding DTCNn value during a capture operation when an edge occurs on DTINn, as programmed in DTMRn. The internal bus clock is assumed to be the clock source. DTINn cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation results if DTINn is set as the clock source when the input capture mode is used. Access: User read-only IPSBAR 0x00_0408 (DTCR0) Offset: 0x00_0448 (DTCR1) 0x00_0488 (DTCR2) 0x00_04C8 (DTCR3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 CAP (32-bit capture counter value) W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-6. DTCRn Registers Table 21-6. DTCRn Field Descriptions Field 31–0 CAP Description Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTINn, as programmed in DTMRn. Freescale Semiconductor 21-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 21.2.4 DMA Timers (DTIM0–DTIM3) DMA Timer Counters (DTCNn) The current value of the 32-bit timer counter can be read at anytime without affecting counting. Writes to DTCNn clear the timer counter. The timer counter increments on the clock source rising edge (internal bus clock divided by 1, internal bus clock divided by 16, or DTINn). IPSBAR 0x00_040C (DTCN0) Offset: 0x00_044C (DTCN1) 0x00_048C (DTCN2) 0x00_04CC (DTCN3) Access: User read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 CNT (32-bit timer counter value count) W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-7. DMA Timer Counters (DTCNn) Table 21-7. DTCNn Field Descriptions Field 31–0 CNT 21.3 21.3.1 Description Timer counter. Can be read at anytime without affecting counting and any write to this field clears it. Functional Description Prescaler The prescaler clock input is selected from the internal bus clock (fsys divided by 1 or 16) or from the corresponding timer input, DTINn. DTINn is synchronized to the internal bus clock, and the synchronization delay is between two and three internal bus clocks. The corresponding DTMRn[CLK] selects the clock input source. A programmable prescaler divides the clock input by values from 1 to 256. The prescaler output is an input to the 32-bit counter, DTCNn. 21.3.2 Capture Mode Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when the corresponding input capture edge detector senses a defined DTINn transition. The capture edge bits (DTMRn[CE]) select the type of transition that triggers the capture and sets the timer event register capture event bit, DTERn[CAP]. If DTERn[CAP] and DTXMRn[DMAEN] are set, a DMA request is asserted. If DTERn[CAP] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted. 21.3.3 Reference Compare Each DMA timer can be configured to count up to a reference value. If the reference value is met, DTERn[REF] is set. • If DTMRn[ORRI] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted. • If DTMRn[ORRI] and DTXMRn[DMAEN] are set, a DMA request is asserted. 21-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 21.2.6 DMA Timers (DTIM0–DTIM3) 21.3.4 Output Mode When a timer reaches the reference value selected by DTRR, it can send an output signal on DTOUTn. DTOUTn can be an active-low pulse or a toggle of the current output, as selected by the DTMRn[OM] bit. 21.4 Initialization/Application Information The general-purpose timer modules typically, but not necessarily, follow this program order: • The DTMRn and DTXMRn registers are configured for the desired function and behavior. — Count and compare to a reference value stored in the DTRRn register — Capture the timer value on an edge detected on DTINn — Configure DTOUTn output mode — Increment counter by 1 or by 65,537 (16-bit mode) — Enable/disable interrupt or DMA request on counter reference match or capture edge • The DTMRn[CLK] register is configured to select the clock source to be routed to the prescaler. — Internal bus clock (can be divided by 1 or 16) — DTINn, the maximum value of DTINn is 1/5 of the internal bus clock, as described in the device’s electrical characteristics NOTE DTINn may not be configured as a clock source when the timer capture mode is selected or indeterminate operation results. • • • The 8-bit DTMRn[PS] prescaler value is set. Using DTMRn[RST], counter is cleared and started. Timer events are managed with an interrupt service routine, a DMA request, or by a software polling mechanism. 21.4.1 Code Example The following code provides an example of how to initialize and use DMA Timer0 for counting time-out periods. DTMR0 DTMR1 DTRR0 DTRR1 DTCR0 DTCR1 DTCN0 DTCN1 DTER0 DTER1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU IPSBARx+0x400 IPSBARx+0x440 IPSBARx+0x404 IPSBARx+0x444 IPSBARx+0x408 IPSBARx+0x448 IPSBARx+0x40C IPSBARx+0x44C IPSBARx+0x403 IPSBARx+0x443 ;Timer0 ;Timer1 ;Timer0 ;Timer1 ;Timer0 ;Timer1 ;Timer0 ;Timer1 ;Timer0 ;Timer1 mode register mode register reference register reference register capture register capture register counter register counter register event register event register * TMR0 is defined as: * *[PS] = 0xFF, divide clock by 256 Freescale Semiconductor 21-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 If the free run/restart bit (DTMRn[FRR]) is set, a new count starts. If it is clear, the timer keeps running. *[CE] = 00 *[OM] = 0 *[ORRI] = 0, *[FRR] = 1, *[CLK] = 10, *[RST] = 0, disable capture event output output=active-low pulse disable ref. match output restart mode enabled internal bus clock/16 timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #0xAFAF,DO ;set the timer0 reference to be move.l #D0,TRR0 ;defined as 0xAFAF The simple example below uses Timer0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached. timer0_ex clr.l DO clr.l D1 clr.l D2 move.l #0x0000,D0 move.l D0,TCN0 move.b #0x03,D0 move.b D0,TER0 move.w TMR0,D0 bset #0,D0 move.w D0,TMR0 ;reset the counter to 0x0000 ;writing ones to TER0[REF,CAP] ;clears the event flags ;save the contents of TMR0 while setting ;the 0 bit. This enables timer 0 and starts counting ;load the value back into the register, setting TMR0[RST] T0_LOOP move.b TER0,D1 btst #1,D1 beq T0_LOOP ;load TER0 and see if ;TER0[REF] has been set addi.l #1,D2 cmp.l #5,D2 beq T0_FINISH ;Increment D2 ;Did D2 reach 5? (i.e. timer ref has timed) ;If so, end timer0 example. Otherwise jump back. move.b #0x02,D0 move.b D0,TER0 jmp T0_LOOP ;writing one to TER0[REF] clears the event flag T0_FINISH HALT 21.4.2 ;End processing. Example is finished Calculating Time-Out Values Equation 21-1 determines time-out periods for various reference values: Timeout period = ( 1 ⁄ clock frequency ) × ( 1 or 16 ) × ( DTMRn[PS] + 1 ) × ( DTRRn[REF] + 1 ) Eqn. 21-1 When calculating time-out periods, add one to the prescaler to simplify calculating, because DTMRn[PS] equal to 0x00 yields a prescaler of one, and DTMRn[PS] equal to 0xFF yields a prescaler of 256. 21-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 DMA Timers (DTIM0–DTIM3) For example, if a 80-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0x1312C (78,124 decimal), the time-out period is: 1 Timeout period = -------------------6- × 16 × ( 127 + 1 ) × ( 78124 + 1 ) = 2.00 seconds × 80 10 Freescale Semiconductor Eqn. 21-2 21-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 DMA Timers (DTIM0–DTIM3) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 DMA Timers (DTIM0–DTIM3) 21-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 22 Queued Serial Peripheral Interface (QSPI) 22.1 Introduction This chapter describes the queued serial peripheral interface (QSPI) module. 22.1.1 Block Diagram Figure 22-1 illustrates the QSPI module. Queue Control Block Queue Pointer Comparator End Queue Pointer 4 80-byte QSPI RAM Done QSPI Address Register QSPI Data Register 4 Control Logic Chip Selects Status Regs Control Regs msb lsb 8/16 Bit Shift Reg. Logic Array QSPI_DIN Rx/Tx Data Reg. 4 QSPI_DOUT Command QSPI_CS[3:0] Delay Counter Internal Bus Internal Bus Clock (fsys) Divide by 2 Baud Rate Generator QSPI_CLK Figure 22-1. QSPI Block Diagram Freescale Semiconductor 22-1 Queued Serial Peripheral Interface (QSPI) Overview The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers. NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 26, “General Purpose I/O Module”) prior to configuring the QSPI module. 22.1.3 Features Features include: • Programmable queue to support up to 16 transfers without user intervention — 80 bytes of data storage provided • Supports transfer sizes of 8 to 16 bits in 1-bit increments • Four peripheral chip-select lines for control of up to 15 devices (All chip selects may not be available on all devices. See Chapter 14, “Signal Descriptions,” for details on which chip-selects are pinned-out.) • Baud rates from 156.9 Kbps to 20 Mbps at 80 MHz internal bus frequency • Programmable delays before and after transfers • Programmable QSPI clock phase and polarity • Supports wraparound mode for continuous transfers 22.1.4 Modes of Operation Because the QSPI module only operates in master mode, the master bit in the QSPI mode register (QMR[MSTR]) must be set for the QSPI to function properly. If the master bit is not set, QSPI activity is indeterminate. The QSPI can initiate serial transfers but cannot respond to transfers initiated by other QSPI masters. 22.2 External Signal Description The module provides access to as many as 15 devices with a total of seven signals: QSPI_DOUT, QSPI_DIN, QSPI_CLK, QSPI_CS[3:0]. Peripheral chip-select signals, QSPI_CSn, are used to select an external device as the source or destination for serial data transfer. Signals are asserted when a command in the queue is executed. More than one chip-select signal can be asserted simultaneously. Although QSPI_CSn signals function as simple chip selects in most applications, up to 15 devices can be selected by decoding them with an external 4-to-16 decoder. 22-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 22.1.2 Queued Serial Peripheral Interface (QSPI) Signal Name 22.3 Hi-Z or Actively Driven Function Data output (QSPI_DOUT) Configurable Serial data output from QSPI Data input (QSPI_DIN) N/A Serial data input to QSPI Serial clock (QSPI_CLK) Actively driven Clock output from QSPI Peripheral chip selects (QSPI_CSn) Actively driven Peripheral selects from QSPI Memory Map/Register Definition Table 22-2 is the QSPI register memory map. Reading reserved locations returns zeros. Table 22-2. QSPI Memory Map IPSBAR Offset1 1 2 Width (bits) Register Access Reset Value Section/Page 0x00_0340 QSPI Mode Register (QMR) 16 R/W 0x0104 22.3.1/22-3 0x00_0344 QSPI Delay Register (QDLYR) 16 R/W 0x0404 22.3.2/22-5 0x00_0348 QSPI Wrap Register (QWR) 16 R/W2 0x0000 22.3.3/22-6 0x00_034C QSPI Interrupt Register (QIR) 16 R/W2 0x0000 22.3.4/22-6 0x00_0350 QSPI Address Register (QAR) 16 R/W2 0x0000 22.3.5/22-7 0x00_0354 QSPI Data Register (QDR) 16 R/W 0x0000 22.3.6/22-8 Addresses not assigned to a register and undefined register bits are reserved for expansion. See the register description for special cases. Some bits may be read- or write-only. 22.3.1 QSPI Mode Register (QMR) The QMR, shown in Figure 22-2, determines the basic operating modes of the QSPI module. Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer size are determined by this register. NOTE Because the QSPI does not operate in slave mode, the master mode enable bit (QMR[MSTR]) must be set for the QSPI module to operate correctly. IPSBAR 0x00_0340 (QMR) Offset: 15 R W Reset MSTR 0 14 Access: User read/write 13 12 0 0 11 10 BITS 0 0 9 8 7 6 5 CPOL CPHA 0 0 0 1 4 3 2 1 0 1 0 0 BAUD 0 0 0 0 0 Figure 22-2. QSPI Mode Register (QMR) Freescale Semiconductor 22-3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 22-1. QSPI Input and Output Signals and Functions Queued Serial Peripheral Interface (QSPI) Field 15 MSTR 14 13–10 BITS Description Master mode enable. 0 Reserved, do not use. 1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly. Reserved, must be cleared. Transfer size. Determines the number of bits to be transferred for each entry in the queue. BITS Bits per Transfer 0000 16 0001–0111 Reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 9 CPOL Clock polarity. Defines the clock polarity of QSPI_CLK. 0 The inactive state value of QSPI_CLK is logic level 0. 1 The inactive state value of QSPI_CLK is logic level 1. 8 CPHA Clock phase. Defines the QSPI_CLK clock-phase. 0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK. 1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK. 7–0 BAUD Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables the QSPI. A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: QMR[BAUD] = fsys/ / (2 × [desired QSPI_CLK baud rate]) 22-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 22-3. QMR Field Descriptions Queued Serial Peripheral Interface (QSPI) QSPI_CLK QSPI_DOUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb QSPI_DIN 15 A B QSPI_CS QMR[CPOL] = 0 QMR[CPHA] = 1 QCR[CONT] = 0 Chip selects are active low A = QDLYR[QCD] B = QDLYR[DTL] Figure 22-3. QSPI Clocking and Data Transfer Example 22.3.2 QSPI Delay Register (QDLYR) The QDLYR is used to initiate master mode transfers and to set various delay parameters. IPSBAR 0x00_0344 (QDLYR) Offset: 15 R W Reset 14 13 Access: User read/write 12 SPE 0 11 10 9 8 7 6 5 4 QCD 0 0 0 0 3 2 1 0 0 1 0 0 DTL 1 0 0 0 0 0 0 Figure 22-4. QSPI Delay Register (QDLYR) Table 22-4. QDLYR Field Descriptions Field Description 15 SPE QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM. The QSPI clears this bit automatically when a transfer completes. The user can also clear this bit to abort transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT]. 14–8 QCD QSPI_CLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from assertion of the chip selects to valid QSPI_CLK transition. See Section 22.4.3, “Transfer Delays” for information on setting this bit field. 7–0 DTL Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer. Freescale Semiconductor 22-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Figure 22-3 shows an example of a QSPI clocking and data transfer. Queued Serial Peripheral Interface (QSPI) QSPI Wrap Register (QWR) The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations. IPSBAR 0x00_0348 (QWR) Offset: 15 R W Reset 14 Access: User read/write 13 12 11 10 HALT WREN WRTO CSIV 0 0 0 0 9 8 7 6 ENDQP 0 0 5 4 3 CPTQP 0 0 0 0 2 1 0 NEWQP 0 0 0 0 0 0 Figure 22-5. QSPI Wrap Register (QWR) Table 22-5. QWR Field Descriptions Field Description 15 HALT Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands after it has completed execution of the current command. 14 WREN Wraparound enable. Enables wraparound mode. 0 Execution stops after executing the command pointed to by QWR[ENDQP]. 1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by QWR[NEWQP] and continue execution. 13 WRTO Wraparound location. Determines where the QSPI wraps to in wraparound mode. 0 Wrap to RAM entry zero. 1 Wrap to RAM entry pointed to by QWR[NEWQP]. 12 CSIV QSPI_CS inactive level. 0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 0, chip selects are active high). 1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 1, chip selects are active low). 11–8 End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue. ENDQP 7–4 CPTQP Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed. This field is read only. 3–0 Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer. NEWQP 22.3.4 QSPI Interrupt Register (QIR) The QIR contains QSPI interrupt enables and status flags. IPSBAR 0x00_034C (QIR) Offset: 15 R W Reset 14 WCEFB ABRTB 0 0 Access: User read/write 13 0 0 12 11 10 ABRTL WCEFE ABRTE 0 0 0 9 0 0 8 SPIFE 0 7 6 5 4 0 0 0 0 0 0 0 0 3 2 WCEF ABRT w1c w1c 0 0 1 0 0 SPIF w1c 0 0 Figure 22-6. QSPI Interrupt Register (QIR) 22-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 22.3.3 Queued Serial Peripheral Interface (QSPI) Field Description 15 Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing WCEFB the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR results in an access error. 14 ABRTB 13 12 ABRTL Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set, an attempt to clear QDLYR[SPE] during a transfer results in an access error. Reserved, must be cleared. Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only cleared by the QSPI when a transfer completes. 11 Write collision (WCEF) interrupt enable. WCEFE 0 Write collision interrupt disabled 1 Write collision interrupt enabled 10 ABRTE 9 8 SPIFE 7–4 Abort (ABRT) interrupt enable. 0 Abort interrupt disabled 1 Abort interrupt enabled Reserved, must be cleared. QSPI finished (SPIF) interrupt enable. 0 SPIF interrupt disabled 1 SPIF interrupt enabled Reserved, must be cleared. 3 WCEF Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is currently being executed. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect. 2 ABRT Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than by completion of the command queue by the QSPI. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect. 1 0 SPIF 22.3.5 Reserved, must be cleared. QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on completion of the command pointed to by QWR[ENDQP], and on completion of the current command after assertion of QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect. QSPI Address Register (QAR) The QAR is used to specify the location in the QSPI RAM that read and write operations affect. As shown in Section 22.4.1, “QSPI RAM”, the transmit RAM is located at addresses 0x0 to 0xF, the receive RAM is located at 0x10 to 0x1F, and the command RAM is located at 0x20 to 0x2F. (These addresses refer to the QSPI RAM space, not the device memory map.) NOTE A read or write to the QSPI RAM causes QAR to increment. However, the QAR does not wrap after the last queue entry within each section of the RAM. The application software must manage address range errors. Freescale Semiconductor 22-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 22-6. QIR Field Descriptions Queued Serial Peripheral Interface (QSPI) R Access: User read/write 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 1 0 0 0 ADDR W Reset 2 0 0 0 0 Figure 22-7. QSPI Address Register (QAR) Table 22-7. QAR Field Descriptions Field Description 15–6 Reserved, must be cleared. 5–0 ADDR 22.3.6 Address used to read/write the QSPI RAM. Ranges are as follows: 0x00–0x0F Transmit RAM 0x10–0x1F Receive RAM 0x20–0x2F Command RAM 0x30–0x3F Reserved QSPI Data Register (QDR) The QDR is used to access QSPI RAM indirectly. The CPU reads and writes all data from and to the QSPI RAM through this register. A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state. IPSBAR 0x00_0354 (QDR) Offset: 15 14 13 Access: User read/write 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DATA W Reset 7 0 0 0 0 0 0 0 0 Figure 22-8. QSPI Data Register (QDR) Table 22-8. QDR Field Descriptions Field Description 15–0 DATA A write to this field causes data to be written to the QSPI RAM entry specified by QAR[ADDR]. Similarly, a read of this field returns the data in the QSPI RAM at the address specified by QAR[ADDR]. During command RAM accesses (QAR[ADDR] = 0x20–0x2F), only the most significant byte of this field is used. 22.3.7 Command RAM Registers (QCR0–QCR15) The command RAM is accessed using the upper byte of the QDR; the QSPI cannot modify information in command RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations. 22-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x00_0350 (QAR) Offset: NOTE The command RAM is accessed only using the most significant byte of QDR and indirect addressing based on QAR[ADDR]. Address: QAR[ADDR] 15 14 Access: CPU write-only 13 12 DT DSCK — — 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 — — — — — — — — R W CONT BITSE Reset — — QSPI_CS — — — — Figure 22-9. Command RAM Registers (QCR0–QCR15) Table 22-9. QCR0–QCR15 Field Descriptions Field Description 15 CONT Continuous. 0 Chip selects return to inactive level defined by QWR[CSIV] when a single word transfer is complete. 1 Chip selects return to inactive level defined by QWR[CSIV] only after the transfer of the queue entries (max of 16 words). Note: To keep the chip selects asserted for transfers beyond 16 words, the QWR[CSIV] bit must be set to control the level that the chip selects return to after the first transfer. 14 BITSE Bits per transfer enable. 0 Eight bits 1 Number of bits set in QMR[BITS] 13 DT 12 DSCK Delay after transfer enable. 0 Default reset value. 1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. The delay between transfers is determined by QDLYR[DTL]. Chip select to QSPI_CLK delay enable. 0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period. 1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK. 11–8 Peripheral chip selects. Used to select an external device for serial data transfer. More than one chip select may be QSPI_CS active at once, and more than one device can be connected to each chip select. Bits 11-8 map directly to the corresponding QSPI_CSn pins. If more than four chip selects are needed, then an external demultiplexor can be used with the QSPI_CSn pins. 0 Enable chip select. 1 Mask chip select. Note: Not all chip selects may be available on all device packages. See Chapter 14, “Signal Descriptions,” for details on which chip selects are pinned-out. 7–0 22.4 Reserved, must be cleared. Functional Description The QSPI uses a dedicated 80-byte block of static RAM accessible to the module and CPU to perform queued operations. The RAM is divided into three segments: • 16 command control bytes (command RAM) • 32 transmit data bytes (transmit data RAM) Freescale Semiconductor 22-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Queued Serial Peripheral Interface (QSPI) Queued Serial Peripheral Interface (QSPI) 32 receive data bytes (receive data RAM) The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF). NOTE Throughout ColdFire documentation, the term word is used to designate a 16-bit data unit. The only exceptions to this appear in discussions of serial communication modules such as QSPI that support variable-length data units. To simplify these discussions, the functional unit is referred to as a word regardless of length. The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt. The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap register (QWR): • New queue pointer (QWR[NEWQP])—points to the first command in the queue • Internal queue pointer—points to the command currently being executed • Completed queue pointer (QWR[CPTQP])—points to the last command executed • End queue pointer (QWR[ENDQP]) —points to the final command in the queue The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the following sequence repeats: 1. The command pointed to by the internal pointer is executed. 2. The value in the internal pointer is copied into QWR[CPTQP]. 3. The internal pointer is incremented. Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs, QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables wraparound mode. QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to show the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be written at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled. Data is transferred relative to QSPI_CLK, which can be generated in any one of four combinations of phase and polarity using QMR[CPHA,CPOL]. Data is transferred with the most significant bit (msb) first. The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]). 22-10 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 • Queued Serial Peripheral Interface (QSPI) QSPI RAM The QSPI contains an 80-byte block of static RAM that can be accessed by the user and the QSPI. This RAM does not appear in the device memory map, because it can only be accessed by the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR). The RAM is divided into three segments with 16 addresses each: • • • Receive data RAM—the initial destination for all incoming data Transmit data RAM—a buffer for all out-bound data Command RAM—where commands are loaded The transmit data and command RAM are user write-only. The receive RAM is user read-only. Figure 22-10 shows the RAM configuration. The RAM contents are undefined immediately after a reset. The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands. A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the value in QAR to increment. Correspondingly, a read from QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state. Relative Address Register 0x00 QTR0 0x01 QTR1 ... ... 0x0F QTR15 0x10 QRR0 0x11 QRR1 ... ... 0x1F QRR15 0x20 QCR0 0x21 QCR1 ... ... 0x2F QCR15 Function Transmit RAM 16 bits wide Receive RAM 16 bits wide Command RAM 8 bits wide Figure 22-10. QSPI RAM Model 22.4.1.1 Receive RAM Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space. Read this segment to retrieve data from the QSPI. Data words with less than 16 bits are stored in Freescale Semiconductor 22-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 22.4.1 the least significant bits of the RAM. Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry. Receive RAM is not writeable. QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data. 22.4.1.2 Transmit RAM Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF. The user normally writes 1 word into this segment for each queue command to be executed. The user cannot read data in the transmit RAM. Outbound data must be written to transmit RAM in a right-justified format. The unused bits are ignored. The QSPI copies the data to its data serializer (shift register) for transmission. The data is transmitted most significant bit first and remains in transmit RAM until overwritten by the user. 22.4.1.3 Command RAM The CPU writes one byte of control information to this segment for each QSPI command to be executed. Command RAM, referred to as QCR0–15, is write-only memory from a user’s perspective. Command RAM consists of 16 bytes, each divided into two fields. The peripheral chip select field controls the QSPI_CS signal levels for the transfer. The command control field provides transfer options. A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in QWR[NEWQP] through the address in QWR[ENDQP]. The QSPI executes a queue of commands defined by the control bits in each command RAM entry that sequence the following actions: • Chip-select pins are activated. • Data is transmitted from the transmit RAM and received into the receive RAM. • The synchronous transfer clock QSPI_CLK is generated. Before any data transfers begin, control data must be written to the command RAM, and any out-bound data must be written to the transmit RAM. Also, the queue pointers must be initialized to the first and last entries in the command queue. Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which QSPI_CLK edge is used to drive outgoing data and to latch incoming data. 22.4.2 Baud Rate Selection The maximum QSPI clock frequency is one-fourth the clock frequency of the internal bus clock (fsys). Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the QSPI_CLK rate from the internal bus clock divided by two. Table 22-10 shows the QSPI_CLK frequency as a function of internal bus clock and baud rate. A baud rate value of zero turns off the QSPI_CLK. 22-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Queued Serial Peripheral Interface (QSPI) The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: f sys QMR[BAUD] = ----------------------------------------------------------------------------------2 × [desired QSPI_CLK baud rate] Eqn. 22-1 Table 22-10. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate Internal Bus Clock = 80 MHz 22.4.3 QMR [BAUD] QSPI_CLK 2 20 MHz 4 10 MHz 8 5 MHz 16 2.5 MHz 32 1.25 Hz 255 156.9 kHz Transfer Delays The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The time between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end of one transfer and the beginning of the next, are both independently programmable. The chip select to clock delay enable bit in the command RAM, QCR[DSCK], enables the programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD] determines the period of delay before the leading edge of QSPI_CLK. The following expression determines the actual delay before the QSPI_CLK leading edge: QDLYR[QCD] QSPI_CS-to-QSPI_CLK delay = ------------------------------------f sys Eqn. 22-2 QDLYR[QCD] has a range of 1–127. When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK period is used. The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay period from the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the user can choose to delay a standard period after serial transfer is complete or can specify a delay period. Writing a value to QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay when DT equals 1: 32 × QDLYR[DTL] Delay after transfer = -----------------------------------------------f sys Freescale Semiconductor (DT = 1) Eqn. 22-3 22-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Queued Serial Peripheral Interface (QSPI) where QDLYR[DTL] has a range of 1–255. A zero value for DTL causes a delay-after-transfer value of 8192/fsys. Standard delay period (DT = 0) is calculated by the following: 17 Standard delay after transfer = ------f sys (DT = 0) Eqn. 22-4 Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers. If the internal bus clock is operating at a slower rate, the delay between transfers must be increased proportionately. 22.4.4 Transfer Length There are two transfer length options. The user can choose a default value of 8 bits or a programmed value of 8 to 16 bits. The programmed value must be written into QMR[BITS]. The command RAM bits per transfer enable field, QCR[BITSE], determines whether the default value (BITSE = 0) or the BITS[3–0] value (BITSE = 1) is used. QMR[BITS] indicates the required number of bits to be transferred, with the default value of 16 bits. 22.4.5 Data Transfer The transfer operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI executes the command at the command RAM address pointed to by QWR[NEWQP]. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM. When the proper number of bits has been transferred, the QSPI stores the working queue pointer value in QWR[CPTQP], increments the working queue pointer, and loads the next data for transfer from the transmit RAM. The command pointed to by the incremented working queue pointer is executed next unless a new value has been written to QWR[NEWQP]. If a new queue pointer value is written while a transfer is in progress, the current transfer is completed normally. When the CONT bit in the command RAM is set, the QSPI_CSn signals are asserted between transfers. When CONT is cleared, QSPI_CSn are negated between transfers. The QSPI_CSn signals are not high impedance. When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If QIR[SPIFE] is set, an interrupt request is generated when QIR[SPIF] is asserted. Then the QSPI clears QDLYR[SPE] and stops, unless wraparound mode is enabled. Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO]. In wraparound mode, the QSPI cycles through the queue continuously, even while requesting interrupt service. QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached, 22-14 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Queued Serial Peripheral Interface (QSPI) QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE]. There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended because this may abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and stops the first time it reaches the end of the queue after QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared. 22.5 Initialization/Application Information The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 5 MHz. The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example. 1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling clock edge, and a QSPI_CLK frequency of 5 MHz (assuming a 80-MHz internal bus clock). 2. Write QDLYR with the desired delays. 3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any interrupts. 4. Write QAR with 0x0020 to select the first command RAM entry. 5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00, 0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each chip select. The chip selects are active low in this example. 6. Write QAR with 0x0000 to select the first transmit RAM entry. 7. Write QDR with sixteen 12-bit words of data. 8. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15. 9. Set QDLYR[SPE] to enable the transfers. 10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete. 11. Write QAR with 0x0010 to select the first receive RAM entry. 12. Read QDR to get the received data for each transfer. 13. Repeat steps 5 through 13 to do another transfer. Freescale Semiconductor 22-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Queued Serial Peripheral Interface (QSPI) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Queued Serial Peripheral Interface (QSPI) 22-16 Freescale Semiconductor 23.1 Introduction This chapter describes the use of the three universal asynchronous receiver/transmitters (UARTs) and includes programming examples. NOTE The designation n appears throughout this section to refer to registers or signals associated with one of the three identical UART modules: UART0, UART1, or UART2. 23.1.1 Overview The internal bus clock can clock each of the three independent UARTs, eliminating the need for an external UART clock. As Figure 23-1 shows, each UART module interfaces directly to the CPU and consists of: • Serial communication channel • Programmable clock generation • Interrupt control logic and DMA request logic • Internal channel control logic Internal Bus UART UCTSn Internal Channel Control Logic Serial Communications Channel URTSn URXDn UTXDn Interrupt Request (to Interrupt Controller) Transmit DMA Request Receive DMA Request Interrupt Control Logic DMA Request Logic Programmable Clock Generation External Signals UART Registers Internal Bus Clock (fsys) or External Clock (DTINn) (To DMA Controller) Figure 23-1. UART Block Diagram Freescale Semiconductor 23-1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Chapter 23 UART Modules UART Modules The DTINn pin can clock UARTn. However, if the timers are operating and the UART uses DTINn as a clock source, input capture mode is not available for that timer. The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on the transmitter serial data output (UTXDn). See Section 23.4.2.1, “Transmitter.” The receiver converts serial data from the receiver serial data input (URXDn) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. The receiver may be polled, interrupt driven, or use DMA requests for servicing. See Section 23.4.2.2, “Receiver.” NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 26, “General Purpose I/O Module”) prior to configuring the UART module. 23.1.2 Features The device contains three independent UART modules with: • Each clocked by external clock or internal bus clock (eliminates need for an external UART clock) • Full-duplex asynchronous/synchronous receiver/transmitter • Quadruple-buffered receiver • Double-buffered transmitter • Independently programmable receiver and transmitter clock sources • Programmable data format: — 5–8 data bits plus parity — Odd, even, no parity, or force parity — One, one-and-a-half, or two stop bits • Each serial channel programmable to normal (full-duplex), automatic echo, local loopback, or remote loopback mode • Automatic wake-up mode for multidrop applications • Four maskable interrupt conditions • All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character 23-2 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NOTE UART Modules Start/end break interrupt/status 23.2 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 • External Signal Description Table 23-1 briefly describes the UART module signals. Table 23-1. UART Module External Signals Signal Description UTXDn Transmitter Serial Data Output. UTXDn is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on UTXDn on the falling edge of the clock source, with the least significant bit (lsb) sent first. URXDn Receiver Serial Data Input. Data received on URXDn is sampled on the rising edge of the clock source, with the lsb received first. UCTSn Clear-to- Send. This input can generate an interrupt on a change of state. URTSn Request-to-Send. This output can be programmed to be negated or asserted automatically by the receiver or the transmitter. When connected to a transmitter’s UCTSn, URTSn can control serial data flow. Figure 23-2 shows a signal configuration for a UART/RS-232 interface. UART RS-232 Transceiver URTSn DI2 UCTSn DO2 UTXDn DI1 URXDn DO1 Figure 23-2. UART/RS-232 Interface 23.3 Memory Map/Register Definition This section contains a detailed description of each register and its specific function. Flowcharts in Section 23.5, “Initialization/Application Information,” describe basic UART module programming. Writing control bytes into the appropriate registers controls the operation of the UART module. NOTE UART registers are accessible only as bytes. NOTE Interrupt can mean an interrupt request asserted to the CPU or a DMA request. Freescale Semiconductor 23-3 Table 23-2. UART Module Memory Map UART0 UART1 UART2 Register Width Access Reset Value Section/Page (bit) 0x00 0x0 0x0 UART Mode Registers1 (UMR1n), (UMR2n) 8 R/W 0x00 23.3.1/23-5 23.3.2/23-6 0x04 0x4 0x4 UART Status Register (USRn) 8 R 0x00 23.3.3/23-8 UART Clock Select Register1(UCSRn) 8 W See Section 23.3.4/23-9 0x08 0x8 0x8 UART Command Registers (UCRn) 8 W 0x00 23.3.5/23-9 0x0C 0xC 0xC UART Receive Buffers (URBn) 8 R 0xFF 23.3.6/23-11 UART Transmit Buffers (UTBn) 8 W 0x00 23.3.7/23-12 0x10 0x0 0x0 UART Input Port Change Register (UIPCRn) 8 R See Section 23.3.8/23-12 UART Auxiliary Control Register (UACRn) 8 W 0x00 23.3.9/23-13 0x14 0x4 0x4 UART Interrupt Status Register (UISRn) 8 R 0x00 23.3.10/23-13 UART Interrupt Mask Register (UIMRn) 8 W 0x00 0x18 0x8 0x8 UART Baud Rate Generator Register (UBG1n) 8 W2 0x00 23.3.11/23-15 0x1C 0xC 0xC UART Baud Rate Generator Register (UBG2n) 8 W2 0x00 23.3.11/23-15 0x34 0x4 0x4 UART Input Port Register (UIPn) 8 R 0xFF 23.3.12/23-15 0x38 0x8 0x8 UART Output Port Bit Set Command Register (UOP1n) 8 W2 0x00 23.3.13/23-16 0x3C 0xC 0xC UART Output Port Bit Reset Command Register (UOP0n) 8 W2 0x00 23.3.13/23-16 1 UMR1n, UMR2n, and UCSRn must be changed only after the receiver/transmitter is issued a software reset command. If operation is not disabled, undesirable results may occur. 2 Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. 23-4 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 UART Modules UART Modules UART Mode Registers 1 (UMR1n) The UMR1n registers control UART module configuration. UMR1n can be read or written when the mode register pointer points to it, at RESET or after a RESET MODE REGISTER POINTER command using UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n. Access: User read/write1 IPSBAR 0x00_0200 (UMR10) Offset: 0x00_0240 (UMR11) 0x00_0280 (UMR12) 7 6 5 RXRTS RXIRQ/ FFULL ERR 0 0 0 R W Reset: 1 4 3 PM 0 2 1 PT 0 0 0 B/C 0 0 After UMR1n is read or written, the pointer points to UMR2n Figure 23-3. UART Mode Registers 1 (UMR1n) Table 23-3. UMR1n Field Descriptions Field Description 7 RXRTS Receiver request-to-send. Allows the URTSn output to control the UCTSn input of the transmitting device to prevent receiver overrun. If the receiver and transmitter are incorrectly programmed for URTSn control, URTSn control is disabled for both. Transmitter RTS control is configured in UMR2n[TXRTS]. 0 The receiver has no effect on URTSn. 1 When a valid start bit is received, URTSn is negated if the UART's FIFO is full. URTSn is reasserted when the FIFO has an empty position available. 6 RXIRQ/ FFULL Receiver interrupt select. 0 RXRDY is the source generating interrupt or DMA requests. 1 FFULL is the source generating interrupt or DMA requests. 5 ERR Error mode. Configures the FIFO status bits, USRn[RB,FE,PE]. 0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR must be 0 for correct A/D flag information when in multidrop mode. 1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the FIFO since the last RESET ERROR STATUS command for the UART was issued. See Section 23.3.5, “UART Command Registers (UCRn).” 4–3 PM Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. Freescale Semiconductor 23-5 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 23.3.1 UART Modules Field 2 PT Description Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11). 1–0 B/C PM Parity Mode Parity Type (PT= 0) Parity Type (PT= 1) 00 With parity Even parity Odd parity 01 Force parity Low parity High parity 10 No parity 11 Multidrop mode N/A Data character Address character Bits per character. Selects the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits. 00 5 bits 01 6 bits 10 7 bits 11 8 bits 23.3.2 UART Mode Register 2 (UMR2n) The UMR2n registers control UART module configuration. UMR2n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do not update the pointer. Access: User read/write1 IPSBAR 0x00_0200 (UMR20) Offset: 0x00_0240 (UMR21) 0x00_0280 (UMR22) 7 6 5 4 TXRTS TXCTS 0 0 3 2 1 0 0 0 R CM SB W Reset: 0 1 0 0 0 After UMR1n is read or written, the pointer points to UMR2n Figure 23-4. UART Mode Registers 2 (UMR2n) 23-6 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 23-3. UMR1n Field Descriptions (continued) UART Modules Field 7–6 CM Description Channel mode. Selects a channel mode. Section 23.4.3, “Looping Modes,” describes individual modes. 00 Normal 01 Automatic echo 10 Local loopback 11 Remote loopback 5 TXRTS Transmitter ready-to-send. Controls negation of URTSn to automatically terminate a message transmission. Attempting to program a receiver and transmitter in the same UART for URTSn control is not permitted and disables URTSn control for both. 0 The transmitter has no effect on URTSn. 1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically clears UOP[RTS] one bit time after any characters in the transmitter shift and holding registers are completely sent, including the programmed number of stop bits. 4 TXCTS Transmitter clear-to-send. If TXCTS and TXRTS are set, TXCTS controls the operation of the transmitter. 0 UCTSn has no effect on the transmitter. 1 Enables clear-to-send operation. The transmitter checks the state of UCTSn each time it is ready to send a character. If UCTSn is asserted, the character is sent; if it is deasserted, the signal UTXDn remains in the high state and transmission is delayed until UCTSn is asserted. Changes in UCTSn as a character is being sent do not affect its transmission. 3–0 SB Stop-bit length control. Selects length of stop bit appended to the transmitted character. Stop-bit lengths of 9/16 to 2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to 2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high condition at the center of the first stop-bit position, one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission. Freescale Semiconductor SB 5 Bits 6–8 Bits SB 5–8 Bits 0000 1.063 0.563 1000 1.563 0001 1.125 0.625 1001 1.625 0010 1.188 0.688 1010 1.688 0011 1.250 0.750 1011 1.750 0100 1.313 0.813 1100 1.813 0101 1.375 0.875 1101 1.875 0110 1.438 0.938 1110 1.938 0111 1.500 1.000 1111 2.000 23-7 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 23-4. UMR2n Field Descriptions UART Modules UART Status Registers (USRn) The USRn registers show the status of the transmitter, the receiver, and the FIFO. IPSBAR 0x00_0204 (USR0) Offset: 0x00_0244 (USR1) 0x00_0284 (USR2) R Access: User read-only 7 6 5 4 3 2 1 0 RB FE PE OE TXEMP TXRDY FFULL RXRDY 0 0 0 0 0 0 0 0 W Reset: Figure 23-5. UART Status Registers (USRn) Table 23-5. USRn Field Descriptions Field Description 7 RB Received break. The received break circuit detects breaks originating in the middle of a received character. However, a break in the middle of a character must persist until the end of the next detected character time. 0 No break was received. 1 An all-zero character of the programmed length was received without a stop bit. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until URXDn returns to the high state for at least one-half bit time, which equals two successive edges of the UART clock. RB is valid only when RXRDY is set. 6 FE Framing error. 0 No framing error occurred. 1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RXRDY is set. 5 PE Parity error. Valid only if RXRDY is set. 0 No parity error occurred. 1 If UMR1n[PM] equals 0x (with parity or force parity), the corresponding character in the FIFO was received with incorrect parity. If UMR1n[PM] equals 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid only when RXRDY is set. 4 OE Overrun error. Indicates whether an overrun occurs. 0 No overrun occurred. 1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. The RESET ERROR STATUS command in UCRn clears OE. 3 TEMP Transmitter empty. 0 The transmit buffer is not empty. A character is shifted out, or the transmitter is disabled. The transmitter is enabled/disabled by programming UCRn[TC]. 1 The transmitter has underrun (the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. 2 TXRDY Transmitter ready. 0 The CPU loaded the transmitter holding register, or the transmitter is disabled. 1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. 23-8 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 23.3.3 UART Modules Field Description 1 FFULL FIFO full. 0 The FIFO is not full but may hold up to two unread characters. 1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost. 0 RXRDY Receiver ready. 0 The CPU has read the receive buffer and no characters remain in the FIFO after this read. 1 One or more characters were received and are waiting in the receive buffer FIFO. 23.3.4 UART Clock Select Registers (UCSRn) The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus clock as the clocking source for the transmitter and receiver. See Section 23.4.1, “Transmitter/Receiver Clock Source.” The transmitter and receiver can use different clock sources. To use the internal bus clock for both, set UCSRn to 0xDD. IPSBAR 0x00_0204 (UCSR0) Offset: 0x00_0244 (UCSR1) 0x00_0284 (UCSR2) 7 Access: User write-only 6 5 4 3 2 1 0 R W Reset: RCS TCS See Note See Note Note: The RCS and TCS reset values are set so the receiver and transmiter use the prescaled internal bus clock as their clock source. Figure 23-6. UART Clock Select Registers (UCSRn) Table 23-6. UCSRn Field Descriptions Field Description 7–4 RCS Receiver clock select. Selects the clock source for the receiver. 1101 Prescaled internal bus clock (fsys) 1110 DTINn divided by 16 1111 DTINn 3–0 TCS Transmitter clock select. Selects the clock source for the transmitter. 1101 Prescaled internal bus clock (fsys) 1110 DTINn divided by 16 1111 DTINn 23.3.5 UART Command Registers (UCRn) The UCRs supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, RESET TRANSMITTER and ENABLE TRANSMITTER cannot be specified in one command. Freescale Semiconductor 23-9 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 23-5. USRn Field Descriptions (continued) UART Modules 7 Access: User write-only 6 5 4 3 2 1 0 R W 0 Reset: 0 MISC 0 0 TC 0 0 RC 0 0 0 Figure 23-7. UART Command Registers (UCRn) Table 23-7 describes UCRn fields and commands. Examples in Section 23.4.2, “Transmitter and Receiver Operating Modes,” show how these commands are used. Table 23-7. UCRn Field Descriptions Field 7 6–4 MISC Description Reserved, must be cleared. MISC Field (this field selects a single command) Command Description 000 NO COMMAND — 001 RESET MODE Causes the mode register pointer to point to UMR1n. REGISTER POINTER 010 RESET RECEIVER Immediately disables the receiver, clears USRn[FFULL,RXRDY], and reinitializes the receiver FIFO pointer. No other registers are altered. Because it places the receiver in a known state, use this command instead of RECEIVER DISABLE when reconfiguring the receiver. 011 RESET Immediately disables the transmitter and clears USRn[TXEMP,TXRDY]. No other registers are altered. Because it places the transmitter in a known state, use this command instead of TRANSMITTER DISABLE when reconfiguring the transmitter. TRANSMITTER 100 Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after a data block is received. RESET ERROR STATUS 101 RESET BREAK – Clears the delta break bit, UISRn[DB]. CHANGE INTERRUPT 23-10 110 START BREAK Forces UTXDn low. If the transmitter is empty, break may be delayed up to one bit time. If the transmitter is active, break starts when character transmission completes. Break is delayed until any character in the transmitter shift register is sent. Any character in the transmitter holding register is sent after the break. Transmitter must be enabled for the command to be accepted. This command ignores the state of UCTSn. 111 STOP BREAK Causes UTXDn to go high (mark) within two bit times. Any characters in the transmit buffer are sent. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x00_0208 (UCR0) Offset: 0x00_0248 (UCR1) 0x00_0288 (UCR2) UART Modules Field 3–2 TC Description Transmit command field. Selects a single transmit command. Command 00 NO ACTION TAKEN Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 TRANSMITTER Enables operation of the UART’s transmitter. USRn[TXEMP,TXRDY] are set. If the transmitter is already enabled, this command has no effect. ENABLE 10 TRANSMITTER DISABLE 11 1–0 RC Description — Terminates transmitter operation and clears USRn[TXEMP,TXRDY]. If a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. If the transmitter is already disabled, the command has no effect. Reserved, do not use. Receive command field. Selects a single receive command. Command 00 NO ACTION TAKEN 01 RECEIVER ENABLE 10 RECEIVER DISABLE 11 23.3.6 — Description Causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled. If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11), RECEIVER ENABLE enables the UART's receiver and forces it into search-for-start-bit state. If the receiver is already enabled, this command has no effect. Disables the receiver immediately. Any character being received is lost. The command does not affect receiver status bits or other control registers. If the UART module is programmed for local loopback or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, the command has no effect. Reserved, do not use. UART Receive Buffers (URBn) The receive buffers contain one serial shift register and three receiver holding registers, which act as a FIFO. URXDn is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift register is full (see Figure 23-18). RB contains the character in the receiver. Freescale Semiconductor 23-11 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 23-7. UCRn Field Descriptions (continued) UART Modules 7 6 Access: User read-only 5 4 R 3 2 1 0 1 1 1 1 RB W Reset: 1 1 1 1 Figure 23-8. UART Receive Buffer (URBn) 23.3.7 UART Transmit Buffers (UTBn) The transmit buffers consist of the transmitter holding register and the transmitter shift register. The holding register accepts characters from the bus master if UART’s USRn[TXRDY] is set. A write to the transmit buffer clears USRn[TXRDY], inhibiting any more characters until the shift register can accept more data. When the shift register is empty, it checks if the holding register has a valid character to be sent (TXRDY = 0). If there is a valid character, the shift register loads it and sets USRn[TXRDY] again. Writes to the transmit buffer when the UART’s TXRDY is cleared and the transmitter is disabled have no effect on the transmit buffer. Figure 23-9 shows UTBn. TB contains the character in the transmit buffer. IPSBAR 0x00_020C (UTB0) Offset: 0x00_024C (UTB1) 0x00_028C (UTB2) 7 6 Access: User write-only 5 4 3 2 1 0 0 0 0 0 R W Reset: TB 0 0 0 0 Figure 23-9. UART Transmit Buffer (UTBn) 23.3.8 UART Input Port Change Registers (UIPCRn) The UIPCRs hold the current state and the change-of-state for UCTSn. IPSBAR 0x00_0210 (UIPCR0) Offset: 0x00_0250 (UIPCR1) 0x00_0290 (UIPCR2) R Access: User read-only 7 6 5 4 3 2 1 0 0 0 0 COS 1 1 1 CTS 0 0 0 0 1 1 1 UCTSn W Reset: Figure 23-10. UART Input Port Changed Registers (UIPCRn) 23-12 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 IPSBAR 0x00_020C (URB0) Offset: 0x00_024C (URB1) 0x00_028C (URB2) UART Modules Field Description 7–5 Reserved 4 COS Change of state (high-to-low or low-to-high transition). 0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS]. 1 A change-of-state longer than 25–50 μs occurred on the UCTSn input. UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected. 3–1 Reserved 0 CTS Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the state of UCTSn. If UCTSn is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled. 0 The current state of the UCTSn input is asserted. 1 The current state of the UCTSn input is deasserted. 23.3.9 UART Auxiliary Control Register (UACRn) The UACRs control the input enable. IPSBAR 0x00_0210 (UACR0) Offset: 0x00_0250 (UACR1) 0x00_0290 (UACR2) Access: User write-only 7 6 5 4 3 2 1 0 W 0 0 0 0 0 0 0 IEC Reset: 0 0 0 0 0 0 0 0 R Figure 23-11. UART Auxiliary Control Registers (UACRn) Table 23-9. UACRn Field Descriptions Field Description 7–1 Reserved, must be cleared. 0 IEC Input enable control. 0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS]. 1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition on the UCTSn input (if UIMRn[COS] = 1). 23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn) The UISRs provide status for all potential interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, internal interrupt output is asserted. If a UIMRn bit is cleared, state of the corresponding UISRn bit has no effect on the output. The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits. Freescale Semiconductor 23-13 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 23-8. UIPCRn Field Descriptions UART Modules True status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module is reset. IPSBAR 0x00_0214 (UISR0) Offset: 0x00_0254 (UISR1) 0x00_0294 (UISR2) Access: User read/write 7 6 5 4 3 2 1 0 R (UISRn) COS 0 0 0 0 DB FFULL/ RXRDY TXRDY W (UIMRn) COS 0 0 0 0 DB FFULL/ RXRDY TXRDY 0 0 0 0 0 0 0 0 Reset: Figure 23-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn) Table 23-10. UISRn/UIMRn Field Descriptions Field Description 7 COS Change-of-state. 0 UIPCRn[COS] is not selected. 1 Change-of-state occurred on UCTSn and was programmed in UACRn[IEC] to cause an interrupt. 6–3 Reserved, must be cleared. 2 DB Delta break. 0 No new break-change condition to report. Section 23.3.5, “UART Command Registers (UCRn),” describes the RESET BREAK-CHANGE INTERRUPT command. 1 The receiver detected the beginning or end of a received break. 1 FFULL/ RXRDY 0 TXRDY 23-14 Status of FIFO or receiver, depending on UMR1[FFULL/RXRDY] bit. Duplicate of USRn[FIFO] and USRn[RXRDY] UIMRn UISRn [FFULL/RXRDY] [FFULL/RXRDY] UMR1n[FFULL/RXRDY] 0 (RXRDY) 1 (FIFO) 0 0 Receiver not ready FIFO not full 1 0 Receiver not ready FIFO not full 0 1 Receiver is ready, Do not interrupt FIFO is full, Do not interrupt 1 1 Receiver is ready, interrupt FIFO is full, interrupt Transmitter ready. This bit is the duplication of USRn[TXRDY]. 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY is cleared are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 NOTE UART Modules The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload value. UBG1n and UBG2n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation, as described in Section 23.4.1.2.1, “Internal Bus Clock Baud Rates.” IPSBAR 0x00_0218 (UBG10) Offset: 0x00_0258 (UBG11) 0x00_0298 (UBG12) 7 6 Access: User write-only 5 4 3 2 1 0 0 0 0 0 R W Reset: Divider MSB 0 0 0 0 Figure 23-13. UART Baud Rate Generator Registers (UBG1n) IPSBAR 0x00_021C (UBG20) Offset: 0x00_025C (UBG21) 0x00_029C (UBG22) 7 6 Access: User write-only 5 4 3 2 1 0 0 0 0 0 R W Reset: Divider LSB 0 0 0 0 Figure 23-14. UART Baud Rate Generator Registers (UBG2n) NOTE The minimum value loaded on the concatenation of UBG1n with UBG2n is 0x0002. The UBG2n reset value of 0x00 is invalid and must be written to before the UART transmitter or receiver are enabled. UBG1n and UBG2n are write-only and cannot be read by the CPU. 23.3.12 UART Input Port Register (UIPn) The UIPn registers show the current state of the UCTSn input. IPSBAR 0x00_0234 (UIP0) Offset: 0x00_0274 (UIP1) 0x00_02B4 (UIP2) R Access: User read-only 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 CTS 1 1 1 1 1 1 1 1 W Reset: Figure 23-15. UART Input Port Registers (UIPn) Freescale Semiconductor 23-15 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) UART Modules Field Description 7–1 Reserved 0 CTS Current state of clear-to-send. The UCTSn value is latched and reflects the state of the input pin when UIPn is read. Note: This bit has the same function and value as UIPCRn[CTS]. 0 The current state of the UCTSn input is logic 0. 1 The current state of the UCTSn input is logic 1. 23.3.13 UART Output Port Command Registers (UOP1n/UOP0n) The URTSn output can be asserted by writing a 1 to UOP1n[RTS] and negated by writing a 1 to UOP0n[RTS]. IPSBAR 0x00_0238 (UOP10) Offset: 0x00_023C (UOP00) 0x00_0278 (UOP11) 0x00_027C (UOP01) 0x00_02B8 (UOP12) 0x00_02BC (UOP02) Access: User write-only 7 6 5 4 3 2 1 0 W 0 0 0 0 0 0 0 RTS Reset: 0 0 0 0 0 0 0 0 R Figure 23-16. UART Output Port Command Registers (UOP1n/UOP0n) Table 23-12. UOP1n/UOP0n Field Descriptions Field Description 7–1 Reserved, must be cleared. 0 RTS Output port output. Controls assertion (UOP1)/negation (UOP0) of URTSn output. 0 Not affected. 1 Asserts URTSn in UOP1. Negates URTSn in UOP0. 23.4 Functional Description This section describes operation of the clock source generator, transmitter, and receiver. 23.4.1 Transmitter/Receiver Clock Source The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The 16-bit divider is used to produce standard UART baud rates. 23-16 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Table 23-11. UIPn Field Descriptions UART Modules Programmable Divider As Figure 23-17 shows, the UARTn transmitter and receiver can use the following clock sources: • An external clock signal on the DTINn pin. When not divided, DTINn provides a synchronous clock; when divided by 16, it is asynchronous. • The internal bus clock supplies an asynchronous clock source divided by 32 and then divided by the 16-bit value programmed in UBG1n and UBG2n. See Section 23.3.11, “UART Baud Rate Generator Registers (UBG1n/UBG2n).” The choice of DTIN or internal bus clock is programmed in the UCSR. DTOUTn On-Chip Timer Module DTINn UART UTXDn Tx Buffer Clocking sources programmed in UCSR TIN ÷1 Tx ÷ 16 TIN Rx 16-bit Divider URXDn ÷ 32 Internal Bus Clock fsys Rx Buffer Figure 23-17. Clocking Source Diagram NOTE If DTINn is a clocking source for the timer or UART, that timer module cannot use DTINn for timer input capture. 23.4.1.2 Calculating Baud Rates The following sections describe how to calculate baud rates. 23.4.1.2.1 Internal Bus Clock Baud Rates When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is: f sys Baudrate = ----------------------------------[ 32 x Divider ] Freescale Semiconductor Eqn. 23-1 23-17 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 23.4.1.1 UART Modules 80MHz Divider = ------------------------------- = 260 ( decimal ) = 0x0104 ( hexadecimal ) [ 32 x 9600 ] Eqn. 23-2 Therefore, UBG1n equals 0x01 and UBG2n equals 0x04. 23.4.1.2.2 External Clock An external source clock (DTINn) passes through a divide-by-1 or 16 prescaler. If fextc is the external clock frequency, baud rate can be described with this equation: f extc Baudrate = --------------------(16 or 1) 23.4.2 Eqn. 23-3 Transmitter and Receiver Operating Modes Figure 23-18 is a functional block diagram of the transmitter and receiver showing the command and operating registers, which are described generally in the following sections. For detailed descriptions, refer to Section 23.3, “Memory Map/Register Definition.” UARTn UART Command Register (UCRn) UART Transmit Buffer (UTBn) (2 Registers) W UART Mode Register 1 (UMR1n) R/W UART Mode Register 2 (UMR2n) R/W UART Status Register (USRn) R Transmitter Holding Register W UTXDn Transmitter Shift Register Receiver Holding Register 1 R FIFO Receiver Holding Register 2 External Interface Receiver Holding Register 3 UART Receive Buffer (URBn) (4 Registers) Receiver Shift Register URXDn Figure 23-18. Transmitter and Receiver Functional Diagram 23.4.2.1 Transmitter The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a character, UART sets USRn[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on UTXDn. It automatically sends a start bit followed by the programmed number of data bits, an 23-18 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 Using a 80-MHz internal bus clock and letting baud rate equal 9600, then optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source. After the stop bits are sent, if no new character is in the transmitter holding register, the UTXDn output remains high (mark condition) and the transmitter empty bit (USRn[TXEMP]) is set. Transmission resumes and TXEMP is cleared when the CPU loads a new character into the UART transmit buffer (UTBn). If the transmitter receives a disable command, it continues until any character in the transmitter shift register is completely sent. If the transmitter is reset through a software command, operation stops immediately (see Section 23.3.5, “UART Command Registers (UCRn)”). The transmitter is reenabled through the UCRn to resume operation after a disable or software reset. If the clear-to-send operation is enabled, UCTSn must be asserted for the character to be transmitted. If UCTSn is negated in the middle of a transmission, the character in the shift register is sent and UTXDn remains in mark state until UCTSn is reasserted. If transmitter is forced to send a continuous low condition by issuing a SEND BREAK command, transmitter ignores the state of UCTSn. If the transmitter is programmed to automatically negate URTSn when a message transmission completes, URTSn must be asserted manually before a message is sent. In applications in which the transmitter is disabled after transmission is complete and URTSn is appropriately programmed, URTSn is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually reenabled by reasserting URTSn before the next message is sent. Figure 23-19 shows the functional timing information for the transmitter. Freescale Semiconductor 23-19 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 UART Modules UART Modules C11 UTXDn C2 C3 C4 Break C6 Transmitter Enabled USRn[TXRDY] internal module select W2 W W C11 C2 C3 Start break W W W C4 Stop break W W C5 not transmitted C6 UCTSn3 URTSn4 Manually asserted by BIT-SET command Manually asserted 1 Cn = transmit characters 2 W = write 3 UMR2n[TXCTS] = 1 4 UMR2n[TXRTS] = 1 Figure 23-19. Transmitter Timing Diagram 23.4.2.2 Receiver The receiver is enabled through its UCRn, as described in Section 23.3.5, “UART Command Registers (UCRn).” When the receiver detects a high-to-low (mark-to-space) transition of the start bit on URXDn, the state of URXDn is sampled eight times on the edge of the bit time clock starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If URXDn is sampled high, start bit is invalid and the search for the valid start bit begins again. If URXDn remains low, a valid start bit is assumed. The receiver continues sampling the input at one-bit time intervals at the theoretical center of the bit until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the URXDn input is sampled on the rising edge of the programmed clock source. The lsb is received first. The data then transfers to a receiver holding register and USRn[RXRDY] is set. If the character is less than 8 bits, the most significant unused bits in the receiver holding register are cleared. After the stop bit is detected, receiver immediately looks for the next start bit. However, if a non-zero character is received without a stop bit (framing error) and URXDn remains low for one-half of the bit period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error, 23-20 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 C1 in transmission framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error and break flags in the USRn at the received character boundary. They are valid only if USRn[RXRDY] is set. If a break condition is detected (URXDn is low for the entire character including the stop bit), a character of all 0s loads into the receiver holding register and USRn[RB,RXRDY] are set. URXDn must return to a high condition for at least one-half bit time before a search for the next start bit begins. The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. The receiver places the damaged character in the Rx FIFO and sets the corresponding USRn error bits and USRn[RXRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RXRDY]. Figure 23-20 shows receiver functional timing. URXDn C1 C2 C3 C4 C5 C6 C7 C8 C6, C7, and C8 is lost Receiver Enabled USRn[RXRDY] USRn[FFULL] Internal module select Status Data (C1) C5 is lost (C2) (C3) (C4) Reset by command Overrun USRn[OE] URTSn1 Status Status Status Data Data Data Manually asserted first time, automatically negated if overrun occurs UOP0[RTS] = 1 1 UMR2n[RXRTS] Automatically asserted when ready to receive =1 Figure 23-20. Receiver Timing Diagram 23.4.2.3 FIFO The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the URXDn (see Figure 23-18). Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Therefore, data flowing from the receiver to the CPU is quadruple-buffered. In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break (RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By Freescale Semiconductor 23-21 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 UART Modules programming the ERR bit in the UART’s mode register (UMR1n), status is provided in character or block modes. USRn[RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom of the FIFO. The FIFO-full status bit (FFULL) is set if all three positions are filled with data. The RXRDY or FFULL bit can be selected to cause an interrupt and TXRDY or RXRDY can be used to generate a DMA request. The two error modes are selected by UMR1n[ERR]: • In character mode (UMR1n[ERR] = 0), status is given in the USRn for the character at the top of the FIFO. • In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO since the last RESET ERROR STATUS command. Status is updated as characters reach the top of the FIFO. Block mode offers a data-reception speed advantage where the software overhead of error-checking each character cannot be tolerated. However, errors are not detected until the check is performed at the end of an entire message—the faulting character is not identified. In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when the receive buffer is read. The USRn should be read before reading the receive buffer. If all three receiver holding registers are full, a new character is held in the receiver shift register until space is available. However, if a second new character is received, the contents of the character in the receiver shift register is lost, the FIFOs are unaffected, and USRn[OE] is set when the receiver detects the start bit of the new overrunning character. To support flow control, the receiver can be programmed to automatically negate and assert URTSn, in which case the receiver automatically negates URTSn when a valid start bit is detected and the FIFO is full. The receiver asserts URTSn when a FIFO position becomes available; therefore, connecting URTSn to the UCTSn input of the transmitting device can prevent overrun errors. NOTE The receiver continues reading characters in the FIFO if the receiver is disabled. If the receiver is reset, the FIFO, URTSn control, all receiver status bits, interrupts, and DMA requests are reset. No more characters are received until the receiver is reenabled. 23.4.3 Looping Modes The UART can be configured to operate in various looping modes. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs and in Section 23.3, “Memory Map/Register Definition.” The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. 23-22 Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: M5282EVB, MCF5214CVF66, MCF5216CVF66, MCF5280CVF66, MCF5280CVF80, MCF5281CVF66, MCF5281CVF80, MCF5282CVF66, MCF5282CVF80 UART Modules UART Modules Automatic Echo Mode In automatic echo mode, shown in Figure 23-21, the UART automatically resends received data bit by bit. The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. In this mode, received data is clocked on the receiver clock and re-sent on UTXDn. The receiver must be enabled, but the transmitter need not be. URXDn Input Rx CPU Disabled Tx Disabled UTXDn Output Figure 23-21. Automatic Echo Because the transmitter is inactive, USRn[TXEMP,TXRDY] is inactive and data is sent as it is received. Received parity is checked but not recalculated for transmission. Character framing is also checked, but stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected. 23.4.3.2 Local Loopback Mode Figure 23-22 shows how UTXDn and URXDn are internally connected in local loopback mode. Thi">
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Key features
ColdFire v2 core
64KB SRAM
512KB Flash memory
SDRAM support
Fast Ethernet controller
FlexCAN
I2C
QSPI
QADC
Low-power modes
Frequently asked questions
The supported devices are MCF5214, MCF5216, MCF5280, MCF5281, and MCF5282.
The devices have 64KB of SRAM and 512KB of Flash memory.
The key features include a ColdFire v2 core, SDRAM support, Fast Ethernet controller, FlexCAN, I2C, QSPI, and QADC.
The low-power modes include Wait, Doze, and Stop mode.
The ColdFire Flash Module (CFM) can be accessed using various registers to program, erase, and verify data.
The SCM controls various peripherals, including the internal peripheral system, memory, core reset, watchdog timers, and bus arbitration.
The clock module supports Normal PLL, 1:1 PLL, and external clock modes.
The devices use a 68K/ColdFire interrupt architecture with two interrupt controllers (INTC0 and INTC1) to manage interrupts from peripherals.
The EPORT provides interrupt/general-purpose I/O pins, with registers for configuring pin assignments, data direction, interrupt enable, and data access.
The Chip Select module provides control over the access of external memory devices and multiplexes address lines for different memory regions.
