STMicroelectronics ST-ONEMP Datasheet
Publicité
Publicité
ST-ONEMP
Datasheet
Fully integrated controller for multiport smart chargers
Product status link
ST-ONEMP
Product label
Features
• ZVS non-complementary active clamp flyback controller with synchronous rectification and USB-PD 3.1 PPS interface
• ARM® 32-bit Cortex®-M0+ MCU with 64 kB flash memory for digital power control and USB protocol
– FW programmable secondary side MCU controls both synchronous rectifier and ZVS active clamp flyback on the primary side to improve system efficiency in every condition
– High switching frequency operations in companion with MasterGaN power stage allow to use small size magnetic components, including planar transformers
• Reinforced galvanically isolated dual communication channel compliant with IEC
62368-1:
– 4 kV pk transient voltage
– 9.6 kV pk 1min hipot type testing
– 6.4 kV pk 1s hipot production testing
• 800 V high voltage startup with integrated input voltage sensing and Brownin/out functions
• Active input filter capacitor discharge circuitry for reduced standby power compliant with IEC 62368-1
• Fully Integrated USB-PD PHY with 24 V tolerant protection, and integrated load switch driver
Application
V
INAC
• USB-PD chargers and adapters up to 100 W for smartphones, tablets, laptops and other handheld equipment
Figure 1. Typical system block diagram
ST-ONEMP
Description
2 nd
PORT
CTRL
V
OUT2
V
BUS
TYPE-C
USB
The ST-ONEMP is the world’s first digital controller embedding ARM Cortex M0+ core, an offline programmable controller with synchronous rectification, and USB PD
PHY in a single package. Such a system is specifically designed to control ZVS non-complementary active clamp flyback converters to create high power density chargers and adapters with a first USB-PD interface and a second output.
The device includes an active clamp flyback controller and its HV startup on the primary side, a microcontroller and all the peripherals required to control the conversion and the USB-PD communication on the secondary side. The two sides are connected through an embedded galvanically isolated dual communication channel. By using a novel non-complementary control technique and specifically designed power modes the device allows to reach both high efficiency and low no load power consumption
The device is delivered with a pre-loaded firmware which handles both the power conversion and the communication protocols for USB-PD including optional PPS and electronically marked cable management.
The output power and available PDOs on the USB-PD port can be changed according to a power sharing pin input to allow power sharing with a second output.
A dedicated memory stores a default device configuration during factory process.
The user can change or adapt this memory area to fit the final product specifications.
DS13989 - Rev 1 - December 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1
ST-ONEMP
ST-ONEMP block diagram
ST-ONEMP block diagram
Figure 2. ST-ONEMP block diagram
LEB
PV3V PVCC PGND HV
OVP
3.3V
LDO
SS_MODE
IS_ON
BURST
Brown-out,
X-Cap discharge, startup SM,
HV generator ON/OFF
OTP
OVP
OC2
AC_IN
HON_SU
SS_MODE
SS TImeout
20u
1.24
HSPWM
LSON
IPK
DEMODULATOR
HON
HSPWM
HON_SU
EN
SS_MODE
IS_ON
CK_SU
LSON
BLANKING
LON
Q
S
R
IPK
OTP
20u
0.6V
Startup
Timer
POTP DT OSC
OC2
-
+
PWM
-
+
0.9V
SS_Timeout
ISEN
- 0.6V
+
SS
2u
VZCD
SR1V
SVCC
1V
IZCD
SPGND
ISO TX
Temp sns
Int Temp
SRVDS
VOPART
VCCPART
GPIO0
GPIO1
Wakeup
VDRV
VDRV
Clamp
SMEDs
SCHEDULER
12 bit
ADC
VCCPART
WakeRef
Oring FET
Driver & Ch. pump
64kB program memory +
8kB boot
8kB SRAM
Bleeder ctrl
Watchdog
Power & clock manager (sys ctrl)
GPIO
TYPE-C phy
I2C / UART
CORTEX M0+
LDO &
SVCC
Ch pump
66kHz clk
OSC &
PLL
VOSNS
SVCC
VDRV
PUMP
SV3V
V1V2
CC1
CC2
GPIO1
GPIO0
DS13989 - Rev 1 page 2/40
2
ST-ONEMP
Pin connections and description
Pin connections and description
Figure 3. Pin connection (top view)
LON
EN_OUT
OSC
DT
LEB
ISEN
PGND
HV nc nc nc
POTP
SS
OVP
PVCC
PGND
P3V3
HON
GPIO0
GPIO1
CSP
CSM
V1V2
SSGND
SV3V
SVCC
VOSNS
CC1
CC2
SSGND
ORGD
SPGND
SRGD
SRVDS
VDRV
PUMP
1
2,3,4
5
6
7
8
9
10
11
12
13
Pin
Table 1. Pin functions nc
Name
HV
POTP
SS
OVP
PVCC
PGND
P3V3
HON
LON
EN_OUT
Function
High voltage start-up generator / ac voltage sensing input. The pin, able to withstand 800 V, must be connected to the ac side of the input bridge via a pair of diodes to sense the ac input voltage.
When the voltage on the pin is higher than V
HVStart connected between the pin PVCC and PGND.
, an internal pull-up circuit charges the capacitor
The pin is used also to sense the ac voltage, which is used by ac brown-out and X-cap discharge functions.
High voltage spacer. The pin is not connected internally to increase spacing between the highvoltage pin and the other pins.
Primary side overtemperature protection. Pulling this pin below V
POVTH
shuts down the IC.
Soft-start setting. Connect a capacitor to PGND to set the soft-start duration.
Aux winding sense for overvoltage protection.
Primary side supply voltage pin. The internal high voltage generator allows to charge an external capacitor connected between this pin and PGND before the converter starts up. A small bypass capacitor (0.1 µF typ.) to PGND must be placed close to the pins to get a clean bias voltage.
Primary side ground. Reference for I/Os.
Primary side internal supply regulator bypass capacitor.
High-side gate-drive control signal.
Low-side gate-drive control signal.
Enable signal for an external driver. Improves efficiency during bursts in case the driver supports this functionality.
DS13989 - Rev 1 page 3/40
DS13989 - Rev 1
ST-ONEMP
Pin connections and description
29
30
31
32
33
21
22
23
18
19
20
14
15
16
17
24
25
26
27
28
34
35
36
Pin Name
OSC
DT
LEB
Function
Oscillator pin. A resistor from the pin to PGND defines the switching frequency during the initial soft-start.
Deadtime programming. A resistor from this pin to PGND sets the deadtime during soft-start and minimum deadtime during functional mode.
Leading edge blanking time programming. A resistor from this pin to ground sets the leading edge blanking time for the ISEN comparator.
ISEN
Current sense (PWM comparator) input. The voltage on this pin is compared with an internal reference to turn off LON.
Primary side signal ground. Reference for analog signals.
PGND
PUMP
VDRV
Charge pump pin 1. Used to power the IC when SVCC drops below 5 V.
Driver supply.
SRVDS Output winding voltage sense. Connect to sync FET drain through a clamping MOSFET.
SRGD Synchronous rectifier gate driver.
SPGND Secondary side power ground. Current return for the sync FET gate-drive current.
ORGD
Load switch gate drive.
The pin controls the gate of a N type MOSFET on the positive output terminal to disconnect the output.
SSGND Secondary side signal ground.
CC2
CC1
USB Type-C CC2 pin. Used for USB-PD compliant communication or alternate function as
DN / GPIO3 / I2C-SCL / UART-TX.
USB Type-C CC1 pin. Used for USB-PD compliant communication or alternate function as
DP / GPIO2 / I2C-SDA / UART-RX.
VOSNS
Output voltage sense. Used to sense the voltage at the power supply output port (after the load switch). The pin is used also for the bleeding function.
Secondary side VCC. The device senses and controls the converter output through this pin.
SVCC
SV3V 3.3 V Regulated supply for the IC. Connect a 1μF capacitor from this pin to SSGND.
SSGND Secondary side signal ground.
V1V2
CSM
CSP
GPIO1
GPIO0
1.2 V regulated supply for the IC. Connect a 4.7μF capacitor from this pin to SSGND.
Output current sense pin. Connect to the negative side of sense resistor on the ground path.
Output current sense pin. Connect to the positive side of sense resistor on the ground path to sense the current drawn by the load.
Power sharing input pin. Can be reconfigured as general purpose digital I/O, digital interface, analog input or alternate function as
Power Good for the second output regulator. Can be reconfigured as general purpose digital I/O, digital interface, analog input or alternate function as
SWDIO-TMS / UART-RX / I2C-SDA.
The pin is also used to enter in programming/boot mode at IC startup. Connect a 100kΩ pullup to SV3V to avoid unwanted entry in boot mode at startup, unless this function is configured as disabled.
1. The firmware loaded on ST-ONEMP configures the pins as either USB-PD or programming interface. The default configuration is USB-PD
2. Alternate functions are not supported by the preloaded firmware.
page 4/40
3
ST-ONEMP
Electrical ratings
Electrical ratings
Stresses above the absolute maximum ratings listed in
Table 2. Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
V
HV
V
PVCC
V
PV3V
I
OVP
V
HON
, V
LON
, V
EN_OUT
V
AMRPri
V
CC1
, V
CC2
V
VOSNS
, V
SVCC
V
PUMP
V
ORGD
V
CSP
, V
CSM
V
SV3V
V
V1V2
V
VDRV
V
SRGD
V
SRVDS
V
GPIO
V
SPGND
Table 2. Absolute maximum ratings
Pin
HV
PVCC
P3V3
OVP
Parameter
Voltage range (referenced to PGND)
Value
-1 to 800
Primary side supply voltage
3.3 V supply range
-0.3 to 18
-0.3 to 3.6
Maximum clamp source/sink current on OVP -200 to 200
-0.3 to 5.5
-0.3 to 3.6
HON, LON, EN_OUT
Other primary side pins
Voltage range
Primary side analog Inputs & Outputs
Secondary side voltages, referred to SSGND
CC1, CC2 USB connector IOs
VOSNS, SVCC Output voltage sense & VCC
PUMP
ORGD
Charge pump pin, referred to SPGND
Oring FET gate driver voltage range
-0.3 to 24
-0.3 to 24
-0.3 to 15
-0.3 to 29
CSP,CSM
SV3V
V1V2
VDRV
SRGD
SRVDS
GPIO0,GPIO1
SPGND
Current sense voltage range
3 V supply voltage range
1.2 V supply voltage range
Secondary side driver voltage
Sync FET gate driver voltage range
Drain sense voltage range
GPIO voltage
Power ground vs. signal ground
-0.3 to 3.6
-0.3 to 3.6
-0.3 to 2
-0.3 to 24
-0.3 to 18
-2 to 28
-0.3 to 3.6
-1 to 1
Unit
V
V
V
V
V
μA
V
V
V
V
V
V
V
V
V
V
V
V
Table 3. Maximum operating conditions
Symbol
V
HV
V
PVCC
C
IO
V
CSP
, V
CSM
V
SVCC
, V
VOSNS
, V
VDRV
Pin
HV
PVCC
Parameter
Voltage range (referenced to PGND)
Primary side supply voltage
HON, LON, EN_OUT Capacitive load on primary side digital outputs
CSP,CSM Current sense voltage range
SVCC, VOSNS, VDRV Secondary side voltage range
Value
-1 to 450
-0.3 to 16
0 to 10
-0.3 to 1
-0.3 to 22.5
Unit
V
V pF
V
V
DS13989 - Rev 1 page 5/40
4
ESD immunity levels
Mode
HBM
CDM
Pin
All
All
Table 4. ESD immunity levels
Reference specification
According to JS-001
According to JS-002
Value
+/- 2
+/- 500
ST-ONEMP
ESD immunity levels
Unit kV
V
DS13989 - Rev 1 page 6/40
ST-ONEMP
Thermal data
5
Thermal data
Table 5. Thermal data
Symbol
R th j-amb
T
J
T
STG
1. Simulated, device mounted on 1s1p board
Parameter
Thermal Resistance, Junction-to-ambient
Junction Temperature Range
Storage Temperature
Max. value
65
-40 to 125
-55 to 150
Unit
°C/W
°C
°C
DS13989 - Rev 1 page 7/40
6
ST-ONEMP
Safety data
Safety data
Table 6. Insulation safety data according to IEC 62368
Parameter
Insulation type
Transient voltage
Electric strength test (type test)
Electric strength test (routine test)
Clearance
Creepage
Value
Reinforced
4 kV
9.6 kV / 1 min
6.4k V / 1 sec
8 mm
8 mm
Table 7. Insulation safety data according to UL 1577
Isolation Voltage
Transmitter maximum current
Receiver maximum current
Transmitter maximum power
Receiver maximum current
Maximum operating ambient temperature
Maximum junction temperature
Maximum storage temperature
Maximum data rate
Parameter Value
3770 Vrms
11 mA
91 mA
1100 mW
130 mW
85 °C
125 °C
150 °C
1 MHz
Maximum line voltage
Overvoltage category
External capacitor value
Series resistor value
Table 8. X-Cap discharge safety data according to IEC 62368
Parameter Value
240 Vrms + 10%
II
47 nF – 2.2 μF
330 Ω – 4700 Ω
DS13989 - Rev 1 page 8/40
7
ST-ONEMP
Electrical data
Electrical data
T
J
= -40 to 125 °C, V
PVCC
= 12 V, V
SVCC
= 5 V , unless otherwise specified.
Symbol Parameter
Table 9. Electrical characteristics
Test Condition
Primary side
Min.
Supply voltage
V
PVCCOn
Turn-on threshold
V
PVCCOff
UVLO / Restart threshold
V
P3V3
Primary side 3V3 regulator voltage
Supply current
I pq
Quiescent current
I cc
Operating supply current
I burst
Current during burst mode
I qdis
Shutdown quiescent current
High voltage start-up generator
V
V
V
HV
HVStart
PVCC_SO
HV breakdown voltage
HV pin start-up voltage
Switchover threshold
Iload < 4 mA
Before turn-on
Fsw=300 kHz,
R
DT
=R
LEB
=12 kohm,
C
EN
=C
LON
=C
HON
=10 pF
Device latched
I
HV
< 100 µA 800
13
6
3.1
I
HVON
ON-state current
I
HVOFF
Leakage current
(Off-state)
X-cap discharge
T
XCDDET
Detection time
V
HVmin
Peak residual voltage
I
HVDIS
Discharge current
V
PVCCClamp
PVCC clamp voltage during X-Cap
AC brown-in/out
V
HVpk_BO
Brown-out threshold
V
HVpk_BI
Brown-in threshold
V
HV
> V
HVStart
V
PVCC
> V
PVCC_SO
V
HV
> V
HVStart
V
PVCC
< V
PVCC_SO
V
HV
= 400 V
I
HV,DIS
> 4.2 mA
V
HV
> 45 V
Peak voltage
Peak voltage
5
94
108
Typ.
Max.
Unit
2.8
1
20
30
1
7
64
7
100
115
14
6.5
3.3
15
7
3.5
0.55
1.1
0.57
mA mA mA mA
V
V
V
45
106
122 ms
V mA
V
V
V
V
V
V mA mA
μA
DS13989 - Rev 1 page 9/40
DS13989 - Rev 1
Symbol
V
HVpk_BI
Parameter
Brown-in/out hysteresis
T
T
BODG
DB_BI
Brown-out deglitch time
Brown-in deglitch time
Overtemperature protection
V
POVTH
Overtemperature threshold
POTP pull-up current
I
POTP
Soft-start
I
SS
Soft start current
T
DT_SS
Deadtime duration during soft-start
Test Condition
Peak voltage
Pin falling (temperature rising)
Pin rising (temperature falling)
V
POTP
= 0.6 V
T
OFFSS
T
LEB
Off-time duration during soft-start
V
I
SSEND
OVTH
Soft-start timeout voltage
Overvoltage protection
V
OVTH
Overvoltage threshold (for flyback aux winding)
Overvoltage threshold (for forward aux winding)
V
OVCLAMP
Clamping voltage on
OVP pin
T
OVFILT
OVP time filtering
Overcurrent protection
V
OCTH
Overcurrent threshold
Burst mode
T
IsoPWMTO
IsoPWM absence time to trigger sleep mode entry
Current mode unit
V
G
TV
IPKCLAMP
Time to voltage conversion gain
Maximum threshold
Blanking time (from
LON rising edge)
V
T
CSDEL
PCSOFF
Total time between
CS crossing and
LON turn-off
CS comparator offset
V
SS
= 0.25 V
R
DT
= 100 kΩ
R
DT
= 12.1 kΩ
R
OSC
= 470 kΩ
R
OSC
= 47 kΩ
OVP sourcing 20 uA
OVP sinking 20 uA
From PWM falling edge
IsoPWM Ton = 380 ns
R
LEB
= 100 kOhm
R
LEB
= 12.1 kΩ
Including driver delay. dV/dt = 2 V/us.
Time to 50%
Min.
48
0.57
1.12
18
1.12
0.8
-22
0.59
0.5
240
33
1.7
240
32
8
0.8
0.55
17
-0.1
3.1
2
0.9
60
0.66
0.525
300
41
0
2
300
40
10
1
0.6
1.24
20
0
3.3
4
Typ.
15
60
500
0.6
1.24
20
1.36
23
0.1
3.5
6
1.0
2.3
360
48
12
1.2
0.65
ST-ONEMP
Electrical data
Max.
72
Unit
V ms
μs
0.63
1.36
22
V
μA
μA ns ns
μs
μs
V
μs
0.73
0.55
360
49
25
22
V/μs
V ns ns ns mV
V
μA
V
V
μs
V page 10/40
DS13989 - Rev 1
Symbol
T
DT
Parameter
LS to HS deadtime duration during normal mode
R
LEB
OPEN protection (ROP)
R
LEB_OPEN
Maximum R
LEB resistance to trigger the protection
IO electrical data
V
OH
LON/HON high voltage
V
OL
LON/HON low voltage
Supply voltage
V
SVCCOP
Secondary side operative range
V
V
SVCCON
SUVLO
Secondary side turnon threshold
Secondary side
UVLO threshold
V
SV3V
Secondary side 3 V regulator voltage
V
I
SV3V
CPON
Maximum current capability from SV3V for external circuitry
Charge pump turn-on threshold
(hysteretic mode)
V
CPOFF
Charge pump turn-off threshold
(hysteretic mode)
Supply current
I
SVCC
Operating supply current
I sleep
Deep sleep mode supply current
SR gate driver
V
SRON
SR driving voltage
T
SRPROP
I
I
T
T
SRRISE
SRFALL
DRVSRC
DRVSNK
Driver propagation delay
Driver rise time
Driver fall time
Driver source current
Driver sink current
Test Condition
R
DT
= 100 kΩ
R
DT
= 12.1 kΩ
Pin sourcing 4 mA
Pin sinking 4 mA
V
< I
Secondary side
SV3V
SVCC
(2 mA)
> 3.3
In burst mode
In burst mode
SVCC=5 V
= 11
SRDRVCONF
SRDRVCONF
SRDRVCONF
Turn-on, time to 10%
Turn-off, time to 90%
10% to 90%, 1 nF load
90% to 10%, 1 nF load
Min.
120
15
Typ.
150
22
ST-ONEMP
Electrical data
Max.
190
30
Unit ns ns
0.8
1.0
1.25
MΩ
4
0.4
V
V
3.05
3.3
3.5
3
3.2
3.1
2
8
8.4
22.5
3.7
3.05
3.3
V
V
V
V
V
V mA
18
1.4
15
40
20
0.45
0.6
9
11
5
7
20
20
65
40 ns
A
A
V
V
V
V ns ns ns mA mA page 11/40
DS13989 - Rev 1
ST-ONEMP
Electrical data
Symbol Parameter
Load switch gate driver
I
ORON
Load switch turn-on current
Test Condition Min.
V
ORON
Load switch-on voltage
Referred to SVCC
SVCC < 12 V
Referred to SVCC
SVCC >= 12 V
4
4
Current sense
V
CSM
V
SCSOFF
Current sense input offset
V
CSFSR
CMRR
Current sense full scale range
Common mode rejection
Voltage sense
V
FSR
Full scale range for
SVCC & VOSNS reading
Gain error
Offset
Adc
N bit
Number of bits
INL Integral non linearity
DNL
Differential non linearity
Wake-up comparator
Including ADC accuracy
Input signal > 4 mV
CSP – CSM voltage
100 kHz – 1 MHz, 10 mV signal (4)
0
-0.5
50
Including ADC contribution T j
= 0 to
125 °C.
Including ADC contribution T j
= 0 to
125 °C
-1
-0.2% * V
FSR
3% V
REF
3% V
REF
< V
IN
< V
IN
< 95% V
< 95% V
REF
REF
-3
-2
V
WUP
Wake-up threshold
DAC
= 6 V
DAC (2) = 0100, FSR (5) = 12 V
DAC (2) = 0101, FSR (5) = 12 V
= 12 V
DAC
= 24 V
= 24 V
DAC
= 24 V
DAC (2) = 1000, FSR (5) = 24 V
Typ.
10
5
5
25
6
12
24
12
8.82
8.91
9
9.09
4.9
4.95
5
5.05
11.76
11.88
12
12.12
14.7
Max.
7
6.5
50
0.5
1
0.2% * V
FSR
3
2
Unit
μA
V
V mV dB
V
LSB
LSB
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
% mV mV page 12/40
DS13989 - Rev 1
Symbol
V
WUP
Parameter
Wake-up threshold
Test Condition
DAC (2) = 1001, FSR (5) = 24 V
DAC (2) = 1010, FSR (5) = 24 V
DAC (2) = 1010, FSR (5) = 24 V
DAC (2) = 0000, FSR (5) = 24 V
DAC (2) = 0001, FSR (5) = 24 V
DAC (2) = 0010, FSR (5) = 24 V
= 24 V
V
WUPACC
Wake-up threshold accuracy
V
WUPHYSY
Hysteresis
= 10, FSR
HYST
= 11, FSR
= 6 V
SR comparators
V
THSR1V
SR1V comparator threshold
T
DSR1V
SR1V comparator delay
V
THIZCD
IZCD threshold
V
T
DIZCD
DYNZCD
IZCD comparator delay
VZCD dynamic comparator threshold
Bleeding resistor
I
R
BLEED
CCBLD
Clock
SVCC / VOSNS
Bleeding current
CC Bleeder resistance
F
CK
Master clock frequency
F
CKLF
Low frequency clock
Internal temperature sense
T
ACC
Temperature reading accuracy
GPIO electrical data
V
V
OHGPIO
OLGPIO
GPIO0/1 high voltage
GPIO0/1 low voltage
V
V
IHGPIO
ILGPIO
GPIO0/1 input high voltage
GPIO0/1 input low voltage
DVS falling @ 0.2 V/ns
DVS rising @ 0.1 V/μs
Negative step starting from SVCC – 1
V
T j
T
j
= 0, V > 0.8 V
= 1, V > 0.8 V
V > 0.8 V
= 0 – 125 °C
= -40 – 125 °C
ADC reading
Pin sourcing 8 mA, digital mode
Pin sinking 8 mA, digital mode
Digital mode
Digital mode
Min.
-0.9%
0.7
-5
7
14
126.7
126.7
60
-10
2.4
2
Typ.
14.85
15
15.15
19.6
19.8
20
20.2
13.5
18
24
34.5
10
20
2500
132
132
66
1
20
0
50
1
1.3
30
2
80
4000
V
V
V
V
V ns mV ns
V mA mA
Ω
136.3
137.3
72
MHz
MHz kHz
10
0.4
0.8
K
ST-ONEMP
Electrical data
Max.
V
V
V
V
Unit
V
V
V
0.9% mV mV mV mV page 13/40
DS13989 - Rev 1
ST-ONEMP
Electrical data
Symbol
VCONN
Parameter
R
VCONN
Vconn switch resistance to SVCC
CC cable connection wakeup
V
THCCWUP
CC wake-up threshold
CC Communication Wakeup
CC communication threshold
CC communication threshold
CC OVP
V
CCOVP
CC pullup
CC OVP threshold
I
CCPUVMAX
CC Pull-up current at
V
CCPUMAX
V
CC
Test Condition
SVCC = 5 V
= V
Rising
Falling
CCPUMAX
= 2.75 V
Min.
2.5
5.5
30
Typ.
20
2.6
0.85
0.25
6
Max.
2.7
Unit
Ω
V
V
V
V
μA
I
CCPU
CC Pull-up current
CC1
= V
CC2
= 2.7V
CC1
= V
CC2
= 2.7V
ICCSET
= 11 V
CC1
= V
CC2
= 2.7V
64
166
303
80
180
330
96
195
360
μA
μA
μA
1. Iload is the current drawn by external circuits connected to SV3V pin.
3. Current sense accuracy is not guaranteed if CSM pin voltage is beyond this range
4. Guaranteed by design.
5. This internal peripheral register is managed by the firmware depending on the output voltage setpoint. See
6. This internal peripheral register is managed by the firmware. See
7. This internal peripheral register is managed by the USB-PD protocol FW according to the standard page 14/40
8
8.1
Device operation
Typical application schematic
The following image is a simplified schematic for the typical application.
Figure 4. Typical configuration
AC
AC
C
BULK
C
CLAMP n:1
HS
LS
SR
R
SNS_PRI
R
ZCD_PU
V
DRV
R
ZCD
V
OUT
C
OUT
R
SNS_IOUT
Second Port
Controller &
DC/DC
OR
C
OUT
ST-ONEMP
Device operation
PGND
P3V3
LEB
GPIO0 (PSHARE)
GPIO1 (PGOOD)
CC1/2
V
DRV
V
OUT
•
•
•
•
The ST-ONEMP is a very intergrated IC, which needs a few external components to build a complete system. On the primary side:
•
An AC full wave power rectifier connected to a bulk capacitor.
Two rectifier diodes to provide HV voltage to ST-ONEMP IC both for high voltage startup and AC brownout and disconnection detection.
An integrated half bridge power stage (e.g ST MasterGaN) or Gate driver + FETs connected to the transformer primary winding.
A clamp capacitor to store the residual energy in the transformer leakage inductance.
An auxiliary winding power supply for the IC PVCC, also used to perform overvoltage function during the soft-start.
•
•
On the secondary side:
•
•
•
A synchronous rectifier FET is connected to the SRGD pin.
A cascode FET connected to the SRVDS pin to provide synchronous rectifier drain voltage sense while limiting the voltage on the pin below its AMR.
An N-channel MOSFET connected to ORGD pin used as load switch to disconnect the output voltage as required by USB-PD power supplies.
A sense resistor is connected to CSM/CSP pins to read the output current.
A capacitor and two diodes connected to the PUMP pin to implement a charge pump providing the driving voltage to the synchronous rectifier.
DS13989 - Rev 1 page 15/40
8.2
8.2.1
8.2.2
8.2.2.1
8.2.2.2
ST-ONEMP
External component selection
The second port controller and DC/DC converter are connected on the SVCC, before the load switch and before the current sense resistor. Using this configuration, both the load switch and the current sense act only on the main TypeC output. The GPIO0 pin is driven by a logic signal providing information about the connection of the second port: depending on its logic level, the ST-ONEMP chooses two different sets of PDOs and APDOs providing either full or reduced power on the main TypeC port to implement a power sharing scheme. The GPIO1 is used to keep the DC/DC converter off during startup until the output voltage is stable.
External component selection
Symbols used in this section
I pk
peak magnetizing current
L p
primary side inductance
L k
primary side leakage inductance
V i
converter input voltage
V o
converter output voltage n transformer turns ratio
T sw
switching period f sw
switching frequency
P o
converter output power
D duty cycle
C ph
phase (switching) node total capacitance (typically, switch C oss
+ transformer input capacitance)
C clamp
clamp capacitor value
V priPk
peak primary side voltage f samp
control loop sampling frequency
C out
output capacitor value
V drop
voltage drop during step load transient
I step
load transient current step
Transformer design
Turns ratio
The ideal operating condition for a flyback is with duty cycle around 50%. The turns ratio is anyway limited by the voltage capability of the primary side switches.
As a first approximation, the turns ratio can be selected considering the maximum input and output voltage and selecting the highest value for which the voltage stress on the primary side switches is acceptable.
The voltage stress can be calculated as
VpriPk = Vi + nVo + Ipk
Lk
Cclamp
(1)
The last term in the equation can be ignored for a first approximation, then considered after component selection.
Typical turns ratio value for a wide input range, 20V output USB-PD application is around 6.
Primary side inductance – switching frequency
The ST-ONEMP Non complementary active clamp operates in a similar way as a quasi-resonant flyback, so as a first approximation the relation between the switching frequency and the primary side inductance can be calculated as
Lp =
VinVo
Vi − nVo
2
1
2fswPo
For a more accurate calculation the clamping time and the deadtimes must be considered, especially for high frequency converters. The following equation can be used to calculate the switching frequency when the system operates in ZVS:
(2)
DS13989 - Rev 1 page 16/40
8.2.3
8.2.4
8.2.4.1
ST-ONEMP
External component selection
Tsw =
2Lp Vi + Vor
Pi Vi + nVo
VinVo
VinVo
+
Cpℎ Vi2 − n2Vo2
Lp
+
π LpCpℎ
2
(3)
Clamp capacitor selection
The clamp capacitor value determines the resonance period between the capacitor and the transformer leakage
inductance during phase 5 of the switching cycle (see Section 8.5.1
).
It is suggested to choose the clamp capacitor value so that the phase 5 lasts approximately 15% of the switching cycle in high line, high output voltage conditions, so
2
Cclamp ≈
0.15Tsw
π2Lk
(4)
Secondary side drain sensing
The SRVDS pin is used for sensing the synchronous rectifier drain voltage to control turn-on and turn-off of the synchronous rectifier MOSFET and to sense the drain oscillations to operate in valley switching. The first function is performed by comparing SRVDS voltage with a 1 V and a 0 V internal threshold, while the second function is implemented by comparing the SRVDS voltage with SVCC.
A proper external clamp circuit is required to limit the voltage on the pin below its operative range while being able to correctly sense the MOSFET drain voltage from 0 V up to SVCC. A signal mosfet with gate tied to VDRV as shown the typical configuration schematic (see
) is the suggested solution. The resistors R
ZCD
and
R
ZCDPU
in the schematic can be added to offset the signal and anticipate the IZCD comparator triggering.
SRVDS comparators
The SRVDS pin has three comparators connected to it which are used to control the switching cycle.
The following figure shows the waveforms associated to the SRVDS comparators when the system is operating in valley skipping mode. The SR drain voltage is drawn as a light blue line, the clamped voltage on the SRVDS pin is shown in dark blue.
Figure 5. SRVDS sensing waveforms
Isec
Ipri
Vlsd
Vsrd
Vsrvds
V
DYNZCD
V
THSR1V
Vlsg
Vhsg
Vsrg
1 2 3 4
VZCD : This comparator is used to count the switching node oscillations in valley skipping mode and to obtain valley turn-on. The comparator has a dynamic threshold, detecting when the voltage on SRVDS drops more than
V
DYNZCD
below the last peak reached. Referring to Figure 5 , the comparator is triggered in instant 3 and 4
DS13989 - Rev 1 page 17/40
8.2.5
8.3
8.4
ST-ONEMP
High voltage startup
IZCD : This comparator compares SRVDS with SSGND. It is used to detect the zero crossing of the current during
SR mos conduction phase. Referring to Figure 5 , the comparator is triggered in instant 2.
SR1V : This comparator compares SRVDS with a 1 V threshold. It is used to detect when the primary side low side FET is turned off, making the voltage across the SR MOS drop. This comparator commands the turn-on of
the SR mos. Referring to Figure 5 , the comparator is triggered in instant 1.
Secondary side current sense resistor
The secondary side current sense has a full-scale range V
CSFSR
equal to 25 mV. The current sense is chosen according to the formula:
RsenseSec <
VCSFSR
IMAX
(5)
High voltage startup
The ST-ONEMP is equipped with internal HV start-up circuitry dedicated to supplying the IC during the initial start-up phase, before the self-supply winding is operating. An external capacitor connected to the PVCC pin is charged by the HV start-up circuitry, connected to the HV pin.
When the power is applied to the circuit and the voltage on the input is high enough, the HV generator is sufficiently biased to start operating, thus it draws the current I
HVON
through the HV pin and charges the capacitor connected between PVCC pin and ground. This charging current is limited at 1 mA in case the voltage on PVCC is lower than V
PVCC_SO
, in order to prevent excessive IC dissipation if the pin is accidentally shorted to ground.
As the PVCC voltage reaches the start-up threshold (V
PVCCOn
) the chip starts operating, and the control logic disables the HV generator.
The IC is powered by the energy stored in the PVCC capacitor until the auxiliary winding develops a voltage high enough to sustain the operation.
Soft-start
As soon as the proper conditions for startup are met, the primary side controller performs a soft-start autonomously until the secondary side is powered and able to take control of the switching.
During soft-start the IC operates in constant off-time, peak current mode. The user can set the off-time by connecting a resistor from the OSC pin to ground.
The peak current during soft-start is determined by comparing the SS pin and ISEN pin voltages. Connecting a capacitor to the SS sets the soft-start duration.
The primary side controlled soft-start ends as the secondary side takes control of the conversion.
During the soft-start the high-side is controlled in complementary mode, with deadtimes determined by a resistor connected between DT and ground. Note that during soft-start both the deadtimes are equal to T
DT_SS approximately double the value used in normal mode for LS to HS.
which is
As the voltage on the secondary side reaches V
SVCCON
, the secondary side IC boots up, takes control of the
conversion and the converter starts to operate in normal mode as described in Section 8.5.1
. The secondary side controller continues the soft-start operating in closed loop and ramping the SVCC voltage to 5 V, then the soft-start ends.
Figure 6. Soft-start waveforms: primary side controlled soft-start phase
Figure 7. Soft-start waveforms: switch to secondary side control
DS13989 - Rev 1 page 18/40
8.5
8.5.1
ST-ONEMP
Switching modes
Switching modes
The following sections describe the switching modes which are used by the device depending on the output power to be delivered.
Normal switching mode
The controller operates a non-complementary active clamp converter. The main waveforms are shown in
.
Figure 8. Normal operation waveforms
Isec
Ipri
Vlsd
Vlsg
Vhsg
Vsrg
1 2 3 4 5 6 7
The converter operation is similar to a traditional QR flyback, with the addition of a clamp switch to recover the energy in the transformer leakage inductance at low-side turn-off and uses the energy to obtain soft switching at low-side turn-on. In particular, the high-side is turned on for a time proportional to the input/output conversion ratio in order to limit the circulating current to what is required to obtain soft switching at low-side turn-on. The synchronous rectifier is kept on after high-side turn-on to obtain zero secondary side current before the high-side is turned off and a new cycle is started through a resonance between the leakage inductance and the clamp capacitor.
The phases are as follows:
1.
LS turn-on. The on timing and peak current are defined by the secondary side controller. The phase terminates when the primary side peak current comparator is triggered.
2.
Deadtime. A deadtime is inserted between LS turn-on and HS / SR turn-on.
3.
SR turn-on / first HS turn-on. When the secondary side ZCD12 comparator is triggered, the secondary side commands the turn-on of both SR and HS switches. During this phase the current in the primary side leakage inductance drops to 0, while the energy is stored in the clamp capacitor. The HS switch turn-on is not strictly required but improves the efficiency of the system by avoiding conduction through the HS body diode. The duration of the first HS pulse can be controlled by the configuration parameters.
4.
During phase 4 current flows on the secondary side through the SR FET. The phase terminates when the
IZCD comparator is triggered (current on the secondary side reached 0).
5.
HS is turned on to recover the energy stored in the clamp capacitor in phase 3 and to store energy in the primary side inductance to force a soft switching. During this phase the leakage inductance resonates with the clamp capacitor, creating a bump on the output current. When the current reaches 0 the SR is turned off.
The duration of this phase is configured through programmable parameters.
6.
Extra HS turn-on time may be added to increase the energy stored in the magnetizing inductor, in particular at low output and high input voltage. The firmware calculates the duration of this phase based on parameters.
7.
Deadtime. The deadtime between HS and LS is controlled by the secondary side through the parameter
DT_HVG_LVG.
DS13989 - Rev 1 page 19/40
8.5.1.1
8.5.1.2
8.5.2
ST-ONEMP
Switching modes
Deadtime
Deadtime between LS on and HS on is set by connecting a resistor between DT pin and ground, according to the following formula:
(6)
Deadtime between HS and LS is instead controlled by the controller parameter DT_HVG_LVG according to the formula:
(7)
Where F
CK
is the IC clock frequency of 132 MHz.
Synchronous rectification voltage
The synchronous rectifier turn-on voltage is clamped to a programmable value. The user can choose the driving voltage which yields the best application performance.
The driver is powered from the VDRV pin.
Skip mode
In order to improve the efficiency at medium load, the controller enters in valley skipping mode when the peak current falls below a programmable value.
While in skip mode the controller keeps the peak current approximately constant at the skipping mode entry point.
If the frequency falls below approximately 20 kHz, the controller starts dropping the peak current while keeping the frequency limited between 20 kHz and a programmable value (typ. 50 kHz).
Figure 9. Transition between normal mode, skip mode and burst mode f sw
20kHz
8.5.3
8.5.3.1
I pk
Normal mode i pkMinSkip
I load
Burst Valley skipping
Burst mode
While in skip mode, if the frequency drops below F
CK
/6500 (approximately 20 kHz) the system enters burst mode.
While in burst mode the controller generates bursts of pulses with a programmable peak current. The number of pulses generated depends on the output voltage and can be programmed through the parameters.
The system exits burst mode and comes back to normal operation when the average time between bursts drops below a programmable time.
Deep burst
When the regulated output voltage is 5 V, 9 V, 15 V or 20 V, all the IC functions are shut down between the bursts, leaving only a dedicated comparator to wake up the system when a new burst is required. In this condition, the consumption of the secondary side IC drops to I sleep
. For any other regulation voltage, the burst is controlled by the firmware and ADC readings, so the IC consumption between bursts is close to the normal mode operating current.
DS13989 - Rev 1 page 20/40
8.5.4
8.5.4.1
8.5.4.2
8.5.4.3
8.5.5
8.6
8.6.1
8.6.2
ST-ONEMP
Control loop
Special modes for voltage transitions
Protocols like USB-PD require to change the output voltage while the converter is operating following specific timing requirements. ST-ONEMP provides special operating modes to Manage negative transition while the applied load to the converter is very low.
Bleeding
The device integrates bleeding current sinks to discharge the output during negative voltage transitions which may happen at light load.
Bleeding current I
BLEED
is initially set to 10 mA, then increased to 20 mA.
Forced burst
In order to maintain the primary side PVCC powered, the IC forces bursts at regular intervals to recharge the primary side through its auxiliary winding.
Active bleeding mode
The IC can be configured to operate in a reverse flyback mode transferring energy from the output capacitor to the input bulk capacitor by switching the SR MOSFET.
This function is useful when the 20 mA bleeding current is not enough to meet the negative transition timing specifications, for example in applications with a big SVCC capacitor.
CCM mode
USB-PD converters allow a wide range of output voltage variations. When the output voltage is low, it is desirable to provide a higher current than what is allowed at maximum output voltage. In normal operating mode the peak current in the transformer is roughly proportional to the output current and loosely related to the voltage. For this reason, an active clamp flyback transformer designed for 45 W at 15 V would require a much higher saturation current to be able to provide the same power at 10 V or 5 V. To help overcome this issue, the device can operate in CCM mode, extending the output current that can be provided for the same transformer saturation level.
to a programmable time, forcing the system to enter CCM mode. The CCM is enabled only if two conditions are met:
•
•
The output voltage is below a programmable threshold
The peak current requested by the control loop is higher than a programmable threshold
The duration of the off-time in CCM mode is equal to the time programmed in the specific parameter, multiplied by
5V/Vout where Vout is the programmed output voltage.
Control loop
The controller includes both a voltage regulation loop, which operates normally, and a current regulation loop which is used in constant current mode, which is used to manage the CC/CV mode as required by USB-PD PPS mode.
Voltage sensing
The IC senses the output voltage through a programmable resistor divider connected to the internal 12 bit ADC.
The resistor divider rescales the SVCC voltage so that the full scale can be configured as 6 V, 12 V or 24 V. The
IC selects the scale depending on the target output voltage.
The thresholds for switching scales are 5.8 V and 11.8 V.
During output voltage transitions, the greater scale between the initial and final voltages is used. At the end of the transition the scale is changed according to the final voltage.
For example in a transition from 5 V to 9 V the scale is initially switched to 12 V, at the end of the transition it is kept at 12 V scale. For a transition 9 V to 5 V, the scale is kept at 12 V and at the end of transition is changed to 6
V scale.
Peak current mode unit
The primary side low-side switch is controlled in peak current mode.
DS13989 - Rev 1 page 21/40
8.6.2.1
8.6.3
8.6.3.1
8.6.4
ST-ONEMP
Control loop
At every switching cycle LON stays high for the blanking time T
LEB turned off when the CS comparator is triggered.
. After the blanking time is expired, the LON is
Reference generator
During normal operation the reference for the peak current mode control is provided by the secondary side through the galvanic isolation communication channel.
The primary side IC converts the duration of pulses received by the secondary side in a voltage reference for the peak current comparator according to the equation: vpk = GTVtpulse
The reference voltage is limited by a hardware clamp to V
IPKCLAMP
.
The pulses are generated by the secondary side SMEDs.
(8)
Voltage loop
The voltage loop is managed by a digital PI (Type2) controller.
The device parameters control the proportional and integral gain of the controller. If sampling effects are ignored, the controller gain can be expressed as follows:
Ipeak
Verr =
GTV
Rsense
8
FckVfsrMax PID_Pgain +
1 sTsampPID_Igain
Where R sense
is the primary side current sense resistor value, Fck is the clock frequency (132 MHz typ.), V fsrMax is the ADC full scale range at the highest scale (24 V), G
TV
is the time-voltage converter gain and T samp
is the control loop sampling period (30 us).
(9)
Considering the primary side peak current to average output current relation, the equation can be written as:
Isec
Verr = nVin nVout + Vin
GTV
Rsense
4
FckVfsrMax PID_Pgain +
1 sTsampPID_Igain
Where n is the turns ratio (primary to secondary) and I sec
is the transformer secondary side average current.
(10)
Setting the voltage loop parameters
The loop cutoff frequency is dominated by the proportional part of the controller, and can be approximated as:
GTV
Rsense
The proportional gain can be set as:
8
FckVfsrMaxPID_Pgain nVin nVout + Vin
1
Cout
(11)
PID_Pgain = ft
πRsenseFckVfsrMax
4GTV n
Vout
Vin + 1 n
Cout (12)
It is advisable to keep the cutoff frequency at least below 1/5 of the loop sampling frequency, i.e. below 8 kHz. If no need for fast transient response is required, a lower bandwidth helps in limiting the control noise.
The integral gain determines the loop zero frequency as:
PID_Igain = PID_Pgain ∙ 2πfzTsamp (13)
Current loop
The current loop is controlled by a dedicated PI controller which acts on the primary side peak current in a similar way to the voltage loop. The control gain is:
Ipeak
Ierr =
RsenseSecGTV
Rsense
2
FckVCSFSR
1 sTsampPIDCC_Igain
Where R senseSec
is the secondary side current sense resistor value.
Considering the primary side peak current to average output current relation, the equation can be written as:
Isec
Ierr = nVin nVout + Vin
RsenseSecGTV
Rsense
1
FckVCSFSR
1 sTsampPIDCC_Igain
Where n is the turns ratio (primary to secondary) and I sec
is the transformer secondary side average current.
(14)
(15)
DS13989 - Rev 1 page 22/40
8.6.4.1
8.6.5
8.7
8.7.1
8.7.1.1
8.7.1.2
8.7.1.3
8.7.2
8.7.3
ST-ONEMP
Fault management
Setting the current loop parameters
If the load impedance is close to 0, the loop cutoff frequency can be calculated as: nVin nVout + Vin
RsenseSecGTV
Rsense
1
FckVCSFSR
1
TsampPIDCC_Igain
The gain can be set as:
(16)
PIDCC_Igain = ft
2πRsenseFckVCSFSRTsamp
RsenseSecGTV n
Vout
Vin + 1 n
(17)
It is advisable to keep the cutoff frequency at least below 1/5 of the loop sampling frequency, i.e. below 8 kHz. If no need for fast transient response is required, a lower bandwidth helps in limiting the control noise.
Cable drop compensation
The cable drop compensation allows to increase the output voltage of the converter proportionally to the current sensed through the CSP/CSM pins.
The cable drop compensation is disabled when the output voltage set by the USB-PD port is above a programmable threshold.
The cable resistance to be compensated can be programmed in the configuration parameters.
Fault management
The IC includes many protections to avoid damage to the converter or to the load in abnormal or failure conditions.
Fault modes
The faults can be either managed as auto-restart, latched, or conditioned restart.The behavior of each fault is described in Fault summary.
Auto-restart mode
In auto-restart mode, once the protection is tripped, the switching activity is stopped, and the condition is maintained until V
PVCC
goes below the V
PVCCOff
restart voltage and then rises again to V
Ultimately, this results in a low frequency intermittent operation (Hiccup-mode operation).
PVCCOn
for six times.
Latched mode
In latched mode the protection is maintained until the input main is removed. During this time the HV generator is activated periodically to cycle the supply voltage between V
PVCCOn
and V
PVCCOff
. The condition is indefinitely maintained until the AC mains is removed triggering a brown-out or an X-Cap discharge fault which clears all fault conditions.
Conditioned restart mode
Faults like the overtemperature or the brown-out, require the fault condition to disappear before the system can restart. When the fault condition is no longer present the system restarts after V
PVCC
goes below V
PVCCOff
restart voltage and then rises again to V
PVCCOn
.
Soft-start timeout
As a protection from secondary side failures, the IC stops switching if no signal is received from the secondary side before the SS pin voltage reaches V
SSEND
.
This fault is managed as auto-restart.
Soft-start overvoltage protection
The primary side IC includes a detection circuit to avoid generating overvoltage on the output when the secondary side is not active. The OV function operates only during primary side soft-start: as the secondary side takes control, the protection is managed by the secondary side.
The overvoltage function of the ST-ONEMP device monitors the voltage on the OVP pin during HS MOSFET's on-time, when the voltage generated by the auxiliary winding tracks converter's output voltage.
DS13989 - Rev 1 page 23/40
ST-ONEMP
Fault management
8.7.3.1
8.7.3.2
8.7.3.2.1
8.7.3.3
8.7.4
8.7.5
8.7.5.1
8.7.5.2
8.7.6
The overvoltage protection is adapted for both flyback and forward mode auxiliary windings. In flyback mode, the auxiliary winding is coupled with the same polarity as the output winding, so when the voltage is positive it reflects the output voltage. In forward mode, the auxiliary winding has a reversed polarity, so when the voltage is positive it reflects the input voltage. This option can be advantageous when the output voltage range is very wide. Both protections for flyback and forward mode OV are active at the same time. The application circuit is designed to allow only the proper protection to be triggered.
To reduce sensitivity to noise and prevent the protection from being erroneously activated, the OVP comparator must be asserted for a time longer than T
OVFILT
for the protection to be triggered.
Flyback aux winding
For flyback windings the OVP condition is detected by comparing the voltage on OVP pin with the V
OVTH threshold.
Forward winding
The OVP pin is clamped at V
OVCLAMP
when sourcing current, avoiding it reaching negative voltages. The current sourced by the clamp is measured and compared with I
OVTH
to detect the OV condition.
OV pin clamping
The OV pin is protected from overvoltage by an internal clamp at 3.3 V, able to sink up to 200 uA.
Soft-start OV Threshold selection
Since the primary side OV is active only during the primary side soft-start, it is suggested to set the threshold to a value which lies between the secondary side turn-on threshold and the maximum secondary side voltage.
Values between 10 V and 15 V are typically good for many applications, including USB-PD with maximum output voltage at 20 V: the higher voltages are reached only when the secondary side is controlling the conversion and the primary side is disabled.
Ac brown-out protection
The ST-ONEMP device is equipped with brown-out protection to prevent the operation at too low ac input voltage.
Power conversion starts only when the voltage on HV becomes higher than V
HVPk_BI
.
If the voltage on HV remains below V
HVPk_BO
for more than T
BODG
the power conversion is turned off until the voltage goes back above V
HVPk_BI
. The T
BODG
masking avoids unexpected turn-offs due to disturbances or line dips.
Primary side overcurrent protection (OCP)
The primary side device includes protections to avoid uncontrolled current rise in the transformer.
First level overcurrent protection
The first protection level is provided by a clamp on the primary side current mode unit comparator which guarantees that, after the blanking time is expired, the LON signal is turned off if the voltage on the ISEN pin bypasses V
IPKCLAMP
. Even if this limit is reached, the device keeps operating unless other faults are triggered, for example if the current limitation causes an unvervoltage on the output voltage.
Second level overcurrent protection (OCP)
The device is protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturated transformer. A comparator monitors continuously the voltage on the CS pin and activates a protection circuitry if this voltage exceeds V
OCTH
.
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the first time the comparator is tripped the protection circuit enters a “warning state”. If in the subsequent switching cycle the comparator is not tripped, a temporary disturbance is assumed, and the protection logic is reset in its idle state; if the comparator is tripped again a real malfunction is assumed and the device is stopped.
The fault is managed in auto-restart mode.
Primary side overtemperature protection
The primary side device can be protected from excess temperature by connecting a thermistor to the POTP pin.
DS13989 - Rev 1 page 24/40
8.7.7
8.7.8
8.8
ST-ONEMP
X-cap discharge
When the voltage on POTP drops below V
POVTH
the conversion is stopped and the device enters fault.
The fault is managed as conditioned-restart.
Primary side undervoltage lockout
In case the voltage on PVCC drops below V
PVCCOff
the IC enters auto-restart fault mode.
Fault summary
The following table summarizes the faults and their effect.
Table 10. Faults table
Fault
UVLO
OVP
Side
Primary
Primary
OCP
SSTO
POTP
Primary
Primary
Primary
BO
XCD
OCP
OVP
UVP
UVLO
SOTP
Primary
Effect
Auto-restart
Enter burst
Auto-restart
Auto-restart
Conditioned-restart
Conditioned-restart
Primary
Secondary
Conditioned-restart
Load switch
Turn off
Enter burst Secondary
Secondary
Secondary
Auto-restart
Auto-restart
Secondary Auto-restart
Comment
Primary side stops and enters burst. In case the secondary side gives no signal, the system enters UVLO.
Second level OC may happen in case of output short. The effect is a shutdown.
Soft-start timeout (SS pin reached V
SSEND
).
Overtemperature protection.
In case of brown-out, switching is stopped. Primary side stops until the
BO condition disappears.
All fault conditions are cleared.
X-Cap discharge is managed in the same way as brown-out.
If load switch is not present, protection is performed by primary side
OCP.
If OVP is triggered secondary side stops and waits the voltage drop under safe condition.
If UVP last for 480us the system stops switching waiting for primary side restart.
If secondary side hits UVLO, the system stops switching waiting for primary side restart.
The secondary overtemperature value is programmable and is considered also a warning temperature (if enabled) before the SOTP.
The fault does not stop switching, but turns off the load switch and sends a hard reset command on the USB-PD.
X-cap discharge
Safety regulations such as IEC 62368-1 require that the capacitors directly connected to the input plug (so called
“X-Caps”) are discharged when the converter mains connector is removed from the outlet, in order to avoid the risk of electrical shock to the user.
Typically, this function is performed by means of a resistor in parallel, but this method cannot be applied in case the converter requires very low power consumption during light-load or no-load operation, because the losses of the X-cap discharging resistor would be too high.
The ST-ONEMP monitors the input voltage through the HV pin and discharges the X-capacitors through the HV pin T
XCDDET
after a plug disconnection is detected.
The discharge continues until the voltage on HV falls below V
HVmin
or the plug is connected again.
Note that a DC voltage on the HV pin is interpreted as a plug disconnection, so the device cannot operate with
DC input voltage.
DS13989 - Rev 1 page 25/40
8.9
8.9.1
8.9.2
8.9.2.1
8.10
8.11
ST-ONEMP
IC Supply
IC Supply
Primary side LDO
A 3.3 V regulator generates the voltage for internal circuitry and digital I/Os. The regulator requires an 100 nF capacitor connected from P3V3 to PPGND.
Secondary side Charge pump & LDO
An internal LDO provides the supply for the IC analog & digital circuits. The SV3V internal LDO can be used to supply external circuits up to 2 mA.
A voltage doubler charge pump provides the driving voltage for the synchronous rectifier. The voltage which can be obtained is approximately 2 * (SVCC – Vf), where Vf is the external diode forward voltage.
The charge pump is turned on when the regulation voltage is below a threshold set by the configuration parameters.
A second LDO provides the 1.2 V supply for the IC logic.
LDO decoupling
The 3V3 LDOs require a 1 uF ceramic capacitor to ground to decouple the supply voltage and guarantee stability.
The V1V2 LDO requires a 4.7 uF ceramic capacitor to ground.
The capacitors should be located as near as possible to the device.
Power Good
The GPIO1 is configured as a power good pin. The purpose of this pin is to disable a DC/DC converter controlling the second port during the system startup until the AC/DC converter has terminated its soft-start and reached a stable operation.
Secondary side controller
The secondary side includes a digital controller which is in charge of both the power conversion and the communication with the load through USB-PD.
Figure 10. Secondary side block diagram
SRGD
VZCD
SVCC
1V
SR1V
IZCD
SMED Event bus
VCLAMP
SPGND
VCLAMP
VDRV
Clamp
Duty cycle estimator
SMED 0 & 1
Connection box
ISO TX
SMED 2
CSM
CSP
Temperature sense
Int Temp
SRVDS
CS_AMP
VOPART
VCCPART
GPIO0
GPIO1
SCHEDULER
Wakeup
12 bit
ADC
VCCPART
WakeRef
Oring FET
Driver & Charge pump (sys ctrl)
64kB program memory + 8kB boot
8kB SRAM
Bleeder ctrl (sys ctrl)
Watchdog
Power & clock manager (sys ctrl)
GPIO
TYPE-C phy
I2C
UART
CORTEX M0+
VOSNS
VOPART VCCPART
LDO & Charge pump
66kHz clk
OSCILLATOR
PLL
SVCC
VDRV
PUMP
SV3V
V1V2
SWD
CC1
CC2
GPIO1
GPIO0
DS13989 - Rev 1 page 26/40
8.11.1
8.11.1.1
8.11.2
ST-ONEMP
Secondary side controller
Microcontroller core
The secondary side is controlled by a Cortex M0+ core clocked at F
CK
/2, with 8kB static RAM and 64kB programmable flash code memory. The flash is loaded in production with a complete code managing both the voltage conversion of an active clamp flyback and the protocol for USB-PD PPS.
A dedicated 8kB ROM area is reserved for the boot activity and trimming area.
Parameter memory
A section of the flash is dedicated to parameters which can be programmed by the user to tune the power conversion, set up the application functionality, choose the protocol and the PDOs or APDOs to be used.
SMED
A set of dedicated event driven state machines can generate complex PWMs. The transitions between the states can be controlled by either timings or external events, or a combination of the two.
The SMED configuration is fully managed by the IC firmware to implement the control modes described in
DS13989 - Rev 1 page 27/40
ST-ONEMP
Communication interface
9
Communication interface
9.1
9.1.1
9.1.1.1
9.1.1.2
USB-PD protocol
The USB-PD module controls the USB Type-C™ connector signals and power delivery on Vbus line using
USB-PD protocol.
The ST-ONEMP device can provide an output voltage between 3.3 V to 21 V. The PDOs or APDOs used in the application can be defined by the user (except for the mandatory 5 V).
The module provides the USB-PD Source layers over one power channel. This is the list of the USB-PD options available on the ST-ONEMP USB-PD firmware stack embedded on the device.
•
•
•
The USB-PD module supports:
•
•
•
•
•
One USB-PD power SOURCE channel (DFP - AC adapter)
USB-PD REV 3.1 specification
PPS (Programmable Power Supply) with Constant Current mode
1 default PDO plus 6 slots for PDOs or APDOs, customer configurable
6 slots for PDOs or APDOs, customer configurable, to be used when a second port is attached (see
Vconn source with 100 mW output power used to identify Electronically Marked Cables
Send Alert on OTP and OCP protections
Send Source_Capability_Extended message
The USB-PD module does NOT support:
•
•
•
•
•
•
•
•
•
Constant power on PPS mode
Communication via USB (D+/D- and or SSTx+/- and SSRx+/-)
Fast Role Swap
VDM message management apart from SVDM-SOP’ to manage the cable discovered
Battery Supply PDO and Variable Supply PDO
Power Sharing
Unchunked message
Type C authentication 1.0 extension
Firmware update using 1.0 extension
USB-PD Physical layer
The device includes a complete physical layer for USB-PD applications.
The CC pins can withstand up to 24 V, requiring no extra protection to manage accidental shorts to Vbus.
CC Pins Vconn
The IC includes an internal switch between CC1/2 and SVCC which is used to provide the VCONN for electronically marked cable detection. The Vconn switch is current limited to avoid damaging the IC in case of short on CC pins.
As required by the USB-PD standard, the CC pins include an integrated bleeder resistor with value R
CCBLD
which is turned on for 10 ms when the Vconn is removed.
The CC Vconn directly connects the CC1 or CC2 pin to the SVCC voltage, so it can be used only when the regulated voltage is 5 V, as during the Electronically Marked Cable detection.
CC OV comparator
The CC pins include a comparator to detect abnormal voltages on the pins caused, for example, by shorts to
Vbus. When the voltage on one of the CC pins bypasses V
CCOVP
the load switch is turned off, and normal operation restarts only once the voltage on the pins drops below 2.5V
DS13989 - Rev 1 page 28/40
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
ST-ONEMP
USB-PD protocol
USB-PD PDO and APDO adaptation and protection
During the attach procedure, the Source and Sink verify the voltage and current, offered and requested. As defined by the USB-PD protocol, upon cable connection the device checks the cable capabilities; in case the cable used is not 5 A capable, the maximum current in all the PDOs and APDOs sent upon capability request is limited to 3 A.
In case of secondary side temperature protection, the capabilities are modified depending on the temperature level.
USB-PD alert management
The device implements protections such as UVP, OVP, OCP. Some, for this mode, are reported during the USB-
PD message exchange between source and sink. In some cases of this alarm type, the VBUS is automatically disconnected and no message is sent.
The temperature is also verified and controlled. The corresponding bit into alert messages is managed.
•
•
Overcurrent management
The IC manages the OCP and turns off the load switch according to the USB-PD standard.
The OCP level and behavior depends on the PDO or APDO selected by sink.
if a PDO is selected, the OCP is set up adding a programmable percentage of the maximum current defined on the PDO. If an OCP is detected, the load switch is turned off and Vbus is disconnected.
if an APDO is selected, the current is limited in CC mode. If the output voltage drops below a programmable threshold, the power module issues a warning, and if a second threshold is bypassed, disconnects the Vbus.
•
•
Undervoltage management
The IC manages the undervoltage protection depending on the PDO or APDO selected by the sink: if a PDO is selected, the UVP threshold is determined as a programmable percentage of the nominal output voltage if an APDO is selected, the undervoltage is triggered by a drop below a programmable threshold while
operating in constant current mode, as described in Section 9.1.4
Temperature management
The ST-ONEMP device supports two temperature measurement points on the secondary side, one internal to the device and one external using an optional NTC.
•
•
The internal temperature is relative to the device and, normally, the default limit is considered good for most applications. The internal temperature sense can read between 0 ºC and +150 ºC, with an accuracy of T
ACC
(see
).
The external temperature limit is defined by the user by connecting an external resistor divider using an
NTC. The user can program the voltage thresholds for the overtemperature fault (OTP) and warning (WTP).
In case of temperature management, the device implements the secondary side Overtemperature Protection
(SOTP) and Warning Temperature Protection (WTP). All the temperature trip points are programmable.
Figure 11. Temperature management
Temperature
low high
WTP OTP
In case of overtemperature, the HARD_RESET message is sent out and the next capability proposed is only 5 V and 500 mA. In case the OTP is confirmed for 10 seconds, the Vbus voltage is switched off. The Vbus voltage is provided only when the secondary temperature returns below OTP-10 ºC for the internal temperature or below
OTP-Hysteresis in case of external temperature. In case the OTP is triggered, the charger functionality is restored if either:
• the AC line is removed, and the temperature returns into an acceptable range.
DS13989 - Rev 1 page 29/40
9.1.7
9.1.8
9.1.9
ST-ONEMP
USB-PD protocol
• the internal temperature returns below WTP range. In that case, the default contract is established automatically.
The WTP range is a range between the WTP point and the OTP point.
When the temperature enters the WTP range an Alarm message is sent, but no other action is performed. Only in case of new capability request or new contract, the next capability message limits the current/power, depending on the setup on the configuration area. When the proposed capability is accepted the new power contract is established.
When the temperature exits from the WTP range and enters into normal range the next contract returns to the default status.
USB-PD VCONN management
The VCONN is automatically provided by the device only during cable identification and before any explicit contract is started. After the first capability message, the VCONN is removed.
PDO selection for multiport operation
The ST-ONEMP provides a dedicated power sharing function for multiport chargers. Depending on the level of the
GPIO1 pin, the ST-ONEMP provides two different PDO/APDO sets. The typical use of this function is to reduce the available power on the main USB-PD port of the charger when a load is connected to a secondary port.
The level which determines the main or secondary PDOs to be used and the two PDO sets are programmable through the configuration parameters.
The GPIO1 input can be filtered with independent deglitch filters for power sharing request assertion and deassertion. This function can be useful for example when the second load detection is based on a current threshold, avoiding repetitive changes on the primary port PDOs.
SVCC voltage change on cable detach
In USB-PD applications with multiple output voltage selection, the converter usually operates at lower efficiency and limited power capability when the output regulated voltage is closer to the minimum. When no cable is connected to the USB-PD output and the load switch is disabled, providing a voltage higher than 5 V can increase the efficiency of the DC/DC converter for the second port if a consistent load is connected to it.
The ST-ONEMP can be configured to provide 9 V instead of 5 V when the Type-C cable is detached and the load switch is turned off.
DS13989 - Rev 1 page 30/40
10
10.1
10.2
10.3
10.4
10.5
ST-ONEMP
Device setup and User personalization
Device setup and User personalization
It is possible to set up device parameters to configure ST-ONEMP behavior. A dedicated GUI and a HW tool are available to change and tune the application behavior during development time. The ST-ONEMP devices are shipped with a pre-defined set-up, but the user can change it using the serial line.
The entire device setup is always modifiable using a dedicated tool. In case the write protection is enabled on the device, the user can only delete this memory area. The devices set-up area is divided into different zones, application set-up area, application parameter area, USB-PD area and power area.
The data area is protected by CRC32 reverse polynomial (ISO 3309 - 0xedb88320).
Please check the ST-ONEMP Parameter Configuration Manual document which specifies any detail regarding the
User personalization.
The same tools can be used also to update the entire program file area with a new firmware version or a dedicated firmware. The program file area is protected by CRC32 reverse polynomial.
Application set-up area
This area stores all the values used to configure the application. This area is read by the Boot code during startup.
Application parameters area
The Application parameters area contains the secondary overtemperature protection levels (SOTP). The SOTP levels are divided into two zones, internal on ST-ONEMP and external.
• The internal temperature is provided by an internal sensor: the user defines the internal temperature trigger point.
• The external temperature requires a thermistor connected to a GPIO pin that is specified in the Application set-up field. The user provides the voltage levels at which SOTP is triggered, and the direction (rising or falling) depending on the external circuit used. External sense circuit is optional, if not connected this function is not available.
The programmability of the ST-ONEMP device also provides a warning temperature limit.
USB-PD area
The USB-PD area defines which PDOs and APDOs are provided by the USB-PD protocol.
This area contains also the maximum power provided by the ST-ONEMP application. The maximum power value is shared with the SINK during USB-PD messages.
Power area
The power parameters area stores the parameters required for the switching control, including loop compensation parameters, low power mode settings, etc.
Default configuration
The default configuration allows the user to set up and define all the parameters .
The default configuration selects the CC1 and CC2 pins as the serial line used to communicate, configure and program the IC through a serial interface. Please visit the product page on www.st.com
to find the dedicated HW programmer and software.
DS13989 - Rev 1 page 31/40
11
Package drawings
Figure 12. Package drawings
ST-ONEMP
Package drawings
Figure 13. Package dimensions
Note: All dimensions are in millimeters and angles in degrees.
DS13989 - Rev 1 page 32/40
12
ST-ONEMP
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS13989 - Rev 1 page 33/40
13
Ordering information
Order codes
ST-ONEMP
ST-ONEMPTR
Table 11. Order codes
Packing
Tube
Tape & Reel
ST-ONEMP
Ordering information
Package
SSOP 36L
DS13989 - Rev 1 page 34/40
Revision history
Date
21-Dec-2022
Version
1
Table 12. Document revision history
Changes
Initial release.
ST-ONEMP
DS13989 - Rev 1 page 35/40
ST-ONEMP
Contents
Contents
High voltage startup
DS13989 - Rev 1 page 36/40
ST-ONEMP
Contents
DS13989 - Rev 1 page 37/40
ST-ONEMP
List of tables
List of tables
DS13989 - Rev 1 page 38/40
ST-ONEMP
List of figures
List of figures
DS13989 - Rev 1 page 39/40
ST-ONEMP
IMPORTANT NOTICE – READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS13989 - Rev 1 page 40/40
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