congatec conga-TS170 User's guide

COM Express™ conga-TS170

6th Generation Intel® Core™

i7, i5, i3 Celeron/Xeon processor with either QM170, HM170, or CM236 Chipset

User’s Guide

Revision 1.8

Revision History

Revision Date (yyyy-mm-dd) Author Changes

0.1

0.2

1.0

1.1

2016-03-22

2016-07-14

2017-01-10

2018-05-07

AEM

BEU

AEM

AEM

• Preliminary release

•

• Updated available product variants in section 1 “Introduction” and section 2 “Specifications”

• Added section 10 “System Resources”

Added section 11 “BIOS Setup Description”

• Added section 12 “Additional BIOS Features”

• Updated section 2.1 “Feature List”

• Updated section 2.5 “Power Consumption”

• Updated the note in section 2.6.1 “CMOS Battery Power Consumption”

• Updated the caution note in section 4.3 “Heatspreader”

•

• Corrected the description of pins D63 and D64 in table 31 “Connector C-D Pinout”

• Corrected typographical error in section 6.1.7 “PCIe Express”

Updated section 6.1.10 “LVDS/eDP”

• Deleted all references of SDIO/SD card because the chipset does not support SD card

• Added VGA to table 2 “conga-TS170 Variants”

• Updated section 3 “Block Diagram”

• Updated table 5 “Power Consumption Values”

• Corrected the maximum HDMI resolution value in table 7 “Maximum Supported Resolutions”

•

• Indicated in table 15 “LPC Signal Description” and 26 “Connector A-B Pinout “ that the LPC_DRQ signal is not supported

• Deleted the note in section 11.4.15 “Serial Port Console Redirection Submenu”

Corrected the pin numbers of USB ports 0 and 1 in table 16 “USB SignalDescriptions”

• Updated section 11 “BIOS Setup Description” and section 12 “Additional BIOS Features”

1.2

2018-08-24 AEM

1.3

1.4

1.5

1.6

2019-04-25

2020-03-24

2020-07-03

2021-04-19

AEM

AEM

AEM

AEM

•

• Updated the cooling diagrams and heatspreader thermal imagery in section 4 “Cooling Solutions”

Updated table 5 “Power Consumption Values”

•

• Changed Intel 100 series PCH to Intel PCH

• Updated section 2.3 “Mechanical Dimensions”

Updated sections 4 .1 “CSA Dimensions”, 4.2 “CSP Dimensions”, 4.3 “HSP Dimensions”

• Updated sections 12.2 “Updating the BIOS“ and 12.3 “Supported Flash Devices”

• Corrected the number of available variants in section 1.2 “Options Information”

• Updated section 4 “Cooling Solutions”

•

• Upated the recommended torque value for carrier board and module screws

• Corrected the CSA and CSP standoff height in sections 4.1 “CSA Dimensions” and 4.2 “CSP Dimensions”

Added note about the minimum pulse width required for proper button detection in table 24 “Power and System

Management Signal Descriptions”

•

• Updated sections 11 “BIOS Setup Description” and 12 “Additional BIOS Features”

Deleted section 13 “Industrial Specifications”

• Corrected a typographic error in section 12. 3 “Supported Flash Devices”

•

• Updated table 2 “conga-TS170 Variants, table 3 “Feature Summary”, table 8 “Maximum Supported Resolutions” and table 16 “TMDS Signal Descriptions”

• Updated section 3 “Block Diagram” and section 6.1.3 “Display Interfaces

Deleted section 6.1.3.1 “HDMI” and section 6.1.3.2 “DVI”

• Added note to table 16 “TMDS Signal Descriptions”

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1.7

1.8

2021-08-02

2021-11-16

AEM

AEM

•

• Added Software License Information

• Changed congatec AG to congatec GmbH

Updated the Power Supply Implementation Guidelines in section 6.1.13 “Power Control”

• Updated section 7.3 “congatec Battery Management Interface”

• Deleted HDMI references from section 1.2 “Options Information”, section 2.1 “Feature List” and section 6.1.3 “Display

Interfaces”

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Preface

This user’s guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-TS170. It is one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should be used include the following:

COM Express ™ Design Guide

COM Express ™ Specification

The links to these documents can be found on the congatec GmbH website at www.congatec.com

Software Licenses

Notice Regarding Open Source Software

The congatec products contain Open Source software that has been released by programmers under specific licensing requirements such as the “General Public License“ (GPL) Version 2 or 3, the “Lesser General Public License“ (LGPL), the “ApacheLicense“ or similar licenses.

You can find the specific details at https://www.congatec.com/en/licenses/. Search for the revision of the BIOS/UEFI or Board Controller

Software (as shown in the POST screen or BIOS setup) to get the complete product related license information. To the extent that any accompanying material such as instruction manuals, handbooks etc. contain copyright notices, conditions of use or licensing requirements that contradict any applicable Open Source license, these conditions are inapplicable.

The use and distribution of any Open Source software contained in the product is exclusively governed by the respective Open Source license. The Open Source software is provided by its programmers without ANY WARRANTY, whether implied or expressed, of any fitness for a particular purpose, and the programmers DECLINE ALL LIABILITY for damages, direct or indirect, that result from the use of this software.

OEM/ CGUTL BIOS

BIOS/UEFI modified by customer via the congatec System Utility (CGUTL) is subject to the same license as the BIOS/UEFI it is based on. You can find the specific details at https://www.congatec.com/en/licenses/.

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Disclaimer

The information contained within this user’s guide, including but not limited to any product specification, is subject to change without notice.

congatec GmbH provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec GmbH assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user’s guide. In no event shall congatec GmbH be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information contained herein or the use thereof.

Intended Audience

This user’s guide is intended for technically qualified personnel. It is not intended for general audiences.

Lead-Free Designs (RoHS)

All congatec GmbH designs are created from lead-free components and are completely RoHS compliant.

Electrostatic Sensitive Device

All congatec GmbH products are electrostatic sensitive devices. They are enclosed in static shielding bags, and shipped enclosed in secondary packaging (protective packaging). The secondary packaging does not provide electrostatic protection.

Do not remove the device from the static shielding bag or handle it, except at an electrostatic-free workstation. Also, do not ship or store electronic devices near strong electrostatic, electromagnetic, magnetic, or radioactive fields unless the device is contained within its original packaging. Be aware that failure to comply with these guidelines will void the congatec GmbH Limited Warranty.

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Symbols

The following symbols are used in this user’s guide:

Warning

Warnings indicate conditions that, if not observed, can cause personal injury.

Caution

Cautions warn the user about how to prevent damage to hardware or loss of data.

Note

Notes call attention to important information that should be observed.

Trademarks

Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property of their respective trademark holders. These trademark holders are not affiliated with congatec GmbH, our products, or our website.

Copyright Notice

Copyright © 2016, congatec GmbH. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from congatec GmbH.

congatec GmbH has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”.

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Warranty

congatec GmbH makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited warranty (“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and conditions can be downloaded from www.congatec.com. congatec GmbH may in its sole discretion modify its Limited Warranty at any time and from time to time.

The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license agreements, which are available at www.congatec.com and/or upon request.

Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec GmbH represents that the products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec’s option and expense.

Customer will obtain a Return Material Authorization (“RMA”) number from congatec GmbH prior to returning the non conforming product freight prepaid. congatec GmbH will pay for transporting the repaired or exchanged product to the customer.

Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to congatec’s direct customer only and is not assignable or transferable.

Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.

congatec GmbH shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the product only.

Certification

congatec GmbH is certified to DIN EN ISO 9001 standard.

ISO 9001

C

ER

TIFICATI

O

N

TM

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Technical Support

congatec GmbH technicians and engineers are committed to providing the best possible technical support for our customers so that our products can be easily used and implemented. We request that you first visit our website at www.congatec.com for the latest documentation, utilities and drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support department by email at [email protected]

Terminology

Term

CSA

CSP eDP

PCH

PCIe

PEG

SATA

TBD

TDP

GB

GHz

HDA

HSP kB kHz

MB

Mbit

MHz

N.A.

N.C.

Description

Active Cooling Solution

Passive Cooling Solution

Embedded DisplayPort

Gigabyte

Gigahertz

High Definition Audio

Heatspreader

Kilobyte

Kilohertz

Megabyte

Megabit

Megahertz

Not available

Not connected

Platform Controller Hub

PCI Express

PCI Express Graphics

Serial ATA

To be determined

Thermal Design Power

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Contents

1 Introduction ............................................................................. 12

1.1

1.2

COM Express™ Concept ......................................................... 12

Options Information ................................................................. 13

2 Specifications ........................................................................... 15

2.1

2.2

2.3

2.4

2.4.1

2.4.2

2.5

2.6

2.7

3

Feature List .............................................................................. 15

Supported Operating Systems ................................................ 16

Mechanical Dimensions ........................................................... 16

Supply Voltage Standard Power .............................................. 17

Electrical Characteristics .......................................................... 17

Rise Time ................................................................................. 17

Power Consumption ................................................................ 18

Supply Voltage Battery Power ................................................. 19

Environmental Specifications ................................................... 20

Block Diagram .......................................................................... 21

4

4.1

4.2

4.3

4.4

5

Cooling Solutions ..................................................................... 22

CSA Dimensions ...................................................................... 23

CSP Dimensions ....................................................................... 24

HSP Dimensions ....................................................................... 25

Heatspreader Thermal Imagery ............................................... 26

Onboard Temperature Sensors ................................................ 27

6 Connector Rows ....................................................................... 29

6.1

6.1.1

6.1.2

6.1.3

Primary and Secondary Connector Rows ................................. 29

PCI Express™ ........................................................................... 29

PCI Express Graphics (PEG) ..................................................... 29

Display Interfaces ..................................................................... 30

6.1.3.1 DisplayPort (DP) ....................................................................... 31

6.1.3.2 LVDS/eDP ................................................................................. 32

6.1.3.3 VGA.......................................................................................... 32

6.1.4 SATA ........................................................................................ 32

6.1.5 USB .......................................................................................... 33

6.1.6

6.1.7

6.1.8

6.1.9

Gigabit Ethernet ..................................................................... 33

High Definition Audio (HDA) Interface .................................... 33

LPC Bus .................................................................................... 33

I²C Bus Fast Mode ................................................................... 33

6.1.10 ExpressCard™ ......................................................................... 34

6.1.11 General Purpose Serial Interface ............................................. 34

6.1.12 GPIOs ....................................................................................... 34

6.1.13

6.1.14

Power Control .......................................................................... 34

Power Management ................................................................. 38

7 Additional Features .................................................................. 39

7.2.2

7.2.3

7.2.4

7.2.5

7.3

7.4

7.5

7.6

7.1

7.1.1 congatec Board Controller (cBC) ............................................. 39

Board Information .................................................................... 39

7.1.2 Watchdog ................................................................................ 39

7.1.3 I 2 C Bus ...................................................................................... 39

7.1.4

7.1.5

7.2

7.2.1

Power Loss Control .................................................................. 39

Fan Control .............................................................................. 40

OEM BIOS Customization ........................................................ 40

OEM Default Settings .............................................................. 40

OEM Boot Logo ....................................................................... 40

OEM POST Logo ..................................................................... 41

OEM BIOS Code/Data ............................................................. 41

OEM DXE Driver ...................................................................... 41 congatec Battery Management Interface ................................ 41

API Support (CGOS) ................................................................ 42

Security Features ...................................................................... 42

Suspend to Ram ....................................................................... 42

8 conga Tech Notes .................................................................... 43

8.1

43

Adaptive Thermal Monitor and Catastrophic Thermal Protection

8.2 Intel ® Processor Features ......................................................... 44

8.2.1 Intel ® SpeedStep ® Technology (EIST) ...................................... 44

8.2.2 Intel ® Turbo Boost Technology ................................................ 44

8.2.3 Intel ® Virtualization Technology ............................................... 45

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8.2.4

8.3

8.4

9

9.1

9.2

10

Thermal Management ............................................................. 45

ACPI Suspend Modes and Resume Events .............................. 46

DDR4 Memory ......................................................................... 46

Signal Descriptions and Pinout Tables ..................................... 47

Connector Signal Descriptions ................................................ 48

Boot Strap Signals ................................................................... 70

System Resources .................................................................... 71

10.1

10.1.1

I/O Address Assignment .......................................................... 71

LPC Bus .................................................................................... 71

10.2 PCI Configuration Space Map ................................................. 72

10.3 I 2 C ............................................................................................ 73

10.4 SM Bus ..................................................................................... 73

11 BIOS Setup Description ........................................................... 74

11.1

11.1.1

11.2

11.3

Entering the BIOS Setup Program ........................................... 74

Boot Selection Popup .............................................................. 74

Setup Menu and Navigation .................................................... 74

Main Setup Screen ................................................................... 75

11.3.1

11.4

Platform Information Submenu ................................................ 76

Advanced Setup ...................................................................... 77

11.4.1 Graphics Submenu ................................................................... 78

11.4.1.1 Display Interface Signal Integrity Settings Submenu ............... 82

11.4.2

11.4.3

Watchdog Submenu ................................................................ 83

Module Serial Ports Submenu ................................................. 85

11.4.4 Hardware Health Monitoring Submenu ................................... 86

11.4.5 Intel ® Ethernet Connection (H) I219-LM Submenu .................. 88

11.4.5.1 NIC Configuration Submenu ................................................... 88

11.4.6 Driver Health Submenu ............................................................ 89

Trusted Computing Submenu .................................................. 89 11.4.7

11.4.8

11.4.9

RTC Wake Settings Submenu .................................................. 90

LPC Generic I/O Range Decode Submenu .............................. 90

11.4.10 GPI IRQ Configuration Submenu ............................................. 91

11.4.11 ACPI Submenu ......................................................................... 91

11.4.12 Intel ® ICC Submenu ................................................................. 93

11.4.13 PCH-FW Configuration Submenu ............................................ 93

11.4.14 SMART Settings Submenu ....................................................... 94

11.4.15 Super IO Submenu .................................................................. 94

11.4.16 Serial Port Console Redirection Submenu ............................... 95

11.4.16.1 Console Redirection Settings Submenu .................................. 95

11.4.17 CPU Submenu .......................................................................... 96

11.4.17.1 CPU Information ...................................................................... 99

11.4.18 SATA Submenu ...................................................................... 100

11.4.18.1 Software Feature Mask Configuration ................................... 102

11.4.19 Acoustic Management Submenu ........................................... 103

11.4.20 PCI Express Configuration Submenu ..................................... 103

11.4.21 PCI Express Configuration Submenu ..................................... 105

11.4.21.1 PCI Express Gen3 Eq Lanes Submenu ................................... 106

11.4.21.2 PCI Express Settings Submenu .............................................. 106

11.4.21.3 PCI Express GEN2 Settings Submenu ................................... 107

11.4.21.4 PCI Express Port 0 - 7 Submenu ............................................ 108

11.4.21.5 PEG Port Configuration Submenu ......................................... 111

11.4.22 UEFI Network Stack Submenu ............................................... 113

11.4.23 CSM & Option ROM Control Submenu ................................. 114

11.4.24 NVMe Configuration Submenu ............................................. 115

11.4.25 USB Submenu ........................................................................ 115

11.4.26 Diagnostics Settings Submenu .............................................. 117

11.4.27 GPIO Configuration Submenu ............................................... 118

11.4.28 Board Controller Command Control Submenu ..................... 118

11.4.29 PC Speaker Submenu ............................................................ 118

11.5

11.6

Chipset Setup ........................................................................ 119

Security Setup ........................................................................ 119

11.6.1 Security Settings .................................................................... 119

11.6.1.1 BIOS Security Features .......................................................... 119

11.6.1.2 Hard Disk Security Features ................................................... 121

11.7

11.7.1

11.8

Boot Setup ............................................................................. 122

Boot Settings Configuration .................................................. 122

Save & Exit Menu ................................................................... 124

12 Additional BIOS Features ...................................................... 125

12.1

12.2

12.3

BIOS Versions......................................................................... 125

Updating the BIOS ................................................................. 125

Supported Flash Devices ....................................................... 126

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List of Tables

Table 1 COM Express™ 2.1 Pinout Types ............................................ 12

Table 2 conga-TS170 Variants .............................................................. 13

Table 3 Feature Summary ..................................................................... 15

Table 4 Measurement Description ........................................................ 18

Table 5 Power Consumption Values ..................................................... 19

Table 6 CMOS Battery Power Consumption ........................................ 19

Table 7 Cooling Solution Variants ......................................................... 22

Table 8 Maximum Supported Resolutions ............................................ 31

Table 9 Wake Events ............................................................................. 46

Table 10 Signal Tables Terminology Descriptions .................................. 47

Table 11 Connector A–B Pinout ............................................................. 48

Table 12 Connector C–D Pinout ............................................................. 50

Table 13 PCI Express Signal Descriptions (General Purpose) ................. 52

Table 14 PCI Express Signal Descriptions (x16 Graphics) ....................... 53

Table 15 DDI Signal Description ............................................................. 55

Table 16 TMDS Signal Descriptions ....................................................... 57

Table 17 DisplayPort (DP) Signal Descriptions ....................................... 58

Table 18 Embedded DisplayPort Signal Descriptions ............................ 60

Table 19 VGA Signal Descriptions .......................................................... 60

Table 20 LVDS Signal Descriptions ......................................................... 61

Table 21 Serial ATA Signal Descriptions ................................................. 61

Table 22 USB 2.0 Signal Descriptions ..................................................... 62

Table 23 USB 3.0 Signal Descriptions ..................................................... 63

Table 24 Gigabit Ethernet Signal Descriptions....................................... 63

Table 25 Intel ® High Definition Audio Link Signals Descriptions ............ 64

Table 26 ExpressCard Support Pins Signal Descriptions ........................ 64

Table 27 LPC Signal Descriptions ........................................................... 65

Table 28 SPI BIOS Flash Interface Signal Descriptions ........................... 65

Table 29 Miscellaneous Signal Descriptions ........................................... 65

Table 30 General Purpose I/O Signal Descriptions ................................ 66

Table 31 Power and System Management Signal Descriptions ............. 66

Table 32 General Purpose Serial Interface Signal Descriptions .............. 67

Table 33 Module Type Definition Signal Description ............................. 68

Table 34 Power and GND Signal Descriptions ....................................... 69

Table 35 Boot Strap Signal Descriptions ................................................ 70

Table 36 PCI Configuration Space Map ................................................. 72

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1 Introduction

1.1 COM Express™ Concept

COM Express™ is an open industry standard defined specifically for COMs (computer on modules). Its creation makes it possible to smoothly transition from legacy interfaces to the newest technologies available today. COM Express™ modules are available in following form factors:

• Mini

• Compact

• Basic

• Extended

84 mm x 55 mm

95 mm x 95 mm

125 mm x 95 mm

155 mm x 110 mm

Table 1 COM Express™ 2.1 Pinout Types

Types Connector Rows PCIe Lanes PCI

Type 1 A-B Up to 6

Type 2

Type 3

Type 4

A-B C-D

A-B C-D

A-B C-D

Type 5

Type 6

A-B C-D

A-B C-D

Type 10 A-B

Up to 22

Up to 22

Up to 32

Up to 32

Up to 24

Up to 4

32 bit

32 bit

-

-

-

-

1

1

-

IDE SATA Ports LAN ports USB 2.0/ USB 3.0

Display Interfaces

4 1 8 / 0 VGA, LVDS

4

4

2

4

4

4

3

1

1

1

3

1

8 / 0

8 / 0

8 / 0

8 / 0

8 / 4 1.

8 / 0

VGA, LVDS, PEG/SDVO

VGA,LVDS, PEG/SDVO

VGA,LVDS, PEG/SDVO

VGA,LVDS, PEG/SDVO

VGA,LVDS/eDP, PEG, 3x DDI

LVDS/eDP, 1xDDI

1. The SuperSpeed USB ports (USB 3.0) are not in addition to the USB 2.0 ports. Up to 4 of the USB 2.0 ports can support SuperSpeed USB.

The conga-TS170 modules use the Type 6 pinout definition and comply with COM Express 2.1 specification. They are equipped with two high performance connectors that ensure stable data throughput.

The COM (computer on module) integrates all the core components and is mounted onto an application specific carrier board. COM modules are legacy-free design (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application. These functions include, but are not limited to a rich complement of contemporary high bandwidth serial interfaces such as PCI Express, Serial

ATA, USB 3.0, and Gigabit Ethernet. The Type 6 pinout provides the ability to offer PCI Express, Serial ATA, USB 3.0 and LPC options thereby expanding the range of potential peripherals. The robust thermal and mechanical concept, combined with extended power-management capabilities, is perfectly suited for all applications.

Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™

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1.2

modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use of different performance class or form factor size modules. Simply unplug one module and replace it with another; no redesign is necessary.

Options Information

The conga-TS170 is currently available in 15 variants. The table below shows the different configurations available.

Table 2 conga-TS170 Variants

Part-No.

Processor

045900

Intel ® Core™ i7-6820EQ

2.8 GHz Quad Core™

045901



045902


2.7 GHz Quad core

045903



Max. Turbo Frequency

Chipset

3.5 GHz

Intel ® QM170

2.8 GHz

Intel ® QM170

3.4 GHz

Intel ® QM170

2.7 GHz

Intel ® QM170

Intel ® Smart Cache

Processor Graphics

8 MB 8 MB 6 MB 6 MB

Intel ® HD Graphics 530 (GT2) Intel ® HD Graphics 530 (GT2) Intel ® HD Graphics 530 (GT2) Intel ® HD Graphics 530 (GT2)

GFX Base/Max. Dynamic Freq.

350 MHz / 1 GHz

Memory (DDR4) 2133 MT/s dual channel

350 MHz / 1 GHz

2133 MT/s dual channel

350 MHz / 1 GHz


350 MHz / 1 GHz


LVDS

DP++

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

VGA

Processor TDP (cTDP)

Yes

45 W (N.A)

Yes

25 W (N.A)

Yes

45 W (N.A)

Yes

25 W (N.A)

Part-No.

Processor

045904

Intel ® Core™ i3-6100E

2.7 GHz Dual Core™

045905


1.9 GHz, Dual Core™

045906 (ECC)

Intel ® Xeon ® E3-1505M v5


045907 (ECC)

Intel ® Xeon ® E3-1505L v5


Max. Turbo Frequency N.A

N.A

3.7 GHz 2.8 GHz

Chipset Intel ® HM170 Intel ® HM170 Intel ® CM236 Intel ® CM236


Processor Graphics

3 MB

Intel ®


350 MHz / 950 MHz

3 MB

HD Graphics 530 (GT2) Intel ® HD Graphics 530 (GT2) Intel

350 MHz / 950 MHz

8 MB

® HD Graphics P530 (GT2) Intel

350 MHz / 1.05 GHz

8 MB

® HD Graphics P530 (GT2)

350 MHz / 1 GHz

Memory (DDR4)

LVDS


Yes


Yes

2133 MT/s dual channel ECC 2133 MT/s dual channel ECC

Yes Yes

DP++ Yes Yes Yes Yes

VGA


Yes

35 W (N.A)

Yes

25 W (N.A)

Yes

45 W (35W)

Yes

25 W (N.A)

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Part-No.

Processor

045908 (ECC)



045909 (ECC)



045910

Intel ® Celeron ® G3900E


045911

Intel ® Celeron ® G3902E


Max. Turbo Frequency

Chipset

N.A

Intel ® CM236

N.A

Intel ® CM236

N.A

Intel ® HM170

N.A

Intel ® HM170


Processor Graphics

3 MB 3 MB 2 MB 2 MB

Intel ® HD Graphics 530 (GT2) Intel ® HD Graphics 530 (GT2) Intel ® HD Graphics 510 (GT1) Intel ® HD Graphics 510 (GT1)


350 MHz / 950 MHz

Memory (DDR4)

350 MHz / 950 MHz 350 MHz / 950 MHz

2133 MT/s dual channel ECC 2133 MT/s dual channel ECC 2133 MT/s dual channel

350 MHz / 950 MHz


LVDS

DP++

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

VGA


Yes

35 W (N.A)

Yes

25 W (N.A)

Yes

35 W (N.A)

Yes

25 W (N.A)

Part-No.

Processor

045912 (ECC)

Intel ® Xeon ® E3-1515M v5


045913 (ECC)


2.0 GHz Quad Core TM

045914 (ECC)


1.9 GHz Quad Core TM

Max. Turbo Frequency 3.7 GHz 3.4 GHz 3.3 GHz

Chipset


Intel ® CM236

8 MB

Intel ®

8 MB

CM236 Intel ®

8 MB

CM236

Processor Graphics Intel ® Iris™ Pro P580 (GT4) Intel ® Iris™ Pro Graphics P580 (GT4) Intel ® Iris Pro Graphics P555 (GT3)


350 MHz / 1 GHz 700 MHz / 1 GHz 650 MHz / 1 GHz

Memory (DDR4)

LVDS

DP++

2133 MT/s dual channel ECC 2133 MT/s dual channel ECC

Yes Yes

Yes Yes

2133 MT/s dual channel ECC

Yes

Yes

VGA


Yes

45 W (35W)

Yes

45 W (N.A)

Yes

45 W (N.A)

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2 Specifications

2.1 Feature List

Table 3 Feature Summary

Form Factor

Processor

Memory

Chipset

Audio

Ethernet

Graphics Options

Based on COM Express™ standard pinout Type 6 Rev. 2.1 (Basic size 95 x 125 mm)

Intel ® 6th Generation Core i7,i5,i3 Celeron and Xeon mobile processors

Two memory sockets (located on the top and bottom side of the conga-TS170). Supports

-

SO-DIMM DDR4 (voltage @ 1.2V) modules

-

Data rates up to 2133 MT/s

-

Maximum 32 GB capacity (2x16 GB)

NOTE : Variants that feature the Intel CM236 chipset support ECC memory

Mobile Intel ® 100 Series Chipset QM170, HM170 and CM236 PCH

High definition audio interface with support for multiple codecs

Gigabit Ethernet support via the onboard Intel ® i219-LM GbE LAN controller (with AMT 11 support)

Intel ® Gen. 9 HD Graphics. Supports:

-

API (DirectX 12, Direct3D 12, OpenGL 4.4, OpenCL 2.1)

-

Intel ® QuickSync & Clear Video Technology HD (hardware accelerated video decode/encode/processing/transcode)

Up to three independent displays

NOTE : Variants equipped with Intel ® Xeon ® E3-1515MV5 feature the Intel ® Iris Pro Graphics

3x DP++

1x LVDS

1x VGA

1x PEG x16 port (Gen 3)

Resolutions up to 4K

Peripheral Interfaces USB Interfaces:

-

-

Up to 8x USB 2.0

Up to 4x USB 3.0

4x SATA

2x UART

® 6 Gb/s with RAID support 0/1/5/10

8x PCI Express ® Gen. 3 lanes

1x Optional eDP 1.3 interface (assembly option)

NOTE :

The conga-TS170 does not natively support TMDS. A DP++ to TMDS converter (e.g. PTN3360D) needs to be implemented.

I²C bus (fast mode, 400 kHz, multi-master)

LPC bus (no DMA)

SM Bus

SPI

GPIOs

BIOS AMI Aptio ® V UEFI 2.x firmware, 8/16 MB serial SPI with congatec Embedded BIOS features

Power Management ACPI 5.0

compliant with battery support. Also supports DeepSx and Suspend to RAM (S3) congatec Board

Controller

Security

Multi-stage watchdog, non-volatile user data storage, manufacturing and board information, board statistics, hardware monitoring, fan control, I²C bus, power loss control

Optional discrete Trusted Platform Module “TPM 1.2/2.0”; AES Instructions

Note

Some features are optional.

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2.2

2.3

Supported Operating Systems

The conga-TS170 supports the following operating systems.

• Microsoft ® Windows ® 10

• Microsoft ® Windows ® 8.1

• Microsoft ® Windows ® 7

• Microsoft ® Windows ® Embedded Standard

• Linux

Mechanical Dimensions

• 95.0 mm x 125.0 mm

• Height approximately 18 or 21 mm (including heatspreader) depending on the carrier board connector that is used. If the 5 mm (height) carrier board connector is used, then approximate overall height is 18 mm. If the 8 mm (height) carrier board connector is used, then approximate overall height is 21 mm.

4.00

5.00

7.00

2.00±10%

4.50

Heatspreader

Module PCB

Carrier Board PCB

All dimensions in millimeter

13.00

18.00

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2.4 Supply Voltage Standard Power

• 12V DC ± 5%

The dynamic range shall not exceed the static range.

12.60V

12.10V

12V

11.90V

11.40V

Absolute Maximum

Dynamic Range

Nominal Static Range

Absolute Minimum

2.4.1 Electrical Characteristics

Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for pinout Type 6 (dual connector, 440 pins).

Power Rail Module Pin

Current Capability

(Ampere)

VCC_12V 12

VCC_5V-SBY 2

VCC_RTC 0.5

5

3

Nominal

Input

(Volts)

12

Input

Range

(Volts)

Derated

Input

(Volts)

11.4-12.6

11.4

4.75-5.25

4.75

2.5-3.3

Max. Input Ripple

(10Hz to 20MHz)

(mV)

+/- 100

+/- 50

+/- 20

Max. Module Input

Power (w. derated input)

(Watts)

137

9

Assumed

Conversion

Efficiency

85%

Max. Load

Power

(Watts)

116

2.4.2 Rise Time

The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250 V/s. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.

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2.5 Power Consumption

The power consumption values were measured with the following setup:

• conga-TS170 COM

• modified congatec carrier board

• conga-TS170 cooling solution

• Microsoft Windows 7 (64 bit)

Note

The CPU was stressed to its maximum workload with the Intel ® Thermal Analysis Tool.

Table 4 Measurement Description

The power consumption values were recorded during the following system states:

System State Description

S0: Minimum value Lowest frequency mode (LFM) with minimum core voltage during desktop idle

S0: Maximum value Highest frequency mode (HFM/Turbo Boost)

S0: Peak value Highest current spike during the measurement of “S0: Maximum value”. This state shows the peak value during runtime

S3

S5

COM is powered by VCC_5V_SBY

COM is powered by VCC_5V_SBY

Note

1. The fan and SATA drives were powered externally.

Comment

The CPU was stressed to its maximum frequency

The CPU was stressed to its maximum frequency

Consider this value when designing the system’s power supply to ensure that sufficient power is supplied during worst case scenarios

2. All other peripherals except the LCD monitor were disconnected before measurement.

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2.6

Table 5 Power Consumption Values

The table below provides additional information about the conga-TS170 power consumption. The values were recorded at various operating mode.

Part

No.

045900

045901

045902

4 GB

4 GB

4 GB

045903

045904

4 GB

4 GB

045905 4 GB

045906 (ECC) 4 GB

045907 (ECC) 4 GB

045908 (ECC) 4 GB

045909 (ECC) 4 GB

045910 4 GB

045911 4 GB

045912 (ECC) 4 GB

045913 (ECC) 4 GB

045914 (ECC) 4 GB

Note

Memory

Size

H.W

Rev.

A.0

A.0

X.0

A.0

A.2

A.2

A.1

A.0

X.0

A.0

A.0

A.1

A.2

A.2

A.2

BIOS

Rev.

OS

(64 bit) Variant

CPU

Cores Freq/Turbo

(GHz)

BQSLR005 Windows 7 Intel ® Core™ i7-6820EQ 4 2.8/3.5

BQSLR005 Windows 7 Intel ® Core™ i7-6822EQ 4


2.0/2.8

2.7/3.4


BHSLR005 Windows 7 Intel ® Core™ i3-6100E 2

BHSLR005 Windows 7 Intel ® Core™ i3-6102E 2

BQSLR005 Windows 7 Intel ® Xeon ® E3-1505M v5 4

BQSLR005 Windows 7 Intel ® Xeon ® E3-1505L v5 4

BQSLR112 Windows 7 Intel ® Core™ i3-6100E 2

BQSLR112 Windows 7 Intel ® Core™ i3-6102E 2

BHSLR112 Windows 7 Intel ® Celeron ® G3900E 2

BHSLR112 Windows 7 Intel ® Celeron ® G3902E 2

BQSLR112 Windows 7 Intel ® Xeon ® E3-1515M v5 4



1.9/2.7

2.7/N.A

1.9/N.A

2.8/3.7

2.0/2.8

2.7/N.A

1.9/N.A

2.4/N.A

1.6/N.A

2.8/3.7

2.0/3.4

1.9/3.3

With fast input voltage rise time, the inrush current may exceed the measured peak current.

S0:

Min

0.65

0.66

0.66

0.66

0.66

0.62

0.72

0.65

0.67

0.62

0.62

0.58

1.02

0.96

0.83

3.15

3.09

2.51

5.73

3.06

3.87

2.73

2.29

1.66

5.70

5.64

5.41

S0:

Max

5.27

3.35

5.32

Current (A)

S0:

Peak

S3

5.45

0.10

3.45

5.69

0.10

0.09

3.24

3.54

2.74

5.95

3.16

4.08

2.86

2.33

1.73

6.23

6.68

5.90

0.10

0.09

0.10

0.10

0.10

0.07

0.07

0.07

0.08

0.15

0.15

0.16

S5

0.06

0.07

0.06

0.06

0.06

0.06

0.06

0.07

0.06

0.06

0.07

0.06

0.14

0.14

0.14

Supply Voltage Battery Power

Table 6 CMOS Battery Power Consumption

RTC @

-10 o C

20 o C

70 o C

Voltage Current

3V DC 1.18 µA

3V DC

3V DC

1.33 µA

1.99 µA

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2.7

Note

1. Do not use the CMOS battery power consumption values listed above to calculate CMOS battery lifetime.

2. Measure the CMOS battery power consumption in your customer specific application in worst case conditions (for example, during high temperature and high battery voltage).

3. Consider also the self-discharge of the battery when calculating the lifetime of the CMOS battery. For more information, refer to application note AN9_RTC_Battery_Lifetime.pdf on congatec GmbH website at www.congatec.com/support/application-notes.

4. We recommend to always have a CMOS battery present when operating the conga-TS170.

Environmental Specifications

Temperature

Humidity

Operation: 0° to 60°C

Operation: 10% to 90%

Caution

Storage: -20° to +80°C

Storage: 5% to 95%

The above operating temperatures must be strictly adhered to at all times. When using a congatec heatspreader, the maximum operating temperature refers to any measurable spot on the heatspreader’s surface.

Humidity specifications are for non-condensing conditions.

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3 Block Diagram

COM Express

Type 6

A-B Connector

Aux Channel

6 th Gen. Intel® Core™ processor

CPU Platform

Turbo Boost 2.0 Technology

HT Technology AMT 11.0

AVX2 SSE 4.2

VT

TXT

AES-NI

TSX

VGA

LVDS/eDP

LVDS/eDP

DP to VGA eDP to LVDS

Bridge eDP

HDA I/F

USB Port 0..7

PCIe lane 0 - 5

Ethernet

Ethernet 10/100/1000

Intel i219LM

SPI Flash 0

SPI

SATA Port 0 - 3

LPC Bus

SM Bus

SER0/1

GPIOs

LID#/SLEEP#

FAN control

I2C Bus

TPM

* Supports only TMDS if VGA is enabled.

HDA

USB 2.0

PCIe Gen. 3

SPI

SATA 6G

LPC

Integrated Intel HD Graphics

Display Interface

TMDS and DP up to 4K resolution

Hardware Graphics Accelerators

3D Vector Graphics

2D DXVA2

Video Codecs

MPEG-2

H.265

WMV9

Multimedia Features

ASRC

APIs

OpenCL 2.1

OpenGL 4.4

DirectX 12

DMI Gen3

Mobile Intel ® 100/C236 Series PCH-H

PCIe Gen. 3

PECI

XDP

2x SO-DIMM (X1/X2)

Dual Channel DDR4

SM Bus

PECI

PCIe Gen. 3

MGMNT

PCIe

SATA

I/O Interfaces

LPC Bus

USB 2.0

HDA

USB 3.0

congatec System

Management

Controller

UART0/1

COM Express

Type 6

C-D Connector

*

DP++ (DP/TMDS)

DP++ (DP/TMDS)

DP++ (DP/TMDS)

PEG x16

USB 3.0 Port 0 - 3

PCIe lane 6 - 7

(TX BC) congatec custom

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4 Cooling Solutions

congatec GmbH offers the following cooling solutions for the conga-TS170 variants. The dimensions of the cooling solutions are shown in the sub-sections. All measurements are in millimeters.

Table 7 Cooling Solution Variants

1

2

3

Cooling Solution

CSA

CSP

HSP

Part No.

045930

045931

045932

045933

045934

045935

Description

Active cooling solution with integrated heat pipes and 2.7 mm bore-hole standoffs

Active cooling solution with integrated heat pipes and M2.5 mm threaded standoffs

Passive cooling solution with integrated heat pipes and 2.7 mm bore-hole standoffs

Passive cooling solution with integrated heat pipes and M2.5 mm threaded standoffs

Heatspreader with integrated heat pipes and 2.7 mm bore-hole standoffs

Heatspreader with integrated heat pipes and M2.5 mm threaded standoffs

Note

1. We recommend a maximum torque of 0.4 Nm for carrier board mounting screws and 0.5 Nm for module mounting screws.

2. The gap pad material used on congatec heatspreaders may contain silicon oil that can seep out over time depending on the environmental conditions it is subjected to. For more information about this subject, contact your local congatec sales representative and request the gap pad material manufacturer’s specification

Caution

1. The congatec heatspreaders/cooling solutions are tested only within the commercial temperature range of 0° to 60°C. Therefore, if your application that features a congatec heatspreader/cooling solution operates outside this temperature range, ensure the correct operating temperature of the module is maintained at all times. This may require additional cooling components for your final application’s thermal solution.

2. For adequate heat dissipation, use the mounting holes on the cooling solution to attach it to the module. Apply thread-locking fluid on the screws if the cooling solution is used in a high shock and/or vibration environment. To prevent the standoff from stripping or crossthreading, use non-threaded carrier board standoffs to mount threaded cooling solutions.

3. For applications that require vertically-mounted cooling solution, use only coolers that secure the thermal stacks with fixing post. Without the fixing post feature, the thermal stacks may move.

4. Do not exceed the recommended maximum torque. Doing so may damage the module or the carrier board, or both.

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4.1 CSA Dimensions

87

31 14.5

29

21

20

96.6

95

M2.5 x 13 mm threaded standoff for threaded version or

ø2.7 x 13 mm non-threaded standoff for borehole version

F

2.7 2.7

R0.3

1.24°

0.62°

R0.9

F

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4.2 CSP Dimensions

87

31 14.5

28

20



95

E

2.7 2.7

R0.3

1.24°

0.62°

R0.9

E

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4.3 HSP Dimensions

87

56

41.5

11

4



95

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4.4 Heatspreader Thermal Imagery

The conga-TS170 heatspreader solution features heat pipes. A heat pipe is a simple device that can quickly transfer heat from one point to another. They are often referred to as the “superconductors” of heat as they possess an extra ordinary heat transfer capacity and rate with almost no heat loss.

The thermal image below provides a reference to where the heat is being transferred to on the heatspreader surface area. System designers must ensure that the system’s cooling solution is designed to dissipate the heat from the hottest surface spots of the heatspreader.

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5 Onboard Temperature Sensors

The conga-TS170 features two sensors on the top side of the module and two optional DRAM sensors (build-time) on the top and bottom side of the module.

Top-Side (CPU Temperature & Board Temperature Sensor) :

The CPU temperature sensor (T00) is located in the CPU (U1). This sensor measures the CPU temperature and is defined in CGOS API as

CGOS_TEMP_CPU.

The board temperature sensor (T01) is located in the congatec Board Controller (U22). This sensor measures the board temperature and is defined in CGOS API as CGOS_TEMP_BOARD.

The sensor locations are shown below:

Optional DRAM Sensor Location

(BOM option)

Board Controller Temp. Sensor

T01

CPU Temperature Sensor

T00

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Bottom-Side (Optional DRAM Sensor):

The conga-TS170 offers an optional sensor on the bottom side of the module. This sensor measures the temperature of the DRAM module and is defined in CGOS API as CGOS_TEMP_BOTDIMM_ENV.

The DRAM sensor location is shown below:

Optional DRAM Sensor Location

(BOM option)

Note

The optional DRAM sensors are not populated on conga-TS170 standard variants. The sensors are available only as assembly option.

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6 Connector Rows

The conga-TS170 is connected to the carrier board via two 220-pin connectors (COM Express Type 6 pinout). These connectors are broken down into four rows. The primary connector consists of rows A and B while the secondary connector consists of rows C and D.

6.1 Primary and Secondary Connector Rows

The following subsystems can be found on the primary and secondary connector rows.

6.1.1 PCI Express™

The conga-TS170 offers six PCI Express™ lanes on the A–B connector and two PCIe lanes on the C–D connector. The lanes support the following:

• up to 8 GT/s (Gen 3) speed

• default 8 x1 link configuration

• a 1 x4 + 4 x1 link, 1 x4 + 1 x2 + 2 x1 link or a 3 x2 + 2 x1 link via a special/customized BIOS firmware

6.1.2 PCI Express Graphics (PEG)

The conga-TS170 offers 16 PEG ports on the C–D connector. The PEG lanes are same as PCIe lanes 16-31. The lanes support the following:

• up to 8 GT/s (Gen 3) speed

• optional configuration for both graphics or non-graphic devices (increases available PCIe lanes and enables PEG port to support x1, x2, x4 or x8 PCIe devices

• lane reversal

• three controllers that can automatically operate on a lower link width, allowing up to three simultaneous operating devices on the PEG interface

• a 1 x16 link (default), 2 x8 link or a 1 x8 + 2 x4 link configuration (see diagram below)

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PCI Express Graphics Lane Configuration

PEG

LANE

0

PEG

LANE

1

PEG

LANE

2

PEG

LANE

3

PEG

LANE

4

PEG

LANE

5

PEG

LANE

6

PEG

LANE

7

PEG

LANE

8

PEG

LANE

9

PEG

LANE

10

PEG

LANE

11

PEG

LANE

12

PEG

LANE

13

PEG

LANE

14

PEG

LANE

15

Single Link (1x16 Link)

Link 1

Double Links (2x8 Links)

Link 1 Link 2

Link 1

Triple Links (1x8 + 2x4 Links)

Link 2 Link 3

Note

The PEG lanes can not be linked together with the PCI Express lanes in section 6.1.1 “PCI Express™”.

6.1.3 Display Interfaces

The conga-TS170 supports the following:

• up to three DP++

• single- or dual-channel LVDS

• VGA

• three independent displays (display combinations are described in the table below)

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Table 8 Maximum Supported Resolutions

Display 1

Interface Max. Resolution

Option 1 DP or

TMDS

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

Option 2 DP or

TMDS

Option 3 DP or

TMDS

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

Option 4 DP or

TMDS

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

Note

Display 2

Interface Max. Resolution

DP or

TMDS

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

DP or

TMDS

DP or

TMDS

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

VGA 1920x1200 @ 60 Hz

Interface

DP or

TMDS

LVDS or eDP (BOM Option)

VGA

LVDS or eDP (BOM Option)

Display 3

Max. Resolution

4096x2304 @ 60 Hz, 24 bpp/

4096x2160 @ 24 Hz, 24 bpp

1920x1200 @ 60 Hz (dual LVDS mode)

4096x2304 @ 60 Hz, 24bpp

1920x1200 @ 60 Hz

1920x1200 @ 60 Hz (dual LVDS mode)

4096x2304 @ 60 Hz, 24bpp

1. If VGA interface is enabled in the BIOS menu, the third DDI interface (DDI3) will support only TMDS.

2. To enable VGA, go to Advanced -> Graphics menu and change the Digital Display Interface 3 option.

6.1.3.1 DisplayPort (DP)

The conga-TS170 supports:

• up to three dual mode DP ports (DP++)

• VESA DisplayPort Standard 1.2

• data rate of 1.62 GT/s, 2.97 GT/s and 5.4 GT/s on 1, 2 or 4 data lanes

• up to 4096x2304 resolutions at 60 Hz

• Audio formats such as AC-3 Dolby Digital, Dolby Digital Plus, DTS-HD, LPCM, 192 KHz/24 bit, 8 channel, Dolby TrueHD, DTS-HD Master

Audio (Lossless Blu-Ray Disc Audio Format)

• up to three independent DP displays

Note

A maximum of two independent DP displays are supported if the VGA interface is enabled

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6.1.3.2 LVDS/eDP

The conga-TS170 offers an LVDS interface with optional eDP overlay on the A-B connector. The LVDS/eDP interface is configured to provide

LVDS signals by default. The interface can optionally support eDP signals via a hardware change (assembly option).

The LVDS interface supports:

• single or dual channel LVDS (color depths of 18 bpp or 24 bpp)

• integrated flat panel interface with clock frequency up to 112 MHz

• VESA and OpenLDI LVDS color mappings

• automatic panel detection via Embedded Panel Interface based on VESA EDID TM 1.3

• resolution up to 1920x1200 in dual LVDS mode

Note

The LVDS/eDP interface does not supports both LVDS and eDP signals at the same time.

6.1.3.3 VGA

The conga-TS170 offers a VGA interface via an eDP to VGA converter, connected to the two upper data lanes of the embedded DisplayPort.

Note

To enable VGA interface, go to the Advanced -> Graphics BIOS setup menu and set the Digital Display Interface 3 to TMDS interface.

6.1.4 SATA

The conga-TS170 offers four SATA interfaces (SATA 0-3) on the A–B connector. The interfaces support:

• independent DMA operation

• data transfer rates up to 6.0 Gb/s

• AHCI mode using memory space and RAID mode

• Hot-plug detect

Note

The interface does not support legacy mode using I/O space.

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6.1.5 USB

The conga-TS170 offers eight USB 2.0 interfaces on the A–B connector and four SuperSpeed signals on the C–D connector. The xHCI host controller supports:

• USB 3.0 specification

• SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling

• data transfers of up to 5 Gbps

• supports USB debug port on all USB 3.0 capable ports

6.1.6 Gigabit Ethernet

The conga-TS170 offers a Gigabit Ethernet interface via an onboard Intel ®

10/100/1000 Mbps and half-duplex operation at 10/100 Mbps.

i219-LM Phy. The interface supports full-duplex operation at

Note

1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation of Ethernet Phy since it has only three LED outputs—ACT#, LINK100# and LINK1000#.

2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS170 module.

6.1.7 High Definition Audio (HDA) Interface

The conga-TS170 provides an HDA interface on the A–B connector.

6.1.8 LPC Bus

The conga-TS170 offers the LPC (Low Pin Count) bus through the Intel ® addresses, see section 10.1.1 ”LPC Bus”.

100/C236 Series PCH. For information about the decoded LPC

6.1.9 I²C Bus Fast Mode

The I²C bus is implemented through the congatec board controller and accessed through the congatec CGOS driver and API. The controller provides a fast-mode multi-master I²C host controller that has maximum I²C bandwidth.

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6.1.10 ExpressCard™

The conga-TS170 supports the implementation of ExpressCards, which requires the dedication of one USB 2.0 port or a x1 PCI Express link for each ExpressCard used.

6.1.11 General Purpose Serial Interface

The conga-TS170 offers two UART interfaces via two UART controllers integrated in the congatec Board Controller. These controllers support up to 1 MB/s and can operate in low-speed, full-speed and high-speed modes. The UART interfaces are routed to the A–B connector.

Note

1. The UART interfaces require congatec driver to function.

2. The interfaces do not support legacy COM port emulation.

6.1.12 GPIOs

The conga-TS170 offers General Purpose Input/Output signals on the A–B connector. The GPIO signals are controlled by the congatec Board controller.

6.1.13 Power Control

PWR_OK

Power OK from main power supply or carrier board voltage regulator circuitry. A high value indicates that the power is good and the module can start its onboard power sequencing.

Carrier board hardware must drive this signal low until all power rails and clocks are stable. Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems. It is a good design practice to delay the PWR_OK signal a little (typically 100ms) after all carrier board power rails are up, to ensure a stable system.

A sample screenshot is shown below:

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Note

The module is kept in reset as long as the PWR_OK is driven by carrier board hardware.

35/126

The conga-TS170 PWR_OK input circuitry is implemented as shown below:

+V12.0_S0

PWR_OK

R1%4k75S02

R1%20k0S02

R1%1k00S02

TBC847

R1%10kS02

R1%4k75S02

To Module Power Logic

The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also allows for carrier board designs that are not driving

PWR_OK. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier board hardware drives the signal low until it is safe to let the module boot-up.

When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when the carrier board hardware is ready to boot.

The three typical usage scenarios for a carrier board design are:

• Connect PWR_OK to the “power good” signal of an ATX type power supply.

• Connect PWR_OK to the last voltage regulator in the chain on the carrier board.

• Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail.

With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable.

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The conga-TS170 provides support for controlling ATX-style power supplies. When not using an ATX power supply then the conga-TS170’s pins

SUS_S3/PS_ON, 5V_SB, and PWRBTN# should be left unconnected.

SUS_S3#/PS_ON#

The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an ATXstyle power supply. In order to accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and is located on the carrier board.

PWRBTN#

When using ATX-style power supplies PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary-contact, active-low debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to 3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this signal from the system may vary as a result of modifications made in BIOS settings or by system software.

Standard 12V Power Supply Implementation Guidelines

The 12 volt input power is the sole operational power source for the conga-TS170. Other required voltages are generated internally on the module using onboard voltage regulators.

Note

When designing a power supply for a conga-TS170 application, be aware that the system may malfunction when a 12V power supply that produces non-monotonic voltage is used to power the system up. Though this problem is rare, it has been observed in some mobile power supply applications.

The cause of this problem is that some internal circuits on the module (e.g. clock-generator chips) generate their own reset signals when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming confused, thereby resulting in a malfunction.

To ensure this problem does not occur, observe the power supply rise waveform through an oscilloscope, during the power supply qualication phase. This will help to determine if the rise is indeed monotonic and does not have any dips. For more information, see the “Power Supply

Design Guide for Desktop Platform Form Factors” document at www.intel.com.

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6.1.14 Power Management

ACPI

The conga-TS170 supports Advanced Configuration and Power Interface (ACPI) specification, revision 5.0

.

It also supports Suspend to RAM

(S3). For more information, see section 8.3 “ACPI Suspend Modes and Resume Events”.

DEEP Sx

The Deep Sx is a lower power state employed to minimize the power consumption while in S3/S4/S5. In the Deep Sx state, the system entry condition determines if the system context is maintained or not. All power is shut off except for minimal logic which supports limited set of wake events for Deep Sx. The Deep Sx on resumption, puts system back into the state it is entered from. In other words, if Deep Sx state was entered from S3 state, then the resume path will place system back into S3.

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7 Additional Features

7.1 congatec Board Controller (cBC)

The conga-TS170 is equipped with Texas Instruments Tiva™ TM4E123GH6ZRBI7R microcontroller. This onboard microcontroller plays an important role for most of the congatec embedded/industrial PC features. It fully isolates some of the embedded features such as system monitoring or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86 processor is in a low power mode. It also ensures that the congatec embedded feature set is fully compatible amongst all congatec modules.

The board controller supports the following features:

7.1.1 Board Information

The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and firmware revisions, and so on. It also keeps track of dynamically changing data like runtime meter and boot counter.

7.1.2 Watchdog

The conga-TS170 is equipped with a multi stage watchdog solution that is triggered by software. For more information about the Watchdog feature, see the BIOS setup description in section 11.4.2 “Watchdog Submenu” of this document and application note AN3_Watchdog.pdf on the congatec GmbH website at www.congatec.com.

Note

The conga-TS170 module does not support the watchdog NMI mode.

7.1.3 I

2

C Bus

The conga-TS170 supports I 2 C bus. Thanks to the I 2 C host controller in the cBC, the I 2 C bus is multi-master capable and runs at fast mode.

7.1.4 Power Loss Control

The cBC has full control of the power-up of the module and therefore can be used to specify the behavior of the system after an AC power loss condition. Supported modes are “Always On”, “Remain Off” and “Last State”.

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7.1.5 Fan Control

The conga-TS170 has additional signals and functions to further improve system management. One of these signals is FAN_PWMOUT, an output signal that allows system fan control using a PWM (Pulse Width Modulation) output. Additionally, there is an input signal called FAN_TACHOIN that provides the ability to monitor the system’s fan RPMs (revolutions per minute). This signal must receive two pulses per revolution in order to produce an accurate reading. For this reason, a two pulse per revolution fan or similar hardware solution is recommended.

Note

1. A four wire fan must be used to generate the correct speed readout.

2. For the correct fan control (FAN_PWMOUT, FAN_TACHIN) implementation, see the COM Express Design Guide.

7.2 OEM BIOS Customization

The conga-TS170 is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI firmware. The congatec Embedded BIOS allows system designers to modify the BIOS. For more information about customizing the congatec Embedded

BIOS, refer to the congatec System Utility user’s guide CGUTLm1x.pdf on the congatec website at www.congatec.com or contact technical support.

The customization features supported are described below:

7.2.1 OEM Default Settings

This feature allows system designers to create and store their own BIOS default configuration. Customized BIOS development by congatec for

OEM default settings is no longer necessary because customers can easily perform this configuration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_OEM_Default_Map.pdf on the congatec website for details on how to add OEM default settings to the congatec Embedded BIOS.

7.2.2 OEM Boot Logo

This feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo. Customized

BIOS development by congatec for OEM Boot Logo is no longer necessary because customers can easily perform this configuration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_And_Add_Bootlogo.pdf on the congatec website for details on how to add OEM boot logo to the congatec Embedded BIOS.

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7.2.3 OEM POST Logo

This feature allows system designers to replace the congatec POST logo displayed in the upper left corner of the screen during BIOS POST with their own BIOS POST logo. Use the congatec system utility CGUTIL 1.5.4 or later to replace/add the OEM POST logo.

7.2.4 OEM BIOS Code/Data

With the congatec embedded BIOS it is possible for system designers to add their own code to the BIOS POST process. The congatec

Embedded BIOS first calls the OEM code before handing over control to the OS loader.

Except for custom specific code, this feature can also be used to support, Windows 7, Windows 8 OEM activation (OA3.0), verb tables for HDA codecs, PCI/PCIe OpROMs, bootloaders, rare graphic modes and Super I/O controller initialization.

Note

The OEM BIOS code of the new UEFI based firmware is only called when the CSM (Compatibility Support Module) is enabled in the BIOS setup menu. Contact congatec technical support for more information on how to add OEM code.

7.2.5 OEM DXE Driver

This feature allows designers to add their own UEFI DXE driver to the congatec embedded BIOS. Contact congatec technical support for more information on how to add an OEM DXE driver.

7.3 congatec Battery Management Interface

In order to facilitate the development of battery powered mobile systems based on embedded modules, congatec GmbH has defined an interface for the exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according to the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable operating system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states, ...) without the need for any additional modifications to the system BIOS.

In addtion to the ACPI-Compliant Control Method Battery mentioned above, the latest versions of the conga-TS170 BIOS and board controller firmware also support LTC1760 battery manager from Linear Technology and a battery only solution (no charger). All three battery solutions are supported on the I2C bus and the SMBus. This gives the system designer more flexibility when choosing the appropriate battery sub-system.

For more information about the supported Battery Manager interface, contact your local congatec sales representative.

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7.4

7.5

7.6

API Support (CGOS)

In order to benefit from the above mentioned non-industry standard feature set, congatec provides an API that allows application software developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming

Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux.

The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules.

All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software developers guide, which is available on the congatec website .

Security Features

The conga-TS170 can be equipped optionally with a “Trusted Platform Module“ (TPM 1.2/2.0). (not available with an internal TPM platform module), however there is software support for an external TPM by the BIOS. This TPM 1.2/2.0 includes coprocessors to calculate efficient hash and RSA algorithms with key lengths up to 2,048 bits as well as a real random number generator. Security sensitive applications like gaming and e-commerce will benefit also with improved authentication, integrity and confidence levels.

Suspend to Ram

The Suspend to RAM feature is available on the conga-TS170.

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8 conga Tech Notes

The conga-TS170 has some technological features that require additional explanation. The following section will give the reader a better understanding of some of these features. This information will also help to gain a better understanding of the information found in the System

Resources section of this user’s guide as well as some of the setup nodes found in the BIOS Setup Program description section.

8.1 Adaptive Thermal Monitor and Catastrophic Thermal Protection

Intel ® Xeon, Core™ i7/i5/i3 and Celeron temperature that the Intel submenu “CPU submenu”.

®

® processors have a thermal monitor feature that helps to control the processor temperature. The integrated TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation

Thermal Monitor uses to activate the TCC can be slightly modified via TCC Activation Offset in BIOS setup

The Adaptive Thermal Monitor controls the processor temperature using two methods:

• Adjusting the processor’s operating frequency and core voltage (EIST transitions)

• Modulating (start/stop) the processor’s internal clocks at a duty cycle of 25% on and 75% off

When activated, the TCC causes both processor core and graphics core to reduce frequency and voltage adaptively. The Adaptive Thermal

Monitor will remain active as long as the package temperature remains at its specified limit. Therefore, the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de-activated. Clock modulation is activated if frequency and voltage adjustments are insufficient. Additional hardware, software drivers, or operating system support is not required.

Intel ® ’s Core™ i7/i5/i3 and Celeron ® processors use the THERMTRIP# signal to shut down the system if the processor’s silicon reaches a temperature of approximately 125°C. The THERMTRIP# signal activation is completely independent from processor activity and therefore does not produce any bus cycles.

Note

1. For THERMTRIP# to switch off the system automatically, use an ATX style power supply

2. The maximum operating temperature for Intel® Xeon, Core™ i7/i5/i3 and Celeron ® processors is 100°C

3. To ensure that the TCC is active for only short periods of time, thus reducing the impact on processor performance to a minimum, it is necessary to have a properly designed thermal solution. The Intel ® Xeon, Core™ i7/i5/i3, Celeron datasheet can provide you with more information about this subject.

® and Pentium ® processor’s respective

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8.2 Intel

®

Processor Features

8.2.1 Intel

®

SpeedStep

®

Technology (EIST)

Intel ® processor on the conga-TS170 runs at different voltage/frequency states (performance states), which is referred to as Enhanced Intel

SpeedStep

®

® Technology (EIST). Operating systems that support performance control take advantage of microprocessors that use several different performance states in order to efficiently operate the processor when it is not being fully used. The operating system will determine the necessary performance state that the processor should run at so that the optimal balance between performance and power consumption can be achieved during runtime. The Windows family of operating systems links its processor performance control policy to the power scheme setting. You must ensure that the power scheme setting you choose has the ability to support Enhanced Intel ® SpeedStep ® technology.

The 6th Generation Intel ® Core ™ processor family supports Intel Speed Shift, a new and energy efficient method for frequency control. This feature is also referred to as Hardware-controlled Performance States (HWP). It is a hardware implementation of the ACPI defined Collaborative

Processor Performance Control (CPPC2) and is supported by newer operating systems (Win 8.1 or newer).

With this feature enabled, the processor autonomously selects performance states based on workload demand and thermal limits while also considering information provided by the OS e.g., the performance limits and workload history.

8.2.2 Intel

®

Turbo Boost Technology

Intel ® Turbo Boost Technology allows processor cores to run faster than the base operating frequency if it’s operating below power, current, and temperature specification limits. Intel ® Turbo Boost Technology is activated when the Operating System (OS) requests the highest processor performance state. The maximum frequency of Intel ® Turbo Boost Technology is dependent on the number of active cores. The amount of time the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment.

Any of the following can set the upper limit of Intel ® Turbo Boost Technology on a given workload:

• Number of active cores

• Estimated current consumption

• Estimated power consumption

• Processor temperature

When the processor is operating below these limits and the user’s workload demands additional performance, the processor frequency will dynamically increase by 100 MHz on short and regular intervals until the upper limit is met or the maximum possible upside for the number of active cores is reached. For more information about Intel ® Turbo Boost 2 Technology visit the Intel ® website.

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Note

1. Only conga-TS170 variants that feature the Xeon, Core™ i7 and i5 processors support Intel ® Turbo Boost 2 Technology. Refer to section

2.5 “Power Consumption” for information about the maximum turbo frequency available for each conga-TS170 variant.

2. For real-time sensitive applications, disable EIST and Turbo Mode in the BIOS setup to ensure a more deterministic performance.

8.2.3 Intel

®

Virtualization Technology

Intel

(Intel

®

®

Virtualization Technology (Intel ® VT) makes a single system appear as multiple independent systems to software. With this technology, multiple, independent operating systems can run simultaneously on a single system. The technology components support virtualization of platforms based on Intel architecture microprocessors and chipsets. Intel ® Virtualization Technology for IA-32, Intel ® 64 and Intel ®

VT-x) added hardware support in the processor to improve the virtualization performance and robustness.

Architecture

RTS Real-Time Hypervisor supports Intel VT and is verified on all current congatec x86 hardware.

Note congatec supports RTS Hypervisor.

8.2.4 Thermal Management

ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This helps the operating system to make cooling decisions according to the demands of the application.

The conga-TS170 supports Critical Trip Point. This cooling policy ensures that the operating system shuts down properly if the temperature in the thermal zone reaches a critical point, in order to prevent damage to the system as a result of high temperatures. Use the “critical trip point” setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system The

Automatic Critical Trip Point BIOS setting shuts down the system 5°C above the maximum specified temperature of the processor e.g. 105°C for the 6th Gen Intel ® Core™ processors supported on conga-TS170.

For processor passive cooling, use the Thermal Control Circuit (TCC ) Activation Offset setting in the CPU configuration setup sub menu. The

TCC in the processor is activated at 100°C by default but can be lowered by the Activation Offset e.g., setting 10 activates TCC at 90°C. ACPI

OS support is not required.

Note

The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the appropriate trip points.

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8.3

8.4

ACPI Suspend Modes and Resume Events

The conga-TS170 BIOS supports S3 (Suspend to RAM). For more information about S3 wake events, see section 11.4.11 “ACPI Submenu”.

Table 9 Wake Events

The table below lists the events that wake the system from S3.

Wake Event

Power Button

Onboard LAN Event

Conditions/Remarks

Wakes unconditionally from S3-S5.

Device driver must be configured for Wake On LAN support.

PCI Express WAKE#

WAKE#

Wakes unconditionally from S3-S5.

Wakes uncondionally from S3.

PME# Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device or enable ‘Resume

On PME#’ in the Power setup menu.

USB Mouse/Keyboard Event When Standby mode is set to S3, USB hardware must be powered by standby power source.

Set USB Device Wakeup from S3/S4 to Enabled in the ACPI setup menu (if setup node is available in BIOS setup program).

In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the computer out of standby’.

RTC Alarm Activate and configure Resume On RTC Alarm in the power setup menu. Wakes unconditionally from S3-S5.

Watchdog Power Button Event Wakes unconditionally from S3-S5.

DDR4 Memory

The Intel 6th Generaation Processor featured on the conga-TS170 supports DDR4 memory modules up to 2133 MT/s. The DDR4 memory modules have lower voltage requirements with higher data rate transfer speeds. They operate at a voltage of 1.2V. With this low voltage system memory interface on the processor, the conga-TS170 offers a system optimized for lowest possible power consumption. The reduction in power consumption due to lower voltage subsequently reduces the heat generated.

Caution

Do not connect memory modules from different vendors or with different part numbers on both memory sockets. Doing so may cause serious signal integrity and functional issues.

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9 Signal Descriptions and Pinout Tables

The following section describes the signals found on COM Express™ Type 6 connectors used for congatec GmbH modules. The pinout of the modules complies with COM Express Type 6 Rev. 2.1.

The table below describes the terminology used in this section. The PU/PD column indicates if a pull-up or pull-down resistor has been used.

If the field entry area in this column for the signal is empty, then no pull-up or pull-down resistor has been implemented by congatec. The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level.

Note

The Signal Description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs implemented by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to the respective chip’s datasheet.

Table 10 Signal Tables Terminology Descriptions

Term

I

PU

PD

O

I/O 3.3V

I/O 5V

I 3.3V

I 5V

I/O 3.3VSB

O 3.3V

O 5V

OD

P

DDC

PCIE

PEG

SATA

REF

PDS

Description congatec implemented pull-up resistor congatec implemented pull-down resistor

Input to the module

Output from the module

Bi-directional signal 3.3V tolerant

Bi-directional signal 5V tolerant

Input 3.3V tolerant

Input 5V tolerant

Input 3.3V tolerant active in standby state

Output 3.3V signal level

Output 5V signal level

Open drain output

Power Input/Output

Display Data Channel

In compliance with PCI Express Base Specification, Revision 2.0

PCI Express Graphics

In compliance with Serial ATA specification Revision 2.6 and 3.0.

Reference voltage output. May be sourced from a module power plane.

Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal module capabilities (pinout type) to the Carrier Board.

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9.1 Connector Signal Descriptions

Table 11 Connector A–B Pinout

Pin Row A

A1 GND (FIXED)

A2 GBE0_MDI3-

A3 GBE0_MDI3+

A4 GBE0_LINK100#

A5 GBE0_LINK1000#

A6 GBE0_MDI2-

A7 GBE0_MDI2+

A8 GBE0_LINK#

A9 GBE0_MDI1-

A10 GBE0_MDI1+

A11 GND (FIXED)

A12 GBE0_MDI0-

A13 GBE0_MDI0+

A14 GBE0_CTREF (*)

A15 SUS_S3#

A16 SATA0_TX+

A17 SATA0_TX-

A18 SUS_S4#

A19 SATA0_RX+

A20 SATA0_RX-

A21 GND (FIXED)

A22 SATA2_TX+

A23 SATA2_TX-

A24 SUS_S5#

A25 SATA2_RX+

A26 SATA2_RX-

A27 BATLOW#

A28 (S)ATA_ACT#

A29 AC/HDA_SYNC

A30 AC/HDA_RST#

A31 GND (FIXED)

A32 AC/HDA_BITCLK

A33 AC/HDA_SDOUT

A34 BIOS_DIS0#

A35 THRMTRIP#

A36 USB6-

Pin Row B

B1 GND (FIXED)

B2 GBE0_ACT#

B3 LPC_FRAME#

B4 LPC_AD0

B5 LPC_AD1

B6 LPC_AD2

B7 LPC_AD3

B8 LPC_DRQ0# (*)

B9 LPC_DRQ1# (*)

B10 LPC_CLK

B11 GND (FIXED)

B12 PWRBTN#

B13 SMB_CK

B14 SMB_DAT

B15 SMB_ALERT#

B16 SATA1_TX+

B17 SATA1_TX-

B18 SUS_STAT#

B19 SATA1_RX+

B20 SATA1_RX-

B21 GND (FIXED)

B22 SATA3_TX+

B23 SATA3_TX-

B24 PWR_OK

B25 SATA3_RX+

B26 SATA3_RX-

B27 WDT

B28 AC/HDA_SDIN2 (*)

B29 AC/HDA_SDIN1

B30 AC/HDA_SDIN0

B31 GND (FIXED)

B32 SPKR

B33 I2C_CK

B34 I2C_DAT

B35 THRM#

B36 USB7-

Pin Row A

A56 PCIE_TX4-

A57 GND

A58 PCIE_TX3+

A59 PCIE_TX3-

A60 GND (FIXED)

A61 PCIE_TX2+

A62 PCIE_TX2-

A63 GPI1

A64 PCIE_TX1+

A65 PCIE_TX1-

A66 GND

A67 GPI2

A68 PCIE_TX0+

A69 PCIE_TX0-

A70 GND (FIXED)

A71 eDP_TX2+/LVDS_A0+

A72 eDP_TX2-/LVDS_A0-





A77 eDP/LVDS_VDD_EN

A78 LVDS_A3+

A79 LVDS_A3-

A80 GND (FIXED)

A81 eDP_TX3+/LVDS_A_CK+

A82 eDP_TX3-/LVDS_A_CK-

A83 eDP_AUX+/LVDS_I2C_CK

A84 eDP_AUX-/LVDS_I2C_DAT

A85 GPI3

A86 RSVD

A87 eDP_HPD

A88 PCIE0_CK_REF+

A89 PCIE0_CK_REF-

A90 GND (FIXED)

A91 SPI_POWER

Pin Row B

B56 PCIE_RX4-

B57 GPO2

B58 PCIE_RX3+

B59 PCIE_RX3-

B60 GND (FIXED)

B61 PCIE_RX2+

B62 PCIE_RX2-

B63 GPO3

B64 PCIE_RX1+

B65 PCIE_RX1-

B66 WAKE0#

B67 WAKE1#

B68 PCIE_RX0+

B69 PCIE_RX0-

B70 GND (FIXED)

B71 LVDS_B0+

B72 LVDS_B0-

B73 LVDS_B1+

B74 LVDS_B1-

B75 LVDS_B2+

B76 LVDS_B2-

B77 LVDS_B3+

B78 LVDS_B3-

B79 eDP/LVDS_BKLT_EN

B80 GND (FIXED)

B81 LVDS_B_CK+

B82 LVDS_B_CK-

B83 eDP/LVDS_BKLT_CTRL

B84 VCC_5V_SBY

B85 VCC_5V_SBY

B86 VCC_5V_SBY

B87 VCC_5V_SBY

B88 BIOS_DIS1#

B89 VGA_RED

B90 GND (FIXED)

B91 VGA_GRN

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Pin Row A

A37 USB6+

A38 USB_6_7_OC#

A39 USB4-

A40 USB4+

A41 GND (FIXED)

A42 USB2-

A43 USB2+

A44 USB_2_3_OC#

A45 USB0-

A46 USB0+

A47 VCC_RTC

A48 EXCD0_PERST#

A49 EXCD0_CPPE#

A50 LPC_SERIRQ

A51 GND (FIXED)

A52 PCIE_TX5+

A53 PCIE_TX5-

A54 GPI0

A55 PCIE_TX4+

Note

Pin Row B

B37 USB7+

B38 USB_4_5_OC#

B39 USB5-

B40 USB5+

B41 GND (FIXED)

B42 USB3-

B43 USB3+

B44 USB_0_1_OC#

B45 USB1-

B46 USB1+

B47 EXCD1_PERST#

B48 EXCD1_CPPE#

B49 SYS_RESET#

B50 CB_RESET#

B51 GND (FIXED)

B52 PCIE_RX5+

B53 PCIE_RX5-

B54 GPO1

B55 PCIE_RX4+

Pin Row A

A92 SPI_MISO

A93 GPO0

A94 SPI_CLK

A95 SPI_MOSI

A96 TPM_PP

A97 TYPE10# (*)

A98 SER0_TX

A99 SER0_RX

A100 GND (FIXED)

A101 SER1_TX

A102 SER1_RX

A103 LID#

A104 VCC_12V

A105 VCC_12V

A106 VCC_12V

A107 VCC_12V

A108 VCC_12V

A109 VCC_12V

A110 GND (FIXED)

The signals marked with asterisk symbol (*) are not connected on the conga-TS170.

Pin Row B

B92 VGA_BLU

B93 VGA_HSYNC

B94 VGA_VSYNC

B95 VGA_I2C_CK

B96 VGA_I2C_DAT

B97 SPI_CS#

B98 RSVD

B99 RSVD

B100 GND (FIXED)

B101 FAN_PWMOUT

B102 FAN_TACHIN

B103 SLEEP#

B104 VCC_12V

B105 VCC_12V

B106 VCC_12V

B107 VCC_12V

B108 VCC_12V

B109 VCC_12V

B110 GND (FIXED)

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Table 12 Connector C–D Pinout

Pin Row C

C1 GND (FIXED)

C2 GND

C3

C4

C5

C6

USB_SSRX0-

USB_SSRX0+

GND

USB_SSRX1-

C7

C8

USB_SSRX1+

GND

C9 USB_SSRX2-

C10 USB_SSRX2+

C11 GND (FIXED)

C12 USB_SSRX3-

C13 USB_SSRX3+

C14 GND

C15 DDI1_PAIR6+ (*)

C16 DDI1_PAIR6- (*)

C17 RSVD

C18 RSVD

C19 PCIE_RX6+

C20 PCIE_RX6-

C21 GND (FIXED)

C22 PCIE_RX7+

C23 PCIE_RX7-

C24 DDI1_HPD

C25 DDI1_PAIR4+ (*)

C26 DDI1_PAIR4- (*)

C27 RSVD

C28 RSVD

C29 DDI1_PAIR5+ (*)

C30 DDI1_PAIR5- (*)

C31 GND (FIXED)

C32 DDI2_CTRLCLK_AUX+

C33 DDI2_CTRLDATA_AUX-

C34 DDI2_DDC_AUX_SEL

C35 RSVD

C36 DDI3_CTRLCLK_AUX+

C37 DDI3_CTRLDATA_AUX-

C38 DDI3_DDC_AUX_SEL

C39 DDI3_PAIR0+

Pin Row D

D1 GND (FIXED)

D2 GND

Pin Row C

C56 PEG_RX1-

C57 TYPE1#

D3 USB_SSTX0-

D4 USB_SSTX0+

D5 GND

D6 USB_SSTX1-

D7 USB_SSTX1+

D8 GND

D9 USB_SSTX2-

D10 USB_SSTX2+

C58 PEG_RX2+

C59 PEG_RX2-

C60 GND (FIXED)

C61 PEG_RX3+

C62 PEG_RX3-

C63 RSVD

C64 RSVD

C65 PEG_RX4+

D11 GND (FIXED)

D12 USB_SSTX3-

D13 USB_SSTX3+

D14 GND

C66 PEG_RX4-

C67 RSVD

C68 PEG_RX5+

C69 PEG_RX5-

D15 DDI1_CTRLCLK_AUX+ C70 GND (FIXED)

D16 DDI1_CTRLDATA_AUX- C71 PEG_RX6+

D17 RSVD

D18 RSVD

C72

C73

PEG_RX6-

GND

D19 PCIE_TX6+

D20 PCIE_TX6-

D21 GND (FIXED)

C74 PEG_RX7+

C75 PEG_RX7-

C76 GND

D22 PCIE_TX7+

D23 PCIE_TX7-

D24 RSVD

D25 RSVD

D26 DDI1_PAIR0+

D27 DDI1_PAIR0-

D28 RSVD

D29 DDI1_PAIR1+

D30 DDI1_PAIR1-

D31 GND (FIXED)

D32 DDI1_PAIR2+

D33 DDI1_PAIR2-

D34 DDI1_DDC_AUX_SEL

D35 RSVD

D36 DDI1_PAIR3+

D37 DDI1_PAIR3-

C77 RSVD

C78 PEG_RX8+

C79 PEG_RX8-

C80 GND (FIXED)

C81 PEG_RX9+

C82 PEG_RX9-

C83 RSVD

C84 GND

C85 PEG_RX10+

C86 PEG_RX10-

C87

C88

C89

C90

C91

C92

GND

PEG_RX11+

PEG_RX11-

GND (FIXED)

PEG_RX12+

PEG_RX12-

D38 RSVD

D39 DDI2_PAIR0+

C93 GND

C94 PEG_RX13+

Pin Row D

D56 PEG_TX1-

D57 TYPE2#

D58 PEG_TX2+

D59 PEG_TX2-

D60 GND (FIXED)

D61 PEG_TX3+

D62 PEG_TX3-

D63 RSVD

D64 RSVD

D65 PEG_TX4+

D66 PEG_TX4-

D67 GND

D68 PEG_TX5+

D69 PEG_TX5-

D70 GND (FIXED)

D71 PEG_TX6+

D72 PEG_TX6-

D73 GND

D74 PEG_TX7+

D75 PEG_TX7-

D76 GND

D77 RSVD

D78 PEG_TX8+

D79 PEG_TX8-

D80 GND (FIXED)

D81 PEG_TX9+

D82 PEG_TX9-

D83 RSVD

D84 GND

D85 PEG_TX10+

D86 PEG_TX10-

D87 GND

D88 PEG_TX11+

D89 PEG_TX11-

D90 GND (FIXED)

D91 PEG_TX12+

D92 PEG_TX12-

D93 GND

D94 PEG_TX13+

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Pin Row C

C40 DDI3_PAIR0-

C41 GND (FIXED)

C42 DDI3_PAIR1+

C43 DDI3_PAIR1-

C44 DDI3_HPD

C45 RSVD

C46 DDI3_PAIR2+

C47 DDI3_PAIR2-

C48 RSVD

C49 DDI3_PAIR3+

C50 DDI3_PAIR3-

C51 GND (FIXED)

C52 PEG_RX0+

C53 PEG_RX0-

C54 TYPE0#

C55 PEG_RX1+

Note

Pin Row D

D40 DDI2_PAIR0-

D41 GND (FIXED)

D42 DDI2_PAIR1+

D43 DDI2_PAIR1-

D44 DDI2_HPD

D45 RSVD

D46 DDI2_PAIR2+

D47 DDI2_PAIR2-

D48 RSVD

D49 DDI2_PAIR3+

D50 DDI2_PAIR3-

D51 GND (FIXED)

D52 PEG_TX0+

D53 PEG_TX0-

D54 PEG_LANE_RV#

D55 PEG_TX1+

Pin Row C

C95 PEG_RX13-

C96 GND

C97 RVSD

C98 PEG_RX14+

C99 PEG_RX14-

C100 GND (FIXED)

C101 PEG_RX15+

C102 PEG_RX15-

C103 GND

C104 VCC_12V

C105 VCC_12V

C106 VCC_12V

C107 VCC_12V

C108 VCC_12V

C109 VCC_12V

C110 GND (FIXED)

The signals marked with an asterisk symbol (*) are not supported on the conga-TS170.

Pin Row D

D95 PEG_TX13-

D96 GND

D97 RSVD

D98 PEG_TX14+

D99 PEG_TX14-

D100 GND (FIXED)

D101 PEG_TX15+

D102 PEG_TX15-

D103 GND

D104 VCC_12V

D105 VCC_12V

D106 VCC_12V

D107 VCC_12V

D108 VCC_12V

D109 VCC_12V

D110 GND (FIXED)

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Signal

PCIE_RX0+

PCIE_RX0-

PCIE_TX0+

PCIE_TX0-

PCIE_RX1+

PCIE_RX1-

PCIE_TX1+

PCIE_TX1-

PCIE_RX2+

PCIE_RX2-

PCIE_TX2+

PCIE_TX2-

PCIE_RX3+

PCIE_RX3-

PCIE_TX3+

PCIE_TX3-

PCIE_RX4+

PCIE_RX4-

PCIE_TX4+

PCIE_TX4-

PCIE_RX5+

PCIE_RX5-

PCIE_TX5+

PCIE_TX5-

PCIE_RX6+

PCIE_RX6-

PCIE_TX6+

PCIE_TX6-

PCIE_RX7+

PCIE_RX7-

PCIE_TX7+

PCIE_TX7-

PCIE_CLK_REF+

PCIE_CLK_REF-

Table 13 PCI Express Signal Descriptions (General Purpose)

Pin # Description

B68

B69

PCI Express channel 0, Receive Input differential pair

PCI Express channel 0, Transmit Output differential pair

B52

B53

A52

A53

C19

C20

D19

D20

C22

C23

A58

A59

B55

B56

A55

A56

D22

D23

A88

A89

B61

B62

A61

A62

B58

B59

A68

A69

B64

B65

A64

A65











PCI Express channel 6, Receive Input differential pair.

PCI Express channel 6, Transmit Output differential pair.

PCI Express channel 7, Receive Input differential pair.

PCI Express channel 7, Transmit Output differential pair.

PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes

I/O

I PCIE

O PCIE

I PCIE

O PCIE

I PCIE

O PCIE

I PCIE

O PCIE

I PCIE

O PCIE

O PCIE

O PCIE

I PCIE

O PCIE

I PCIE

O PCIE

I PCIE

PU/PD Comment

Supports PCI Express Base Specification, Revision 3.0
















A PCI Express Gen2/3 compliant clock buffer chip must be used on the carrier board if the design involves more than one

PCI Express device.

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Table 14 PCI Express Signal Descriptions (x16 Graphics)

Signal

PEG_RX0+

PEG_RX0-

PEG_RX1+

PEG_RX1-

PEG_RX2+

PEG_RX2-

PEG_RX3+

PEG_RX3-

PEG_RX4+

PEG_RX4-

PEG_RX5+

PEG_RX5-

PEG_RX6+

PEG_RX6-

PEG_RX7+

PEG_RX7-

PEG_RX8+

PEG_RX8-

PEG_RX9+

PEG_RX9-

PEG_RX10+

PEG_RX10-

PEG_RX11+

PEG_RX11-

PEG_RX12+

PEG_RX12-

PEG_RX13+

PEG_RX13-

PEG_RX14+

PEG_RX14-

PEG_RX15+

PEG_RX15-

Pin # Description

C89

C91

C92

C94

C95

C81

C82

C85

C86

C88

C98

C99

C101

C102

C72

C74

C75

C78

C79

C65

C66

C68

C69

C71

C52

C53

C55

C56

C58

C59

C61

C62

PCI Express Graphics Receive Input differential pairs.

Note: Can also be used as PCI Express Receive Input differential pairs 16 through 31 known as PCIE_RX[16-31] + and -.

I/O PU/PD

I PCIE

Comment

53/126

Signal

PEG_TX8-

PEG_TX9+

PEG_TX9-

PEG_TX10+

PEG_TX10-

PEG_TX11+

PEG_TX11-

PEG_TX12+

PEG_TX12-

PEG_TX13+

PEG_TX13-

PEG_TX14+

PEG_TX14-

PEG_TX15+

PEG_TX15-

PEG_TX0+

PEG_TX0-

PEG_TX1+

PEG_TX1-

PEG_TX2+

PEG_TX2-

PEG_TX3+

PEG_TX3-

PEG_TX4+

PEG_TX4-

PEG_TX5+

PEG_TX5-

PEG_TX6+

PEG_TX6-

PEG_TX7+

PEG_TX7-

PEG_TX8+

Pin # Description

D88

D89

D91

D92

D94

D79

D81

D82

D85

D86

D95

D98

D99

D101

D102

D71

D72

D74

D75

D78

D62

D65

D66

D68

D69

D52

D53

D55

D56

D58

D59

D61

PCI Express Graphics Transmit Output differential pairs.

Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31 known as PCIE_TX[16-31] + and -.

PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane order.

Note

I/O PU/PD

O PCIE

I

Comment

PU 10k 3.3V PEG_LAN_RV# is a boot strap signal (see note below)

Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”.

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Table 15 DDI Signal Description

Signal

DDI1_PAIR0+

DDI1_PAIR0-

Pin # Description

D26

D27

Multiplexed with DP1_LANE0+ and TMDS1_DATA2+.

Multiplexed with DP1_LANE0- and TMDS1_DATA2-.

DDI1_PAIR1+

DDI1_PAIR1-

DDI1_PAIR2+

DDI1_PAIR2-

DDI1_PAIR3+

DDI1_PAIR3-

DDI1_PAIR4+

DDI1_PAIR4-

DDI1_PAIR5+

DDI1_PAIR5-

DDI1_PAIR6+

DDI1_PAIR6-

D29

D30

D32

D33

D36

D37

C25

C26

C29

C30

C15

C16





Multiplexed with DP1_LANE3+ and TMDS1_CLK+.

Multiplexed with DP1_LANE3- and TMDS1_CLK-.

Multiplexed with SDVO1_INT+.

Multiplexed with SDVO1_INT-.

Multiplexed with SDVO1_TVCLKIN+.

Multiplexed with SDVO1_TVCLKIN-.

Multiplexed with SDVO1_FLDSTALL+.

Multiplexed with SDVO1_FLDSTALL-.

DDI1_HPD C24 Multiplexed with DP1_HPD and HDMI1_HPD.

DDI1_CTRLCLK_AUX+ D15 Multiplexed with DP1_AUX+ and HMDI1_CTRLCLK.

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high

DDI1_CTRLDATA_AUXD16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.

DP AUX- function if DDI1_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high

DDI1_DDC_AUX_SEL

DDI2_PAIR0+

DDI2_PAIR0-

DDI2_PAIR1+

DDI2_PAIR1-

D34 Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-.

This pin shall have a 1M pull-down to logic ground on the module. If this input is floating, the AUX pair is used for the DP AUX+/- signals. If pulledhigh, the AUX pair contains the CTRLCLK and CTRLDATA signals.

D39

D40

D42

D43





DDI2_PAIR2+

DDI2_PAIR2-

DDI2_PAIR3+

DDI2_PAIR3-

DDI2_HPD

D46

D47

D49

D50





D44 Multiplexed with DP2_HPD and HDMI2_HPD.

DDI2_CTRLCLK_AUX+ C32 Multiplexed with DP2_AUX+ and HDMI2_CTRLCLK.



I/O

O PCIE

O PCIE

O PCIE

O PCIE

PU/PD Comment

Not supported

Not supported

Not supported

I 3.3V

I/O PCIE

I/O OD 3.3V

PD 1M

PD100k

I/O PCIE

I/O OD 3.3V

I 3.3V

PU 100k 3.3V DDI1_CTRLDATA_AUX- is a boot strap signal (see note below).

DDI enable strap already populated.

PD 1M

O PCIE

O PCIE

O PCIE

O PCIE

I 3.3V

I/O PCIE

I/O OD 3.3V

PD 1M

PD 100k

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Signal Pin # Description

DDI2_CTRLDATA_AUXC33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.


HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high.

DDI2_DDC_AUX_SEL

DDI3_PAIR0+

DDI3_PAIR0-

DDI3_PAIR1+

DDI3_PAIR1-

C34 Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-.

This pin shall have a IM pull-down to logic ground on the module. If this input is floating, the AUX pair is used for the DP AUX+/- signals. If pulledhigh, the AUX pair contains the CTRLCLK and CTRLDATA signals

C39

C40

C42

C43





DDI3_PAIR2+

DDI3_PAIR2-

DDI3_PAIR3+

DDI3_PAIR3-

DDI3_HPD

C46

C47

C49

C50





C44 Multiplexed with DP3_HPD and HDMI3_HPD.

DDI3_CTRLCLK_AUX+ C36 Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK.



DDI3_CTRLDATA_AUXC37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.


HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high.

DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-.

This pin shall have a IM pull-down to logic ground on the module. If this input is floating, the AUX pair is used for the DP AUX+/- signals. If pulledhigh, the AUX pair contains the CTRLCLK and CTRLDATA signals

Note

I/O

I/O PCIE

I/O OD 3.3V

PU/PD Comment

PU 100k 3.3V DDI2_CTRLDATA_AUX- is a boot strap signal (see note below).

DDI enable strap already populated.

I 3.3V

O PCIE

O PCIE

O PCIE

O PCIE

I 3.3V

PD 1M

PD 100k

I/O PCIE

I/O OD 3.3V

I/O PCIE

I/O OD 3.3V

I 3.3V

PU 100k 3.3V

1. Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”.

2. The Digital Display Interface (DDI) signals are multiplexed with TMDS and DisplayPort (DP). The signals for these interfaces are routed to the DDI interface of the COM Express connector.

56/126

Table 16 TMDS Signal Descriptions

Signal

TMDS1_CLK +

TMDS1_CLK -

TMDS1_DATA0+

TMDS1_DATA0-

TMDS1_DATA1+

TMDS1_DATA1-

TMDS1_DATA2+

TMDS1_DATA2-

HDMI1_HPD

HDMI1_CTRLCLK

HDMI1_CTRLDATA D16

TMDS2_CLK +

TMDS2_CLK -

TMDS2_DATA0+

TMDS2_DATA0-

TMDS2_DATA1+

TMDS2_DATA1-

TMDS2_DATA2+

TMDS2_DATA2-

HDMI2_HPD

HDMI2_CTRLCLK

TMDS3_CLK +

TMDS3_CLK -

TMDS3_DATA0+

TMDS3_DATA0-

TMDS3_DATA1+

TMDS3_DATA1-

TMDS3_DATA2+

TMDS3_DATA2-

HDMI3_HPD

C49

C50

C46

C47

C42

C43

C39

C40

C44

D49

D50

D46

D47

D42

D43

D39

D40

D44

HDM12_CTRLDATA C33

HDMI3_CTRLCLK

Pin # Description

D36

D37

TMDS Clock output differential pair.

Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.

D32

D33

D29

D30

D26

D27

C24

D15

C32

C36

TMDS differential pair.



Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-..



TMDS Hot-plug detect.

Multiplexed with DDI1_HPD.

TMDS I 2 C Control Clock

Multiplexed with DDI1_CTRLCLK_AUX+

TMDS I 2 C Control Data

Multiplexed with DDI1_CTRLDATA_AUX-

TMDS Clock output differential pair..









Multiplexed with DDI2_HPD



TMDS I 2 C Control Data


TMDS Clock output differential pair..












I/O

O PCIE

PU/PD Comment

O PCIE

O PCIE

O PCIE

I PCIE PD 1M

I/O OD 3.3V PD 100k

I/O OD 3.3V PU 100k

3.3V

O PCIE

Boot strap signal (see note below).

Enable strap is already populated

O PCIE

O PCIE

O PCIE

I PCIE PD 1M

I/O OD 3.3V PD 100k

I/O OD 3.3V PU 100k

3.3V

O PCIE


Enable strap is already populated.

O PCIE

O PCIE

O PCIE

I PCIE PD 1M

I/O OD 3.3V PD 100K

57/126


HDMI3_CTRLDATA C37 TMDS I 2 C Control Data


Note

I/O PU/PD Comment

I/O OD 3.3V PU 100k

3.3V


Enable strap is already populated .

1. Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”.

2. The conga-TS170 does not natively support TMDS. A DP++ to TMDS converter (e.g PTN3360D) needs to be implemented.

Signal

DP1_LANE3+

DP1_LANE3-

DP1_LANE2+

DP1_LANE2-

DP1_LANE1+

DP1_LANE1-

DP1_LANE0+

DP1_LANE0-

DP1_HPD

DP1_AUX+

DP1_AUX-

DP2_LANE3+

DP2_LANE3-

DP2_LANE2+

DP2_LANE2-

DP2_LANE1+

DP2_LANE1-

Table 17 DisplayPort (DP) Signal Descriptions

Pin # Description

D36

D37

Uni-directional main link for the transport of isochronous streams and secondary data.


D32

D33



D29

D30

D26

D27





C24 Detection of Hot Plug / Unplug and notification of the link layer.


D15 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.

D16 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.

D49

D50


Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-

D46

D47

D42

D43





I/O

O PCIE

PU/PD Comment

O PCIE

O PCIE

O PCIE

I 3.3V

PD 1M

I/O PCIE PD 100k

I/O PCIE PU 100k

3.3V

O PCIE

DP1_AUX- is a boot strap signal (see note below).

DP enable strap is already populated.

O PCIE

O PCIE

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Signal

DP2_LANE0+

DP2_LANE0-

DP2_HPD

DP2_AUX+

DP2_AUX-

DP3_LANE3+

DP3_LANE3-

DP3_LANE2+

DP3_LANE2-

DP3_LANE1+

DP3_LANE1-

DP3_LANE0+

DP3_LANE0-

DP3_HPD

DP3_AUX+

DP3_AUX-

Pin # Description

D39

D40



D44 Detection of Hot Plug / Unplug and notification of the link layer.


C32 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.


C49

C50



C46

C47

C42

C43





C39

C40



C44 Detection of Hot Plug / Unplug and notification of the link layer.




I/O

O PCIE

PU/PD Comment

I 3.3V

PD 1M

I/O PCIE PD 100k

I/O PCIE PU 100k

3.3V

O PCIE


DP enable strap already populated.

O PCIE

O PCIE

O PCIE

I 3.3V

PD 1M

I/O PCIE PD 100k

I/O PCIE PU 100k

3.3V


DP enable strap already populated

Note


59/126

Table 18 Embedded DisplayPort Signal Descriptions

Signal eDP_TX3+ eDP_TX3eDP_TX2+ eDP_TX2eDP_TX1+ eDP_TX1eDP_TX0+ eDP_TX0eDP_AUXeDP_HPD

Pin # Description

A81

A82

A71

A72

A73

A74

A75

A76 eDP differential pairs.

eDP_VDD_EN eDP_BKLT_EN

A77

B79 eDP_BKLT_CTRL B83 eDP_AUX+ A83

A84

A87

I/O

AC coupled off module.

eDP power enable.

eDP backlight enable.

eDP backlight brightness control.

eDP AUX+.

O 3.3V

O 3.3V

O 3.3V


eDP AUX-.


Detection of Hot Plug / Unplug and notification of the link layer. I 3.3V

PU/PD Comment

PD 10k

PD 10k

Table 19 VGA Signal Descriptions

Signal

VGA_RED

Pin # Description I/O PU/PD

B89 Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load. O Analog PD 150R

Comment

Optional

VGA_GRN B91 Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.

VGA_BLU B92

VGA_HSYNC B93

VGA_VSYNC B94

VGA_I2C_CK B95

VGA_I2C_DAT B96

Horizontal sync output to VGA monitor

Vertical sync output to VGA monitor

DDC clock line (I²C port dedicated to identify VGA monitor capabilities)

DDC data line.

O Analog

Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load. O Analog

O 3.3V

O 3.3V

PD 150R

PD 150R

I/O OD 5V PU 1k2 3.3V

I/O OD 5V PU 1k2 3.3V

Optional

Optional

Optional

Optional

Optional

Optional

60/126

Table 20 LVDS Signal Descriptions

Signal

LVDS_A0+

LVDS_A0-

LVDS_A1+

LVDS_A1-

LVDS_A2+

LVDS_A2-

LVDS_A3+

LVDS_A3-

LVDS_A_CK+

LVDS_A_CK-

LVDS_B0+

LVDS_B0-

LVDS_B1+

LVDS_B1-

LVDS_B2+

LVDS_B2-

LVDS_B3+

LVDS_B3-

LVDS_B_CK+

LVDS_B_CK-

LVDS_VDD_EN

LVDS_BKLT_EN

A81

A82

B71

B72

B73

B74

B75

B76

B77

B78

B81

B82

A77

B79

LVDS_BKLT_CTRL B83

LVDS_I2C_CK A83

LVDS_I2C_DAT A84

Pin # Description

A71

A72

A73

A74

A75

A76

A78

A79

LVDS Channel A differential pairs

LVDS Channel A differential clock

LVDS Channel B differential pairs

LVDS Channel B differential clock

I/O

O LVDS

O LVDS

O LVDS

O LVDS

PU/PD

LVDS panel power enable

LVDS panel backlight enable

O 3.3V

PD 10k

O 3.3V

PD 10k

LVDS panel backlight brightness control O 3.3V

DDC lines used for flat panel detection and control.

O 3.3V

PU 2k2 3.3V for LVDS support (default)

DDC lines used for flat panel detection and control.

I/O 3.3V PU 2k2 3.3V for LVDS support (default)

Comment

Table 21 Serial ATA Signal Descriptions

Signal

SATA0_RX+

SATA0_RX-

SATA0_TX+

SATA0_TX-

SATA1_RX+

SATA1_RX-

SATA1_TX+

SATA1_TX-

SATA2_RX+

SATA2_RX-

Pin # Description

A19

A20

Serial ATA channel 0, Receive Input differential pair.

Serial ATA channel 0, Transmit Output differential pair.

A16

A17

B19

B20


B16

B17

A25

A26



I/O

I SATA

O SATA

I SATA

O SATA

I SATA

PU/PD Comment

Supports Serial ATA specification, Revision 3.0





61/126

Signal

SATA2_TX+

SATA2_TX-

Pin # Description

A22

A23


I/O

O SATA

SATA3_RX+

SATA3_RX-

B25

B26


I SATA

SATA3_TX+

SATA3_TX-

B22

B23


O SATA

(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low.

I/O 3.3v

PU/PD Comment




Table 22 USB 2.0 Signal Descriptions

Signal

USB0+

Pin # Description

A46 USB Port 0, data + or D+

USB0-

USB1+

USB1-

USB2+

USB2-

USB3+

USB3-

A45 USB Port 0, data - or D-

B46 USB Port 1, data + or D+

B45 USB Port 1, data - or D-





USB4+

USB4-

USB5+

USB5-





USB6+

USB6-

USB7+




USB7B36 USB Port 7, data - or D-

USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .

USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

I/O

I/O

PU/PD Comment

USB 2.0 compliant. Backwards compatible to USB 1.1

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I 3.3VSB PU 10k

3.3VSB
















Do not pull this line high on the carrier board.

I 3.3VSB PU 10k

3.3VSB

I 3.3VSB PU 10k

3.3VSB

I 3.3VSB PU 10k

3.3VSB




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Table 23 USB 3.0 Signal Descriptions

Signal

USB_SSRX0+

USB_SSRX0-

USB_SSTX0+

USB_SSTX0-

USB_SSRX1+

USB_SSRX1-

USB_SSTX1+

USB_SSTX1-

USB_SSRX2+

USB_SSRX2-

USB_SSTX2+

USB_SSTX2-

USB_SSRX3+

USB_SSRX3-

USB_SSTX3+

USB_SSTX3-

Pin # Description

C4 Additional receive signal differential pairs for the Superspeed USB data path I

I/O

C3 I

D4

D3

C7

C6

Additional transmit signal differential pairs for the Superspeed USB data path O

O

Additional receive signal differential pairs for the Superspeed USB data path I

I

D7

D6

Additional transmit signal differential pairs for the Superspeed USB data path O

O


C9 I

D10 Additional transmit signal differential pairs for the Superspeed USB data path O

D9 O


C12 I

D13 Additional transmit signal differential pairs for the Superspeed USB data path O

D12 O

PU/PD Comment

Table 24 Gigabit Ethernet Signal Descriptions

Gigabit

Ethernet

GBE0_MDI0+

GBE0_MDI0-

GBE0_MDI1+

GBE0_MDI1-

GBE0_MDI2+

GBE0_MDI2-

GBE0_MDI3+

GBE0_MDI3-

Pin # Description

A13

A12

A10

A9

A7

A6

A3

A2

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:

MDI[0]+/-

MDI[1]+/-

1000

B1_DA+/-

B1_DB+/-

100

TX+/-

RX+/-

10

TX+/-

RX+/-

MDI[2]+/-

MDI[3]+/-

B1_DC+/-

B1_DD+/-

GBE0_ACT#

GBE0_LINK#

GBE0_LINK100# A4

GBE0_LINK1000# A5

GBE0_CTREF

B2

A8

Gigabit Ethernet Controller 0 activity indicator, active low.

Gigabit Ethernet Controller 0 link indicator, active low.

Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.

Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.

A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the module. In the case in which the reference is shorted to ground, the current shall be limited to 250mA or less.

I/O

I/O

Analog

O 3.3VSB

O 3.3VSB

O 3.3VSB

O 3.3VSB

PU/PD Comment

Twisted pair signals for external transformer.

Not connected

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Note

1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation of Ethernet Phy since it only has 3 LED outputs—ACT#, LINK100# and LINK1000#.

2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS170 module.

Table 25 Intel ® High Definition Audio Link Signals Descriptions

Signal

AC/HDA_RST#

AC/HDA_SYNC

Pin # Description

A30 Intel ® High Definition Audio Reset: This signal is the master hardware reset to external codec(s).

A29 Intel ® High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync to the codec(s). It is also used to encode the stream number.

AC/HDA_BITCLK

AC/HDA_SDOUT

A32

A33

Intel ® High Definition Audio Bit Clock Output: This signal is a 24.000MHz serial data clock generated by the Intel ® High Definition Audio controller.

Intel ® High Definition Audio Serial Data Out: This signal is the serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48

Mb/s for Intel ® High Definition Audio.

AC/HDA_SDIN[1:0] B29-B30 Intel ® High Definition Audio Serial Data In [0]: These signals are serial TDM data inputs from the three codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel ® High Definition Audio.

I/O

O 3.3VSB

O 3.3VSB

O 3.3VSB

O 3.3VSB

I 3.3VSB

Note

PU/PD Comment

AC’97 codecs are not supported.




AC/HDA_SDOUT is a boot strap signal

(see note below)

Pin B28 (HDA_SDIN2) is not connected.


Table 26 ExpressCard Support Pins Signal Descriptions

Signal

EXCD0_CPPE#

EXCD1_CPPE#

EXCD0_PERST#

EXCD1_PERST#

Pin # Description

A49

B48

ExpressCard capable card request.

A48

B47

ExpressCard Reset

I/O

I 3.3V

O 3.3V

PU/PD

PU 10k 3.3VSB

PU 10k 3.3V

Comment

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Table 27 LPC Signal Descriptions

Signal

LPC_AD[0:3]

LPC_FRAME#

LPC_DRQ[0:1]#

LPC_SERIRQ

LPC_CLK

Pin # Description

B4-B7 LPC multiplexed address, command and data bus

B3 LPC frame indicates the start of an LPC cycle

B8-B9 LPC serial DMA request

A50 LPC serial interrupt

B10 LPC clock output - 24 MHz nominal

I/O

I/O 3.3V

O 3.3V

PU/PD Comment

I 3.3V

PU 10k 3.3V

Not supported

I/O OD 3.3V PU 10k 3.3V

O 3.3V

Table 28 SPI BIOS Flash Interface Signal Descriptions

Signal

SPI_CS#

Pin # Description

B97 Chip select for Carrier Board SPI BIOS Flash.

SPI_MISO

SPI_MOSI

SPI_CLK

A92

A95

A94

SPI_POWER A91

BIOS_DIS0# A34

BIOS_DIS1# B88

I/O

O 3.3VSB

PU/PD

Data in to module from carrier board SPI BIOS flash.

Data out from module to carrier board SPI BIOS flash.

Clock from module to carrier board SPI BIOS flash.

Power source for carrier board SPI BIOS flash. SPI_POWER shall be used to power SPI BIOS flash on the carrier only.

Selection strap to determine the BIOS boot device.

Selection strap to determine the BIOS boot device.

I 3.3VSB

O 3.3VSB

O 3.3VSB

3.3VSB

I 3.3VSB

PU 10K

3.3VSB

I 3.3VSB

PU 10K

3.3VSB

Comment

Carrier shall pull to SPI_POWER when external SPI is provided but not used.

Carrier shall be left as no-connect.

Carrier shall be left as no-connect

Table 29 Miscellaneous Signal Descriptions

Signal

I2C_CK

I2C_DAT

SPKR

Pin # Description

B33 General purpose I²C port clock output/input

B34 General purpose I²C port data I/O line

B32 Output for audio enunciator, the “speaker” in PC-AT systems

I/O PU/PD

I/O 3.3V PU 2K2 3.3VSB

I/O 3.3V PU 2K2 3.3VSB

O 3.3V

Comment

SPEAKER is a boot strap signal (see note below)

WDT B27 Output indicating that a watchdog time-out event has occurred.

FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.

FAN_TACHIN B102 Fan tachometer input.

TPM_PP A96 Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip has an internal pull-down. This signal is used to indicate Physical Presence to the TPM.

O 3.3V

PD 10K

O OD

3.3V

I OD

I 3.3V

PU 10K 3.3V

Requires a fan with a two pulse output.

Trusted Platform Module chip is optional.

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Note


Table 30 General Purpose I/O Signal Descriptions


GPO0 A93 General purpose output pins.

GPO1

GPO2

GPO3

GPI0

GPI1

GPI2

GPI3

B54

B57

B63

A54

A63

A67

A85

I/O

O 3.3V

General purpose output pins.

General purpose output pins.

O 3.3V

O 3.3V

General purpose output pins. O 3.3V

General purpose input pins. Pulled high internally on the module. I 3.3V




Note

The conga-TS170 does not support SD card on these pins.

PU/PD

PU 10K 3.3V

PU 10K 3.3V

PU 10K 3.3V

PU 10K 3.3V

Comment

Table 31 Power and System Management Signal Descriptions

Signal

PWRBTN#

Pin # Description

B12 Power button to bring system out of S5 (soft off), active on falling edge.

Note: For proper detection, assert a pulse width of at least 16 ms.

SYS_RESET# B49 Reset button input. Active low input. Edge triggered.

System will not be held in hardware reset while this input is kept low.


CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.

PWR_OK B24 Power OK from main power supply. A high value indicates that the power is good.

I/O

I 3.3VSB

I 3.3VSB

O 3.3V

I 3.3V

SUS_STAT#

SUS_S3#

B18 Indicates imminent suspend operation; used to notify LPC devices.

A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.

O 3.3VSB

O 3.3VSB

PU/PD

PU 10k 3.3VSB

PU 10k 3.3VSB

PD 100k

Comment

Set by resistor divider to accept 3.3V.

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Signal

SUS_S4#

SMB_DAT#

Pin # Description

A18 Indicates system is in Suspend to Disk state. Active low output.

SUS_S5#

WAKE0#

WAKE1#

BATLOW#

A24 Indicates system is in Soft Off state.

B66 PCI Express wake up signal.

B67 General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.

A27 Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.

THRM# B35 Input from off-module temp sensor indicating an over-temp situation.

THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown.

SMB_CK B13 System Management Bus bidirectional clock line.

B14 System Management Bus bidirectional data line.

I/O

O 3.3VSB

O 3.3VSB

I 3.3VSB

I 3.3VSB

I 3.3VSB

PU/PD

PU 1k 3.3VSB

PU 10k 3.3VSB

PU 8k2 3.3VSB

I 3.3V

PU 10k 3.3V

O 3.3V

PU 10k 3.3V

I/O 3.3VSB PU 2k2 3.3VSB

I/O OD

3.3VSB

I 3.3VSB

PU 2k2 3.3VSB

PU 2k2 3.3VSB

SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System

Management Interrupt) or to wake the system.

LID# A103 Lid button. Used by the ACPI operating system for a LID switch.


SLEEP# B103 Sleep button. Used by the ACPI operating system to bring the system to sleep state or to wake it up again.


I OD 3.3V

PU 10k 3.3VSB

I OD 3.3V

PU 10k 3.3VSB

Comment

Not supported

Table 32 General Purpose Serial Interface Signal Descriptions

Signal

SER0_TX

SER1_TX

SER0_RX

SER1_RX

Pin #

A98

A101

A99

A102

Description

General purpose serial port transmitter

General purpose serial port transmitter

General purpose serial port receiver

General purpose serial port receiver

I/O

O 3.3V

O 3.3V

I 3.3V

I 3.3V

PU/PD

PU 47k 3.3V

PU 47k 3.3V

Comment

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Table 33 Module Type Definition Signal Description


TYPE0#

TYPE1#

TYPE2#

C54

C57

D57

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X).

TYPE2# TYPE1# TYPE0#

X

NC

NC

NC

NC

GND

X

NC

NC

GND

GND

NC

X

NC

GND

NC

GND

NC

Pinout Type 1

Pinout Type 2

Pinout Type 3 (no IDE)

Pinout Type 4 (no PCI)

Pinout Type 5 (no IDE, no PCI)

Pinout Type 6 (no IDE, no PCI)

TYPE10# A97

The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off

(e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The

Carrier Board logic may also implement a fault indicator such as an LED.

Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev. 1.0/2.0 module is installed.

TYPE10#

NC

PD

12V

Pinout R2.0

Pinout Type 10 pull down to ground with 4.7k resistor

Pinout R1.0

This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin is defined as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0 module Types 1-6 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7k resistor.

I/O Comment

PDS TYPE[0:2]# signals are available on all modules following the Type 2-6

Pinout standard.

The conga-TS170 is based on the COM Express Type

6 pinout therefore the pins

0 and 1 are not connected and pin 2 is connected to

GND.

PDS Not connected to indicate

“Pinout R2.0”.

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Table 34 Power and GND Signal Descriptions

Signal

VCC_12V

Pin #

A104-A109

B104-B109

C104-C109

D104-D109

VCC_5V_SBY B84-B87

VCC_RTC

GND

Description

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

A47

A1, A11, A21, A31, A41,

A51, A57, A60, A66,

A70, A80, A90, A100,

A110, B1, B11, B21, B31,

B41, B51, B60, B70, B80,

B90, B100, B110

C1, C2, C5, C8, C11,

C14, C21, C31, C41,

C51, C60, C70,C73, C76,

C80, C84, C87, C90,

C93, C96, C100, C103,

C110, D1, D2, D5, D8,

D11, D14, D21, D31,

D41, D51, D60, D67,

D70, D73, D76, D80,

D84, D87, D90, D93,

D96, D100, D103, D110

Standby power input: +5.0V nominal. If VCC5_SBY is used, all available

VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.

Real-time clock circuit-power input. Nominally +3.0V.

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to Carrier Board GND plane.

I/O

P

P

P

P

PU/PD Comment

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9.2 Boot Strap Signals

Table 35 Boot Strap Signal Descriptions

Signal

AC/HDA_SDOUT

SPKR

PEG_LAN_RV#

Pin # Description of Boot Strap Signal

A33 High Definition Audio Serial Data Out: This signal is the serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for High Definition Audio.

B32 Output for audio enunciator, the “speaker” in PC-AT systems

D54 PCI Express Graphics lane reversal input strap. Pull low on the carier board to reverse lane order.

DDI1_CTRLDATA_AUX- D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA

DP1_AUX-

HDM1_CTRLDATA

DP AUX- function if DDI1_DDC_AUX_SEL is no connect

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high

DDI2_CTRLDATA_AUX- C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.

DP2_AUXDP AUX- function if DDI2_DDC_AUX_SEL is no connect

HDM2_CTRLDATA HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high

I/O

O 3.3VSB

O 3.3V

13.3V

I/O PCIE

I/O OD 3.3 V

I/O PCIE

I/O OD 3.3 V

Caution

PU/PD Comment

PU 1k

3.3VSB

Bootstrap signals

PU 10k

3.3V

PU 100 k

3.3 V

PU 100 k

3.3 V

1. The signals listed in the table above are used as chipset configuration straps during system reset. In this condition (during reset), they are inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented resistors located on the module.

2. No external DC loads or external pull-up or pull-down resistors should change the configuration of the signals listed in the above table.

External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/or cause irreparable damage to the module.

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10 System Resources

10.1 I/O Address Assignment

The I/O address assignment of the conga-TS170 module is functionally identical with a standard PC/AT.

Note

The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not consume

I/O resources in that area.

10.1.1 LPC Bus

On the conga-TS170 the PCIExpress Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus. Only specified I/O ranges are forwarded to the LPC Bus. In the congatec Embedded BIOS the following I/O address ranges are sent to the LPC Bus:

2Eh – 2Fh

4Eh – 4Fh

60h, 64h

A00h – A1Fh

E00h - EFFh (always used internally)

Parts of these ranges are not available if a Super I/O is used on the carrier board. If a Super I/O is not implemented on the carrier board then these ranges are available for customer use. If you require additional LPC Bus resources other than those mentioned above, or more information about this subject, contact congatec technical support for assistance.

71/126

10.2 PCI Configuration Space Map

Table 36 PCI Configuration Space Map

Bus Number (hex) Device Number (hex)

00h 00h

00h

00h

00h

00h

01h

01h

01h

02h

00h

00h

00h

00h ( Note1)

00h ( Note1)

00h ( Note1)

00h ( Note1)

00h ( Note1)

00h

00h

00h (Note2)

00h (Note2)

00h (Note2)

00h (Note2)

00h (Note2)

00h (Note2)

00h (Note2)

00h (Note2)

00h

00h

00h

00h

00h

01h (Note3)

02h (Note3)

1Dh

1Dh

1Dh

1Dh

1Fh

1Ch

1Ch

1Ch

1Ch

1Ch

16h

16h

16h

16h

17h

08h

14h

14h

16h

1Fh

1Fh

1Fh

1Fh

00h

00h

00h

01h

02h

03h

00h

00h

04h

05h

06h

07h

01h

02h

03h

04h

00h

00h

00h

02h

00h

02h

03h

04h

06h

00h

00h

Function Number (hex) Description

00h HOST and DRAM Controller

00h

01h

02h

00h

PCI Express Graphic Root Port 0



Integrated Graphics Device

Gaussian Mixture Model Device

USB 3.0 xHCI Controller

Thermal Subsystem

Management Engine (ME) Interface 1

Intel ME Interface 2

ME IDE Redirection (IDE-R) Interface

ME Keyboard and Text (KT) Redirection

Intel ME Interface 3

SATA Controller

Not connected (PCI Express Root Port)

PCI Express Root Port 0








PCI to LPC Bridge

Power Management Controller

Intel ® High Definition Audio (Intel® HD Audio)

SMBus Controller

GbE Controller

PEG Port 0

PEG Port 1

72/126

03h (Note3)

04h (Note3)

05h (Note3)

06h (Note3)

07h (Note3)

08h (Note3)

09h (Note3)

0Ah (Note3)

0Bh (Note3)

Note

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

PEG Port 2

PCI Express Port 0

PCI Express Port 1

PCI Express Port 2

PCI Express Port 3

PCI Express Port 4

PCI Express Port 5

PCI Express Port 6

PCI Express Port 7

1. In the standard configuration, the Intel Management Engine (ME) related devices are partly present or not present at all.

2. The PCI Express Ports are visible only if a device is attached to the PCI Express Slot on the carrier board.

3. The table represents a case when a single function PCI/PCIe device is connected to all possible slots on the carrier board. The given bus numbers will change based on actual hardware configuration.

4. Internal PCI devices not connected to the conga-TS170 are not listed.

10.3 I

2

C

There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.

10.4 SM Bus

System Management (SM) bus signals are connected to the Intel® QM170 or HM170 PCH. The SM bus is not intended to be used by off-board non-system management devices. For more information about this subject contact congatec technical support.

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11 BIOS Setup Description

The following section describes the BIOS setup program. The BIOS setup program can be used to view and change the BIOS settings for the module. Only experienced users should change the default BIOS settings.

11.1 Entering the BIOS Setup Program

The BIOS setup program can be accessed by pressing the <DEL> or <F2> key during POST.

11.1.1 Boot Selection Popup

The BIOS offers the possibility to access a Boot Selection Popup menu by pressing the <F11> key during POST. If this option is used, a selection will be displayed immediately after POST allowing the operator to select either the boot device that should be used or an option to enter the BIOS setup program.

11.2 Setup Menu and Navigation

The congatec BIOS setup screen is composed of the menu bar and two main frames. The menu bar is shown below:

Main Advanced Chipset Security Boot Save & Exit

The left frame displays all the options that can be configured in the selected menu. Grayed-out options cannot be configured. Only the blue options can be configured. When an option is selected, it is highlighted in white.

The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options and the possible impacts when changing the selected option in the left frame.

Note

Entries in the option column that are displayed in bold print indicate BIOS default values.

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The setup program uses a key-based navigation system. Most of the keys can be used at any time while in setup. The table below explains the supported keys:

Key

← → Left/Right

↑ ↓ Up/Down

+ - Plus/Minus

Tab

F1

F2

F9

F10

ESC

ENTER

Description

Select a setup menu (e.g. Main, Boot, Exit)

Select a setup item or sub menu

Change the field value of a particular setup item

Select setup fields (e.g. in date and time)

Display General Help screen

Load previous settings

Load optimal default settings

Save changes and exit setup

Discard changes and exit setup

Display options of a particular setup item or enter submenu

11.3 Main Setup Screen

When you first enter the BIOS setup, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. The ‘Main’ screen reports BIOS, processor, memory and board information and is used to configure the system date and time.

Feature

BIOS Information

Main BIOS Version

OEM BIOS Version

Build Date

Board Information

Product Revision

Serial Number

BC Firmware Revision

MAC Address (1st Ethernet)

Boot Counter

Running Time

► Platform Information

System Time

Options

No option

No option

No option

No option

No option

No option

No option

No option

No option

Submenu

Hour:Minute:Second

Description

Displays the main BIOS version

Displays the additional OEM BIOS version (blank by default)

Displays the date the BIOS was built

Displays the hardware revision of the board

Displays the serial number of the board

Displays the congatec board controller firmware revision

Displays the MAC address of the onboard i218 Ethernet controller

Displays the number of boot-ups (maximum 16777215)

Displays the time the board is running (in hours, maximum 65535)

Opens the ‘Platform Information’ submenu

Displays the current system time. Note: The time is in 24-hour format

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Feature

System Date

System Time

Options

Day of week, month/day/year

Hour:Minute:Second

Description

Displays the current system date. Note: The date is in month-day-year format

Displays the current system time. Note: The time is in 24-hour format

11.3.1 Platform Information Submenu

The platform information submenu offers additional hardware and software information.

Feature

Processor Information

Processor Type

Codename

Processor Speed

Processor Signature

Stepping

Processor Cores

Microcode Revision

IGD HW Version

IGD VBIOS Version

Total Memory

PCH Information

Codename

PCH SKU

Stepping

ME FW Version

ME Firmware SKU

Options

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

Description

Displays the processor ID string. The “Processor Type” text is not displayed

Displays the processor codename

Displays the processor speed

Displays the processor signature

Displays the processor stepping

Displays the number of processor cores

Displays the processor microcode revision

Displays the version of the graphics controller

Displays the video BIOS version

Displays the total amount of installed memory

Displays the codename of the Platform Controller Hub (PCH)

Displays the SKU name of the PCH

Displays the PCH stepping

Displays the ME Firmware (FW) Version if available

Displays the ME FW SKU if available

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11.4 Advanced Setup

Select the Advanced tab from the setup menu to enter the Advanced BIOS Setup screen. The menu is used for setting advanced features. Only enabled features are displayed.

Main Advanced

Graphics

Watchdog

Module Serial Ports

Hardware Health Monitoring

Intel ® Ethernet Connection (H) I219-LM

Driver Health

Trusted Computing

RTC Wake Settings

LPC Generic I/O Range Decode

GPI IRQ Configuration

ACPI

Intel ® ICC

PCH-FW Configuration

SMART Settings

Super IO

Serial Port Console Redirection

CPU

SATA Configuration

Acoustic Management

PCI Configuration

PCI Express Configuration

PEG Port Configuration

UEFI Network Stack

CSM & Option ROM Control

NVMe Configuration

USB

Diagnostic Settings

GPIO Configuration

Board Controller Command Control

Chipset Boot Security Save & Exit

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Main Advanced

PC Speaker

Chipset Boot Security Save & Exit

Note

1. The Intel Ethernet Connection (H) I219-LM and Driver Health submenus are not displayed if the UEFI Network Stack is set to “disabled”.

2. The PCH-FW submenu is not displayed if the feature is disabled.

11.4.1 Graphics Submenu

Feature

Primary Display

Options

Auto

IGD

PEG

PCI/PCIe

Primary PEG

Primary PCIE

Internal Graphics Device

Auto

PEG1

PEG2

Auto

PCIE1

PCIE2

PCIE3

PCIE4

PCIE5

PCIE6

PCIE7

Auto

Disabled

Enabled

Primary IGD Boot Display Device Auto

CRT

LFP

EFP

EFP2

EFP3

Description

Select primary graphics adapter to be used during boot up:

‘Auto’ - The system selects the primary graphics adapter automatically

‘IGD’ - Uses the Internal Graphics Device (IGD) located in the chipset

‘PEG’ - Uses the external PCI Express Graphics (PEG) card attached to the PEG port

‘PCI/PCIe’ - Uses a PCI/PCIe graphics card attached to a PCI/PCIe port

Select which graphics device should be Primary PEG

‘Auto’ selects PEG 0 as primary PEG

Select which graphics device should be Primary PCIE

‘Auto’ selects PCIE 0 as primary PCIE

Set IGD to ‘Auto’, ‘Disabled’, or ‘Enabled’

Select the Primary IGD display device(s) to be used for boot up:

‘CRT’ - Uses the analog VGA display port

‘LFP’ - Uses the LVDS panel connected to the integrated LVDS port

‘EFPx’ - Uses the HDMI/DVI or DisplayPort device connected to DDI1, DDI2 and DDI3

Note: EFP selections are valid only when at least one DDI is enabled. The first enabled DDI is assigned to EFP. Therefore, EFP and DDI numbering do not necessarily match

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Feature

Secondary IGD Boot Display

Device

Active LFP Configuration

Always Try Auto Panel Detect

Local Flat Panel Type

Backlight Inverter Type

PWM Inverter Polarity

PWM Inverter Frequency (Hz)

Options

Disabled

CRT

LFP

EFP

EFP2

EFP3

No Local Flat Panel

Integrated LVDS eDP

No

Yes

Auto

VGA 640x480 1x18 (002h)

VGA 640x480 1x18 (013h)

WVGA 800x480 1x18 (01Fh)

WVGA 800x480 1x24 (01Bh)

SVGA 800x600 1x18 (01Ah)

XGA 1024x768 1x18 (006h)

XGA 1024x768 2x18 (007h)

XGA 1024x768 1x24 (008h)

XGA 1024x768 2x24 (012h)

WXGA 1280x800 1x18 (01Eh)

WXGA 1280x768 1x24 (01Ch)

SXGA 1280x1024 2x24 (00Ah)

SXGA 1280x1024 2x24 (018h)

UXGA 1600x1200 2x24 (00Ch)

HD 1920x1080 2x24 (01Dh)

WUXGA 1920x1200 2x18 (015h)

WUXGA 1920x1200 2x24 (00Dh)

Customized EDID™ 1



None

PWM

I2C

Normal

Inverted

200 - 40000

Description

Select the Secondary IGD display device(s) used for boot up

Note: VGA modes are only supported on the primary display. For further details, see ‘Primary

IGD Boot Display Device’

Select active local flat panel configuration

If set to ‘Yes’, the BIOS will use the EDID ™ data set in an external EEPROM to configure the LFP.

In case it cannot be found, the data set selected under ‘Local Flat Panel Type’ will be used

Select a predefined LFP type or choose ‘Auto’ to let the BIOS automatically detect and configure the attached LVDS panel. Auto detection is performed by reading an EDID ™ data set via the video I²C bus. The number in brackets specifies the congatec internal number of the respective panel data set

Note: Customized EDID™ utilizes an OEM defined EDID™ data set stored in the BIOS flash device

Select the type of backlight inverter:

‘PWM’ - IGD PWM signal

‘I2C’ - I2C backlight inverter device connected to the video I²C bus

Set PWM inverter polarity

Set the PWM inverter frequency in Hertz

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Feature

Backlight Setting

Options

0%

10%

25%

40%

50%

60%

75%

90%

100%

Force Backlight Enable

Inhibit Backlight

No

Yes

No

Permanent

Until End Of POST

Backlight Delay

Invert Backlight Setting

LVDS SSC

No delay

100ms Delay

250ms Delay

500ms Delay

1s Delay

No

Yes

Disabled

0.5%

1.0%

1.5%

2.0%

2.5%

Digital Display Interface 1 (DDI1) Auto Selection

Disabled

DisplayPort

HDMI/DVI


Disabled

DisplayPort

HDMI/DVI


Disabled

DisplayPort

HDMI/DVI

VGA Port Disabled

Enabled

Description

Select the backlight value in percentage of the maximum setting

Set to ‘Yes’, if the operating system driver does not activate the backlight signal

Select whether the backlight enable signal should be activated when the panel is activated.

Note: The signal should be permanently activated or remain inhibited until the end of BIOS

POST

Select delay to adjust LVDS panel timings

Note: T he congatec board controller will add the delay to the backlight signal coming from the

SoC according this setup node. This feature may help to avoid panel flickering

Allow to invert backlight control values if required for the actual I2C type backlight hardware controller

Select LVDS spread spectrum clock modulation depth

Note: Performs center spreading and DDI1 fixed modulation frequency of 32.9kHz

Select the output type of the DDI

Select the output type of the DDI

S elect the output type of DDI3

Note: If ‘VGA Port’ is enabled, ‘Auto Selection’ and ‘DisplayPort’ are not supported

Enable or disable VGA port.

Note: If enabled, the Auto Selection and DisplayPort is not supported on DDI3

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Feature

DisplayPort Spread Spectrum

Clock

► Display Interface Signal Integrity

Settings

Graphics Turbo IMON Current

Max. GPU Frequency

GTT Size

Aperture Size

IGD Pre-Allocated Graphics

Memory

IGD Total Graphics Memory

Options

Disabled

Enabled

Submenu

128MB

256MB

512MB

1024MB

2048MB

4096MB

320M

352M

384M

416M

448M

480M

512M

1024M

1536M

2048M

32M

64M

96M

128M

160M

192M

224M

256M

288M

31

(more values)

Default

800 MHz

700 MHz

600 MHz

500 MHz

2MB

4MB

8MB

128M

256M

MAX

Description

Enable or disable SSC for DisplayPort. Only valid if the attached DisplayPort panel supports SSC

Opens the ‘Display Interface Signal Integrity Settings submenu

Enter the value for the graphics turbo IMON current. Supported values are between 14 - 31

Allows to limit the maximum frequency of the integrated graphics engine

Select the GTT Size

Select the aperture size

Note:

To use this feature, disable CSM support

Above 4GB MMIO, BIOS assignment is automatically enabled when selecting 2048MB aperture

Select amount of pre-allocated graphics memory to be used by the IGD

Select amount of total graphics memory that may be used by the IGD. Memory above the fixed graphics memory is dynamically allocated by the graphics driver

Note: Refer to the DVMT 5.0 specification for more detailed information

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Feature

Gfx Low Power Mode

VDD Enable

PM Support

RC6 (Render Standby)

PAVP Enable

Cdynmax Clamping Enable

Cd Clock Frequency

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

337.5 MHz

450 MHz

540 MHz

675 MHz

11.4.1.1 Display Interface Signal Integrity Settings Submenu

Feature

HDMI 1 Level Shifter Config


Options

400mV/0.0dB

400mV/3.5dB

400mV/6.0dB

600mV/0.0dB

600mV/2.0dB

600mV/4.5dB

800mV/0.0dB

800mV/2.0dB

1000mV/2.0dB

1200mV/0.0dB

400mV/0.0dB

400mV/3.5dB

400mV/6.0dB

600mV/0.0dB

600mV/2.0dB

600mV/4.5dB

800mV/0.0dB

800mV/2.0dB

1000mV/2.0dB

1200mV/0.0dB

Description

This option applies only to SFF

Enable or disable VDD in the BIOS

Enable or disable PM support

Check to enable render standby support

Enable or disable PAVP

Enable or disable Cdynmax Clamping

Select the highest Cd clock frequency the platform supports

Description

Specifies HDMI level shifter configuration


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Feature


DisplayPort 1 Trace Lenght



DDI x IBoost

Magnitude for DP

Magnitude for HDMI

11.4.2 Watchdog Submenu

Feature

POST Watchdog

Options

Disabled

30sec

1min

2min

5min

10min

30min

Default

Short

Long

Default

Short

Long

Default

Short

Long

Options

400mV/0.0dB

400mV/3.5dB

400mV/6.0dB

600mV/0.0dB

600mV/2.0dB

600mV/4.5dB

800mV/0.0dB

800mV/2.0dB

1000mV/2.0dB

1200mV/0.0dB

Disabled

Enabled

0x1

0x3

0x7

0x1

0x3

0x7

Description


Determines the DP trace lenght from the silicon to the DP outport port



This setting, when enabled, will activate the IBoost feature for the selected port on all the

VSwing/pre-emphasis levels

Selects the supported IBoost magnitude level

Selects the supported IBoost magnitude level

Description

Select the timeout value for the POST watchdog

Note: The watchdog is only active during the system POST and provides a facility to prevent errors during boot up by performing a reset

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Feature

Stop Wdog for User Interaction

Stop Wdog for Password Entry

Runtime Watchdog

Delay

Event 1

Event 2

Event 3

Timeout 1

Timeout 2

Timeout 3

Options

No

Yes

No

Yes

Disabled

One-time Trigger

Single Event

Repeated Event

Disabled

10sec

30sec

1min

2min

5min

10min

30min

ACPI Event

Reset

Power Button

Disabled

ACPI Event

Reset

Power Button

Disabled

ACPI Event

Reset

Power Button

1sec

2sec

5sec

10sec

30sec

1min

2min

5min

10min

30min see above see above

Description

Select whether the POST watchdog should be stopped during the popup boot selection menu or while waiting for the setup password

Select whether the POST watchdog should be stopped while waiting for the setup password for password entry

Select the operating mode of the runtime watchdog

‘One-time Trigger’ - Disables watchdog after first trigger

‘Single Event’ - Executes every stage only once before the watchdog is disabled

‘Repeated Event’ - Executes last stage repeatedly until reset

Note: This watchdog will be initialized just before the operating system starts booting

Select the delay time before the runtime watchdog is activated

Note: This feature may be used to ensure that the operating system has enough time to load

Select the type of event that will be generated when timeout 1 is reached. For more information about

ACPI Event read the note at the end of this table

Select the type of event that will be generated when timeout 2 is reached

Select the type of event that will be generated when timeout 3 is reached

Select the timeout value for the first stage watchdog event

Select the timeout value for the second stage watchdog event

Select the timeout value for the third stage watchdog event

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Feature

Watchdog ACPI Event

Options

Shutdown

Restart

Description

Select the operating system event to be initiated by the watchdog ACPI event. This feature performs a critical but orderly operating system shutdown or restart

Note

In ACPI mode, the “Watchdog ACPI Event” handler cannot directly restart or shutdown the OS. The congatec BIOS will perform one of the following actions instead:

•

• Shutdown: An over temperature notification is executed. This causes the operating system to shut down in an orderly fashion.

Restart: An ACPI fatal error is reported to the OS.

11.4.3 Module Serial Ports Submenu

Feature

Serial Port 0

I/O Base Address

Interrupt

PNP ID

Baudrate

Options

Disabled

Enabled

3F8h

2F8h

220h

228h

238h

2E8h

338h

3E8h

None

IRQ3

IRQ4

IRQ5

IRQ6

IRQ14

IRQ15

None

PNP0501

CGT0501

2400

4800

9600

19200

38400

57600

115200

Description

Enable or disable module serial port 0

Set serial port base address

Set serial port interrupt

Set serial port ACPI ID

Set serial port initial baudrate

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Feature

Serial Port 1

I/O Base Address

Interrupt

PNP ID

Baudrate

Options

Disabled

Enabled

3F8h

2F8h

220h

228h

238h

2E8h

338h

3E8h

None

IRQ3

IRQ4

IRQ5

IRQ6

IRQ14

IRQ15

None

PNP0501

CGT0501

CGT0502

2400

4800

9600

19200

38400

57600

115200

11.4.4 Hardware Health Monitoring Submenu

Feature

CPU Temperature

Board Temperature

DC Input Voltage

5V Standby

DC Input Current

Options

No option

No option

No option

No option

No option

Description

Enable or disable module serial port 1

Set serial port base address

Set serial port interrupt

Set serial port ACPI ID

Set serial port initial baudrate

Description

Displays the module CPU temperature in °C

Displays the module board temperature in °C

Displays the actual voltage of the 12 V standard power supply

Displays the actual voltage of the 5V standby power rail

Displays the module input current from 12 V standard voltage

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Feature

CPU Fan Speed

Fan PWM Frequency Mode

Fan PWM Frequency

Fan PWM Frequency (kHz)

Pulses Per Revolution

Fan Speed Update Interval (ms)

Fan Speed Stepping Width

Default Fan Speed

Automatic Fan Speed Control

Fan Control Temperature

Lower Temperature Threshold

Upper Temperature Threshold

Minimum Fan Speed

Lower Temperature Fan Speed

Upper Temperature Fan Speed

Options

No option

Low Frequency

High Frequency

Description

Displays the CPU Fan Speed in RPM

Select the fan PWM base frequency mode:

‘Low Frequency’ - 11.0 to 88.2Hz

‘High Frequency’ - 1k to 63kHz

Select fan PWM base frequency (11.0Hz-88.2Hz).

(Only visible in low frequency mode)

3

4

1

2

11.0 Hz, 14.7 Hz, 22.1 Hz, 29.4

Hz, 35.3 Hz , 44.1 Hz, 58.8 Hz,

88.2 Hz

1-63

Default: 31

100ms ----1000ms

Select fan PWM base frequency (1kHz-63kHz).

(Only visible in high frequency mode)

Select the number of pulses per revolution generated by the attached fan

1%,2%, 4%, 8%, 16%, 32%,

64%, 100%

0%, 10%, 25%, 40%, 50%, 60%,

75%, 90%, 100%

Disabled

Enabled

CPU Temperature

Board Temperature

10ºC, 20ºC, 30ºC, 40ºC, 50ºC ,

60ºC, 70ºC, 80ºC, 90ºC

20ºC, 30ºC, 40ºC, 50ºC, 60ºC,

70ºC, 80ºC , 90ºC, 100ºC

Fan Off, 10%, 15%, 20%, 25%,

30%, 35%, 40%, 45%, 50%,

55%, 60%, 65%, 70%, 75%,

80%, 85%, 90%, 95%

Fan Off, 10%, 15%, 20%, 25%,

30%, 35%, 40%, 45%, 50%,

55%, 60% , 65%, 70%, 75%,

80%, 85%, 90%, 95%

Fan Off, 10%, 15%, 20%, 25%,

30%, 35%, 40%, 45%, 50%,

55%, 60%, 65%, 70%, 75%,

80% , 85%, 90%, 95%

A longer update interval lets the fan adjust slower to temperature changes and generate less noise

Defines how much the output value is adjusted to a new set point within one update interval

Choose the fan speed in percent of the maximum supported speed which is valid if the automatic fan speed control has been disabled

Enable or disable automatic fan speed control

Choose the temperature sensor used for automatic fan speed control

Set the temperature which defines the lower limit of the control range

Set the temperature which defines the upper limit of the control range

Choose the fan speed to be set if the temperature is below the lower temperature limit

Choose the fan speed to be set if the temperature is within the lower area of the control range

Choose the fan speed to be set if the temperature is within the upper area of the control range

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Feature

Maximum Fan Speed

Options

10%, 15%, 20%, 25%, 30%,

35%, 40%, 45%, 50%, 55%,

60%, 65%, 70%, 75%, 80%,

85%, 90%, 95%, 100%

Description

Choose the fan speed to be set if the temperature exceeds the upper temperature limit

Note

For more information about fan speed control settings, refer to congatec technical note CTN20180425.pdf.

11.4.5 Intel

®

Ethernet Connection (H) I219-LM Submenu

Feature

► NIC Configuration

Blink LEDs

UEFI Driver

Adapter PBA

Chip Type

PCI Device ID

PCI Address

Link Status

MAC Address

Options

Submenu

0

(more values)

No option

No option

No option

No option

No option

No option

No option

Description

Opens the NIC Configuration submenu

Set the duration in seconds for the Ethernet LEDs to blink

Displays the UEFI Driver version

Displays the Adapter PBA

Displays the type of the chip in which the Ethernet controller is integrated

Displays the PCI Device ID of the Ethernet controller

Displays the PCI Bus:Device:Function number of the Ethernet controller

Displays the Link Status

Displays the MAC Address

11.4.5.1 NIC Configuration Submenu

Feature

Link Speed

Description

Select the port speed used for the selected boot protocol

Wake On LAN

Options

Auto Negotiated

10 Mbps Half

10 Mbps Full

100 Mbps Half

100 Mbps Full

N/A

Disabled

Enabled

Enable for the server to power on after receiving an in-band magic packet

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11.4.6 Driver Health Submenu

Feature

Intel ® Gigabit 0.0.09

Options

Healthy

Description

Provides Health Status for the drivers/controllers

11.4.7 Trusted Computing Submenu

Feature

Security Device Support

Pending Operation

Platform Hierarchy

Storage Hierarchy

Endorsement Hierarchy

TPM 2.0 UEFI Spec Version

Physical Presence Spec Version

Device Select

Options

Disable

Enable

None

TPM Clear

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

TCG_1_2

TCG_2

1.2

1.3

TPM1.2

TPM2.0

Auto

Description

Enable or disable BIOS support for security device. Operating system will not show the security device. TCG EFI protocol and INT1A interface will not be available

Schedule an operation for the security device

Enable or disable Platform Hierarchy

Enable or disable Storage Hierarchy

Enable or disable Endorsement Hierarchy

Select the TCG2 spec version support

Select the PPI spec version support

Auto supports both with the default set to TPM2.0 devices. If TPM2.0 device is not found, TPM1.2 devices will be enumerated

Note

Additional features are shown in this submenu if a TPM device is connected.

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11.4.8 RTC Wake Settings Submenu

Feature

RTC Wake Mode

Wake up hour

Wake up minute

Wake up second

0

0

0

Options

Disabled

Wake from S4 and S5

Wake from S3, S4 and S5

11.4.9 LPC Generic I/O Range Decode Submenu

Feature

LPC Generic I/O Range Decode 2

Base IO Address

Lenght


Base IO Address

Lenght


Base IO Address

Length

Game Port Decoding

Reserve Resources in ACPI

LPC COM Port Decoding 1

I/O Base Address

Description

Set system wake mode on alarm event.

Enable this feature to wake from the specified Sx states on the hr::min::sec as specified

Specify wake up hour. For example: Enter 3 for 3am and 15 for 3pm

Specify wake up minute

Specify wake up second

Options

Disabled

Enabled

A00

4 Bytes, 8 Bytes, 16 Bytes, 32 Bytes ,

64 Bytes, 128 Bytes, 256 Bytes

Disabled

Enabled

100

4 Bytes, 8 Bytes, 16 Bytes, 32 Bytes,


Disabled

Enabled

100

4 Bytes, 8 Bytes, 16 Bytes, 32 Bytes,


Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

3F8h , 2F8h, 220h, 228h, 238h,2E8h,

338h, 3E8h

Description

Enable LPC generic I/O decode range register

Base I/O address of the LPC decode range (100h – FFFh)

Length of the LPC decode range







Enable address range 200h-20Fh I/O decoding on LPC bus

Reserve the LPC I/O resources in ACPI. A PNP0C02 device consuming the selected resources will be reported to the OS

Enable LPC COM port I/O decoding

Select COM port I/O base address

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Feature

Reserve Legacy Interrupt

LPC COM Port Decoding 2

I/O Base Address

Reserve Legacy Interrupt

Reserve Legacy Interrupt 1

Reserve Legacy Interrupt 2

Options

None , IRQ3, IRQ4, IRQ5, IRQ6,

IRQ10, IRQ11, IRQ14, IRQ15

Disabled

Enabled

3F8h, 2F8h , 220h, 228h, 238h,2E8h,

338h, 3E8h



None , IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,

IRQ10, IRQ11, IRQ12, IRQ14, IRQ15

None , IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,

IRQ10, IRQ11, IRQ12, IRQ14, IRQ15

Description

The interrupt reserved here will not be assigned to any PCI or PCI Express device and thus might be available for a legacy LPC bus device

Enable LPC COM port I/O decoding

Select COM port I/O base address




11.4.10 GPI IRQ Configuration Submenu

Feature

IRQ on GPIx

(x = 0 to 3)

IRQ Select

Options

Disabled

Enabled


IRQ7, IRQ8, IRQ9, IRQ10, IRQ11,


Description

Enables the GPIx to cause an IRQ

Select the IRQ that should be triggered

11.4.11 ACPI Submenu

Feature

Enable ACPI Auto Configuration

Hibernation Support

ACPI Sleep State

Lock Legacy Resources

S3 Video Repost

Options

Disabled

Enabled

Disabled

Enabled

Suspend Disabled

S3 (Suspend to RAM)

Disabled

Enabled

Disabled

Enabled

Description

Enable or disable BIOS ACPI auto configuration

Enable or disable system’s ability to hibernate (operating system S4 sleep state)

Note: Ensure that your operating system supports this feature if you want to use it

Select the state used for ACPI system sleep/suspend

Enable or disable locking of legacy resources

Enable or disable video BIOS re-post on S3 resume

Note: Enable this feature if it is required by your operating system

91/126

Feature

ACPI Low Power S0 Idle

Automatic Critical Trip Point

Critical Trip Point Value

ACPI 3.0 T-States

Native PCI Express Support

Native ASPM

BDAT ACPI Table Support

ACPI Debug

Lid Button Support

Sleep Button Support

Options

Disabled

Enabled

Disabled

Enabled

71 C

79 C

87 C

95 C

100 C

103 C

111 C

119 C

127 C

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Description

Enable or disable ACPI low power S0 idle support

Enable this feature to set the critical trip point (temperature threshold) to the recommended value at which the ACPI aware operating system performs a critical shutdown automatically

Disable this feature to configure the critical trip point manually

Select the temperature threshold at which the ACPI aware operating system performs a critical shutdown

Note: Only visible if Automatic Critical Trip Point is set to ‘Disabled’

Enable or disable ACPI 3.0 T-States

Enable or disable native OS PCI Express support

Enabled = The OS will control the ASPM support of the PCI Express device

Disabled = The BIOS will control the ASPM support of the PCI Express device

Enables support for the BDAT ACPI table

Opens a memory buffer for storing debug strings. Use method ADBG to write strings to buffer

If this feature is enabled, the COM Express LID# signal acts as ACPI lid

If this feature is enabled, the COM Express SLEEP# signal acts as ACPI sleep button

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11.4.12 Intel

®

ICC Submenu

Feature

ICC/OC Watchdog Timer

ICC Locks after EOP

ICC Profile

Options

Disabled

Enabled

Default

0

11.4.13 PCH-FW Configuration Submenu

Displayed only if this feature is enabled.

Feature

ME FW Version

ME Firmware Mode

ME Firmware Type

ME Firmware SKU

PTT Capability / State

NFC Support

ME State fTPM Switch Selection

TPM Device Selection

Options

No option

No option

No option

No option

No option

No option

Disabled

Enabled

GPDMA Work-Around

MSFT QFE Solution dTPM 1.2

PTT

► Firmware Update Configuration

Me FW Image Re-Flash

Submenu

Disabled

Enabled

Description

Enable this feature to expose the ICC/OC watchdog timer to the operating system as an

ACPI device

Note: WDT HW is always used by BIOS when clock settings are changed

Description

Displays ME FW Version

Displays ME Firmware Mode

Displays ME Firmware Type

Displays ME Firmware SKU

Displays PTT Capability / State

Displays NFC Support

Enable to set ME to Soft Temporary Disabled

Selects the desired fTPM solution to be used

Select TPM device:

‘PTT’ - Enables PTT and disables dTPM in SkuMgr

‘dTPM 1.2’ - Enables dTPM 1.2 and disables PTT in SkuMgr

Warning: If you enable PTT, dTPM will be disabled and all data saved on it will be lost.

Likewise, if you enable dTPM, PTT will be disabled and all data saved on it will be lost

Opens submenu to configure management engine technology parameters

Enable or disable Me FW Image Re-Flash function

93/126

11.4.14 SMART Settings Submenu

Feature

SMART Self Test

Options

Disabled

Enabled

11.4.15 Super IO Submenu

Description

Run SMART self test on all HDDs during POST

Feature

Super IO Chip

SIO Clock

Serial Port

Device Settings

Serial Port

Device Settings

Parallel Port

Device Settings

Device Mode

Options

W83627

24MHz

48MHz

Disabled

Enabled

IO=3F8h

IRQ=4

Disabled

Enabled

O=2F8h

IRQ=3

Disabled

Enabled

IO=378h

IRQ=5

STD Printer Mode

SPP Mode

EPP-1.9 and SPP Mode

EPP-1.7 and SPP Mode

ECP Mode

ECP and EPP 1.9 Mode

ECP and EPP 1.7 Mode

Description

Select Super IO base clock

Enable or disable serial port (COM)

Displays the currently used settings

Enable or disable serial port (COM)


Enable or disable parallel port (LPT/LPTE)


Select the parallel port mode

Note

This setup menu is available only if an external Winbond W83627 Super I/O is implemented on the carrier board.

94/126

11.4.16 Serial Port Console Redirection Submenu

Feature

COMx

Console Redirection

► Console Redirection Settings

► Legacy Console Redirection Settings

Serial Port for Out-of-Band Management /

Windows Emergency Management Services

(EMS) Console Redirection

► Console Redirection Settings

Options

Disabled

Enabled

Submenu

Submenu

Disabled

Enabled

Submenu

Description

Enable or disable serial port x console redirection

Opens the console redirection configuration submenu

Opens the Legacy Console Redirection Settings submenu

Enable or disable the Serial Port for Out-of-Band Management/ Windows Emergency

Management Services (EMS) Console Redirection

Opens the console redirection configuration submenu

Note

The Serial Port Console Redirection can be enabled (functional) only if an external Super I/O offering UARTs has been implemented on the carrier board or with the onboard Serial Ports being enabled.

11.4.16.1 Console Redirection Settings Submenu

Feature

Terminal Type

Baudrate

Data Bits

Parity

Stop Bits

Options

VT100

VT100+

VT-UTF8

ANSI

7

8

9600

19200

38400

57600

115200

1

2

None

Even

Odd

Mark

Space

Description

Select terminal type

Select baud rate

Set the number of data bits

Select the parity

Set the number of stop bits

95/126

Feature

Flow Control

VT-UTF8 Combo Key Support

Recorder Mode

Resolution 100x31

Legacy OS Redirection Resolution

Putty KeyPad

Redirection After BIOS POST

Options

None

Hardware RTS/CTS

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

80x24

80x25

VT100

LINUX

XTERMR6

SCO

ESCN

VT400

Enabled

Disabled

Description

Select the flow control

Enable the VT-UTF8 combination key support for ANSI/VT100 terminals

Enable this feature to only send text output over the terminal

Note: This feature is helpful to capture and record terminal data

Enable or disable the extended terminal resolution

Select the number of rows and columns supported for legacy operating system redirection

Select function key and keypad on Putty

Enable to continue serial redirection after POST

Note

The Console Redirection Settings submenu for Serial Port for Out-of-Band Management/ Windows Emergency Management Services (EMS)

Console Redirection does not contain all above listed items and contains the additional Out-of-Band Management Port selection item.

11.4.17 CPU Submenu

Feature

► CPU Information

Set Boot Freq Ratio

Hyper-Threading

Active Processor Cores

Overclocking Lock

Intel Virtualization Technology

Hardware Prefetcher

Options

Submenu

255

(more values)

Disabled

Enabled

All , 1, 2, 3

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Description

Range: 4 – 28. If out of range ratio, maximum ratio is used. This sets the boot ratio. Non-ACPI OSes will use this ratio

Enable or disable hyper-threading technology

Set number of cores to be enabled

FLEX_RATIO(194) MSR

When enabled, a VMM can utilize the integrated hardware virtualization support

To turn on or off the MLC streamer prefetcher

96/126

Feature

Adjacent Cache Line Prefetch

CPU AES

Boot performance mode

Intel ® Speed Shift Technology

Intel ® SpeedStep™

Turbo Mode

TCC Activation Offset

P-State Reduction

Package Power Limit Lock

1-Core Ratio Limit Override




Configurable TDP Boot Mode

Configurable TDP Lock

Disabled by 1 by 2 by 3 by 4 by 5 by 6 by 7 by 8

Disabled

Enabled

0

(more values)

0

(more values)

0

(more values)

0

(more values)

Nominal

Down

Up

Deactivate

Options

Disabled

Enabled

Disabled

Enabled

Max Battery

Max Non-Turbo

Performance

Turbo Performance

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

0

(more values)

Description

To turn on or off prefetching of adjacent cache lines

Enable or disable CPU Advanced Encryption Standard (AES) instructions

Select the performance state that the BIOS will set before OS handoff

Enable or disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states

Allows more than two frequency ranges to be supported

Enable or disable Turbo Mode

Offset from the Intel factory Thermal Control Circuit (TCC) activation temperature. TCC activation will lower CPU core and graphics core frequency, voltage or both. The factory TCC activation temperature is normally 100C. By entering 10 for TCC offset the TCC will be activated at 90C

Limits the maximum non-turbo CPU performance state in an ACPI operating system

Note: Only visible if Intel Speed Shift Technology and Turbo Mode are disabled

Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register

This limit is for 1 cores active. 0 means using the factory-configured value




Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to

Nominal and MMIO to Zero

Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL

Note: When CTDP Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot

Index will be forced to 0

97/126

Feature

CTDP BIOS control

Platform PL1 Enable

Platform PL1 Power

Platform PL1 Time Window

Platform PL2 Enable

Platform PL2 Power

CPU C States

Enhanced C1 State

C-State Auto Demotion

C-State Un-demotion

Package C State Demotion

Package C State Undemotion

CState Pre-Wake

Package C State Limit

Options

Disabled

Enabled

Disabled

Enabled

0

(more values)

0

(more values)

Disabled

Enabled

0

(more values)

Disabled

Enabled

Disabled

Enabled

C0/C1

C2

C3

C6

C7

C7s

C8

C9

C10

AUTO

Disabled

Enabled

Disabled

C1

C3

C1 and C3

Disabled

C1

C3

C1 and C3

Disabled

Enabled

Disabled

Enabled

Description

Enables CTDP control via runtime ACPI BIOS methods. This “BIOS only” feature does not require EC or driver support

Enable or disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window

Platform Power Limit 1 Power in Milli Watts and step size is 125mW. Any value can be programmed between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). This setting will act as the new PL1 value for the Package RAPL algorithm

Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. If the value is 0, default values will be programmed. Indicates the time window over which Platform TDP value should be maintained.

Enable or disable Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2

Platform Power Limit 2 Power in Milli Watts and stepsize is 125mW. Any value can be programmed between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). This setting will act as the new PL2 value for the

Package RAPL algorithm

Enable or disable CPU C states

Enable or disable C1E. If this feature is enabled, the CPU will switch to minimum speed when all cores enter

C-State

Configure C-State Auto Demotion

Configure C-State Un-demotion

Configure C-State demotion

Configure C-State Un-demotion

Disable this feature to set bit 30 of POWER_CTL MSR(0x1FC) to 1, disabling the Cstate Pre-Wake

Package C state limit

98/126

Feature

CFG Lock

Options

Disabled

Enabled

Intel ® TXT(LT) Support

Debug Interface

Debug Interface Lock

SW Guard Extensions (SGX)

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Software Controlled

Select Owner EPOCH input type No Change in Owner

EPOCHs

Change to New

Random Owner

EPOCHs

Manual User Defined

Owner EPOCHs

PRMRR Size AUTO

Description

Configure MSR 0xE2[15], CFG lock bit

Enable or disable Intel ® TXT(LT) support

Enable or disable CPU debug feature

Lock CPU debug feature setting

Enable or disable Software Guard Extensions (SGX)

Select owner EPOCH mode. Each EPOCH is 64-bit

There are three Owner EPOCH modes (Each EPOCH is 64bit): no change in owner epoch, change to new random owner epoch and manually entered by user. After the user enters epoch values manually, the values will not be visible, for security reasons

11.4.17.1 CPU Information

Feature

Processor Type

CPU Signature

Microcode Patch

Max CPU Speed

Min CPU Speed

CPU Speed

Processor Cores

Hyper Threading Technology

Intel ® VT-x Technology

Intel ® SMX Technology

64-bit

EIST Technology

CPU C3 State

CPU C6 State

CPU C7 State

CPU C8 State

CPU C9 State

Options

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

No option

Description

Displays the processor ID string. The “Processor Type” text is not displayed

Displays the CPU signature

Displays the revision of the microcode patch

Displays the maximum CPU speed

Displays the min CPU speed

Displays the current CPU speed

Displays the number of the processor cores

Displays whether Intel ® HT technology is supported

Displays whether Intel ® VT-x technology is supported

Displays whether Intel ® SMX technology is supported

Displays whether 64-bit is supported

Displays whether enhanced Intel ® SpeedStep Technology (EIST) is supported

Displays whether CPU C3 state is supported





99/126

Feature

CPU C10 State

L1 Data Cache

L1 Code Cache

L2 Cache

L3 Cache

L4 Cache

11.4.18 SATA Submenu

Feature

SATA Controller(s)

SATA Mode Selection

SATA RAID ROM

CR#1 - RST Pcie Storage Remapping

CR#1 - Remap Port Selection

Options

No option

No option

No option

No option

No option

No option





Options

Enabled

Disabled

AHCI

RAID

Legacy ROM

UEFI Driver

Both

Enabled

Disabled

Auto

Port 9

Port 10

Port 11

Port 12

Enabled

Disabled

Auto

Port 13

Port 14

Port 15

Port 16

Enabled

Disabled

Auto

Port 17

Port 18

Port 19

Port 20

Description


Displays the size of the L1 data cache

Displays the size of the L1 code cache

Displays the size of the L2 cache



Description

Enable or disable the onboard SATA controller(s)

Select SATA controller mode

Note: RAID option is not supported on all chipsets

Legacy ROM: Legacy option ROM

EFI Driver: UEFI Raid Driver

Both: Run the legacy Option ROM and UEFI driver

Enable or disable RST PCIe storage remapping

Select port for RST PCIe storage remapping

Enable or disable RST Pcie storage remapping


Enable or disable RST PCIe storage remapping


100/126

Feature

SATA Test Mode

Alternate ID

► Software Feature Mask Configuration

Aggressive LPM Support

SATA Controller Speed

Serial ATA Port 0, 1, 2, 3

Software Preserve

SATA Port

Hot Plug

External SATA

SATA Power

Spin Up Device

SATA Device Type

Topology

Device Sleep

SATA DEVSLEP Idle Timeout Config

Options

Enabled

Disabled

Enabled

Disabled

Submenu

Enabled

Disabled

Default

Gen1

Gen2

Gen3

No option

No option

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

SATA SSD/HDD

SATA DOM

Disabled

Enabled

Hard Disk Drive

Solid State Drive

Unknown

ISATA,

Direct Connect

Flex

M2

Disabled

Enabled

Disabled

Enabled

Description

Only enable this feature for verification measurements

Enable this feature to report an alternate device ID

Note: Displayed only for RAID SATA mode

RAID option ROM and Intel ® Rapid Storage Technology driver will refer to the ‘Software Feature

Mask Configuration’ to enable or disable the storage features

Enable PCH to aggressively enter link power state

Indicates the maximum speed the SATA Controller can support

Default = maximum speed

Gen1 = 1.5 Gbit/s

Gen2 = 3 Gbit/s

Gen3 = 6 Gbit/s

Displays the name of the connected Hard Disk or DVDROM if the port is enabled. No options are displayed if the port is disabled or when the port is enabled but no device is connected to it

Indicates whether the detected drive supports software settings preservation

Enable or disable the relevant SATA port

Enable or disable hot plug support for relevant SATA port

Enable or disable external SATA support on relevant SATA port

Change the sata power configuration - enable disk on

Module

Enable this feature to run an initialization sequence for the connected device during startup at relevant SATA port

Note: Enable this feature if your hard disk or special (special) solid-state drive requires it

Select whether the relevant SATA port is connected to solid-state drive or a hard disk drive

Select the SATA topology

Enable or disable mSata for RTD3

Enable or disable SATA DTIO Config

101/126

11.4.18.1 Software Feature Mask Configuration

Feature

RAID0

RAID1

RAID10

RAID5

Intel ® Rapid Recovery Technology

Option ROM UI and Banner

HDD Unlock

LED Locate

IRRT Only on eSATA

Smart Response Technology

Option ROM UI Normal Delay

RST Force Form

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

2 Seconds

4 Seconds

6 Seconds

8 Seconds

Disabled

Enabled

Description

Enable or disable RAID0 feature




Enable or disable Intel ® Rapid Recovery Technology

Enable this feature to display the option ROM user interface

Note: No option ROM banner or information are displayed if all disks and RAID volumes are normal

If this feature is enabled, the HDD password unlock option is available in the operating system

Enable or disable ‘LED Locate’

If this feaute is enabled, only Intel ® Rapid Recovery Technology (IRRT) volumes can span internal and external SATA (eSATA) drives

If this feautre is disabled, only RAID volume can span internal and eSATA drives

Enable or disable ‘Intel ® Smart Response Technology’

If this feature is enabled, select the delay of the option ROM user interface splash screen in normal status

Enable or disable form for Intel ® Rapid Storage Technology

102/126

11.4.19 Acoustic Management Submenu

Feature

Acoustic Management Configuration

SATA Port 0

Disk drive name

Acoustic Mode

Options

Disabled

Enabled

Bypass

Quiet

Max Performance

Description

Disable or enable ‘Acoustic Management Configuration’

Select acoustic noise level and performance optimization of optical or hard disk drives:

‘Bypass’ - Uses drive's preset value

‘Quiet’ - Reduces the drive’s speed

‘Max Performance’ - Maximizes the drive’s speed

Same as at SATA Port 0 SATA Port 1

Disk drive name

Acoustic Mode

SATA Port 2

Disk drive name

Acoustic Mode

SATA Port 3

Disk drive name

Acoustic Mode

Bypass

Quiet

Max Performance

Bypass

Quiet

Max Performance

Bypass

Quiet

Max Performance

Same as at SATA Port 0

Same as at SATA Port 0

Note

SATA ports are displayed only if an optical or hard disk drive is detected.

11.4.20 PCI Express Configuration Submenu

Feature

PCI Bus Driver Version

PCI Settings

PCI Latency Timer

Options

No option

32 PCI Bus Clocks

64 PCI Bus Clocks

96 PCI Bus Clocks

128 PCI Bus Clocks

160 PCI Bus Clocks

192 PCI Bus Clocks

224 PCI Bus Clocks

248 PCI Bus Clocks

Description

Select value to be programmed into PCI latency timer register

103/126

Feature

PCI-X Latency Timer

VGA Palette Snoop

PERR# Generation

SERR# Generation

Above 4G Decoding

Don't Reset VC-TC Mapping

BIOS Hot-Plug Support

PCI Buses Padding

I/O Resources Padding

MMIO 32 bit Resources Padding

Disabled

Enabled

4

5

2

3

Disabled

1

Disabled

4 K

8 K

16 K

32 K

Disabled

1 M

2 M

4 M

8 M

16 M

32 M

64 M

128 M

Options

32 PCI Bus Clocks

64 PCI Bus Clocks

96 PCI Bus Clocks

128 PCI Bus Clocks

160 PCI Bus Clocks

192 PCI Bus Clocks

224 PCI Bus Clocks

248 PCI Bus Clocks

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Description

Select value to be programmed into the PCI latency timer register

Enable or disable VGA palette registers snooping

Enable or disable PCI device to generate PERR#

Enable or disable PCI device to generate SERR#

Enables or disables 64-bit capable devices to be decoded in Above 4G Address Space (only if system supports 64-bit PCI Decoding)

If the system has Virtual Channels, software can reset traffic class mapping to its default state through virtual channels

Note: Enabling this feature will not modify VC resources

Enable this feature to allow BIOS build in hot-plug support

Note: Use this feature if the operating system does not support PCIe and SHPC hot-plug natively

Padd PCI buses behind the bridge for hot-plug

Select padd PCI I/O resources behind the bridge for hot-plug

Select padd PCI MMIO 32-bit resources behind the bridge for hot-plug

104/126

Feature

PFMMIO 32 bit Resources Padding

Options

Disabled

1 M

2 M

4 M

8 M

16 M

32 M

64 M

128 M

11.4.21 PCI Express Configuration Submenu

Feature

PCI Express Clock Gating

DMI Link ASPM Processor Side

Port8xh Decode

Peer Memory Write Enable

Compliance Test Mode

PCIe-USB Glitch W/A

PCIe Function Swap

PCIe Spread Spectrum Clocking

► PCI Express Gen3 Eq Lanes

► PCI Express Settings

► PCI Express Gen2 Settings

► PCI Express Port 0


Description

Select padd PCI MMIO 32-bit prefetchable resources behind the bridge for hot-plug

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Auto

0.1%, 0.2%, 0.3%, 0.4%, 0.5%,

0.6%, 0.7%, 0.8%, 0.9%, 1.0%,

1.1%, 1.2%, 1.3%, 1.4%, 1.5%,

1.6%, 1.7%, 1.8%, 1.9%, 2.0%

Submenu

Submenu

Submenu

Submenu

Submenu

Description

Enable or disable PCI Express clock gating for each root port

Enable or disable Active State Power Management of the DMI link on the processor side. DMI link is the main bus between the Processor and Platform Controller Hub (PCH)

Enable or disable Port8xh Decode

Enable or disable Peer Memory Write

Enable or disable Compliance Test Mode. Enable when using compliance load board

Enable or disable PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIe/PEG port

Enable or disable PCIe Function Swap. When disabled, it prevents PCIe root port function swap. If any function other than 0th is enabled, 0th will become visible

PCIe PLL SSC percentage

Auto keeps hardware default, no BIOS override

Note: Hardware default is 0.45%

PCI Express Gen3 equalization settings per PCIe lane

Change PCI Express settings

Change PCI Express Gen Devices settings

PCI Express port 0 settings


105/126

Feature







Options

Submenu

Submenu

Submenu

Submenu

Submenu

Submenu

11.4.21.1 PCI Express Gen3 Eq Lanes Submenu

Feature

Override SW EQ Settings

Options

Disabled

Enabled

11.4.21.2 PCI Express Settings Submenu

Feature

PCI Express Device Register Settings

Relaxed Ordering

Extended Tag

No Snoop

Maximum Payload

Maximum Read Request

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Auto

128 Bytes

256 Bytes

512 Bytes

1024 Bytes

2048 Bytes

4096 Bytes

Auto

128 Bytes

256 Bytes

512 Bytes

1024 Bytes

2048 Bytes

4096 Bytes

Description







Description

Description

Enable or disable PCI Express device relaxed ordering

Enable or disable Extended Tag. If enabled, a device may use an 8-bit tag field as a requester

Enable or disable PCI Express device ‘No Snoop’ option

Set maximum payload of PCI Express device or allow system BIOS to select the value

Set maximum read request size of PCI Express device or allow system BIOS to select the value

106/126

Feature

PCI Express Link Register Settings

ASPM

Extended Synch

Link Training Retry

Link Training Timeout (us)

Unpopulated Links

Restore PCIe Registers

11.4.21.3 PCI Express GEN2 Settings Submenu

Feature

PCI Express GEN2 Device Register Settings

Completion Timeout

ARI Forwarding

Options

Default

Shorter

Longer

Disabled

Disabled

Enabled

AtomicOp Requester Enable

AtomicOp Egress Blocking

IDO Request Enable

IDO Completion Enable

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Options

Disabled

Enabled

Disabled

Enabled

3

5

Disabled

2

1000

(more values)

Keep Link On

Disabled

Disabled

Enabled

Description

Enable or disable Active State Power Management settings

Warning: Enabling ASPM may cause some PCIe devices to fail

Enable or disable the generation of extended synchronization patterns

Defines the number of retry attempts software will take to retrain the link if previous training attempt was unsuccessful

Defines the number of microseconds software will wait before polling link training bit in the link status register. Value ranges from 10 to 10000 microseconds

If set to ‘disabled’, the software will disable unpopulated PCI Express links in order to save power

On non-PCI Express aware operating systems, some devices may not be re-initialized correctly after

S3. Setting this mode to ‘Enabled’ restores PCI Express configuration on S3 resume

Warning: Enabling this may cause issues with other hardware after S3 resume

Description

In device functions that support Completion Timeout programmability, allows system software to modify the Completion Timeout value. Default is between 50 microseconds and 50 milliseconds

If supported by hardware and set to ‘Enabled’, the downstream port disables its traditional device number field being 00 enforcement when turning a Type1 configuration request in to aType0 configuration request, permitting access to Extended Functions in an ARI device immediately below the port

If supported by hardware and set to ‘Enabled’, this function initiates AtomicOp Requests only if Bus

Master Enable bit is in the Command Register Set

If supported by hardware and set to ‘Enabled’, outbound AtomicOp Requests via Egress ports will be blocked

If supported by hardware and set to ‘Enabled’, this permits setting the number of ID-Based Ordering

(IDO) bit requests to be initiated

If supported by hardware and set to ‘Enabled’, this permits setting the number of ID-Based Ordering

(IDO) bit requests to be initiated

107/126

Feature

LTR Mechanism Enable

End-end TLP Prefix Blocking

PCI Express GEN2 Link Register Settings

Target Link speed

Clock Power Management

Compliance SOS

Hardware Autonomous Width

Hardware Autonomous Speed

Options

Disabled

Enabled

Disabled

Enabled

Auto

Force to 2.5 GT/s

Force to 5.0 GT/s

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

11.4.21.4 PCI Express Port 0 - 7 Submenu

Feature

PCI Express Port

Topology

ASPM

Gen3 Eq Phase3 Method

UPTP

Options

Disabled

Enabled

Unknown x1 x4

Sata Express

M2

Disabled

L0s

L1

L0sL1

Auto

Software Search

Hardware

Static Coeff.

5

(more values)

Description

If supported by hardware and set to ‘Enabled’, this enables the Latency Tolerance Reporting (LTR)

Mechanism

If supported by hardware and set to ‘Enabled’, this function will block forwarding of TLPs containing

End-End TLP Prefixes

If supported by hardware and set to ‘Force to 2.5 GT/s’, for downstream ports, this sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences.

When ‘Auto’ is selected, hardware initialized data will be used

If supported by hardware and set to ‘Enabled’, the device is permitted to use CLKREQ# signal for power management of link clock

If supported by hardware and set to ‘Enabled’, this will force LTSSM to send SKP Ordered Sets between sequences when sending Compliance Pattern or Modified Compliance Pattern

If supported by hardware and set to ‘Disabled’, this will disable the hardware’s ability to change link width except width size reduction for the purpose of correcting unstable link operation

If supported by hardware and set to ‘Disabled’, this will disable the hardware’s ability to change link width except width size reduction for the purpose of correcting unstable link operation

Description

Enable or disable the PCI Express Port

Identify the SATA topology if it is default or ISATA or Flex or DirectConnect or M2

Enable or disable PCI Express Active State Management settings

PCIe Gen3 Equalization Phase 3 method

Upstream Port Transmitter Preset

108/126

Feature

DPTP

ACS

URR

FER

NFER

CER

CTO

SEFE

SENFE

SECE

PME SCI

Hot Plug

Advanced Error Reporting

PCIe Speed

Transmitter Half Swing

Detect Non-Compliance Device

Extra Bus Reserved

Reserved Memory

Options

7

(more values)

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Auto

Gen1

Gen2

Gen3

Disabled

Enabled

Disabled

Enabled

0

(more values)

10

(more values)

Description

Downstream Port Transmitter Preset

Enable or disable Access Control Service Extended Capability

Enable or disable PCI Express Unsupported Request Reporting

Enable or disable PCI Express Device Fatal Error Reporting

Enable or disable PCI Express Device Non-Fatal Error Reporting

Enable or disable PCI Express Device Correctable Error Reporting

Enable or disable PCI Express Completion Timer TO

Enable or disable Root PCI Express System Error or Fatal Error

Enable or disable Root PCI Express System Error or Non-Fatal Error

Enable or disable Root PCI Express System Error on Correctable Error

Enable or disable PCI Express PME SCI

Enable or disable PCI Express hot plug

Enable or disable Advanced Error Reporting

Select PCI Express port speed

Enable or disable Transmitter Half Swing

Detect Non-Compliance PCI Express Device. If enabled, POST takes longer

Extra bus reserved (0-7) for bridges behind this root bridge

Reserved memory range for this root bridge

109/126

Feature

Prefetchable Memory

Reserved I/O

PCIe Cp

PCIe Cm

PCIe LTR

PCIe LTR Lock

Snoop Latency Override

Snoop Latency Multiplier

Snoop Latency Value

Non Snoop Latency Override

Non Snoop Latency Multiplier

Force LTR Override

Non Snoop Latency Value

Options

10

(more values)

4

(more values)

2

(more values)

6

(more values)

Disabled

Enabled

Disabled

Enabled

Disabled

Manual

Auto

1 ns

32 ns

1024 ns

32768 ns

1048576 ns

33554432 ns

60

(more values)

Disabled

Manual

Auto

1 ns

32 ns

1024 ns

32768 ns

1048576 ns

33554432 ns

Disabled

Enabled

60

(more values)

Description

Prefetchable memory range for this root bridge

Reserved I/O range for this root bridge

Gen3 Equalization settings for physical PCIe lane

Gen3 Equalization settings for physical PCIe lane

Enable or disable PCIe Latency Reporting

Enable or disable PCIe LTR Configuration Lock

Snoop Latency Override for PCH PCIe

Snoop latency multiplier for PCH PCIe

Snoop latency value for PCH PCIe

Non Snoop Latency Override for PCH PCIe

Non Snoop latency override for PCH PCIe

Force LTR Override for PCH PCIE

Disabled: LTR override values will not be forced

Enable: LTR override values will be forced and LTR messages from the device will be ignored

Non Snoop Latency Value for PCH PCIe

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11.4.21.5 PEG Port Configuration Submenu

Feature

PEG Port Configuration

PEG 0:1:0

Enable Root Port

PEG0 Speed

Max Link Width

Power Down Unused Lanes

Gen3 Eq Phase 2

Gen3 Eq Phase 3 Method

PEG0 ASPM

De-emphasis Control

OBFF

Options

1x16

2x8

1x8+2x4

No option

Description

Select how many ports, with certain widths, will be formed with the 16 PCIe lanes

Displays the width and operation mode of the device on PEG0 port (B0:D1:F0). Some Gen2 and Gen3 devices start up in Gen1 mode and their operating system driver sets them to the right mode

Enable or disable the root port Disabled

Enabled

Auto

Auto

Gen1

Gen2

Gen3

Set maximum speed for PEG0 port (B0:D1:F0):

‘Auto’ - Gen1, Gen2 or Gen3

‘Gen1’ - 2.5GT/s

‘Gen2’ - 5.0GT/s

‘Gen3’ - 8.0GT/s

Note: Some older non-compliant PCI Express devices will only function if Gen1 is selected

Force PEG link to retrain to x1, x2, x4 or x8 Auto

Force x1

Force x2

Force x4

Force x8

Auto

Disabled

Disabled

Enabled

Auto

Auto

Adaptive Hardware Equalization

Adaptive Software Equalization

Static Equalization

Disabled

Disabled

Auto

ASPM L0s

ASPM L1

ASPM L0sL1

-6 dB

-3.5 dB

Disabled

Enabled

Power down unused lanes

‘Auto’: BIOS will power down unused lanes based on the maximum possible link width

‘Disabled’: No power saving

Perform Gen3 Equalization Phase 2

Select method for Gen3 Equalization Phase 3

Select ASPM support for the PEG device. This has no effect if PEG is not the currently active device

Set the de-emphasis control on PEG

Enable or disable CPU PEG0 (0,1,0) OBFF

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Feature

LTR

PEG0 Slot Power Limit Value

PEG0 Slot Power Limit Scale

PEG0 Physical Slot Number

PEG0 Max Payload Size

Options

Disabled

Enabled

75

(more values)

1.0x

0.1x

0.01x

0.001x

1

(more values)

Auto

128 TLP

256 TLP

PEG 0:1:1

Same items under PEG 0:1:0 are displayed

PEG 0:1:2

Same items under PEG 0:1:0 are displayed

Detect Non-compliant Device Disabled

Enabled

Program PCIe ASPM after

OpROM

Program Static Phase1 Eq Disabled

Enabled

► Gen3 Root Port Preset Value for each Lane

► Gen3 Endpoint Preset Value for each Lane

Submenu

Submenu

► Gen3 Endpoint Hint Value for each Lane

Submenu

► Gen3 RxCTLE Control Submenu

Gen3 Adaptive Software Equalization

Always Attempt SW EQ

Disabled

Enabled

Enabled

Disabled

Description

Enable or disable CPU PEG0 (0,1,0) latency reporting

Sets the upper limit on power supplied by slot. Power limt (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values are between 0 and 255

Select the scale used for the Slot Power Limit Value

Set the physical slot number attached to this port. The number has to be globally unique within the chassis. Values are 0 - 8191

Select PEG0 Max Payload Size.

Choose ‘Auto’ (default device capability) or force to 128/256 bytes

Displays the width and the operation mode at which the attached device currently operates on PEG0 port (B0:D1:F1). Some Gen3, Gen2 devices start up in Gen1 mode and their OS driver just sets them to

Gen3 or Gen2 mode

Displays the width and the operation mode at which the attached device currently operates on PEG0 port (B0:D1:F2). Some Gen3, Gen2 devices start up in Gen1 mode and their OS driver just sets them to

Gen3 or Gen2 mode

Enable or disable the detection of non-compliant PCI Express device on the PEG port

‘Enabled’ - PCIe ASPM will be programmed after OpROM.

‘Disabled’ - PCIe ASPM will be programmed before OpROM

Program Phase1 Presets/CTLEp

In this submenu, the root port preset value for PEG port lanes 0 -15 can be set individually

In this submenu the endpoint preset value for PEG port lanes 0 -15 can be set individually

In this submenu the endpoint hint value for PEG port lanes 0 -15 can be set individually

In this submenu, the RxCTLE Value for PEG bundle 0 - 7 can be set individually

Enable to always attempt SW EQ, even it has been done once

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Feature

Number of Presets to test

SW EQ Enable VOC

Jitter Dwell Time

Jitter Error Target

VOC Dwell Time

VOC Error Target

Generate BDAT PEG Margin

Data

PCIe Rx CEM Test Mode

PEG Lane number for Test

Non-Protocol Awareness

Options

7, 3, 5

0-9

Auto

Jitter Only Test Mode

Jitter & VOC Test Mode

Auto

3000

0-65535

2

0-65535

10000

0-65535

2

0-65535

Disabled

Generate Port Jitter Data

Disabled

Enabled

2

(more values)

Disabled

Enabled

Description

‘Auto’ - Recommended by Intel ®

Select Jitter and VOC test mode (default) or Jitter only test mode

‘Auto’ will select Jitter and VOC test mode

Set PEG Gen3 preset search dwell time in [ms]

Set margin search error target value

Set VOC dwll time in [usec]

Set VOC margin search error target value

Disable or generate PEG generate BDAT margin table

Enable or disable the PEG Rx CEM Loopback Mode

PEG Lane number for Rx CEM Loopback mode (0 ~ 15)

Enable or disable Non-Protocol Awareness

Note

PEG 0:1:1 port related items displays only when 2 x8 or 1 x8 + 2 x4 is selected as PEG port configuration.

PEG 0:1:2 port related items displays only when 1 x8 + 2 x4 is selected as PEG port configuration

11.4.22 UEFI Network Stack Submenu

Feature

UEFI Network Stack

IPv4 PXE Support

IPv6 PXE Support

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Description

Enable or disable the UEFI network stack

Enable or disable IPv4 PXE boot support. If disabled, IPv4 PXE boot option will not be created

Enable or disable IPv6 PXE boot support. If disabled, IPv6 PXE boot option will not be created

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Feature

PXE boot wait time

Media detect count

Options

0

(more values)

1

(more values)

11.4.23 CSM & Option ROM Control Submenu

Feature

CSM Support

CSM16 Module Version

Gate A20 Active

Option ROM Messages

INT19 Trap Response

Boot Option Filter

Option ROM execution

PXE Option ROM Launch Policy

Storage Option ROM Launch Policy

Video Option ROM Launch Policy

Other Option ROM Launch Policy

Description

Set wait time to press ESC key to abort the PXE boot

Set the number of times to check for the presence of media

Options

Disabled

Enabled

No option

Upon Request

Always

Force BIOS

Keep Current

Immediate

Postponed

UEFI and Legacy

Legacy only

UEFI only

Description

Enable or disable CSM support

‘Upon Request’ - Gate A20 can be disabled with BIOS services

‘Always’ - Gate A20 cannot be disabled

Note: This feature is useful if runtime code above 1MB is executed

Set display mode for option ROMs

Set BIOS reaction on INT19 trapping by option ROM:

‘Immediate’ - Executes the trap right away

‘Postponed’ - Executes the trap during legacy boot

This feature controls which devices/boot loaders the system should boot to

Do not launch

UEFI ROM Only

Legacy ROM Only

Do not launch

UEFI ROM Only

Legacy ROM Only

Do not launch

UEFI ROM Only

Legacy ROM Only

Do not launch

UEFI ROM Only

Legacy ROM Only

This feature controls the execution of UEFI and legacy PXE option ROMs

This feature controls the execution of UEFI and legacy mass storage device option ROMs

This feature controls the execution of UEFI and legacy video option ROMs

This feature controls the execution of option ROMs for PCI / PCI Express devices other than network, mass storage and video

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11.4.24 NVMe Configuration Submenu

Settings are displayed if an NVMe device is connected.

11.4.25 USB Submenu

Feature

USB Controllers

USB Devices

Overcurrent Protection

Options

No option

No option

Disabled

Enabled

USB Precondition Disabled

Enabled

XHCI Disable Compliance Mode FALSE

TRUE

XDCI Support

USB Port Disable Override

USB SS Physical Connector #0




USB HS Physical Connector #0





Description

Displays the number of enabled EHCI (USB2.0) and xHCI (USB3.0) controllers

Displays the detected USB devices

Disable or enable overcurrent protection on all USB ports

Enable or disable USB Precondition (precondition makes enumeration faster)

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Select Per Port

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Options to disable Compliance Mode

‘False’ - do not disable compliance mode

‘True’ - disable compliance mode

Enable or disable USB OTG device

Selectively enable or disable the corresponding USB port from reporting a device connection to the controller

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Legacy USB Support

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Enabled

Disabled

Auto

External USB Controller Support xHCI Hand-off

Disabled

Enabled

Enabled

Disabled

USB Mass Storage Driver Support Disabled

Enabled

USB hardware delays and time-outs:

USB Transfer Timeout 1 sec

5 sec

10 sec

20 sec

Device Reset Timeout 10 sec

20 sec

30 sec

40 sec

Device Power-up Delay Selection Auto

Manual

USB Mass Storage Device Name

(Auto detected USB mass storage devices are listed here dynamically)

Auto

Floppy

Forced FDD

Hard Disk

CD-ROM

Disable this feature to keep USB devices available for EFI applications and BIOS setup only

Select ‘Auto’ to disable legacy support if no USB devices are connected

Enable or disable BIOS support for external USB controllers

This feature is a workaround for operating system without xHCI hand-off support

Note: If this feature is enabled, the xHCI ownership change should be claimed by the xHCI operating system driver

Enable or disable USB mass storage driver support

Select the timeout value for control, bulk, and interrupt transfers

Select the USB mass storage device Start Unit command timeout

‘Manual’ - Set maximum time a USB device requires to report itself to the host controller

‘Auto’ - Sets maximum time a USB device requires to report itself to the host controller to 100ms for a root port or derives the value from the hub descriptor of a hub port

Every USB mass storage device that is enumerated by the BIOS will have an emulation type setup option. This option specifies the type of emulation the BIOS has to provide for the device

Note: The device’s formatted type and the emulation type provided by the BIOS must match for the device to boot properly

Select ‘Auto’ to let the BIOS auto detect the current formatted media

If ‘Floppy’ is selected then the device will be emulated as a floppy drive

‘Forced FDD’ allows a hard disk image to be connected as a floppy image. Works only for drives formatted with FAT12,

FAT16 or FAT32.

‘Hard Disk’ allows the device to be emulated as hard disk

‘CDROM’ assumes the CD.ROM is formatted as bootable media, specified by the ‘El Torito’ Format Specification

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11.4.26 Diagnostics Settings Submenu

Feature Options

POST Code Redirection Settings

Relay Interface

Primary Port Addr.

Lowbyte (Dec)

Disabled

I2C

SMBus

BC Diagnostics Console

0-255 (128)

0-255 (0) Primary Port Addr.

Highbyte (Dec)

Relay Device Address

(Dec)

0-255 (226)

BC Diagnostics Console Settings

BC Diagnostics

Console Interface

Disabled

BC AUX Port

BC COM Port 0

BC COM Port 1

Parity Bit

Stop Bits

No Parity

Even Parity

Odd Parity

1 Stop Bit

2 Stop Bits

Data Bits

Baudrate

5 Data Bits

6 Data Bits

7 Data Bits

8 Data Bits

1200 Baud

2400 Baud

4800 Baud

9600 Baud

19200 Baud

38400 Baud

115200 Baud

Description

Select the relay interface to which the POST code will be redirected

Set the address for the primary debug port. The usual address value is 0x80 (i.e. 128 dec lowbyte and 0 highbyte). However, any multiple of 8 is valid for a primary debug port address

Set the address for the primary debug port. The usual address value is 0x80 (i.e. 128 dec lowbyte and 0 highbyte). However, any multiple of 8 is valid for a primary debug port address

Specify the I2C/SMBus device address of e.g. a 7-segment LCD for POST code display. The factory settings for the SparkFun device is 0xE2(226). However, any even device address can be specified

Select the interface to be used for the congatec Board Controller Diagnostic Console output or disable the diagnostic output

Choose the parity bits for the BC Diagnostic Console interface

Choose the stop bits for the BC Diagnostic Console interface

Choose the data bits for the BC Diagnostic Console interface

Choose the baudrate for the BC Diagnostic Console interface

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11.4.27 GPIO Configuration Submenu

Feature

GPO x State

(x = 0 to 3)

Current GPI configuration

Options

Low

High

Fh (bitmask)

Description

Set the state for GPO x

Each bit respresents the state of the corresponding GPI

11.4.28 Board Controller Command Control Submenu

Feature

CGBC_CMD_CFG_PINS

Options

Enabled

Disabled

CGBC_CMD_AVR_SPM Enabled

Disabled

BC Command Re-Enabling Event System Reset

S5 Power Cycle

G3 Power Cycle

Description

Enables or disables the command to set or get the system configuration pin states. On Intel platforms this also controls the Flash Descriptor Override (FDO)

Enables or disables the command to update the board controller firmware

Event that has to occur in order to re-enable a disabled command

11.4.29 PC Speaker Submenu

Feature

Debug Beeps

Input Device Debug Beeps

Output Device Debug Beeps

USB Driver Beeps

Options

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Description

Enable or disable general debug / status beep generation

Enable or disable input device debug beeps

Enable or disable output device debug beeps

Enable or disable USB driver beeps

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11.5 Chipset Setup

The description of this feature is beyond the scope of this document

11.6 Security Setup

Select the Security tab from the setup menu to enter the Security setup screen

11.6.1 Security Settings

Feature

BIOS Password

BIOS Lock

BIOS Update & Write Protection

HDD Security Configuration

List of all detected hard disks supporting the security feature set

► Secure Boot Menu

Options

Enter password

Disabled

Enabled

Disabled

Enabled

Submenu

Description

Set the desired BIOS and setup administrator password

Enable or disable BIOS Lock Enable (BLE) and SMM BIOS Write Protect (SMM_BWP) bits.

If enabled, BIOS flash write access is only possible via dedicated BIOS SMM interfaces

If enabled, the congatec flash software will require the BIOS password to perform write or erase operations

Select the device to open its security configuration submenu

11.6.1.1 BIOS Security Features

BIOS Password/ BIOS Write Protection

A BIOS password protects the BIOS setup program from unauthorized access. This ensures that end users cannot change the system configuration without authorization. With an assigned BIOS password, the BIOS prompts the user for a password on a setup entry. If the password entered is wrong, the BIOS setup program will not launch.

The congatec BIOS uses a SHA256 based encryption for the password, which is more secured than the original AMI encryption. The BIOS password is case sensitive with a minimum of 3 characters and a maximum of 20 characters. Once a BIOS password has been assigned, the

BIOS activates the grayed out ‘BIOS Update and Write Protection’ option. If this option is set to ‘enabled’, only authorized users (users with the correct password) can update the BIOS. To update the BIOS, use the congatec system utility cgutlcmd.exe with the following syntax:

CGUTLCMD BFLASH <BIOS file> /BP: <password> where <password> is the assigned BIOS password.

For more information about “Updating the BIOS” refer to the congatec system utility user’s guide, which is called CGUTLm1x.pdf and can be

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found on the congatec GmbH website at www.congatec.com.

With the BIOS password protection and the BIOS update and write protection, the system configuration is completely secured. If the BIOS is password protected, you cannot change the configuration of an end application without the correct password.

Note

Use cgutlcmd.exe version 1.5.3 or later.

Built in BIOS recovery is disabled in the congatec BIOS firmware to prevent the BIOS from updating itself due to the user pressing a special key combination or a corrupt BIOS being detected. congatec considers such a recovery update a security risk because the BIOS internal update process bypasses the implemented BIOS security explained above.

Only the congatec utility interface to the SMI handler of the BIOS flash update is enabled. Other interfaces to the SMI handler are disabled to prevent non congatec tools from writing to the BIOS flash. As a result of this restriction, flash utilities supplied by AMI or Intel will not work .

UEFI Secure Boot

Secure Boot is a security standard defined in UEFI specification 2.3.1 that helps prevent malicious software applications and unauthorized operating systems from loading during system start up process. Without secure boot enabled (not supported or disabled), the computer simply hands over control to the bootloader without checking whether it is a trusted operating system or malware. With secure boot supported and enabled, the UEFI firmware starts the bootloader only if the bootloader’s signature has maintained integrity and also if one of the following conditions is true:

• The bootloader was signed by a trusted authority that is registered in the UEFI database.

• The user has added the bootloader’s digital signature to the UEFI database. The BIOS provides the key management setup sub-menu for this purpose.

Note

The congatec BIOS by default enables CSM (Compatibility Support Module) and disables secure boot because most of the industrial computers today boot in legacy (non-UEFI) mode. Since secure boot is only enabled when booting in native UEFI mode, you must therefore disable the

CSM (compatibility support module) in the BIOS setup to enable Secure Boot.

A full description of secure boot is beyond the scope of this users guide. For more information about how secure boot leverages signature databases and keys, see the secure boot overview in the windows deployment options section of the Microsoft TechNet Library at www.technet.microsoft.com.

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11.6.1.2 Hard Disk Security Features

Hard Disk Security uses the Security Mode feature commands defined in the ATA specification. This functionality allows users to protect data using drive-level passwords. The passwords are kept within the drive, so data is protected even if the drive is moved to another computer system.

The BIOS provides the ability to ‘lock’ and ‘unlock’ drives using the security password. A ‘locked’ drive will be detected by the system, but no data can be accessed. Accessing data on a ‘locked’ drive requires the proper password to ‘unlock’ the disk.

The BIOS enables users to enable/disable hard disk security for each hard drive in setup. A master password is available if the user can not remember the user password. Both passwords can be set independently however the drive will only lock if a user password is installed. The max length of the passwords is 32 bytes.

During POST each hard drive is checked for security mode feature support. In case the drive supports the feature and it is locked, the BIOS prompts the user for the user password. If the user does not enter the correct user password within four attempts, the user is notified that the drive is locked and POST continues as normal. If the user enters the correct password, the drive is unlocked until the next reboot.

In order to ensure that the ATA security features are not compromised by viruses or malicious programs when the drive is typically unlocked, the BIOS disables the ATA security features at the end of POST to prevent their misuse. Without this protection it would be possible for viruses or malicious programs to set a password on a drive thereby blocking the user from accessing the data.

Note

If the user enables password support, a power cycle must occur for the hard drive to lock using the new password. Both user and master password can be set independently however the drive will only lock if a user password is installed.

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11.7 Boot Setup

Select the Boot tab from the setup menu to enter the Boot setup screen.

11.7.1 Boot Settings Configuration

Feature

Quiet Boot

Setup Prompt Timeout

Options

Disabled

Enabled

1

(more values)

Bootup NumLock State

Enter Setup If No Boot Device

Enable Popup Boot Menu

Boot Priority Selection

Boot Option Sorting Method

On

Off

No

Yes

No

Yes

UEFI Standard

Type Based

Legacy First

UEFI First

1st, 2nd, 3rd, ...

Boot Device

(Up to 12 boot devices can be prioritized if “UEFI Standard” priority list control is selected. If “Type Based” priority list control is enabled only 8 boot devices can be prioritized.)

Battery Support

System Off Mode

Disabled

SATA 0 Drive

SATA 1 Drive

USB Harddisk

USB CDROM

Other USB Device

Onboard SD Card Storage

Onboard LAN

External LAN

Firmware-based Bootloader

Other Device

Auto (Batt. Manager)

Battery-Only On I2C Bus

Battery-Only On SMBus

G3/Mech Off

S5/Soft Off

Description

Enable this feature to display OEM logo instead of POST messages

Note: The default OEM logo is a dark screen

Set number of seconds to wait for a setup activation key:

‘65535’ - Waits indefinitely (0xFFFF)

‘0’ - Disables waiting but setup access is still possible (not recommended)

Set the keyboard numlock state

Set whether the setup menu should be started if no boot device is connected

Set whether the popup boot menu can be started

‘UEFI Based’ - Select boot priority from a list of currently detected devices

‘Type Based’ - Select boot priority from a list of device types even if they are not connected yet

Set boot option sorting method:

‘UEFI First’ - Tries all UEFI boot options before first legacy boot option

‘Legacy First’ Tries all Legacy boot options before first UEFI boot option

This view is only available in the default “Type Based” mode

In “UEFI Standard” mode, you will only see the devices that are connected to the system

‘Battery-Only On I2C Bus’ - Battery-only systems using I2C bus

‘Battery-Only On SMBus’ - Battery-only systems using SMBus

‘Auto’ - Real battery system manager systems using I2C or SMBus

Set system state after shutdown if a battery system is present

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Feature

Power Loss Control

AT Shutdown Mode

UEFI Fast Boot

SATA Support

Options

Remain Off

Turn On

Last State

System Reboot

Hot S5

Disabled

Enabled

Last Boot HDD Only

All SATA Devices

Auto

UEFI Driver

Description

Set the mode of operation if an AC power loss occurs:

‘Remain Off’ - Keeps the power off until the power button is pressed

‘Turn On’ - Restores power to the computer

‘Last State’ - Restores the power state before power loss occurred

Note: This feature only works with an ATX type power supply

Set the behavior of an AT-powered system after a shutdown

Enable to boot with a minimum set of devices

Note: This feature has no effect for BBS / legacy boot options

Select SATA support

VGA Support

USB Support

PS/2 Device Support

Network Stack Driver Support

Redirection Support

UEFI Screenshot Capability

Disabled

Full Init

Partial Init

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

‘Auto’ - Installs legacy video option ROM for legacy operating system boot

Note: The boot logo will not be displayed during POST

‘UEFI Driver’ - Installs UEFI GOP driver

‘Disabled’ - The USB devices will not be available before operating system boot.

‘Full Init’ - All USB devices will be available during POST and after operating system boot

‘Partial Init’ - Specific USB ports/devices will not be available before operating system boot

Disable to skip PS/2 devices

Disable to skip the UEFI network stack driver installation

Disable to deactivate the Redirection function

Enable this feature to take a screenshots from the current screen by pressing LCtrl+LAlt+F12.

The image will be saved as PNG on the first writable FAT32 partition found

Note

1. The term ‘AC power loss’ stands for the state when the module looses the standby voltage on the 5V_SB pins. On congatec modules, the standby voltage is continuously monitored after the system is turned off. If the standby voltage is not detected within 30 seconds, this is considered an AC power loss condition. If the standby voltage remains stable for 30 seconds, it is assumed that the system was switched off properly.

2. Inexpensive ATX power supplies often have problems with short AC power sags. When using these ATX power supplies it is possible that the system turns off but does not switch back on, even when the PS_ON# signal is asserted correctly by the module. In this case, the internal circuitry of the ATX power supply has become confused. Usually, another AC power off/on cycle is necessary to recover from this situation.

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11.8 Save & Exit Menu

Select the Save & Exit tab from the setup menu with the <Arrow> keys to enter the Save & Exit setup screen.

Feature

Save Changes and Exit

Discard Changes and Exit

Save Changes and Reset

Discard Changes and Reset

Description

Exit setup menu after saving the changes. The system is only reset if settings have been changed

Exit setup menu without saving any changes

Save changes and reset the system

Reset the system without saving any changes

Save Options

Save Changes

Discard Changes

Save changes made so far to any of the setup options. Stay in setup menu

Discard changes made so far to any of the setup options. Stay in setup menu

Restore Defaults

► Generate Menu Layout File

Boot Override

Restore default values for all the setup options

Setup menu layout file will be generated and stored on the first writable file system found

List of all boot devices currently detected Select device to leave setup menu and boot from the selected device. Only visible and active if Boot Priority Selection setup node is set to “Device Based”

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12 Additional BIOS Features

The BIOS setup description of the conga-TS170 can be viewed without having access to the module. However, access to the restricted area of the congatec website is required in order to download the necessary tool (CgMlfViewer) and Menu Layout File (MLF).

The MLF contains the BIOS setup description of a particular BIOS revision. The MLF can be viewed with the CgMlfViewer tool. This tool offers a search function to quickly check for supported BIOS features. It also shows where each feature can be found in the BIOS setup menu.

For more information, read the application note “AN42 - BIOS Setup Description” available at www.congatec.com.

Note

If you do not have access to the restricted area of the congatec website, contact your local congatec sales representative.

12.1 BIOS Versions

The BIOS displays the BIOS project name and the revision code during POST, and on the main setup screen. The initial production BIOS for conga-TS170 is identified as

The BIOS displays a message during POST and on the main setup screen identifying the BIOS project name and a revision code. The initial production BIOS is identified as BQSLR1xx or BHSLR1xx for conga-TS170, where:

• R is the identifier for a BIOS ROM file,

• 1 is the so called feature number and

• xx is the major and minor revision number.

The BQSL binary size is 16 MB and the BHSL binary size is 8 MB.

12.2 Updating the BIOS

BIOS updates are recommeded to correct platform issues or enhance the feature set of the module. The conga-TS170 features a congatec/AMI

AptioEFI firmware on an onboard flash ROM chip. You can update the firmware with the congatec System Utility. The utility has five versions—

UEFI shell, DOS based command line 1 , Win32 command line, Win32 GUI, and Linux version.

For more information about “Updating the BIOS” refer to the user’s guide for the congatec System Utility “CGUTLm1x.pdf” on the congatec website at www.congatec.com.

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Note

1. Deprecated

Caution

The DOS command line tool is not officially supported by congatec and therefore not recommended for critical tasks such as firmware updates. We recommend to use only the UEFI shell for critical updates.

12.3 Supported Flash Devices

The conga-TS170 supports the following flash devices:

• Winbond W25Q128JVSIQ (16 MB)

• Winbond W25Q64JVSSIQ (8 MB)

The flash devices listed above can be used on the carrier board for external BIOS support. For more information about external BIOS support, refer to the Application Note AN7_External_BIOS_Update.pdf on the congatec website at http://www.congatec.com.

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