NXP P89C669FA P89C669FA Data Sheet

P89C669

80C51 8-bit microcontroller family with extended memory;

96 kB Flash with 2 kB RAM

Rev. 02 — 13 November 2003 Product data

1.

General description

The P89C669 represents the first Flash microcontroller based on Philips

Semiconductors’ new 51MX core. The P89C669 features 96 kbytes of Flash program memory and 2 kbytes of data SRAM. In addition, this device is equipped with a

Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs and byte based I 2 C-bus serial interface.

Philips Semiconductors’ 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices.

The linear address range of the 51MX has been expanded to support up to 8 Mbytes of program memory and 8 Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use 80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits (ASICs).

The P89C669 provides greater functionality, increased performance and overall lower system cost. By offering an embedded memory solution combined with the enhancements to manage the memory extension, the P89C669 eliminates the need for software work-arounds. The increased program memory enables design engineers to develop more complex programs in a high-level language like C, for example, without struggling to contain the program within the traditional 64 kbytes of program memory. These enhancements also greatly improve C Language efficiency for code size below 64 kbytes.

The P89C669 device contains a non-volatile Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable.

In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. A default serial loader (boot loader) program in ROM allows serial In-System programming of the

Flash memory via the UART without the need for a loader in the Flash code. For

In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM.

The 51MX core is described in more detail in the 51MX Architecture Reference.

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

2.

Features

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Product data

2.1 Key features

■ Extended features of the 51MX Core:

◆ 23-bit program memory space and 23-bit data memory space

◆ Linear program and data address range expanded to support up to 8 Mbytes each

◆ Program counter expanded to 23 bits

◆ Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation

◆ New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to access variables in different spaces

■ 100% binary compatibility with the classic 80C51 so that existing code is completely reusable

■ Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

■ 96 kbytes of on-chip program Flash

■ 2 kbytes of on-chip data RAM

■ Programmable Counter Array (PCA)

■ Two full-duplex enhanced UARTs

■ Byte based Fast I 2 C serial interface (400 kbits/s)

2.2 Key benefits

■ Increases program/data address range to 8 Mbytes each

■ Enhances performance and efficiency for C programs

■ Fully 80C51-compatible microcontroller

■ Provides seamless and compelling upgrade path from classic 80C51

■ Preserves 80C51 code base, investment/knowledge, and peripherals and ASICs

■ Supported by wide range of 80C51 development systems and programming tools vendors

■ The P89C669 makes it possible to develop applications at lower cost and with a reduced time-to-market

2.3 Complete features

■ Fully static

■ Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

■ 96 kbytes of on-chip Flash with In-System Programming (ISP) and In-Application

Programming (IAP) capability

■ 2 kbytes of on-chip RAM

■ 23-bit program memory space and 23-bit data memory space

■ Four-level interrupt priority

■ 32 I/O lines (4 ports)

■ Three Timers: Timer0, Timer1 and Timer2

■ Two full-duplex enhanced UARTs with baud rate generator

Rev. 02 — 13 November 2003

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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P89C669


■ Byte based Fast I 2 C-bus serial interface (400 kbits/s)

■ Framing error detection

■ Automatic address recognition

■ Power control modes

■ Clock can be stopped and resumed

■ Idle mode

■ Power-down mode

■ Second DPTR register

■ Asynchronous port reset

■ Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five

Capture/Compare modules

■ Low EMI (inhibit ALE)

■ Watchdog timer with programmable prescaler for different time ranges

(compatible with 8xC66x with added prescaler)

3.

Ordering information

Table 1: Ordering information

Type number Package

Name Description

P89C669FA PLCC44 plastic leaded chip carrier; 44 leads

P89C669BBD LQFP44 plastic low profile quad flat package; 44 leads; body 10

×

10

×

1.4 mm

Version

SOT187-2

SOT389-1

3.1 Ordering options

Table 2: Ordering options

Type number Memory Temperature range V

DD

voltage range

OTP RAM

P89C669FA 96 kB 2048 B

−

40

°

C to +85

°

C

P89C669BBD 96 kB 2048 B 0

°

C to +70

°

C

4.5 to 5.5 V

4.5 to 5.5 V

Frequency

0 to 24 MHz

0 to 24 MHz

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Product data Rev. 02 — 13 November 2003


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4.

Block diagram

CRYSTAL OR

RESONATOR

96 kB

CODE FLASH

HIGH PERFORMANCE

80C51 CPU

UART 0 internal bus

2 kB

DATA RAM

BAUD RATE

GENERATOR

PORT 3

PORT 2

UART 1

TIMER 0

TIMER 1

PORT 1

PORT 0

OSCILLATOR

WATCHDOG TIMER

PCA (PROGRAMMABLE

COUNTER ARRAY)

TIMER2

I2C

P89C669


Fig 1.

Block diagram.

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Product data

002aaa405

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5.

Functional diagram

P89C669


VDD VSS

Address bus 0-7

Data Bus

RXD0

TXD0

INT0

INT1

CEX3/T0

CEX4/T1

WR

RD

RXD1

TXD1

RST

EA/VPP

PSEN

ALE/PROG

Fig 2.

Functional diagram.

P89C669

XTAL2

XTAL1

002aaa403

T2

T2EX

ECI

CEX0

CEX1

CEX2

SCL

SDA

Address Bus 16-22

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P89C669


6.

Pinning information

6.1 Pinning

6.1.1

Plastic leaded chip carrier

P1.5/CEX2 7

P1.6/SCL 8

P1.7/SDA 9

RST 10

P3.0/RXD0 11

RXD1 12

P3.1/TXD0 13

P3.2/INT0 14

P3.3/INT1 15

P3.4/CEX3/T0 16

P3.5/CEX4/T1 17

Fig 3.

PLCC44 pin configuration.

P89C669FA

39 P0.4/AD4

38 P0.5/AD5

37 P0.6/AD6

36 P0.7/AD7

35 EA/VPP

34 TXD1

33 ALE

32 PSEN

31 P2.7/A15

30 P2.6/A14/A22

29 P2.5/A13/A21

002aaa404

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P89C669


6.1.2

Plastic low profile quad flat package

P1.5/CEX2 1

P1.6/SCL 2

P1.7/SDA 3

RST 4

P3.0/RXD0 5

RXD1 6

P3.1/TXD0 7

P3.2/INT0 8

P3.3/INT1 9

P3.4/CEX3/T0 10

P3.5/CEX4/T1 11

Fig 4.

LQFP44 pin configuration.

P89C669BBD

33 P0.4/AD4

32 P0.5/AD5

31 P0.6/AD6

30 P0.7/AD7

29 EA/VPP

28 TXD1

27 ALE

26 PSEN

25 P2.7/A15

24 P2.6/A14/A22

23 P2.5/A13/A21

002aaa406

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P89C669


6.2 Pin description

Table 3: Pin description

Symbol Pin

PLCC LQFP

Type

P0.0 - P0.7

43 - 36 30 - 37 I/O

Description

P1.0 - P1.7

2 - 9

2

3

4

5

6

7

8

9

1 - 3,

40 - 44

I/O

40

41

42

43

44

1

2

3

I

I

I/O

I/O

I/O

I/O

I/O

I/O

P2.0 - P2.7

24 - 31 18 - 25 I/O

Port 0: Port 0 is an open drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s.

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins.

Port 1 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled LOW will source current because of the internal pull-ups.

•

P1.0, T2

– Timer/Counter 2 external count input/Clock out

•

P1.1, T2EX

– Timer/Counter 2 Reload/Capture/Direction Control

•

P1.2, ECI

– External Clock Input to the PCA

•

P1.3, CEX0

– Capture/Compare External I/O for PCA module 0

•

P1.4, CEX1

– Capture/Compare External I/O for PCA module 1 (with pull-up on pin)

•

P1.5, CEX2

– Capture/Compare External I/O for PCA module 2 (with pull-up on pin)

•

P1.6, SCL

– I 2 C serial clock (when I 2 C is used, this pin is open-drain and requires external pull-up due to I 2 C-bus specification)

•

P1.7, SDA

– I 2 C serial data (when I 2 C is used, this pin is open-drain and requires external pull-up due to I 2 C-bus specification)

Port 2: Port 2 is a 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled LOW will source current because of the internal pull-ups. (See

Section 9 “Static characteristics”

, I

IL

). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR) or 23-bit addresses (MOVX @EPTR,

EMOV). In this application, it uses strong internal pull-ups when emitting 1s.

During accesses to external data memory that use 8-bit addresses (MOV @ Ri), port 2 emits the contents of the P2 Special Function Register.

Note that when 23-bit address is used, address bits A16-A22 will be outputted to

P2.0-P2.6 when ALE is HIGH, and address bits A8-A14 are outputted to

P2.0-P2.6 when ALE is LOW. Address bit A15 is outputted on P2.7 regardless of

ALE.

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P89C669


Table 3: Pin description …continued

Symbol Pin Type

PLCC LQFP

P3.0 - P3.7

11,

13 - 19

5,

7 - 13

I/O

RXD1

TXD1

RST

ALE

PSEN

EA/V

PP

XTAL1

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Product data

11

13

14

15

16

17

18

19

12

34

10

33

32

35

21

5

7

8

9

10

11

12

13

6

28

4

27

26

29

15 I

I

I

I

I

I

I

I

I

O

O

O

O

O

O

Description

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled LOW will source current because of the internal pull-ups.

•

P3.0, RXD0

– Serial input port 0

•

P3.1, TXD0

– Serial output port 0

•

P3.2, INT0

– External interrupt 0

•

P3.3, INT1

– External interrupt 1

•

P3.4, T0/CEX3

– Timer0 external input/capture/compare external I/O for PCA module 3

•

P3.5, T1/CEX4

– Timer1 external input/capture/compare external I/O for PCA module 3

•

P3.6, WR

– External data memory write strobe

•

P3.7, RD

– External data memory read strobe

•

RXD1

– Serial input port 1 (with pull-up on pin)

•

TXD1

– Serial output port 1 (with pull-up on pin)

Reset: A HIGH on this pin for two machine cycles, while the oscillator is running, resets the device. An internal diffused resistor to V

SS

permits a power-on reset using only an external capacitor to V

DD

.

Address Latch Enable: Output pulse for latching the LOW byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1

⁄

6

the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR AUXR.0. With this bit is set,

ALE will be active only during a MOVX instruction.

Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.

External Access Enable/Programming Supply Voltage: EA must be externally held LOW to enable the device to fetch code from external program memory locations. If EA is held HIGH, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

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P89C669


Table 3: Pin description …continued

Symbol Pin Type

XTAL2

V

SS

V

DD

PLCC LQFP

20 14

22

44

16

38 I

I

O

(NC/V

(NC/V

SS

DD

)

)

1

23

39

17 I

I

Description

Crystal 2: Output from the inverting oscillator amplifier.

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as

Idle and Power-down modes.

No Connect/Ground: This pin is internally connected to V

SS on the P89C669. If connected externally, this pin must only be connected to the same V

SS

as at pin 22. (Note: Connecting the second pair of V

SS

and V

DD

pins is not required.

However, they may be connected in addition to the primary V

SS

and V

DD

pins to improve power distribution, reduce noise in output signals, and improve system-level EMI characteristics.)

No Connect/Power Supply: This pin is internally connected to V

DD

on the

P89C669. If connected externally, this pin must only be connected to the same

V

DD

as at pin 44. (Note: Connecting the second pair of V

SS

and V

DD

pins is not required. However, they may be connected in addition to the primary V

SS

and

V

DD

pins to improve power distribution, reduce noise in output signals, and improve system-level EMI characteristics.)

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P89C669


7.

Functional description

7.1 Flash memory description

The P89C669 contains 96 kbytes of Flash program memory. It is organized as

12 separate blocks, each block containing 8 kbytes.

The P89C669 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip

Erase operation will erase the entire program memory. The Block Erase function can erase any Flash byte block. In-system programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface. The P89C669 Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The P89C669 uses a +5 V V

PP supply to perform the Program/Erase algorithms.

• Flash internal program memory with Block Erase.

• Internal 4 kbytes Boot Flash, containing low-level in-system programming routines and a default UART loader. User program can call these routines to perform

In-Application Programming (IAP). The BootFlash can be turned off to provide access to the full 8 Mbytes memory space.

• Boot vector allows user provided Flash loader code to reside anywhere in the

Flash memory space. This configuration provides flexibility to the user.

• Default loader in BootFlash allows programming via the UART interface without the need for a user provided loader.

• Up to 8 Mbytes of external program memory if the internal program memory is disabled (EA = 0).

• +5 V programming and erase voltage.

• Read/Programming/Erase using ISP/IAP:

– Byte Programming (20

µ s).

– Typical quick erase times (including preprogramming time):

– Block Erase (8 kbytes) in 1 second.

– Full Erase (96 kbytes) in 1 second.

• Parallel programming with 87C51-like hardware interface to programmer.

• Programmable security for the code in the Flash.

• 10,000 minimum erase/program cycles for each byte.

• 10 year minimum data retention.

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P89C669


7.2 Memory arrangement

P89C669 has 96 kbytes of Flash (MX universal map range: 80:0000-81:7FFF) and

2 kbytes of on-chip RAM:

Table 4: Memory arrangement

Data memory

Type

DATA

Description memory that can be addressed both directly and indirectly; can be used as stack

Size (Bytes) and MX universal memory map range

P89C669

128

(7F:0000-7F:007F)

256

(7F:0000-7F:00FF)

IDATA superset of DATA; memory that can be addressed indirectly (where direct address for upper half is for SFR only); can be used as stack

EDATA superset of DATA/IDATA; memory that can be addressed indirectly using Universal Pointers (PR0,1); can be used as stack

XDATA memory (on-chip ‘External Data’) that is accessed via the MOVX/EMOV instructions using DPTR/EPTR

1280

(7F:0000-7F:04FF)

768

(00:0000-00:02FF)

For more detailed information, please refer to the P89C669 User Manual.

7.3 Special function registers

Special Function Register (SFR) accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’, or ‘1’ can only be written and read as follows:

– ‘-’ must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Table 5: Special function registers

Name Description SFR addr.

Bit functions and addresses

MSB

Bit address E7 E6 E5 E4 E3 E2 E1

LSB

E0

Reset value

ACC [1]

AUXR [2]

AUXR1

[2]

Accumulator

Auxiliary Function Register

E0H

8EH -

Auxiliary Function Register 1 A2H -

Bit address F7

-

-

F6

-

ENBOOT -

F5 F4

-

GF2

F3

-

0

F2

EXTRAM AO

-

F1

DPS

F0

00H

00H

[6]

00H

[6]

B [1]

BRGCON

[2]

BRGR0 [2][5]

BRGR1 [2][5]

CCAP0H

[2]

CCAP1H

[2]

CCAP2H

[2]

CCAP3H

[2]

CCAP4H

[2]

CCAP0L [2]

CCAP1L [2]

CCAP2L [2]

CCAP3L [2]

CCAP4L [2]

CCAPM0

[2]

CCAPM1

[2]

CCAPM2

[2]

CCAPM3

[2]

CCAPM4

[2]

CCON

[1] [2]

CH [2]

CL

[2]

CMOD

[2]

B Register

Baud Rate Generator Control

F0H

85H

[3]

Baud Rate Generator Rate LOW 86H

[3]

Baud Rate Generator Rate HIGH 87H

[3]

Module 0 Capture HIGH





Module 0 Capture LOW





Module 0 Mode

Module 1 Mode

Module 2 Mode

Module 3 Mode

Module 4 Mode

PCA Counter Control

PCA Counter HIGH

PCA Counter LOW

PCA Counter Mode

FAH

FBH

FCH

FDH

FEH

EAH

EBH

ECH

EDH

EEH

DAH

DBH

DCH

DDH

D8H

F9H

E9H

D9H

-

-

-

-

-

DEH -

Bit address DF

CF

CIDL

-

XXH

XXH

ECOM_0 CAPP_0 CAPN_0 MAT_0 TOG_0 PWM_0 ECCF_0 00H

[6]


[6]


[6]


[6]


[6]

DE DD DC DB DA D9 D8

CR CCF4 CCF3 CCF2 CCF1 CCF0 00H

[6]

00H

WDTE -

-

-

-

-

-

CPS1

00H

S0BRGS BRGEN 00H

[6]

CPS0 ECF

00H

00H

[6]

XXH

XXH

XXH

XXH

XXH

XXH

XXH

XXH

00H

00H

[6]

DPTR Data Pointer (2 bytes) 00H

DPL

EPL [2]

EPM

[2]

EPH

[2]

I2ADR

I2CON

I2DAT

I2CLH xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 5: Special function registers …continued



MSB LSB

Reset value

DPH Data Pointer HIGH 83H 00H

I2CLL

I2STA

IEN0 [1]

IEN1 [1]

IP0

[1]

Data Pointer LOW

Extended Data Pointer LOW

Extended Data Pointer Middle

Extended Data Pointer HIGH

I 2 C Slave Address Register

I 2 C Control Register

I 2 C Data Register

I 2 C Clock Generator HIGH

Register

I 2 C Clock Generator LOW

Register

I 2 C Status Register

82H

FCH

[3]

FDH

[3]

FEH [3]

94H

91H

93H

96H

95H

addr.6

92H code.4

Bit address AF

Interrupt Enable 0 A8H EA

Interrupt Enable 1

Interrupt Priority

Bit address EF

E8H -

Bit address BF

B8H addr.5

I2EN code.3

AE

EC

-

EE

BE

PPC addr.4

STA code.2

AD

ET2

-

ED

BD

PT2 addr.3

STO code.1

AC

ES0/

ES0R

EC

EI2C addr.2

SI

-

EB

BB

PT1 addr.1

AA code.0

0

AB AA

ET1 EX1

EA

ES1T

BA

PX1

addr.0

0

A9

ET0

E9

ES0T

B9

PT0

00H

00H

00H

00H

GC 00H

CRSEL 00H

0

A8

EX0

E8

ES1/

ES1R

B8

PX0

00H

00H

F8H

00H

00H

[6]

00H

IP0H

IP1

[1]

Interrupt Priority 0 HIGH

Interrupt Priority 1

B7H -

Bit address FF

F8H -

PPCH

-

FE

PT2H

-

FD

BC

PS0/

PS0R

PS0H/

PS0RH

FC

PI2C

PT1H

-

FB

PX1H PT0H PX0H 00H

00H

[6]

IP1H

MXCON

[2]

Interrupt Priority 1 HIGH

MX Control Register

F7H

FFH

[3]

-

-

-

-

-

-

-

PI2CH

-

-

FA

PS1T

F9

PS0T

F8

PS1/

PS1R

PS1TH PS0TH PS1H/

PS1RH

EAM ESMM EIFM

00H

[6]

00H

[6]





MSB

Bit address 87 86 85 84 83 82 81

LSB

80

Reset value

P0 [1]

Port 0 80H AD7

Bit address 97

AD6

96

AD5

95

AD4

94

AD3

93

AD2

92

AD1

91

AD0

90

FFH

P1 [1]

Port 1 90H CEX4 CEX3 CEX2/

SPICLK

CEX1/

MOSI

CEX0 ECI T2EX T2 FFH

P2 [1]

Port 2

Bit address A7

A0H AD15 FFH

P3 [1]

PCON [2]

Port 3

Power Control Register

Bit address B7

B0H RD

87H SMOD1

A6

AD14/

AD22

A5

ADA13/

AD21

B6

WR

SMOD0 -

B5

T1

A4

AD12/

AD20

B4

T0

POF

A3

AD11/

AD19

B3

INT1

GF1

A2

AD10/

AD18

B2

INT0

GF0

A1

AD9/

AD17

B1

TxD0

PD

A0

AD8/

AD16

B0

RxD0

IDL

FFH

00H/

10H

[4]

PSW

[1]

Program Status Word

RCAP2H

[2]

Timer2 Capture HIGH

RCAP2L [2]

Timer2 Capture LOW

Bit address D7

D0H CY

CBH

CAH

D6

AC

D5

F0

D4

RS1

D3

RS0

D2

OV

S0CON [1]

Serial Port 0 Control

Bit address 9F

98H SM0_0/

FE_0

9E

SM1_0

9D

SM2_0

9C

REN_0

9B

TB8_0

9A

RB8_0

S0BUF Serial Port 0 Data Buffer

Register

Serial Port 0 Address Register

99H

S0ADDR A9H

S0ADEN Serial Port 0 Address Enable

S0STAT

[2]

Serial Port 0 Status

S1CON [1] [2]

Serial Port 1 Control

B9H

8CH [3]

DBMOD_0 INTLO_0 CIDIS_0 DBISEL_

0

Bit address 87

[3]

86

[3]

85

[3]

84

[3]

80H

[3]

SM0_1/

FE_1

SM1_1 SM2_1 REN_1

FE_0

83 [3]

TB8_1

BR_0

82

[3]

RB8_1

S1BUF [2]

Serial Port 1 Data buffer Register 81H

[3]

S1ADDR

[2]

Serial Port 1 Address Register 82H

[3]

D1

F1

99

TI_0

OE_0

81 [3]

TI_1

D0

P

98

RI_0

00H

00H

00H

00H

00H

STINT_0 00H

[6]

80

[3]

RI_1

00H xxH

00H

XXH

00H



Name

S1ADEN [2]

S1STAT

[2]

SP

Description

Serial Port 1 Address Enable

Serial Port 1 Status

Stack Pointer (Stack Pointer

LOW Byte)

SFR addr.

83H

[3]

84H

[3]

81H


MSB

DBMOD_1 INTLO_1 CIDIS_1 DBISEL1 FE_1 BR_1 OE_1

Reset value

LSB

00H

STINT_1 00H

[6]

07H

SPE [2]

Stack Pointer HIGH

FBH [3]

Bit address 8F 8E 8D 8C 8B 8A 89 88

00H

TCON

[1]

Timer Control Register 88H TF1

CF

TR1

CE

TF0

CD

TR0

CC

IE1

CB

IT1

CA

IE0

C9

IT0

C8

00H

T2CON

[1] [2]

Timer2 Control Register

T2MOD

[2]

Timer2 Mode Control

C8H

C9H -

TF2

-

EXF2

-

RCLK

-

TCLK

-

EXEN2 TR2

-

C/T2

T2OE

CP/RL2 00H

DCEN 00H

[6]

TH0

TH1

TH2

TL0

Timer 0 HIGH

Timer 1 HIGH

Timer 2 HIGH

Timer 0 LOW

TL1

TL2

Timer 1 LOW

Timer 2 LOW

TMOD Timer 0 and 1 Mode

WDTRST

[2]

Watchdog Timer Reset

WDCON [2]

Watchdog Timer Control

8CH

8DH

CDH

8AH

8BH

CCH

89H

A6H

8FH [3]

-

GATE

-

C/T

-

M1

-

M0

-

GATE

00H

00H

00H

00H

00H

00H

C/T M1 M0 00H

FFH

WDPRE2 WDPRE1 WDPRE0 00H

[6]

[1] SFRs are bit addressable.

[2] SFRs are modified from or added to the 80C51 SFRs.

[3] Extended SFRs accessed by preceding the instruction with MX escape (opcode A5h).

[4] Power-on reset is 10H. Other reset is 00H.

[5] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any of them is written if BRGEN = 1, result is unpredictable.

[6] The unimplemented bits (labeled ‘-’) in the SFRs are X’s (unknown) at all times. ‘1’s should NOT be written to these bits, as they may be used for other purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.


P89C669


7.4 Security bits

The P89C669 has security bits to protect users’ firmware codes. With none of the security bits programmed, the code in the program memory can be verified. When only security bit 1 (see

Table 6

) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. EA is latched on Reset and all further programming of EPROM is disabled.

When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.

Table 6: EPROM security bits

Security Bits

[1][2]

1

2

3

4

Bit 1

U

P

P

P

Bit 2

U

U

P

P

Bit 3

U

U

U

P

Protection description

No program security features enabled. Flash is programmable and verifiable.

MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the

EPROM is disabled.

Same as 2, also verification is disabled.

Same as 3, external execution is disabled.

[1] P - programmed. U - unprogrammed.

[2] Any other combination of security bits is not defined.

8.

Limiting values

Table 7: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

I

T

T

V

I

P amb stg

I

, I

O operating temperature under bias storage temperature range input voltage on EA/V

PP

pin to V

SS input voltage on any other pin to V

SS maximum I

OL

per I/O pin power dissipation based on package heat transfer, not device power consumption

-

Min

0

−

40

−

65

-

0

−

0.5

Max

+70

+85

+150

+13

Unit

°

C

°

C

°

C

V

V

DD

+ 0.5

V

20 mA

1.5

W

[1] The following applies to the Limiting values: a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in

Section 9 “Static characteristics” and

Section 10 “Dynamic characteristics” of this specification is not implied.

b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

SS

unless otherwise noted.

9397 750 12299

Product data


17 of 33 Rev. 02 — 13 November 2003


P89C669


9.

Static characteristics

Table 8: DC electrical characteristics

T amb

= 0

°

C to

+

70

°

C for commercial, unless otherwise specified; V

DD

= 4.5 V to 5.5 V unless otherwise specified.

Symbol Parameter

V

IL

LOW-level input voltage

Conditions Min

−

0.5

-

Typ [1]

Max

0.2V

DD

−

0.1

V

IH

HIGH-level input voltage

(ports 0, 1, 2, 3, 4, EA)

0.2V

DD

+ 0.9 V

DD

+ 0.5

V

IH1

0.7V

DD

V

DD

+ 0.5

V

V

OL

OL1

HIGH-level input voltage,

XTAL1, RST

LOW-level output voltage, ports 1, 2, 3, 4

[8]

LOW-level output voltage, port 0, ALE, PSEN

[7][8]

V

V

DD

DD

= 4.5 V; I

= 4.5 V; I

OL

OL

= 1.6 mA

= 3.2 mA -

-

-

0.4

0.4

V

OH

V

DD

= 4.5 V; I

OH

=

−

30 A V

DD

−

0.7

-

V

OH1

HIGH-level output voltage, ports 1, 2, 3, 4

HIGH-level output voltage

(port 0 in external bus

mode), ALE [9]

, PSEN [3]

I

V

DD

OH

= 4.5 V;

=

−

3.2 mA

V

DD

−

0.7

-

I

IL

−

1 -

−

75

I

I

I

TL

L1

CC

R

C

RST

10

Logical 0 input current, ports 1, 2, 3, 4

V

IN

= 0.4 V

Logical 1-to-0 transition current, ports 1, 2, 3, 4

[8]

4.5 V < V

DD

< 5.5 V;

V

IN

= 2.0 V

Input leakage current, port 0 0.45 < V

IN

< V

DD

−

0.3

Power supply current

Active mode

[5]

Idle mode [5]

V

DD

= 5.5 V

Power-down mode or clock stopped (see

Figure 13

for conditions)

Internal reset pull-down resistor

Pin capacitance [10]

(except EA)

[4]

[5]

-

-

-

-

-

-

-

40

-

-

-

-

-

-

-

20

−

±

650

10

Unit

V

A

A

-

7 + 2.7

× f osc

[MHz] mA

4 + 1.3

× f osc

[MHz] mA

100

µ

A

225

15

V

V

V

V

V

V

µ

µ

µ

A k

Ω pF

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), 5 V, unless otherwise stated.

[2] Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

OL of ALE and ports 1, 3 and 4. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading >100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

OL

can exceed these

[3] conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

Capacitive loading on ports 0 and 2 may cause the V

OH on ALE and PSEN to momentarily fall below the V

DD

−

0.7 V specification when the address bits are stabilizing.

[4] Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from ‘1’ to ‘0’. The transition current reaches its maximum value when V

IN

is approximately 2 V for 4.5 V < V

DD

< 5.5 V.

[5] See

Figure 10

through

Figure 13 for I

CC

[6] This value applies to T amb test conditions. f

= 0

°

C to +70

°

C.

osc

is the oscillator frequency in MHz.

[7] Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

[8] Under steady state (non-transient) conditions, I

OL

must be externally limited as follows: a) Maximum I

OL

per port pin: 15 mA b) Maximum I

OL

per 8-bit port: 26 mA

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18 of 33


P89C669

80C51 8-bit microcontroller family with extended memory c) Maximum total I

OL

for all outputs: 71 mA

If I

OL

exceeds the test condition, V

OL

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

[9] ALE is tested to V

OH1

, except when ALE is off then V

OH is the voltage specification.

[10] Pin capacitance is characterized but not tested.

10. Dynamic characteristics

Table 9: AC electrical characteristics

T amb

= 0

°

C to +70

°

C for commercial unless otherwise specified. Formulae including t

50/50 duty cycle.

[1][2][3]

CLCL

assume oscillator signal with

Symbol Figure f

OSC t

CLCL t

LHLL t

AVLL t

LLAX t

LLIV t

LLPL t

PLPH t

PLIV t

PXIX t

PXIZ t

AVIV

5

5

5

5

5

5

5

5

5

5

5

5

,

,

6

6

,

,

7

7

Parameter

Oscillator frequency

Clock cycle

ALE pulse width

Address valid to ALE LOW

Address hold after ALE LOW

ALE LOW to valid instruction in

ALE LOW to PSEN LOW

PSEN pulse width

PSEN LOW to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

(non-Extended Addressing Mode)

-

-

-

-

-

4.5 V < V

DD

< 5.5 V

Variable clock

[4]

Min

0 t

CLCL

−

15

0.5t

CLCL

−

15

0.5t

CLCL

−

15

0.5t

CLCL

−

12

1.5t

CLCL

−

20

0

-

-

-

-

-

-

Max

24

2t

CLCL

−

30

1.5t

CLCL

−

35 f

5

5

8

-

0.5t

CLCL

−

5

2.5t

CLCL

−

30 -

-

0

OSC

Min

41.5

26

42

= 24 MHz

-

-

-

-

-

-

-

-

Max

53

27

15

74

[4]

Unit

MHz ns ns ns ns ns ns ns ns ns ns ns t

AVIV1

5

Address (A16-A22) to valid instruction in (Extended Addressing Mode)

1.5t

CLCL

−

34 28 ns

PSEN LOW to address float 8 8 ns t

PLAZ

5

Data Memory

6

t

RLRH t

WLWH t

RLDV t

RHDX t

RHDZ t

LLDV t

AVDV

7

6

6

6

6

6

RD pulse width

WR pulse width

RD LOW to valid data in

Data hold after RD

Data float after RD

ALE LOW to valid data in

Address to valid data in (non-Extended

Addressing Mode)

-

-

-

-

3t

CLCL

−

20

3t

CLCL

−

20

0 -

-

-

2.5t

CLCL

−

40 t

CLCL

−

15

4t

CLCL

−

35

4.5t

CLCL

−

30 -

-

-

105

105

0 -

-

-

64

26

131

157 ns ns ns ns ns ns ns t

AVDV1

6

Address (A16-A22) to valid data in

(Extended Addressing Mode)

3.5t

CLCL

−

35 110 ns t t

LLWL

AVWL

6

6

,

,

7

7

ALE LOW to RD or WR LOW

Address valid to WR or RD LOW

(non-Extended Addressing Mode)

1.5t

CLCL

−

10

2t

CLCL

−

5 -

1.5t

CLCL

+ 20 52

78 -

82 ns ns t

AVWL1

6 ,

7

Address (A16-A22) valid to WR or RD

LOW (Extended Addressing Mode) t

CLCL

−

10 31 ns

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19 of 33


P89C669


Table 9: AC electrical characteristics …continued

T amb

= 0

°

C to +70

°

C for commercial unless otherwise specified. Formulae including t

50/50 duty cycle.

[1][2][3]

CLCL

assume oscillator signal with

Symbol Figure t

QVWX t

WHQX t

QVWH t

RLAZ

7

7

7

6

t

WHLH

6 ,

7

External Clock

Parameter

Data valid to WR transition

Data hold after WR

Data valid to WR HIGH

RD LOW to address float

RD or WR HIGH to ALE HIGH

4.5 V < V

DD

Min

0.5t

CLCL

−

15

0.5t

CLCL

−

11

3.5t

CLCL

−

10

-

0.5t

CLCL

−

11

< 5.5 V

Variable clock [4]

-

-

-

Max

0

0.5t

CLCL

+ 10

f

OSC

Min

5

9

135

9

= 24 MHz

-

-

-

Max

0

30

[4]

Unit ns ns ns ns ns t

CHCX t

CLCX

9

9

t

CLCH

9

t

CHCL

9

Shift Register

HIGH time

LOW time

Rise time

Fall Time

-

-

16

16 t

CLCL

− t

CLCX t

CLCL

− t

CHCX

4

4

-

-

16

16 -

-

4

4 ns ns ns ns t

XLXL t

QVXH t

XHQX t

XHDX t

XHDV

8

8

8

8

8

Serial port clock cycle time 6t

CLCL

Output data set-up to clock rising edge 5t

CLCL

−

10

Output data hold after clock rising edge t

CLCL

−

15

Input data hold after clock rising edge

Clock rising edge to input data valid -

0 -

-

-

-

5t

CLCL

−

35 -

250

198

26

0 -

-

-

-

173 ns ns ns ns ns

[1] Parameters are valid over operating temperature range unless otherwise specified.


[3] Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

[4] Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.

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20 of 33


P89C669


Table 10: I 2 C-bus interface characteristics

Symbol Parameter Conditions t t

HD;STA t

LOW t

HIGH t

RC t

FC t

SU;DAT1 t

SU;DAT2 t

SU;DAT3 t

HD;DAT t

SU;STA

SU;STO t

BUF t

RD t

FD

START condition hold time

SCL LOW time

SCL HIGH time

SCL rise time

SCL fall time

Data set-up time

SDA set-up time

SDA set-up time

Data hold time

Repeated START set-up time

STOP condition set-up time

Bus free time

SDA rise time

SDA fall time before repeated START condition before STOP condition

Input

≥

7t

CLCL

≥

8t

CLCL

≥

7t

CLCL

≤

1

µ s

≤

0.3

µ s

≥

250 ns

≥

250 ns

≥

250 ns

≥

0 ns

≥

7t

CLCL

≥

7t

CLCL

≥

7t

CLCL

≤

1

µ s

≤

300 ns

-

-

Output

> 4.0

µ s

> 4.7

µ s

> 4.0

µ s

< 0.3

µ s

> 10t

CLCL

− t

RD

> 1

µ s

> 4t

CLCL

> 4t

CLCL

- t

FC

> 4.7

µ s

> 4.0

> 4.7

< 0.3

µ

µ

µ s s s

[1] Parameters are valid over operating temperature range unless otherwise specified.


[3] Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

[4] Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.

10.1 Explanation of AC symbols

Each timing symbol has five characters. The first character is always ‘t’ ( = time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are:

A — Address

C — Clock

D — Input data

H — Logic level HIGH

I — Instruction (program memory contents)

L — Logic level LOW, or ALE

P — PSEN

Q — Output data

R — RD signal

t — Time

V — Valid

W — WR signal

X — No longer a valid logic level

Z — Float

9397 750 12299



21 of 33


P89C669


Examples: t

AVLL

— Time for address valid to ALE LOW.

t

LLPL

— Time for ALE LOW to PSEN LOW.

10.2 Timing diagrams tLHLL

ALE

PSEN

PORT 0

PORT 2 tLLPL tAVLL tLLAX

A0-A7 tPLPH tLLIV tPLIV tPLAZ tPXIX

INSTR IN tAVIV tAVIV1

P2.0-P2.7 OR A8-A15

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

Fig 5.

External program memory read cycle.

tPXIZ

A0-A7

002aaa150

ALE

PSEN tLLDV tLLWL tRLRH

RD tLLAX tAVLL tRLAZ tRLDV

PORT 0

A0-A7 tAVWL

PORT 2

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

Fig 6.

External data memory read cycle.

tAVDV tAVWL1 tAVDV1

P2.0-P2.7 OR A8-A15 tRHDX

DATA in tWHLH tRHDZ

A0-A7 FROM PCL

INSTR IN

002aaa151

9397 750 12299



22 of 33


P89C669


ALE

PSEN tLLWL tWLWH

WR tLLAX tAVLL tQVWX

PORT 0

A0-A7 tQVWH

DATA OUT tAVWL1 tAVWL

PORT 2

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

Fig 7.

External data memory write cycle.

P2.0-P2.7 OR A8-A15 tWHLH tWHQX

A0-A7 FROM PCL

INSTR IN

002aaa153

INSTRUCTION 0 1 2 3 4 5 6 7 8

ALE tXLXL

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI tQVXH tXHQX

0 1 tXHDV

VALID VALID

2 tXHDX

VALID

3 4 5 6

VALID VALID VALID VALID

7

SET TI

VALID

SET RI

002aaa155

Fig 8.

Shift register mode timing.

9397 750 12299



23 of 33


P89C669


VDD -0.5 V

0.45 V

0.7 VDD

0.2 VDD -0.1 V tCHCL tCLCX tCHCX tCLCL tCLCH

002aaa160

Fig 9.

External clock drive.

11. Test information

VDD

RST VDD

ICC

VDD

VDD

P0

EA

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

VSS

002aaa161

Fig 10. I

CC

test condition, active mode (all other pins are disconnected).

RST VDD

ICC

VDD

VDD

P0

EA

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

VSS

002aaa162

Fig 11. I

CC

test condition, idle mode (all other pins are disconnected).

9397 750 12299



24 of 33


P89C669


VDD -0.5 V

0.45 V

0.7 VDD

0.2 VDD -0.1 V tCHCL tCLCX tCHCX tCLCL tCLCH

Fig 12. Clock signal waveform for I

CC

tests in active and idle modes

(t

CLCH

= t

CHCL

= 5 ns).

002aaa163

RST VDD

ICC

VDD

VDD

P0

EA

(NC)

XTAL2

XTAL1

VSS

002aaa164

Fig 13. I

CC

test condition, power-down mode (all other pins are disconnected,

V

DD

= 2.0 V to 5.5 V).

9397 750 12299



25 of 33


12. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

P89C669


SOT187-2 e

D e

E y

39

X

29

28

Z E

A b p

40 b

1 w M

44

1 E H

E pin 1 index e

A

A

4

A

1

β k

6

7 e

18

17

Z D v M A

B v M B detail X

L p

D

H

D

0 5 scale

10 mm

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

UNIT A

A1 min.

A3

A4 max.

bp b1 D

(1)

E

(1) e eD eE HD HE mm

4.57

4.19

0.51

inches

0.180

0.165

0.02

0.25

0.01

3.05

0.12

0.53

0.33

0.81

0.66

16.66

16.51

16.66

16.51

1.27

0.021

0.013

0.032

0.026

0.656

0.650

0.656

0.650

0.05

16.00

14.99

16.00

14.99

17.65

17.40

17.65

17.40

0.63

0.59

0.63

0.59

k

1.22

1.07

Lp

1.44

1.02

v

0.18

w

0.18

y

0.1

ZD

(1) max.

2.16

ZE

(1) max.

2.16

β

0.695

0.685

0.695

0.685

0.048

0.042

0.057

0.040

0.007

0.007 0.004

0.085

0.085

45 o

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE

VERSION

SOT187-2

IEC

112E10

REFERENCES

JEDEC JEITA

MS-018 EDR-7319

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27

01-11-14

Fig 14. SOT187-2.

9397 750 12299



26 of 33


P89C669


LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1 y

X

A

34

33

23

22 ZE e

E H

E

44

1 pin 1 index e w M b p bp

D

H

D w M

11

12

ZD

B v M A v M B c

A A

2

A

1 detail X

L

Lp

θ

0 2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c mm 1.6

0.15

0.05

1.45

1.35

0.25

0.45

0.30

0.20

0.12

D

(1)

E

(1)

10.1

9.9

10.1

9.9

e

0.8

H

D

H

E

12.15

11.85

12.15

11.85

L

1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

SOT389-1

IEC

136E08

REFERENCES

JEDEC JEITA

MS-026

L p

0.75

0.45

v

0.2

w

0.2

y

0.1

Z

D

(1)

Z

E

(1)

1.14

0.85

1.14

0.85

θ

7 o

0 o

EUROPEAN

PROJECTION

ISSUE DATE

00-01-19

02-06-07

Fig 15. SOT389-1.

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P89C669


13. Soldering

9397 750 12299

Product data

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended.

13.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 270

°

C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:

• below 225

°

C (SnPb process) or below 245

°

C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness

≥

2.5 mm

– for packages with a thickness < 2.5 mm and a volume

≥

350 mm 3 so called thick/large packages.

• below 240

°

C (SnPb process) or below 260

°

C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

Rev. 02 — 13 November 2003


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9397 750 12299

Product data

P89C669


• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45

°

angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250

°

C or

265

°

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

13.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300

°

C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320

°

C.

13.5 Package related soldering information

Table 11: Suitability of surface mount IC packages for wave and reflow soldering methods

Package [1] Soldering method

Wave Reflow [2]

BGA, HTSSON..T

[3] , LBGA, LFBGA, SQFP,

SSOP..T

[3] , TFBGA, USON, VFBGA not suitable suitable not suitable [4] suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

PLCC [5] , SO, SOJ suitable

LQFP, QFP, TQFP

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L

[8] , PMFP [9] , WQCCN..L

[8] suitable not recommended [5][6] not recommended [7] not suitable suitable suitable not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales office.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

Rev. 02 — 13 November 2003


29 of 33


P89C669


[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217

°

C

±

10

°

C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45

°

angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

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P89C669


14. Revision history

Table 12: Revision history

Rev Date CPCN

02 20031113 -

01 20030508 -

Description

Product data (9397 750 12299); ECN 853-2422 01-A14403 of 6 November 2003

•

Figure 6 “External data memory read cycle.” on page 22 ; adjusted drawing.

Product data (9397 750 11359); ECN 853-2422 29812 of 14 April 2003

9397 750 12299



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P89C669


15. Data sheet status

I

Level Data sheet status

II

III

Objective data

Preliminary data

Product data

[1]

Product status

Development

Qualification

Production

[2][3]

Definition

This data sheet contains data from the objective specification for product development. Philips

Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process

Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

18. Licenses

17. Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors

Purchase of Philips I 2 C components

Purchase of Philips I

2

C components conveys a license under the Philips’ I 2 C patent to use the components in the

I

2

C system provided the system conforms to the I

2

C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales office addresses, send e-mail to: [email protected].

9397 750 12299


Fax: +31 40 27 24825


32 of 33


P89C669


16

17

18

13.2

13.3

13.4

13.5

14

15

Contents

7

7.1

7.2

7.3

7.4

6

6.1

6.1.1

6.1.2

6.2

8

9

10

10.1

10.2

1

4

5

2

2.1

2.2

2.3

3

3.1

11

12

13

13.1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Complete features . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

Pinning information . . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Plastic leaded chip carrier . . . . . . . . . . . . . . . . 6

Plastic low profile quad flat package. . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional description . . . . . . . . . . . . . . . . . . 11

Flash memory description . . . . . . . . . . . . . . . 11

Memory arrangement . . . . . . . . . . . . . . . . . . . 12

Special function registers . . . . . . . . . . . . . . . . 12

Security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Static characteristics. . . . . . . . . . . . . . . . . . . . 18

Dynamic characteristics . . . . . . . . . . . . . . . . . 19

Explanation of AC symbols . . . . . . . . . . . . . . . 21

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 22

Test information . . . . . . . . . . . . . . . . . . . . . . . . 24

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29

Package related soldering information . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 32

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

© Koninklijke Philips Electronics N.V. 2003.

Printed in the U.S.A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 13 November 2003 Document order number: 9397 750 12299

NXP P89C669FA P89C669FA Data Sheet

80C51 8-bit microcontroller family with extended memory;

96 kB Flash with 2 kB RAM

Rev. 02 — 13 November 2003 Product data

1.

General description

2.

Features

3.

Ordering information

4.

Block diagram

HIGH PERFORMANCE

80C51 CPU

5.

Functional diagram

6.

Pinning information

7.

Functional description

8.

Limiting values

9.

Static characteristics

10. Dynamic characteristics

11. Test information

12. Package outline

13. Soldering

14. Revision history

15. Data sheet status

16. Definitions

18. Licenses

17. Disclaimers

Contact information

Contents

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