Avionic Design Embedded Tegra K1 Processor Module User Manual
The Embedded Tegra K1 Processor Module is a multimedia platform for embedded, avionic and industrial operation. It has a very high graphic performance but it consumes little power. The module's core component is the NVIDIA Tegra K1 SoC. It supports various interfaces, like DSI, CSI, eDP, USB3.0, SATA (GEN2) and HDMI.
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User Manual
Embedded Tegra K1 processor module
All rights reserved
Product information
Product:
Product number:
Manufacturer:
In cooperation with:
Year:
Embedded Tegra K1 processor module
1477-110-000
Avionic Design GmbH
Wragekamp 10
22397 Hamburg
NVIDIA c
2014
Revision history
Document number Date
1477-011-315-01 23.06.2015
Version
01
Remarks first release
1477-011-315-00 26.01.2015
00 Preliminary release
Copyright
All the rights to this manual provided through this service revert to AVIONIC DESIGN GmbH.
Any and all reproduction, modification, or publication of the guides and/or manuals either in part or their entirety without the permission of AVIONIC DESIGN GmbH is prohibited under copyright laws.
NVIDIA, the NVIDIA logo and TEGRA are trademarks and/or registered trademarks of NVIDIA Corporation.
Other company and product names may be trademarks of the respective companies with which they are associated.
The Embedded Tegra K1 products are subject to change. Please check www.avionic-design.de
for updates.
1
Section 1 Document Change History
1 Document Change History
Table 1: Document Change History
Version Date Description
Rev01 23.06.2015
Meerkat Rev02 changes:
• Define X5:10 as W_Disable
• Change the VDDIO_GMI and VDDIO_BB voltage from 3.3V to 1.8V
(like on Jetson). The level of the following pins are affected:
− X4:2 (GPIO_PK3)
− X4:2 (GPIO_PK3)
− X4:3 (GPIO_PK1)
− X4:4 (GPIO_PI5)
− X4:5 (GPIO_PI7)
− X4:6 (GPIO_PH6)
− X4:7 (GPIO_PH5)
− X4:8 (GPIO_PK2)
− X4:9 (BL_EN)
− X4:10 (GPIO_PJ0)
− X4:11 (BL_PWM)
− X4:12 (FAN_PWM)
− X4:14 (GPIO_PK0)
− X4:18 (SPI4C_nCS1)
− X4:20 (GPIO_PH3)
− X4:22 (GPIO_PK4)
− X4:24 (GPIO_PI2)
− X4:35 (UART4_DEBUG_nCTS)
− X4:36 (GPIO_PJ2)
− X4:37 (UART4_DEBUG_TXD)
− X4:39 (UART4_DEBUG_nRTS)
− X4:41 (UART4_DEBUG_RXD)
− X4:43 (GEN2_I2C_nIRQ)
− X4:52 (HDMI_VDD_EN)
− X5:10 (W_DISABLE)
− X5:13 (GPIO_PO1)
− X5:18 (GPIO_PP2)
− X5:19 (GPIO_PO2)
− X5:21 (SPI1A_nIRQ)
− X5:23 (GPIO_PO3)
− X5:27 (GPIO_PO4)
− X5:45 (SPI1A_MISO)
− X5:47 (SPI1A_nCS0)
− X5:49 (SPI1A_SCK)
− X5:51 (SPI1A_MOSI)
− X5:53 (SPI4C_nCS0)
− X5:55 (SPI4C_MOSI)
− X5:57 (SPI4C_MISO)
− X5:59 (SPI4C_SCK)
• Add possible PCIe configurations
• Define default PCIe configuration
• Define GEN2 as default mini PCIe socket I2C bus
Avionic Design GmbH | Wragekamp 10 | 22397 Hamburg | Germany
T + 49(0)40 88 187-0 | F + 49(0)40 88 187-150 | [email protected] | www.avionic-design.de
2
Section 1 Document Change History
Version Date Description
• PCB Changes for Meerkat Rev02:
− add nWAKEUP_POWER pull-up (100k)
− add WAKEUP_LID pull-down (10k)
− add pull-down resistor for JTAG_TCK (100k)
− use LDO4 of the PMIC for AVDD_LVDS_PLL to support LVDS and eDP
− replace OWR with GPIO_PP0 (OWR is not supported by NVIDIA)
− add X3:42 GPIO_PBB4
− update the pinmux table (reference is the customer pinmux table from the Jetson reference board)
• NVIDIA does not officially support SPI2D and SPI3C
Rev00 26.01.2015
Draft release (Initial Release)
3
Avionic Design GmbH | Wragekamp 10 | 22397 Hamburg | Germany
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Contents
Purpose of this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Designated use of the COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of the COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Mechanical properties of the COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power management of the COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
eDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MIPI CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MIPI DSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4
Section Contents 5
4.10.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.10.2 Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.10.3 Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.11.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.11.2 Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.11.3 Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.12.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.12.2 Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.12.3 Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.13.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.13.2 Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.13.3 Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.14.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.14.2 Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.14.3 Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.15.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.15.2 Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.15.3 Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.16.1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.16.2 Example schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.16.3 Necessary layout properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
BCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Using tegra-uboot-flasher-scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Build cross-compiling toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Checkout required sources and utilities . . . . . . . . . . . . . . . . . . . . . . . . 54
Build required utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Build u-boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Flash u-boot to System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Connector overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Connector pinout and pin-muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . 11
Function block diagram of the COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Mechanical properties of the COM (top view) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Mechanical properties of the COM (bottom view) . . . . . . . . . . . . . . . . . . . . . . . 13
Mechanical properties of the COM (heatsink mounting points) . . . . . . . . . . . . . . . . 13
Power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DAP2 schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
HDMI schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PCI Express schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Mini PCI Express socket schematic example . . . . . . . . . . . . . . . . . . . . . . . . . 37
SDMMC schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
USB Client schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
head office in Duvenstedt (Germany) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6
List of Tables
1 Document Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Mechanical properties of the COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Absolute maximum operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Recommended operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8 DAP/I2S interface signal routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 embedded DisplayPort (eDP) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11 eDP (HBR2) main link signal routing requirements . . . . . . . . . . . . . . . . . . . . . . 22
16 HDMI interface signal routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 26
C bus-number assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
C GEN1 (1V8) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
C GEN2 (3V3) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
C CAM (1V8) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
22 HDMI DDC signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
31 PCIe: Clock and control signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
36 SATA interface signal routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 40
38 SDMMC1 (SDIO) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
39 SDMMC3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
40 SDMMC3/1 interface signal routing requirements . . . . . . . . . . . . . . . . . . . . . . . 42
41 SDMMC3/1 interface delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
50 UART4 (DEBUG) signals (1.8V level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7
Section List of Tables 8
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Section 2 Introduction
2 Introduction
9
Tegra
R R R technology. It defines the form factor, the pinout and the function set.
Please read all the information in this manual carefully!
If you have any questions about the Tegra
R
2.1
Purpose of this manual
This manual will give you information about the abilities and the interfaces of the Tegra
R module (COM). You will read about the production parameters and the operating conditions of the Tegra
R
K1 processor module so you will be able to operate it safely. This manual will enable you to develop a carrier that obeys the COM parameters.
This document includes an overview of the Tegra
R pinout of the board connectors. You will also get information about the power management of the Tegra
R
K1 processor module.
You will read about the interfaces of the Tegra
R
2.2
Designated use of the COM
The Tegra
R
Its core component is the NVIDIA
R
K1 processor.
The COM supports various interfaces, like DSI, CSI, eDP, USB3.0, SATA (GEN2) and HDMI.
Avionic Design GmbH | Wragekamp 10 | 22397 Hamburg | Germany
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Section 3 Properties of the COM
3 Properties of the COM
10
This chapter will give you information about the different properties of the Tegra
R as well as its compliance requirements and operating parameters.
3.1
Structure of the COM
In this section you will receive an overview of the Tegra
R
3.1.1
General overview
The Tegra
R
It has a very high graphic performance but it consumes little power (see Section 2.6). The hardware of the
Processor Module has a NVIDIA
R
K1 SoC as its core component.
The main properties of the CPU are:
• NVIDIA
R
K1 quad core:
– ARM
R
TM
-A15 “r3” with NVIDIA 4-Plus-1
TM
– FPU: ARM
R
TM
– L1 cache:
∗ 32 KB instruction cache for each core
∗ 32 KB data cache for each core
– L2 cache: 2 MB shared by all cores
– Operation frequency: up to 2.2 GHz
The properties of the COM memory are:
• 2GB DDR3L (64 Bit)
• 16 GB eMMC (eMMC5.0)
The Tegra
R
• 2 GB DDR3
• eMMC 16 GB (eMMC5.0)
• up to 2 x4 MIPI CSI
• up to 2 x4 MIPI DSI
• 1x eDP
• up to 5 PCIe lanes
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Section 3 Properties of the COM
• 2x standard USB 2.0 hosts
• 1x HSIC (shared with USB1)
• 1x standard USB 2.0 client (configurable as host)
• up to 2x USB 3.0 hosts
• 1x standard SATA
• 1x standard SDMMC (4 bit)
• 1x standard SDMMC/SDIO (4 bit)
• 2x DAP (I2S/PCM)
• 1x Debug UART
• 3x UART
• 2x standard I2C (1x 3.3 V and 1x 1.8 V)
• 4x SPI
• 8x 1.8V GPIOs
• 22x 3.3V GPIOs
• 1x JTAG
• 1x S/PDIF In/Out
• 1x standard HDMI 1.4b
The following figure will give you an overview of the Tegra
R
11
Figure 3.1: Top view of the Tegra
R
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Section 3 Properties of the COM
Explanation to :
1. DDR3L
2. PMU
3. Temperature sensor
4. eMMC
5. NVIDIA
R
K1 SoC
3.1.2
Function block diagram
Below you can find a function block diagram of the Tegra
R
12
Figure 3.2: Function block diagram of the COM
3.2
Mechanical properties of the COM
In this section you can find information about the mechanical properties of the Tegra
R ule. The diagram below shows the general layout of the processor board.
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Section 3 Properties of the COM
Figure 3.3: Mechanical properties of the COM (top view)
13
Figure 3.4: Mechanical properties of the COM (bottom view)
Figure 3.5: Mechanical properties of the COM (heatsink mounting points)
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Section 3 Properties of the COM
In the table below you can find a list of the mechanical properties of the Tegra
R
Parameter
Table 2: Mechanical properties of the COM
Properties
Size of the COM
Size of the NVIDIA
R
TM
70 x 50 mm
3 SoC 23 x 23 mm
Total PCB height
Maximum stacking height (top)
Maximum stacking height (bottom)
Weight connector type
Total pin count
5.70 mm
2 mm
2.3
18 g
DF12(3.0)-60DP-0.5V(86)
360
14
3.3
Operation parameters
In this section you can find a list of the maximum operation conditions for the Tegra
R
The module can operate under those conditions for a short time. If these operation conditions continue for an extended time, they could damage the module. You can find recommended operation conditions in Table
Please note:
• Stress above the ranges listed in Table 3 can permanently damage the Tegra
R module!
• Operate the Tegra
R
Absolute maximum operation conditions:
Parameter
Vmax +3V3_SYS
Vmax +5V_SYS
Table 3: Absolute maximum operation conditions
Explanation Min Max
Main 3.3 V power supply
Main 5 V power supply
-0.5 V
-0.5
3.63
7.0
Vmax VBAT_BKUP RTC backup battery voltage
Vmax PIN Voltage applied to powered I/O pins
0 V
-0.5
Vmax USB_VBUS USB supply voltage
5
3.63
-0.5 V 6.0 enabled
Operating temperature
Storage temperature
Storage humidity
-
Measured by a thermal diode
Relative humidity; in a sealed bag -
-25
-40
(0.5 not enabled)
105
125 less then 90
V
V
V
Unit
V
V
◦
C
◦
C
%
In the next table you will find the recommended operation parameters. It is safe to operate the module under these conditions.
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Section 3 Properties of the COM
Recommended operation conditions:
Parameter
+3V3_SYS
Table 4: Recommended operation conditions
Explanation Typical
Main 3.3 V power supply 3.3
Unit
V
+5V_SYS
Vmax_ PIN
VBAT_BKUP
USB_ VBUS
Power dissipation -
Main 5 V power supply 5
Voltage applied to powered I/O pins 3.3 or 1.8
RTC backup battery voltage
V
V
3 (max 3.6) V
USB supply voltage
Operating temperature Measured by a thermal diode
5
TBD
TBD
V
W
◦
C
15
3.4
Power management of the COM
The Tegra
R of the module is specified and it is necessary for the carrier board to follow these specifications so the module can power-up correctly.
3.4.1
Power sequence
To start the power sequence of the Tegra
R
+5V_SYS and +3V3_SYS. If both voltage are "Okay" the nPOWER_GOOD must pulled low (pull-up agains +5V_SYS are on the SoM). The Tegra
R ton: pull-up on the SoM agains 2V5_AON_RTC) or by pull low WAKEUP_nPOWER. After a fix delay the Tegra will release the nRESET_PERIPH signal, this indicates that the power for the external periphery can be powered (see power sequencing). It is necessary that the external periphery is not powered before the nRESET_PERIPH signal will be released. Otherwise the Tegra
R
produce unwanted behaviors. To autoboot the SoM see section 4.1.1. It is not necessary which power
(+5V_SYS or +3V3_SYS) will be powered first. The best is that both voltages will powered at the same time.
After the power sequence is complete, the boot ROM passes control to the system-dependent software.
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Section 4 Interfaces of the COM 16
4 Interfaces of the COM
Figure 3.6: Power sequence
In this chapter you will find information that will help you develop a carrier board for the Tegra
R processor module. The COM has a larger number of interfaces and some of these have specified layout properties. When you develop your own carrier, you need to obey these properties.
This chapter will give you examples of schematics for the interfaces and it will list the signals of the interfaces.
Please note:
• Read all the information in this chapter carefully, when you develop a carrier board!
• If you have any questions on how to develop your own carrier board, please contact Avionic
Design.
4.1
Tegra
R
Signal
+2V5_AON_RTC
USB0_ID_PMU
+1V8_VDDIO
+1V8_VDDIO nRESET_COM nPOWER_GOOD nRESET_PERIPH
+VBAT_BKUP
Table 5: Meerkat special functions
Pin Description I/O Comment
X6:26 Pull-up voltage
X6:33 TBD
X6:35 +1.8V power source
X6:36 +1.8V power source
P
P
P
I
X6:37 SoM reset signal
X6:38 power good signal
I (low active)
I (low active)
X6:39 periphery reset signal O (low active)
X6:40 PMU backup battery input P (2.5V - 3.6V)
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Section 4 Interfaces of the COM
Signal nONKEY nWAKEUP_POWER
WAKEUP_LID
Pin Description
X6:41 Power button
X6:43 power wakeup signal
X6:45 LID wakeup signal
FORCE_nRECOVERY X2:51 Force to recovery mode
PMU_GPIOA X6:47 PMU GPIO
PMU_GPIOB X6:49 PMU GPIO
I/O Comment
I
I (low active)
I (high active)
I (low active)
I/O
I/O
17
4.1.1
Signal descriptions
• +2V5_AON_RTC
This voltage rise after the PMU will be powered by the +5V_SYS. The +5V_SYS will be loaded after the nPOWER_GOOD signal will be set (low active). This voltage should be used to pull the nWAKEUP_POWER pin.
• USB0_ID_PMU
TBD
• +1V8_VDDIO
The signal +1V8_VDDIO is a power source which is powered by the PMU. The maximum current is
600 mA.
• nRESET_COM
This signal reset the PMU. It is pulled on the SoM against +2V5_AON_RTC (100k).
• nPOWER_GOOD
The power good signal (low active) indicate that the voltages +5V_SYS and +3V3_SYS are okay.
This signal can be connect to the power good outputs of the power supplies. Or it can also be connect to ground. This signal is pulled against +5V_SYS (100k).
• nRESET_PERIPH
This output is pulled against +1V8_VDDIO (10k) and indicate if the Tegra is powered. The signal should be used to unload all device which are connected to the SoM, otherwise reverse supply can happen.
• +VBAT_BKUP
This pin can be used for a RTC battery, but it can also be opened. The RTC backup battery can be loaded by the internal battery charger of the PMU to 2.5 V or to 3.0 V. In the power off mode the current should below 10 uA (supplier specification).
• nONKEY
This input can be used to start the PMU. The signal is low active and pulled on the SoM against
+2V5_AON_RTC (220k).
• nWAKEUP_POWER
This signal can also be used to start the PMU. The signal is low active and is pulled on the SoM with
100k against +2V5_AON_RTC.
Autoboot:
– if no "Power Off Mode" will be required, this signal can be connected to ground. In this case the PMU will be reseted instead of powered off, when a long press event is detected at the nONKEY signal.
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Section 4 Interfaces of the COM 18
– otherwise a reset chip should be used to generate the power on event. In this case the reset chip must generate a low level until the nPOWERGOOD is high plus minimum 210 ms.
• WAKEUP_LID
This signal is high active and can be used to leave the suspend mode, when the input is configured.
The suspend mode can also be leaved by the nWAKEUP_POWER event. The signal is pulled on the
SoM with 10k against ground.
• FORCE_nRECOVERY
If this signal is low at the power up, the Tegra will starts in recovery mode.
• PMU_GPIOA
Free usable GPIO from the PMU.
• PMU_GPIOB
Free usable GPIO from the PMU.
4.2
DAP (I
2
S)
The K1 processor module support up to two I2S interfaces (DAP2 and DAP4). The I2S Controller transports streaming audio data between system memory and an audio codec. The controller supports I2S format,
Left-justified Mode format, Right-justified Mode format, and DSP mode format, as defined in the Philips inter-IC-sound (I2S) bus specification. The I2S and PCM (master and slave modes) interfaces support clock rates up to 24.576 MHz.
The I2S controller supports point-to-point (P2P) serial interfaces for the I2S digital audio streams. I2Scompatible products, such as compact disc players, digital audio tape devices, digital sound processors and those with digital TV sound may be directly connected to the I2S controller. The controller also supports the PCM and telephony mode of data-transfer. Pulse-Code-Modulation (PCM) is a standard method used to digitize audio (particularly voice) patterns for transmission over digital communication channels. The
Telephony mode is used to transmit and receive data to and from an external mono CODEC in a slot-based scheme of time-division multiplexing. The I2S controller supports bidirectional audio streams and can operate in half-duplex or full-duplex mode.
Features:
• Basic I2S modes to be supported (I2S, RJM, LJM, and DSP) in both Master and Slave modes
• PCM mode with short (one-bit-clock-wide) and long-fsync (two bit-clocks wide) in both master and slave modes
• NW-mode with independent slot-selection for both TX and RX
• TDM mode with flexibility in number of slots and slot(s) selection
• Capability to drive-out a High-z outside the prescribed slot for transmission
• Flow control for the external input/output stream
• Support for u-Law and A-Law compression/decompression
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Section 4 Interfaces of the COM
4.2.1
Signals
Table 6: DAP2 signals
Signal
DAP2_DIN
Pin
DAP_MCLK1 X5:42 DAP master clock 1: External Peripheral 1
Clock: Connect to MCLK pin of the audio device if reference clock is required
X5:46
Description
Data In. DAP pins support I2S/PCM audio.
Interface can be master or slave
DAP2_DOUT X5:48 Data Out. DAP pins support I2S/PCM audio.
Interface can be master or slave
DAP2_FS X5:44 Frame Sync/Word Select. DAP pins support
I2S/PCM audio. Interface can be master or slave
DAP2_SCLK X5:50 Serial Clock/Bit Clock.
DAP pins support
I2S/PCM audio. Interface can be master or slave
I/O Comment
O
I
O
I/O
I/O
Table 7: DAP4 signals
Signal Pin Description
CLK3_OUT X4:50 Clock 3 out: External Peripheral 3 Clock:
Connect to MCLK pin of the audio device if reference clock is required Conntect to
MCLK if
DAP4_DIN X4:55 Data In. DAP pins support I2S/PCM audio.
Interface can be master or slave
DAP4_DOUT X4:57 Data Out. DAP pins support I2S/PCM audio.
Interface can be master or slave
DAP4_FS X4:53 Frame Sync/Word Select. DAP pins support
I2S/PCM audio. Interface can be master or slave
DAP4_SCLK X4:51 Serial Clock/Bit Clock.
DAP pins support
I2S/PCM audio. Interface can be master or slave
I/O Comment
O
I
O
I/O
I/O
19
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Section 4 Interfaces of the COM
4.2.2
Example schematic
Figure 4.1: DAP2 schematic example
4.2.3
Necessary layout properties
Parameter
Configuration / Device
Organization
Max loading
Topology
Table 8: DAP/I2S interface signal routing requirements
Reference plane
Breakout impedance region
Trace impedance
Via proximity (signal to reference)
Requirement
1
8
Point to Point
GND
Min width / spacing
50
< 3.8 (24)
Units Notes load pF
Ω
±20% mm (ps) Up to 4 signal vias can dielectric shared a single GND return via
Trace spacing (Microstrip
/Stripline)
Max trace delay
2x / 2x
3600 (∼555)
Max trace delay skew between SCLK &
SDATA_OUT/IN
250 (∼38) ps (mm) Include Package & PCB routing delays for max trace delays parameter ps (mm) Include Package & PCB routing delays for max trace delay skew parameter
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20
Section 4 Interfaces of the COM
Table 9: DAP/I2S interface delays
Signal Name Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
DAP2_DIN 69 169.5
238.5
DAP2_DOUT
DAP2_FS
61
78
158.9
200.3
219.9
278.3
DAP2_SCLK
DAP4_DIN
DAP4_DOUT
DAP4_FS
DAP4_SCLK
64
66
61
72
71
110.0
348.2
360.9
336.1
245.4
174.0
414.2
421.9
408.1
316.4
21
4.3
eDP
The Tegra K1 supports up to a 4-lane Embedded Display Port (eDP) interface. The maximum resolution supported with eDP is 3840x2160 @60fps.
• Embedded Display Port mode: interface will take in a clock frequency of 270 Mht (i.e. it will generate a 6x, 10x, and 20x high frequency clock (1.6 GHz for RBR, 2.7 GHz for HBR, and 5.4 GHz for
HBR2)).
4.3.1
Signals
Table 10: embedded DisplayPort (eDP) signals
Signal eDP_HPD eDP0_N eDP0_P eDP1_N eDP1_P eDP2_N eDP2_P
Pin
X1:10
Description eDP Hot Plug detect
X1:39 eDP data lane (negative)
X1:37 eDP data lane (positive)
X1:45 eDP data lane (negative)
X1:43 eDP data lane (positive)
X1:55 eDP data lane (negative)
X1:57 eDP data lane (positive) eDP3_N eDP3_P
X1:33
X1:31 eDP data lane (negative) eDP data lane (positive)
LVDS_TXD3_N X1:49 LVDS lane 3 (negative)
LVDS_TXD3_P X1:51 LVDS lane 3 (positive)
DP_AUX_CH0_N eDP Auxiliary Channel: Connect to
AUX_CH_N on the display connector
DP_AUX_CH0_P eDP Auxiliary Channel: Connect to
AUX_CH_P on the display connector
EN_LVDS_EDP X5:17 eDP enable signal
I/O Comment
I/O
O
O
O
O
O
O
O
O
O LVDS is not supported
O LVDS is not supported
O
O
O
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Section 4 Interfaces of the COM
4.3.2
Example schematic
Schematics follow soon
22
4.3.3
Necessary layout properties
Table 11: eDP (HBR2) main link signal routing requirements
Parameter
Max data rate (per data lane)
Min UI
Requirement
5.4
(HBR2) /
2.7 (HBR) / 1.62
(RBR)
185 (HBR2) / 370
(HBR) / 617 (RBR)
1
Units
Gbps ps
Notes
Number of loads
Topology load
Ω mm
Ω
Point to Point, Differential, unidirectional on die at TX / RX Termination
Max breakout PCB length
Trace impedance Diff / Single
Stripline Routing for Main Trunk
Max trace length from Tegra TX pin to connector
100
7.63
90 / 45-60
Max propagation delay - HBR2
Max number of signal vias
PCB pair-to-pair spacing
PCB main link to AUX spacing
Max stub length on the vias allowed
±15%
215 (RBR/HBR) /
165 (HBR2)
1137
4 (RBR, HBR) / 2
(HBR2)
3x
3x mm Max trace delays & max trace delays skew matching must include substrate pin delays unless otherwise specified ps
HBR2: one more test via right after AC cap OK dielectric height 3x of the thinner of above and below dielectric height 3x of the thinner of above and below
Rout below core to minimize stub length
Microstrip routing for main trunk
Max trace length from Tegra TX pin to connector
Max propagation delay HBR2 (5x / 7x spacing)
Max number of signal vias
PCB pair-to-pair spacing
PCB main link to AUX spacing
Signal skews (Stripline or Mircoline)
215 (RBR/HBR) /
127, 152.4 (HBR2
5x, 7x spacing)
750 / 900 mm ps
4 (RBR, HBR) / 2
(HBR2)
4x (RBR/HBR) /
5x-7x (HBR2)
5x dielectric height dielectric height
Max Trace Delay & Max
Trace Delay Skew matching must include substrate pin delays
150 ps/inch delay assumption for microstrip
HBR2: one more test via right after AC cap OK
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Section 4 Interfaces of the COM
Parameter
Max intra-pair (within pair) skew
Max inter-pair (pair-pair) skew
Requirement
1
150
Units ps ps
Notes
Table 12: eDP (LVDS) interface delays
Signal Name eDP0_N / (LVDS2_TX0N) eDP0_P / (LVDS2_TX0P) eDP1_N / (LVDS1_TX0N) eDP1_P / (LVDS1_TX0P) eDP2_N / (LVDS0_TX0N) eDP2_P / (LVDS0_TX0P) eDP3_N / (LVDS4_TX0N) eDP3_P / (LVDS4_TX0P)
/ (LVDS3_TX0N)
/ (LVDS3_TX0P)
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
30 137.2
167.2
30
44
137.2
134.5
167.2
178.5
45
50
51
38
134.5
134.8
134.8
134.9
179.5
184.8
185.8
172.9
38
46
47
134.9
134.5
134.5
172.9
180.5
181.5
23
4.4
GPIO
The Tegra processor GPIO controller provides the tools for configuring each MPIO for use as softwarecontrolled GPIO. Each GPIO is individually configurable as Output/Input/Interrupt sources with level/edge controls. The GPIO controller is divided into 8 banks. Each bank handles the GPIO functionality for up to 32
MPIOs. Within a bank, GPIOs are arranged as four ports of 8-bits each. The ports are labeled consecutively from A through Z and the AA through FF. Ports A through D are in bank 0. Ports E through H are in bank
1. There are 183 available GPIOs, but not all GPIOs are routed to the connectors. See the list below which
GPIOs are available:
4.4.1
Signals
Table 13: 1.8V GPIOs signals
Signal Pin
GPIO_PC7 X4:43
GPIO_PEE2 X5:39
GPIO_PH0 X4:12
GPIO_PH1 X4:52
GPIO_PH2 X4:11
GPIO_PH3 X4:20
GPIO_PH4 X4:9
GPIO_PH5 X4:7
GPIO_PH6 X4:6
GPIO_PI2
GPIO_PI4
X4:24
X4:18
GPIO_PI5
GPIO_PI7
X4:4
X4:5
Description I/O Comment
I/O GEN2_I2C_IRQ
I/O SATA_PWR_EN
I/O FAN_PWM
I/O HDMI_VDD_EN
I/O BL_PWM
I/O
I/O BL_EN
I/O
I/O
I/O
I/O SPI4C_nCS1
I/O
I/O
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Section 4 Interfaces of the COM
Signal
GPIO_PJ0
Pin
X4:10
GPIO_PJ2 X4:36
GPIO_PK0 X4:14
GPIO_PK1 X4:3
GPIO_PK2 X4:8
GPIO_PK3 X4:2
GPIO_PK4 X4:22
GPIO_PN2 X5:41
GPIO_PO1 X5:13
GPIO_PO2 X5:19
GPIO_PO3 X5:23
GPIO_PO4 X5:27
GPIO_PP0 X5:54
GPIO_PP1 X5:21
GPIO_PP2 X5:18
GPIO_PR0 X5:25
GPIO_PR2 X5:38
GPIO_PR4 X5:20
GPIO_PR5 X5:16
GPIO_PR6 X5:29
GPIO_PR7 X5:22
GPIO_PT0 X5:31
GPIO_PU1 X4:48
GPIO_PU5 X5:60
GPIO_PW2 X5:8
GPIO_PW3 X5:43
GPIO_PX3 X5:36
GPIO_PX5 X5:14
GPIO_PX6 X5:12
GPIO_PX7 X5:10
Description I/O Comment
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O SATA_LED
I/O SPI3E_MOSI
I/O SPI3E_MISO
I/O SPI3E_SCK
I/O SPI3E_nCS1
I/O
I/O SPI1A_nIRQ
I/O
I/O SDMMC3_VDD_EN
I/O AUDIO_EN
I/O
I/O
I/O
I/O HEAD_DET
I/O SOC_ALIVE
I/O SDMMC1_PWR_EN
I/O CODEC_nIRQ
I/O
I/O
I/O SPI2D_nIRQ
I/O GEN1_I2C_nIRQ
I/O
I/O
Table 14: 3.3V GPIOs signals
Signal Pin
GPIO_PK5 X5:56
GPIO_PK6 X5:58
Description I/O Comment
I/O SPDIF_OUT
I/O SPDIF_IN
4.4.2
Example schematic
No special schematics are required.
4.4.3
Necessary layout properties
It is necessary that all Inputs are not powered unit the Tegra is running.
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24
Section 4 Interfaces of the COM
4.5
HDMI
25
High-Definition Multimedia Interface (HDMI) support provides a unified method of transferring both audio and video data over a TMDS-compatible physical link to an audio/visual device. The HDMI block receives video from either display controller and audio from a separate high-definition audio (HDA) controller; it combines and transmits them as appropriate.
Features:
• High-definition Multimedia Interface (HDMI) specification 1.4b
• High-bandwidth Digital Content Protection (HDCP) system specification 1.4
• On-Chip HDCP key storage, no external SecureROM required
• TMDS (Transition Minimized Differential Signaling) PHY I/F
4.5.1
Signals
Table 15: HDMI signals
Signal
HDMI_CEC
Pin Description
X1:6 HDMI Consumer Electronics Control
HDMI_DDC_SCL X1:4 HDMI I2C clock
HDMI_DDC_SDA X1:2 HDMI I2C data
HDMI_INT
HDMI_TXC_N
HDMI_TXC_P
HDMI_TXD0_N
HDMI_TXD0_P
HDMI_TXD1_N
X1:8
X1:1
X1:3
X1:7
X1:9
X1:13
HDMI interrupt. Used for Hot Plug detection
Transmit clock (negative)
Transmit clock (positive)
Data lane (negative)
Data lane (positive)
Data lane (negative)
I
O
O
O
O
O
I/O Comment
I/O
O
I/O
HDMI_TXD1_P
HDMI_TXD2_N
X1:15 Data lane (positive)
X1:19 Data lane (negative)
HDMI_TXD2_P X1:21 Data lane (positive)
HDMI_VDD_EN X4:52 HDMI power enable
O
O
O
O
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Section 4 Interfaces of the COM
4.5.2
Example schematic
Figure 4.2: HDMI schematic example
4.5.3
Necessary layout properties
Table 16: HDMI interface signal routing requirements
Parameter
Max frequency
Requirement
297
Units Notes
MHz Data rate is ten times larger than the pixel frequency
Topology
Termination
Reference plane
Max Breakout length / delay
Trace impedance
Trace spacing
Point to Point
50 (At Receiver) / 500
(on-board)
GND
7.62 (52.5)
90 (diff pair) / 45-60 (single ended)
4x (microstrip) / 3x
(stripline)
Ω mm (ps)
Ω
To 3.3V at receiver / To
GND near connector
±15%
Max Trunk delay (297
MHz)
114 (675) (Microstrip /
Stripline)
Max Trunk delay (225
MHz)
204 (1400) (Microstrip /
Stripline) dielectric Mircostrip routing is recommended for HDMI due to limited eye height and has longer MAX length mm (ps) Include package & PCB routing delays for Max trace delays and max trace delay skew parameters mm (ps) Include package & PCB routing delays for Max trace delays and max trace delay skew parameters
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Section 4 Interfaces of the COM
Parameter
Max Trunk delay (16
MHz)
Requirement
254 (1500) (Microstrip /
Stripline)
Units Notes mm (ps) Include package & PCB routing delays for Max trace delays and max trace delay skew parameters mm (ps) Max distance from ESD to connector
Max distance from signal line to ESD pad
12.7 (87)
6.35 (37.5) mm (ps) ps
Keep stub connecting
ESD to signal trace very short or overlay pad on signal trace.
Max intra-pair (within pair) skew
Max inter-pair (pair-pair) skew
1
150 ps
27
Table 17: HDMI interface delays
Signal Name
HDMI_TXC_N
HDMI_TXC_P
HDMI_TXD0_N
HDMI_TXD0_P
HDMI_TXD1_N
HDMI_TXD1_P
HDMI_TXD2_N
HDMI_TXD2_P
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
29 182.2
211.2
29
29
182.2
182.8
211.2
211.8
29
38
39
49
50
182.8
182.4
182.4
182.6
182.6
211.8
220.4
221.4
231.6
232.6
4.6
I
2
C
The Inter-Chip Communication (I2C) controller implements an I2C master and a slave controller. The
I2C controller supports multiple masters and slaves in: Standard-mode (up to 100Kbit/s), Fast-mode (up to 400Kbit/s), Fast-mode plus (FM+, up to 1Mbit/s) and High-speed mode (up to 3.4Mbit/s) of operations.
A general purpose I2C controller allows system expansion for I2C-based devices, such as AM/FM radio, remote LCD display, serial ADC/DAC, and serial EPROMs, as defined in the NXP Inter-IC-bus (I2C) specification. The I2C bus supports serial device communications to multiple devices. The I2C controller handles bus mastership with arbitration, clock source negotiation, speed negotiation for standard and fast devices, and 7-bit and 10-bit slave address support according to the i2c protocol and supports master and slave mode of operation.
The following table shows the our default U-Boot and Kernel I
2
C bus-number assignment:
Table 18: I
2
C bus-number assignment
Bus Description Comment i2c0 GEN1_I2C 1.8V I2C bus i2c1 GEN2_I2C 3.3V I2C bus i2c2 CAM_I2C 1.8V I2C bus
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Section 4 Interfaces of the COM
Bus Description Comment i2c3 HDMI DDC 5V tolerant I2C bus i2c4 PWR_I2C 1.8V I2C bus (only on the SoM)
4.6.1
Signals
Table 19: I
2
C GEN1 (1V8) signals
Signal Pin Description I/O Comment
GEN1_I2C_SCL X5:2 GEN1 I2C clock O
GEN1_I2C_SDA X5:4 GEN1 I2C data I/O
Table 20: I
2
C GEN2 (3V3) signals
Signal Pin Description I/O Comment
GEN2_I2C_SCL X4:45 GEN2 I2C clock O
GEN2_I2C_SDA X4:47 GEN2 I2C data I/O
Table 21: I
2
C CAM (1V8) signals
Signal Pin Description I/O Comment
CAM_I2C_SCL X1:56 Camera I2C clock O
CAM_I2C_SDA X1:58 Camera I2C data I/O
Table 22: HDMI DDC signals
Signal Pin Description I/O Comment
CAM_I2C_SCL X1:4 HDMI DDC clock O
CAM_I2C_SDA X1:2 HDMI DDC data I/O
4.6.2
Example schematic
No special schematics are required.
4.6.3
Necessary layout properties
The I2C bus lines are pulled already on the SoM.
28
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Section 4 Interfaces of the COM
4.7
JTAG
29
K1 series processors have an optional JTAG interface that can be used for SCAN testing or for communication with either integrated CPU.
4.7.1
Signals
JTAG signals
Signal Pin Description
JTAG_nTRST X4:21 Test reset
I/O Comment
I Normal operation: Pulldown only Do not connect to TRST pin of connector
Scan test mode: Connect to TRST_N pin of the connector pulled with 10k to
GND on the SoM
JTAG_RTCK X4:23 Return Test reset I
JTAG_TCK X4:15 Test clock I
JTAG_TDI
JTAG_TDO
JTAG_TMS
X4:19
X4:25
Test data In
Test data Out
I
O
X4:17 Test mode select I
4.7.2
Example schematic
No special schematics are required.
4.7.3
Necessary layout properties no necessary layout properties
4.8
MIPI CSI
The Camera Serial Interface (CSI) is based on MIPI CSI 2.0 specification and implements the CSI receiver which receives data from an external camera module with a CSI transmitter. It consists of two CSI receiver interfaces so it can receive serial transmissions from two cameras.
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Section 4 Interfaces of the COM 30
• MIPI CSI 2.0 receiver
• Support for 3 camera sensors (any 2 can be active at the same time)
1 x4 (single camera with 4 lane sensor)
1 x4 + 1 x1 (one high resolution camera nad antoher front facing low resolution camera)
2 x4 (dual cameras for stereo with 4 lanes for each camera)
• Supported input data formats:
RGB: RGB888, RGB666, RGB565, RGB555, RGB444
YUV: YUV422-8b, YUV420-8b (legacy), YUV420-8b, YUV444-8b
RAW: RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
DPCM: user defined
User defined: JPEG8
Embedded: Embedded control information
• Supports single-shot mode
• D-PHY Modes of Operation
High Speed Mode - High speed differential signaling up to 1.5 Gbps; burst transmission for low power
Low Power Control - Single-ended 1.2 V CMOS level. Low speed signaling for handshaking.
Low speed signaling for data, used for escape command entry only: 20 Mbps
4.8.1
Signals
Table 24: MIPI CSI signals
Signal
CAM_nRST
Pin Description
X4:56 CAM reset
I/O Comment
O
CAM1_MCLK X1:60 CAM1 master clock O
CAM1_PWDN X4:54 CAM1 power down O
CAM2_MCLK X1:54 CAM2 master clock O
CAM2_PWDN X4:58 CAM2 power down O
CSI_A_CLK_N X2:41 CSI clock (negative) I
CSI_A_CLK_P X2:39 CSI clock (positive) I
CSI_A_D0_N X2:27 CSI data (negative) I/O
CSI_A_D0_P X2:29 CSI data (positive) I/O
CSI_A_D1_N X2:35 CSI data (negative) I/O
CSI_A_D1_P X2:33 CSI data (positive) I/O
CSI_B_D0_N
CSI_B_D0_P
CSI_B_D1_N
CSI_B_D1_P
X2:21
X2:23
X2:17
X2:15
CSI data (negative)
CSI data (positive)
CSI data (negative)
CSI data (positive)
I/O
I/O
I/O
I/O
CSI_E_CLK_N X2:11 CSI clock (negative) I
CSI_E_CLK_P X2:9 CSI clock (positive) I
CSI_E_D0_N
CSI_E_D0_P
X2:3
X2:5
CSI data (negative)
CSI data (positive)
I/O
I/O
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Section 4 Interfaces of the COM
4.8.2
Example schematic
No special schematics are required.
4.8.3
Necessary layout properties
Table 25: CSI interface signal routing requirements
Parameter
Max frequency / data rate
(per data lane)
Number of loads
Max loading (per pin)
Reference plane
Requirement
750 / 1500
1
10
GND or PWR
Units
MHz / Mbps
Notes load pF
Ω
If PWR, 10nF decoupling cap required for return current
±15%
Breakout impedance region 90 (diff) / 45-55 (single ended)
Max PCB breakout delay 48
Trace impedance 90 (diff pair) / 45-55 (single ended)
<3.8 (24) Via proximity (signal to reference)
Trace spacing
Max trace delay
2x (microstrip / stripline)
1620 ps
Ω mm (ps) dielectric ps
Max intra-pair pair) skew
(within
Max inter-pair (pair-pair) skew
1
10 ps ps
PCB routing delays for
Max trace delays and max trace delay skew parameters
PCB routing delays for
Max trace delays and max trace delay skew parameters
PCB routing delays for
Max trace delays and max trace delay skew parameters
Table 26: CSI interface delays
Signal Name
CSI_A_CLK_N
CSI_A_CLK_P
CSI_A_D0_N
CSI_A_D0_P
CSI_A_D1_N
CSI_A_D1_P
CSI_B_D0_N
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
61
62
78
46
46
81
81
109.5
109.5
73.8
73.8
94.1
93.0
76.4
155.5
155.5
154.8
154.8
155.1
155.0
154.4
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31
Section 4 Interfaces of the COM
Signal Name
CSI_B_D0_P
CSI_B_D1_N
CSI_B_D1_P
CSI_E_CLK_N
CSI_E_CLK_P
CSI_E_D0_N
CSI_E_D0_P
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
79 75.5
154.5
66
67
88.0
87.1
154.0
154.1
67
68
57
58
87.4
86.4
97.5
96.5
154.4
154.4
154.5
154.5
32
4.9
MIPI DSI
The MIPI Display Serial Interface (DSI) us a serial bit-stream replacement for the parallel MIPI DPI and
DBI display interface standards. DSI reduces package pin-count and I/O power consumption. DSI support enables both display controllers to connect to an external display(s) with a MIPI DSI receiver. The DSI transfers pixel data from the internal display controller to an external third-party LCD module.
Features:
• Phy Layer:
– Start / End of transmission. Other out-of-band signaling
– Per DSI interface: 1 Clock Lane; up to 4 data lanes
– Supports link configuration: 1x4, 2x4
– Supports Dual link operation in 2x4 configurations for asymmetrical/symmetrical split in both left-right side or odd-even group split schemes
– Maximum link rate 1.5 Gbps as per MIPI D-PHY 1.1v version
– Maximum 10 MHz LP receive rate
• Maximum resolution supported:
– Dual link - 2x4: 3840x1920 @60Hz, 24-bpp at 1.5 Gbps per lane
– Single link - 1x4: 2560x1440 @60Hz, 24-bpp at 1.5 Gbps per lane
• Lange Managment Layer with Distributor
• Protocol Layer with Packet Constructor
• Supports MIPI DSI 1.0.1v version mandatory features
• Command Mode (one-shot) with host and/or display controller as master
• Clocks:
– Bit clock: Serial data stream bit-rate clock
– Byte clock: Lane management layer byte-rate clock
– Application clock: Protocol layer byte-rate clock
• Error Detection / Correction:
– ECC generation for packet Headers
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Section 4 Interfaces of the COM
– Checksum generation for Long Packets
• Error recovery
• High speed transmit timer
• Low power receive timer
• Turnaround acknowledge Timeout
4.9.1
Signals
Table 27: MIPI DSI signals
Signal Pin Description
DSI_A_CLK_N X2:46 DSI clock (negative)
I/O Comment
O
DSI_A_CLK_P X2:44 DSI clock (positive) O
DSI_A_D0_N X2:32 DSI bidirectional data lanes (negative) I/O
DSI_A_D0_P X2:34 DSI bidirectional data lane (positive) I/O
DSI_A_D1_N X2:56 DSI bidirectional data lane (negative) I/O
DSI_A_D1_P X2:58 DSI bidirectional data lane (positive) I/O
DSI_A_D2_N X2:40 DSI bidirectional data lane (negative) I/O
DSI_A_D2_P X2:38 DSI bidirectional data lane (positive) I/O
DSI_A_D3_N X2:52 DSI bidirectional data lane (negative) I/O
DSI_A_D3_P X2:50 DSI bidirectional data lane (positive) I/O
DSI_B_CLK_N X2:20 DSI clock (negative)
DSI_B_CLK_P X2:22 DSI clock (positive)
O
O shared with CSI C/D shared with CSI C/D
DSI_B_D0_N
DSI_B_D0_P
DSI_B_D1_N
DSI_B_D1_P
X2:16
X2:14
X2:4
X2:2
DSI bidirectional data lane (negative)
DSI bidirectional data lane (positive)
DSI bidirectional data lane (negative)
DSI bidirectional data lane (positive)
I/O
I/O
I/O
I/O shared with CSI C/D shared with CSI C/D shared with CSI C/D shared with CSI C/D
DSI_B_D2_N
DSI_B_D2_P
DSI_B_D3_N
DSI_B_D3_P
X2:26 DSI bidirectional data lane (negative) I/O shared with CSI C/D
X2:28 DSI bidirectional data lane (positive) I/O shared with CSI C/D
X2:10 DSI bidirectional data lane (negative) I/O shared with CSI C/D
X2:8 DSI bidirectional data lane (positive) I/O shared with CSI C/D
33
4.9.2
Example schematic
No special schematics are required.
4.9.3
Necessary layout properties
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Section 4 Interfaces of the COM
Table 28: DSI interface signal routing requirements
Parameter
Max frequency / data rate
(per data lane)
Number of loads
Max loading (per pin)
Reference plane
Requirement
750 / 1500
1
10
GND or PWR
Units
MHz / Mbps
Notes load pF
Ω
If PWR, 10nF decoupling cap required for return current
±15%
Breakout impedance region
Via proximity (signal to reference)
90 (diff) / 45-55 (single ended)
Max PCB breakout delay 48
Trace impedance 90 (diff pair) / 45-55 (single ended)
<3.8 (24)
Trace spacing
Max trace delay
2x (microstrip / stripline)
1620 ps
Ω mm (ps) dielectric ps
Max intra-pair pair) skew
(within
Max inter-pair (pair-pair) skew
1
10 ps ps
PCB routing delays for
Max trace delays and max trace delay skew parameters
PCB routing delays for
Max trace delays and max trace delay skew parameters
PCB routing delays for
Max trace delays and max trace delay skew parameters
34
Table 29: DSI interface delays
Signal Name
DSI_A_CLK_N
DSI_A_CLK_P
DSI_A_D0_N
DSI_A_D0_P
DSI_A_D1_N
DSI_A_D1_P
DSI_A_D2_N
DSI_A_D2_P
DSI_A_D3_N
DSI_A_D3_P
DSI_B_CLK_N
DSI_B_CLK_P
DSI_B_D0_N
DSI_B_D0_P
DSI_B_D1_N
DSI_B_D1_P
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
66 85.9
151.9
66
76
86.0
76.3
152.0
152.3
75
50
51
75
76.5
102.0
101.6
77.5
151.5
152.0
152.6
152.5
67
47
48
75
56
57
68
67
67
77.5
97.6
96.5
84.9
85.8
85.9
85.9
105.7
104.7
152.5
153.6
153.5
152.9
152.8
152.9
152.9
152.7
152.7
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Section 4 Interfaces of the COM
Signal Name
DSI_B_D2_N
DSI_B_D2_P
DSI_B_D3_N
DSI_B_D3_P
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
74 78.3
152.3
73
55
55
79.3
97.8
97.0
152.3
152.8
152.8
35
4.10
PCIe
K1 series processors integrate a x4 lane bridge to enable a control path from the Tegra chip to external PCIe devices. Two PCIe Gen2 controllers (5.0 GT/s) supports up to 5 PCIe lanes (two interfaces).
Use Case
Jetson TK1
1
2
3
4
USB3.0
2
1
0
1
PCIe
1 x1 & 1 x2
1 x4
1 x1 & 1 x4
1 x1 & 1 x4
Table 30: Possible PCIe Configurations
SATA
1
1
1
0
LANE0
USB_SS#0
USB_SS#0 USB_SS#1 PCIe#1_0 PCIe#0_1 PCIe#0_0
USB_SS#0 PCIe#0_3 PCIe#0_2 PCIe#0_1 PCIe#0_0
PCIe#1_0
PCIe#1_0
LANE1 unused
PCIe#0_3
PCIe#0_3
LANE2
PCIe#1_0
LANE3 LANE4
PCIe#0_0
SATA
SATA
SATA
SATA
PCIe#0_2 PCIe#0_1 PCIe#0_0 SATA
PCIe#0_2 PCIe#0_1 PCIe#0_0 USB_SS#1
We use in our Universal-Bootloader (U-Boot) per default the configuration 1. If you require a different setup, please contact us.
The mapping of the control signals are the following:
Table 31: PCIe: Clock and control signal mapping
PCIe controller Clock signal Clock request signal Reset signal
PCIe#0 PEX_CLK1 PEX_L0_nCLKREQ PEX_L0_nRST
PCIe#1 PEX_CLK2 PEX_L1_nCLKREQ PEX_L1_nRST
4.10.1
Signals
Table 32: PCIe signals
Signal
PEX_CLK1_N
PEX_CLK1_P
PEX_CLK2_N
Pin Description
X3:58 PCIe clock (negative)
X3:60 PCIe clock (positive)
X3:24 PCIe clock (negative)
PEX_CLK2_P X3:22 PCIe clock (positive)
PEX_L0_nCLKREQ X3:44 PCIe clock request
PEX_L0_nRST X3:46 PCIe reset. This signal provides a reset signal to all the PCIe links. It must be asserted
100 ms after power to the PCIe slots has stabilized.
PEX_L1_nCLKREQ X3:48 PCIe clock request
I/O Comment
O
O
O
O
I
O
I
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Section 4 Interfaces of the COM
Signal
PEX_L1_nRST
PEX_nWAKE
USB3_RX0_N
USB3_RX0_P
Pin Description
X3:50 PCIe reset. This signal provides a reset signal to all the PCIe links. It must be asserted
100 ms after power to the PCIe slots has stabilized.
X3:52 PCIe Wake. This signal is used as the PCIe defined WAKE# signal. When asserted by a
PCIe device, it is a request that the system power be restored. No interrupt or other consequences result from
X3:9 PCIe receive data lane0 (negative). Shared with USB3.0
X3:7 PCIe receive data lane0 (positive).
Shared with USB3.0
USB3_TX0_N
USB3_TX0_P
X3:1 PCIe transmit data lane0 (negative). Shared with USB3.0
X3:3 PCIe transmit data lane0 (positive). Shared with USB3.0
PEX_USB3_RX1_N X3:19 PCIe receive data lane1 (negative). Shared with USB3.0
PEX_USB3_RX1_P X3:21 PCIe receive data lane1 (positive).
Shared with USB3.0
PEX_USB3_TX1_N X3:13 PCIe transmit data lane1 (negative). Shared with USB3.0
PEX_USB3_TX1_P X3:15 PCIe transmit data lane1 (positive). Shared with USB3.0
PEX_RX2_N
PEX_RX2_P
PEX_TX2_N
PEX_TX2_P
PEX_RX3_N
PEX_RX3_P
PEX_TX3_N
PEX_TX3_P
PEX_RX4_N
PEX_RX4_P
PEX_TX4_N
PEX_TX4_P
X3:31
X3:33
X3:25
X3:27
X3:45
X3:43
X3:37
X3:39
X3:49
X3:51
X3:57
X3:55
PCIe receive data lane2 (negative)
PCIe receive data lane2 (positive)
PCIe transmit data lane2 (negative)
PCIe transmit data lane2 (positive)
PCIe receive data lane3 (negative)
PCIe receive data lane3 (positive)
PCIe transmit data lane3 (negative)
PCIe transmit data lane3 (positive)
PCIe receive data lane4 (negative)
PCIe receive data lane4 (positive)
PCIe transmit data lane4 (negative)
PCIe transmit data lane4 (positive)
I/O Comment
O
O
O
O
O
I
I
I
I
I
I
I
O
O
O
O
I
I
I
I
O
O
36
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Section 4 Interfaces of the COM
4.10.2
Example schematic
Figure 4.3: PCI Express schematic example
37
Figure 4.4: Mini PCI Express socket schematic example
4.10.3
Necessary layout properties
Parameter
Table 33: PCIe interface signal routing requirements
Max frequency / UI period
Topology
Requirement
5.0 / 200
Point-to-Point
Units Notes
Gbps / ps 2.5 GHz, half-rate architecture
Unidirectional, differential load Configuration / Device organization
Max loading (per pin)
1
N/A pF
Termination 50 Ω see return loss spec in
PCIe 2.0 spec
To GND single ended for
P & N
Reference plane
Breakout region Width/line spacing
Breakout region pair spacing
GND
4
10 mils mils Maximum pair spacing of
500 mils
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Section 4 Interfaces of the COM
Parameter
Trace impedance
Requirement
90 (diff pair) / 45-55 (single ended)
Pair to Pair Trace Spacing 3x (stripline) / 4x (mi-
Max trace length/delay
Max intra-pair pair) skew
(within crostrip)
254 (1700)
1
Units
Ω dielectric mm (ps) ps
Notes
Max inter-pair (pair-pair
(RX-TX)) skew
600 ps
PCB routing delays for
Max trace delays and max trace delay skew parameters
PCB routing delays for
Max trace delays and max trace delay skew parameters
38
Table 34: PCIe interface delays
Signal Name
PEX_CLK1_N
PEX_CLK1_P
PEX_CLK2_N
PEX_CLK2_P
USB3_RX0_N
USB3_RX0_P
USB3_TX0_N
USB3_TX0_P
PEX_USB3_RX1_N
PEX_USB3_RX1_P
PEX_USB3_TX1_N
PEX_USB3_TX1_P
PEX_RX2_N
PEX_RX2_P
PEX_TX2_N
PEX_TX2_P
PEX_RX3_N
PEX_RX3_P
PEX_TX3_N
PEX_TX3_P
PEX_RX4_N
PEX_RX4_P
PEX_TX4_N
PEX_TX4_P
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
73 149.8
222.8
72
67
150.5
147.2
222.5
214.2
64
43
43
36
149.8
145.7
145.5
146.4
213.8
188.7
188.5
182.4
26
39
38
37
36
35
46
46
26
49
48
39
39
45
45
29
28
147.6
136.6
136.9
147.4
147.4
159.2
160.2
142.9
143.6
147.2
147.2
165.4
166.3
145.3
146.4
168.6
168.6
182.6
182.6
182.9
173.4
173.4
198.2
198.2
179.9
179.6
192.2
192.2
194.4
194.3
194.3
194.4
207.6
207.6
4.11
SATA
The Serial ATA (SATA) controller enables a control path from the Tegra processor to an external SATA device. A SSD / HDD / ODD drive can be connected. Controller can support the maximum troughput of a
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Section 4 Interfaces of the COM
GEN 2 drive.
Features:
• SATA specification rev 3.1 and AHCI specification rev 1.3.1 compliant
– Including all errata, ENC, and TP, except DHU (direct head unload)
• Device sleep feature support
– Software initialed device sleep from slumber state only
– Software initialed device sleep from any link states (active, partial, slumber)
– Hardware initialed aggressive device sleep management
• Port multiplier support
– Command based switching (CBS)
– FIS based switching (FBS)
• Supported Cables and connectors
– Standard internal connector
– Internal micro connector
– Internal slimline connector
– mSATA connector
– BGA SSD interface
– Not supported: External connector (eSATA), USM, Internal LIF-SATA
4.11.1
Signals
Table 35: SATA signals table:sata
Signal Pin Description
SATA_L0_RX_N X3:10 receive data lane (negative)
I/O Comment
I
SATA_L0_RX_P X3:12 receive data lane (positive) I
SATA_L0_TX_N X3:6 transmit data lane (negative) O
SATA_L0_TX_P X3:4 transmit data lane (positive) O
SATA_LED X5:41 SATA status LED O
SATA_PWR_EN X5:39 SATA power enable O
4.11.2
Example schematic
No special schematics are required.
39
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Section 4 Interfaces of the COM
4.11.3
Necessary layout properties
Table 36: SATA interface signal routing requirements
Parameter
Max frequency / UI period
Topology
Requirement
3.0 / 333.3
Point-to-Point
Units
Gbps / ps
Notes
1.5 GHz
Unidirectional, differential
Configuration / Device organization
Max loading (per pin)
Termination
Reference plane
Breakout region Width/-
1
0.5
100
GND
4 line spacing
Trace impedance 90 (diff pair) / 55 (single ended)
Pair to Pair Trace Spacing 3x (stripline) / 3x (microstrip)
Max trace length/delay 203 (1330) load pF
Ω mils
Ω dielectric
Max intra-pair pair) skew
(within 1
On die termination mm (ps) Include Package & PCB routing delays for max trace delays and max trace delay skew parameters ps PCB routing delays for
Max trace delays and max trace delay skew parameters
Table 37: PCIe interface delays
Signal Name
SATA_LO_RX_N
SATA_LO_RX_P
SATA_LO_TX_N
SATA_LO_TX_P
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
44 65.7
109.7
44
50
49
65.7
61.9
62.9
109.7
111.9
111.9
40
4.12
SD/MMC (SDIO)
The Tegra K1 has four SD/MMC controllers. The Meerkat uses SDMMC3 for an SD Card interface and
SDMMC4 to interface to an eMMC device (primary boot option). SDMMC1 is available to use as SDIO.
SDMMC2 is not routed on the Meerkat SoM.
For the SD Card and SDIO interfaces, SDMMC3 and SDMMC1 support up to UHS-1. For eMMC, SD-
MMC4 supports up to HS200.
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Section 4 Interfaces of the COM
4.12.1
Signals
Table 38: SDMMC1 (SDIO) signals
Signal Pin Description
SDMMC1_PWR_EN X4:48 SDMMC1 power enable
SDMMC1_CLK
SDMMC1_CMD
SDMMC1_DAT0
SDMMC1_DAT1
X1:50
X1:52
X1:42
X1:44
SDMMC/SDIO clock
SDMMC/SDIO command
SDMMC/SDIO data
SDMMC/SDIO data
SDMMC1_DAT2
SDMMC1_DAT3
SDMMC1_nIRQ
SDMMC1_nWP
X1:40
X1:48
SDMMC/SDIO data
SDMMC/SDIO data
I/O
O
O
I/O
I/O
I/O
I/O
I/O
Comment
X1:38 SDMMC/SDIO interrupt request I low active
X1:46 SDMMC/SDIO write protect O low active
Table 39: SDMMC3 signals
Signal Pin Description
SDMMC3_VDD_EN
SDMMC3_CLK
SDMMC3_CLK_LB_IN
X5:25 SDMMC power enable
X1:30 SDMMC clock
X1:26 SDMMC clock loop back input: SD-
MMC3_CLK_LB_IN connects to SD-
MMC3_CLK_LB_OUT.
Total trance length is the length of a round trip, from Tegra to connector and back.
SDMMC3_CLK_LB_OUT X1:28 SDMMC clock loop back output
SDMMC3_CMD X1:18 SDMMC command
SDMMC3_DAT0
SDMMC3_DAT1
X1:22
X1:16
SDMMC data
SDMMC data
SDMMC3_DAT2
SDMMC3_DAT3
SDMMC3_nCD
SDMMC3_nWP
X1:20 SDMMC data
X1:14 SDMMC data
X1:32 SDMMC card detect
X1:34 SDMMC write protect
I/O Comment
O
O
I
O
I/O
I/O
I/O
I/O
I/O
O low active
O low active
41
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Section 4 Interfaces of the COM
4.12.2
Example schematic
Figure 4.5: SDMMC schematic example
4.12.3
Necessary layout properties
Parameter
Max frequency
Table 40: SDMMC3/1 interface signal routing requirements
3.3V
DS
HS
1.8V SDR12
SDR25
SDR50
SDR104
DDR50
Requirement
25 (12.5)
50 (25)
25 (12.5)
50 (25)
100 (50)
208 (104)
50 (50)
Units Notes
MHz / (MB/s) Actual frequencies my be slightly different due to clock source/divider limitations
Topology
Max loading (per pin)
Reference plane
Breakout region impedance
Trace impedance
Max trace delay
SDR12, SDR25, SDR50 /
SDR104
Point-to-Point
10
GND or PWR
45-50
45-50
1100 / 745 pF
Ω
Ω ps
±15%
±15%
Include Package & PCB routing delays for max trace delays and max trace delay skew parameters
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42
Section 4 Interfaces of the COM
Parameter
Max trace delay skew in/between CLK & CMD/DAT
SDR12, SDR25, SDR50 /
Loopback clock routing
SDR104
LB_OUT to LB_IN = CLK length + Average of DAT[3:0]
Requirement
100 / 20
+/- 150
Units ps ps
Notes
PCB routing delays for
Max trace delays and max trace delay skew parameters
PCB routing delays for
Max trace delays and max trace delay skew parameters
Table 41: SDMMC3/1 interface delays
Signal Name
SDMMC1_CLK
SDMMC1_CMD
SDMMC1_DAT0
SDMMC1_DAT1
SDMMC1_DAT2
SDMMC1_DAT3
SDMMC3_CLK
SDMMC3_CMD
SDMMC3_DAT0
SDMMC3_DAT1
SDMMC3_DAT2
SDMMC3_DAT3
SDMMC3_CLK_LB_IN
SDMMC3_CLK_LB_OUT
Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
97 91.1
188.1
86
68
95.8
103.3
181.8
171.3
68
69
90
63
76
104.1
103.5
101.2
81.4
69.0
172.1
172.5
191.2
144.4
145.0
74
89
77
72
72
73
70.1
73.5
76.5
81.4
70.0
76.1
144.1
162.5
153.5
153.4
142.0
146.1
43
4.13
S/PDIF
The Sony/Philips Digital Interconnect Format (SPDIF) interface supports both professional and consumer applications. When used in a professional application, the interface is primarily intended to carry monophonic or stereophonic programs, at a 48 kHz sampling frequency and with a resolution of up to 24-bits per sample; it may alternatively be used to carry signals sampled at 32 kHz or 44.1 kHz. When used in a consumer application, the interface is primarily stereophonic programs with a resolution of up to 20-bits per sample.
The Interface normally carries audio data coded as other than linear PCM-coded audio samples. The interface may also carry data related to computer software or signals coded using non-linear PCM.
Features:
• Fire data formats: 16-bit, 20-bit, 24-bit, RAW and 16-bit packed
• Supprted sample rates: 32, 44.1, 48, 88.2, 96, 176.4 and 192 kHz
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Section 4 Interfaces of the COM
• Flexible clock divisor for use to generate different "spdifout" data rate
• SPDIFOUT (TX)
– 16-word data FIFO for storage of outgoing audio data
– 4-word user FIFO for storage of outgoing user data
– 6-word page buffer for storage of outgoing channel status
44
4.13.1
Signals
Table 42: S/PDIF signals
Signal
SPDIF_IN
Pin
X5:58
Description
Data In
SDPIF_OUT X5:56 Data Out
I/O
I
O
Comment
4.13.2
Example schematic
No special schematics are required.
4.13.3
Necessary layout properties no necessary layout properties
4.14
SPI
The Serial Peripheral Interface (SPI) controller supports master/slave operations up to 50 MHz (50 Mbps maximal data rate). It allows a duplex. synchronous, serial communication between the controller and external peripheral devices. It consists of 4 signals, nCS (chip select), SCK (clock), MOSI (master data out and Slave data in) and MISO (master data in and Slave data out). The data is transferred on MOSI or MISO based on the data transfer direction on every SCK edge. The receiver always receives the data on the other edge of SCK.
Features:
• Independent RX FIFO and RX FIFO
• Software controlled bit-length supports packet sizes of 1 to 32 bits
• Packed mode support for bit-length of 7 (8-bit packet size) and 15 (16-bit packet size)
• nCS can be selected to be controlled by software, or it can be generated automatically by the hardware on packet boundaries
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Section 4 Interfaces of the COM 45
• Receive compare mode (controller listens for a specified pattern on the incoming data before receiving the data in the FIFO)
• Simultaneous receive and transmit supported
• Supports Master and Slave modes of operation
4.14.1
Signals
Table 43: SPI1A signals (1.8V level)
Signal Pin Description I/O Comment
SPI1A_MISO X5:45 Master In/Slave Out I
SPI1A_MOSI X5:51 Master Out/Slave In O
SPI1A_nCS0 X5:47 Chip Select O
SPI1A_SCK X5:49 Serial Clock
SPI1A_nIRQ X5:43 Interrupt request
O
I
Table 44: SPI2D signals (1.8V level)
Signal Pin Description I/O Comment
SPI2D_MISO X5:7 Master In/Slave Out I
SPI2D_MOSI X5:3 Master Out/Slave In O
SPI2D_nCS0 X5:1 Chip Select O
SPI2D_SCK X5:5 Serial Clock
SPI2D_nIRQ X5:36 Interrupt request
O
I
Table 45: SPI3E signals (1.8V level)
Signal Pin Description I/O Comment
SPI2D_MISO X5:19 Master In/Slave Out I
SPI2D_MOSI X5:13 Master Out/Slave In O
SPI2D_nCS1 X5:27 Chip Select O
SPI2D_SCK X5:23 Serial Clock O
Table 46: SPI4C signals (1.8V level)
Signal Pin Description I/O Comment
SPI4_MISO X5:57 Master In/Slave Out I
SPI4_MOSI X5:55 Master Out/Slave In O
SPI4_nCS0 X5:53 Chip Select O
SPI4_SCK X5:59 Serial Clock O
NOTE: SPI2 and SPI3 are not officially supported from NVIDIA. You can use them on your own risk. The
SPI3 interface pins will be used as GPIOs per default.
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Section 4 Interfaces of the COM
4.14.2
Example schematic
No special schematics are required.
4.14.3
Necessary layout properties no necessary layout properties
46
4.15
UART
The Universal Asynchronous Receiver Transmitter (UART) controller provides serial data synchronization and data conversion (parallel-to-serial and serial-to-parallel) for both receiver and transmitter sections. Synchronization for serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character. Data integrity is accomplished by attaching a parity bit to the data character. The parity bit can be checked by the receiver for any transmission bit errors.
Features:
• Synchronization for the serial data stream with start and stop bits to transmit data and form a data character
• Supports both 16450- and 16550-compatible modes. Default mode is 16450
• Device clock up to 200 MHz, baudrate of 12.5 Mbits/second
• Data integrity by attaching parity bit to the data character
• Support for word lengths from five to eight bits, an optional parity bit and one or two stop bits
• Support for modem control inputs
• DMA capability for both TX and RX
• 8-bit x 36 deep TX FIFO
• 11-bit x 36 deep RX FIFO. 3 bits of 11 bits per entry will log the RX errors in FIFO mode (break, framing and parity errors as bits 10,9,8 of fifo entry)
• Auto sense baud detection
• Timeout interrupts to indicate if the incoming stream stopped
• Priority interrupts mechanism
• Flow control support on RTS and CTS
• Internal loopback
• SIR encoding/decoding (3/16 or 4/16 baud pulse widths to transmit bit zero)
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Section 4 Interfaces of the COM
4.15.1
Signals
Table 47: UART1 signals (1.8V level)
Signal Pin Description
UART1_RXD X5:9 UART receive
I/O
I
UART1_TXD X5:11 UART transmit O
Comment
Table 48: UART2 signals (1.8V level)
Signal Pin Description
UART2_nCTS X4:34 UART Clear-to-send
I/O Comment
I low active
UART2_nRTS X4:32 UART Request-to-send O low active
UART2_RXD X4:28 UART receive I
UART2_TXD X4:30 UART transmit O
Table 49: UART3 signals (1.8V level)
Signal Pin Description
UART3_nCTS X4:44 UART Clear-to-send
I/O Comment
I low active
UART3_nRTS X4:42 UART Request-to-send O low active
UART3_RXD X4:38 UART receive I
UART3_TXD X4:40 UART transmit O
Table 50: UART4 (DEBUG) signals (1.8V level)
Signal Pin Description I/O Comment
UART4_DEBUG_nCTS X4:35 UART Clear-to-send I low active
UART4_DEBUG_nRTS X4:39 Request-to-send
UART4_DEBUG_RXD X4:41 UART receive
UART4_DEBUG_TXD X4:37 UART transmit
O
I
O low active
4.15.2
Example schematic
No special schematics are required.
4.15.3
Necessary layout properties no necessary layout properties
47
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Section 4 Interfaces of the COM
4.16
USB (HSIC)
48
The K1 USB complex provides a mechanism to communicate with a PC and/or USB2.0 peripherals, such as keyboard, mouse, and card readers; USB3.0 peripherals, such as camera and storage devices, as a host using regular USB 3.0 ports; and to an ob-board baseband controller using ether USB HSIC or HSI interfaces.
The USB complex consists of a single USB 3.0 controller and three USB 2.0 controllers. The USB 3.0
controller supports up to 2 regular USB 3.0 ports and their companion regular USB 2.0 ports. The USB 2.0
controllers support up to: 2x regular USB ports, 2x HSIC interfaces. On the K1 Meerkat SoM is only on
HSIC interface (HSIC1) routed, which is shared with USB1 (USB 2.0).
Tegra USB interfaces are compliant with the following USB specifications:
• Universal Serial Bus Specification Revision 3.0
• Universal Serial Bus Specification Revision 2.0, plus the following:
– USB Battery Charging Specification, version 1.0; Including Data Contract Detect protocol
– Modes: Host and Device
– Speeds: low, Full and High
• Enhanced Host Controller Interface Specification for Universal Serial Bus revision 1.0
USB 3.0 controller The USB 3.0 controller (XUSB) - USB 3.0 ports only operate in USB 3.0 Super Speed
(SS) mode. All USB 3.0 ports share one Super Speed Bus Instance (5Gb/s bandwidth is distributed across these ports). The XUSB controller supports:
• xHCI programming model for scheduling transactions and interface management as a host that natively support USB 3.0, USB 2.0, and USB 1.1 transactions through USB 3.0 and USB 2.0 interfaces.
• Remote wakeup, wake on connect, wake on disconnect, and wake on overcurrent in all Tegra power states, including deep sleep mode.
USB 2.0 controller All USB 2.0 controllers support:
• USB hast controller registers and data structures are compliant to Intel
TM
EHCI specification. The max packet size supported on any endpoint is 1024 bytes in high-speed mode, for both device and host modes
• USB legacy (USB 1.1) Full and Low speed devices without a companion USB 1.1 host controller or host controller driver software using EHCI standard data structures.
USB 2.0 Controller #1 - Supports both USB 2.0 device and USB 2.0 host operations. USB recovery is supported only with USB 2.0 port0 (USB0_CLIENT). USB controller #1 only connects to USB 2.0 port 0, which is the primary USB 2.0 port on the Tegra devices. This controller shares the same USB 2.0 port 0 pins with the XUSB controller.
USB 2.0 Controller #2 - Can be configured to use regular USB 2.0 port 1 (USB1) or can be configured to use an HSIC interfaces that allows connection of an on-board peripheral supporting an HSIC interface to the Tegra processor. This controller shares the same USB 2.0 port 1 pins with the XUSB controller.
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Section 4 Interfaces of the COM 49
USB 2.0 Controller #3 - Can be configured to use regular USB 2.0 port 2 (USB2). This controller shares the same USB 2.0 port 2 pins with the XUSB controller.
4.16.1
Signals
Table 51: USB signals
Signal
USB0_D_N
USB0_D_P
USB0_ID
Pin Description
X2:53 USB0 (OTG) data
X2:55 USB0 (OTG) data
X2:57 USB0 (OTG) ID
I/O Comment
I/O
I/O
I
USB0_VBUS X2:59 USB0 (OTG) VBUS P
USB_VBUS_EN0_nOC X3:36 USB0 enable/overcurrent I requires pull-up against 3.3V
USB1_D_N
USB1_D_P
X3:28
X3:30
USB1 data
USB1 data
I/O
I/O
USB_VBUS_EN1_nOC X3:34 USB1 enable/overcurrent I requires pull-up against 3.3V
USB2_D_N X3:18 USB2 data I/O
USB2_D_P X3:16 USB2 data I/O
USB_VBUS_EN2_nOC X3:54 USB2 enable/overcurrent I requires pull-up against 3.3V
USB3_RX0_N X3:9 USB 3.0 receive data lane I
USB3_RX0_P
USB3_TX0_N
(negative).
Shared with
PCIe.
X3:7 USB 3.0 receive data lane
(positive).
Shared with
PCIe.
X3:1 USB 3.0 transmit data lane (negative).
Shared with PCIe.
I
O
USB3_TX0_P O
PEX_USB3_RX1_N
PEX_USB3_RX1_P
PEX_USB3_TX1_N
PEX_USB3_TX1_P
X3:3 USB 3.0 transmit data lane (positive).
Shared with PCIe.
X3:19 USB 3.0 receive data lane
(negative).
Shared with
PCIe.
X3:21 USB 3.0 receive data lane
(positive).
Shared with
PCIe.
X3:13 USB 3.0 transmit data lane (negative).
Shared with PCIe.
X3:15 USB 3.0 transmit data lane (positive).
Shared with PCIe.
I
I
O
O
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Section 4 Interfaces of the COM
4.16.2
Example schematic
The following figure shows a schematic example of a OTG-capable USB Client port:
50
Figure 4.6: USB Client schematic example
4.16.3
Necessary layout properties
Table 52: USB 2.0 interface signal routing requirements
Parameter
Max frequency (High
Speed)
Max loading High Speed /
Full Speed / Low Speed
Reference plane
Breakout impedance
Trace impedance region
Requirement
480 / 2083 / 240
10 / 150 / 600
GND min width/spacing
Via proximity (Signal to reference)
90 (diff pair) / 50 (single ended)
<3.8 (24)
Units
Mbps / ns / MHz
Notes pF
Ω mm (ps)
±15%
Up to 4 signal vias can share a single GND return via
Max trace delay 1280 (microstrip) / 1150
(stripline) ps
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Section 4 Interfaces of the COM
Parameter
Max intra-pair skew between USBx_D_P &
USBx_D_N
Requirement
7.5
Units ps
Notes
PCB routing delays for
Max trace delays and max trace delay skew parameters
51
Parameter
Data rate / UI period
Max number of loads
Termination
Table 53: USB 3.0 interface signal routing requirements
Notes Requirement
5.0 / 200
1
90 differential
Units
Gbps / ps load
Ω On die termination TX &
RX
Reference plane
Breakout region
GND
Max length 7.62
mm 4x dielectric spacing preferred
Trace impedance dielectric
Microstrip / Stripline
To Ref plane & capacitor pad
To unrelated high-speed signals
4x / 3x
5x / 3x
5x / 4x
Max trace length 152
Max PCB Via distance from
BGA ball
Max intra-pair skew (RX/TX_N to RX/TX_P)
Max intra-pair matching between subsequent discontinuities
Via placement (GND via distance)
Max number of vias
Via stub length
7.62
1 (0.15)
1 (0.15)
<1x
4
<0.4
AC coupling capacitor 100
AC coupling capacitor location <8 (53) mm Include Package & PCB routing delays for max trace delays and max trace delay skew parameters mm ps (mm) PCB routing delays for
Max trace delays and max trace delay skew parameters ps (mm) Recommended trace length matching to <1 ps before Vias or any discontinuity to minimize common mode conversion
Diff via pitch Recommended trace length matching to <1 ps before Vias or any discontinuity to minimize common mode conversion mm nF mm (ps)
Discrete 0402
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Section 4 Interfaces of the COM
Table 54: USB 2.0 interface delays
Signal Name Pkg Delay (ps) SoM PCB delay (ps) total delay (ps)
USB0_D_N 73 75.5
148.5
USB0_D_P
USB1_D_N
72
67
75.5
156.8
147.5
223.8
USB1_D_P
USB2_D_N
USB2_D_P
64
43
43
157.4
125.9
126.1
221.4
168.9
169.1
For the USB 3.0 interface delays take a look on table 34 (PCIe interface delays).
52
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Section 5 Software
5 Software
This chapter contains information about the BCT and the Bootloader.
53
5.1
BCT
The BCT is a nvidia specific format, which contains initialisation data for the Tegra processor. Most importantly it includes the initial configuration for the memory controller, which is required to set timings matching the connected DDR memory modules. As those timings depend on chip characteristics as well as
PCB layout data they differ between boards. Avionic Design provides a BCT file for the Meerkat processor module that is independent of the carrier board, and which can to be used for flashing the Meerkat modules.
The BCT files are flashed onto the processor along with the bootloader files using the nvidia tegrarcm tool. Nvidia provides a set of helper utilities called "tegra-uboot-flasher-scripts" which ease the process of building BCT and bootloader and flashing them onto the module. BCT is a binary format which is generated using the nvidia tool called "cbootimage", which compiles clear text BCT configuration files into BCT files.
5.2
Bootloader
Once the Tegra has read the BCT it jumps to the initial load address from which it should load a bootloader.
There are two bootloaders available for the Tegra K1: fastboot (deprecated):
Fastboot is a minimalistic bootloader which is available in a special nvidia version supporting the Tegra K1.
This was the default for early software releases but shall not be used for new projects anymore.
u-boot:
The u-boot bootloader is the default bootloader for Tegra K1 running a mainline or L4T linux system. u-boot is an open source project (http://www.denx.de/wiki/U-Boot) and widely used as bootloader on embedded systems, especially on ARM processors. Avionic Design has added support for the Meerkat processor module as well as the Avionic Design Evaluation Carrier to u-boot, and provides the source code on github.
5.3
Using tegra-uboot-flasher-scripts
The tegra-uboot-flasher-scripts can be used to build a u-boot image, generate the BCT file and flash them to a Avionic Design Evaluation Carrier equipped with a Meerkat processor module. The following steps show how to use tegra-uboot-flasher scripts for an Avionic Design Evaluation Carrier.
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Section 5 Software
5.3.1
Build cross-compiling toolchain
54
In order to build the bootloader, you need a cross-compilation toolchain for armv7l as a prerequisite. If you already have a toolchain for the target, you can just set the environment variable CROSS_COMPILE and skip this step. Otherwise, you may build a toolchain using the buildroot-based BSP for Meerkat from
Avionic Design. The BSP has the form of a buildroot external. Get the BSP sources by running:
$ git clone https://github.com/avionic-design/buildroot-external-ad.git
Then follow the instructions in the file buildroot-external-ad/README to build the toolchain.
Then point the environment variable CROSS_COMPILE to that toolchain. Assuming your buildroot root directory is $BR_ROOT (insert absolute path here) and you have built the BSP resp. the BSP toolchain there using the commandline make O=build/meerkat-rootfs [toolchain] as described in the buildroot-external-ad README, then do export CROSS_COMPILE=$BR_ROOT/build/meerkat-rootfs/host/usr/bin/arm-buildroot-linux-gnueabihf-
If you have chosen a different directory for O=... when building the BSP, adapt accordingly.
5.3.2
Checkout required sources and utilities
1. Enter working-directory:
# mkdir -p ~/dev/tegra-linux
# export BUILD_DIR=~/dev/tegra-linux
# cd $BUILD_DIR
2. Checkout tegra-uboot-flasher-scripts from github:
# git clone --branch tk1/master https://github.com/avionic-design/tegra-uboot-flasher-scripts.git
3. Checkout helper repositories:
# git clone https://github.com/NVIDIA/cbootimage.git
# git clone https://github.com/NVIDIA/tegrarcm.git
# git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git
4. Checkout configuration repositories:
# git clone https://github.com/avionic-design/cbootimage-configs.git
5. Checkout u-boot
# git clone --branch tk1/master https://github.com/avionic-design/u-boot.git
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Section 5 Software
5.3.3
Build required utilities
# cd $BUILD_DIR/tegra-uboot-flasher-scripts
# ./build-tools
5.3.4
Build u-boot
Make sure that the environment variable CROSS_COMPILE is correctly set.
# cd $BUILD_DIR/tegra-uboot-flasher-scripts
# ./build --boards kein-baseboard build
5.3.5
Flash u-boot to System
1. Connect the USB debug port of the baseboard to your host PC
2. Put the carrier into recovery mode
3. Make sure that the carrier was detected on the USB host by running
# lsusb | grep NVidia
Output should look like this:
Bus 001 Device 011: ID 0955:7140 NVidia Corp.
Bus number and device may be different on your system.
4. Flash u-boot onto the system:
# sudo ./tegra-uboot-flasher flash kein-baseboard
55
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6 Pinout List
In this section you will find a list of pinouts for all the connectors of the Tegra
R
6.1
Connector overview
6.2
Connector pinout and pin-muxing
Pin Net Name
X1:1 HDMI_TXC_N
X1:2
X1:3
HDMI_DDC_SDA
HDMI_TXC_P
X1:4
X1:5
X1:6
X1:7
HDMI_DDC_SCL
Ground
HDMI_CEC
HDMI_TXD0_N
X1:8
X1:9
HDMI_INT
HDMI_TXD0_P
X1:10
X1:11
X1:12
X1:13 eDP_HPD
Ground
Ground
HDMI_TXD1_N
X1:14 SDMMC3_DAT3
X1:15 HDMI_TXD1_P
GPIO Tegra Ball Name
-
GPIO3_PV.05
-
GPIO3_PV.04
HDMI_TXCN
DDC_SDA
HDMI_TXCP
DDC_SCL
GPIO3_PEE.03
-
HDMI_CEC
HDMI_TXD0N
GPIO3_PN.07
-
HDMI_INT
HDMI_TXD0P
GPIO3_PFF.00
DP_HPD
-
GPIO3_PB.04
-
HDMI_TXD1N
SDMMC3_DAT3
HDMI_TXD1P
AD7
AD5
AC3
AD6
AC2
Tegra
Pin
Name
AF5
AC8
AF6
AC7
SFI0
HDMI_TXCN
I2C4_DAT
HDMI_TXCP
I2C4_CLK
CEC
HDMI_TXD0N
-
HDMI_TXD0P
DP_HPD
AD4
G1
AD3
HDMI_TXD1N
SDMMC3_DAT3
HDMI_TXD1P
-
-
-
SFI2
-
-
-
-
-
-
-
-
-
SFI1
-
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
-
-
-
-
-
-
-
-
-
Power Rail avdd_hdmi
(3.3V) vddio_hv (3.3V) avdd_hdmi
(3.3V) vddio_hv (3.3V)
z
z
Pin
State
Note vddio_hv (3.3V) avdd_hdmi
(3.3V) vddio_hv (3.3V) avdd_hdmi
(3.3V) vddio_hv (3.3V) z
pd
z avdd_hdmi
(3.3V) vddio_sdmmc3
(1.8V-3.3V) avdd_hdmi
(3.3V)
pu
-
Pin Net Name
X1:19 HDMI_TXD2_N
X1:20 SDMMC3_DAT2
X1:21 HDMI_TXD2_P
X1:22 SDMMC3_DAT0
GPIO Tegra Ball Name Tegra
Pin
Name
H1 X1:16 SDMMC3_DAT1
X1:17
X1:18
Ground
SDMMC3_CMD
GPIO3_PB.06
GPIO3_PA.07
-
GPIO3_PB.05
-
GPIO3_PB.07
SDMMC3_DAT1
SDMMC3_CMD
HDMI_TXD2N
SDMMC3_DAT2
HDMI_TXD2P
SDMMC3_DAT0
X1:23
X1:24
X1:25
X1:26
Ground
Ground
DP_AUX_P
SDMMC3_CLK_LB_IN
AC6
F3
X1:27
X1:28
DP_AUX_N
SDMMC3_CLK_LB_OUT
-
GPIO3_PEE.04
DP_AUX_CH0_N
SDMMC3_CLK_LB_OUT
AC5
F4
X1:29
X1:30
Ground
SDMMC3_CLK
-
GPIO3_PEE.05
DP_AUX_CH0_P
SDMMC3_CLK_LB_IN
GPIO3_PA.06
-
SDMMC3_CLK
LVDS0_TXD4P
F5
AF4 X1:31 eDP3_P
X1:32
X1:33
SDMMC3_nCD eDP3_N
GPIO3_PV.02
-
SDMMC3_CD_N
LVDS0_TXD4N
GPIO3_PQ.04
KB_COL4
V24
AF3
AF28 X1:34
X1:35
X1:36
X1:37
SDMMC3_nWP
Ground
Ground eDP0_P
X1:38 SDMMC1_nIRQ
-
GPIO3_PCC.05
LVDS0_TXD2P
CLK2_REQ
AG6
L4
F2
AD2
F1
AD1
H2
SFI0
SDMMC3_DAT1
SDMMC3_CMD
HDMI_TXD2N
SDMMC3_DAT2
HDMI_TXD2P
SDMMC3_DAT0
SDMMC3_CLK
LVDS0_TXD4P
SDMMC3_CD_N
LVDS0_TXD4N
-
LVDS0_TXD2P
-
SFI1
-
I2C6_CLK
SDMMC3_CLK_LB_IN
I2C6_DAT
SDMMC3_CLK_LB_OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDMMC3_WP_N -
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
Power Rail vddio_sdmmc3
(1.8V-3.3V)
Pin
State
Note pu vddio_sdmmc3
(1.8V-3.3V) avdd_hdmi
(3.3V) vddio_sdmmc3
(1.8V-3.3V) avdd_hdmi
(3.3V) vddio_sdmmc3
(1.8V-3.3V) pu
pu
pu vddio_hv (3.3V) vddio_sdmmc3
(1.8V-3.3V) vddio_hv (3.3V) vddio_sdmmc3
(1.8V-3.3V) z z z pd vddio_sdmmc3
(1.8V-3.3V) avdd_lvds0_io
(1.05V) vddio_sys (1.8V) avdd_lvds0_io
(1.05V) vddio_sys (1.8V) pd
pu
pu avdd_lvds0_io
(1.05V) vddio_sdmmc1
(1.8V)
z
Pin Net Name
X1:39 eDP0_N
X1:40 SDMMC1_DAT2
X1:41
X1:42
Ground
SDMMC1_DAT0
X1:43 eDP1_P
X1:44 SDMMC1_DAT1
X1:45 eDP1_N
X1:46 SDMMC1_nWP
X1:47
X1:48
Ground
SDMMC1_DAT3
X1:49 LVDS_TXD3_N
X1:50 SDMMC1_CLK
X1:51 LVDS_TXD3_P
X1:52 SDMMC1_CMD
X1:53
X1:54
Ground
CAM2_MCLK
X1:55 eDP2_N
X1:56 CAM_I2C_SCL
X1:57 eDP2_P
X1:58 CAM_I2C_SDA
X1:59 Ground
GPIO Tegra Ball Name
-
GPIO3_PY.05
LVDS0_TXD2N
SDMMC1_DAT2
GPIO3_PY.07
-
GPIO3_PY.06
-
GPIO3_PV.03
SDMMC1_DAT0
LVDS0_TXD1P
SDMMC1_DAT1
LVDS0_TXD1N
SDMMC1_WP_N
GPIO3_PY.04
-
GPIO3_PZ.00
-
GPIO3_PZ.01
SDMMC1_DAT3
LVDS0_TXD3N
SDMMC1_CLK
LVDS0_TXD3P
SDMMC1_CMD
GPIO3_PBB.00
GPIO_PBB0
LVDS0_TXD0N
GPIO3_PBB.01
CAM_I2C_SCL
LVDS0_TXD0P
GPIO3_PBB.02
CAM_I2C_SDA
Tegra
Pin
Name
AG5
L1
SFI0
LVDS0_TXD2N
SDMMC1_DAT2
L2
AG4
L3
AG3
L5
SDMMC1_DAT0
LVDS0_TXD1P
SDMMC1_DAT1
LVDS0_TXD1N
SDMMC1_WP_N
J8
AG1
L7
AG2
L8
SDMMC1_DAT3
LVDS0_TXD3N
SDMMC1_CLK
LVDS0_TXD3P
SDMMC1_CMD
AK5
AJ2
AF8
AJ3
AG8
-
LVDS0_TXD0N
-
LVDS0_TXD0P
-
-
-
-
-
-
SFI1
-
-
SFI2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_CLK -
-
-
-
I2C3_DAT -
-
-
-
-
-
SFI3
-
-
-
-
-
-
-
-
-
-
-
-
-
vimclk2_alt3
-
-
Power Rail avdd_lvds0_io
(1.05V) vddio_sdmmc1
(1.8V)
Pin
State
Note
pu vddio_sdmmc1
(1.8V) avdd_lvds0_io
(1.05V) vddio_sdmmc1
(1.8V) avdd_lvds0_io
(1.05V) vddio_sdmmc1
(1.8V) pu
pu
pu vddio_sdmmc1
(1.8V) avdd_lvds0_io
(1.05V) vddio_sdmmc1
(1.8V) avdd_lvds0_io
(1.05V) vddio_sdmmc1
(1.8V) pd
pu
pu vddio_cam
(1.8V) avdd_lvds0_io
(1.05V) vddio_cam
(1.8V) avdd_lvds0_io
(1.05V) vddio_cam
(1.8V) z
pd
z
Pin Net Name
X1:60 CAM1_MCLK
X2:1
X2:2
Ground
DSI_B_D1_P
X2:3 CSI_E_D0_N
X2:4 DSI_B_D1_N
X2:5 CSI_E_D0_P
X2:6
X2:7
X2:8
Ground
Ground
DSI_B_D3_P
X2:9 CSI_E_CLK_P
X2:10 DSI_B_D3_N
X2:11 CSI_E_CLK_N
X2:12
X2:13
X2:14
Ground
Ground
DSI_B_D0_P
X2:15 CSI_B_D1_P
X2:16 DSI_B_D0_N
X2:17 CSI_B_D1_N
X2:18
X2:19
X2:20
Ground
Ground
DSI_B_CLK_N
X2:21 CSI_B_D0_N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GPIO Tegra Ball Name
GPIO3_PCC.00
CAM_MCLK
DSI_B_D1_P
CSI_E_D0_N
DSI_B_D1_N
CSI_E_D0_P
Tegra
Pin
Name
AL5
SFI0
-
AD12
AF9
AE12
AG9
DSI_B_D1_P
CSI_E_D0_N
DSI_B_D1_N
CSI_E_D0_P
DSI_B_D3_P
CSI_E_CLK_P
DSI_B_D3_N
CSI_E_CLK_N
DSI_B_D0_P
CSI_B_D1_P
DSI_B_D0_N
CSI_B_D1_N
DSI_B_CLK_N
CSI_B_D0_N
AG12
AH8
AF12
AJ8
AJ12
AH9
AH12
AJ9
AJ11
AK8
DSI_B_D3_P
CSI_E_CLK_P
DSI_B_D3_N
CSI_E_CLK_N
DSI_B_D0_P
CSI_B_D1_P
DSI_B_D0_N
CSI_B_D1_N
DSI_B_CLK_N
CSI_B_D0_N
SFI1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI2 vimclk_alt3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
Power Rail vddio_cam
(1.8V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
-
-
Pin
State
Note pu avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
-
avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
-
avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
Pin Net Name
X2:22 DSI_B_CLK_P
X2:23 CSI_B_D0_P
X2:24
X2:25
X2:26
Ground
Ground
DSI_B_D2_N
X2:27 CSI_A_D0_N
X2:28 DSI_B_D2_P
X2:29 CSI_A_D0_P
X2:30
X2:31
X2:32
Ground
Ground
DSI_A_D0_N
X2:33 CSI_A_D1_P
X2:34 DSI_A_D0_P
X2:35 CSI_A_D1_N
X2:36
X2:37
X2:38
Ground
Ground
DSI_A_D2_P
X2:39 CSI_A_CLK_P
X2:40 DSI_A_D2_N
X2:41 CSI_A_CLK_N
X2:42
X2:43
X2:44
Ground
Ground
DSI_A_CLK_P
-
-
-
-
-
-
-
-
-
-
-
-
-
GPIO
-
-
Tegra Ball Name
DSI_B_CLK_P
CSI_B_D0_P
Tegra
Pin
Name
AH11
AL8
SFI0
DSI_B_CLK_P
CSI_B_D0_P
DSI_B_D2_N
CSI_A_D0_N
DSI_B_D2_P
CSI_A_D0_P
DSI_A_D0_N
CSI_A_D1_P
DSI_A_D0_P
CSI_A_D1_N
DSI_A_D2_P
CSI_A_CLK_P
DSI_A_D2_N
CSI_A_CLK_N
DSI_A_CLK_P
AL12
AK9
AK12
AL9
AK11
AD9
AL11
AE9
AK15
AD11
AL15
AE11
AH14
DSI_B_D2_N
CSI_A_D0_N
DSI_B_D2_P
CSI_A_D0_P
DSI_A_D0_N
CSI_A_D1_P
DSI_A_D0_P
CSI_A_D1_N
DSI_A_D2_P
CSI_A_CLK_P
DSI_A_D2_N
CSI_A_CLK_N
DSI_A_CLK_P
SFI1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI2
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
-
-
-
-
Power Rail avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
Pin
State
Note avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
-
avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
-
avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V) avdd_dsi_csi
(1.2V)
-
-
-
avdd_dsi_csi
(1.2V)
-
Pin Net Name GPIO Tegra Ball Name
X2:45 HSIC1_DATA
X2:46 DSI_A_CLK_N
X2:47 HSIC1_STROBE
X2:48
X2:49
X2:50
Ground
Ground
DSI_A_D3_P
X2:51 FORCE_nRECOVERY
X2:52 DSI_A_D3_N
X2:53
X2:54
X2:55
X2:56
USB0_D_N
Ground
USB0_D_P
DSI_A_D1_N
X2:57
X2:58
USB0_ID
DSI_A_D1_P
X2:59
X2:60
X3:1
USB0_VBUS
Ground
USB3_TX0_N
X3:2
X3:3
Ground
USB3_TX0_P
X3:4 SATA_L0_TX_P
X3:5
X3:6
Ground
SATA_L0_TX_N
X3:7 USB3_RX0_P
X3:8 Ground
-
-
-
-
-
-
-
-
-
-
-
-
-
HSIC1_DATA
DSI_A_CLK_N
HSIC1_STROBE
-
-
-
GPIO3_PI.01
DSI_A_D3_P
GPIO_PI1
DSI_A_D3_N
USB0_DN
USB0_DP
DSI_A_D1_N
USB0_ID
DSI_A_D1_P
USB0_VBUS
USB3_TX0N
USB3_TX0P
SATA_L0_TXP
SATA_L0_TXN
USB3_RX0P
Tegra
Pin
Name
AF18
AJ14
AE18
SFI0
HSIC1_DATA
DSI_A_CLK_N
HSIC1_STROBE
AF14
AA6
AG14
AH20
DSI_A_D3_P
-
DSI_A_D3_N
USB0_DN
AJ20
AD14
AK20
AE14
AL20
USB0_DP
DSI_A_D1_N
USB0_ID
DSI_A_D1_P
USB0_VBUS
AJ21 USB3_TX0N
AH21
AL27
USB3_TX0P
SATA_L0_TXP
AK27
AK21
SATA_L0_TXN
USB3_RX0P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI1
-
-
-
SFI2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
Power Rail vddio_hsic
(1.2V) avdd_dsi_csi
(1.2V) vddio_hsic
(1.2V)
-
-
Pin
State
Note
avdd_dsi_csi
(1.2V) vddio_gmi
(1.8V) avdd_dsi_csi
(1.2V) avdd_usb (3.3V)
pu
-
-
Pull-Up on SoM against 3.3V
avdd_usb (3.3V) avdd_dsi_csi
(1.2V) avdd_usb (3.3V) avdd_dsi_csi
(1.2V) avdd_usb (3.3V)
-
-
-
-
-
dvddio_pex
(1.05V) dvddio_pex
(1.05V) vddio_sata
(1.05V)
-
vddio_sata
(1.05V) dvddio_pex
(1.05V)
-
-
Pin Net Name
X3:9 USB3_RX0_N
X3:10 SATA_L0_RX_N
X3:11
X3:12
Ground
SATA_L0_RX_P
X3:13 PEX_USB3_TX1_N
X3:14
X3:15
Ground
PEX_USB3_TX1_P
X3:16
X3:17
X3:18
X3:19
USB2_D_P
Ground
USB2_D_N
PEX_USB3_RX1_N
X3:20
X3:21
Ground
PEX_USB3_RX1_P
X3:22 PEX_CLK2_P
X3:23
X3:24
Ground
PEX_CLK2_N
X3:25 PEX_TX2_N
X3:26
X3:27
Ground
PEX_TX2_P
X3:28
X3:29
X3:30
X3:31
USB1_D_N
Ground
USB1_D_P
PEX_RX2_N
X3:32 Ground
-
-
-
-
-
-
GPIO
-
-
-
-
-
-
-
-
-
-
Tegra Ball Name
USB3_RX0N
SATA_L0_RXN
SATA_L0_RXP
PEX_USB3_TX1N
PEX_USB3_TX1P
USB2_DP
USB2_DN
PEX_USB3_RX1N
PEX_USB3_RX1P
PEX_CLK2P
PEX_CLK2N
PEX_TX2N
PEX_TX2P
USB1_DN
USB1_DP
PEX_RX2N
Tegra
Pin
Name
AL21
AH27
SFI0
USB3_RX0N
SATA_L0_RXN
AJ27
AG21
SATA_L0_RXP
PEX_USB3_TX1N
-
-
SFI1
-
-
SFI2
-
-
-
-
AF21
AD20
PEX_USB3_TX1P
USB2_DP
AE20
AL23
USB2_DN
PEX_USB3_RX1N
-
-
-
AK23
AC26
AC27
AJ23
AH23
AF20
AG20
AE21
PEX_USB3_RX1P
PEX_CLK_OUT_2_P
PEX_CLK_OUT_2_N
PEX_TX2N
PEX_TX2P
USB1_DN
USB1_DP
PEX_RX2N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
-
-
-
-
-
-
-
-
-
-
Power Rail dvddio_pex
(1.05V) vddio_sata
(1.05V) vddio_sata
(1.05V) dvddio_pex
(1.05V) dvddio_pex
(1.05V) avdd_usb (3.3V)
-
avdd_usb (3.3V) dvddio_pex
(1.05V)
-
-
-
-
-
-
Pin
State
Note dvddio_pex
(1.05V) vddio_pex_ctl
(3.3V)
-
0 vddio_pex_ctl
(3.3V) dvddio_pex
(1.05V)
0
dvddio_pex
(1.05V) avdd_usb (3.3V)
-
avdd_usb (3.3V) dvddio_pex
(1.05V)
-
-
Pin Net Name GPIO Tegra Ball Name
X3:33 PEX_RX2_P
X3:34
X3:35
X3:36
X3:37
USB_VBUS_EN1_nOC
Ground
USB_VBUS_EN0_nOC
PEX_TX3_N
X3:38
X3:39
Ground
PEX_TX3_P
X3:40
X3:41
X3:42 unconnected
Ground
GPIO_PBB4
X3:43 PEX_RX3_P
X3:44 PEX_L0_nCLKREQ
X3:45 PEX_RX3_N
X3:46 PEX_L0_nRST
X3:47
X3:48
Ground
PEX_L1_nCLKREQ
X3:49 PEX_RX4_N
X3:50 PEX_L1_nRST
X3:51 PEX_RX4_P
X3:52 PEX_nWAKE
X3:53
X3:54
Ground
USB_VBUS_EN2_nOC
X3:55 PEX_TX4_P
-
GPIO3_PN.05
PEX_RX2P
USB_VBUS_EN1
GPIO3_PN.04
-
USB_VBUS_EN0
PEX_TX3N
PEX_TX3P
GPIO3_PBB.04
GPIO_PBB4
PEX_RX3P
GPIO3_PDD.02
PEX_L0_CLKREQ_N
PEX_RX3N
GPIO3_PDD.01
PEX_L0_RST_N
GPIO3_PDD.06
PEX_L1_CLKREQ_N
PEX_RX4N
GPIO3_PDD.05
PEX_L1_RST_N
PEX_RX4P
GPIO3_PDD.03
PEX_WAKE_N
GPIO3_PFF.01
USB_VBUS_EN2
PEX_TX4P
Tegra
Pin
Name
AD21
AC1
AB1
AG23
SFI0
PEX_RX2P usb_vbus_en1 usb_vbus_en0
PEX_TX3N
AF23 PEX_TX3P
AH6
AL24
AK29
AK24
AJ29
VGP4
PEX_RX3P pe0_clkreq_l
PEX_RX3N pe0_rst_l
AJ30
AL26
AJ31
AK26
AG28 pe1_clkreq_l
PEX_RX4N pe1_rst_l
PEX_RX4P pe_wake_l
AG29
AJ26 usb_vbus_en2
PEX_TX4P
SFI1
-
-
-
-
SFI2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
-
-
Power Rail dvddio_pex
(1.05V) vddio_hv (3.3V)
-
0
Pin
State
Note vddio_hv (3.3V) dvddio_pex
(1.05V)
0
dvddio_pex
(1.05V)
vddio_cam
(1.8V) dvddio_pex
(1.05V) vddio_pex_ctl
(3.3V) dvddio_pex
(1.05V) vddio_pex_ctl
(3.3V)
z
z vddio_pex_ctl
(3.3V) dvddio_pex
(1.05V) vddio_pex_ctl
(3.3V) dvddio_pex
(1.05V) vddio_pex_ctl
(3.3V) z
z
z vddio_pex_ctl
(3.3V) dvddio_pex
(1.05V)
0
-
Pin Net Name
X4:7 GPIO_PH5
X4:8 GPIO_PK2
X4:9 BL_EN
X4:10 GPIO_PJ0
X4:11 BL_PWM
X4:12 FAN_PWM
X4:13
X4:14
Ground
GPIO_PK0
X4:15 JTAG_TCK
X4:16
X4:17
Ground
JTAG_TMS
X3:56
X3:57
Ground
PEX_TX4_N
X3:58 PEX_CLK1_N
X3:59
X3:60
Ground
PEX_CLK1_P
X4:1
X4:2
Ground
GPIO_PK3
X4:3 GPIO_PK1
X4:4 GPIO_PI5
X4:5 GPIO_PI7
X4:6 GPIO_PH6
-
-
PEX_TX4N
PEX_CLK1N
PEX_CLK1P
GPIO3_PK.03
GPIO_PK3
GPIO3_PK.01
GPIO_PK1
GPIO3_PI.05
GPIO3_PI.07
GPIO_PI5
GPIO_PI7
GPIO3_PH.06
GPIO_PH6
GPIO3_PH.05
GPIO_PH5
GPIO3_PK.02
GPIO_PK2
GPIO3_PH.04
GPIO_PH4
GPIO3_PJ.00
GPIO3_PH.02
GPIO_PJ0
GPIO_PH2
GPIO3_PH.00
GPIO_PH0
GPIO3_PK.00
GPIO_PK0
JTAG_TCK
JTAG_TMS
GPIO Tegra Ball Name Tegra
Pin
Name
SFI0
AH26
AG26
PEX_TX4N
PEX_CLK_OUT_1_N
SFI1
-
-
SFI2
-
-
AF26 PEX_CLK_OUT_1_P
Y1
R5
U8
R4
U7
Y4
R2
R3
U6
AA4
Y6
SDMMC2A_DAT4
SDMMC2A_CLK
SDMMC2A_DAT1
-
SDMMC2A_DAT3
SDMMC2A_DAT2
-
SDMMC2A_DAT0
-
PM3_PWM2
PM3_PWM0
tracectl traceclk
tracedata7 -
-
tracedata3 -
-
-
-
-
-
-
tracedata2 -
-
-
AA1
H6
J5
-
JTAG_TCK
JTAG_TMS
-
-
-
-
-
-
SFI3 Power Rail Pin
State
Note
-
dvddio_pex
(1.05V) vddio_pex_ctl
(3.3V)
-
0
-
-
-
-
DTV_ERR_PSYNC
DTV_DATA
-
-
-
-
-
DTV_VALID vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) soc_therm_oc3_n
vddio_gmi
(1.8V) vddio_sys_2
(1.8V)
vddio_sys_2
(1.8V) vddio_pex_ctl
(3.3V)
0 pu pu pu pd pu pu pu pd pu pd pd pu pu
-
Pin Net Name GPIO Tegra Ball Name
X4:18 SPI4C_nCS1
X4:19 JTAG_TDI
X4:20 GPIO_PH3
X4:21 JTAG_nTRST
X4:22 GPIO_PK4
X4:23 JTAG_RTCK
X4:24 GPIO_PI2
X4:25 JTAG_TDO
X4:26
X4:27
X4:28
Ground unconnected
UART2_RXD
X4:29
X4:30
Ground
UART2_TXD
X4:31
X4:32 unconnected
UART2_nRTS
X4:33
X4:34
Ground
UART2_nCTS
X4:35 UART4_DEBUG_nCTS
X4:36 GPIO_PJ2
X4:37 UART4_DEBUG_TXD
X4:38 UART3_RXD
X4:39 UART4_DEBUG_nRTS
GPIO3_PI.04
-
GPIO_PI4
JTAG_TDI
GPIO3_PH.03
GPIO_PH3
-
GPIO3_PK.04
JTAG_TRST_N
GPIO_PK4
-
GPIO3_PI.02
-
JTAG_RTCK
GPIO_PI2
JTAG_TDO
GPIO3_PC.03
GPIO3_PC.02
GPIO3_PJ.06
UART2_RXD
UART2_TXD
UART2_RTS_N
GPIO3_PJ.05
GPIO3_PB.01
GPIO3_PJ.02
GPIO3_PJ.07
UART2_CTS_N
GPIO_PB1
GPIO_PJ2
GPIO_PJ7
GPIO3_PW.07
UART3_RXD
GPIO3_PK.07
GPIO_PK7
J2
V1
H4
T1
H5
V8
Tegra
Pin
Name
Y9
J1
SFI0
L9 IR3_RXD
M8 IR3_TXD
P4 -
M3
V5
M1
V9
W1
V4
-
UD3_CTS
-
UD3_TXD
UC3_RXD
UD3_RTS
SPI4C_CS1
JTAG_TDI
PM3_PWM3
JTAG_TRST_N
SDMMC2A_DAT5
JTAG_RTCK
SDMMC2A_DAT6
JTAG_TDO
SFI1 SFI2 tracedata6 -
-
-
-
-
-
-
tracedata5 -
-
-
-
-
-
UB3_RTS -
-
-
-
UB3_CTS -
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
-
-
-
-
-
Power Rail vddio_gmi
(1.8V) vddio_sys_2
(1.8V) vddio_gmi
(1.8V) vddio_sys_2
(1.8V) vddio_gmi
(1.8V) vddio_sys_2
(1.8V) vddio_gmi
(1.8V) vddio_sys_2
(1.8V) pu pu pd pd pu
0
Pin
State
Note pd pu
-
-
vddio_uart
(1.8V) vddio_uart
(1.8V) vddio_uart
(1.8V)
-
-
-
soc_therm_oc4_n
vddio_uart
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_gmi
(1.8V) vddio_uart
(1.8V) vddio_gmi
(1.8V) pu pu pu pu z pu z pu z
Pin Net Name GPIO Tegra Ball Name
X4:40 UART3_TXD
X4:41 UART4_DEBUG_RXD
X4:42 UART3_nRTS
X4:43 GEN2_I2C_nIRQ
X4:44 UART3_nCTS
X4:45 GEN2_I2C_SCL
X4:46
X4:47
Ground
GEN2_I2C_SDA
X4:48 SDMMC1_PWR_EN
X4:49
X4:50
Ground
CLK3_OUT
X4:51 DAP4_SCLK
X4:52 HDMI_VDD_EN
X4:53 DAP4_FS
X4:54 CAM1_PWDN
X4:55 DAP4_DIN
X4:56 CAM_nRST
X4:57 DAP4_DOUT
X4:58 CAM2_PWDN
X4:59
X4:60
Ground
BOOT_SEC
GPIO3_PW.06
UART3_TXD
GPIO3_PB.00
GPIO3_PC.00
GPIO_PB0
UART3_RTS_N
GPIO3_PC.07
GPIO3_PA.01
GPIO3_PT.05
GPIO_PC7
UART3_CTS_N
GEN2_I2C_SCL
GPIO3_PT.06
GPIO3_PU.01
GEN2_I2C_SDA
GPIO_PU1
GPIO3_PEE.00
CLK3_OUT
GPIO3_PP.07
GPIO3_PH.01
DAP4_SCLK
GPIO_PH1
GPIO3_PP.04
DAP4_FS
GPIO3_PBB.05
GPIO_PBB5
GPIO3_PP.05
DAP4_DIN
GPIO3_PBB.03
GPIO_PBB3
GPIO3_PP.06
DAP4_DOUT
GPIO3_PBB.06
GPIO_PBB6
U1
R8
Y2
U4
R9
Tegra
Pin
Name
M2
SFI0
UC3_TXD
UD3_RXD
UC3_RTS
-
UC3_CTS
I2C2_CLK
AA2
P2
I2C2_DAT
-
AH5
P3
AK6
P5
AL6
U3
P1
P7
N1 extperiph3_clk
I2S3_SCLK
PM3_PWM1
I2S3_LRCK
VGP5
I2S3_SDATA_IN
VGP3
I2S3_SDATA_OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI1 SFI2
-
-
-
-
-
-
-
UA3_RXD -
-
-
-
-
-
-
-
-
-
-
-
SFI3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Power Rail vddio_uart
(1.8V) vddio_gmi
(1.8V) vddio_uart
(1.8V) vddio_gmi
(1.8V) vddio_uart
(1.8V) vddio_gmi
(3.3V) vddio_gmi
(3.3V) vddio_uart
(1.8V) vddio_uart
(1.8V) vddio_uart
(1.8V) vddio_gmi
(1.8V) vddio_uart
(1.8V) vddio_cam
(1.8V) vddio_uart
(1.8V) vddio_cam
(1.8V) vddio_uart
(1.8V) vddio_cam
(1.8V) z z pu z pu pu
Pin
State
Note pu z pd pd pd pd pd pd pd z pd
Pull-Down
SoM
GND on against
Pin Net Name
X5:1
X5:2
SPI2D_nCS0
GEN1_I2C_SCL
X5:3
X5:4
SPI2D_MOSI
GEN1_I2C_SDA
X5:5
X5:6
X5:7
X5:8
SPI2D_SCK
Ground
SPI2D_MISO
GPIO_PW2
X5:9
X5:10
UART1_RXD
W_DISABLE
X5:11
X5:12
UART1_TXD
GPIO_PX6
X5:13
X5:14
GPIO_PO1
GEN1_I2C_nIRQ
X5:15
X5:16
X5:17
Ground
GPIO_PR5
EN_LVDS_EDP
X5:18
X5:19
X5:20
X5:21
X5:22
X5:23
X5:24
X5:25
X5:26
X5:27
GPIO_PP2
GPIO_PO2
GPIO_PR4
SPI1A_nIRQ
HEAD_DET
GPIO_PO3
Ground
SDMMC3_VDD_EN unconnected
GPIO_PO4
GPIO
GPIO3_PS.05
GPIO3_PC.04
GPIO3_PQ.00
GPIO3_PC.05
GPIO3_PS.06
Tegra Ball Name
KB_ROW13
GEN1_I2C_SCL
KB_COL0
GEN1_I2C_SDA
KB_ROW14
GPIO3_PQ.01
GPIO3_PW.02
KB_COL1
GPIO_W2_AUD
GPIO3_PS.02
GPIO3_PX.07
KB_ROW10
GPIO_X7_AUD
GPIO3_PS.01
GPIO3_PX.06
KB_ROW9
GPIO_X6_AUD
GPIO3_PO.01
GPIO3_PX.05
ULPI_DATA0
GPIO_X5_AUD
GPIO3_PR.05
GPIO4
GPIO3_PP.02
GPIO3_PO.02
GPIO3_PR.04
GPIO3_PP.01
GPIO3_PR.07
GPIO3_PO.03
KB_ROW5
DAP3_DOUT
ULPI_DATA1
KB_ROW4
DAP3_DIN
KB_ROW7
ULPI_DATA2
GPIO3_PR.00
KB_ROW0
GPIO3_PO.04
ULPI_DATA3
Tegra
Pin
Name
AF29
P6
AD30
M6
AC30
SFI0
-
I2C1_CLK
-
I2C1_DAT
-
AC28
M28
AA31
P28
AA28
N31
AF15
R31
-
-
-
-
-
-
SPI3E_DOUT (
1
)
-
Y31 -
AE17
AH15
Y29
AF17
Y30
AD17
I2S2_SDATA_OUT
SPI3E_DIN (
1
)
-
I2S2_SDATA_IN
-
SPI3E_SCK (
1
)
W31
AJ15
-
SPI3E_CS1 (
1
)
-
-
-
-
-
-
-
-
SFI1
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI2 SFI3
SPI2D_nCS0
1
-
SPI2D_DOUT (
1
)
-
-
-
SPI2D_SCK (
1
) -
-
-
-
-
-
-
-
-
SPI2D_DIN (
1
)
-
-
-
-
-
UA3_RXD
-
UA3_TXD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Power Rail Pin
State
Note vddio_sys (1.8V) vddio_uart
(1.8V) vddio_sys (1.8V) vddio_uart
(1.8V) vddio_sys (1.8V) pd z pu z pd vddio_sys (1.8V) vddio_audio
(1.8V) vddio_sys (1.8V) vddio_audio
(1.8V) vddio_sys (1.8V) vddio_audio
(1.8V) vddio_bb (1.8V) vddio_audio
(1.8V) pu pu pd pd pd pu pu pu vddio_sys (1.8V) pd
AS3722
Pin B3
PMU vddio_bb (1.8V) vddio_bb (1.8V) vddio_sys (1.8V) vddio_bb (1.8V) vddio_sys (1.8V) vddio_bb (1.8V) pd pd pu pd pu pd vddio_sys (1.8V) pd vddio_bb (1.8V) pu
Pin Net Name
X5:28
X5:29
X5:30
X5:31
X5:32
X5:33
X5:34
X5:35
X5:36 unconnected
GPIO_PR6 unconnected
SOC_ALIVE unconnected
Ground unconnected unconnected
SPI2D_nIRQ
X5:37
X5:38
X5:39
Ground
AUDIO_EN
SATA_PWR_EN
X5:40
X5:41
Ground
SATA_LED
X5:42 DAP_MCLK1
X5:43 GPIO_PW3
X5:44 DAP2_FS
X5:45
X5:46
SPI1A_MISO
DAP2_DIN
X5:47
X5:48
SPI1A_nCS0
DAP2_DOUT
X5:49
X5:50
SPI1A_SCK
DAP2_SCLK
X5:51
X5:52
SPI1A_MOSI
Ground
GPIO
GPIO3_PR.06
GPIO3_PT.00
Tegra Ball Name
KB_ROW6
KB_ROW16
Tegra
Pin
Name
SFI0
AB31 -
AA26 -
GPIO3_PX.03
GPIO_X3_AUD
GPIO3_PR.02
GPIO3_PEE.02
KB_ROW2
DAP_MCLK1_REQ
AF30
M31
-
-
GPIO3_PN.02
DAP1_DOUT
GPIO3_PW.04
DAP_MCLK1
GPIO3_PW.03
GPIO_W3_AUD
GPIO3_PA.02
GPIO3_PY.01
GPIO3_PA.04
GPIO3_PY.03
GPIO3_PA.05
GPIO3_PY.02
GPIO3_PA.03
GPIO3_PY.00
DAP2_FS
ULPI_DIR
DAP2_DIN
ULPI_STP
DAP2_DOUT
ULPI_NXT
DAP2_SCLK
ULPI_CLK
M30 -
L28
L29
J30
R30
AL18
L30
AL16
J29
AG15
M29
AK17
I2S0_SDATA_OUT extperiph1_clk
-
I2S1_LRCK
SPI1A_DIN
I2S1_SDATA_IN
SPI1A_CS0
I2S1_SDATA_OUT
SPI1A_SCK
I2S1_SCLK
SPI1A_DOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFI1 SFI2
-
-
DCA_LSPII
-
SFI3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SATA_DEV_SLP
-
-
-
-
-
-
-
-
-
-
-
-
-
Power Rail Pin
State
Note vddio_sys (1.8V) pd vddio_sys (1.8V) pd vddio_audio
(1.8V) pu vddio_sys (1.8V) vddio_audio
(1.8V) pd pd vddio_audio
(1.8V) vddio_audio
(1.8V) vddio_audio
(1.8V) vddio_audio
(1.8V) vddio_bb (1.8V) vddio_audio
(1.8V) vddio_bb (1.8V) vddio_audio
(1.8V) vddio_bb (1.8V) vddio_audio
(1.8V) vddio_bb (1.8V) pd pd pu pd z pd z pd z pd z
Pin Net Name
X5:53 SPI4C_nCS0
X5:54
X5:55
GPIO_PP0
SPI4C_MOSI
X5:56
X5:57
SPDIF_OUT
SPI4C_MISO
X5:58
X5:59
SPDIF_IN
SPI4C_SCK
X5:60 CODEC_nIRQ
Ground
Ground
+5V_SYS
+5V_SYS
+5V_SYS
+5V_SYS
+5V_SYS
+5V_SYS
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
+5V_SYS
+5V_SYS
+5V_SYS
+5V_SYS
X6:9
X6:10
X6:11
X6:12
X6:13
X6:14
X6:15
X6:16
X6:1
X6:2
X6:3
X6:4
X6:5
X6:6
X6:7
X6:8
X6:17
X6:18
X6:19
X6:20
GPIO Tegra Ball Name
GPIO3_PI.03
GPIO3_PP.00
GPIO3_PG.06
GPIO_PI3
DAP3_FS
GPIO_PG6
GPIO3_PK.05
GPIO3_PG.07
SPDIF_OUT
GPIO_PG7
GPIO3_PK.06
GPIO3_PG.05
SPDIF_IN
GPIO_PG5
GPIO3_PU.05
GPIO_PU5
Tegra
Pin
Name
V7
AA8
AA3
M4
AE15
Y8
AC4
V3
SFI0
-
I2S2_LRCK
-
SPDIF_OUT
-
SPDIF_IN
-
-
SFI1
-
-
-
-
-
-
-
-
SFI2
-
-
-
-
-
-
-
-
SFI3
SPI4C_CS0
-
SPI4C_DOUT
-
SPI4C_DIN
-
SPI4C_SCK
-
Power Rail Pin
State
Note vddio_gmi
(1.8V) vddio_bb (1.8V) vddio_gmi
(1.8V) vddio_hv (3.3V) vddio_gmi
(1.8V) vddio_hv (3.3V) vddio_gmi
(1.8V) vddio_uart
(1.8V) pu pd z pu z pd z z
Pin Net Name
X6:21
X6:22
X6:23
X6:24
X6:25
X6:26
X6:27
X6:28
X6:29
X6:30
X6:31
X6:32
X6:33
+5V_SYS
+5V_SYS
+5V_SYS
+5V_SYS
+5V_SYS
+2V5_AON_RTC
Ground
Ground
Ground
Ground
Ground
Ground
USB0_ID_PMU
X6:34
X6:35
X6:36
X6:37 unconnected
+1V8_VDDIO
+1V8_VDDIO nRESET_COM
X6:38 nPOWER_GOOD
X6:39 nRESET_PERIPH
X6:40 +VBAT_BKUP
X6:41 nONKEY
X6:42
X6:43
+3V3_SYS nWAKEUP_POWER
X6:44
X6:45
+3V3_SYS
WAKEUP_LID
X6:46 +3V3_SYS
GPIO Tegra Ball Name Tegra
Pin
Name
SFI0 SFI1 SFI2 SFI3 Power Rail Pin
State
Note
AS3722 PMU H2
AS3722
B11
PMU
Pull-Up on SoM against 2.5V
Pull-Up on SoM against 5V
Pull-UP on SoM against 1.8V
RTC
Voltage
Batterie
Pull-Up on SoM against 2.5V
pull-up required on carrier against
+2V5_AON_RTC pull-down required on carrier
Pin Net Name
X6:47 PMU_GPIOA
X6:48
X6:49
+3V3_SYS
PMU_GPIOB
X6:50
X6:51
X6:52
X6:53
X6:54
X6:55
X6:56
X6:57
X6:58
X6:59
X6:60
+3V3_SYS
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
GPIO Tegra Ball Name Tegra
Pin
Name
SFI0 SFI1 SFI2 SFI3 Power Rail Pin
State
Note
AS3722
GPIO
PMU
AS3722
GPIO
PMU
1
NVIDIA does not officially support these interfaces. You can use them on your on risk.
Section 7 Reference documents
7 Reference documents
72
In the following chapter, you can find a list of documents that will provide you with more information on the processor module and the carrier.
You can find information about the Tegra
R https://developer.nvidia.com/
Technical Reference Manual (TRM) for Tegra
R
Please note:
To access the TRM, you need to follow these steps:
1. Be registered on the NVIDIA
R
2. Apply for the Tegra
TM
Registered Developer Program through your account settings.
Avionic Design GmbH | Wragekamp 10 | 22397 Hamburg | Germany
T + 49(0)40 88 187-0 | F + 49(0)40 88 187-150 | [email protected] | www.avionic-design.de
Section 8 Contact
8 Contact
Figure 8.1: head office in Duvenstedt (Germany)
If you have any questions about the Tegra
R
Avionic Design GmbH
Wragekamp 10
22397 Hamburg
Germany
Fon: +49 40-88187-0
Fax: +49 40-88187-150
E-Mail: [email protected]
www.avionic-design.de
Avionic Design GmbH | Wragekamp 10 | 22397 Hamburg | Germany
T + 49(0)40 88 187-0 | F + 49(0)40 88 187-150 | [email protected] | www.avionic-design.de
73
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Key features
Multimedia platform
High graphic performance
Low power consumption
NVIDIA Tegra K1 SoC
DSI, CSI, eDP, USB3.0, SATA (GEN2) and HDMI interfaces
2GB DDR3L (64 Bit)
16 GB eMMC (eMMC5.0)
Frequently asked questions
The Embedded Tegra K1 Processor Module is a multimedia platform for embedded, avionic and industrial operation. Its core component is the NVIDIA Tegra K1 SoC.
The Embedded Tegra K1 Processor Module supports various interfaces, like DSI, CSI, eDP, USB3.0, SATA (GEN2) and HDMI.
The operation frequency of the Embedded Tegra K1 Processor Module is up to 2.2 GHz.
