SGS-THOMSON ST10 R166, 166, F166 16-bit Microcontroller USER MANUAL

ST10 FAMILY
16 BIT MCU
USER MANUAL
1st EDITION
APRIL 1992
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics.
As used herein :
1. Life support devices or systems are those which
(a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with
instructions for use provided with the product, can
be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can reasonably be expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
GENERAL INDEX
INTRODUCTION
FEATURES
1
ARCHITECTURAL OVERVIEW
1.1
BASIC CPU CONCEPTS AND OPTIMIZATIONS …………………………………………………
1-1
1.1.1
High Instruction Bandwidth/Fast Execution ………………………………………………………
1-1
1.1.2
High Function 8-bit and 16-bit Arithmetic and Logic Unit ……………………………………
1-2
1.1.3
Extended Bit Processing and Peripheral Control ………………………………………………
1-2
1.1.4
High Performance Branch-, Call-, and Loop Processing ……………………………………
1-2
1.1.5
Consistent and Optimized Instruction Formats …………………………………………………
1-3
1.1.6
Programmable Multiple Priority Interrupt Structure ……………………………………………
1-3
1.2
FUNCTIONAL BLOCKS ……………………………………………………………………………………
1-4
1.2.1
1.2.1.1
1.2.1.2
1.2.1.3
16-Bit CPU ……………………………………………………………………………………………………
BARREL SHIFTER ………………………………………………………………………………………………
1-4
1-4
1-4
1-4
1.2.2
Peripheral Event Controller (PEC) and Interrupt Control ……………………………………
1-4
1.2.3
Internal RAM …………………………………………………………………………………………………
1-4
1.2.4
Internal Program Memory ………………………………………………………………………………
1-4
1.2.5
Clock Generator ……………………………………………………………………………………………
1-6
1.2.6
Peripherals and Ports ……………………………………………………………………………………
1-6
2
INSTRUCTION DECODING ……………………………………………………………………………………
ARITHMETIC AND LOGIC UNIT ………………………………………………………………………………
SYSTEM DESCRIPTION
2.1
MEMORY ORGANIZATION ………………………………………………………………………………
2-2
2.2
EXTERNAL BUS CONTROLLER ………………………………………………………………………
2-2
2.3
CENTRAL PROCESSING UNIT (CPU) ………………………………………………………………
2-2
2.4
INTERRUPT SYSTEM ………………………………………………………………………………………
2-4
2.5
CAPTURE/COMPARE (CAPCOM) UNIT ……………………………………………………………
2-4
2.6
GENERAL PURPOSE TIMER (GPT) UNIT …………………………………………………………
2-5
2.7
A/D CONVERTER ……………………………………………………………………………………………
2-5
2.8
SERIAL CHANNELS ………………………………………………………………………………………
2-6
2.9
WATCHDOG TIMER …………………………………………………………………………………………
2-6
2.10
PARALLEL PORTS …………………………………………………………………………………………
2-6
4

GENERAL INDEX
3
MEMORY ORGANIZATION
3.1
INTERNAL PROGRAM MEMORY ………………………………………………………………………
3-5
3.2
EXTERNAL MEMORY ………………………………………………………………………………………
3-5
3.3
INTERNAL RAM………………………………………………………………………………………………
3-6
3.3.1
3.3.2
3.3.3
System Stack …………………………………………………………………………………………………
General Purpose Registers………………………………………………………………………………
Pec Source and Destination Pointers ………………………………………………………………
3-6
3-7
3-9
3.4
INTERNAL SPECIAL FUNCTION REGISTERS …………………………………………………… 3-10
4
ON-CHIP FLASH MEMORY ………………………………………………………………………………… 4-1
5
CENTRAL PROCSSING UNIT
5.1
INSTRUCTION PIPELINING………………………………………………………………………………
5-2
5.1.1
5.1.2
Sequential Instruction Processing …………………………………………………………………
Standard Branch Instruction Processing …………………………………………………………
5-2
5-3
5.1.3
5.1.4
Cache Jump Instruction Processing …………………………………………………………………
Particular Pipeline Effects ………………………………………………………………………………
5-3
5-4
5.2
INSTRUCTION STATE TIMES ……………………………………………………………………………
5-5
5.2.1
5.2.2
5.2.3
Time Unit Definitions ………………………………………………………………………………………
Minimum State Times ……………………………………………………………………………………
Additional State Times ……………………………………………………………………………………
5-5
5-5
5-6
5.3
CPU SPECIAL FUNCTION REGISTERS ……………………………………………………………
5-8
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.1.5
5.3.1.6
5.3.1.7
SYSCON: System Configuration Register …………………………………………………………
5.3.2
5.3.3
BUSCON1: Bus Configuration Register …………………………………………………………… 5-13
ADDRSEL1: ADDRESS SELECT REGISTER ……………………………………………………… 5-13
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
PSW: Processor Status Word …………………………………………………………………………
ALU STATUS (N, C, V, Z, E, MULIP) …………………………………………………………………………
CPU INTERRUPT STATUS (IEN, ILVL) ………………………………………………………………………
5-9
5-9
5-9
5-9
5-10
CLOCK OUTPUT PIN CONTROL (VIA CLKEN) …………………………………………………………… 5-11
NON-SEGMENTED MEMORY MODE SELECTION (VIA SGTDIS) ……………………………………… 5-11
MAXIMUM SYSTEM STACK SIZE SELECTION (VIA STKSZ) …………………………………………… 5-11
INTERNAL ROM OR FLASH MEMORY/EXTERNAL MEMORY ACCESS MODE SELECTION ………
EXTERNAL BUS TIMING CONTROL (VIA MCTC, MTTC, RWDC) ………………………………………
BYTE HIGH ENABLE PIN CONTROL (VIA BYTDIS) ………………………………………………………
READY PIN CONTROL (VIA RDYEN) ………………………………………………………………………
5-14
5-14
5-16
HOLD/HLDA/BREQ BUS ARBITRATION …………………………………………………………………… 5-16
5

GENERAL INDEX
5.3.5
IP: Instruction Pointer …………………………………………………………………………………… 5-16
5.3.6
5.3.7
CSP: Code Segment Pointer …………………………………………………………………………… 5-17
DPP0, DPP1, DPP2, DPP3: Data Page Pointers ………………………………………………… 5-18
5.3.8
5.3.8.1
5.3.8.2
CP: Context Pointer ………………………………………………………………………………………
IMPLICIT CP USE WITH SHORT 4-BIT GPR ADDRESSES ………………………………………………
5.3.9
5.3.10
SP: Stack Pointer …………………………………………………………………………………………… 5-22
STKUN: Stack Underflow Pointer …………………………………………………………………… 5-24
5.3.11
5.3.12
5.3.13
STKOV: Stack Overflow Pointer ……………………………………………………………………… 5-24
MDH: Multiply/Divide Register High Portion ……………………………………………………… 5-25
MDL: Multiply/Divide Register Low Portion ……………………………………………………… 5-25
5.3.14
5.3.15
MDC: Multiply/Divide Control Register……………………………………………………………… 5-26
ONES: Constant Ones Register ……………………………………………………………………… 5-26
5.3.16
ZEROS: Constant Zeros Register …………………………………………………………………… 5-26
6
5-20
5-20
IMPLICIT CP USE WITH SHORT 8-BIT REGISTER ADDRESSES ……………………………………… 5-20
INSTRUCTION SET OVERVIEW
6.1
SUMMARY OF INSTRUCTION CLASSES……………………………………………………………
6-1
6.1.1
6.1.2
6.1.3
Arithmetic Instructions ……………………………………………………………………………………
Logical Instructions ………………………………………………………………………………………
Boolean Bit Manipulation Instructions ………………………………………………………………
6-1
6-1
6-1
6.1.4
Compare and Loop Control Instructions ……………………………………………………………
6-1
6.1.5
6.1.6
6.1.7
6.1.8
Shift and Rotate Instructions ……………………………………………………………………………
Prioritize Instruction ………………………………………………………………………………………
Data Movement Instructions ……………………………………………………………………………
System Stack Instructions ………………………………………………………………………………
6-2
6-2
6-2
6-2
6.1.9
Jump and Call Instructions………………………………………………………………………………
6-2
6.1.10
6.1.11
6.1.12
6.1.13
Return Instruction …………………………………………………………………………………………
System Control Instructions ……………………………………………………………………………
Miscellaneous ………………………………………………………………………………………………
Software Instruction Set …………………………………………………………………………………
6-2
6-2
6-3
6-3
6.2
ADDRESSING MODES ……………………………………………………………………………………
6-3
6.2.1
6.2.2
Constants ………………………………………………………………………………………………………
Short Addressing Modes …………………………………………………………………………………
6-3
6-4
6.2.3
6.2.4
Long Addressing Mode……………………………………………………………………………………
Indirect Addressing Modes………………………………………………………………………………
6-5
6-6
6.2.5
Branch Target Addressing Modes ……………………………………………………………………
6-7
6.3
CONDITION CODE SPECIFICATION …………………………………………………………………
6-8
6

GENERAL INDEX
7
INTERRUPT AND TRAP FUNCTION
7.1
INTERRUPT SYSTEM STRUCTURE …………………………………………………………………
7-2
7.2
NORMAL INTERRUPT PROCESSING AND PEC SERVICE ……………………………………
7-4
7.2.1
7.2.1.1
7.2.1.2
Interrupt System Register Description………………………………………………………………
7-5
7-5
7-8
7.2.2
7.2.2.1
7.2.2.2
PEC Service Channels Register Description………………………………………………………
PEC CHANNEL COUNTER/CONTROL REGISTERS ………………………………………………………
PEC SOURCE AND DESTINATION POINTERS ……………………………………………………………
7-9
7-9
7-10
7.2.3
7.2.3.1
7.2.3.2
7.2.3.3
Prioritization of Interrupt and PEC Service Requests …………………………………………
ENABLING AND DISABLING OF INTERRUPT SOURCES ………………………………………………
PRIORITY LEVEL STRUCTURE ………………………………………………………………………………
EXAMPLE FOR THE USE OF THE CPU PRIORITY ………………………………………………………
7-12
7-12
7-12
7-12
7.2.4
7.2.4.1
7.2.4.2
7.2.4.3
Interrupt Procedure …………………………………………………………………………………………
INTERRUPT PROCEDURE WITH SEGMENTATION DISABLED …………………………………………
INTERRUPT PROCEDURE WITH SEGMENTATION ENABLED …………………………………………
CONTEXT SWITCHING FOR INTERRUPT SERVICE ROUTINES ………………………………………
7-14
7-14
7-14
7-15
7.2.5
7.2.6
7.2.7
Interrupt Processing via the Peripheral Event Controller PEC …………………………… 7-15
Interrupt and PEC Response Times ………………………………………………………………… 7-17
External Interrupts ………………………………………………………………………………………… 7-19
7.3
TRAP FUNCTIONS ………………………………………………………………………………………… 7-21
7.3.1
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
7.3.2.4
7.3.2.5
7.3.2.6
7.3.2.7
7.3.2.8
Software Traps ……………………………………………………………………………………………… 7-21
Hardware Traps ……………………………………………………………………………………………… 7-21
EXTERNAL NMI TRAP ………………………………………………………………………………………… 7-22
STACK OVERFLOW TRAP …………………………………………………………………………………… 7-22
STACK UNDERFLOW TRAP ………………………………………………………………………………… 7-23
UNDEFINED OPCODE TRAP ………………………………………………………………………………… 7-23
PROTECTION FAULT TRAP ………………………………………………………………………………… 7-23
ILLEGAL WORD OPERAND ACCESS TRAP ……………………………………………………………… 7-23
ILLEGAL INSTRUCTION ACCESS TRAP …………………………………………………………………… 7-23
ILLEGAL EXTERNAL BUS ACCESS TRAP ………………………………………………………………… 7-23
8
INTERRUPT CONTROL REGISTERS ………………………………………………………………………
INTERRUPT CONTROL FUNCTIONS IN THE PSW ………………………………………………………
PERIPHERALS
8.1
CAPTURE/COMPARE (CAPCOM) UNIT ……………………………………………………………
8-2
8.1.1
8.1.1.1
8.1.1.2
8.1.1.3
8.1.1.4
8.1.1.5
Timers T0 and T1 ……………………………………………………………………………………………
8-5
8-5
8-6
8-7
8-7
8-8
TIMER MODE ……………………………………………………………………………………………………
COUNTER MODE ………………………………………………………………………………………………
RELOAD …………………………………………………………………………………………………………
TIMER T0 AND T1 INTERRUPTS ……………………………………………………………………………
BLOCK DIAGRAM ………………………………………………………………………………………………
7

GENERAL INDEX
8.1.2
8.1.2.1
8.1.2.2
8.1.2.3
Capture/Compare Registers ……………………………………………………………………………
CAPTURE MODE ………………………………………………………………………………………………
8.2
GENERAL PURPOSE TIMERS (GPT) ………………………………………………………………… 8-19
8.2.1
8.2.1.1
8.2.1.2
GPT1 Block ……………………………………………………………………………………………………
GPT1 CORE TIMER T3 …………………………………………………………………………………………
GPT1 AUXILIARY TIMERS T2 AND T4 ………………………………………………………………………
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
GPT2 Block ……………………………………………………………………………………………………
GPT2 CORE TIMER T6 …………………………………………………………………………………………
8.3
A/D Converter (ADC) ……………………………………………………………………………………… 8-45
8.3.1
8.3.1.1
8.3.1.2
8.3.1.3
8.3.1.4
Conversion Modes and Operation ……………………………………………………………………
SINGLE CHANNEL CONVERSION MODE …………………………………………………………………
SINGLE CHANNEL CONTINUOUS CONVERSION …………………………………………………………
8.3.2
A/D Converter Interupt Control………………………………………………………………………… 8-49
8.4
SERIAL CHANNELS ……………………………………………………………………………………… 8-49
8.4.1
8.4.1.1
8.4.1.2
Modes of Operation…………………………………………………………………………………………
ASYNCHRONOUS OPERATION………………………………………………………………………………
8.4.2
8.4.2.1
8.4.2.2
Baud Rates ……………………………………………………………………………………………………
ASYNCHRONOUS MODE BAUD RATES ……………………………………………………………………
8.4.3
Serial Channels Interrupt Control …………………………………………………………………… 8-60
8.5
WATCHDOG TIMER (WDT) ……………………………………………………………………………… 8-61
9
8-9
8-11
COMPARE MODES …………………………………………………………………………………………… 8-12
CAPTURE/COMPARE INTERRUPTS………………………………………………………………………… 8-19
8-22
8-23
8-27
8-36
8-37
GPT2 AUXILIARY TIMER T5 ………………………………………………………………………………… 8-38
GPT2 CAPTURE/RELOAD REGISTER CAPREL …………………………………………………………… 8-41
8-45
8-48
8-48
AUTO SCAN CONVERSION MODE ………………………………………………………………………… 8-49
AUTO SCAN CONTINUOUS CONVERSION ……………………………………………………………… 8-49
8-51
8-52
SYNCHRONOUS OPERATION ……………………………………………………………………………… 8-56
8-58
8-58
SYNCHRONOUS MODE BAUD RATES …………………………………………………………………… 8-59
EXTERNAL BUS INTERFACE
9.1
EXTERNAL BUS CONFIGURATION DURING RESET……………………………………………
9-2
9.2
SINGLE CHIP MODE ………………………………………………………………………………………
9-4
9.3
16/18-BIT ADDRESS, 8-BIT DATA, NON-MULTIPLEXED BUS ………………………………
9-4
9.4
16/18-BIT ADDRESS, 8-BIT DATA, MULTIPLEXED BUS ………………………………………
9-5
9.5
16/18-BIT ADDRESS, 16-BIT DATA, MULTIPLEXED BUS ……………………………………
9-6
9.6
16/18-BIT ADDRESS, 16-BIT DATA, NON-MULTIPLEXED BUS………………………………
9-8
8

GENERAL INDEX
9.7
EXTERNAL BUS TRANSFER CHARACTERISTICS………………………………………………
9.7.1
9.7.1.1
9.7.1.2
Multiplexed Bus Transfer Characteristics …………………………………………………………
9.7.2
9.7.2.1
9.7.2.2
Non-Multiplexed Bus Transfer Characteristics …………………………………………………
NON-MULTIPLEXED BUS MEMORY READS ………………………………………………………………
NON-MULTIPLEXED BUS MEMORY WRITES ………………………………………………………………
9.8
USER SELECTABLE BUS CHARACTERISTICS ………………………………………………… 9-12
9.8.1
Programmable Memory Cycle Time ………………………………………………………………… 9-12
9.8.2
9.8.3
9.8.4
Programmable Memory Tri-State Time ……………………………………………………………… 9-14
Read/Write Signal Delay ………………………………………………………………………………… 9-16
ALE signal delay …………………………………………………………………………………………… 9-17
9.8.5
Switching between the Bus Modes. ………………………………………………………………… 9-18
9.9
EXTERNAL MEMORY ACCESS VIA THE DATA READY SIGNAL…………………………… 9-19
10
9-9
9-9
9-10
MULTIPLEXED BUS MEMORY WRITES …………………………………………………………………… 9-10
MULTIPLEXED BUS MEMORY READS ………………………………………………………………………
9-10
9-11
9-11
PARALLEL PORT
10.1
PORTS 0 THROUGH 4 …………………………………………………………………………………… 10-1
10.1.1
Port 0 and Port 1 …………………………………………………………………………………………… 10-4
10.1.2
10.1.3
10.1.3.1
10.1.3.2
10.1.3.3
10.1.3.4
Port 2 …………………………………………………………………………………………………………… 10-6
Port 3 …………………………………………………………………………………………………………… 10-10
PORT 3 PINS T0IN, T2IN, T3IN, T4IN, T3EUD, CAPIN, AND READY …………………………………… 10-11
PORT 3 PINS T3OUT, T6OUT, TXD0, TXD1, WR, CLKOUT ……………………………………………… 10-12
PORT 3 PIN BHE ……………………………………………………………………………………………… 10-13
PORT 3 PINS RXD0 AND RXD1 ……………………………………………………………………………… 10-14
10.1.4
Port 4 …………………………………………………………………………………………………………… 10-15
10.2
PORT 5 ………………………………………………………………………………………………………… 10-16
11
SYSTEM RESET
11.1
RSTIN and RSTOUT Pins ………………………………………………………………………………… 11-1
11.2
RESET VALUES FOR ST10x166 REGISTERS …………………………………………………… 11-2
11.3
WATCHDOG TIMER OPERATION AFTER RESET ……………………………………………… 11-3
11.4
PORTS AND EXTERNAL BUS CONFIGURATION DURING RESET ……………………… 11-3
11.5
INITIALIZATION SOFTWARE ROUTINE …………………………………………………………… 11-4
11.6
THE BOOT-STRAP MODE ……………………………………………………………………………… 11-4
9

GENERAL INDEX
12
POWER REDUCTION MODE
12.1
POWER DOWN MODE …………………………………………………………………………………… 12-1
12.2
IDLE MODE …………………………………………………………………………………………………… 12-1
12.3
STATUS OF OUTPUT PINS DURING IDLE AND POWER DOWN MODE ………………… 12-2
13
SYSTEM PROGRAMMING
13.1
INSTRUCTIONS PROVIDED AS SUBSETS OF INSTRUCTIONS …………………………… 13-1
13.1.1
13.1.2
Directly Substitutable Instructions …………………………………………………………………… 13-1
Modification of System Flags ………………………………………………………………………… 13-1
13.1.3
External Memory Data Access ………………………………………………………………………… 13-1
13.2
MULTIPLICATION AND DIVISION……………………………………………………………………… 13-2
13.3
BCD CALCULATIONS …………………………………………………………………………………… 13-3
13.4
STACK OPERATIONS……………………………………………………………………………………… 13-3
13.4.1 Internal System Stack …………………………………………………………………………………… 13-3
13.4.1.1 USE OF STACK UNDERFLOW/OVERFLOW REGISTERS ……………………………………………… 13-4
13.4.2
User Stacks …………………………………………………………………………………………………… 13-5
13.5
REGISTER BANKING ……………………………………………………………………………………… 13-5
13.6
PROCEDURE CALL ENTRY AND EXIT ……………………………………………………………… 13-5
13.6.1
Passing Parameters on the System Stack ………………………………………………………… 13-5
13.6.2
Cross Segment Subroutine Calls …………………………………………………………………… 13-5
13.6.3
Providing Local Registers for Subroutines ……………………………………………………… 13-6
13.7
TABLE SEARCHING ……………………………………………………………………………………… 13-7
13.8
PERIPHERAL CONTROL AND INTERFACE ……………………………………………………… 13-7
13.9
FLOATING POINT SUPPORT …………………………………………………………………………… 13-7
13.10
TRAP/INTERRUPT ENTRY AND EXIT………………………………………………………………… 13-7
10

GENERAL INDEX
APPENDICES
A
INSTRUCTION SET
A.1
DEFINITIONS …………………………………………………………………………………………………
A-1
A.1.2
Instruction Name ……………………………………………………………………………………………
A-1
A.1.3
Syntax …………………………………………………………………………………………………………
A-1
A.1.4
Operation / Description……………………………………………………………………………………
A-1
A.1.5
Data Types ……………………………………………………………………………………………………
A-2
A.1.6
Condition Flags ………………………………………………………………………………………………
A-2
A.1.7
Addressing Modes …………………………………………………………………………………………
A-3
A.1.8
Format …………………………………………………………………………………………………………
A-4
A.1.9
Number of Bytes ……………………………………………………………………………………………
A-4
A.2
SINGLE INSTRUCTION DESCRIPTION ………………………………………………………………
A-4
B
REGISTERS
B.1
CPU GENERAL PURPOSE REGISTERS (GPRs) …………………………………………………
B-2
B.2
SPECIAL FUNCTION REGISTERS Ordered by Address………………………………………
B-4
B.3
SPECIAL FUNCTION REGISTERS ALPHABETICAL ORDER ……………………………… B-12
C
APPLICATION EXAMPLE
EXTERNAL BUS AND MEMORY CONFIGURATIONS……………………………………………
C-1
CALCULATION OF THE USER SELECTABLE BUS TIMING PARAMETERS ……………
C-6
……………………………
D-1
…………………………………………………………………
E-1
D
APPLICATION NOTE, PROGRAMMING FLASH MEMORY
E
EXAMPLE BOOT-STRAP LOADER
F
DATASHEETS
ST10F166
ST10166 and ST10R166
11

INTRODUCTION
The rapidly growing area of embedded control applications represents one of the most time-critical
operating environments for today’s microcontrollers. Complex control algorithms must be processed
based on a large number of digital as well as analog input signals, and the appropriate output signals
must be generated within a defined minimum response time. With the increasing complexity of
embedded control applications, a significant increase in CPU performance and peripheral functionality over conventional 8-bit controllers is required of microcontrollers.
Driven by the non-volatile FLASH memory technology developed internally by SGS-THOMSON
Microelectronics, the new ST10 family of 16-bit CMOS microcontrollers achieves this high performance goal. The ST10 family offers a 16 bit core, FLASH/ROM and RAM capabilities, and advanced
peripheral functions.
The real 16-bit core of the ST10 family combines the advantages of both RISC and CISC processors.
It consists of a RISC-like architecture with a 16-bit ALU, 4 stages of instruction pipeline and dedicated
Special Function Registers (SFRs) and a CISC-like instruction set for the high performance CPU (10
million instructions per second).
Intelligent peripherals have been integrated to reduce the need for CPU intervention to a minimum
extent. The ST10 family includes a 10 channel Analog to Digital Converter with 10 bits of resolution
and 9.75µs of conversion time, Multifunction Timers, a Capture/Compare unit, 2 serial channels
(USARTs) offering 625Kbaud in full duplex asynchronous communication and 2.5Mbaud in half
duplex synchronous communication, an 8 channel Peripheral Event Controllerallowing data transfer
in only 1 instruction cycle time and 76 I/O lines with individual bit addressability.
Based on a von Neumann architecture, up to 256Kbytes of linear address space for code and data
can be accessed with the External Bus Controller interface.
This high performance 16 bit microcontroller family with its different sets of on-chip peripherals and
the FLASH memory technology meet the requirements of real-time control applications such as
automotive engine control, industrial control and data communication.
In addition, many applications require program or data updating during the product life. In the same
way it can be very helpful to modify the program during the developmentor production phase in many
control applications. With the on-chip Flash memory of the ST10F166, flexibility and security are
brought to these applications.
The ST10x166 family currently includes:
ST10R166 : ROMless Version
ST10166 : mask-programmable ROM-Version for volume production.
ST10F166 : reprogrammableFLASH-Version for prototyping, preproduction,small volume and reprogrammable applications.
Note: In this document, any reference to the ST10x166 can be applied to the different members of the
family unless otherwise noted. The ST10R166 is ROMless, and the ST10166 and ST10F166 are fully
compatible except for the program mode of the FLASH memory of the ST10F166. All time specifications
12

INTRODUCTION
Die photo of ST10F166 with 32K on-chip FLASH Memory
13

FEATURES
High Performance 16-Bit CPU With Four
Stage Pipeline
100ns minimum instruction cycle time, with most
instructions executed in 1 cycle
500ns multiplication (16-bit x 16bit), 1µs division
(32-bit/16bit)
High bandwidth internal data buses
Register based design with multiple variable register banks
Single cycle context switching support
256Kbytes linear address space for code and
data (von Neumann architecture)
System stack cache support with automatic stack
overflow/underflow detection
Control Oriented Instruction Set with High Efficiency
Bit, byte, and word data types
Flexible and efficient addressing modes for high
code density
Enhanced boolean bit manipulation with direct
addressability of 4Kbits for peripheral control and
user defined flags
Hardware traps to identify exception conditions
during runtime
Intelligent Peripheral Subsystems
10-Channel 10-bit A/D Converter,
9.75µs conversion time, auto scan modes
16-Channel Capture/Compare Unit with 2 independent time basesvery flexible PWM unit/event
recording unit with 5 different operating modes,
includestwo 16-bit timers/counters with 400ns
maximum resolution
2 Multifunctional General Purpose Timer Units
GPT1: three 16-bit timers/ counters, 400ns maximum resolution
GPT2: two 16-bit timers/counters, 200ns maximum resolution
2 Serial Channels (USART) with independent
baud rate generators provide parity, framing, and
overrun error detection
Watchdog Timer with programmable time intervals
76 I/O Lines With Individual Bit Addressability
Tri-stated in input mode, Schmitt-Trigger characteristics
Different Temperature Ranges
-0 to 70°C, -40 to 85°C, -40 to 105°C
Integrated On-chip Memory
1Kbyte internal RAM,
32Kbytes internal ROM (ST10166)
32Kbytes internal FLASH memory (ST10F166)
Micron Multifunctional Cmos Process
Low Power CMOS Technology, including power
saving Idle and Power Down modes
External Memory Expansion Interface
Supports 3 different bus configurations plus segmentation capability
100-Pin Metric Plastic Quad Flat Pack (PQFP)
Package
JEDEC standard, 0.65mm lead spacing, surface
mount technology
16 Priority Level Interrupt System
32 interrupt sources with separate interrupt vectors
300/500ns typical/maximum interrupt latency in
case of internal program execution
8 Channel Peripheral Event Controller (PEC)
Interrupt driven single cycle data transfer
Transfer count option (CPU interrupt generation
after a programmable number of PEC transfers)
Eliminates overhead of saving and restoring system state for interrupt requests
Complete Development Support
‘C’ Compiler
Macro Assembler, Linker, Locater, Library Manager, Object-to-Hex-Converter
Simulator for the complete simulation of the CPU
and the on-chip peripherals
Real-Time In-Circuit Emulator
Flash programming board for ST10F166
Evaluation Board with monitor program
14

NOTES:


CHAPTER 1
ARCHITECTURAL OVERVIEW
1. ARCHITECTURAL OVERVIEW
This chapter contains an overview of the 1.1.1 High Instruction Bandwidth/Fast
ST10x166’s architecture with combines advan- Execution
tages of both RISC and CISC processors in a very To achieve the desired performance, a goal of apwell-balanced way. It introduces the features proximately one instruction executed during each
which do in sum result in a high performance mi- machine cycle was set for the core CPU. Primarily,
crocontroller which is the right choice not only forthis goal has been reached except for branch-,
today’s applications, but also for future
engineermultiply-or divide ins
tructions. These instructions,
ing challenges.
however, have also been optimized. For example,
branch instructions only require additionalmaan
chine
cycle
when
a
branch
is
taken,
and most
1.1 BASIC CPU CONCEPTS AND
branches taken in loops require no additional maOPTIMIZATIONS
chine cycles.
To meet the demand for greater performance and The instruction cycle time has been dramatically
pipelining.
flexibility, a number of areas has been optimized in reduced through the use of instruction
the processor core. These are summarized below, This techniqueallows the core CPU to process
portions of multiple sequential instruction stages in
and described in detail in the
followingsections:
parallel. The ollowing
f
four stagepipelineprovides
the
optimumbalancingfor
the ST10x166 family’s
High Instruction Bandwidth/Fast Execution
High Function 8-bit and 16-bit Arithmetic and CPU core:
Logic Unit
Extended Bit Processing anderipheralControl
P
FETCH:
In this stage, an instruction is
High Performance Branch-, Call-, and Loop
fetched from the internal ROM or
Processing
RAM, or from the external memory
Consistent and Optimized Instruction Formats
based on the current IP value.
Programmable Multiple Priority Interrupt StrucDECODE:
In this stage, the previously
ture
fetched instruction is decoded
and the requiredoperandsare
fetched.
1/6
1 - Architectural Overview
EXECUTE:
In this stage, the specified operat- 1.1.3 Extended Bit Processing and Peripheral
ion is performed on the previously Control
fetchedoperands.
A large number of instructions has been dedicated
WRITE BACK: In this stage, the result is written to bit processing. These instructions provide effito the specified location.
cient control and testing of
peripheralswhile enhancing
datamanipulation.Unlike
many current
If this techniquewere not used, each instruction
would require four machine cycles. This increased microcontrollers, these instructions provide direct
performance allows a greater number of tasks and access to twooperands in the bit-addressable
space withoutrequiringmovement into temporary
interrupts to be processed.
flags.
The same logical instructions
availablefor words
1.1.2 High Function 8-bit and 16-bit
and bytes are also supported for bits. This allows
Arithmetic and Logic Unit
the user to compare and modify a control bit for a
Most internal execution blocks have been opti- peripheralin one instruction. Multiple bit shift inmized to performoperationson either 8-bit or 16- structions have beenincludedto avoid long inbit quantities. Once thepipelinehas been filled, struction streams of single bit shift operations.
one instruction is completed per machine cycle ex-These are also performed in a single machine cycept for multiply and divide. An advanced Booth al-cle.
gorithm has been incorporated to allow four bits toIn addition, bit field instructions have been probe multiplied and two bits to be divided per ma- vided which allow the modification of multiple bits
chine cycle. Thus, theseoperationsrequire four
from one operand in a single instruction.
and nine machine cycles, respectively, to perform
a 16-bit by 16-bit (or 32-bit by 16-bit) calculation
plus one machine cycle to setup and adjust the op- 1.1.4 High Performance Branch-, Call-, and
erands and the result. Even these longer multiply Loop Processing
and divide instructions can be interrupted duringDue to the high percentage of branching in controltheir execution to allow for very fast interrupt re- ler applications, branch instructions have been opsponse. Instructions have also been provided to al- timized to require one extra machine cycle only
low byte packing in memory while
providingsign
when a branch is taken. This is implemented by
extension of bytes for word wide arithmetic opera- precalculating the target address while
decoding
tions. The internal bus structure also allows trans-the instruction. To decrease loop execution overfers of bytes or words to or from
peripheralsbased
head, three enhancements have been provided.
on the peripheralrequirement
s.
The first solution provides single cycle branch exeA set of consistent flags is automatically updated incution after the first iteration of a loop.
the PSW after each arithmetic, logical, shift, or Thus, only one machine cycle is lost during the
movement operation. These flags allow
branching
execution of the entire loop.In loops which fall
on specific conditions. Support for both signed andthrough upon completion, no machine cycles are
unsigned arithmetic is provided through user-spe- lost when exiting the loop. No special instructions
cifiable branch tests. These flags are also pre- are required to perform loops, and loops are autoserved automatically by the CPU upon entry to an matically detected during execution of branch ininterrupt or trap routine.
structions.
2/6

1 - Architectural Overview
The second loopenhancement allows the detec- 2) Avoid complexencodingschemes byplacing
tion of the ends of tables and avoids the use of two
operands in consistent fields for each instruccompare instructionsembedded in loops. One
tion. Also avoid complex addressing modes
simply places the lowest negative number at the
which are not frequently used. This decreases
end of the specific table, and specifies branching if
the instruction decode time while also simplifyneither this value nor the compared value have
ing the development of compilers and assembeen found. Otherwise the loop is terminated if
blers.
either condition has been met. One can then test 3) Provide most frequently used instructions with
which condition has occurred. This method is deone-word instruction formats. All other instrucscribed in detail in section 13.7.
tions are placed into two-word formats. This alThe third loop enhanc
ement provides a more flexlows all instructions to be placed on word
ible solution than the Decrement and Skip on Zero
boundaries
, which alleviates the need for cominstruction which is found in many other microcon- plex alignment hardware. It also has the benetrollers. Through the use of Compare and Increfit of increasing the range for relative
branching
ment or Decrement instructions, the user can
instructions.
make comparisons to any value. This allows loop
counters to cover any range. This is particularly ad1.1.6 Programmable Multiple Priority Interrupt
vantageous in table searching.
Structure
Saving of system state is automatically performed
A number of enhancements have been included to
on the internal system stack
avoidingthe use of instructions to preserve state upon entry and exit of allow processing of a large number of interrupt
interrupt or trap routines. Call instructions push thesources. These are presented below:
value of the IP on the system stack, and require the 1) PeripheralEvent Controller (PEC): This procsame execution time as branch instructions.
essor is used to off-load many interrupt requests from the CPU. It avoids the overhead of
Instructions have also been provided to support indientering and exiting interrupt or trap routines
rect branch and call instructions. This supports imby performing single-cycle interrupt-driven
plementation of multiple CASE statement
byte or word data transfers.
branchingin assembler macros and high level languages.
2) Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at any
specified priority. Interrupts may also be
1.1.5 Consistent and Optimized Instruction
grouped, which provides the user with the abilFormats
ity to prevent similar priority tasks from interTo obtain optimum performanceainpipelinedderupting each other.
sign, an instruction set has been
designedwhich
3) Multiple Register Banks: This feature allows
incorporates concepts from Reduced Instruction
the user to specify up to sixteen general purSet Computers (RISC). These concepts primarily
pose registers located anywhere in the internal
allow fast decoding of the instructions and operRAM. A single one machine cycle instruction is
ands while reducing pipeline holds. These conused to switch register banks from one task to
cepts, however, do not preclude the use of
another.
complex instructions which are required by micro4) Interruptable Multiple Cycle Instructions: Recontroller users. he
T following goals wer
e used to
duced interrupt latency is providedallowing
by
design the instruction set:
multiple cycle instructions (multiply, divide) to
1) Provide powerful instructions to perform opbe interruptable.
erations which currently require sequences of
instructions and are frequently used. Avoid
transfer into and out of temporary registers
such as accumulators and carry bits. Perform
tasks inparallelsuch as saving state upon entry to interrupt routines or
ubroutines
s
.
3/6

1 - Architectural Overview
1.2 FUNCTIONAL BLOCKS
1.2.1.3 BARREL SHIFTER
A 16-bit barrel shifter provides multiple bit shifts in
The ST10x166 family clearly separates peripher- a single cycle. Rotates and arithmetic shifts are
als from the core.
also supported.
This structure permits the maximum number of operations to be performed in
paralleland allows peripherals to be added or deleted from family 1.2.2 Peripheral Event Controller (PEC) and
members without modifications to the core. Each Interrupt Control
functional block processes data
independentlyand
Each interrupt source is prioritized every machine
communicates information over common buses. cycle in the interrupt control block. If PEC service is
Functional blocks in the CPU core are controlled selected, a PEC transfer is started. If CPU interrupt
by signals from the instruction decode logic. Pe- service is requested, the current CPU priority level
ripheralsare controlled by data written to the Spe- stored in the PSW register is tested to determine
cial Function Registers (SFRs).
whether a higher priority interrupt is currently
being
ac
The following sections describe the functional serviced. When an interrupt is knowledged,the
current state of the machine is saved on the interblocks of the ST10x166 and interac
tions between
nal system stack and the CPU branches to the systhese blocks.
tem specific vector for the peripheral.
The PEC contains a set of SFRs which store the
1.2.1 16-Bit CPU
count value and control bits for eight data transfer
channels. In addition, the PEC uses a dedicated
area of RAM which contains the source and desti1.2.1.1 INSTRUCTION DECODING
nation addresses. The PEC is controlled similar to
Instruction dec
oding is primarily generated from any other peripheral through Rs
SF containingthe
PLA outputs based on the selected opcode. No mi- desired configuration of each channel.
crocode is used andeach pipeline stage receiv
es
control signals staged in control registers from the
decode stage PLAs.Pipelineholds are primarily 1.2.3 Internal RAM
caused by wait states for external memory ac- A dual port 512 by 16-bit internal RAM provides
cesses and cause theholdingof signals in the con- fast access to General Purpose Registers (GPRs),
trol registers. Multiple-cycle instructions are user data, and system stack. A unique
decoding
performed through instruction injection and simplescheme provides flexible user register banks in the
internal state machines which modify required con-internal memory while optimizing the
emaining
r
trol signals.
RAM for user data.
Hardware detection of the selected memory space
1.2.1.2 ARITHMETIC AND LOGIC UNIT
is placed at the internal memory decoders and alAll standard arithmetic and logical operations are lows the user to specify any address directly or inperformed in a 16-bit ALU. In addition, for byte op- directly and obtain the desired data without using
erations, signals are provided from bits six and temporary registers or special instructions.
seven of the ALU result to correctly set the condition flags. Multiple precis
ion arithmetic isprovided
1.2.4 Internal Program Memory
through a ‘CARRY-IN’ signal to the ALU from previously calculated portions of the desired opera- For both code and data storage, the ST10166 protion. Booth multiplication and division are vides an internal ROM of 32 Kbytes and the
supported by an ext
ended ALU and a bit shifter ST10F166 provides an internal FLASH memory of
placed on two coupled 16-bit registers, MDL and 32Kbytes. For both, this memory area is connected
double
MDH. All targets for branch calculations are also to the CPU via a 32-bit bus. Thus, an entire
word instruction can be fetched in one machine cycomputed in the central ALU.
cle. Program execution from the on-chip ROM or
FLASH memory is the fastest of all possible alternatives.
4/6

1 - Architectural Overview
Figure 1-1. Functional Block Diagram
Clock
Generator
Watchdog
Timer
ROM or FLASH
RAM
32KBytes
1KByt e
10-Channel
16-Bit CPU
10-Bit A/D
Converter
16-Bit
Timer T0
Interrupt & PEC Control
Serial
Channel
16-Channel
Capture /
Compare
Unit
General Purpose
Timer Unit
GPT1
16-Bit Timer T2
General Purpose
Timer Unit
GPT2
16-Bit Timer T5
Serial
16-Bit Timer T3
16-Bit
Timer T1
16-Bit Timer T4
External Bus
Controller
ASC0
Channel
16-Bit Timer T6
ASC1
I/O Ports
VR001622
5/6

1 - Architectural Overview
1.2.5 Clock Generator
1.2.6 Peripherals and Ports
The on-chip clock generator contains a prescaler The ST10x166 also contains:
which divides the external clock frequency by 2. two blocks of general purpose timers
Thus, the internal clock frequency is half the exter- nal clock frequency (i.e.OSC
f = 40MHz at internal
- a capture/compare unit
clock frequency = 20MHz). Two separated clocks - two serial interface
channels
are generated for the CPU and the peripheral part
an
A/D
converter
of the chip. While the CPU clock is stopped during wait statesor during the idle mode,
the peripheral
- a watchdog timer
clock keeps running. Both clocks are switched off six I/O ports with a total of 76 I/O lines
when the power down mode is entered.
Each peripheral also contains a set of SFRs which
control the functionality of the ipheral
per
and tem
porarily store intermediate data results. Each peripheral has an associated set of status flags.
Individually selected clock signals are
generated
for each peripheralfrom binary multiples of the
system clock.
6/6

CHAPTER 2

SYSTEM DESCRIPTION
2. SYSTEM DESCRIPTION
In this chapter, a summary of the ST10x166 is pre- advanced, high bandwidth internal bus structure of
sented. Thefollowingblock diagram gives an over- the ST10F166.
view of the different on-chip components and ofthe
Figure 2-1. Block Diagram
16
Internal
FLASH EPROM
32KBytes
ST10F166
32
Internal
RAM
1KBytes
16
CPU - CORE
16
PEC
...........
Interrupt Controller
O SC
XTAL
Watchdog
16
16
GPT1
Ext.
16
Bus
Port 0
Control
10-bit USART USART
ADC
ASC0 ASC1
...
BRG
BRG
GPT2
CAPCOM
T2
T1
T3
T5
T4
T6
...
T0
2
Port 4
Port 1
16
Port 5
Port 3
10
16
Port 2
16
VR 00 16 13
1/6
2 - System Description
In the non-multiplexed bus mode, Port 1 is used as
an output for addresses and Port 0 is used as an
The memory space of the ST10x166 is configured input/output for data; the upper half of Port 0 can
not be used for general purpose I/O in the 8-bit
in a Von Neumann architecture
which meansthat
code memory, data memory, registers and I/O data bus mode. In the multiplexed bus modes, one
ports areorganizedwithin the same linear address 16-bit port, Port 0, is used as an input/output for
space which currently includes 256Kbytes. Ad- both addresses and data.
dress space expansion to 16 Mbytes provided
is
Important timing characteristics of the external bus
for future versions. The entire memory space can interface (Memory Cycle Time, Memory Tri-State
be accessedby byte or by word. Particular portions Time and Read/Write Delay) have been made proof the on-chip memory haveadditionallybeen
grammable to allow the user the adaption of a wide
made directly bit addressable.
range of different types of memories. Access to
The ST10166 contains 32Kbytes of mask-pro- very slow memories is supported via a particular
grammable on-chip ROM for code or constant ‘Ready’ function.
data.
For applications which require less than 64Kbytes
The ST10F166 contains 32Kbytes of reprogram- of memory space, a non-segmented memory
mable on-chip FLASH memory for code or con- model can be selected. In this case, all memory locations can be addressed by 16 bits, and thus Port
stant data.
tput for the two most sigA large dual port RAM of 1Kbyte is contained on all 4 isnot needed as an ou
nificant
address
bits
(A17
and A16), as is the case
members of the ST10x166 family. This internal
when
using
the
segmented
memory model.
RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can 2.3 CENTRAL PROCESSING UNIT (CPU)
consist of up to 16
wordwide(R0 toR15) and/or bytewide (RL0, RH0, ..., RL7, RH7) called General The main core of the CPU consists of a 4-stage inPurpose Registers (GPRs).
structionpipeline, a 16-bit arithmetic and logic unit
Aditionalhardware
512 bytes of the address space are reserved for (ALU) and dedicated SFRs. d
and divide
the Special Function Register (SFR) area. SFRs has been spent for a separate multiply
are wordwideregisters which are used for control- unit, a bit-mask generator and a barrel shifter.
ling and monitoring functions of the different on-Based on these hardware provisions, most of the
chip units. 118 SFRs are currently implemented. ST10x166’s instructions can be executed in just
Unused SFR addresses are reserved for future one machine cycle which requires 100ns at 20MHz
members of the ST10x166 family.
CPU clock. For example, shift and rotate instrucIn order to meet the needs of designs where more tions are always processed during one machine
memory is required than is provided on chip, up tocycle independentof the number of bits to be
256Kbytes of external RAM and/or ROM can be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as
connected to the microcontroller.
well: A 32-bit/16-bit division in
µs,
1 a 16-bit x 16-bit
multiplication in 0.5
µs, and branches in 200ns. An2.2 EXTERNAL BUS CONTROLLER
other pipelineoptimization, the ‘Jump Cache’, allows reducing the execution time of repeatedly
All of the external memory accesses are performed performed jumps in a loop from 200ns to 100ns.
by a particular on-chip External Bus Controller
(EBC). It can be programmed to either the Single The CPU disposes of an actual register context
wordwideGPRs which are
Chip Mode when no external memory is required, consisting of up to 16
physically
allocated
within
the on-chip RAM area.
or to one of four different external memory access
A
Context
Pointer
(CP)
register
determines the
modes, which are as follows:
base address of the active register bank to be ac- 16-bit/18-bit Addresses, 16-bit Data, Non-Multi- cessed by the CPU at the time. The number of regplexed
ister banks is only restricted by the
available
internal
RAM
space.
For
easy
parameter
passing,
Addresses, 16-bit Data, Multi- 16-bit/18-bit
register banks can also be organized to overlap.
plexed
2.1 MEMORY ORGANIZATION
-
16-bit/18-bit Addresses, 8-bit Data, Multiplexed
16-bit/18-bit Addresses, 8-bit data, Non-Multiplexed
2/6

2 - System Description
Figure 2-2. CPU Block Diagram
CPU
SP
MDH
STKOV
32
R15
1K
Bytes
RAM
MDL
STKUV
32K
Bytes
FLASH
EPROM
16
R15
Exec. Unit
Mul./Div.-HV
Instr. Ptr.
Bit-Mask Gen.
General
Purpose
Instr. Reg.
ALU
4 - Stage
Pipeline
Registers
(16-bit)
Barrel-Shifter
R0
PSW
SYSCON
Data Page Ptr.
Context Ptr.
Code Seg. Ptr.
R0
16
VR 0 01 614
A system stack of up to 512 bytes is provided as a - Compare and Loop Control Instructions
storage for temporary data. The system stack is al- Shift and Rotate Instructions
located in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two - Prioritize Instruction
separate SFRs, STKOV and STKUN, are implicitly - Data Movement Instructions
compared against the stack pointer value upon System Stack Instructions
each stack access for the detection of a stack over- flow or underflow.
- Jump and Call Instructions
The high performance offered by the hardware im- - Return Instructions
plementation of the CPU can efficiently be utilized System Control Instructions
by a programmer via the highly functional
ST10x166 instruction set which includes the fol- - MiscellaneousInstructions
The basic instruction length is either 2 or 4 bytes.
lowing instruction classes:
Possible operand types are bits, bytes and words.
- Arithmetic Instructions
A variety of direct, indirect or immediate addressing modes are provided to specify the required op- Logical Instructions
erands.
Boolean
Bit
M
anipulat
i
on
Instructions
-
3/6

2 - System Description
2.4 INTERRUPT SYSTEM
bit in the trap flag register (TFR). Except another
higher prioritized trap service being in progress, a
With an interrupt response time within a range from hardware trap will interrupt any actual program
just 250ns to 500ns (in case of internal program execution. In turn, hardware trap services can norexecution), the ST10x166 is capable of reacting mally not be interrupted by standard or PEC intervery quickly to the occurrence of non-deterministicrupts.
events.
The architecture of the ST10x166 supports several 2.5 CAPTURE/COMPARE (CAPCOM) UNIT
mechanisms for fast and flexible response to service requests which can be generated from various The CAPCOM unit supports generation and consources internal or external to the microcontroller.trol of timing sequences on up to channelswith
16
Any of these interrupt requests can be pro- a maximum resolution of 400ns. The CAPCOM
grammed to be serviced by the Interrupt Controller unit is typically used to handle high speed I/O tasks
or by the PeripheralEvent Controller (PEC).
such as pulse and waveform generation, pulse
In contrast to a standard interrupt service where width modulation (PWM), Digital to Analog (D/A)
the current program executionsuspended
is
and a
conversion, software timing, or time recording relabranch to the interrupt vector table is performed, tive to external events.
just one cycle is ‘stolen’ from the current CPU ac- Two 16-bit timers (T0/T1) with reload registers protivity to perform a PEC service. A PEC service im- vide two independenttime bases for the capplies a single byte or word data transfer between ture/compare register array.
any two memory locations with an additional increment of either the PEC source or the destination The input clock for the timers is programmable to
pointer. AnindividualPEC transfer counter is im- several prescaled values of the internal system
plicitly decremented for each PEC service except clock, or may be derived from an overflow/underwhen performing in the continuous transfer mode.flow of timer T6 in module GPT2.
When this counter reaches zero, a standard inter- This provides a wide range of variation for the timer
rupt is performed to the corresponding source re-period and resolution and allows precise adjustlated vector location. PEC services are very well ment to the application specific requirements. In
suited, for example, for supporting the transmis- addition, an external count input for CAPCOM
sion or reception of blocks of data, or for transfer-timer T0 allows eventschedulingfor the capring A/D converted results to a memory table. The ture/compare registers relative to external events.
ST10x166 has 8 PEC channels each of which ofThe capture/compare register array contains 16
fers such fast interrupt-driven data transfer capa- dual purpose capture/compare registers, each of
bilities.
which may beindividuallyallocated to either CAPA separate control register which contains an inter- COM timer T0 or T1, and programmed for capture
rupt request flag, an interrupt enable flag and an in- or compare function. Each register has one port
terrupt priority bitfield, exists for each of the pin associated with it which serves as an input pin
possible interrupt sources. Via its related register,for triggering the capt
ure function, or as an output
each source can be programmed to one of sixteen pin to indicate the occurrence of a compare event.
interrupt priority levels. Once having been ac- When a capture/compare register has been secepted by the CPU, an interrupt service can only lected for capture mode, the current contents of the
be interrupted by a higher prioritized service reallocated timer will be latched (‘captured’) into the
quest. For the standard interrupt processing, each
capture/compare register in response to an exterof the possible interrupt sources has a dedicated
nal event at the port pin which is associated with
vector location.
this register. In addition, a specific interrupt request
Software interrupts are supported by means of the for this capture/compare register is generated.
‘TRAP’ instruction in combination withindividual
an
Either a positive, a negative, or both a positive and
trap (interrupt) number.
a negative external signal transition at the pin can
The ST10x166 also provides an excellent mecha- be selected as the triggering event. The contents
nism to identify and to process exceptions or errorof all registers which have been selected for one of
the five compare modes are cont
inuouslycomconditions that arise during run-time,
called ‘Hardware Traps’. Hardware traps cause immediate pared with the contents of the allocated timers.
non-maskable system reaction which is similiar to When a match occurs between the timer value and
a standard interrupt service (branching to a dedi- the value in a capture/compare register, specific
cated vector table location). The occurrence of a actions will be taken based on the selected comhardware trap is additionally signified by a individualpare mode.
4/6

2 - System Description
cludes two timers (T5, T6) and a capture/reload
register (CAPREL). Both timers can
independently
The GPT unit represents a very flexible multifunc- count up or down, clocked with an input clock
tional timer/counter structure which may be used forwhich is derived from a programmable prescaler.
many different time related tasks such as event tim- Concatenation of the timers is supported via the
ing and counting, pulse width and duty cycle meas-output toggle latch of timer T6, which changes its
urement, pulse generation, or pulse multiplication. state on each timer overflow/underflow.
The GPT unit incorporates five 16-bit timers which The state of this latch may be used to clock timer
are organized in two separate modules, GPT1 and T5, or it may be output on a port pin. Overflows/unGPT2. Each timer in each module may operate inde- derflows of timer T6 can additionally be used to
pendently in a number of different modes, or may be clock the CAPCOM timers T0 or T1, and to cause
concatenated with another timer of the same mod- a reload from the CAPREL register. The CAPREL
ule.
register may capture the contents of timer T5
Each of the three timers T2, T3, T4 of the GPT1 based on an external signal transition on the corremodule can be configured individually for one ofspondingport pin, and timer T5 will be cleared by
three basic modes of operation, which are Timer, this external transition if the clear function is enGated Timer, and Counter Mode. In Timer Mode, the abled. This allows absolute time differences to be
input clock for a timer is derived from the internalsys-measured or pulse multiplication to be performed
tem clock, divided by a programmable prescaler, without software overhead.
while Counter Mode allows a timer to be clocked in
reference to external events.
2.7 A/D CONVERTER
Pulse width or duty cycle measurementis supported
in Gated Timer Mode, where the operation of a timer For analog signal measurement, a 10-bit A/D conis controlled by the ‘gate’ level on an external inputverter with 10 multiplexed input channels and a sampin. For these purposes, each timer has one associ- ple and hold circuit has been integrated on-chip. It
ated port pin which servesas gate or clock input. The uses the method of successiveapproximation which
maximum resolution of the timers in the GPT1 mod- returns the conversion result for an analog channel
within 9.75µs @ fOSC=40MHz.
ule is 400ns (@fOSC=40MHz).
The count direction (up/down) for each timer is pro- Overrun error detection capability is provided for the
grammable by software. For timer T3, the count di- conversionresult register: an interrupt request willbe
rectionmay additionallybe altered dynamicallyby angenerated when the result of a previous conversion
external signal on a port pin to facilitate e.g. positionhas not been read from the result register at the time
tracking.
the next conversion is complete.
Timer T3 has an output toggle latch which changes For applications which require less than 10 analog
its state on each timer overflow/underflow. The state input channels, the remaining channels can be used
of this latch may be output on a port pin e.g for timeas digital input port pins.
out monitoring of external hardware components, orThe A/D converter of the ST10x166 supports four
may be used internally to clock timers T2 and T4 for different conversion modes. In the standard Single
measuring long time periods with high resolution. Channel conversion mode, the analog level on a
In addition to their basic operating modes, timers T2specified channel is once sampled and converted
and T4 may be configured as reload or capture reg- into a digital result. In the Single Channel Continous
isters for timer T3. When used as capture or reload mode, the analog level is repeatedly sampled and
registers, timers T2 and T4 are stopped. The con- converted without software intervention.
tents of timer T3 are captured into T2 or T4 in re- In the Auto Scan mode, the analog levels on a presponse to a signal at their associated input pins. specified number of channels are sequentially samTimer T3 is reloaded with the contents of T2 or T4 pled and converted. In the Auto Scan Continuous
either by an external signal or by a selectable state mode, the number of prespecified channels is retransition of its toggle latch. When both T2 and T4 peatedly sampled and converted.
are configured to alternately reload T3 with the low
and high times of a PWM signal, this signal can be The Peripheral Event Controller (PEC) may be used
constantly generated without software intervention. to automatically store the conversion results into a
table in memory for later evaluation, without requirWith its maximum resolution of 200ns ing the overhead of entering and exiting interrupt
(@fOSC=40MHz), the GPT2 module provides pre- routines for each data transfer.
cise event control and time measurement. It in2.6 GENERAL PURPOSE TIMER (GPT) UNIT
5/6

2 - System Description
2.8 SERIAL CHANNELS
When the software has been
designedto service
the Watchdog Timer before it overflows, the
Serial communication with other microcontrollers,Watchdog Timer times out if the program does not
processors, terminals, or external per
ipheral comprogress properly due to hardware or software reponents is provided by two serial interfaces with lated failures. When the Watchdog Timer overidentical functionality, Serial
Channel 0 (ASC0)
flows, it generates an intern
al hardware reset and
and SerialChannel1 (ASC1).
pulls theRSTOUT pin low in order to allow external
Both channels support
full-duplexasynchronous hardware components to reset.
communication up to 625Kbaud and half-duplex The Watchdog Timer of the ST10x166 is a 16-bit
synchronouscommunication up to 2.5 Mbaud.
timer which can either be clocked with
OSCf /4 or
/256.
The
high
byte
of
the
Watchdog
Timer
f
OSC
Two dedicated baud rate generators allow to set
register
can
be
set
to
a
prespecified
reload
value
in
up all standard baud rates without oscillator tuning.
For transmission, reception, and erroneous recep- order to allow further variation of the monitored
ed by the applition 3 separate interrupt vectors are provided for time interval. Each time it is servic
cation software, the high byte of the Watchdog
each serial channel.
Timer is reloaded. Thus, time intervals between
In the synchronousmode, one data byte is trans- 25µs and 420ms can be monitored (@f
OSC=40MHz).
mitted or received sy
nchronous
ly to a shift clock The default Watchdog Timer interval after reset is
which is generated by the ST10x166. In the asyn- 6.55ms.
chronous mode, an 8- or 9bit data frame is transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiproc- 2.10 PARALLEL PORTS
essor communication, a mechanism to dist
inguish
The ST10x166 provides 76 I/O lines which are oraddress from data bytes has been
included(8-bit
data+wake up bit mode), and a loop back option is ganized into four 16-bit I/O ports (Port0 through 3),
one 2-bit I/O port (Port 4), and one 10-bit input port
availablefor testing purposes.
A number of optional hardware error detection ca- (Port 5). All port lines are bit addressable, and all
lines of Port 0 through 4 are individually bit-wise
pabilitieshas been included to increase the
reliability of data transfers. A parity bit can automatically programmable as inputs or outputs via direction
be generated on transmission or be checked on re- registers. The I/O ports are true bidirectional ports
which are switched to the high
impedancestate
ception. Framing error detect
ion allowsthe recogwhen
configured
as
inputs.
During
the internal renition of data frames with missing stop bits. An
overrun error will be generated if the last character set, all port pins are configured as inputs.
received has not been read out of the receive buff- Each port line has one programmable alternate iner register at the time reception of a new character put or output function associated with it. Ports 0
and 1 may be used as address and data lines when
is complete.
accessing external memory, while Port 4 outputs
the additional segment address bits A16 and A17
2.9 WATCHDOG TIMER
in systems where segmentation enabledto
is
access more than 64Kbytes of memory. Port 2 is asThe Watchdog Timer of the ST10x166 represents sociated with the capture inputs/compare outputs
one of the fail-safe mechanism
s which have been
of the CAPCOM unit, and Port 3 includes alternate
implemented to prevent the controller from mal- functions of timers, serial interfaces, optional bus
functioning for longer periods of time.
control signalsWR,BHE,READY),
(
and the system
The Watchdog Timer of the ST10x166 is always clock output (CLKOUT). Port 5 is used for the anaenabledafter a reset of the chip, and can only be log input channels to the A/D converter. When anydisabledin the time interval until the EINIT (end of one of these alternate functions is not used, the
initializ
a tion) instruction has been executed. Thus, respective port line may be used as general purthe chip’s start-up procedure is always monitored. pose I/O line.
6/6

CHAPTER 3

MEMORY ORGANIZATION
3. MEMORY ORGANIZATION
The ST10x166 family’s memory space is config- The ST10x166 provides a total addressable memured in a von Neumann architecture. This means ory space of 256Kbytes.
that code and data are accessed within the same This address space is arranged in four segments
linear address space. All of the physically sepa- of 64Kbytes each, and each segment is again subrated memory areas,includingthe internal ROM
divided in four pages of 16Kbytes each. The total
(for the ST10166, internalFLASH memory for the addressable memory space can be panded
ex
up
ST10F166), internal RAM, internal Special Func- to 16 Mbytes for future members of the 10x166
ST
tion Registers (SFRs), and external memory are family.
mapped into a common address space.
Figure 3-1. Memory Segment And Page Arrangement
Data
Page
Address
3FFFFh
Code
Segment
15
14
3
13
30000h
12
2FFFFh
11
10
2
9
20000h
8
1FFFFh
7
6
1
5
10000h
4
0FFFFh
3
2
0
1
00000h
0
256KByte
Total Address
Space
1/10
3 - Memory Organization
Bytes are stored at even or odd byte addresses. followingwords. Single bits are always stored in
Words are stored in ascending memory locations the specified bit position at a word address. Bit powith the low byte at an even byte address being fol- sition 0 is the least significant bit of the byte at an
lowed by the high byte at the next odd byte ad- even byte address, and bit position 15 is the most
dress. Double words (code only) are stored in significant bit of the byte at the next odd byte adascending memory locations as two
subsequent
ly
dress.
Figure 3-2. Word, Byte And Bit Storage In a Byte Organised Memory (Example)
. . .
xxxx6h
15
14
. . . Bits . . .
8
xxxx5h
7
6
. . . Bits . . .
0
xxxx4h
Byte
xxxx3h
Byte
xxxx2h
Word (High Byte)
xxxx1h
Word (Low Byte)
xxxx0h
. . .
Table 3.1 shows how the different memory areas
are mapped into the physical 256Kbyte address
space. Basically, all of the internal memory areas
(ROM or FLASH memory, RAM, SFRs) are
mapped into partsof memory segment 0. The external memory is mapped into the rem
aining parts
2/10

xxxxFh
of memory segment 0 and into memory segments
1 through 3. Whenever the Program memory has
been disabledduring reset, or remapped to segment 1 duringinitialis
ation, the lowest 32Kbytes of
segment 0 also specify an external memory area.
3 - Memory Organization
Table 3-1. Memory Address Space Mapping
Address Space
Memory Range
Size (Bytes)
00000h - 07FFFh
Internal Program Memory Segment 0
or External Memory
08000h - 0F9FFh
External Memory
30.5K
0FA00h - 0FDFFh
Internal Memory (RAM)
1K
0FE00h - 0FFFFh
Internal SFRs
512
10000h - 17FFFh
Internal Program Memory Segment 1
or External Memory
18000h - 3FFFFh
External Memory
32K
32K
160K
The internal program memory, the internal RAM RAM can basicallybe used for the system stack
and the external memory space can be used for implementation. The highest 32 bytes of the intergeneral code and data storage. The internal SFR nal RAM (addresses from 0FDE0h to 0FDFFh) are
space is provided for control data, but not for codeprovided for the Peripheral Event
Controller(PEC)
storage.
source and destination pointers. Three memory
Note that byte units forming a single word or a dou- spaces (from 0FF00h to 0FFDFh in the internal
ble word must always be stored within the same SFR area, from 0FD00h to 0FDFFh in the internal
physical and organizational memory area (page, RAM area, and the address space occupied by the
currently selected register bank) are basically prosegment).
vided for single bit accesses.
A particular use is provided for some memory arFigure 3.3 gives an overview of the memory oreas, as follows. Addresses from
00000h to 000BFh
in code segment zero are reserved for the hard- ganization of the ST10x166. For more details
ware trap and interrupt vector jump table. The ac- about the different memory areas see the corretive General Purpose Register Bank which is spondingsubsections in this chapter. The princiselected by the Context Pointer (CP) Register can ples of the physical address generation are
be situated anywhere in the internal RAM area (ad- described in section 6.2 (Addressing Modes).
dresses from 0FA00h to 0FDFFh). Word ad- Chapter 9 is dedicated to the External Bus Controlponsiblefor all of the memory acdresses from 0FA00h to 0FBFEh in the internal ler which is res
cesses made externally.
3/10

4/10

Stack
Pointer
Context
Pointer
0FE00h
0FA00h
0FBFFh
0FD00h
0FDFFhh
0FDE0h
INTERNAL MEMORY
1KByte
Internal RAM
System Stack
GPRs
PEC Source and
Destination Pointers
512Bytes
Internal SFRs
0FF00h
0FFFFh
0FFE0h
0FFDFh
Bit Addressable
Space
00000h
07FFFh
Internal
Memory
64KBytes
External
Memory
1FFFFh
30000h
VR001615
INTERNAL/EXTERNAL MEMORY
Code Segment 1
Code Segment 3
32KBytes 17FFFh
External
Memory
20000h
or
Code Segment 2
Internal
FLASH
Memory 10000h
Code Segment 0
External
Memory
32KBytes
Internal
FLASH
Memory
or
30.5KBytes
External
Memory
0FFFFh
32KBytes
External
Memory
64KBytes
External
Memory
2FFFFh
3FFFFh
3 - Memory Organization
Figure 3-3. Memory Organization
3 - Memory Organization
3.1 INTERNAL PROGRAM MEMORY
3.2 EXTERNAL MEMORY
The Program memory is an on-chip mask-pro- Basically, the ST10x166 provides for up to 4 x
grammable ROM for the ST10166, and on-chip re- 64Kbytes of external ROM and/or RAM which may
programmable FLASH memory for the ST10F166. be organized in either 8 or 16 bits. Since a part of
The memory is organized in 8Kx32bits and the first 64Kbytes address space is already occumapped in the same segment memory: segment 0 pied by the on-chip memory areas, only 62.5Kbyduring reset or segment 1 if remapped during in- tes (30.5Kbytes for the ST10F166 and ST10166
itialization. This program memoryenabledduris
with internal program memory
enabled)of external
ing reset with the pinBUSACT high and the memory are really av
ailablein segment 0.
external bus configuration pins EBC1 and EBC0 The bus mode for external memory accessesis selow. This mode is named the Single Chip Mode. lected during reset by means of the external bus
For further details about the external bus configu- configuration pins,BUSACT, EBC1 and EBC0.
ration see chapter 9.
According to there logic levels, external memory
The internal Program memory can be used for both accesses are eitherenabledor disabledduring recode and data storage. The highest possible code set, as shown in chapter 9. The selected external
storage location in this memory is 07FFEh for 16- bus configuration is saved in the BTYP bit field in
bit instructions or 07FFCh for 32-bit instructions. Athe SYSCON register. During the
initializat
ion roubranch instruction neededto
is
cross the boundary tine, however, the user has the option change
to
between the internal Program memory to the ex- any configuration which was selected during reset.
ternal memory, otherwise this would cause errone- After the EINIT instruction, only the external bus
ous results.
configuration can be changed at any time.
No short addressing mode and bit addressable For further details about the external bus configumode are allowed for any accesses to the internal ration and control see chapter 9 “External Bus InProgram memory. For PEC data transfers, these terface”.
accesses are independentof the contents of the The external memory can be used for both code
DPP registers via the PEC source and destination and data storage. If the ST10x166 segmentation
pointers.
mode is disabled (SGTDIS bit in the SYSCON regWhenever a reset, hardware trap or interrupt oc- ister contains a ‘1’), all external memory accesses
curs, orwhenevera software TRAP instruction is are restricted to segment 0 only. Code accesses
executed, and provided that the Program memory are always made on even byte addresses. Thus,
accesses are enabled, program execution the highest possible external code storage location
branches to an implicit internal address inde- in segment 0 is either 0F9FEh for single word inpendent of the current Code Segment Pointer structions or 0F9FCh for double word instructions.
(CSP) register contents, expecting a jump vector If used for code storage, the cor
respondinglocabeing situated there. For detailed information tion must contain a branch instruction, because seabout the trap and interrupt jump vector table see quential boundary crossing from the external
section 9.1 “Interrupt System Structure”.
memory to the internal RAM space is not
provided
and
would
cause
erroneous
results.
In any segWith the possibility to remap the
internal Progr
am
ment
other
than
0,
the
highest
code
storage
locamemory to segment 1 during initialization, however,the user can configure the device with com- tion is either xFFFEh for single word instructions or
mon routines and constants programmed into the xFFFCh fordouble wordinstructions (x=1, 2, 3). If
pondinglocation
Program memory to have a fast execution speed used for code storage, the corres
and with the interrupt vector programmed into Ex- must contain a branch instruction, because segment crossing for program execution is only possiternal memory.
ble by changing the CSP register contents by
For the ST10F166, the special features of the means of the particular branch instructions JMPS
FLASH memory are described in the FLASH mem- and CALLS.
ory chapter 4.
5/10

3 - Memory Organization
External word and byte data can only be accessed is either 0FDFEh for single word instructions or
via indirect or long 16-bit addressing modes in col-0FDFCh for double word instructions. If used for
laborationwith the DPP registers. There is no short code storage, the cor
respondinglocation must
addressing mode for external operands. Any word contain a branch instruction to a memory location
data access is made to an even byte address.
other than in the SFR space, because this space is
Thus, the highest possible word data storage loca- not provided for code execution.
tions in the external memory are address 0F9FEh Any word and byte data in the internal RAM can be
in segment 0, and addresses xFFFEh in all other accessed via indirect or long 16 bit addressing
segments (x=1, 2, 3). For PEC data transfers, the modes if the selected DPP register points to data
external memory in segment 0 can be accessed in- page 3. Any word data access is made on an even
dependent of the contents of the DPP registers via byte address. Provided that the PEC source and
the PEC source and destination pointers.
destination pointers are not required, the highest
a storage location in the internal
The external memory is not provided for single bit possible word dat
RAM
is
address
0FDFEh.
For PEC data transfers,
storage, and thus it is not bit addressable.
the internal RAM can be accessed
independentof
Whenever a reset, a hardware trap or an interrupt the contents of the DPP registers via the PEC
occurs, or whenever a software TRAP instruction source and destination pointers.
is executed, and provided that internal program
memory accesses are disabled, program execu- All system stack operations are implicitly pertion branches to an implicit external memory ad- formed by means of the Stack Pointer (SP) regisdress independent of the current CSP register ter. The GPRs are accessed via short 2-, 4- or 8-bit
c
with a particular
contents, expecting a jump vector being situated addressing modes inollaboration
Context
Pointer
(CP)
register.
The
channel numthere. For detailed information about the trap and
ber
of
a
PEC
data
transfer
to
be
performed
deterinterrupt jump vector table see section 7.1 ‘Intermines which PEC source or destination pointers
rupt System Structure’.
will be implicitly accessed. All of the just
entioned
m
implicit internal RAM accesses are made independent of the current DPP register contents.
3.3 INTERNAL RAM
The upper portion of the internal RAM (addresses
The ST10x166 contains 1Kbyte of on-chip dual from 0FD00h to 0FDFFh) and the currently active
port RAM which is organized in 512x16 bytes. In- GPRs are provided for single bit storage, and thus
ternal RAM accesses are always
enabled.
they are bit addressable.
The system stack, the General Purpose Registers The followingsubsections describe in more detail
(GPRs) and the PEC source and destination point- the organization of the system stack, of the GPRs
ers are situated within the internal RAM space. Ad- and of the PEC source and destination pointers.
ditionally,the internal RAM can be used for both
code and data storage. The ST10x166 assembler
supports the reservation of the required internal3.3.1 System Stack
RAM areas according to the just mentioned par- The internal RAM address space from 0FBFFh
ticular uses.
downwardto 0FA00h is basically provided for the
Code accessesare always made on even byte ad- ST10x166’ssystem stack implementation. The dedresses. Provided that the PEC source and desti- fault maximum stack size of 256 words can easily
nation pointers are not required, the highest be reduced by h
cangingthe stack size (STKSZ) bit
possible code storage location in the internal RAM field in the SYSCON register, as shown in the following table.
6/10

3 - Memory Organization
Table 3-2. Maximum System Stack Size Selection
STKSZ
Stack Size (words)
Internal RAM Addresses (in descending order)
00b
256
0FBFFh - 0FA00h (default)
01b
128
0FBFFh - OFB00h
10b
64
0FBFFh - OFB80h
11b
32
0FBFFh - 0FBC0h
3.3.2 General Purpose Registers
For all system stackoperations
, the on-chip RAM
is accessed via the Stack Pointer (SP) register. The ST10x166’s GPRs can basically be situated
The stack growsdownwardfrom higher towards anywhere within the internal RAM address space
lower RAM address locations. Only word accesses (addresses from 0FA00h to 0FDFFh). A particular
are permitted to the system stack. A stack overflow Context Pointer (CP) register determines the base
(STKOV) and a stack underflow (STKUN) register address of the currently active register bank. This
are provided to control when the selected stack register bank may consist of up to 16 word GPRs
area is left. These two stack boundary registers (R0, R1, ..., R15) and/or of up to 16 byte GPRs
can be used not only for protection against data (RL0, RH0, ..., RL7, RH7). The sixteen byte GPRs
destruction, but also to implement a circular stackare mapped onto the first eight word GPRs, as
with hardware supported system stack
lushing
f
shown in figure 3.4.
and filling.
In contrast to the system stack, a register bank
For further details about system stack addressing grows from lower towards higher address locations
via the SP register and the use of the STKOV and and occupies a maximum space of 32bytes. Short
STKUN registers see section 5.3 ‘CPU Special 4- and 8-bit addressing modes inollaboration
c
with
Function Registers’.
the CP register support word or byte GPR ac-
7/10

3 - Memory Organization
Figure 3-4. Word and Byte GPR Organization
WORD Register R15
WORD Register R14
WORD Register R13
WORD Register R12
WORD Register R11
WORD Register R10
WORD Register R9
WORD
WORD Register R8
Register
BYTE Register RH7
BYTE Register RL7
R7
BYTE Register RH6
BYTE Register RL6
R6
BYTE Register RH5
BYTE Register RL5
R5
BYTE Register RH4
BYTE Register RL4
R4
BYTE Register RH3
BYTE Register RL3
R3
BYTE Register RH2
BYTE Register RL2
R2
BYTE Register RH1
BYTE Register RL1
R1
BYTE Register RH0
BYTE Register RL0
R0
←
CP
cessesregardless of the current DPP register con- switching and an automatic saving of the previous
tents. Additionally,each bit in the currently active context. Any number of variously sized register
register bank can be accessed
individually
.
banks, only limited by the
availableinternal RAM
aneously.
The ST10x166 supports fast register bank (con- size, can be implemented simult
text) switching. Based on that, multiple register For more details about GPR addressing via the CP
banks can physically exist in the internal RAM at register, see the chapter 5. Advanced programthe same time. However, only the register bank se- ming methods for an optimum utilization of the
lected by the CP register is active, and the remain- GPRs’ features such as Context Switching, Coning register banks are inactive at that time. text Packing, OverlappingRegister Banks, Local
Selecting a new active register bank is simply done GPRs on the system stack and so on, are deby updating the CP register. A particular Switch scribed in chapter 13 ‘System Programming’.
Context (SCXT) instruction performs register bank
8/10

3 - Memory Organization
3.3.3 Pec Source and Destination Pointers
Whenever a PEC data transfer is performed, the
The upper 16 word locations in the internal RAM pair of source and destination pointers which is selected by the specified PEC channel number is ac(addresses from 0FDE0h to 0FDFEh) are
provided
as source and destination address pointers for cessed independent of the current DPP register
contents. If a PEC channel is not used, the correPEC data transfers.
spondingpointer locations can be used for word,
As shown in figure below, a pair of source and des- byte or single bit data storage.
tination pointers is stored two
in subsequent
ly following word memory locations with the source For more details about the use of the source and
pointer (SRCPx) on the lower and with the destina- destination pointers for PEC data transfers refer to
tion pointer (DSTPx) on the higher word address chapter 7.
(x=0 to 7).
Figure 3-5. PEC Source And Destination Pointer Word Organization
FDFEh
DSTP7
FDFCh
SRCP7
SFRs
FE00h
FDFEh
FDE0h
FDDEh
PEC
Source
and
Destination
Pointers
FDE2h
DSTP0
FDE0h
SRCP0
Internal
RAM
FA00h
External
Memory
F9FEh
9/10

3 - Memory Organization
3.4 INTERNAL SPECIAL FUNCTION
REGISTERS
that the selected DPP register points to data page
3, any high byte, low byte or any word in the SFR
memory space can be accessediav an indirector
The ST10x166 provides 512bytes of on-chip Spe- long 16-bit addressing mode.
cial Function Register (SFR) space. The SFRs are The upper portion of the SFR memory space (admapped into the address space from 0FE00h to dresses from 0FF00h to 0FFDFh) contains SFRs
0FFFFh.
with many single flag control functions. Thus, this
The SFRs are not provided for general code or memory area is directly bit addressable.
data storage, but for data storage dedicated to very Some bits in already existing SFRs and some word
particular uses, mainly for contr
olling CPU, Periphlocations in the SFR address space have been reeral and I/O functions.
served for a future implementation of additional onAccording to the just mentioned control functions,chip peripherals.Any intended write access to
the SFRs are described in detail in one of the chap- such a reserved SFR memory space
would be igters 5 ‘CPU’, 8 ‘Peripherals’,or 10 ‘Parallel Ports’.
nored by the m
achine, andany intended read will
A table containinga short description, symbolic ad- supply a read result of ‘0’.
dresses, physical 18-bit and short 8-bit addresses Note that any byte write to an existing SFR causes
of the SFRs can be found in
appendixB.
the non-addressed complementary byte to be
Most commonly, an SFR can be accessed by word cleared.
via an implicit base address plus a short 8-bit offsetSome SFRs or parts of them have a restricted acaddressindependentof the current DPP register cess type such as read-only or write only. For more
contents. The low byte portion of an SFR (but not details, see the functional description of the correits high byte portion!) can be accessed via these spondingSFRs.
short 8 bit addressing modes. However,
provided
10/10

CHAPTER 4

ON-CHIP FLASH MEMORY
4. ON-CHIP FLASH MEMORY
The ST10F166 provides, in addition to the on-chip Optionallythe FLASH Memory may be protected
RAM, 32K bytes of Electrically Erasable and Re- against read and write accesses performed by
programmable non-volatile (FLASH) memory. This fetch instructions from programs running in the inmemory isorganisedas 8Kx32 bits,allowinga
ternal RAM or in external memory.
complete instruction to be read during one instruc-All control of programming and erasing the FLASH
tion fetch cycle. Data values stored can be read as memory is made from one Register, the FLASH
16 bit operands using
all addressing modes of the Control Register (FCR), which is tually
vir
mapped
ST10x166 instruction set.
into the FLASH memory space.
The FLASH memory is located in segment 0 (0 to The Presto F algorithm is used for
eliability.
r
The
07FFFh) during reset, and thus contains the typical programming time is 100
µs and erase time
power-on reset and interrupt vectors. To provide is 1s. The FLASH memory features a typical enfull flexibility in the use of the ST10F166, the durance of 100 erase/write cycles.
FLASH memory may be remapped to segment 1
WARNING: Access to or code execution from the
(10000 to 17FFFh) during init
ialization.This allows
the interrupt vectors to be programmed from exter- FLASH memory can not be performed during an
nal memory, while retaining the common routines erase or programming operation on the FLASH
e routines must
and constants programmed into the FLASH mem- memory. Therefore theappropriat
be executed from internal RAM or external memory.
ory outside of the FLASH memory address range.
For erase or program updating, the FLASH memory isorganisedinto 4 banks (12K, 12K, 6K and
2K) each of which may be
independentlyerased.
Figure 4-1. Flash Memory Architecture
HIGH VOLTAGE
MANAGEMENT
32Bits
BIDIRECTIONAL
INTERFACE
+
FLASH
TIMER
+
PROTECTION
ADDRESS
DECODER
+
READ/WRITE
CIRCUIT
MATRIX
1/8
4 - Flash Memory
FLASH MODES
Write mode:
This section describes the differents modes used As it is not possible to fetch instructions from and
with the FLASH memory and is detailed in the fol- write to the FLASH memory at the same time, a
lowing sections.
Write mode has been defined. In this mode FLASH
memory accesses can be made only with indirect
Normal mode:
addressing modes and FCR register is accessed
This mode is the standard mode of the FLASH with direct access modes.
memory. In this operation mode, the FLASH memory works exactly as the 32K bytes ROM of the In Write mode, all programming and erase operaolledby softST10166 with the same timing and functionality. tions on the FLASH memory are contr
ware with the Flash Control Register (FCR).
Therefore only instruction fetches or data
operand
reads are performed in this mode with all the ad- Therefore to write the FLASH memory, the FWE bit
dressing modes of the ST10x166 instruction set. of FCR register has to be set to “1”.
To enter the Write Program mode, the FEE bit of
No read or write operations on the FCR register FCR register has to be cleared. If FEE and FWE of
are possible in this mode, except the protection bitFCR register are set to ”1”, the Erase mode is en(RPROT) which can be modified in this mode but tered.
only from a program instruction within the FLASH
In these two modes, a Verify mode is automatically
memory.
entered when the programming or erase operation
is ended, respectivly Program Verify Mode (PVM)
and Erase Verify Mode (EVM).
Figure 4-2. Flash Modes Description
2/8

4 - Flash Memory
FLASH CONTROL REGISTER
BE1
BE0
Bank
Addresses (segment0)
During the normal operation mode, the FLASH
0
0
0
00000h to 02FFFh
memory is read as normal ROM memory with all
0
1
1
03000h to 05FFFh
addressing modes of the ST10x166.
1
0
2
06000h to 077FFh
(1)
All programming or erase operations of the
1
1
3
07800h to 07FFFh
FLASH memory are controlled via the Flash Control Register (FCR).
b7= WDWW : if set at a logical “1”, enables a 32 bit
To prevent inadvertent writing of the FLASH mem- operation, otherwise it will be a 16 bit operation. At
ory, FCR is locked and inactive during the normal ”0” during reset.
operation modes. The FLASH memory must be set
into the Write mode to provide a valid access to the b5,6 =CKCTL0,1 : select the FLASH internal timer
FCR. A key code sequence is used to enter the as shown in Table below:
Write mode.
In state “0” during reset.
The FCR is virtually located within the address
TPRG
space of the FLASH memory (it does not occupy CKCTL1
CKCTL0
1/TCL = 2 to 40MHz
an absolute address) and is only accessed with a
direct addressing mode.
0
0
4.102 TCL
When the segmented memory mode enabled,
is
4.103 TCL
0
1
4
the data page pointer must beonsideredfor
c
all
4.10 TCL
1
0
FCR accesses.
4.105 TCL
1
1
Note 1: According to the IEEE Standard on floating
gate arrays, the ollowing
f
terminology is used: writ- The maximum programming pulse (PT) allowed is
ing means a state change of the floating gate, pro- 200µs with a maximum programming time of
gramming means the
loadingof electrons onto the 2.5ms. Therefore the value ’00b’ covers all the frefloating gate, erase means the removal of elec- quency range.
The maximum erasing pulse (ET) allowed is 10ms
trons from the floating gate.
with a maximum erasing time of 30s.
At 20MHz CPU clock, ’11b’ is the rec
ommended
FCR
value.
At
1MHz
CPU
clock,
’01b’
is
the recomFlash Control Register
mended value.For all otherrequencies
f
, ’10b’ is
Reset Condition:0000h
recommended
15
14
13
12
11
10
9
8
b4 = VPPRIV: READ ONLYbit reflects the status
of VPP in the write mode. If VPP is not high
enough
R
FWMSET
BE1
BE0
for reliableprogramming, it will be at a logical “0”.
The reset value depends on the status of the exter7
6
5
4
3
2
1
0
nal Vpp on the EBC1/Vpp pin.
FBUSY
WDWW CKCTL1 CKCTL0 VPPRIV FCVPP
FEE
FWE
b3 =FCVPP: READ ONLYbit, if set at a logical “1”,
RPROT
will indicate to the user that VPP voltage has gone
below the programming threshold during a prob15 = FWMSET: will be set at a logical “1”, once gramming or erase operation. At ”0” during reset.
the Write mode has been entered. This bit must be b2 =FBUSY: READ ONLYbit is set at a logical “1”
set to ”1” at each writing of the FCR for an erase or during a program/erase operation. At ”0” during reprogramming operation. It will stay set at “1” whenset.
the operation has ended. The user must reset b2 = RPROT: WRITE ONLY bit is used when the
FWMSET to exit from the FLASH memory Write protected FLASH option is chosen. This bit, set at
mode. At ”0” during reset.
a logical “1” and with the option selected, will enb14 to b10 =R : reserved for future development, able protection. At ”1” during reset.
must be written to “0”.
b1= FEE : if set at a logical “1”, will enable the
b8,9 = BE0,1 : select the different Banks for Erase erase operation; otherwise ”0” for the programming operation. At “0” during reset.
as shown in thefollowingTable:
b0= FWE: if set at a logical “1”, will enable the writIn state “0” during reset.
ing operation; the programming or erase
operation
is selecteddependingon the state of FEE bit; otherwise ”0” for reading mode. At “0” during reset.
3/8

4 - Flash Memory
FLASH MEMORY PROTECTION
A programmable option, set by the FLASH Programming Board, prevents any access to the
FLASH memory from the internal RAM or External
memory.
When this option isenabled,the configuration of
the FLASH memory depends on the RPROT bit of
FCR.
THE WRITE MODE
To enter the Write mode a key code sequence of
two dummy write instructions has to be performed:
MOV
MEM,Rn
MOV
[Rn],Rn
where MEM is any even absolute address in the
FLASH memory space and Rn a General Purpose
Registerloaded with the even address of any value
Protection Option
RPROT
Protection
within the FLASH memory address space (segEnabled
bit
Active
ment 0 or segment 1).
Yes
1
Yes
The FWMSET bit of FCR is automatically set by
Yes
0
No
the unlock sequence.
No
1
No
Once in Write mode, all read and write accessesto
No
0
No
FCR are enabled. However, before performing the
This bit is set at “1” during reset, so any access to FIRST programming or erase operation, a delay of
the FLASH memory from the internal RAM or Ex- 10µs must be executed. The device requires this
ternal memory is disabled and access to FCR is al- time to set up the internal high voltage.
lowed only from the FLASH memory.
When the FLASH memory is mapped in segment
0, it is recommended to disable the interrupts when
To disable the protection, the
ollowinginstruction
f
has to be performed in the normal mode and from in write mode, as they would not be served if the
program code is the FLASH memory.
the FLASH memory ONLY:
When the FLASH memory is a
mpped in segMOV
MEM,Rn
ment 1, some care must be taken for the
management of interrupts during the write mode.
where MEM is any even absolute address in the
FLASH memory space. The RPROT bit of FCR (bit The unlock sequence and the 32-bit program2 of Rn) must be reset, the other bits of FCR are ming sequence must not be interrupted.
protected in the normal mode and are not affected. All erase or programming operations and verify sequences can be interrupted, if no FLASH reading is
When the protection is disabled, reading of the
performed from an external program (internal RAM
FLASH memory can be performed from all inor external memory) during the interrupt.
ternal or external memory. Access to FCR register and the FLASH programming or
erase
To exit from the Write mode to the normal mode,
operations is available only after having enthe followinginstruction has to be performed:
tered the Write mode.
MOV
MEM,Rn
where bit 15 of Rn must be “0” to disable the Write
mode (FWMSET) and MEM is any even absolute
address in the FLASH memory space.
Note: When the segmented memory mode is enabled, the data page pointer must beonsidered
c
for all FLASH memory accesses.
4/8

4 - Flash Memory
FLASH PROGRAMMING OPERATION
After the Write mode has been entered, the FLASH
memory is accessed for programming with indirect
addressing mode instructions. One or two words
(word = 16 bits) can be programmed at once, de- pendingon the WDWW bit value of FCR.
A programming operation is realized with the fol- lowing sequence:
VPPRIV bit of FCR to verify the correct
- Test
voltage on VPP.
- Load the desired value in FCR.
15
14
13
1
0
0
7
6
5
FWMSET
12
11
10
0
0
0
4
3
2
R
WDWW CKCTL1 CKCTL0 VPPRIV FCVPP
0/1
0/1
0/1
0
0
FBUSY
0
9
8
BE1
BE0
0
0
1
0
FEE
0
FWE
1
FLASH programming will automatically start.
The programming time depends on CKCTL0,1
bits of FCR. End of programming is detected
by polling onthe FBUSY bit of FCR.
Test FCVPP bit of FCR to verify that VPP had
the correct voltage dur
ing program
ming.
After programming, the FWE bit remains at a
logical “1”. The Program Verify Mode (PVM), is
then entered automatically. An
internallygenerated margin voltage is applied to the FLASH,
and reading valid data indicates the word has
been programmed successfully.
PVM needs a double read instruction with the
same operand and time to stabilize the internal circuitry.
e.g.
MOV
R1,[R2]
;
Time out of 4µs
MOV
R1,[R2]
As FCR is a virtual register, all bits previously writ-- To perform normal reading of the FLASH memory, the FWE bit must be reset.
ten must be confirmed in the same state at each
FCR writing (especially FWMSET).
A programming operation of the FLASH memory
can not be performed with a routine in the FLASH
- Write the FLASH memory
memory itself.
e.g. for one word
MOV
[Rm],R1
FLASH ERASE OPERATION
for two words
As for the programming operation, FLASH memMOV
[Rm],R1
ory erase can be performed only inside the Write
MOV
[Rm],R2
mode, with indirect addressing mode instruction.
One of the four Banks is erased performing this opThe address used for a long word write (32 bits)
eration,depending on the BE0,1 bits of FCR.
Rm must be an aligned even address (xxx0h,
following
xxx4h, xxx8h, xxxCh...) and is used as a base An erase operation is realized with the
pointer for the FLASH memory writing. The two sequence:
words to write must be contiguous,
alignedat an
all the words of the relevant bank
- Program
even address.
to 0000h.
R1 contains the data to write at the first address
VPPRIV bit of FCR to verify the correct
- Test
and R2 contains the data to write at the
following
voltage
on VPP.
even word address.
- Load the desired value in FCR.
5/8

4 - Flash Memory
15
14
13
12
11
10
9
8
PRESTO F PROGRAM WRITE ALGORITHM
FWMSET
R
BE1
BE0
Programming with Presto F algorithm consists of
applying a e
squence of program pulses to each
1
0
0
0
0
0
0/1
0/1
word until correct verify occurs. A maximum of
7
6
5
4
3
2
1
0
programming operations are
allowed for each
word. Each program operation consists of a proWDWW CKCTL1 CKCTL0 VPPRIV FCVPP FBUSY
FEE
FWE
gram command; the programming is then automat0
0/1
0/1
0
0
0
1
1
ically performed. After a time out of
µs4a Program
Verify is then performed which compares data outAs FCR is a virtual register, all bits previously writ-put with data expected. This sequence
guarantees
ten must be confirmed in the same state at each that each cell is programmed
eliably.
r
FCR writing (especially FWMSET).
Figure 4.3 illustrates the Presto F Program Write
Algorithm.
- Perform the erase command
e.g. MOV [R0],R0
As the program pulse varies in inverse ratio to the
This special instruction for erase, guarantees us- frequency, PT=400 TCL, the number of operations
allwed varies also:
ers against inadvertent operation.
N=6250/TCL with I/TCL= 2 to 40MHz.
- FLASH erase will automatically start. The
erase time depends on CKCTL0,1 bits of FCR.
PRESTO F ERASE ALGORITHM
End of erase is detected bypolling on the
FBUSY bit of FCR.
Erasing with Presto F algorithm allows the electrically erasing of the selected Bank inreliableway.
a
Test
FCVPP
bit
of
FCR
to
verify
that
VPP
had
- the correct voltage during erase.
The algorithm starts by first programming all the
words to 0000h in order to perform an uniform eraThen
all
the
FLASH
memory
must
be
read
to
verify the completely correct erasure. After era- sure. This step is performed by using the Presto F
sure, bits FWE and FEE remain at a logical “1”. Program Write Algorithm.
The Erase Verify Mode (EVM), is then entered The erase command (see erase operation) is writautomatically.
ten and erase is performed. An Erase Verify begins
An internally generated margin voltage is ap- at the first address and continues until the last adplied to the FLASH memory. If the memory lo- dress is accessed or until the comparison of data to
cation is erased, the Erase Verify is repeated FFFFh fails. The address of the last word verified is
for the next location. This process continues for stored and a new erase operation is performed.
each word of the array until the last address is Then the Erase Verify restarts from the stored adaccessed or a word does not return FFFFh. In dress.
this case where the word is not erased, anFigure 4.4 illustrates the Presto F Erase Algorithm.
other erase operation must be performed.
As the erasing pulse (ET) varies in inverse ratio to
EVM needs a double reading instruction with the
the frequency, the number of erasing operation
same operand, and time for abilizingthe
st
internal
varies also:
circuitry.
at 1MHz CPU clock ET = 2ms, N =15000
e.g.
at 40 MHz CPU clock ET = 10ms, N = 3000
for other requencies
f
ET = 4.104 TCL,
MOV R1,[R2]
4
N = 75.10 /TCL
Time out of 4ms
MOV R1,[R2]
-
To perform a normal FLASH reading, the
FWE,FEE bits must be reset.
The erase of one bank can not be performed from
another bank of the FLASH memory.
6/8

4 - Flash Memory
Figure 4-3. Presto F Program Write Algorithm
7/8

4 - Flash Memory
Figure 4-4. Presto F Erase Algorithm
8/8


CHAPTER 5
CENTRAL PROCESSING UNIT (CPU)
5. CENTRAL PROCESSING UNIT
Basic tasks of the CPU are to fetch and decode in- the priority of the current CPU operation is less
structions, to supply operands for the arithmeticthan the priority of the selected peripheral request,
and logic unit (ALU), to perform operations on an interrupt will occur.
these operands in the ALU, and to store the pre- Basically, there are two types of interrupt processviously calculated results. Since a four stage pipe- ing: One type, the standard interrupt processing,
line is implemented in the ST10x166, up to four forces the CPU to save the current program status
instructions can be processed parallel.Section
in
and the return address on the stack before branch5.1 describes how the
pipelineworks for sequential ing to the interrupt vector jump table. The second
and branch instructions in general, and which type, the PEC interrupt processing, steals just one
hardware provisions have been made to speed the machine cycle from the current CPU activity to perexecution of jump instructions in particular.
form a single data transfer via the on-chip PeriphWith reference to instruction
pipelining, most
eral Event Controller (PEC). System errors
ST10x166 instructions can be regarded as
being
detected during program execution (so called
executed during one machine cycle (=100ns at hardware traps), or an external non-maskable in40MHz oscillator frequency). Section 5.2 de- terrupt are also processed as standard interrupts
scribes the general instruction timing
including
with a very high priority. For more information
standard and exceptional timing.
about interrupts, PEC data transfers and
hardware
traps
see
chapter
7.
While internal memory accesses are normally performed by the CPU itself, all of the external mem- In contrast to other on-chip
peripherals, there is a
ory accesses are performed by a particular on-chip closer conjunction between the Watchdog Timer
External Bus Controller (EBC) which is automat- and the CPU. If enabled, the Watchdog Timer exically invoked by the CPU whenever a code or data pects to be serviced by the CPU within a programaddressbelongsto the external memory space. If mable period of time, otherwise it will reset the
possible, the CPU continues operating while an ex- chip. Thus, the Watchdog Timer is able to prevent
ternal memory access is in progress. If external the CPU from going totally astray when executing
data are required but are not yet
available,or if a
erroneouscode. After reset, the Watchdog Timer
new external memory access is requested by the starts counting automatically, but it candisabled
be
CPU before a previous access has been com- via software if desired.
pleted, the CPU will be held by the EBC until the re- By any reset, the CPU is forced intopredefined
a
quest can be satisfied. Chapter 9 is dedicated to a active state. Further particular CPU states are: The
description of the external bus interface
being
IDLE state where the CPU clock is switched off and
serviced by the EBC.
the peripheral clocks keep running, and the
The ST10x166 peripherals work nearly inde- POWER DOWN state where all of the on-chip
pendent of the CPU with a separate clock gener- clocks are switched off. A transition into an active
ator. An interchange of data and control CPU state is forced by an interrupt if being IDLE, or
information between the CPU andthe peripherals by a reset if being in POWER DOWN mode, reis done via Special Function Registers (SFRs). spectively. The IDLE, POWERDOWN and RESET
Whenever peripherals non-deterministically need states can be entered by particular ST10x166 sysa CPU action, an on-chip Interrupt Controller com- tem control instructions. For more information on
pares all pending peripheral service requests these states see chapter 12.
against each other and prioritizes one of them. If
1/26
5 - Central Processing Unit
Section5.3 describes the Special Function Registers situated within the CPU core which are all
dedicated to particular uses, as follows:
General System Configuration: SYSCON
Bus Configuration: BUSCON1
Address Select: ADDRSEL1
CPU Status Indication and Control: PSW
Code Access Control: IP, CSP
Data Paging Control: DPP0, DPP1, DPP2,
DPP3
GPRs Access Control: CP
System Stack AccessControl: SP, STKUN, STKOV
Multiply and Divide Support: MDL, MDH, MDC
ALU Constant Support: ZEROS, ONES
struction. All explicit writes to the SFR memory
space and all auto-increment or auto-decrement
writes to GPRs used as indirect address pointers
are performed during the execute stage of an instruction, too.
4th -> WRITE BACK: In this stage, all external operands and the emainingoperandswithin
r
the internal RAM space are written back.
A particularity of the ST10x166 are the so called injected instructions. These injected instructions are
internallygenerated by the machine to provide the
time neededto process instructions which cannot
be processed within one machine cycle.They are
automatically injected into the decode stage of the
pipeline, and then they pass through the
emaining
r
5.1 INSTRUCTION PIPELINING
stages as every standard instruction. Program interrupts are performed by means of injected inAs mentioned in the introductional part of thisstructions, too. Although one will not notice these
chapter, a four stage instruction
pipelineis impleinternallyinjected instructions in reality, they are inmented in the ST10x166. This means that instruc- troduced here to ease the explanation of the pipetion processing is partitioned in four stages ofline in thefollowing.
which each one has its individual task as follows:
1st -> FETCH: In this stage, the instruction se- 5.1.1 Sequential Instruction Processing
lected by the Instruction Pointer and the Code Segment Pointer is fetched from either the internal Each single instruction has to pass through each of
ROM or FLASH memory, internal RAM, or external the fourpipelinestages regardlessof whether all
possible stage operations are really performed or
memory.
not. Since passing through one
pipeline stage
2nd -> DECODE: In this stage, the instructions are takes at least one machine cycle, any single indecoded, and if required,the operand addresses struction takes at least four machine cycles to be
are calculated and the resulting
operands are
completed. Pipelining, however, allowsparallel
fetched. For all instructions which implicitly access(this means s
imultaneous
) processing of up to four
the system stack, the SP register is either decre- instructions. Thus, most of the instructions seem to
mented or incremented as specified. For branch in- be processed during one machine cycle as soon
structions, the Instruction Pointer and the Code as thepipelinehas been filled once after reset (see
Segment Pointer are updated with the desired figure 5.1).
branch target addresses (provided that the branch
Instructionpipeliningincreases the average inis taken).
struction throughput considered over a certain pe3rd -> EXECUTE: In this stage, an operation is riod of time. In theollowing,any
f
execution time
performed on the previously fetched
operandsin
specification of an instruction always refers to the
the ALU. Additionally, the condition flags in the average execution time due to
pipelined parallelinPSW register are updated as specified by an in- struction processing.
Figure 5-1. Sequential Instruction Pipelining
→
FETCH
DECODE
1 Machine
Cycle
I1
←
time
→
I2
I3
I4
I5
I6
I1
I2
I3
I4
I5
I1
I2
I3
I4
I1
I2
I3
EXECUTE
WRITE BACK
2/26

5 - Central Processing Unit
5.1.2 Standard Branch Instruction Processing
struction as shown in figure 5.2.
Instruction p
ipelininghelps to speed equential
s
program processing. In the case that a branch is If a conditionalbranch is not taken, there is no detaken, the instruction which has already been viation from thesequentialprogram flow, and thus
fetched providently is mostly not the instructionno extra itme is required.In this case, the instrucwhich must be decoded next. Thus, at least one tion after the branch instruction will enter the deadditionalmachine cycle is normally required to code stage of thepipelineat the beginningof the
conditional
fetch the branch target instruction. This extra ma- next machine cycle after decode of the
chine cycle is provided by means of an injected in- branch instruction.
Figure 5-2. Standard Branch Instruction Processing
→
FETCH
1 Machine
Cycle
←
injection
time
→
BRANCH
In + 2
ITARGET
ITARGET + 1
ITARGET + 2
ITARGET + 3
DECODE
In
BRANCH
(IINJECT)
ITARGET
ITARGET + 1
ITARGET + 2
EXECUTE
. ..
In
BRANCH
(IINJECT)
ITARGET
ITARGET + 1
WRITE BACK
. ..
. ..
In
BRANCH
(IINJECT)
ITARGET
5.1.3 Cache Jump Instruction Processing
struction (JMPA, JMPR, JB, JBC, JNB,JNBS)is adA jump cache has been incorporated in the ditionallystored in a cache after having been
fetched.
ST10x166 as an optimization of
conditional jum
ps
which are processed repeatedly within a loop. After each repeatedlyfollowingexecution of the
Whenever a jump on cache is taken, the extra time same cache jump instruction, the jump target into fetch the branch target instruction can be saved, struction is not fetched but taken from the cache
and thus the cor
respondingcache jump instruction and immediatly injected into the decode stage of
in most cases takes only one machine cycle to be the pipeline(see figure 5.3).
performed.
A time saving jump on cache is always taken after
the second and any further occurence of the same
This performance is achieved by the
following
mechanism. Whenever a cache jump instruction cache jump instruction, unless an instruction which
passes through the decode stage of the
pipeline
has the fundamentalcapabilityof changingthe
for the first time (and provided that the jump condi-CSP register contents (JMPS, CALLS, RETS,
tion is met), the jump target instruction is fetchedTRAP, RETI) or any standard interrupt has been
processed during the period of time between two
as usual causing a time delay of
one machine cycle. In contrast to standard branch instructions, followingoccurences of the same cache jump inhowever, the target instruction of a cache jump in- struction.
Figure 5-3. Cache Jump Instruction Pipelining
→
FETCH
Injection of Cached
Target Instruction
Injection
1 Machine
Cycle
←
In + 2
ITARGET
ITARGET + 1
In+2
ITARGET + 1
ITARGET + 2
DECODE
Cache Jump
(IINJECT)
ITARGET
Cache Jump
TI ARGET
ITARGET + 1
EXECUTE
In
Cache Jump
(IINJECT)
In
Cache Jump
I ARGET
T
WRITE BACK
. ..
In
Cache Jump
nI
Cache Jump
→
1st loop iteration
. ..
→
Repeated loop iteration
3/26

5 - Central Processing Unit
Explicit Stack Pointer Updating
5.1.4 Particular Pipeline Effects
Since up to four different instructions are processedAny of the RET, RETI, RETS, RETP or POP instrucsimultaneously, additional hardware has been spenttions is not capable of correctly using a new SP regin the ST10x166to considerall causal dependencies ister value which is to be updated by an immediately
which may exist on instructions in different pipelinepreceding instruction. Thus, if one wants the new SP
stages without a loss of performance. This extra register value to be used without erroneously perhardware (i.e. for ‘forwarding’ operand read and formed stack accesses,one must put at least one inwrite values) avoids that the pipeline becomes no- struction between an explicitly SP-writing and any
subsequent of the just mentioned implicitly SP-using
ticeable for the user in most of the cases.
However, there are some very rare caseswhere one instructions, as shown in the following example:
MOV SP, #0FA40h
must pay attention to the circumstance that the In
; select a new top of stack
ST10x166 is a pipelined machine. Intelligent
ST10x166 tools like the simulator and the emulator In+1
....
; must not be an instruction
popping
support the user by easing the association with the
; operands from the system stack
following particular pipeline effects.
In+2 POP R0
; pop the word value from the new top of
Context Pointer Updating
; stack into GPR 0
An instruction which calculatesa physicalGPR operand address via the CP register is mostly not capa- External Memory Access
Sequences
ble of using a new CP value which is to be updated
by an immediately precedinginstruction. Thus, if oneThe effect described here will only become noticesurely wants the new CP value to be used, one must able if one looks at the external memory accessseput at least one instruction between a CP-changing quences on the external bus (i.e. by means of a
pipelinestages can siand a subsequent GPR-using instruction, as shown Logic Analyzer). Different
multaneous
ly put a request on the External Bus
in the following example:
Controller(EBC). Since thepredefinedpriority of
SCXT CP, #0FC00h
In
external memory accesses is as follows, 1st Write
; select a new context
Data, 2nd Fetch Code, 3rd Read Data, the se....
In+1
quence of instructions processed by the CPU may
; must not be an instruction using a GPR
diverge from the sequence of the corr
esponding
In+2 MOV R0, #dataX
external memory accesses performed by the EBC
; write to GPR 0 in the new context
.
Timing
Data Page Pointer Updating
As already described, instruction elining
pip
reAn instruction which calculates a physical operandduces the average instruction processing time in a
address via a particular DPPn (n = 0 to 3) register is wide scale (from four to one machine cycles). Howmostly not capable of using a new DPPn register ever, there are some rare cases where a particular
value which is to be updated by an immediately pre- pipeline situation causes a single instruction procceding instruction. Thus, if one surely wants the newessing time to be extended either by a half or by
DPPn register value to be used, one must put at one machine cycle. Although this
additionaltime
least one instruction between a DPPn-changing in- represents only a tiny part of the total program exestruction and a subsequent instruction which implic-cution time, it might be of interest to avoid these
itly uses DPPn via a long or indirect addressing pipeline-caused time delays in time critical promode, as shown in the following example:
gram modules.
MOV DPP0, #4
In
Besides a general execution time description, sec; select data page 4 via DPP0
tion 5.2 provides some hints how one can optimize
In+1
....
time-critical program parts with regard to such
; must not be an instruction using DPP0
pipeline-caused timing particularities.
; (for long or indirect addresses from 0000h
; to 3FFFh)
In+2 MOV 0000h, R1
; move contents of GPR 1 to address
; location10000h (in data page 4)
; supposed that segmentation is not
; disabled
4/26

5 - Central Processing Unit
5.2 INSTRUCTION STATE TIMES
1 [State] = 2 x 1/f OSC [s]; for f OSC = variab le
= 50 [ns] ; for OSC
f = 40MHz
Basically, the time to execute an instruction de- [ACT]: This ALE (Address Latch Enable) Cycle
pends on where the instruction is fetched from, and
Time specifies the time required to perwhere possible operands are read from or written
form one external memory access. One
to. The fastest processing mode of the ST10x166 is
ALE Cycle Time consists of either two
to execute a program fetched from the internal pro(for a non-multiplexed external bus
gram memory. In that case, most of the instructions
mode) or three (for a multiplexed external
can be processed within just one machine cycle,
bus mode) state times plus a number of
which also represents the general minimum execustate times which is determined by the
tion time.
number of wait states programmed in the
All of the external memory accesses are performed
MCTC (Memory Cycle Time Control) and
by the ST10x166 on-chip External Bus Controller
MTTC (Memory Tristate Time Control) bit
(EBC) which works in parallel with the CPU. Mostly,
fields of the SYSCON register plus one
instructions from the external memory can not be
state time if ALECTL1 bit of ADDRSEL1
processed as fast as instructions from the internal
register is set to ‘1’.
program memory, because some data transfers
In the case of the non-m
ultiplexedexterwhich internally can be performed in parallel, have
nal bus mode:
to be performed sequentially via the external inter- 1xACT =(2+(15 - MCTC)+(1- MTTC)
face. In contrast to internal program memory pro+(ALECTL1))xStates
gram execution, the time required to process an
= 100ns ... 900ns ; for OSC
f = 40MHz
In the case of the multiplexed external
external program additionally depends on the
bus modes:
length of the instructions and operands, on the selected bus mode, and on the duration of an external 1x ACT=3 + (15 -MCTC) + (1 - MTTC
+(ALECTL1)) x States
memory cycle which is partly selectable by the user.
= 150ns ... 950ns ; for OSC
f = 40MHz
Processing a program from the internal RAM space
is not as fast as execution from the internal ROM The total time (Ttot) which a particular part of a proarea, but it offers a lot of flexibility (i.e., for end of linegram takes to be processed can be calculated by
programming where a program could be loaded into the sum of the single instruction processing times
(TIn) of the considered instructions plus an offset
the internal RAM via the chip’s serial interface).
The following description allows evaluating thevalue of 6 state times which considers the solitary
minimum and maximum program execution times. filling of thepipeline,as follows:
This will be sufficient for most of the requirements. Ttot = TI1 + TI2 + ... + TIn + 6 x States
This section is arranged in subsections of which theThe time TIn which a single instruction takes to be
(T)
first one defines the subsequently used time units,processed consists of a minimum numberImin
the second contains an overview about the mini- plus an additionalnumber (TIadd) of instruction
mum (standard) state times of the ST10x166 in- state times and/or ALE Cycle Times, as follows:
structions, and the third describes the exceptionsTIn = TImin + TIadd
from that standard timing.
5.2.2 Minimum State Times
5.2.1 Time Unit Definitions
The followingtable 5.1 shows the minimum numThe followingtime units are used to describe the ber of state times required to process a10x166
ST
instruction processing times:
instruction fetched from the internal ROMImin
(T
(ROM)). The minimum number of state times for invariable
structions fetched from the internal RAMImin
(T
[f OSC]: Oscillator frequency (may be
from 2MHz to 40MHz).
(RAM)), or of ALE Cycle Times for instructions
fetched from the external memoryImin
(T (ext)), can
[State]: One state time is specified by two times
also be easily calculated by means of table 5.1.
an oscillator period. Henceforth, one
Most of the ST10x166 instructions - except some
State is used as the basic time unit, beof the branches, the multiplication, the division and
cause it represents the shortest period of a special move instruction - require a minimum of
time which has to beonsidered
c
for intwo state times. In the case of internal ROM prostruction timing evaluations.
5/26

5 - Central Processing Unit
gram execution there is no execution time
dependFor 4-byte instructions:
ency on the instruction length except for some spe-TImin(RAM) =TImin (ROM) + 6 x States
cial branch situations. The injected target In contrast to the internal ROM program execution,
instruction of a cache jump instruction can be con-the minimum time Imin
T (ext) to process an external
sidered for timing evaluations asbeingexecuted
if
instruction additionally depends on the instruction
from the internal ROM,regardless of which mem- length. TImin(ext) is either 1 ALE Cycle Time for
ory range the rest of the current program is really most of the 2-byte instructions, or 2 ALE Cycle
fetched from.
Times for most of the 4-byte instructions. The folFor some of the branch instructions, table 5.1 rep- lowing formula represents the minimum execution
resents both the standard number of state times time of instructions fetched from an external memory via a 16-bit data bus:
which means that the corres
ponding branch is
taken, and anadditionalTImin value in parentheses For 2-byte instructions:
which refers to the case that either the branch con- TImin(ext)=1xACT + (TImin(ROM) - 2) x States
dition is not met or that a cache jump is taken.
Instructions executed from the internal RAM re- For 4-byte instructions:
quire the same minimum time as if being fetched TImin(ext)=2xACTs + (TImin(ROM) - 2) x States
from the internal ROM plus an instruction-length For instructions fetched from an external memory
dependent number of state times, as follows:
via an 8-bit data bus, the minimum number of required ALE Cycle Times is twice the number for a
For 2-byte instructions:
16-bit bus.
TImin(RAM) =TImin (ROM) + 4 x States
Table 5-1. Minimum Instruction State Times
TImin (ROM)
[States ]
Instruction
TImin (ROM)
(at 20MHz CPU Clock)
2
Any (except the following)
Unit
100
ns
4
4
4
4
4
10
20
4
4
4
CALLI, CALLA
CALLS, CALLR, PCALL
JB, JBC, JNB, JNBS
JMPS
JMPA, JMPI, JMPR
MUL, MULU
DIV, DIVL, DIVU, DIVLU
MOV[B] Rn, [Rm + #data 16]
RET, RETI, RETP, RETS
TRAP
(2)
(2)
(2)
200
200
200
200
200
500
1000
200
200
200
(100)
(100)
(100)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 )Internal ROM operand reads: TIadd = 2x States
5.2.3 Additional State Times
As described in theollowing,some
f
operand ac- Both byte and word operand reads always require
cesses can extend the execution time of an in- 2 additional state times.
struction, TIn. Since the additionaltime, TIadd, is
2) Internal RAM operand reads via indirect admostly caused by internal instruction
ipelining,
p
it
dressing modes: TIadd = 0 or 1 x State
often will be possible to evade these timing effects
in time-critical program modules by means of a Reading a GPR or any other directly addressed
operand within the internal RAM space does NOT
suitable rearrangement of the corres
ponding instruction sequences. The ST10x166 simulator and cause additional state times. However, reading an
emulator offer many facilities which support the indirectly addressed internal RAM operand will exuser in optimizing the program whenever required. tend the processing time by 1 state time if the pre-
6/26

5 - Central Processing Unit
ceding instruction auto-increments or auto-decre-5) External operand writes:
ments a GPR as shown in the
followingexample:
TIadd = 0 x State ... 1 x ACT
MOV R1 , [R0+]
In
Writing of an external operand via a 16-bit data bus
; auto-increment R0
takes one additional ALE Cycle Time. For timing
calculations of external program parts, this extra
In+1 MOV [R3], [R2]
; if R2 points into the internal RAM space:
time must always be considered. The value of
T
Iadd
; TIadd = 1 x State
which must be considered for timing evaluations of
In this case, the additional time can simply be internal program parts, may fluctuate between 0
avoided by putting another suitable instruction be-state times and 1 ALE Cycle Time. This is because
in
fore the instructionn+1
I indirectly reading the inter- external writes are normally performedparallel
to other CPU operations. Thus,Iadd
T could already
nal RAM.
have been considered in the standard processing
3)Internal SFR operand reads:
time of another instruction. Writing a word
operand
TIadd = 0, 1 x State or 2 x States
via an 8-bit data bus requires twice as much time
Mostly, SFR read accesses do NOT require addi- (2 ALE Cycle Times) as the writing of a byte opertional processing time. In some rare cases, how- and.
ever, either one or two additional state times will be 6)Testing Branch Conditions:
caused by particular SFR operations, as follows: T
Iadd = 0 or 1 x States
Reading
an
SFR
immediately
after
an
instruc- tion which writes to the internal SFR space, as Mostly, NO extra time is required for
conditional
branch instructions to decide whether a branch
shown in the following example:
condition is met or not. However, an
additional
MOV T0, #1000h
In
state time will be caused if the preceding instruc; write to Timer 0
tion writes to the PSW register, as shown in the folIn+1 ADD R3, T1
lowing example:
; read from Timer 1: ITadd = 1 x State
BSET USR0
In
; write to PSW
- Readingthe PSW register immediately after an
instruction which implicitly updates the condi-In+1 JMPR cc_Z, label
tion flags, as shown in the
following ex
ample:
; test condition flag in PSW:
; TIadd = 1 x State
In
ADD R0, #1000h
; implicit modification of PSW flags
In this case, the extra state time can simply be intercepted by putting another suitable instruction
In+1 BAND C, Z
; read from PSW: TIadd = 2 x States
before the conditionalbranch instruction.
Implicitly
incrementing
or
decrementing
the
SP
- register immediately after an instruction which 7) Jumps into the internal ROM space:
TIadd = 0 or 2 x States
explicitly writes to the SP register, as shown in As already described, standard jumps into the inthe followingexample:
ternal ROM space require 4 state times to be exeMOV SP, #0FB00h
In
cuted. This minimum time will be extended by 2
; explicit update of the stack pointer
additionalstate times, if the branch target instrucIn+1 SCXT R1, #1000h
tion is a double word instruction atnon-aligned
a
; implicit decrement of the stack pointer:
double word location (xxx2h, xxx6h, xxxAh,
; TIadd = 2 x States
xxxEh), as shown in theollowing
f
example:
In these cases, the extra state times can be label ....
avoided by putting other suitable instructions be; anynon-aligneddouble word instruction
fore the instruction In+1 reading the SFR.
; (i.e. at location 0FFEh)
....
....
4) External operand reads: TIadd = 1 x ACT
JMPA
cc_UC, label
I
Any external operand reading via a 16-bit data bus n+1
;
if
a
standard
branch is taken:
requires one additional ALE Cycle Time.
Reading
; TIadd = 2 x States (TIn = 6 x States)
word operands via an 8-bit data bus takes twice as
much time (2 ALE Cycle Times) as the reading of A cache jump, which normally requires just 2 state
times, will be ex
tended by 2 additionaltate
s times
byte operands.
if both the cached jump target instruction and its
7/26

5 - Central Processing Unit
successor instruction are non-aligned double wordSYSCON (FF0Ch / 86h)
instructions, as shown in the
ollowing
f
example:
System Configuration Register
label ....
Reset Values: 0000h, 0400h, 0440h, 0480h or
; anynon-aligneddoubleword instruction
04C0h
; (i.e. at location 12FAh)
15
14
13
12
11
10
9
8
....
; anynon-aligneddoubleword instruction
R
STKSZ
RDYEN SGTDIS BUSACT BYTDIS CLKEN
; (i.e. at location 12FEh)
7
6
5
4
3
2
1
0
In+1 JMPR cc_UC, label
; provided that a cache jump is taken:
BTYP
MTTC
RWDC
MCTC
; TIadd = 2 x States (TIn = 4 x States)
b15 =R: Reserved.
If required, these extra state times can be
avoided
by allocating double word jump target instructionsb14,b13 =STKSZ: Maximum System Stack Size
Selectionof between 32 and 256 words.
to aligneddoubleword addresses (xxx0h, xxx4h,
xxx8h, xxxCh).
b12 =RDYEN: READY Input Enable control bit:
RDYEN = 0: READY disabled; pin can be used
for normal I/O
5.3 CPU SPECIAL FUNCTION REGISTERS
RDYEN = 1: READY enabled; pin used for
The core CPU requires a set of Special Function READY input
Registers (SFRs) to maintain the system state in- b11 =SGTDIS: Segmentation Disable controle bit:
formation, to supply the ALU with register-address- SGTDIS = 0: A16 andA17 enabled;Port 4 used
able constants and to control system configuration, for segment address
SGTDIS = 1: A16 and A17 disabled; Port 4 can
multiply and divide ALU operations, code memory
segmentation, data memory paging, and accesses be used for normal I/O
onto the General P
urpose Regist
ers and the Sysb10 =BUSACT: Bus Active Control Bit
.
tem Stack.
b9 =BYTDIS: Byte High EnableBHE)
(
pin control
The accessmechanism for these SFRs in the CPU bit:
core is identical to the access mechanism for any BYTDIS = 0: BHE enabled
other SFR. Since all SFRs can simply be controlled BYTDIS = 1: BHE disabled; pin can be used for
by means of any instruction which is capable of ad- normal I/O
dressing the SFR memory space, a lot of
lexibilit
f
y
has been gained, and the need to create a set of b8 =CLKEN: System Clock Output (CLKOUT) Ensystem specific instructions was avoided. Note, able bit :
however, that there are user access restrictions for CLKEN = 0: CLKOUT disabled; pin can be used
some of the CPU core SFRs to ensure proper proc- for normal I/O
CLKEN = 1: CLKOUT enabled; pin used for sysessoroperations
.
tem clock output
The PSW, SP, and MDC registers can be modified
not only explicitly by the programmer, but also im-b7,b6 =BTYP: External Bus Configuration Control
plicitly bythe CPU during normal instruction proc- b5 =MTTC: Memory Tri-state Time Control
essing. Note that any explicit programmer’s write b4 =RWDC: Read/Write Delay Control.
request to an SFR supersedes a simult
aneous
b3,b2,b1,b0 =MCTC: Memory Cycle TIme Conmodification by hardware of the same register.
trol.
Note furthermore, that any byte write operation to
an SFR clears thenon-addressed complementary
byte within the specified SFR. Note also that nonimplemented (reserved) SFR bits can not be modified, and will always supply a read value of ‘0’.
It +1
8/26

5 - Central Processing Unit
5.3.1.2 EXTERNAL BUS TIMING CONTROL (VIA
5.3.1 SYSCON: System Configuration
MCTC, MTTC, RWDC)
Register
This bit-addressable register provides general sys-The MCTC bit field and the MTTC and RWDC bits
tem configuration and control functions. There are in the SYSCON register are provided for varying
five different reset values for the SYSCON register, external bus timing parameters as follows. The
because the BTYP bit field and the BUSACT bit are Memory Cycle Time can be extended within a
range from 0 to 15 state times by means of the
initializ
e d during resetdependenton the state of
MCTC bit field (1 state time = 2 x 1/f
OSC). By means
the BUSACT, EBC0 and EBC1 input pins.
of the MTTC bit, the Memory Tri-State time can be
extended by either 1 or a
0dditionalstate time. The
5.3.1.1 INTERNAL ROM OR FLASH MEMORY/EXMemory Tri-State Time isadditionallyextended by
TERNAL MEMORY ACCESS MODE SELECTION
one state time whenever a multiplexed external
A two-bit field, BTYP, and BUSACT, reflect the se- bus configuration is selected. The RWDC bit allows
lected external bus configuration, as shown in ta- programming a time delay of either 0 or 0.5 state
times between the falling edges of the ALE and the
ble 5.2.
BTYP bits and the BUSACT bit are always read- Read/Write signals. This read/write delay does not
and writeable bits,
regardless of the bus configura- extend the general memory access time. Note that
tion selected during reset. But after the EINIT additionalexternal wait states do not slow down ininstruction (end of initialization), only the externalternal memory accesses. Table 5.3 summarizes
the SYSCON control functions for the external bus
bus configuration can behanged
c
at any time.
When the SYSCON parameters are modified dur- timing.
ing initializat
ion, an instruction from a source (ex- After reset, the MCTC, MTTC and RWDC are all internal bus or internal ROM) which is to be switched itialized to zero. Thus, even very slow memories
will be accessed correctly.
must not be performed. (e.g.
disablingthe external
bus when executing from external memory)!
Switching between the bus modes can also be per- 5.3.1.3 BYTE HIGH ENABLE PIN CONTROL (VIA BYTformed with the BUSCON1 register. (see section DIS)
5.3.1.5 for further information).
The BYTDIS bit is provided for controlling the acNote that the selection of a multiplexed external tive low Byte High EnableBHE)
(
pin. The function
bus configuration automatically extends the Mem- of the BHE pin isenabledif the BYTDIS bit conory Tri-State Time by one state time (1 state tains a ‘0’. Otherwise, it is
disabledand the pin can
time=2 x 1/fOSC).
be used as standard I/O pin. The
BHE pin is implicFor further information and for examples about the itly used by the External Bus Controller to select
Single Chip Mode and the ext
ernal bus configura- one of two byte-organized memory chips which are
connected with the ST10x166 via a word wide-extion modes, see section 9.1.
ternal data bus. After reset, BYTDIS is initialized to
zero.
For further information about the use of the
BHE
pin see chapter 10.
Table 5-2. External Bus Configuration via BUSACT, BTYP bit field
BUSACT
BTYP
Reset
During Init
After Init
0
0
0
0
00
01
10
11
ROM enable Seg. 0 No ext. Bus
(Reserved)
(Reserved)
(Reserved)
ROM enable Seg. 0
ROM enable Seg. 1
Disable ROM
Disable ext. Bus
No
No
No
No
1
1
1
1
00
01
10
11
8-Bit Non-Mux no ROM
8-Bit Mux no ROM
16-Bit Mux no ROM
16-Bit Non-Mux no ROM
8-Bit Non-Mux
8-Bit Mux
16-Bit Mux
16-Bit Non-Mux
8-Bit Non-Mux
8-Bit Mux
16-Bit Mux
16-Bit Non-Mux
Action
Action
Action
Action
9/26

5 - Central Processing Unit
Table 5-3. SYSCON External Bus Timing Control Functions
Control
Parameter
Value
Number of Additional
State Times
Affected Time
MCTC
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MTTC
0b
1b
1
0
Memory Tri-State Time
RWDC
0b
1b
0
0
Read/Write Signal Delay
BTYP
00b
01b
10b
11b
0
1
1
0
Memory Cycle Time
(implicit)
(implicit)
Memory Tri-State Time
(implicit for multiplexed
bus configurations)
5.3.1.4 READY PIN CONTROL (VIA RDYEN)
into the memory cycle (Cycle Time Wait States),
The RDYEN bit provides an optional Data-Ready regardlessof the state of theREADY line. Then affunction via the active low
READY input pin, to al- ter the wait state time has expired, the CPU will
check theREADY line and delay the memory aclow an external memory controllerperipherals
or
to
READY line.
determine the duration of an external memory ac- cess depending on the state of the
cess. The Data-Ready function is
enabledby setWarning : If the Data-Ready function is enabled,
ting the RDYEN bit to ‘1’. In this case, port pin the READY input pin must be activated for every
P3.14 takes on its alternate function as active low external memory access. Otherwise, the system
READY input pin. An active low signal on the would be halted until a reset occurs. No time-out
READY input pin signifies that data available
is
protection other than a Watchdog Timer overflow is
and must be latched by the on-chip External Bus provided for that case.
Controller. Note, that it is the user’s
esponsibilit
r
y
In order to allow one to interface to a variety of peto set the direction of the
READY pin to input be- ripherals, support for both asynchronous and synfore using this function.
chronous modes of operation is provided. If the
When the Data-Ready function is enabled and bits Data-Ready function is enabled, bit 3 in the SY0 to 2 of SYSCON register are cleared, the external SCON register (the MSB of the MCTC bit field) debus timing is only determined by the
READY pin,
termines whether theREADY input pin is to be
the MTTC bit, the RWDC bit and by the selected used in asynchronous or nchronous
sy
mode:
external bus mode. If 1 to 7 wait states are pro- SYSCON.3 = 1:Asynchronous READY input
grammed in bits 0 to 2 of the MCTC field, the CPU
will first insert the selected number of wait states SYSCON.3 = 0:Synchronous READY input
10/26

5 - Central Processing Unit
In the asynchronous mode of operation, the physical address generation. This means also that
READY input signal is internally synchronized to the pins of Port 4 can be used as standard I/O pins.
the microcontroller’s operation. In this case, an ad-In the case of the segmented memory mode
ditional delay of up to two state times may be re- (SGTDIS = ‘0’), the CSP and DPP registers are used
quired in order to
internallysynchronize the signal. for the generation of physical 18-bit addresses as
In the synchronous mode of operation, it is the described in sections 5.3.6 and 5.3.7. The pins of
Port 4 are used as address pins A17 and A16 prouser’s responsibilityto ensure that theREADY input signal meets the specified setup and hold vided that an external bus has been configured.
times. In order to obtain the necessary timing infor- Whenever the segmented memory mode is semation and to perform external synchronization, lected, the CSP register is pushed onto the system
the Clock Output function can be used.
stack in addition to the IP register before an interrupt
service routine is entered, and it is repopped when
After reset, the Data-Ready functiondisabled.
is
the interrupt service routine is left again.
After reset, the segmented memory mode is se5.3.1.5 CLOCK OUTPUT PIN CONTROL (VIA CLKEN)
lected by default.
The Clock Output function is enabled by setting the
CLKEN bit of the SYSCON register to ‘1’. If enabled, port pin P3.15 takes on its alternate function 5.3.1.7 MAXIMUM SYSTEM STACK SIZE SELECas CLKOUT output pin. The Clock Output is a 50% TION (VIA STKSZ)
duty cycle clock whose frequency is half the oscil-The maximum size of the system stack is directly
lator frequency OUT
(f = fOSC/2). For a 40MHz clock
determined by the two-bit field STKSZ as shown in
oscillator, the CLKOUT frequency is 20MHz.
table below.
Note that it is the user’s responsibility to set the direction of the CLKOUT pin to output and to write a Table 5-4. Maximum System Stack Size
‘1’ into port latch P3.15 before using this function.
STKSZ
Maximum System Stack Size
After reset, the Clock Output functiondisabled.
is
5.3.1.6 NON-SEGMENTED MEMORY MODE SELECTION (VIA SGTDIS)
00b
01b
10b
11b
256
128
64
32
words
words
words
words
The SGTDIS bit allows selecting either the segmented or non-segmented memory mode. In the
case of the non-segmented memory mode (SGTDIS Note that the contents of the STKSZ bit field immegenera= ‘1’), the entire address space is restricted to 64 diately affect the physical stack address
tion
via
the
SP
register
described
in
section
5.3.9.
Kbytes (segment 0), and thus all addresses can be
represented by 16-bits. Thus, the contents of the After reset, the maximum stack size of 256 word loCSP register are totally ignored, and only the two cations is selected by default.
least significant bits of the DPP registers are used for
11/26

5 - Central Processing Unit
BUSCON1 (FF14h / 8Ah)
Bus Configuration Register
Reset Value:0000h
Figure 5-4. Partitioning Example with
BUSCON1 and SYSCON
Segment 0
15
14
FFFF
13
R
External Memory
Accessed
via SYSCON
Parameters
7
BTYP
C000
16K Range,
Start Address
8000h (32K)
6
External Memory
Accessed
via BUSCON1
Parameters, e.g. 8Bit
Data Multiplexed Bus,
2 Wait-States+READY
enabled
8000
12
11
RDYEN1
R
4
3
5
10
9
BUSACT1ALECTL1
2
MTTC1 RWDC1
1
8
R
0
MCTC
b15,b14,b13,b11,b8 =R: Reserved.
b12 =RDYEN1: READY Input Enable control bit:
RDYEN = 0: READY function disabled for
BUSCON1 accesses
RDYEN = 1: READY function enabled for
BUSCON1 accesses
b10 =BUSACT1: Bus Active Control Bit.
b9 =ALECTL1: ALELengtheningControl Bit
b7,b6 =BTYP: External Bus Configuration Control
b5 =MTTC1: Memory Tri-state Time Control
b4 =RWDC1: Read/Write Delay Control.
b3 to b0 =MCTC: Memory Cycle TIme Control.
ADDRSEL1 (FE18h / 0Ch)
Address Select Register
Reset Value:0000h
External Memory
Accessed
via SYSCON
Parameters, e.g.
16Bit Data NonMultiplexed Bus,
No Wait-State
15
14
13
12
11
10
R
7
6
5
RGSAD[4..0]
9
8
RGSAD[6..5]
4
3
2
1
0
RGSZ
b15 t o b10 =R: Reserved.
b9,b3 =RGSAD: BUSCON1 Address Range
Start Address Selection.
b2,b1,b0 =RGSZ: BUSCON1 Address Range Selection.
0000
12/26

5 - Central Processing Unit
Warning: The BUSCON1 register controls only the
5.3.2 BUSCON1: Bus Configuration Register
This register used with the ADDRSEL1 register al- external bus. It’s not possible to control the on-chip
lows the automatic selection of a different bus con-ROM or FLASH space through the BUSCON1 regisfiguration. It includes all control bits of the ter. This can only be done with SYSCON register.
SYSCON register relevant for configuring.
There are three different methods to lengthen an 5.3.3 ADDRSEL1: ADDRESS SELECT
access to external memories or peripherals. One is REGISTER
using MCTC to lengthen the middle of a bus cycle, This register specifies the address space in which
another is using MTTC to lengthen the end of a bus the BUSCON1 register will control the external bus
cycle, and the third is the ALECTL1 (ALE Control configuration.
Bit) of BUSCON1 to lengthen the
beginning of a
This register is divided into three parts. Bits 0 to 2,
bus cycle.
RGSZ (Range Size Selection bit field), specify the
After reset, the ALECTL1 bit is reset. For periph- address range according to the
followingtable 5.5:
eral componentsrequiringa longer ALE pulse,
longer address setup, and hold times, the The next bit field, bits 3 to 9, Range Start Address
ALECTL1 bit must be set to “1”. Then any access specified the start address of the address range.
within the address range specified by the AD- The third field of register ADDRSEL1, bits 10 to 15,
DRSEL1 register islengthenedby one machine is reserved for future expansion.
state (50ns @ 20MHz CPU clock). The ALE signal There is a fixed relationship between the range
is lengthened by one TCL (TCL=1/2 machine size and the range start address. The range start
state), and the address hold time after ALE is also address can only be specifiedboundaries
in
deterlengthenedby one TCL.
mined by the selected range size. That is, for a
After reset, all bits of the BUSCON1 register are range size of 16Kbyte, the start address of this
cleared. As opposed to SYSCON register, the range can only be programmed to 16Kbyte
state of the external bus control pins EBC0, EBC1 boundaries.For a range size of 2Kbyte, the start
address can be programmed to any 2Kbyte adand BUSACT are not copiedinto BUSCON1 after
dress boundary. If the range size is 128Kbyte, then
reset.
for the ST10x166 the start address can only be
To enable the BUSCON1 register, an address 0Kbyte or 128Kbyte, since the total address range
range plus a start address must be specified is 256 Kbyte (two blocks of 128 Kbyte). Bits 3 to 9,
through ADDRSEL1 register, then BUSCON1 reg- the Address Start Location bit field of register ADister must be programmed to the desired bus con- DRSEL1, canbe ragarded as the most significant
figuration and the BUSACT1 control bit must be address bits of the selected address range. Thus,
set. The BUSCON1 register will then take control dependingon the selected range size, only a part
of the external bus when an accessto the specified of this bit field is relevant for specification of the
address range is performed, otherwise the SY- start address. This is shown in the
followingtable
SCON parameters control the external bus charac- (x = don’t care; R = relevant bit):
teristics.
Figure 5.4 shows an example of control of partitions of the external address range by SYSCON
and BUSCON1.
Table 5-5. Address Range Selection
Range Size
RGSZ
000
001
010
011
100
101
110
111
Relevant Bits of
Range Start Address
Selected Address Range
2 KByte
16 KByte
32 KByte
64 KByte
128 KByte
reserved
reserved
reserved
RRRRRRR
RRRRxxx
RRRxxxx
RRxxxxx
Rxxxxxx
–
–
–
13/26

5 - Central Processing Unit
5.3.4 PSW: Processor Status Word
PSW (FF10h/88h)
This bit-addressable register reflects the current Processor Status Word Register
state of the microcontroller. It is subdivided into twoReset Value :0000h
parts of which the first one contains bits which rep14
13
12
11
10
9
8
resent the current ALU status, and the second bits 15
which determine the current CPU interrupt status.
ILVL
IEN
HLDEN
R
A separate bit (USR0) within the PSW register is
7
6
5
4
3
2
1
0
provided for use as general purpose flag.
R
USR0
MULIP
E
Z
V
C
N
5.3.4.1 ALU STATUS (N, C, V, Z, E, MULIP)
The condition flags of the PSW (N, C, V, Z, E) indicate b15,b14,b13,b12 =ILVL: This field represents the
the ALU status due to the last recently performed ALU current interrupt level being serviced by the CPU.
operation. They are set by most of the instructions due Upon entry into an interrupt routine, the four bits
ac
interrupt
to specific rules which depend on the ALU or data of the priority level of the knowledged
are copied into this field. By modifying this field,
movement operation performed by an instruction.
After execution of an instruction which explicitly up- the priority level of the current CPU task can be
dates the PSW register, the condition flags can not be programmed.
enablesor disables acinterpreted as described in the following because any b11 = IEN: This bit globally
explicitwrite to the PSW register supersedes the con- ceptance of interrupts.
dition flag values which are implicitly generated by the IEN = 0: CPU Interruptsdisabled.
CPU. Explicitly reading the PSW register supplies a IEN = 1: CPU Interruptsenabled.
read value which represents the state of the PSWreg- b10 = HLDEN: Bus Arbitration Enable Bit
ister after execution of the immediately preceding in- HLDEN = 0:HOLD/HLDA/BREQdisabled.
struction.
HLDEN = 1:HOLD/HLDA/BREQenabled.
E-Flag:
The
E-flag
can
be
altered
by
instruc- tions which perform ALU or data movement op- Pin P2.13-P2.15 are used for these functions
,b9,b8,b7 =R: Reserved.
erations. The E-flag is cleared by those
instructions which can not be reasonably used b6 = USR0: This bit is provided as the user’s general purpose flag.
for table searchoperations
. In all other cases,
the E-flag is setdependingon the value of the b5 = MULIP: This bit specifies that a multiply divide
source operand to signify whether the end of a operation was interrupted before completion.
search table is reached or not. If the value of MULIP = 0: No multiply/divide operation in prothe source operand of an instruc
tion equals the
gress.
lowest negative number which is representable MULIP = 1: Multiply/divide operation in progress.
by the data format of the cor
respondinginb4 = E: This bit supports table search operation by
struction(‘8000h’ for the word data type, or
signifying the end of a table.
‘80h’ for the byte data type) the E-Flag is set to
b3 = Z: This bit represents a zero result from the
‘1’, otherwise it is cleared.
ALU.
The Z-Flag is normally set to ‘1’ if the
- Z-Flag:
b2
= V: This bit represents an overflow result from
result of an ALU operation equals zero, otherthe
ALU.
wise it is cleared.
b1 = C: This bit represents a carry result from the
For the addition and subtraction with carry, the ALU.
Z-flag is only set to ‘1’ if the flag
Z- already con
b0 = N: This bit represents a negative result from
tains a ‘1’, and if the result of the current ALU the ALU.
operation addit
ionally equalszero. This mechanism is provided for the support ofultiple
m
precision calculations
.For Boolean bit operations
with only one operand, the Z-flag represents
the logical negation of the previous state of the
specified bit.
14/26

5 - Central Processing Unit
-
For Boolean bit operations with two operands,
the Z-flag represents the logical NORing of the
two specified bits. For the prioritize ALU operation, the Z-flag allows a differentiation of the
two cases which cause a result of zero.
V-Flag: For the addition, subtraction and 2’s complementation, the V-flag is always set to ‘1’
if the result overflows the maximum range of
signed numbers which are representable by
either 16 bits for word operations (‘-8000h’ to
‘+7FFFh’), or by 8-bits for byte operations (‘80h’ to ‘+7Fh’), otherwise the V-flag is cleared.
Note that the result of an integer addition, integer subtraction, or 2’s complement is not valid if
the V-flag signifies an arithmetic overflow.
For the multiplication and division, the V-flag is
set to ‘1’ if the result can not be represented in a
word data type, otherwise it is cleared. Note that
a division by zero will always cause an overflow.
In contrast to the result of a division, the result
of a multiplication is valid regardless of whether
the V-flag is set to ‘1’ or not.
Since logical ALU operations can not produce
an invalid result, the V-flag is cleared by these
operations.
For Boolean bit operations with only one operand, the V-flag is always cleared. For Boolean
bit operations with two operands, the V-flag
represents the logical ORing of the two specified bits.
C-Flag: After an addition, the C-flag indicates
that a carry from the most significant bit of the
specified word or byte data type has been generated.
After a subtraction or a comparison, the C-flag
indicates a borrow which represents the logical
negation of a carry for the addition. This means
that the C-flag is set to ‘1’ no
if carry from the
most significant bit of the specified word or
byte data type has been generated during a
subtraction which is perfor
med internallyby the
ALU as a 2’s complement addition, and the Cflag is cleared when this complement addition
caused a carry.
The C-flag is always cleared for logical, multiply and divide ALU operations, because these
operations can not cause a carry anyhow.
For the shift and rotate operations, the C-flag
represents the value of the bit shifted out last.
The V-flag is also used as ‘Sticky Bit’ for rotate If a shift count of zero is specified, the C-flag
right and shift right operations. With only using will be cleared. The C-flag is also cleared for a
the C-flag, a rounding error caused by a shift prioritize ALU operation because a ‘1’ is never
right operation can be estimated up to a quan- shifted out of the MSB during the normalization
tity of one half of the LSB of the result. In con- of an operand.
junction with the V-flag, the C-flag allows
evaluating the rounding error with a finer resolu- For Boolean bit operations with only one operand, the C-flag is always cleared. Foroolean
B
tion, as shown in table below.
bit operationswith two operands, the C-flag
represents the logical ANDing of the two specified bits.
Table 5-6. Shift Right Rounding Error Evaluation
C-Flag
V-Flag
0
0
1
1
0
1
0
1
Rounding Error Quantity
No Rounding Error
0 < Rounding Error < 1/2 LSB
Rounding Error = 1/2 LSB
Rounding Error < 1/2 LSB
15/26

5 - Central Processing Unit
-
y into an interN-Flag: For most of the ALU operations, the N- updated byhardware upon the entr
flag is set to ‘1’ if the most significant bit of the rupt service routine, but it can also be modified by
result contains a ‘1’, otherwise it is cleared. In software to prevent other interrupts from being acknowledged.In the case that an interrupt level ‘15’
the case of integeroperations
, the N-flag can
be interpreted as the sign bit of the result has been assigned to the CPU, it has the highest
(negative: N=1, positive: N=0). Negative num- possible prior
ity, and thus the current CPU operabers are always represented as the 2’s com- tion can not be interrupted except by hardware
plement of the corr
espondingpositive number. traps or external non-maskable interrupts. For deThe range of signed numbers extends from ‘- tails about the ST10x166 interrupt system see
8000h’ to ‘+7FFFh’ for the word data type, or chapter 7.
from ‘-80h’ to ‘+7Fh’ for the byte data type.
After reset, all interrupts are
globallydisabled, and
the lowest priority (ILVL=0) is assigned to the initiFor Boolean bitoperationswith only one oper- tial CPU activity.
and, the N-flag represents the previous state of
the specified bit. For Boolean bit operations
with two operands, the N-flag represents the 5.3.4.3 HOLD/HLDA/BREQ BUS ARBITRATION
logical XORing of the two specified bits.
The HLDEN bit allows to enable the alternate funcThe MULIP flag will be set to ‘1’ tions at pins P2.15 HOLD),
(
P2.14 (HLDA), and
- MULIP-Flag:
by hardware upon the entrance into an inter- P2.13 (BREQ). If HLDEN bit is cleared after once
rupt service routine when a multiply or divide being set, this will disable the bus arbitration funcALU operation was interrupted before comple- tion of this pins, but WILL NOT turn them back to
tion. Depending on the state of the MULIP bit, I/O or CAPCOM mode. This feature is interesting
the hardware decides whether a mult
iplication
in case of execution of critical real time routines
or division must be continued or not at the end which must not be interrupted or delayed by exterof an interrupt service. The MULIP bit is over- nal HOLD requests.
written with the contents of the stacked MULIP- 5.3.5 IP: Instruction Pointer
flag when the return-from-interrupt-instruction
(RETI) is executed. This normally means that This register determines the 16-bit intra-segment
address of the instruction which is currently
the MULIP-flag is cleared againafter that.
fetched within the code segment selected by the
After reset, all of the ALU status bits are CSP register. The IP register is not mapped into
the ST10x166’s address space, and thus it can not
cleared.
be directly accessed by the programmer. The IP
5.3.4.2 CPU INTERRUPT STATUS (IEN, ILVL)
can, however, be modified indirectly via the stack
The Interrupt Enable bit allows togloballyenable
by means of a return instruction.
(IEN = ‘1’) or disable (IEN = ‘0’) interrupts. The fourThe IP register is implicitly updated by the CPU for
bit Interrupt Level field (ILVL) specifies the priority
branch instructions and after instruction fetch opof the current CPU activity. The interrupt level is
erations.
16/26

5 - Central Processing Unit
CSP (FF08h/04h)
5.3.6 CSP: Code Segment Pointer
This non-bit addressable register selects the code Code Segment Pointer Register
segment being used at run-time to access instruc- Reset Value:0000h
tions. Currently, only two bits of the CSP register
14
13
12
11
10
9
8
are implemented while bits 2 to 15 are reserved for 15
R
future use. The CSP register allows accessing the
entire memory space in currently four segments of
7
6
5
4
3
2
1
0
64 Kbytes each.
R
SEGNR
Code memory addresses are generated by directly
extendingthe 16-bit contents of the IP register by b15 to b2 =R: Reserved.
the contents of the CSP register.
b1,b0 =SEGNR: Code Segment Pointer Register
.
In the case of the segmented memory mode, bit 1 Specifies the code segment number where the
and bit 0 of the CSP register are output on the seg- current instruction is to be tetched. Will be igment address pins A17 and A16 of Port 4 for all ex- nored in the case of segmentation being disternal code accesses. For the non-segmented abled.
memory mode or the Single Chip Mode, the contents of this register are not significant, because all
code acccesses are automatically restricted to
segment 0.
Note that the CSP register can only be read but not
written for data operations. It is, however, modified
either directly by means of the JMPS and CALLS
instructions, or indirectly via the stack by means of
the RETS and RETI instructions. Upon the acceptance of an interrupt or the execution of a software
TRAP instruction, the CSP register is automatically
set to zero. After reset, the CSP register is initialized to ‘0000h’.
Figure 5-5. Addressing via the Code Segment Pointer
C ode segment
3FFFF
3
15
CSP Regis ter
. . .
IP Register
1
SEGNR
2
’0’
. ..
15
0
0
16-Bi t Intra-Segment Address
’0’
SYSCON.
SGTDIS
1
17
16
0
15
0
00000
18-Bi t Code Address
18-Bit Address
Sp ace
VR001621
17/26

5 - Central Processing Unit
DPP0 (FE00h / 00h)
5.3.7 DPP0, DPP1, DPP2, DPP3: Data Page
Pointers
Data Page Pointer Registers
These four non-bit addressable registers select up Reset Value : 0000h
to four different data pages being active at run14
13
12
11
10
9
8
time. Currently, only the four least significant bits of 15
each DPP register are implem
ented whilethe bits
R
R
R
R
R
R
R
R
4 to 15 are reserved for future use. The DPP regis6
5
4
3
2
1
0
ters allow accessing the entire memory space in 7
currently 16 pages of 16 Kbytes each.
R
R
R
R
DPP0PN
The DPP registers are implicitly used whenever
data accesses to any memory space are made via
indirect or direct long 16-bit addressing modes (ex-DPP1 (FE02h / 01h)
cept for PEC data transfers). After reset, the Data Data Page Pointer Registers
Page Pointers areinitializedin a way that all indi- Reset Value 0001h
rect or direct long 16-bit addresses result in identi- 15
14
13
12
11
10
9
8
cal 18-bit addresses. This allows accessing data
R
R
R
R
R
R
R
R
pages 0 to 3 in segment 0 as shown in figure 5.6. If
the user does not want to use any data paging, no 7
6
5
4
3
2
1
0
further action is required.
R
R
R
R
DPP1PN
Data paging is performed by extending the lower
14 bits of indirect or direct long 16-bit addresses by
the contents of a DDP register as shown in figure DPP2 (FE04h / 02h)
5.7. The two MSBs of the 16-bit address are interpreted as the number of the DPP register which is Data Page Pointer Register
to be used for the address extension. The contents Reset Value : 0002h
of the selected DPP register specify one of cur- 15
14
13
12
11
10
9
8
rently sixteen possible data pages. This 4-bit data
R
R
R
R
R
R
R
R
page number in addition to the
remaining14-bit
page offset address forms the physical 18-bit ad- 7
6
5
4
3
2
1
0
dress.
R
R
R
R
DPP2PN
In the case of the non-segmented memory mode,
only the two least significant bits of the implicitly selected DPP register are used for the physical ad- DPP3 (FE06h / 03h)
dress generation just described. Thus, extreme
Data Page Pointer Register
care should be taken whenhanginga
c
DPP register contents if a non-segmented memory model is Reset Value : 0003h
selected, because otherwise unexpected results 15
14
13
12
11
10
9
8
could occur.
R
R
R
R
R
R
R
R
In the case of the segmented memory mode, bits 3
7
6
5
4
3
2
1
0
and 2 of the implicitly selected DPP register are
output on the segment address pins A17 and A16
R
R
R
R
DPP3PN
of Port 4 for all external data accesses.
A DPP register can be updated via any instruction
which is capable fomodifying an SFR. Due to the b15 to b4 =R: Reserved.
internal instruction
pipeline,a new DPP value is
b3 to b0 =DPPxPN (x=0 to 3): Data Page Pointer.
not yet usable for the operand address calculation Specified the data page number selected by
of the instruction immediately
ollowing
f
the instrucDPPx. In the case that segmentation is disabled,
tion updating the DPP register.
only the two least significant bits of DPPxPN are
significant!
18/26

5 - Central Processing Unit
Figure 5-6. Default Configuration of the Data PagePointers
Sixteen
16-KByte
Pages
* Note that all of the internal memory is accessible
Page 15
via 16-Bit addresses after reset !
Page 14
Page 13
Page 12
Page 11
15 14
Page 10
16-Bit Data Address
. . .
0
Page 9
Page 8
Page 7
Page 6
Page 5
Page 4
DPP Registers
specify
4-Bit Page Address *
Bit
3
2
1
0
Page 3
0
0
1
1
DPP3
11b
Page 2
0
0
1
0
DPP2
10b
Page 1
0
0
0
1
DPP1
01b
Page 0
0
0
0
0
DPP0
00b
14-Bit
Intra-Page Address
(is concatened to the
DDP contents)
V R001634
Figure 5-7. Addressing via the Data Page Pointers
Sixteen
16-KByte
Pages
* In the case that segmentation is desabled,
only the two least significant bits of the DPPs are used,
and thus only pages 0 to 3 can be specified !
Page 15
Page 14
Page 13
Page 12
Page 11
15 14
Page 10
16-Bit Data Address
. . .
0
Page 9
Page 8
Page 7
Page 6
Page 5
Page 4
DPP Registers
specify
4-Bit Page Address *
Bit
3
2
1
0
Page 3
1
1
1
0
DPP3
11b
Page 2
1
1
0
0
DPP2
10b
Page 1
0
1
1
0
DPP1
01b
Page 0
0
0
0
0
DPP0
00b
14-Bit
Intra-Page Address
(is concatened to the
DDP contents)
VR 0A1634
19/26

5 - Central Processing Unit
5.3.8 CP: Context Pointer
The Switch Context (SCXT) instruction allows savThis non-bit addressable register is used to select ing the contents of the CP register on the stack and
the current register context. This means that the updating the CP with a new value in just one maganizationof the GPRs within
CP register value determines the address of the chine cycle. The or
first GPR within a register bank of up to 16 word- the internal RAM is described in the chapter 3 For
detailed information about the different addressing
wide and/or bytewide GPRs.
modes mentioned in theollowing,
f
see chapter 6
Since the least significant bit of the CP register is
The
CP
register
is
implicitly
used
for address calcutied to ‘0’ and bit 10 is tied to the negated state of
lations
by
different
addressing
modes,
as follows.
bit 9 and bits 11 to 15 are tied to ‘1’ by hardware,
the CP register can only point to even word addresses from 0FA00h to 0DFFEh. Note however,
5.3.8.1 IMPLICIT CP USE WITH SHORT 4-BIT GPR
that it is the user’s res
ponsibilitythat the physical ADDRESSES
GPR address specified via the CP register in addition with the short GPR address must always be an When a short 4-bit GPR address (mnemonic: Rw
internal RAM location. If this condition is not met,or Rb) is used, the four bits specify an address
relative to the memory location specified by the
unexpected results may occur.
contents of the CP register.
After reset, the CP register is
initializedto ‘FC00h’.
Depending on whether a relative word (Rw) or byte
Figure 5.10 shows how the CP register is used to (Rb) GPR address is specified, the short 4-bit GPR
select a register bank. The CP register can be up- address is m
ultipliedeither by two or by one before
dated via any instruction which is capable of modi-it is added to the contents of the CP register as
fying an SFR. Due to the internal instruction shown in figure 5.8. Thus, both byte and word GPR
pipeline,a new CP value is not yet usable for GPR accesses are possible in this way.
address calculations of the instruction immediately
followingthe instruction updating the CP register. GPRs used as indirect address pointers are always accessed wordwise. For some instructions
only the first four GPRs can be used as indirect address pointers. These GPRs are specified via short
CP (FE10h / 08h)
2-bit GPR addresses. The respective physical address calculation is identical to that for the short 4Context Pointer Register
bit GPR addresses.
Reset Value : FC00h
15
14
13
12
11
1
1
1
1
1
10
9
8
CP
5.3.8.2 IMPLICIT CP USE WITH SHORT 8-BIT REGISTER ADDRESSES
When a short 8-bit address (mnemonic: reg or bitoff) is used, and supposed that the respective
value is within a range from F0h to FFh, the four
b15 to b11 =1: Bits tied to ’1’ by hardware. This al- least significant bits are interpreted as short 4-bit
lows possible contents from ’FA00h’ to ’FDFEh’. GPR address while the four most significant bits
Note, however, that valid GPR addresses must are ignored. As shown in figure 5.9, the respective
be situated within the internal RAM space.
physical GPR address alculationis
c
identical to
that for the short 4-bit GPR addresses. For single
b10 to b1 =CP: Context Pointer Register.
bit accesses on a GPR, the GPR’s word address is
Modifiableportion of the CP register.
Note that bit 10 is always forced to the inverse calculated as just described, but the position of the
state of bit 9 by hardware. For software, bit 10 bit within the word is specified by a separate additional 4-bit value.
can only be read but not directly be written.
b0 = 0:
Bit tied to ’0’ by hardware, since only even CP
contents areallowed.
7
6
5
4
3
2
1
0
CP (continuation)
0
20/26

5 - Central Processing Unit
Figure 5-8. Implicit CP Use by Short 4-Bit GPR addressing Modes
Figure 5-9. Implicit CP Use by Short 8-Bit Addressing
21/26

5 - Central Processing Unit
Figure 5-10. Register Bank Selection via the
CP register
5.3.9 SP: Stack Pointer
This non-bit addressable register is used to point to
the top of the internal system stack (TOS). The SP
register is pre-decremented
wheneverdata is to be
pushed onto the stack, and it is post-incremented
whenever data is to be popped from the stack.
Thus, the system stack grows from higher toward
lower memory locations.
Since the least significant bit of the SP register is
tied to ‘0’ and bits 11 to 15 are tied to ‘1’ by hardware, the SP register can only point to even word
addresses from 0F800h to 0FFFEh. After reset,
the SP register is initialized to ‘FC00h’.
The SP register can be updated via any instruction
which is capable of modifying an SFR. Based on
the internal instruction pipeline, a POP or RETURN
instruction must not immediatly follow an instruction updating the SP register.
The maximum system stack size is programmable
via the STKSZ bit field in the SYSCON register.
The address space which can be addressed via
the SP register (addresses from 0F800h to
0FFFEh) can be regarded as virtual stack range
while the physical system stack range is forced by
the hardware to be situated within the internal RAM
with its upperboundaryat address 0FBFEh and
with its lower boundary at the memory location
which is specified by the selected maximum stack
size shown in table 5.7.
Dependingon the selected
maximum stack size, different numbers of significant SP bits are used for the physical address calculation while the remaining bits are masked off.
After reset, the SP register is
initializedin a way
that the system stack can be accessed as usual as
long as the dynamic stack
boundariesdo not exceed the selected maximum stack size. This
means that the (virtual) SP contents are directly
mapped onto identical physical system stack addresses.
The virtual stack address space isubdividedin
s
portions whose size is identical to the maximum
size of the selected physical stack space. All of
these virtual stack portions are mapped onto the
availablephysical stack area by means of an address calculation shown in the
following:A number
of significant bits of the inverted SP contents is
subtracted from the upper stack base address,
0FBFEh. An AND mask being changedepending
d
on the STKSZ bit field determines which of the bits
are significant.
Internal RAM
R15
(CP) + 30
R14
(CP) + 28
R13
R12
Context
Pointer
R11
R10
R9
R8
R7
. ..
R6
R5
R4
R3
R2
R1
(CP) + 2
R0
(CP)
22/26

5 - Central Processing Unit
Physical Stack Address =
SP (FE 12h / 09h)
FBFEh - (~ (SP) ^ 1FEh)
Stack Pointer Register
for 256 words stack size
Reset Value : FC00h
FBFEh - (~ (SP) ^ FEh)
15
14
13
12
11
10
9
8
for 128 words stack size
FBFEh - (~ (SP) ^ 7Eh)
1
1
1
1
1
sp
for 64 words stack size
7
6
5
4
3
2
1
0
FBFEh - (~ (SP) ^ 3Eh)
sp (continuation)
0
for 32 words stack size
The followingexample demonstrates the circular b15 to b11 =1:
stack mechanism which is also an effect of this vir- Bits tied to ’1’ by hardware. This allows possible
tual stack mapping: First, register R1 ispushed
contents from ’F800h’ through ’FFFEh’. Note howonto the lowest physical stack location accordingever, that the physical system stack is forced to into the selected maximum stack size. With the fol- ternal RAM addresses by hardware, as shown in
lowing instr
uction, regist
er R2 will be pushed onto table 5.7.
the highest physical stack location although the SP
is decremented by 2 as for the previous push op- b10 to b1 =sp: Stack Pointer Register.
Modifiable portion of the SP register.
eration.
b0 = 0:
; Assumed stack size is 64
Bit tied to ’0’ by hardware, because only even SP
; Assumed SP content is
contents areallowed.
...
; (SP) =FC82h
; Physical stack address=FB82h
PUSH R1; (SP) =FC80h
; Physical stack address=FB80h
PUSH R2; (SP) =FC7Eh
; Physical stack address=FBFEh
Upon each stack access, the SP register is compared against two stack boundary registers. This
may cause a stack overflow or stack underflow
hardware trap to occur. For more details about the
use of this feature see the description of the
STKOV and STKUN stackboundaryregisters.
Table 5-7. Selectable Physical System Stack Ranges
SYSCON.
(STKSZ)
Physical Stack Spaces
00b
FA00h - FBFFh
256
0 through 8
01b
FB00h - FBFFh
128
0 through 7
10b
FB80h - FBFFh
64
0 through 6
11b
FBC0h - FBFFh
32
0 through 5
Size (words)
Significant SP Bits
23/26

5 - Central Processing Unit
5.3.10 STKUN: Stack Underflow Pointer
This non-bit addressable register is compared try into an interrupt service routine. Then, six addiagainst the SP register after each data pop opera- tional stack word locations are requiredpushing
for
tion from the system stack (i.e. for POP and RE- the IP, PSW, and CSP registers for both the interTURN instructions) and after each addition to the rupt service and the hardware trap service. For
SP register. If the contents of the SP register are more details about the implementation of a stack
greater than the contents of the STKUN register, a overflow trap service routine see chapter 13.
stack overflow hardware trap will occur.
Stack Underflow Condition: (SP) > (STKUN)
Since the least significant bit of the STKUN register
is tied to ‘0’ and bits 11 to 15 are tied to ‘1’ by hardware, the STKUN register can only point to even STKUN (FE16h / 0Bh)
word addresses from 0F800h through 0FFFEh. Af- Stack Underflow Pointer Register
ter reset, the STKUN register isinitialized to
Reset Value : FC00h
‘FC00h’.
15
14
13
12
11
10
9
8
A stack underflow trap can be used for an automat1
1
1
1
STKUN
ic filling of the system stack, for example, when an 1
external user stack is used as a storage extension 7
6
5
4
3
2
1
0
of the internal system stack. For more details about
STKUN
(continuation)
0
the implementation of a stack underflow trap service routine see chapter 13.
b15 to b11 =1 :
Bits tied to ’1’ by hardware. This restricts contents
to values from ’F800h’ to ’FFFEh’.
5.3.11 STKOV: Stack Overflow Pointer
b10
to b1 =STKUN: Stack Underflow Pointer RegThis non-bit addressable register is compared
ister.
against the SP register after each operation which
pushes data onto the system stack (e.g.: PUSH Modifiableportion of the STKUN register.
and CALL instructions or interrupts) and after eachb0 =0:
subtraction from the SP register. If the contents of Bit tied to ’0’ by hardware because only even
the SP register are less than the the contents of the STKUN contents are compared against the SP
STKOV register, a stack overflow hardware trap register.
will occur.
Stack Overflow Condition:(SP) < (STKOV)
Since the least significant bit of the STKOV register STKOV (FE14h / 0Ah)
is tied to ‘0’ and bits 11 to 15 are tied to ‘1’ by hard- Stack Overflow Pointer Register
ware, the STKOV register can only point to even
word addresses from 0F800h to 0FFFEh. After re- Reset Value : FA00h
15
14
13
12
11
10
9
8
set, the STKOV register isinitialized to ‘FA00h’.
The default initialization allows treating a stack
1
1
1
1
1
STKOV
overflow as a fatal error in the cor
respondingtrap
6
5
4
3
2
1
0
service routine. Note, however, that data in the bot- 7
tom of the stack may have been overwritten by the
STKOV (continuation)
0
status information stacked upon servicing the
b15 to b11 =1:
stack overflow trap.
Bits tied to ’1’ by hardware. This restricts contents
The stack overflow trap could also be used for to values from F800h to FFFEh.
automatic system stack flushing when the system
stack is used as a ‘Stack Cache’ for an external b10 to b1 =STKOV: Stack Overflow Pointer Reguser stack. In this case, the STKOV register should ister.
be initialized to a value which represents the de- Modifiableportion of the STKOV register.
sired lowest Top of Stack address plus 12 accord- b0 =0:
ing to the selected maximum stack size. This Bit tied to ’0’ by hardware because only even
considers the worst case that will occur when a STKOV contents are compared against the SP
stack overflow condition is detected just during en- register.
24/26

5 - Central Processing Unit
5.3.12 MDH: Multiply/Divide Register High
5.3.13 MDL: Multiply/Divide Register Low
Portion
Portion
This register is implicitly used by the CPU when it This register is implicitly used by the CPU when it
performs a multiplication or a division. After a mul-performs a multiplication or a division. After a multiplication, this non- bit addressable register repre-tiplication, this non-bit addressable register represents the high order 16 bits of the 32-bit result. For sents the low order16 bits of the 32-bit result. For
long divisions, the MDH register must loaded
be
long divisions, MDL must be loaded with the low orwith the high order 16 bits of the 32-bit
dividendbeder 16 bits of the 32-bit dividend before the division
fore the division is started. After any division, the is started. After any division, the MDL register repMDH register represents the 16-bit remainder.
resents the 16-bit quotient.
Whenever this register is updated via software, the Whenever this register is updated via software, the
Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Register In Use (MDRIU) flag in the
Multiply/Divide Control register (MDC) is set to ‘1’. Multiply/Divide Control register (MDC) is set to ‘1’.
When a multiplication or division is interrupted be-The MDRIU flag is cleared whenever the MDL register is read via software. When a multiplication or
fore its completion
and when a new mult
iply or divide operation is to be performed in the interrupt division is interrupted before its completion, and
service routine, the MDH register must be saved when a new multiply or divide operation is to be
along with the MDL and MDC registers to avoid er- performed in the interrupt service routine, the MDL
register must be saved along with the MDH and
roneous results.
MDC registers to avoid erroneous results.
After reset, this register is initialized‘0000h’.
to
After reset, this register is
initializedto ‘0000h’.
A detailed description of how to use the MDH regA
detailed
description
of
how to use the MDL regisister for programming multiply and divide algoter
for
programming
multiply
and divide algorithms
rithms can be found in section 13.2.
can be found in section 13.2.
MDL (FE0Eh / 07h)
Multiply Divide Register Low Portion
Reset Value :0000h
MDH (FE0Ch / 06h)
Multiply Divide Register High Portion
Reset Value :0000h
15
14
13
12
11
10
9
8
15
14
13
12
6
5
4
10
9
8
3
2
1
0
MDL
MDH
7
11
3
2
1
0
MDH (continuation)
7
6
5
4
MDL (continuation)
b15 to b0 = MDH: Multiply Divide Register High b15 to b0 = MDL: Multiply Divide Register Low
Portion
Portion
Specifies the high order 16 bits of the 32-bit Mul- Specifies the low order 16 bits of the 32-bit Multiply and Divide Register (MD).
tiply and Divide Register (MD).
25/26

5 - Central Processing Unit
5.3.14 MDC: Multiply/Divide Control Register
MDC (FE0Eh / 87h)
This bit addressable 16-bit register is implicitlyMultiply/Divide Control Register
used by the CPU when it performs a multiplication Reset Value : 0000h
or a division. It is used to store the required control
15
14
13
12
11
10
9
8
information for the corres
ponding multiply or divide
operation. The MDC register is updated by hardR
ware during each single cycle of a multiply or divide
7
6
5
4
3
2
1
0
instruction.
!
!
!
MDRIU
!
!
!
!
When a division or mult
iplicationwas interrupted
before its completion, the MDC register must first b15 to b8 =R: Reserved.
be saved along with the MDH and MDL registers
(to be able to restart the interrupted operation b7 to b5 - b3 to b0 =!:
These bit portions are used by the machine for
later), and then it must be cleared to be
prepared
for the new calculation. After completion ofthe new controllingmultiply and divide operations interdivision or multiplication, the state of the inter- nally. Thus, they should never be modified by the
rupted multiply or divide operation must be re- user except after having saved the previous MDC
contents or by restoring the MDC register.
stored.
b4
=MDRIU: MD Register In Use Flag.
The MDRIU flag is the only portion of the MDC regIs
set to ’1’ when the MDL or MDH register is writister which might be of interest for the user. The reten
by software, or when a divide or multiply inmaining portions of the MDC register are reserved
for a dedicated use by the hardware, and thus they struction is executed. This MD-Register-inshould never be modified by the user other than as Use-Flag is cleared when the MDL register is
read by software.
described in theprecedingparagraph. Otherwise,
a correct continuation of an interrupted multiply or
divide operation can not be
guaranteed.
After reset, this register is initialized‘0000h’.
to
ONES (FE1Eh / 8Fh)
A detailed description of how to use the MDC reg- Constant Ones Register
ister for programming multiply and divide algoReset Value : FFFFh
rithms can be found in section 13.2..
15
14
13
12
11
10
9
8
1
1
1
1
1
1
1
1
5.3.15 ONES: Constant Ones Register
6
5
4
3
2
1
0
All bits of this bit-addressable register are tied to ‘1’ 7
by hardware. This register read-only
is
. The ONES
1
1
1
1
1
1
1
1
register can be used as a register-addressable
b15 to b0 =1:
constant of all ones, i.e., for bit
manipulationor
mask generation. It can be accessed via any in- All of the bits are tired to ’1’ by hardware. The entire ONES register isread-only.
struction which is capable of addressing an SFR.
5.3.16 ZEROS: Constant Zeros Register
All bits of this bit- addressable register are tied to ‘0’ZEROS (FF1Ch / 8Eh)
by hardware. This register is read-only. The ZE- Constant Zeros Register
ROS register can be used as a register- address- Reset Value :0000h
able constant of all zeros, i.e., for bit
manipulation
14
13
12
11
or mask generation. It can be accessed via any in- 15
struction which is capable of addressing an SFR.
0
0
0
0
0
10
9
8
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
b15 to b0 =0:
All of the bits are tired to ’0’ by hardware. The entire ZEROS register is read-only.
26/26


CHAPTER 6
INSTRUCTION SET OVERVIEW
6. INSTRUCTION SET OVERVIEW
This chapter describes the ST10x166’s instruction 6.1.2 Logical Instructions
set. In the first section, a short overview of all avail- Bitwise ANDing of two words or bytes:
able instructions ordered by instruction classes is
AND
ANDB
given. The second section describes which the ad- Bitwise ORing of two words or bytes:
dressing modes av
ailable for each class. Section
OR
ORB
6.3 contains a description of the condition codes
Bitwise XORing of two words or bytes:
availablefor conditional branch instructions.
XOR
XORB
A detailed description of each instruction,
including
its operand data type, condition flag settings, addressing modes, length (number of bytes) and ob- 6.1.3 Boolean Bit Manipulation Instructions
ject code format can be found appendixA.
in
Manipulation of a maskable bit field in either the
high or the low byte of a word:
BFLDH BFLDL
6.1 SUMMARY OF INSTRUCTION CLASSES
Setting of a bit:
This section contains a summary of the
BSET
ST10x166’s instruction set subdivided in instruc- Clearingof a bit:
tion classes. Mnemonic instruction names refer to
BCLR
the corresponding descriptionappendixA
in
where
Movement of a bit:
one can gain more detailed information.
BMOV
Movement of a negated bit:
6.1.1 Arithmetic Instructions
BMOVN
Addition of two words or bytes:
ANDing of two bits:
ADD
ADDB
BAND
Addition with Carry of two words or bytes:
ORing of two bits:
ADDC
ADDCB
BOR
Subtraction of two words or bytes:
XORing of two bits:
SUB
SUBB
BXOR
Subtraction with Carry of two words or bytes:
Comparison of two bits:
SUBC
SUBCB
BCMP
16x16 bit signed or unsigned multiplication:
MUL
MULU
6.1.4 Compare and Loop Control Instructions
16/16 bit signedor unsigned division:
Comparison of two words or bytes:
DIV
DIVU
CMP
CMPB
32/16 bit signedor unsigned division:
Comparison of two words with post-increment
DIVL
DIVLU
by either 1 or 2:
1’s complement of a word or byte:
CMPI1
CMPI2
CPL
CPLB
Comparison of two words with post-decrement
2’s complement (negation) of a word or byte:
by either 1 or 2:
NEG
NEGB
CMPD1 CMPD2
1/8
6 - Instruction Set Overview
6.1.5 Shift and Rotate Instructions
Shifting right of a word:
SHR
Shifting left of a word:
SHL
Rotating right of a word:
ROR
Rotating left of a word:
ROL
Arithmetic shifting right of a word (sign bit shifting):
ASHR
6.1.6 Prioritize Instruction
Determination of the number of shift cycles required to normalize a word operand (floating
point support):
PRIOR
6.1.7 Data Movement Instructions
Standard data movement of a word or byte:
MOV
MOVB
Data movement of a byte to a word location
with either sign or zero byte extension:
MOVBS MOVBZ
with a post-inversion of the tested bit in case of
jump taken (semaphore support):
JBC
JNBS
Conditionalcalling of an either absolutly or indirectly addressed subroutine within the current
code segment:
CALLA CALLI
Unconditional allingof
c
a relatively addressed
subroutine within the current code segment:
CALLR
Unconditional allingof
c
an absolutely addressed subroutine within any code segment:
CALLS
Unconditional allingof
c
an absolutely addressed subroutine within the current code
segment plus anadditionalpushing of a selectable register onto the system stack:
PCALL
Unconditional branching to the interrupt or trap
vector jump table in code segment 0:
TRAP
6.1.10 Return Instruction
Returning from a subroutine within the current
code segment:
RET
Returning from a subroutine within any code
6.1.8 System Stack Instructions
segment:
Pushing of a word onto the system stack:
RETS
PUSH
Returning from a subroutine within the current
Popping of a word from the system stack:
code segment plus an
additionalpopping of a
POP
selectable register from the system stack:
Saving of a word on the system stack, and then
RETP
updating the old word with a new value (proReturning from an interrupt service routine:
vided for register bank switching):
RETI
SCXT
6.1.11 System Control Instructions
6.1.9 Jump and Call Instructions
Conditional jumping to an either absolutely, indi- Resetting the ST10x166 by software:
rectly, or relatively addressed target instruction
SRST
within the current code segment:
Entering the Idle mode:
JMPA
JMPI JMPR
IDLE
Unconditional jumping to an absolutely adEntering the Power Down mode:
dressed target instruction within any code
PWRDN
segment:
Servicing the Watchdog Timer:
JMPS
SRVWDT
Conditional jumping to a relatively addressed
Disablingthe Watchdog Timer:
target instruction within the current code segmentdependingon the state of a selectable bit:
DISWDT
Signifying the end of the
initialization routine
JB
JNB
(pullsRSTOUT
pin
high,
and disables the effect
Conditional jumping to a relatively addressed
of
any
later
execution
of
a DISWDT instruction):
target instruction within the current code segmentdependingon the state of a selectable bit
EINIT
2/8

6 - Instruction Set Overview
6.1.12 Miscellaneous
6.2 ADDRESSING MODES
Null operation which requires 2 bytes of storage
and the minimum time for execution:
The ST10x166 provides many powerful addressing modes for access on word, byte and bit data, or
NOP
to specify the target address of a branch instruction. The addressing modes areubdividedin
s
different categories as follows.
6.1.13 Software Instruction Set
BSO/Tasking provides softwaredevelopment
tools for the ST10includinga C Compiler package 6.2.1 Constants
with the Assembler a166. This accepts all assembly language instruction mnemonics that have The ST10x166 instruction set supports the use of
been described before, and adds a software in- wordwideor bytewide immediate constants. For an
availablecode storage,
struction set which is an extension of the previousoptimum utilization of the
these constants are represented in the instruction
hardware instruction set.
formats by either 3, 4, 8 or 16 bits. Thus, short conThe BSO/Tasking software instruction set recog- stants are always zero-extended while long connises all instructions of the hardware instruction setstants are truncated if necessary to match the data
and some additional mnemonics. These
additional
format required for the particular operation:
mnemonics are added to allow easy and comfortable programming. The assembler will determine Immediate constants are always signified by a
by means of the combination of operands, which leadingnumber sign ‘#’.
opcode is entered in the instruction format. This
means that based on the combination of operands
the appropriat
e hardware mnemonic is chosen.
Please refer to the BSO/Tasking Documentation
for further information.
Table 6-1. Data Type Adaptation of Immediate Constants
Mnemonic
#data3
#date4
#data16
#data8
#mask
Word Operation
0000h + data3
0000h + data4
data16
0000h + data8
0000h + mask
Byte Operation
00h + data3
00h + data4
data 16∧ 0FFh
data8
mask
3/8

6 - Instruction Set Overview
6.2.2 Short Addressing Modes
All of these addressing modes use an implicit base reg:
offset address to specify a physical 18-bit address. (cont’d)
By these addressing modes, data can be specified
within the GPR, SFR or bit-addressable memory
space:
Physical Add. = Base Add.+
∆ x Short Add.
In the following,the short addressing modes which
are shown in table 6.2 are described in more detail:
Rw, Rb: Specifies direct access to any GPR in bitoff:
the currently active context (register
bank). Both ‘Rw’ and ‘Rb’ require four
bits in the instruction format. The base
address is determined by the contents
of the CP register. ‘Rw’ specifies a 4 bit
word GPR address relative to the base
address (CP), while ‘Rb’ specifies a 4
bit byte GPR address relative to the
base address (CP).
reg:
Specifies direct access to any SFR or
GPR in the currently active context
(register bank). ‘reg’equires
r
eightbits
in the instruction format. Short ‘reg’ addresses from 00h to EFh always specify SFRs. In that case, the base
address is 0FE00h and the factor∆’‘
equates 2.Dependingon the opcode of
an instruction, either the total word (for
word operations) or the low byte (for
byte operations) of an SFR can be addressed via ‘reg’.
Note that the high byte of an SFR can
not be accessed via the ‘reg’ addressing mode. Short ‘reg’ addresses from
F0h to FFh always specify GPRs. In
that case, only the lower four bits of
‘reg’ are significant for physical address
generation,and thus it can beregarded
as being identical to the address generation described for the
‘Rb’ and‘Rw’
addressing modes.
Specifies direct access to any word in
the bit-addressable memory space.
‘bit off’ requires eight bits in the instruction format. Depending on the
specified ‘bitoff’ range, different base
addresses are used to generate physical addresses: Short ‘bitoff’ addresses
from 00h to 7Fh use 0FD00h as a base
address, and thus they specify the 128
highest internal RAM word locations
(0FD00h to 0FDFEh). Short ‘bitoff’ addresses from 80h to EFh use 0FF00h
as a base address, and thus they
specify the highest internal SFR word
locations (0FF00h to 0FFDEh). Short
‘bitoff’ addresses from 80h to EFh use
0FF00h as a base address, and thus
they specify the highest internal SFR
word locations (0FF00h to 0FFDEh).
For short ‘bitoff’ addresses from F0h to
FFh, only the lowest four bits and the
contents of the CP register are used to
generate the physical address of the
selected word GPR.
Table 6-2. Short Addressing Modes
Nmemonic
Physical Address
Short Address Range
Allows Access On
Rw
(CP)
+ 2xRw
Rw
= 0...15
GPRs
(Word)
Rb
(CP)
+ 1xRb
Rb
= 0...15
GPRs
(Byte)
reg
0FE00h
(CP)
(CP)
+ 2xreg
+ 2x(reg∧ 0Fh)
+ 1x(reg∧ 0Fh)
reg
reg
reg
= 00h...EFh
= F0h...FFh
= F0h...FFh
SFRs
GPRs
GPRs
(Word. Low Byte)
(Word)
(Byte)
bitoff
0FD00h
0FF00h
(CP)
+ 2xbitoff
+ 2xbitoff∧ 0FFh
+ 2x(bitoff∧ 0Fh)
bitoff
bitoff
bitoff
= 00h...7Fh
= 80h...EFh
= F0h...FFh
RAM
SFR
GPR
Bit Word Offset
Bit Word Offset
Bit Word Offset
bitaddr
Word offset see bitoff;
Immediate Bit Position
bitoff
bitpos
= 00h...FFh
= 0...15
Any Single Bit
4/8

6 - Instruction Set Overview
bitaddr:
Any bit address is specified by a word Any long 16-bit address consists of two portions
address within the bit-addressable which are interpreted in different ways. Bits 0 to 13
memory space (see ‘bitoff’), and by a specify a 14-bit data page offset address while bits
bit position (‘bitpos’) within that word. 14 to 15 specify that of the four Data Page Pointer
Thus, ‘bitaddr’ requires twelve bits in registers which is to be used to generate the physithe instruction format.
cal 18-bit address as described below:
At present, the ST10x166 supports 256 Kbytes of
6.2.3 Long Addressing Mode
address space, and thus only the lowest four bits of
This addressing mode uses one of the four DPP the selected DPP register contents are added to
registers to specify a physical 18-bit address. Any the 14-bit data page offset address. In case of segword or byte data within the entire memory space mentation being disabled, all data accesses are recan be accessed in such a manner. Word ac- stricted on segment 0, and thus only the lowest two
cesses may not be performed on odd byte ad- bits of the selected DPP register are significant at
all. For more details about data paging see secdresses. Otherwise, a hardwarerap
t would occur.
After reset, the DPP registers are initialized in a tion 5.3.7.
The long addressing mode is represented by the
way that all long addresses are directly
mapped
mnemonic ‘mem’. Table 6.3 shows the association
onto the identical physical addresses.
between long 16-bit addresses and the correspondingData Page Pointer registers.
Table 6-3. Long Addressing Mode
Mnemonic
mem
Physical Address
(DPP0)
(DPP1)
(DPP2)
(DPP3)
+
+
+
+
Long Address Range
mem∧ 3FFFh
mem ∧ 3FFFh
mem ∧ 3FFFh
mem ∧ 3FFFh
0000...3FFFh
4000...7FFFh
8000...BFFFh
C000...FFFFh
Allows Access On
Any Byte or Word
Any Byte or Word
Any Byte or Word
Any Byte or Word
Long Address
[Bits 15...14]
Long Address
[Bits 13...0]
specifies x
Physical Address
=
Contents of DPPx
(x = 0 .. 3)
+
Page Offset Address
5/8

6 - Instruction Set Overview
6.2.4 Indirect Addressing Modes
These addressing modes can be regarded as a 2) In case of pre-decrement (signified by a leadmixture of short and long addressing modes. This
ing minus sign ‘-’), the indirect address pointer
means that long 16-bit addresses are specified inis decremented by a data-ty
pe-dependent
directly by the contents of a word GPR which is
value (∆ = 1 for byte operations,
∆ = 2 for word
specified directly by a short 4-bit address (‘Rw’=0
operations) before the long 16-bit address is
to 15). Note that for some instructions only the lowgenerated:
est four word GPRs (R0 to R3) can be used as in(GPR Address) = (GPR Address) - ∆
direct address pointers which are specified via
; optional step !
short 2-bit address in that case. There are indirect
3)
Then, the long 16-bit address is determined by
addressing modes where the GPR contents are
the contents of the indirect address pointer
modified by a constant addition before the long 16(plus a selectable constant value in some
bit address is calculated. Moreover, there are adcases):
dressing modes which allow decrementing or
incrementing the indirect address pointers by a
Long Address = (GPR Address) + Constant
data type-dependentvalue.
4) Afterwards, the physical 18-bit address is deIn each case, one of the four DPP registers is used
termined via the resulting long address and the
to specify physical 18-bit addresses. Any word or
correspondingDPP register contents as albyte data within the entire memory space can be
ready described for the long ‘mem’ addressing
addressed indirectly. Word accesses may not be
modes. For more details about data paging,
performed on odd byte addresses. Otherwise, a
see section 5.3.7.
hardware trap would occur. After reset, the DPP
registers areinitializedin a way that all indirectly 5) In case of Post-Increment (signified by a subsequent plus sign ‘+’), the indirect address
generated long addresses are directly
mapped
pointer value isadditionallyincremented by a
onto the identical physical addresses.
data-type-dependent value∆( = 1 for byte opThe followingalgorithm describes how physical
erations,∆ =2 for word operations):
addresses are generated via indirect address
(GPR Address) = (GPR Address) + ∆
pointers:
; optional step
1) Determination of the physical address of the
word GPR which is used as indirect address The table below gives an overview of the particular
pointer. This address is calculated via the reg- indirect addressing modes of the ST10x166.
ister bank base address specified by the CP
register contents plus two times the specified
short address (‘Rw’).
GPR Address = (CP) + 2 x Short Address
Table 6-4. Indirect Addressing Modes
Mnemonic
Particularity
[Rw]
Normally, any word GPR can be used as indirect address pointer. For some instructions,
however, only the first tour word GPRs can be used as indirect address pointers.
[Rw + ]
The specified indirect address pointer is automatically post-incremented by either 1 (for byte
data operations) or 2 (for word data operations).
[-Rw]
The specified indirect address pointer is automatically predecremented by either 1 (for byte
data operations) or 2 (for word data operations).
[Rw + #data 16]
A 16-bit constant and the contents of the indirect address pointer are added before the long
16-bit address is calculated.
6/8

6 - Instruction Set Overview
6.2.5 Branch Target Addressing Modes
Different addressing modes are provided to spec- value. A special mode is provided to address the
ify the target address and segment of jump or call interrupt and trap jump vector table which is alloinstructions. Relative, absolute and indirect modescated to the lowest portion of code segment 0.
can be used to update the Instruction Pointer (IP) In the following,the branch target addressing
register while the Code Segment Pointer (CSP) modes are described in more detail:
register can be updated only with an absolute
Table 6-5. Branch Target Addressing Modes
Mnemonic
caddr
rel
[Rw]
seg
#trap7
Target Address
(IP) = caddr
(I)=(IP)
(IP)=(IP)
(IP)=((CP)
(IP)=0000h
Target Segment
_
_
_
_
(CSP) =
(CSP) =
+ 2xrel
+ 2x( rel + 1)
+ 2xRw)
+ 4xtrap7
Valid Address Range
seg
0000h
caddr:
Specifies an absolute 16-bit code ad- [Rw]:
dress within the current segment.
Branches MAY NOT be taken to odd
code addresses. Therefore, the least
significant bit of ‘caddr’ must always
contain a ‘0’, otherwise a hardware trap
will occur.
rel:
This mnemonic represents an 8-bit
signed word offset address relative to
the current Instruction Pointer contents
which represent the address of the instruction after the branch instruction.
Depending on the offset address # trap7:
range, either forward (‘rel’ = 00h to 7F)
or backward (‘rel’ = 80h to FFh)
branches are possible. According to an
either word- or double-word sized
branch instruction, a ‘rel’ value of ‘-1’
(FFh) or ‘-2’ (FEh) leads to a repeated
execution of the branch instruction itself.
seg:
Specifies an absolute code segment
number. Currently, the ST10x166 supports four different code segments, and
thus only the two least significant bits of
the ‘seg’ operand value are used for
updating the CSP register.
caddr
rel
rel
Rw
seg
trap7
= 0...FFFEh
= 00h...7Fh
= 80h...FFh
= 0...15
= 0...3
= 0...7Fh
In this case, the 16-bit branch target instruction address is determined indirectly by the contents of a word GPR.
In contrast to indirect data addresses,
indirectly specified code addresses are
NOT calculated via additional pointer
registers (e.g. DPP registers). Note
that branches MAY NOT be taken to
odd code addresses. Therefore, the
least significant bit of the address
pointer GPR must always contain a ‘0’,
otherwise a hardware trap would occur.
Specifies a particular interrupt or trap
number for branching to the corresponding interrupt or trap service routine via a jump vector table. According
to the maximum number of interrupt
sources which are provided for the future, only trap numbers from 00h to 7Fh
can be specified. Any double word
code location in the address range
from 00000h to 001FCh in code segment 0 can be accessed by the ‘trap’
addressing mode. The association between trap numbers and the corresponding interrupt or trap sources is
specified in table 7.1.
7/8

6 - Instruction Set Overview
6.3 CONDITION CODE SPECIFICATION
monic abbreviations are av
ailablefor that. It also
describes which kinds of tests are performed due
16 possible conditioncodes can be used to deter- to the selected condition code, and it shows the asmine whether aconditionalbranch shall be taken sociation between the condition codes and their inor not. Table 6.6 gives an overview of which mne- ternal representation by a four-bit number.
Table 6-6. Condition Codes
Condition Code
Mnemonics
Test
Description
cc_UC
1 =1
Unconditional
cc_Z
Z=1
Zero
2h
cc_NZ
Z=0
Not zero
3h
cc_V
V=1
Overflow
4h
cc_NV
V=0
No overflow
5h
cc_N
N =1
Negative
6h
cc_NN
N =0
Not negative
7h
cc_C
C =1
Carry
8h
cc_NC
C =0
No carry
9h
cc_EQ
Z =1
Equal
2h
cc_NE
Z=0
Not equal
3h
cc_ULT
C=1
Unsigned less than
8h
cc_ULE
(ZVC) = 1
Unsigned less than or equal
Fh
cc_UGE
C=0
Unsigned greater than or equal
9h
cc_UGT
(ZVC) = 0
Unsigned greater than
Eh
cc_SLT
(N⊕V) = 1
Signed less than
Ch
cc_SLE
(ZV(N⊕V)) = 1
Signed less than or equal
Bh
cc_SGE
(N⊕V) = 0
Signed greater than or equal
Dh
cc_SGT
(ZV(N⊕V)) = 0
Signed greater than
Ah
cc_NET
(ZVE) = 0
Not equal AND not end of table
1h
8/8

CC
Number
0h
CHAPTER 7

INTERRUPT AND TRAP FUNCTIONS
7. INTERRUPT AND TRAP FUNCTIONS
The architecture of the ST10x166 supports several is halted for 1 instruction cycle. No internal promechanisms for fast and flexible response to serv- gram status information needs to be saved. For
ice requests that can be generated from various PEC service, the same prioritization scheme is apsources internal or external to the microcontroller.plied which is used for normal interrupt processing.
These mechanisms include:
PEC transfers share the 2 highest priority levels.
- Normal Interrupt Processing
- Trap Functions:
The CPU temporarily suspends the current pro- In response to the execution of certain instructions,
gram execution and branches to an interrupt serv- trap functions are activated. A trap can also be
ice routine in order to service an interrupt caused externally by the Non-Maskable Interrupt
requesting device. The current program status (IP, pin NMI. Several hardware trap functions are proPSW, in segmentation mode also: CSP) is saved vided forhandlingerroneous conditions and exon the internal system stack. A prioritization ceptions that arise during the execution of an
scheme with 16 priority levels allows the user to instruction. Hardware traps always have highest
specify the order in which multiple interrupt re- priority and cause immediate system reaction. The
quests are to be handled.
software trap function is invoked by the TRAP instruction which generates a software interrupt for a
- Interrupt Processing via the Peripheral Event
specified interrupt vector. For all types of traps, the
Controller (PEC):
current program status is saved on the system
As a faster alternative to normal software oriented stack.
interrupt processing, any interrupt requesting
source can also be serviced by the ST10x166’s in- Warning: When program code is installed in the
Flash memory (ST10F166) and located in segtegrated Peripheral Event
Controller
. Upon an inment 0, the CPU can receive an interrupt, but will
terrupt request, the PEC has the apability
c
of
w operation
performing a single word or byte data transfer be- not be able to service it during ariting
on
the
Flash
memory.
This
condition
can be avoid
tween any two memory locations in segment 0
(data pages 0 through 3) through one of eight pro- ed with the Flash memory located in segment 1
and the program code in segment 0 (external
grammable PEC ServiceChannels.During a PEC
transfer, the normal program execution of the CPU memory).
1/24
7 - Interrupt And Trap Functions
7.1 INTERRUPT SYSTEM STRUCTURE
In order to support modular and consistent soft- TFR can then be used to determine the type of the
ware design echniques
t
, each source of an inter- trap (see section 7.2 for more details). For the special software TRAP instruction, the vector address
rupt or PEC request issuppliedwith a separate
interrupt control register and interrupt vector. Theis specified by the operand field of the instruction,
control register contains the interrupt request flag,which is a seven bit trap number.
the interrupt enable bit, and the interrupt priority ofThe reserved vector locations of the ST10x166’s
the associated source. Each source request is ac- memory space form a jump table. Here, one can
tivated by one specific event,ependingon
d
the seplace the appropriat
e jump instructions to the
lected operating mode of the respective device. memory locations where the interrupt or trap servThe only exceptions are the two serial
channelsof
ice routines will actually start. The entries to the
the ST10x166, where an error interrupt request jump table are located at the lowest addresses in
can be generated by a parity, framing, or overrun code segment zero of the memory space. Jump taerror. However, specific status flags which identifyble entries have a distance of 4 bytes between
the type of error are implemented in the serial consecutive entries, except for the reset vector and
channels cont
rol registers (see section 8.4 for de- the hardware trap vectors where the distance is 8
tails).
or 16bytes.
The ST10x166 provides a vectored interrupt sys- The followingtable contains all sources that are
tem. In this system, certain vector locations in the capable of requesting interrupt or PEC service in
memory space are reserved for the reset, trap, and the ST10x166, includingthe associated interrupt
interrupt service functions. Whenever a request vectors and trap numbers. Also listed are the mneoccurs, the CPU branches to one of these locations monics of the affected Interrupt Request flags and
which is predetermined by hardware. This allows their correspondingInterrupt Enable flags. The
direct identification of the source that caused the mnemonics are composed of a part that specifies
request. The only exceptions are the class B hard- the respective source, followed by a part that
ware traps, which all share the same vector ad- specifies their function (IR=Interrupt Request flag,
dress. The status flags in the Trap Flag Register IE=Interrupt Enable flag).
2/24

7 - Interrupt And Trap Functions
Table 7-1. Interrupt Sources And Associated Interrupt Vectors
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0
CC0IR
CC0IE
CC0INT
40h
10h
CAPCOM Register 1
CC1IR
CC1IE
CC1INT
44h
11h
CAPCOM Register 2
CC2IR
CC2IE
CC2INT
48h
12h
CAPCOM Register 3
CC3IR
CC3IE
CC3INT
4Ch
13h
CAPCOM Register 4
CC4IR
CC4IE
CC4INT
50h
14h
CAPCOM Register 5
CC5IR
CC5IE
CC5INT
54h
15h
CAPCOM Register 6
CC6IR
CC6IE
CC6INT
58h
16h
CAPCOM Register 7
CC7IR
CC7IE
CC7INT
5Ch
17h
CAPCOM Register 8
CC8IR
CC8IE
CC8INT
60h
18h
CAPCOM Register 9
CC9IR
CC9IE
CC9INT
64h
19h
CAPCOM Register 10
CC10IR
CC10IE
CC10INT
68h
1Ah
CAPCOM Register 11
CC11IR
CC11IE
CC11INT
6Ch
1Bh
CAPCOM Register 12
CC12IR
CC12IE
CC12INT
70h
1Ch
CAPCOM Register 13
CC13IR
CC13IE
CC13INT
74h
1Dh
CAPCOM Register 14
CC14IR
CC14IE
CC14INT
78h
1Eh
CAPCOM Register 15
CC15IR
CC15IE
CC15INT
7Ch
1Fh
CAPCOM Timer 0
T0IR
T0IE
T0INT
80h
20h
CAPCOM Timer 1
T1IR
T1IE
T1INT
84h
21h
GPT1 Timer 2
T2IR
T2IE
T2INT
88h
22h
GPT1 Timer 3
T3IR
T3IE
T3INT
8Ch
23h
GPT1 Timer 4
T4IR
T4IE
T4INT
90h
24h
GPT2 Timer 5
T5IR
T5IE
T5INT
94h
25h
GPT2 Timer 6
T6IR
T6IE
T6INT
98h
26h
GPT2 CAPREL Register
CRIR
CRIE
CRINT
9Ch
27h
A/D Conversion Complete
ADCIR
ADCIE
ADCINT
A0h
28h
A/D Overrun Error
ADEIR
ADEIE
ADEINT
A4h
29h
Serial channel 0 Transmit
S0TIR
S0TIE
S0TINT
A8h
2Ah
Serial channel 0 Receive
S0RIR
S0RIE
S0RINT
ACh
2Bh
Serial channel 0 Error
S0EIR
S0EIE
S0EINT
B0h
2Ch
Serial channel 1 Transmit
S1TIR
S1TIE
S1TINT
B4h
2Dh
Serial channel 1 Receive
S1RIR
S1RIE
S1RINT
B8h
2Eh
Serial channel 1 Error
S1EIR
S1EIE
S1EINT
BCh
2Fh
3/24

7 - Interrupt And Trap Functions
The vector locations for hardware traps and the est priority (trap priority III). For more details on recorrespondingstatus flags in register TFR are set refer to chapter 1.
listed in table 7.2. Also listed are the priorities of Software traps may be performed to any vector lotrap service in case simultaneous trap conditionscation between 0h and 1FCh. A routine entered by
might be detected within the same instruction. Af- a software TRAP instruction is always executed on
ter any reset (hardware reset, software reset in- the current CPU priority level whichindicated
is
in
struction SRST, or reset by watchdog timer the ILVL field in the PSW. This means that routines
overflow), program execution starts from locationentered via the software TRAP instruction can be
0000h. Reset conditionshave priority over every interrupted by all hardware traps or higher level inother system activity and ther
efore have the high
terrupt requests.
Table 7-2. Reset And Trap Vector Locations
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
-
RESET
RESET
RESET
0h
0h
0h
0h
0h
0h
III
III
III
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
08h
10h
18h
2h
4h
6h
II
II
II
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
28h
28h
28h
28h
28h
Ah
Ah
Ah
Ah
Ah
I
I
I
I
I
Exception Condition
Reset Functions :
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps :
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps :
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
[2Ch-3Ch]
[Bh-Fh]
Software Traps
TRAP Instruction
Any
[0h-1FCh]
in steps
of 4h
Any
[0h-7Fh]
Current
CPU
Priority
7.2 NORMAL INTERRUPT PROCESSING
AND PEC SERVICE
The priority of service for interrupts and PEC re- simultaneous requests from a group of different
quests is completely programmable. Each source sources on the same priority level. At the end of the
request can be assigned to a specific priority. Once instruction cycle, only one source with the highest
per instruction cycle, all sources which require priority will be left with control of the interrupt sysenabledfor servicing
PEC or interrupt processing will contend for servic-tem. This source will then be
is
than the cur
ing. Every requesting source will try to exert its pri-if the priority of the request higher
ority on the interrupt system. A special mechanismrent CPU priority in the PSW. This arbitration,
(called ‘group priority’) has been implemented thatwhich occurs once every instruction cycle, is called
allows the specification of the order of service fora ‘round of prioritization’.
4/24

7 - Interrupt And Trap Functions
7.2.1 Interrupt System Register Description
xxIC
Interrupt processing is controlled
globallyby the
Interrupt Control Register for Source xx
PSW through a general interrupt enable bit (IEN) Reset Value :0000h
and the CPU priority field (ILVL).dditionally
A
, the
6
5
4
3
2
1
0
different interrupt sources are controlled individu- 7
ally by their specific interrupt control registers. xxIR
xxIE
ILVL
GLVL
Thus, the acceptance of requests by the CPU is
determined by both the individual interrupt controlb7 = xxIR: Interrupt Request Flag.
registers and the PSW. For PEC service, one addi- xxIR = 0: No interrupt request
tional dedicated register and 2 pointers must be xxIR = 1: Interrupt request.
programmed in order to specify the task which is tob6 = xxIE: Interrupt Enable Control Bit.
be performed by the respective PEC service chan- xxIE = 0: Interruptdisabled
nel.
xxIE = 1: Interruptenabled.
b5 to b2 =ILVL: Interrupt Priority Level.
ILVL = Fh: Highest priority level
7.2.1.1 INTERRUPT CONTROL REGISTERS
ILVL = 0: Request will not be serviced.
All interrupt control registers are organized identically. An interrupt control register is 8 bits wide andb1, b0 = GLVL: Interrupt Group Priority.
contains the complete interrupt status information GLVL = 3: Highest group priority
of the associated source which is required during GLVL = 0: Lowest group priority.
one round of prioritization. All interrupt control registers are bit addressable, and all bits can be read
or written by software. This allows each interrupt
source to be programmed or modified with just one
instruction. When accessing interrupt control registers through instructions which operate on word
data types, bits 8 through 15 will be read as zeros, xxIE - Interrupt Enable Flag
while the written value is
insignific
ant.
This bit is used to indiv
idually enable or disable the
acceptance of a service request.
Besides, an example of the ST
10x166’s Interrupt
Control registers xxIC is shown, where xx replaces ILVL - Interrupt Priority Level Field, xxIC[5..2]
the mnemonic for the specific source. Each interrupt control register with its name and address willThese four bits specify the priority level of a service
request. Values from 0h through Fh can be specibe shown in the specific section on the
peripheralit
is associated with (see chapter 8). The function of fied in this field, where Fh represents the highest
each single or multiple bit field of an interrupt con-priority level.
trol register is described in more detail in the
ollow
fInterrupt requests that are programmed to priority
ing paragraphs.
levels 15 or 14 (i.e. ILVL=111Xb) will be serviced
by the PEC, unless the COUNT field of the associxxIR - Interrupt Request Flag
ated PEC channel contains zero. In this case, the
This bit is set by hardware whenever a service re- request will be serviced by normal interrupt procquest from source xx occurs. The Interrupt Re- essing. Interrupt requests that are programmed to
quest flag is automatically cleared upon entry to priority levels 13 through 1illwalways be serviced
the interrupt service routine or upon service of theby normal interrupt processing.
request by the PEC. In the case of PEC service,
the Interrupt Request flag remains set if the For interrupt requests which are selected for PEC
COUNT field of the selected PEC channel goes to service by the method described above, the LSB of
zero (see section 7.2.2.1 for details). This allows a ILVL represents the MSB of the associated PEC
normal CPU interrupt to respond to a completed channel number. In other words, by programming
PEC block transfer. Modifying the Interrupt Re- a source on priority level 15 (ILVL=1111b), PEC
quest flag by software causes the same effects as channels7 through 4 can be selected. By programming a source on priority level 14 (ILVL=1110b),
if it had been set or cleared by hardware.
5/24

7 - Interrupt And Trap Functions
PEC channels 3 through 0 can be selected. The These two bits are interpreted as the relative prioractual PEC channel number is then determined by ity of an interrupt service request within a group of
the Group Priority field GLVL which is described insimultaneous requests from different sources on
the followingparagraph. Figure 7.1 shows the the same priority level. For sources which are promapping of the ILVL and GLVL fields and their in- grammed for PEC service in their ILVL fields, the 2
terpretation during a round of prioritization.
bits of GLVL represent the 2 LSBs of the associDuring the prioritization process, the ILVL fields ofated PEC channel number. See also figure 7.1.
all interrupt requesting sources are compared to The group priority field is particularly relevant for
the current CPU priority level which is contained inresolving simultaneous interrupt requests from
the ILVL field of the PSW. An interrupt request of several sources on the same priority level. Up to 4
higher priority than the current CPU priority can in-sources can be programmed to the same priority
level. They are prioritized according to
heir
t group
terrupt the executing routine.
priority,
where
3
is
highest
group
priority.
This also
Upon entry into an interrupt service routine, the primeans
that
s
i
multaneous
requests
for
PEC
service
ority level of the source that won the arbitration is
are prioritized according to their PEC
channel
copied into the ILVL field of the PSW after
pushing
number:
the
PEC
channel
with
the
highest
number
the old PSW contents on the stack.
has the highest priority.
The interrupt system of the ST10x166 allows nestenabled and
ing of up to 15 interrupt service routines of differentNote: All interrupt sources that are
programmed
to
the
same
priority
level
must always
priority levels. Note that an interrupt source which
be
programmed
to
different
group
priorities.
Othis programmed to priority level 0 will never be serverwise,
an
incorrect
interrupt
vector
will
be
genericed by the CPU, because its priority level can
ated.
never be higher than the CPU priority.
Figure 7.2 exemplifies the possible configurations
GLVL - Interrupt Group Priority Field, xxIC[1..0]
which can be programmed in the interrupt control
registers.
7.2.1.2 INTERRUPT CONTROL FUNCTIONS IN THE
PSW
Figure 7-1. Mapping Of ILVL And GLVL Fields For The Interrupt Control Registers
Interrupt
Control Register
ILVL
Prioritization
GLVL
PEC Channel #
Priority Level
6/24

Group Priority
7 - Interrupt And Trap Functions
Figure 7-2. Examples Of Possible Configurations In The Interrupt Control Registers
Field
Type of Service
(COUNT: PEC Transfer Counter field Of Selected PEC Channel)
ILVL
GLVL
1 111
11
If COUNT ≠ 0: PEC Service, Channel 7
1 111
11
If COUNT = 0: CPU Interrupt, Priority Level 15,
Group Priority 3
1 111
10
If COUNT ≠ 0: PEC Service, Channel 6
1 111
10
If COUNT = 0: CPU Interrupt, Priority Level 15,
Group Priority 2
1 110
11
If COUNT ≠ 0: PEC Service, Channel 3
1 110
11
If COUNT = 0: CPU Interrupt, Priority Level 14,
Group Priority 3
1 110
00
If COUNT ≠ 0: PEC Service, Channel 0
1 110
00
If COUNT = 0: CPU Interrupt, Priority Level 14,
Group Priority 0
1 101
11
CPU Interrupt, Priority Level 13, Group Priority 3
1 101
10
CPU Interrupt, Priority Level 13, Group Priority 2
1 101
01
CPU Interrupt, Priority Level 13, Group Priority 1
1 101
00
CPU Interrupt, Priority Level 13, Group Priority 0
0 001
00
CPU Interrupt, Priority Level 1, Group Priority 0
0 000
11
No Service
0 000
10
No Service
0 000
01
No Service
0 000
00
No Service
7/24

7 - Interrupt And Trap Functions
The Processor Status Word (PSW) is funct
ionally
Because a PEC data transfer takes only one individed into 2 parts: the lower byte of the PSW ba- struction cycle and is never interrupted, the CPU
sically represents the arithmetic status of the CPU, priority field remains unaffected by a PEC service.
the upper byte of the PSW controls the interrupt For hardware traps, the CPU priority is set to the
system of the ST10x166. This section specifically highest priority level (i.e. 15) in the ILVL field of the
refers only to those fields of the PSW that
globally
PSW. Therefore, no interrupt or PEC request can
control interrupt and PEC service functions. The be serviced while an exception trap service routine
organization of the PSW is shown in figure 7.3.
is in progress. The software TRAP instruction,
ILVL - CPU Priority Field, PSW[15..12]
however, does not change the CPU priority in the
These four bits represent the priority level of the ILVL field of the PSW, thus it can be interrupted by
routine that is currently being executed by the higher level requests.
CPU. During reset, the CPU Priority field is initial- IEN - Interrupt Enable Control Bit, PSW.11
ized to the lowest priority level (i.e. level 0). Upon This bitgloballyenables or disables PEC
operation
entry to an interrupt service routine, the four bitsand the acceptance of interrupts by the CPU.
from the interrupt source’s Priority Level field ILVLWhen IEN is cleared, no interrupt requests are acare copied into these four bits of the PSW, after the cepted by the CPU. When IEN is set to ‘1’, all interprevious contents of the PSW have been
pushed
rupt sources, which have been indiv
idually
onto the system stack.
enabledby the Interrupt Enable bits in their associTo determine which interrupt will be serviced, the ated control registers, are
globally enabled.
interrupt system ontinuously
c
compares the cur- Note: Traps are non-maskable and are therefore
rent CPU priority to the priority levels ofpending
all
not affected by the IEN bit.
interrupts. Modifying the ILVL field of the PSW offers the capabilityof programming the priority level
below which the CPU can not be interrupted.
7.2.2 PEC Service Channels Register
Description
Figure 7-3. Interrupt Control Functions In The PSW
PSW (FF10h / 88h)
Processor Status Word
Reset Value :0000h
15
14
13
12
ILVL
11
10
IEN
HLDEN
9
8
R
7
6
5
4
3
2
1
0
R
USR0
MULIP
E
Z
V
C
N
8/24

7 - Interrupt And Trap Functions
The ST10x166’s Peripheral Event Controller PECCy
(PEC) provides 8 PEC Service
Channels. Upon an
PEC Channel Counter/Control Registers, Organiinterrupt request, a PEC channel is capable of per- zation (y = 0 through 7)
forming a single byte or word data transfer between any two memory locations in segment 0 Reset Value :0000h
(data pages 0 through 3). Each channel consists of 15
14
13
12
11
10
9
8
a dedicated PECChannelCounter/Control register
R
INC
BWT
and a pair of pointers for source and destination of
the data transfer.
7
6
5
4
3
2
1
0
7.2.2.1 PEC CHANNEL COUNTER/CONTROL REGISTERS
COUNT
Each of the 8 PEC servic
e channels implem
ented
b15 to b11 =R: Reserved.
in the ST10x166 issuppliedwith a separate PEC
Channel Counter
/Control register. Note that these b10, b9 = INC: Increment Control Field:
registers are NOT bit addressable. They will be re- INC = 00b: Increment no pointer
ferred to as PECCy, where y represents the num- INC = 01b: Increment destination pointer
INC = 10b: Increment source pointer
ber of the associated PEC channel (y=0
hrough
t
7). Each register specifies the task which is to be INC = 11b: (Reserved).
performed by the associated PEChannel
c
. A speb8 = BWT: Byte/Word Transfer Select bit:
cific PEC channel is selected by an interrupt BWT = 0: Word Transfer
source through the ILVL and GLVL field in the in- BWT = 1: Byte Transfer.
terrupt control register of the respective source
b7 to b0 =COUNT: PEC Transfer Counter Field:
(see figure 7.1). Table 7.3 lists all PEC
channel
counter/control registers, while their organization COUNT = FFh :Countinuous transfer mode,
COUNT value not decremented
is shown besides. In the llowing,their
fo
function
FEh ≥ COUNT ≥ 1 :COUNT value decremented
will be discussed in detail.
after each transfer
COUNT = 0:CPU interrupt is generated
INC - Increment Control Field
This 2-bit field specifies whether the Source
Pointer or the Destination Pointer of the associated
PEC channel shall be incremented after a PEC
data transfer. Only one of the 2 pointers (either the
Source or the Destination Pointer) may be incremented, it is not possible to increment both pointers after a transfer. When the function ‘increment
no pointer’ is selected (INC = 00b), the transfer is
always performed between the same two memory
locations.
Note: When software tries to program the INC field
to 11b, this value is modified by hardware to 10b.
Table 7-3. PEC Channel Counter/Control Registers, Su
mmary
Control
Register
Physical
Address
8-Bit
Address
Control
Register
Physical
Address
8-Bit
Address
PECC0
FEC0h
60h
PECC4
FEC8h
64h
PECC1
FEC2h
61h
PECC5
FECAh
65h
PECC2
FEC4h
62h
PECC6
FECCh
66h
PECC3
FEC6h
63h
PECC7
FECEh
67h
9/24

7 - Interrupt And Trap Functions
This will cause the Source Pointer to be incre- data transfers through service channels 4 through
mented after a PEC data transfer.
7 can be processed.
BWT - Byte/Word Transfer Selection Bit
If the Transfer Counter field has been set to FFh,
This bit selects the data type to be transferred the continuous transfer mode is selected for the reupon a PEC service request. When the BWT bit is spective PEC channel. In this mode, the COUNT
set to ‘1’, the BYTE data type is selected for a PEC value is not decremented, which means that an unlimited number of transfers will be performed by
transfer.
this PEC channel. The operation of a PEC Service
When BWT is cleared, the selected data type for a Channelprogrammed forcontinuoustransfer can
PEC transfer is WORD. For byte transfers, the op- only be terminated either by
disablingPEC service,
tional increment value of the source or destinationor by reprogramming its PEC Channel
pointer is 1. For word transfers, the optional incre- Counter/Control register. For the different possibiliment value of the source or destination pointer is 2. ties of disabling interrupt sources, see section
7.2.3.1.
COUNT - PEC Transfer Counter Field
This 8-bit field is used to specify the number of data
transfers to be performed by the respective PEC 7.2.2.2 PEC SOURCE AND DESTINATION POINTERS
channel. Either an unlimited or a limited number of
transfers (0 through 254) can be programmed. The Eight pairs of word-wide pointers are associated
Transfer Counter field operates as an 8-bit down- with the 8 PEC Service Channels. Each pair is dicounter. Values from 0 through FFh can be speci- rectly assigned to one specific PEC channel. Each
fied in this field, where 0 and FFh have a special of these pairs of pointers consists of a Source
Pointer,which containsthe source address of the
meaning.
PEC data transfer, and a Destination Pointer,
If the COUNT value is between FEh and 2 at the which contains the respective destination address.
time the PEC service request is generated, the
value is decremented after each PEC data trans- These pointers share the top 16 word locations
fer. Also, the Interrupt Request flag of the source (byte addresses FDE0h through FDFFh) in the inwhich generated the PEC service request is ternal RAM. If no PEC service is required for a specific PEC channel, the locations of its pointers can
cleared.
be used for general data storage.
If the COUNT value equals 1 at the time the PEC
service request is generated, the value is decre- Note: If word data transfer is selected for a specific
mented to zero after the PEC data transfer, but the PEC channel (i.e. bit BWT=0), the respective
Interrupt Request flag of the source which gener- Source and Destination Pointers must both contain
ated the request remains set. This will cause an- a valid word address which points to an even byte
boundary. Otherwise the Illegal Word Access trap
other request from the associated source.
will be invoked when this channel is used (see secIf the COUNT value equals 0 at the time the re- tion 7.3.2.6).
quest is generated, no PEC data transfer will be
performed. Instead, a CPU interrupt request is In the following, a Source Pointer will be referred to
generated onthe same priority level (15 or 14) as as SRCPx, and a Destination Pointer will be rethe originalPEC request. The CPU branches to the ferred to as DSTPx, where x indicates the number
interrupt service routine of the source that gener- of the associated PEC ServiceChannel (x=0
ated the request. This interrupt service routine can through 7). Figure 7.4 shows the mapping of the
be used to reprogram the associated PEC service PEC Source and Destination Pointers into the internal RAM.
channel.
Note: This feature can be used to specifically gen- Note that for all PEC data transfers, the data page
erate CPU interrupt requests on the 2 highest pri- pointers DPP0 through DPP3 are NOT used. The
ority levels (level 15 or 14). For any source request addresses contained in the PEC source and destion priority level 15 or 14 whose COUNT field of the nation pointers are interpreted as direct 16-bit
associated PEC channel contains 0, a CPU inter- memory addresses in segment 0, so that data
rupt request with the vector of that source is gener- transfers can be performed between any two
ated. Note that no PEC data transfer operation can memory locations within the first four data pages
be performed while the CPU is executing a routine (pages 0 through 3).
on CPU priority level 15. While the CPU is execut- 7.2.3 Prioritization of Interrupt and PEC
ing a routine on CPU priority level 14, only PEC Service Requests
10/24

7 - Interrupt And Trap Functions
Figure 7-4. Mapping Of PEC Source And Destination Pointers into the Internal RAM
15
15
0
0
SFRs
DSTP7
FE00h
SRCP7
FDE0h
FDDEh
PEC
Source
and
Destination
Pointers
Internal
RAM
DSTP0
FA00h
SRCP0
External
Memory
F9FEh
PEC
Source Pointer
RAM Location
(Word Address)
PEC
Destination Pointer
RAM Location
(Word Address)
SRCP0
FDE0h
DSTP0
FDE2h
SRCP1
FDE4h
DSTP1
FDE6h
SRCP2
FDE8h
DSTP2
FDEAh
SRCP3
FDECh
DSTP3
FDEEh
SRCP4
FDF0h
DSTP4
FDF2h
SRCP5
FDF4h
DSTP5
FDF6h
SRCP6
FDF8h
DSTP6
FDFAh
SRCP7
FDFCh
DSTP7
FDFEh
11/24

7 - Interrupt And Trap Functions
Interrupt and PEC service requests from all ferent sources on the same priority level is not fixed
sources that areenabled compete for service in by the system but can be assigned via software.
the prioritization process. The prioritization se- In all cases, the source on the
highest priority level
quence is repeated every instruction cycle.
which also has the highest group priority wins the
current round of prioritization. Whether the request
of this source will be accepted by the CPU or not
7.2.3.1 ENABLING AND DISABLING OF INTERRUPT
depends on the current CPU priority. If the priority
SOURCES
of the requesting source is higher, the request is
Enablingand disabling of interrupt sources can be acknowledgedand the CPU passes control to the
performed in several ways:
source’s interrupt vector.
1) Each interrupt source can be
individuallyenThe interrupt system supports 16 different priority
abled or disabled by setting or clearing its In- levels. Only 15 of those levels are actually effective
terrupt Enable flag in the interrupt control priority levels because requests on level 0 are not
register that is associated with this source. capable of interrupting the CPU. Therefore, up to
However, as long as the global Interrupt En- 15 interrupt service routines on different priority
able control bit IEN in the PSW has not been levels can be nested. In the following section, a
set, all interrupt sources remain
globallydismethod will be described which allows the limitaabled and no interrupt requests will be ac- tion of nested interrupt levels to a number less than
knowledgedby the CPU.
15. This may be desirable for reasons of stack effi2) When the IEN bit in the PSW is set to ‘1’, all in- ciency.
terrupt sources that have been individually en- Normally, the 2 highest priority levels (level 15 and
abled become globally enabled. Interrupt 14) are used by PEC requests. Those levels can
requests which are generated by these also be used to process h
aigh priorityCPU intersources can then participate in the prioritiza- rupt if the COUNT field of the selected PEC chantion process. The requests will be acknow- nel contains 0 at the time this channel is invoked
ledged by the CPU according to their priority. ( see section 7.2.2.1).
3) By programming the ILVL field of an Interrupt
Control register to level 0, the associated
7.2.3.3 EXAMPLE FOR THE USE OF THE CPU PRIsource can never interrupt the CPU.
ORITY
4) Programming the CPU priority in the PSW to a
being
certain level prevents the CPU from being in- The priority level of the routine currently
terrupted by requests on the same or any serviced by the CPU is indicated in the CPU Priorlower level. With this method, all interrupts be- ity field (ILVL) of the PSW. Modifying the CPU Priadditional
low a certain level can be disabled with one in- ority field of the PSW by software adds
struction, e.g. the Bit F ield (BFLDH) flexibility to the interrupt system of the ST10x166.
For example, it provides the user with a means of
instruction.
‘reducing’ the implemented number of 16 priority
levels to any smaller integer number. This may be
desirable to prevent a group of several different
7.2.3.2 PRIORITY LEVEL STRUCTURE
In the ST10x166’s interrupt system, the priority of a tasks with similar importance from interrupting
request for interrupt or PEC service is completely each other. It also reduces the stack depth. For up
programmable. All enabled source requests must to 4 tasks per group, this can simply be done by asbe programmed to different priorities, which meanssigning the associated interrupt sources to the
that sources which are programmed to the same same priority level (in their ILVL field), but to differpriority level must be programmed to different ent group priorities (in their GLVL field).
group priorities. Otherwise, undetermined results
may occur for the interrupt vector. Using the group
priorities 0 through 3, up to 4 sources can be proTo prevent a group of more than 4 tasks with simigrammed to the same priority level.
lar importance from interrupting each other, the
The advantage of this priority scheme is that the or- first action within an interrupt service routine of
der for servicing of simultaneous requests from dif-each of these tasks could be to set the CPU Priority
12/24

7 - Interrupt And Trap Functions
field to the priority level (ILVL) of the source with For example, an application may have 24 interrupt
the highest priority within this group. In this way, in-sources, where these sources must be
organized
terrupt or PEC service requests of higher priority in 3 priority classes with 8, 10, and 6 sources per
other than in this group are still accepted.
class. In the priority scheme of the ST10x166, the
c
as
All interrupt requests of lower or equal priority be-24 sources could be organized andonfigured
follows:
come pending. Thus, the interrupt system operates as if all tasks of the group were on the same In this example, the 3 user-defined priority levels
priority level.
are called ‘classes’. Each of the three classes A
throughC includesinterrupt sources on 2 or 3 priTable 7-4. Example of 24-Interrupt Organization In 3 Classes
ILVL
GLVL
3
2
Organization
1
0
Fh
PEC Service, 8 Channels
Eh
Dh
Ch
x
x
x
x
Bh
x
x
x
x
8
x
x
x
x
7
x
x
x
x
6
x
x
5
x
x
x
x
4
x
x
Class A, 8 Interrupts
Ah
9
Class B, 10 Interrupts
Class C, 6 Interrupts
3
2
1
0
No Service
ority levels of the interrupt system. The 2 highest Using this technique, interrupts generated by the
priority levels of the interrupt system are used by lowest class (i.e. C) can be interrupted by a request
the PEC service functions. Priority level 0 does not from higher classes (i.e. B or A). However, an interprovide interrupt service. With the organization rupt service routine of a source that
belongsto the
shown in table 7.4, any acknowledged interrupt highest class (i.e. A) can not be interrupted by refrom the sources within a class (e.g. A) must set quests of the same or lower classes.
the CPU Priority field of the PSW to the highest pri- 7.2.4 Interrupt Procedure
ority level c
ontained inits class (e.g. 8 for class B)
Once an interrupt has been selected for servicing,
at thebeginningof its interrupt service routine.
the state of the task currently being executed by
13/24

7 - Interrupt And Trap Functions
the CPU is saved on the system stack. To ensure
correct return to the location where the task had to ‘1’. The Interrupt Request Flag of the source that
been interrupted, the information stored on the caused the interrupt is cleared. The CPU then
stack also depends on whether segmentation is passes control to the source’s interrupt vector. The
currentlyenabled, as indicated by the SGTDIS bit pushed IP contains the address of the instruction
in the SYSCON register.
to which execution will return after the interrupt
service routine is completed.
Upon execution of the RETI instruction (Return
7.2.4.1 INTERRUPT PROCEDURE WITH SEGMENTATION DISABLED
from Interrupt), the information that was pushed on
If segmentation isdisabled,the contents of the the stack ispoppedin reverse order. In this way,
PSW and the contents of the IP are pushed on the the status of the interrupted routine is restored.
system stack. The interrupt source’s priority level isFigure 7.5 shows how the system stack is affected
nowledgedwhile segmenthen copied into the CPU Priority field of the PSW. when an interrupt is ack
If a multiply or divide operation was in progress tation is disabled.
when the interrupt was ack
nowledged,the MULIP
bit in the PSW of the interrupt service routine is set 7.2.4.2 INTERRUPT PROCEDURE WITH SEGMENTATION ENABLED
Figure 7-5. Interrupt Procedure With Segmentation Disabled
High
Addresses
High
Addresses
SP →
__
PSW
SP
__
→
__
Low
Addresses
IP
}
State of interrupted task
saved on system stack
__
Low
Addresses
a) System Stack before
Interrupt Entry
b) System Stack after
Interrupt Entry
The procedure that will be performed by the terrupt Request flag of the source that caused the
ST10x166’s interrupt system when segmentation interrupt is cleared. If a multiply or divide
operation
is enabled isindependent of the code segment that was in progress when the interrupt was acknowthe CPU is currently executing from.
ledged, the MULIP bit in the PSW of the interrupt
service routine is set to ‘1’. No data page pointer is
If segmentation is used
when an interr
upt request
is acknowledged, the Code Segment Pointer affected.
(CSP) must also be pushed on the system stack to Upon execution of the RETI instruction (Return
ensure correctreturn to the previous segment after from Interrupt), the information that was pushed on
completion of the interrupt service routine. The the stack ispopped inreverse order to restore the
contents of the PSW are pushed first, then the con- previous status. Figure 7 .6 shows how the system
tents of the CSP and IP are pushed on the system stack is affected by an interrupt that is acknowstack. The CSP for the interrupt service routine is ledged when segmentation enabled.
is
set to segment zero. As with segmentation dis- 7.2.4.3 CONTEXT SWITCHING FOR INTERRUPT
abled, the interrupt source’s priority level is copiedSERVICE ROUTINES
into the CPU Priority field of the PSW, and the In14/24

7 - Interrupt And Trap Functions
Figure 7-6. Interrupt Procedure With Segmentation Enabled
High
Addresses
High
Addresses
SP →
__
PSW
SP →
__
__
Low
Addresses
CSP
IP


State of interrupted task
saved on system stack
Low
Addresses
a) System Stack before
Interrupt Entry
b) System Stack after
Interrupt Entry
Context switching in conjunction with processingAs an alternative to software oriented interrupt
an interrupt service routine allows ablishinga
est
processing, the PEC provides a way to minimize
new context within the interrupt service routine.interrupt latency and software overhead in cases
Thus, a completely new set of General Purpose where only a single data transfer operation is reRegisters (GPRs) can be provided for the interrupt quired to service aperipheraldevice. As all the
service routine, without the need of explicitly sav- ST10x166’s peripheral functions are
ontrolled
c
by
ing and restoring registers.
Special Function Registers (SFRs), it is sufficient
Context switching can be performed by executing for many applications to simply transfer data to or
the Switch Context instruction (SCXT) within the from the Special Function Registers and a data
interrupt service routine before any GPR is ac- memory location to handle service requests. Excessed. For example, the instruction SCXT CP, amples would be storing of results from the A/D
#New Bank is used to push the previous value of converter, or data from a serial channel. With the
the Context Pointer (CP) on the system stack and ST10x166’s PEC, data transfers between two
set the CP to the value #New Bank which is speci- memory locations in segment 0 (data page 0
fied as an immediate operand in the SCXT instruc- through 3) are possible.
tion. Note that GPRs in the new register bank The PEC data transfer itself does not affect the IP
should not be accessed by the instruction immedi-or the flags in the PSW. Therefore, no program
atelyfollowingthe SCXT instruction (see also sec- status information needs to be saved when the
tion 5.1.4).
PEC performs a data transfer. This improves the
oughput and speeds up the servBefore executing the RETI instruction at the end of overall system thr
an interrupt service routine, the previous Context icing ofperipheralrequests.
Pointer must bepoppedfrom the system stack to The priority level structure of the 10x166’sinterST
ensure correct return to the previous context.
rupt system has been
designedsuch that requests
for PEC service have priority over requests for
7.2.5 Interrupt Processing via the Peripheral
CPU interrupt service. Exceptions to this are when
Event Controller PEC
the CPU is executing a routine on CPU priority
15/24

7 - Interrupt And Trap Functions
level 15 or 14. While the CPU is executing a routine the associated interrupt service routine can be
on CPU priority level 14, only PEC data transfers used to reprogram the affected PEC channel. A
through service channels 4 through 7 can be proc- functional diagram of the basic PEC service proceessed. While the CPU is executing a routine on dure is shown in figure below.
CPU priority level 15, no PEC data transfers can be Note: All sources which are requesting PEC servprocessed.
ice should be programmed to the same PEC servWhen an interrupt request that has been pro- ice channel ONLY if it is ensured that they do not
grammed for PEC service is selected for servicing generate simultaneous requests while the COUNT
by the prioritization circuit, the PEC performs one field of the respectivehannel
c
contains 1. In the
data transfer operation. The data type (byte or case of simult
aneous requests where the COUNT
word) for this transfer is determined by bit BWT in field contains a value greater than 1 at the time the
the PEC channel control register PECCy of the re- PEC channel is invoked, only one PEC data transspective PEC channel. The source and the desti- fer will be performed for all of the simultaneous renation of this data transfer are pointed to by sourcequests. When the COUNT field contains 1 and
pointer SRCPy and destination pointer DSTPy.
simultaneous PEC requests for this channel are
After completion of the transfer operation, one of generated, one PEC data transfer is performed,
the 2 pointers can optionally be incremented and and an interrupt to an undetermined vector adthe channel’s transfer counter COUNT can be de- dress may occur.
cremented. When the transfer counter reaches 0, 7.2.6 Interrupt and PEC Response Times
a normal CPU interrupt request is generated and
Figure 7-7. PEC Service Procedure
16/24

7 - Interrupt And Trap Functions
Interrupt response time is defined as the time required from the moment an interrupt request flag ofon the instructions N through N-3 which are in the
an enabled interrupt source is set until fetching ofpipelineat the time the request flag is set, and on
the first instruction I1 at the interrupt vector locationthe followingtwo instructions N+1 and N+2. This is
can begin. In general, the interrupt response time explainedby thepipelinediagram in figure 7.8.
in the ST10x166 is 3 instruction cycles.depends
It
Figure 7-8. Pipeline Diagram For Interrupt Response
FETCH
N
N +1
N +2
I1
DECODE
N-1
N
TRAP (1)
TRAP (2)
EXECUTE
N-2
N -1
N
TRAP
WRITEBACK
N-3
N -2
N -1
N
1
IR-Flag
0
Interrupt Response Time
Whenever thepipelineis advanced and a new in- flag is set during the first state of an instruction cystruction cycle is started, all sources whose inter-cle, the minimum interrupt response time under
rupt request flags have been set during the these conditions is 6 state times (300ns at 40MHz).
previous cycle compete for service in a round of In general, all delays with respect to the standard
prioritization. In the next cycle, a TRAP is per- instruction execution time which may occur during
formed to the vector location of the
winningsource,
execution of instructions in the pipeline may result
and the source’s interrupt request flag is reset to in a longer interrupt response time. W
hen internal
‘0’. Fetching of the instruction I1 at the vector loca- hold conditions between instruction pairs N-2/N-1
tion is started in the
followingcycle. All instructions or N-1/N occur, or instruction N explicitly writes to
that are in the pipeline at the time the interrupt re- the PSW, the minimum interrupt response time
quest flag is set will be completed before the inter- may be extended by 1 state time for each of these
rupt service routine, while the
following ins
truction
conditions. When instruction N reads operand
an
N+1 will be executed after return from the interrupt from the internal ROM, or when N is a call, return,
service routine. As can be seen from figure 7.8, trap, or MOV Rn, [Rm+ #data16] instruction, the
the TRAP instruction requires two cycles to push minimum interrupt response time may addit
ionally
the PSW generated by instruction N and the IP and be extended by 2 state times during internal ROM
(in segmentation mode) the CSP of instruction program execution. In case instruction N reads the
N+1.
PSW and instruction N-1 has an effect on the conThe minimum interrupt response time is 5 states dition flags, the interrupt response time may addi(250ns at 40MHz). Thisappliesto program execu- tionally be extended by 2 state times. The worst
tion from the internal ROM when no external oper- case interrupt response time during internal ROM
and read requests are performed, and when the program execution is 12 state times (500 ns at
interrupt request flag is set during the last state of40MHz). See paragraph 5 for more details on inan instruction cycle. When the interrupt request struction timing.
17/24

7 - Interrupt And Trap Functions
The absolute worst case interrupt response time location in the internal ROM, the interrupt response
will occur when instructions N through N+2 are time is 1 word bus access plus 4 states.
executed out of an external memory, instructions N After an interrupt service routine has been termiand N+1 require ext
ernal operand read ac
cesses,
nated through execution of the RETI instruction,
instructions N-3hrough
t
N write bac
k external opand if further interrupts are pending, the next intererands, and the interrupt vector location is also in rupt service routine will not be entered until at least
the external memory. In this case, the interrupt re- two instruction cycles have been executed in the
sponse time is the time to perform 9 word bus ac- program section returned to. In most cases, two incesses, because instruction I1 can not be fetched structions will be executed during this time. Only
over the external bus until all write, fetch and read one instruction will typically be executed if the first
requests of preceding instructions in the
pipeline
instruction ollowing
f
the RETI instruction is a
are terminated. Under the sameconditions
, but
branch instruction (without cache hit), or if it reads
with the interrupt vector location in the internalan operand in the internal ROM, or if it is executed
ROM, the interrupt response time is 7 word bus ac- out of the internal RAM.
cesses plus 2 states, because fetching of I1 from
the internal ROM can start earlier. Note that these Similar to the interrupt response time, the reworst case situations are rather untypical and oc- sponse time for a PEC data transfer request can
cur only when instructions N and N-1 are indirect be defined as the time required from the moment
MOV instructions between two external memory an interrupt request flag has been set until the PEC
locations. When instructions N through N+2 are data transfer is started. In general, the PEC reexecuted out of an external memory, and the inter- sponse time in the ST10x166 is 2 instruction cytructions N-3 through N
rupt vector location is also in external memory, butcles. It depends on the ins
which
are
in
the
pipelineat
the moment the request
all operands for instructions N-3 through N are in
internal memory, then the interrupt response time flag is set, and on thefollowinginstruction N+1.
is the time to perform 3 word bus accesses. Under This is explainedby thepipelinediagram in figure
the same conditions
, but with the interrupt vector 7.9.
Figure 7-9. Pipeline Diagram For PEC Response Time
FETCH
N
N +1
N +2
N +2
DECODE
N-1
N
PEC
N +1
EXECUTE
N-2
N -1
N
PEC
WRITEBACK
N-3
N -2
N -1
N
1
IR-Flag
0
PEC Response Time
PEC is equivalent
to MOV/B [DSTPx],[SRCPx]
or MOV/B [DSTPx+],[SRCPx]
or MOV/B [DSTPx],[SRCPx+]
18/24

x=(0 . . 7)
7 - Interrupt And Trap Functions
Once per instruction cycle, all
enabled interrupt
PEC response time during internal ROM program
sources whose interrupt request flags have been execution is 9 state times (350ns at 40MHz).
set during the previous cycle compete for service The absolute worst case PEC response time will
in a round of prioritization. In the next cycle, the occur when instructions N and N+1 are executed
PEC data transfer is started when the
winning
out of an external memory and both require extersource was programmed for PEC service, and the nal operand read accesses, and instructions N-3
source’s interrupt request flag is reset to ‘0’. Note through N-1 write back external operands. In this
that when instruction N reads any of the PEC con- case, the PEC response time is the time to perform
trol registers PECC0 through PECC7 while a PEC 7 word bus accesses. Note that this worst case
request wins the current round of prioritization, thissituation is rather untypical and occurs only when
round is repeated and the PEC data transfer is instructions N and N-1 are indirect MOV instrucstarted one cycle later.
tions between two external memory locations.
The minimum PEC response time is 3 states When instructions N and N+1 are executed out of
(150ns at 40MHz). Thisappliesto program execu- an external memory, but all operands for instruction from the internal ROM when no external oper- tions N-3 through N-1 are in internal memory, then
and read requests are performed, and when the the PEC response time is the time to perform 1
interrupt request flag is set during the last state ofword bus access plus 2 state times.
an instruction cycle. When the request flag was set
during the first state of an instruction cycle, the Once a request for PEC service has been acknowledged by the CPU, the execution of the next inPEC response time is 4 state times.
struction is delayed by 2 state times plus the
When internal hold onditions
c
between instruction
additionaltime it might take to fetch the source oppairs N-2/N-1 or N-1/N occur, the minimum PEC erand from internal ROM or external memory and
response time may be extended by 1 state time for to write the destination operand over the external
each hold condition. When instruction N reads an bus in an external program environment.
operand from the internal ROM, or when N is a call,
return, trap, or MOV Rn, [Rm+#data16] instruction,
the minimum PEC response time may addit
ionally
7.2.7 External Interrupts
be extended by 2 state times during internal ROM Nineteen of the ST10x166’sport pins may be used
program execution. In case instruction N reads the
as universal external interrupt input pins if their alPSW and instruction N-1 has an effect on the conternate function is notequired
r
inconjunction with
dition flags, the PEC response time may additionan on-chip peripheral. These pins are listed in table
ally be extended by 2 state times. The worst case
below .
Table 7-5. Port Pins Configurable As External Interrupt Input Pins
Port Pin
Alternate Symbol
Alternate Function
P2.0
CC0IO
:
:
P2.15
CC15IO
CAPCOM Register 15 Capture Input/Compare Output
P3.2
CAPIN
CAPREL Register Capture Input
P3.5
T4IN
Timer 4 Count/Gate/Reload/Capture Input
P3.7
T2IN
Timer 2 Count/Gate/Reload/Capture Input
CAPCOM Register 0 Capture Input/Compare Output
:
:
19/24

7 - Interrupt And Trap Functions
For each of these pins, either a positive, a nega- grammed to X01b, interrupt request flags T2IR or
tive, or both a positive and a negative external tran- T4IR in registers T2IC or T4IC will be set on a posisition can be selected to cause an interrupt or PEC tive external transition at pins T2IN/P3.7 or
service request. The edge selection is performed T4IN/P3.5, respectively. When T2I or T4I are proin the control register of the
peripheraldevice asgrammed to X10b, then a negative external transisociated with the respective port pin. The periph- tion will set the corres
pondingrequest flag. When
eral must be programmed to a specific operating T2I or T4I are programmed to X11b, both a positive
mode to allow generation of an interrupt by the ex- and a negative transition will set the request flag. In
ternal signal. The priority of the interrupt request isall three cases, the contents of the core timer T3
determined by the interrupt control register of thewill be captured into the
auxiliarytimer registers T2
respective peripheral interrupt source, and the in- or T4 based on the transition at pins T2IN or T4IN.
terrupt vector of this source will be used in case an When the interrupt enable bits T2IE or T4IE are
interrupt is ack
nowledged.
set, a PEC request or an interrupt request for vecIn order to use any of the pins listed in Table 7.5 as tor T2INT or T4INT will be generated. For further
external interrupt inputs, its direction control bitdetails on the GPT1 block, see section 8.2.
DPx.y in the corr
espondingport direction control Pin CAPIN/P3.2 differs slightly from the other pins
register DPx must be ‘0’.
described before in that it can be used as external
When port pins CCxIO/P2.x (x=0 through 15) are interrupt input pin without affecting peripheral functo be used as external interrupt input pins, bit fieldtions. When the capture mode enable bit T5SC in
CCMODx in the control register of the correspond- register T5CON is set to ‘0’, signal transitions on
ing capture/compare register CCx must be config- pin CAPIN/P3.2 will only set the interrupt request
ured for capture mode. When CCMODx is flag CRIR in register CRIC, and the capture funcprogrammed to 001b, the interrupt request flag tion of register CAPREL is not activated. This
CCxIR in register CCxIC will be set on a positive means that register CAPREL can still be used as
external transition at pin CCxIO/P2.x. When reload register for GPT2 timer T5 while pin
CCMODx is programmed to 010b, a negative ex- CAPIN/P3.2 is used as external interrupt input.
ternal transition will set the interrupt request flag.Through bit field CI in register T5CON, the effecWhen CCMODx=011b, both a positive and a nega- tive transition of the external interrupt input signal
tive transition will set the request flag. In all three can be selected. When CI is programmed to 01b, a
cases, the contents of the allocated CAPCOM positive external transition will set the interrupt retimer T0 or T1 will be latched into capture register quest flag. CI=10b selects a negative transition to
CCx, independent whether the timer is running or set the interrupt request flag, and with CI=11b,
not. When the interrupt enable bit CCxIE is set, a both a positive and a negative transition will set the
PEC request or an interrupt request for vector request flag. When the interrupt enable bit CRIE is
CCxINT will be generated. For further details on set, an interrupt request for vector CRINT or a PEC
the CAPCOM unit, see section 8.1.
request will be generated. See section 8.2.2 for furPins T2IN/P3.7 or T4IN/P3.5 can be used as exter- ther details on the GPT2 block.
nal interruptinput pins whenthe associated auxil- The non-maskable interrupt input pin
NMI provides
iary timer T2 or T4 in block GPT1 is configured for another possibility to obtain CPU reaction on an
capture mode. This mode is selected by program- external input signal. The
NMI pin is a dedicated inming the mode control fields T2M or T4M in control put pin which causes a hardware trap when a
registers T2CON or T4CON to 101b. The active negative transition is detected on this pin. The
NMI
edge of the external input signal is determined by trap function is discussed in detail
in the following
bit fields T2I or T4I. When these fields are pro- section.
20/24

7 - Interrupt And Trap Functions
7.3 TRAP FUNCTIONS
is selected for servicing according to table 7.2 in
The ST10x166 provides two different kinds of trap- section 7.1.
ping mechanisms. These are software traps and Whenever a trap occurs, the PSW, the IP, and in
hardware traps. Trap functions offer the possibilitysegmentation mode also the CSP, are pushed on
to bypass the interrupt system’s prioritization proc-the system stack. The CPU priority field of the
ess in cases where immediate system reaction is PSW of the trap service routine is set to the highest
disabling
required. Trap functions are not maskable and al- possible priority level (i.e., level 15), thus
ways have priority over interrupt requests on any all interrupts. The CSP is set to code segment zero
priority level.
if segmentation is enabled. The trap service routine must be terminated with the RETI instruction.
The eight hardware trap functions of the10x166
ST
7.3.1 Software Traps
are divided into two classes, class A and B. The
The TRAP instruction is used to cause a software traps of class A are the external Non-Maskable Incall to an interrupt service routine. Associated withterrupt (NMI), the Stack Overflow, and the Stack
the trap instruction is a trap number that can be Underflow trap. All of these traps have the same
specified in the operand field of the instruction.trap priority, but each of them has a separate vecThis trap number determines which vector locationtor address.
in the memory space from 0h through 1FCh will be
The traps of class B are the
following:
branched to (see also table 7.2 in section 7.1.).
Executing a TRAP instruction causes a similar ef- - Undefined Opcode Trap
fect as if an interrupt at the same vector had oc- - Protection Fault Trap
cured. The IP and PSW, and in segmentation
Illegal Word Operand Access Trap
mode also the CSP, are pushed on the internal system stack and a jump is taken to the specified - Illegal Instruction Access Trap
vector location. When segmentation enabled
is
- Illegal External Bus Access Trap
and a trap is executed, the CSP for the trap service These trap functions all share the same trap priorroutine is set to code segment 0. However, the ity and vector address.
CPU Priority field of the PSW is not modified and
the trap service routine is executed on the priorityIn order to allow a trap service routine to identify
level from which it was invoked. Therefore, the the kind of trap which caused the exception, a bitservice routine entered by the TRAP instruction addressable Special Function Register, the Trap
iguration
can be interrupted by other traps or higher priorityFlag Register (TFR), is provided. The conf
interrupts. No Interrupt Request flags are affected of this register is shown next page.
by the TRAP instruction. The interrupt service rou- For each trap function, a separate request flag is
tine called by a TRAP instruction must be termi- implemented. When a hardware trap occurs, the
nated with a RETI (return from interrupt) instruction correspondingrequest flag in the TFR register is
to ensure correct return.
set to ‘1’. It must be reset by software in the trap
service routine, otherwise a new trap will be requested after exiting the service routine. Setting a
7.3.2 Hardware Traps
trap request flag by software causes the same efHardware traps are used to identify faults or spe- fects as if it had been set by hardware.
cific system states at runtime which cannot be After the reset functions which have highest sysidentified at assembly time. Eight different hard- tem priority (trap priority III), the traps of class A
ware trap functions are supported by the have the second highes
t priority (trap priority II). A
ST10x166. When a hardware trap condition has class A trap can interrupt a class B trap, but not anbeen detected, the CPU branches to the trap vec- other class A trap. If more than one of the class A
tor location for the respective trap condition. De- traps occurs at a time, an inter
nal hardwar
e prioripendingon the trap condition, the instruction which tization takes place. The NMI trap has the highest,
caused the trap is either completed or
ancelled
c
the stack underflow trap the lowest priority.
(i.e., it has no effect on the system state) before the
The traps of class B all have the same trap priority
trap handlingroutine is entered.
(trap priority I), which is lower than the priority of
Hardware traps are non-maskable and always class A traps. Thus, class B traps can never interhave priority over every other CPU activity. If sev- rupt class A traps; but
pendingclass B traps will be
eral hardware trap conditions are detected within executed after all class A traps are finished. In the
the same instruction cycle, the highest priority trapcase of simultaneously occurring class B traps, the
21/24

7 - Interrupt And Trap Functions
correspondingflags in the TFR register are set and A class A trap occurring during the execution of a
the trap service routine is entered. Since all class B class B trap service routine will be serviced immetraps have the same vector, the priority of service diately. During the execution of a class A trap servof simultaneous
ly occurring class B traps is deter- ice routine, however, any class B trap occurring will
mined by software in the trap service routine.
not be serviced until the class A trap service routine has finished. Thus, in this case, the occurrence of the class B trap is stored in the TFR
register, but the IP value of the instruction which
TFR (FFACh / D6h)
caused this trap is lost.
Trap Flag Register TFR
In the case where e.g.an UndefinedOpcode trap
Reset Value :0000h
occurs simultaneously with an NMI trap, both the
15
14
13
12
11
10
9
8
NMI and the UNDOPC flag is set, the IP of the instruction with the undefined opcode is pushed onto
NMI
STKOF STKUF
R
the system stack, but the NMI trap is executed. Af7
6
5
4
3
2
1
0
ter return from the NMI service routine, the IP is
popped from the stack and immediately
pushed
UNDOPC
R
PRTFLT ILLOPA ILLINA ILLBUS
again be cause of the pending UNDOPC trap.
b15 = NMI: External non-Maskable Interrupt Trap
request flag.
Set when a negativ
e transition is detected at the 7.3.2.1 EXTERNAL NMI TRAP
NMI pin. Must be reset by software.
Whenever a high to low transition on the dedicated
b14 = STKOF: Stack Overflow Trap request flag. externalNMI pin (Non-Maskable Interrupt) is deSet when the stack pointer value is less than the tected, the NMI flag in register TFR is set and the
contents of the Stack Overflow (STKOV) register. CPU will enter the External NMI trap routine. The
IP value pushed on the system stack is the address
Must be reset by software.
followingthe one after which norb13 = STKUF: Stack Underflow Trap request flag. of the instruction
mal
processing
was interrupted by the NMI trap.
Set when the stack pointer value is greater than
the contents of the Stack Underflow (STKUV)
register. Must be reset by software.
7.3.2.2 STACK OVERFLOW TRAP
b12 to b8 and b6 to b4 =R: Reserved.
Whenever the Stack Pointer value is decremented
b7 = UNDOPC: Undefined Opcode Trap request to a value which is less than the value in the Stack
Overflow register STKOV, the STKOF flag is set in
flag.
Set when the opcode of the instruction currently the TFR register and the Stack Overflow trap is enin decode is not a valid ST10x166 opcode. Must tered. Which IP value willbe pushed onto the system stack depends on which operation caused the
be reset by software.
decrement of the SP. When an implicit decrement
b3 = PRTFLT: Protection Fault Trap request flag.
of the SP is made through a Push or Call instrucSet when anillegalformat of a protected instruction, or upon interrupt or trap entry, the IP value
tion is detected. Must be reset by software.
pushed is the address of the
followinginstruction.
b2 = ILLOPA: Illegal Word Operand Access Trap When the SP is decremented by a Subtract inrequest flag.
struction, the IP value pushed represents the adSet when a word operand read or write access is dress of the instruction after the instruction
made to an odd byte address. Must be reset by followingthe Subtract instruction.
software.
For recovery from stack overflow it must be enb1 = ILLINA: Illegal Instruction Access Trap re- sured that there is enough excess space on the
quest flag.
stack for twice saving the current system state
Set when a branch is made to an odd byte ad- (PSW, IP, in segmented mode also: CSP). Otherdress. Must be reset by software.
wise, a system reset should be generated. See
b0 =ILLBUS: Illegal External Bus Access Trap re- chapter 13 for more details on stack usage.
quest flag.
Set when an external access is requested and no
external bus is configured. Must be reset by software.
22/24

7 - Interrupt And Trap Functions
not repeated twice in the second word of the in7.3.2.3 STACK UNDERFLOW TRAP
f
opcode is not
Whenever the Stack Pointer is incremented to a struction and the byteollowingthe
value which is greater than the value in the Stack the complement of the opcode, the PRTFLT flag in
Underflow register STKUN, the STKUF flag is set the TFR register is set and the Protection Fault
include
in the TFR register and the Stack Underflow trap is Trap is entered. The protected instructions
DISWDT,
EINIT,
IDLE,
PWRDN,
SRST,
and
entered. Again, which IP value will be pushed onto
SRVWDT.
The
IP
value
pushed
onto
the
system
the system stack depends on which operation
caused the increment of the SP. When an implicit stack for the protection fault trap is the address of
increment of the SP is made through a Pop or Re- the instruction that caused the trap.
turn instruction, the IP value pushed is the address
of the followinginstruction. When the SP is incre- 7.3.2.6 ILLEGAL WORD OPERAND ACCESS TRAP
mented by an Add instruction, the IP value
pushed
represents the address of the instruction after the Whenevera word operandread or write access is
instructionollowing
f
the Add instruction. See chap- made to an odd byte address, the ILLOPA flag is
set and the Illegal Word Operand Access trap is
ter 13 for more details on stack usage.
entered. The IP value pushed onto the system
stack is the address of the instruction
followingthe
one which caused the trap.
7.3.2.4 UNDEFINED OPCODE TRAP
Whenever the opcode of an instruction currently
decoded by the CPU is not the opcode of a valid in- 7.3.2.7 ILLEGAL INSTRUCTION ACCESS TRAP
struction in the ST10x166’s instruction set, the UNDOPC flag is set in the TFR register and the CPU Whenever a branch is made to an odd byte adenters the Undefined Opcode trap. The IP value dress, the ILLINA flag is set in the TFR register and
pushed onto the system stack is the address of the the Illegal Instruction Access trap is entered. The
illegal
instruction that caused the trap. This can be used IP value pushed onto the system stack is the
to emulate unimplemented instructions. The trap odd target address of the branch instruction.
service routine can examine the faulting instruction
to decode operands for
unimplement
ed opcodes
7.3.2.8 ILLEGAL EXTERNAL BUS ACCESS TRAP
based on the stacked IP. In order to resume processing, the stacked IP value must be incremented Whenever the CPU requests an external instrucby the size of theundefinedinstruction which is de- tion or data fetch, and no external bus configuratermined by the user, before a RETI instruction is tion has been specified in the BTYP field of the
SYSCON register, the ILLBUS flag in the TFR regexecuted.
ister is set and the Illegal Bus Access trap is en7.3.2.5 PROTECTION FAULT TRAP
tered. The IP value pushed onto the system stack
Whenever one of the special protected instructions is the address of the instruction
followingthe one
is executed where the opcode of that instruction iswhich caused the trap.
23/24

7 - Interrupt And Trap Functions
NOTES :
24/24


CHAPTER 8
PERIPHERALS
8. PERIPHERALS
This chapter provides a description of the function-Peripheral Timing
ality and programming of the peripherals incorpo-Internal operation of CPU and
peripheralsis based
rated in the ST10x166. Each of the
peripheralunits
on the oscillator frequencyOSC
(f ) divided by 2. The
is discussed in a separate section: the CAPCOM resulting frequency is referred to as ‘system clock’.
unit in section 8.1, the General Purpose Timers The basic time unit for internal operation of a chip
(GPT) in section 8.2, the A/D Converter in section is commonly called ‘state time’. For the ST10x166,
8.3, the Serial Channels in section 8.4, and the one state is defined as 2 periods of the oscillator
Watchdog Timer in section 8.5.
frequency. When a 40MHz oscillator is used, the
Peripheral Interfaces
internal system clock is 20MHz, and 1 state lasts
The peripheralsgenerallyhave two different types for 50ns.
of interfaces, an interface to the CPU and an inter- The clock which is gated to the
peripheralsis indeface to external hardware.
pendent from the CPU clock. During Idle mode, the
CPU clock is stopped while the
peripheralsconCommunication between CPU and
periphera ls is
tinue
their
operation.
eripheral
P
S
FRs may be acperformed through Special Function Registers
cessed
by
the
CPU
on
ceper
state.
When an SFR
(SFRs) and interrupts. The SFRs serve as conis
written
to
by
software
in
the
same
state where it
trol/status and data registers for the
peripherals
.
is
also
to
be
modified
by
the
peripher
a
l,
the softInterrupt requests are generated by the peripherals based on specific events (e.g. operation com- ware write operation has priority. Further details on
peripheraltiming are included in the specific secplete, error) which occur during their operation.
tions about each peripheral.
For interfacing with external hardware, specific
pins of ports P2, P3, or P5 are used when an input Programming Hints
or output function has been selected for a periph- (1) All SFRsreside in data page 3 ofthe memory
eral. During this time, the port pins are controlled
space. Whenever SFRs are to be accessed
by the peripheral (when used as outputs) or by the
through indirect or direct addressing with 16external hardware which controls the
peripheral
bit (mem) addresses, it must be
guaranteed
(when used as inputs). This isalled
c the ‘alternate
that data page 3 is selected by one of the data
(input or output) function’ of a port pin, in contrast page pointer registers DPP0 through DPP3.
to its function as a general purpose I/O pin.
This is not required for accessing SFRs via
Each port consists of a port data register and a dishort 8-bit (reg) addressing or via the Periphrection control register (except for port 5 which is
eral Event Controller (PEC), because in these
an input only port). The name Px (x=0..5) of a port
cases the data page pointers are not used.
data register isgenerallyused to refer to thewhole
(2) Byte write operations to word wide SFRs via
port Px. For reference to a port pin, the notation
indirect or direct 16-bit (mem) addressing or
Px.y (y=0..15) for the associated bit in the port data
byte transfers via the PEC force zeros in the
register is used as well as the symbol for the alternon-addressed byte. Byte write operations via
nate function of a port pin.
short 8-bit (reg) addressing can only access
This chapter about the
peripheralswill provide all
the low byte of an SFR and force zeros in the
information which is necessary to use the alternate
high byte. It is therefore recommended to use
functions of a port in conjunction with a peripheral.
the bit field instructions (BFLDL and BFLDH) to
A detailed description of the internal port structure
write to any number of bits in either byte of an
will be given in chapter 10 (Parallel Ports).
SFR without disturbing the
non-addressed
byte and the unselected bits.
1/64
8 - Peripherals
(3) Some of the bits which are contained in the T6 in block GPT2. T0 may also operate in counter
ST10x166’s SFRs are marked as ‘reserved’. mode allowingit to be clocked by an external
User software should never write ‘1’s to re- event.
served bits. These bits are currently not imple- Each capture/compare register may be promented and may be used in future ST
10x166
grammedindividuallyfor capture or compare funcfamily products to invoke new functions. In thistion, and each register may be allocated to either
case, the active state for these functions will be timer T0 or T1. Each capture/compare register has
‘1’, and the inactive state will be ‘0’. In the one pin of port 2 associated with it which serves as
ST10x166, the value read from reserved bits is an input pin for the capture function or as an output
0.
pin for the compare function.
The capture function causes the current timer con8.1 CAPTURE/COMPARE (CAPCOM) UNIT
tents to be latched into the capture/compare register based on an external event on its associated
The CAPCOM unit supports generation and con- port 2 pin. The compare function may cause an
trol of timing sequences on up to 16 channels with output signal transition on that port 2 pin whose asa minimum of software intervention. The CAPCOM sociated capture/compare register matches the
unit is typically used to handle high speed I/O tasks current timer contents. Specific interrupt requests
such as pulse and waveform generation, pulse are generated up on each capture/ compare event
width modulation, or recording of the time at whichor upon timer overflow. Figure 8.1 shows a block
specific events occur, and it also allows the imple- diagram of the CAPCOM unit.
mentation of up to 16 software timers. The maxi- Register Overview
mum resolution of the CAPCOM unit is 400ns (at
From the programmer’s point of view, the term
40MHz oscillator frequency).
‘CAPCOM unit’ refers to a set of SFRs which are
CAPCOM Block Diagram
associated with this
peripheral,includingthe port
The CAPCOM unit consists of two 16-bit timers (T0 pins which may be used for alternate input/output
and T1), each with its own reload register (T0REL functions. As can be seen from Figure 8.2, for each
and T1REL), and a bank of sixteen dual purpose pin (e.g. P3.0) within a port there is a direction con16-bit capture/compare registers (CC0hrough
t
trol bit (e.g. DP3.0) within the associated port diCC15).
rection control register (e.g. DP3). In this figure,
The input clock for T0 or T1 is programmable to those portions of port and direction registers which
several presc
aled valuesof the system clock, or it are not used by the CAPCOM unit for alternate
can be derived from an overflow/underflow of timer functions are not shaded.
2/64

8 - Peripherals
Figure 8-1. CAPCOM Unit Block Diagram
Reload Reg.T0REL
System Clock
Input
T0IN/P3.0
GPT2 Timer T6
Over/Underflo w
Control
CAPCOM Timer T0
Interrupt
Request
T0IR
CC0IR
CC0IO/P2.0
Port 2
Alternate
In put/Ou tput
Function s
Mode
Control
16
16-Bit
Ca pture/
Compare
Registers
CC0 - CC15
16
Cap ture/Comp are
Interrup t Request
Flags
CC15IR
CC15IO/P2.15
System Clock
GPT2 Timer T6
Over/Un derflow
Input
Control
CAPCOM Timer T1
T1IR
Interrupt
Request
Reload Reg.T1REL
V R00 1616
3/64

8 - Peripherals
Figure 8-2. SFRs and Port Pins Associated with the CADCON Unit
Ports & Direction Control
Alternate Functions
DP3
P3
Data
Registers
Control
Registers
TOREL
T0
T0IC
T01CON
T0IN/P3.0
T1REL
T1
DP2
P2
CC15IO ... CC0IO
P2.15 ... P2.0
Interrupt
Control
T1IC
CC15IC
CC0
CC15IC
CC1
CC15I
C
CC2
CC3
CC15
IC
CCM0
CC15IC
CC0IC
CC15IC
CC1IC
CC15IC
CC2I C
CC15IC
CC3IC
CC4
CC5
CC6
CCM1
CC15
CC4IC
IC
CC15IC
CC5IC
CC15IC
CC 6I C
CC15IC
CC7IC
CC15IC
CC8
CC15I
C
CC9
CC15
IC
CC10
CC15IC
CC11
CCM2
CC15
IC
CC8IC
CC15IC
CC 9IC
CC1 0IC
CC15IC
CC15IC
CC11 IC
CC12
CC15IC
CC15IC
CC13
CC1CC14
5IC
CCCC15
15I C
CCM3
CC12IC
CC 13I C
CC14IC
CC15IC
CC7
VR 001640
DP3
P3
DP2
P2
T0
T0REL
T1
T1REL
CC0 .. CC15
T01CON
CCM0 .. CCM3
T0IC
T1IC
CC0IC .. CC15IC
Port 3 Direction Control Register
Port 3 Data Register
Port 2 Direction Control Register
Port 2 Data Register
CAPCOM Timer 0 Register
CAPCOM Timer 0 Reload Register
CAPCOM Timer 1 Register
CAPCOM Timer 1 Reload Register
CAPCOM Registers 0 .. 15
CAPCOM Timer 0 and Timer 1 Control Register
CAPCOM Mode Control Registers 0 .. 3
CAPCOM Timer 0 Interrupt Control Register
CAPCOM Timer 1 Interrupt Control Register
CAPCOM Register 0 ..15 Interrupt Control Registers
4/64

8 - Peripherals
8.1.1 Timers T0 and T1
In all modes, both timer T0 and timer T1 are always
The primary use of the timers T0 and T1 is to pro- counting upward.The current timer values are acvide twoindependent time bases (400ns maximum cessible by the CPU in timer registers T0 and T1,
resolution for the capture/compare registers, but which are both non bit addressable SFRs. When
T0 or T1 are written by the CPU in the state immethey may also be usedindependent of the capdiately before a timer increment or reload is to be
ture/compare registers.
performed, the CPU write operation has priority,
The functions of the timers T0 and T1 are control- and the increment or reload disabledto
is
guaranled by the bit addressable 16-bit control register tee correct timer operation.
T01CON described below. T1 is controlled by the
upper byte, and T0 is controlled by the lower byte
of T01CON. T0R and T1R are the run flags of T0 8.1.1.1 TIMER MODE
and T1, respectively. They allow for
enablingand
disablingthe timers. Thefollowingdescription of Bits T0M and T1M in SFR T01CON select between
timer or counter mode for T0 or T1, respectively. In
the timer modes and operation always
appliesto
the enabledstate of the timers, i.e., when both T0R timer mode (T0M= ‘0’ or T1M= ‘0’), the input clock
for a timer is derived from the internal system clock
and T1R are set to ‘1’.
divided by a programmable prescaler. The different options for the prescaler are selected separately for T0 and T1 by the bit fields T0I and T1I.
The input requencies
f
fT0 and fT1 for T0 and T1 are
T01CON (FF50h / A8h)
determined as a function of the oscillator frequency
as follows, where <T0I> and <T1I> represent the
CAPCOM Timer 0 and 1 Control Register
contents of the bit fields T0I and T1I:
Reset Value :0000h
15
14
R
T1R
7
6
R
T0R
13
12
R
5
10
T1M
4
R
11
3
T0M
9
8
T1I
2
1
0
T0I
b15,b13,b12,b7,b5,b4 =R: Reserved.
b14 =T1R: Timer/Counter 1 Run Bit.
If set at ’1’ will enable the Timer/Counter 1
b11 =T1M: Timer/Counter 1 Mode Selection Bit.
If set at ’1’ will enable counter mode, otherwise
enable timer mode.
b10 to b8 =T1I: Timer/Counter 1 input Selection
Bits.
See table 8.1 and 8.2 for more information on the
input.
b6 = T0R: Timer/Counter 0 Run Bit.
If set at ’1’ will enable the Timer/Counter 0.
b3 = T0M: Timer/Counter 0 Mode Selection Bit.
If set at ’1’ will enable counter mode, otherwise
enable timer mode.
b2 to b0 = T0I: Timer/Counter 0 input Selection
Bits.
See table 8.1 and 8.2 for more information on the
input.
fT0 =
fOSC
16 × 2<T0I>
, fT1 =
fOSC
16 × 2<T1I>
When a timer overflows from FFFFh to 0000h, it is
reloaded with the value stored in its respective reload register T0REL or T1REL. The reload values
determine the periods T0
P and PT1 between two
consecutive overflows of T0 and T1 as follows:
16
<T0I>
PT0 = 16× ( 2 − <T0REL> ) × 2
fOSC
16
<T1I>
PT1 = 16× ( 2 − <T1REL> ) × 2
fOSC
The timer inputrequencies
f
, resolution, and periods which result from the selected prescaler option
in T0I or T1I when using a 40MHz oscillator are
listed in table 8.1. The numbers for the timer periods are based on a reload value of 0000h. Note
that some numbers may be rounded to 3 significant digits.
5/64

8 - Peripherals
Table 8-1. CAPCOM Timers T0 and T1 Input Frequencies, Resolution and Periods
Timer Input Selection T01/T1I
f osc = 40MHz
Prescaler for osc
f
000b
001b
010b
011b
100b
101b
16
32
64
128
256
512
Input Frequency
2.5MHz
1.25MHz
625kHz
Resolution
400ns
800ns
1.6
µs
Period
26ms
52.5ms
105ms
110b
1024
312.5kHz 156.25kHz 78.125kHz 39.06kHz
3.2µs
6.4µs
210ms
420ms
12.8µs
25.6µs
840ms
1.68s
111b
2048
19.53kHz
51.2µs
3.36s
After a timer has been started by setting its run flag for T1. This is the only option for T1, and it is se(T0R or T1R) to ‘1’, the first increment will occur lected by the c
ombinationT1I=X00b. When bit field
within the time interval which is defined by the se- T1I is programmed to other combinations, timer T1
lected timer resolution. All further increments occurstops.
exactly after the time defined by the timer resolu- When T0 is programmed to run in counter mode
tion. When both timers are to be incremented or re- (T0M= ‘1’), bit field T0I is used to select the count
loaded at the same time, T0 is always serviced one source and transition which should cause a count
state before T1.
trigger for T0. Table 8.2 shows the possible selections for the counter mode of timers T0 and T1.
8.1.1.2 COUNTER MODE
In order to use pin P3.0/T0IN as external count inCounter mode is selected for timer T0 or T1 by set- put pin for T0, P3.0 must be configured as input,
ting the appropriat
e mode selection bit (T0M or i.e., the correspondingdirection control bit DP3.0
T1M) in register T01CON to ‘1’. Both timers can in register DP3 must be set to ‘0’. If P3.0/T0IN is
operate in counter mode by counting the over- configured as output, timer T0 may be clocked by
flows/underflows of timer T6 in block GPT2 (see modifying port data register bit P3.0 through softsection 8.2.2 for details on GPT2). In addition, ware, e.g. for testing purposes.
timer T0 offers thecapabilit
y of being clocked by The maximum external input frequency to T0 in
external events. Either a positive, a negative, or counter mode is OSC
f /16 (1.25MHz at 40MHz
both a positive and a negative transition at pin fOSC). To ensure that a signal transition is properly
T0IN (alternate input function of port pin P3.0) can recognized, an external count input signal should
be held for at least 8 state times before hanges
it c
be selected to cause an increment of T0.
its
level
again.
The
incremented
count
value apWhen T1 is programmed to run in counter mode
(T1M= ‘1’), bit field T1I is used to enable the over- pears in SFR T0 within 8 state times after the sigflows/underflows of timer T6 as the count source nal transition at pin T0IN.
TABLE 8-2.Input Selection for T0 and T1 in Counter Mode
T0I/T1I
Counter T0 is incremented on
(2)
(1)
Counter T1 is incremented on
(0)
Overflow or Underflow of GPT2 Timer T6
X
0
0
Overflow or Underflow of GPT2 Timer T6
Positive External Transition at Pin T0IN
X
0
1
(Counter T1 stops)
Negative External Transition at Pin T0IN
X
1
0
(Counter T1 stops)
Positive and Negative Transition at T0IN
X
1
1
(Counter T1 stops)
6/64

8 - Peripherals
8.1.1.3 RELOAD
T0IC (FF9Ch / CEh)
A reloadof a timer with the 16-bit value stored in its CAPCOM Timer T0 Interrupt Control Registers
associated reload register is performed in timer T0IC
mode as well as in counter mode each time a timer
overflows from FFFFh to 0000h. The reload regis- Reset Value :0000h
7
6
5
4
3
2
1
0
ters T0REL and T1REL are not bit-addressable.
T0IR
T0IE
ILVL
GLVL
8.1.1.4 TIMER T0 AND T1 INTERRUPTS
b7 = T0IR: Timer 0 Interrupt Request Bit.
This flag can be used to generate an interrupt or
Upon timer overflow, the corres
pondingtimer interrupt request flag T0IR or T1IR for the respective trigger a PEC service request.
timer will be set. This flag can be used to generate b6 = T0IE: Timer 0 Interrupt Enable Bit.
an interrupt or trigger a PEC service request when If set at ’1’ will enable the timer 0 interrupt.
enabledby the interrupt enable bits T0IE or T1IE. b5 to b2 =ILVL: Interrupt Priority Level Bits.
Each of the two timers (T0 or T1) has its own bit- See chapter 7 for more details.
addressable interrupt control register (T0IC or
T1IC) and its own interrupt vector (T0INT or b1,b0 =GLVL: Interrupt Group Priority Bits.
See chapter 7 for more details.
T1INT). The organization of the interrupt control
registers T0IC and T1IC is described hereafter.
Refer to chapter 7 for more details on the interrupt
control registers.
T1IC (FF9Eh / CFh)
CAPCOM Timer T1 Interrupt Control Registers
T1IC
Reset Value :0000h
7
6
T1IR
T1IE
5
4
3
ILVL
2
1
0
GLVL
b7 = T1IR: Timer 1 Interrupt Request Bit.
This flag can be used to generate an interrupt or
trigger a PEC service request.
b6 = T1IE: Timer 1 Interrupt Enable Bit.
If set at ’1’ will enable the timer 1 interrupt.
b5 to b2 =ILVL: Interrupt Priority Level Bits.
See chapter 7 for more details.
b1,b0 =GLVL: Interrupt Group Priority Bits.
See chapter 7 for more details.
7/64

8 - Peripherals
8.1.1.5 BLOCK DIAGRAM
The followingblock diagrams illustrate the selec- while Figure 8.4 shows a block diagram of timer
tion of theavailablefunctions for timer T0 and timer T1.
T1. Figure 8.3 shows a block diagram of timer T0,
Figure 8-3. CAPCOM Timer T0 Block Diagram
Figure 8-4. CAPCOM Timer T1 Block Diagram
8/64

8 - Peripherals
CCM0 (FF52h / A9h)
8.1.2 Capture/Compare Registers
The sixteen 16-bit capture/compare registers CC0 CAPCOM Mode Control Registers CCM0
through CC15 are used as data registers for cap- Reset Value :0000h
ture or compare operations with respect to timer T0
14
13
12
11
10
9
8
and T1. The capture/ compare registers are not bit- 15
addressable.
ACC3
CCMOD3
ACC2
CCMOD2
Each of the registers CC0 through CC15 may be
7
6
5
4
3
2
1
0
individuallyprogrammed for capture- or one of 4
CCMOD1
ACC0
CCMOD0
different compare modes, and may be allocated in- ACC1
dividuallyto one of the timers T0 or T1. A special b15 = ACC3: Capture/Compare Register CC3 Alcombination of compare modes additionally allows location bit.
the implement
ation of a ‘double-regist
er’ compare
If set at ’1’, allocate CC3 to Timer 1, otherwise almode. When capture orompare
c
operat
ion is dislocate CC3 to Timer 0.
abled for one of the registers, it may be used for
b14
to b12 =CCMOD3: Capture/Compare Regisgeneral purpose variable storage.
ter CC3 Mode Selection.
The functions of the 16 capture/compare registers See Table 8.3.
are controlled by 4 bit-addressable 16 bit mode
control registers named CCM0, CCM1, CCM2, b11 = ACC2: Capture/Compare Register CC2 Aland CCM3, which are all organized identically. location Bit.
Each register contains bits for the mode selection If set at ’1’ allocate CC2 to timer 1, otherwise alloand timer allocation of four capture/compare regis- cate CC2 to timer 0.
ters. The organization of CAPCOM mode control b10 to b8 =CCMOD2: Capture/Compare Register
register CCM0, and the organization of CAPCOM CC2 Mode Selection.
See Table 8.3.
mode control registers CCM1, CCM2, and CCM3
are decribed below. As the selection of the individ- b7 = ACC1: Capture/Compare Register CC1 Alloual operating mode is identical for each of the cap- cation Bit.
ture/compare registers, only a detailed description If set at ’1’ allocate CC1 to timer 1, otherwise alloof register CCM0 is given. The description for reg- cate CC1 to timer 0.
isters CCM1 through CCM3 is identical except for
the indices of the respective capture/compare reg- b6 to b4 =CCMOD1: Capture/Compare Register
CC1 Mode Selection.
isters.
See Table 8.3.
Table 8.3 lists the possible capture and compare
b3
= ACC0: Capture/Compare Register CC0 Allomodes which can be programmed for each capcation
Bit.
ture/compare register. The different modes are
If set at ’1’ allocate CC0 to timer 1, otherwise allodiscussed in detail in the
followingsubsections.
cate CC0 to timer 0.
b2 to b0 = CCMOD0: Capture/Compare register
CC0 Mode Selection.
See Table 8.3.
9/64

8 - Peripherals
CCM3 (FF58h / ACh)
CAPCOM Mode Control Registers CCM3
Reset Value : 0000h
CCM1 (FF54h / AAh)
CAPCOM Mode Control Registers CCM1
Reset Value : 0000h
15
14
ACC7
7
13
12
11
CCMOD7
6
5
ACC5
10
ACC6
4
3
CCMOD5
9
15
8
ACC15
CCMOD6
2
ACC4
1
14
7
0
CCMOD4
ACC13
13
12
CCMOD15
6
5
11
10
ACC14
4
CCMOD13
3
9
8
CCMOD14
2
ACC12
1
0
CCMOD12
See description CCM0.
See description CCM0.
CCM2 (FF56h / ABh)
CAPCOM Mode Control Registers CCM2
Reset Value : 0000h
15
14
ACC11
7
13
11
CCMOD11
6
ACC9
12
5
10
ACC10
4
3
CCMOD9
9
CCMOD10
2
ACC8
8
1
0
CCMOD8
See description CCM0.
Table 8-3. Capture/Compare Register Mode Selection
CCMODx
Function
(2)
(1)
(0)
0
0
0
Capture / Compare Disabled
0
0
1
Capture on Positive External Transition at Pin CCxIO
0
1
0
Capture on Negative External Transition at Pin CCxIO
0
1
1
Capture on Positive and Negative External Transition at Pin CCxIO
1
0
0
Compare Mode 0: Interrupt only; several interrupts per timer period; enables doubleregisters compare mode for registers CC8 through CC15
1
0
1
Compare Mode 1: Pin toggles on each match; several compare events per timer
period; registers CC0 through CC7 have to be in this mode for double-register
compare operate
1
1
0
Compare Mode 2 : Interrupt only; only one interrupt per timer period
1
1
1
Compare Mode 3: Pin set on match; pin reset on timer overflow; only one compare
event per timer period
Note : x = 0 ..15
10/64

8 - Peripherals
As each of the 16 capture/compare registers CC0 The active transition is selected by the mode bits
through CC15 can be programmed to any of the CCMODx in the respective CAPCOM mode conavailablecapture or compare modes, these modes trol register. In any case, the event causing a capwill be described in detail in the following only forture will also set the respective interrupt request
one representative capture/compare register flag CCxIR which can cause an interrupt or a PEC
which is referred to as CCx. The index x may be service request when enabled.
substituted by any of the indices 0 through 15.
Figure 8.5 shows a block diagram for one capIdentically, the Port 2 pin which is associated with ture/compare register in capture mode.
register CCx will be referred to as CCxIO, where In order to use pin P2.x/CCxIO as external capture
CCxIO is the alternate function of P2.x. The inter- input pin for capture register CCx, P2.x must be
rupt request flag which is associated with cap- configured as input, i.e., the corresponding directure/compare register CCx is referred to as CCxIR, tion control bit DP2.x in register DP2 must be set to
and the allocation and mode control bits for CCx ‘0’. To ensure that a signal transition is properly
are referred to as ACCx and CCMODx, respec- recognized, an external capture input signal
tively.
should be held for at least 8 state times before it
changes its level.
8.1.2.1 CAPTURE MODE
During these 8 states, the capture input signals are
The contents of the timer (T0 or T1, according to scanned sequentially. When a timer is modified or
the state of the allocation control bit ACCx) are incremented during this process, the new timer
remaining
latched into the allocated capture register CCx in contents will already be captured for the
response to an external event. The external event capture registers within the scanning sequence.
causing a capture can be programmed to be either If P2.x/CCxIO is configured as output, the capture
a positive, a negative, or both a positive and a function may be performed by modifying port data
negative transition at the respective external input register bit P2.x through software, e.g. for testing
pin CCxIO.
purposes.
Figure 8-5. Capture Mode Block Diagram
11/64

8 - Peripherals
8.1.2.2 COMPARE MODES
8.1.2.2.1 Compare mode 0
The compare modes allowriggering
t
of events with This is an interrupt-only mode which can be used
minimum software overhead. In all compare for software timing purposes. Compare mode 0 is
modes, the 16-bit value stored in compare register selected for a given compare register CCx by setCCx (in the following also
referred to as ‘compare ting bit field CCMODx of the corres
pondingmode
value’) is continuously compared with the contentscontrol register to ‘100b’.
of the timer (T0 or T1) to which the register is allo- In this mode, interrupt request flag CCxIR is set
cated. If the current timer contents match the com- each time a match is detected between the conpare value, an appropriate output signal which is tents of compare register CCx and the allocated
based on the selected compare mode can be gen- timer. Several of these compare events are possierated at the cor
respondingPort 2 pin, and an in- ble within a single tim
er period when the compare
terrupt request is generated by setting the value in register CCx is updated during the timer
associated interrupt request flag CCxIR.
period. The corresponding Port 2 pin P2.x is not afAs for the capture mode, the compare registers are fected by compare events in this mode and can be
also processed sequentially during compare used as a normal I/O pin.
mode. When any two compare registers are pro- If compare mode 0 is programmed for one of the
grammed to the same compare value, their corre- registers CC8 to CC15, thedouble-register comspondinginterrupt request flags will be set to ‘1’ pare mode becomesenabled for this register if the
and the selected output signals will be generated correspondingbank 1 register is programmed to
within 8 state times after the allocated timer is in- compare mode 1 (see section 8.1.2.2.5 for details
cremented to the compare value. Further compare on thedouble-register mode).
events on the same compare value are
disabled
until the timer is incremented or written to by soft-Figure 8.6 shows a functional diagram of a comware. After a reset, compare events for register pare register CCx configured for compare mode 0.
h and pin remainunaffected
CCx will only become enabled if the allocated timer Note that the port latc
in
compare
mode
0.
Figure
8.7 shows a simple timhas been incremented or written to by software
and one of the compare modes described in the ing example for this mode. In this example, the
compare value in register CCx is modified from cv1
followinghas been selected for this register.
to cv2 after compare events #1 and #3, and from
The different compare modes which can be pro- cv2 to cv1 after events #2 and #4, etc... This results
grammed for a given compare register CCx are se- in periodic interrupt requests from timer Ty, and in
lected by the mode control field CCMODx in the interrupt requests from register CCx which occur at
associated capture/compare mode control register the time specified by the user through cv1 and cv2.
(see table 8.3). In the following, each of the compare modes,includingthe special‘double-register’
mode, is discussed in detail.
Figure 8-6. Compare Mode 0 and 1 Block Diagram
12/64

8 - Peripherals
Figure 8-7. Timing Example for Compare Mode 0
Contents of Ty:
FFFFh
Compare Value cv2
Compare Value cv1
Reload Value < TyREL >
0000h
Interrupt
Requests:
TyIR
t
CCxIR
CCxIR
TyIR
Event #1 Event #2
CCx:=cv2 CCx:=cv1
CCxIR
CCxIR
TyIR
Event #3 Event #4
CCx: =cv2 CCx: =cv1
x = (0...15)
y = (0, 1)
VR0A1639
8.1.2.2.2 Compare Mode 1
mode 1, P2.x must be configured as output, i.e.,
Compare mode 1 is selected for register CCx by the correspondingdirection control bit DP2.x in
register DP2 must be set to ‘1’. With this configurasetting bit field CCMODx of the cor
responding
tion, the initial state of the output signal can be promode control register to ‘101b’.
grammed or its state can be modified at any time
When a match between the contents of the allo- by writing to bit latch P2.x. However, if P2.x is writcated timer and the compare value in register CCx ten to by software at the same time it would be alis detected in this mode, interrupt request flag tered by a compare event, the software write will
CCxIR is set to ‘1’, but also the correspon
ding pin
have priority. In this case, the hardware-t
riggered
CCxIO (alternate output function of Port 2 pin P2.x) change will not become effective.
is toggled. For this purpose, the state of Port 2 outter compare
put latch P2.x (not the pin) is read, inverted, and For operation in thedouble-regis
mode, compare mode 1 must be selected for the
then written back to the output latch.
registers CC0 to CC7 (see section 8.1.2.2.5 for deCompare mode 1 allows several compare events tails on the double register mode).
within a single timer period. An overflow of the
timer to which compare register CCx is allocated Figure 8.8 shows the timing example from the prehas no effect on pin P2.x, nor does it disable or en- vious section, now for compare mode 1. The functional block diagram of a compare register in
able further compare events.
compare mode 1 is included in figure 8.6 of the preIn order to use pin P2.x/CCxIOas compare signal vious section. Note that in compare mode 1 the
output pin for compare register CCx in compare port latch is toggled upon each compare event.
13/64

8 - Peripherals
Figure 8-8. Timing Example for Compare Mode 1
Contents of Ty:
FFFFh
Compare Value CCz
Compare Value CCx
Reload Value < TyREL >
0000h
Interrupt
Requests:
TyIR
CCxIR
CCzIR
TyIR
State of CCxIO:
CCxIR
CCzIR
TyIR
1
0
t
x = (0... 7)
y = (0, 1)
z = (8...15)
VR 001639
8.1.2.2.3 Compare Mode 2
for compare register CCx until the allocated timer
Compare mode 2 is an interrupt-only mode similar overflows. This means that, after the first match,
is
a
to compare mode 0, but only one interrupt request even when the compare registerreloadedwith
valuehigher
than
the
current
timer
value,
no
comper timer period will be generated. Compare mode
2 is selected for register CCx by setting bit field pare event will occur until the next timer period.
CCMODx of the corr
espondingmode control regis- Figure 8.9 shows a functional diagram of a comter to ‘110b’.
pare register configured for compare mode 2. Note
When a match is detected in compare mode 2 for that the port latch and pin remain unaffected in
the first time within a timer period, interrupt requestcompare mode 2. Figure 8.10 shows a simple timing example for this compare mode. In this examflag CCxIR is set to ‘1’. The cor
respondingPort 2
pin P2.x is not affected and can be used as a nor- ple, the compare value in register CCx is modified
mal I/O pin. However, after the first match has from cv1 to cv2 after compare event #1. However,
been detected in this mode, all further compare compare event #2 will not occur until the next period of timer Ty.
events within the same timer period are
disabled
14/64

8 - Peripherals
Figure 8-9. Compare Mode 2 and 3 Block Diagram
Figure 8-10. Timing Example for Compare Mode 2
Contents of Ty:
FFFFh
Compare Value cv2
Compare Value cv1
Reload Value < TyREL >
0000h
Interrupt
Requests:
TyIR
t
CCxIR
TyIR
CCxIR
Event #1
Event #2
C C x: =cv2
CC x:=cv1
TyIR
x = (0...15)
y = (0, 1)
VR0 B1639
15/64

8 - Peripherals
8.1.2.2.4 Compare Mode 3
Figure 8.11 shows the timing example from the
Compare mode 3 is selected for register CCx by previous section, now for compare mode 3. The
functional block diagram of a compare register in
setting bit field CCMODx of the cor
responding
compare mode 3 is included in figure 8.9 of the premode control register to
‘111b’. In compare mode
3, only one compare event will be generated per vious section. Note that in compare mode 3 the
port latch is set by the compare event and reset by
timer period.
the next timer overflow.
When the first match within the timer period is detected, interrupt request flag CCxIR is set to ‘1’ and
pin CCxIO (alternate function of Port 2 pin P2.x) 8.1.2.2.5 Double-Register Compare Mode
will be set to ‘1’. The pin will be reset to ‘0’ when the In the double-register compare mode, two comallocated timer overflows. If a match was found for pare registers work together to control one pin.
register CCx in this mode, all further compare This mode is selected by a specialombination
c
of
events during the current timer period disabled
are
modes for the two registers.
for CCx until the corres
pondingtimer overflows. If,
after a match was detected, the compare register For thedouble-register mode, the 16 capture/comis reloadedwith a new value, this value will not be- pare registers are regarded as two banks of 8 registers each. Registers CC0 through CC7 form bank
come effective until the next timer period.
1, while registers CC8 through CC15 form bank 2.
In order to use pin P2.x/CCxIOas compare signal For the double-register mode, a bank 1 register
output pin for compare register CCx, P2.x must be and a bank 2 register form a register pair. Both regconfigured as output, i.e., the corr
espondingdirecisters of the register pair operate on the pin assocition control bit DP2.x in register DP2 must be set to ated with the bank 1 register (pins CC0IO through
‘1’. With this configuration, the initial state of the CC7IO, which are the alternate functions of Port 2
output signalcan be programmed or its state can pins P2.0 through P2.7). Table 8.4 shows the relabe modified at any time by writing to bit latch P2.x. tionship between the bank 1 and 2 register pairs
and the affected pins for the
double-register mode.
Figure 8-11. Timing Example for Compare Mode 3
Contents of Ty:
FFFFh
Compare Value cv2
Compare Value cv1
Reload Value < TyREL >
0000h
Interrupt
Requests:
TyIR
CCxIR
TyIR
CCxIR
TyIR
State of
CCxIO:
1
0
t
x = (0...15)
Event#2
CCx:=cv1
Event #1
CCx: =cv2
y = (0, 1)
VR0 C1639
16/64

8 - Peripherals
Table 8-4. Double-Register Mode Compare
Register Pairs
Register Pair
Associated Pin
Bank 1
Bank 2
CC0
CC8
CC0IO
CC1
CC9
CC1IO
CC2
CC10
CC2IO
CC3
CC11
CC3IO
CC4
CC12
CC4IO
CC5
CC13
CC5IO
CC6
CC14
CC6IO
CC7
CC15
CC7IO
The double-regis
ter mode can be programmed individuallyor
f each register pair. In order to enable
the double-regis
ter mode, a bank 1 register (CC0
through CC7) must be programmed for compare
mode 1, and the corr
espondingbank 2 register
(CC8 through CC15) must be programmed for
compare mode 0. If the cor
respondingbank 1 compare register isdisabled or programmed for a
mode other than mode 1, the bank 2 register will
operate in compare mode 0 (interrupt-only mode)
as described in section 8.1.2.2.1 .
In thefollowing,a bank 2 register (programmed to
compare mode 0) will be referred to as CCz,
while
the corres
pondingbank 1 register (programmed to
compare mode 1) will be referred to as CCx.
When a match is detected for one of the two registers in a register pair (CCx or CCz), the associated
interrupt request flag (CCxIR or CCzIR) is set to ‘1’
and pin CCxIO corres
ponding to bank 1 register
CCx is toggled. The interrupt generated always
corresponds to the register that caused the match.
NOTE: If a match occurs sim
ultaneouslyfor both
register CCx and register CCz of the register pair,
pin CCxIO will be toggled only once, but two separate compare interrupt requests will be generated,
one for vector CCxINT, and one for vector CCzINT.
In order to use pin P2.x/CCxIO as compare signal
output pin in the
double-regis
ter mode, P2.x must
be configured as output, i.e., the corr
espondingdirection control bit DP2.x in register DP2 must be
set to ‘1’. With this configuration, P2.x has the
same characteristics as in compare mode 1.
Figure 8.12 shows a functional diagram of a register pair configured for the
double-register compare
mode. In this configuration example, the same
timer allocation was chosen for both compare registers, but each register may also be
individuallyallocated to either timer T0 or T1. Figure 8.13 shows
a timing example for this compare mode. In this example, the compare values in registers CCx and
CCz are not modified.
17/64

8 - Peripherals
Figure 8-12. Double-Register Compare Mode Block Diagram
Figure 8-13. Timing Example for the Double-Register Compare Mode
Contents of Ty:
FFFFh
Compare Value CCz
Compare Value CCx
Reload Value < TyREL >
0000h
Interrupt
Requests:
TyIR
CCxIR
CCzIR
TyIR
State of CCxIO:
CCxIR
CCzIR
TyIR
1
0
t
x = (0...7)
y = (0, 1)
z = (8...15)
VR 001639
18/64

8 - Peripherals
8.1.2.3 CAPTURE/COMPARE INTERRUPTS
8.2 GENERAL PURPOSE TIMERS (GPT)
Upon a capture or compare event, the interrupt request flag CCxIR for the respective capture/com- The GPT unit represents a very flexible multifuncpare register CCx is set to ‘1’. This flag can be used tional timer structure which may be used for timing,
to generate an interrupt or trigger a PEC service re- event counting, pulse width measurement, pulse
quest whenenabled by the interrupt enable bit generation, frequency multiplication, and other
purposes. It incorporates five 16-bit timers that
CCxIE.
have been divided into two blocks, GPT1 and
Capture interrupts can be regarded as external in- GPT2.
terrupt requests with the additional feature of reBlock GPT1 contains 3 timers/counters,
while
cording the time at which theriggeringevent
t
block GPT2 contains 2 timers/counters and a 16occurred (see also section 7.2.7 ).
bit Capture/Reload register (CAPREL). The GPT2
Each of the 16 capture/compare registers (CC0 timers have a maximum resolution of 200ns (at
through CC15) has its own bit addressable inter- 40MHz oscillator frequency), the resolution of the
rupt control register (CC0IC through CC15IC) and GPT1 timers is 400ns. Each timer in each block
its own interrupt vector (CC0INT hrough
t
may operateindependently in a number of differCC15INT). The organization of the interrupt control ent modes such as gated timer or counter mode, or
registers CC0IC through CC15IC is described on may be concatenated with another timer of the
next page. Refer to chapter 7 for more details on same block. The auxiliary timers of GPT1 may opthe interrupt control registers.
tionally be configured as reload or capture registers for the core timer. In the GPT2 block, the
additionalCAPREL register supports capture and
reload operation with extended functionality, and
its core timer T6 may be concatenated with CAPCOM timers T0 and T1. Each block has alternate
input/output functions and specific interrupts associated with it. Figures 8.14 and 8.15 show block
diagrams of GPT1 and GPT2. In the
following,the
GPT1 and GPT2 blocks will be described separately.
19/64

8 - Peripherals
CAPCOM Registers Interrupt Control Registers
CC0IC through CC15IC
Reset Value for all of the registers:
0000h
CC8IC (FF88h / C4h)
CC0IC (FF78h / BCh)
7
6
CC0IR
CC0IE
5
4
3
2
1
ILVL
0
GLVL
6
CC1IR
CC1IE
5
4
3
2
1
ILVL
0
GLVL
6
CC2IR
CC2IE
5
4
3
2
1
ILVL
0
GLVL
6
CC3IR
CC3IE
5
6
4
3
2
1
ILVL
CC4IR
CC4IE
5
0
GLVL
6
4
3
2
1
ILVL
CC5IR
CC5IE
5
0
6
CC6IR
CC6IE
4
3
2
1
0
6
CC7IR
CC7IE
GLVL
6
CC9IR
CC9IE
5
4
3
2
1
ILVL
0
GLVL
7
6
5
4
3
2
1
ILVL
0
GLVL
7
6
CC11IR
CC11IE
5
4
3
2
1
ILVL
0
GLVL
7
6
5
4
3
2
1
ILVL
0
GLVL
7
6
5
4
3
2
1
ILVL
0
GLVL
CC14IC (FF94h / CAh)
4
3
2
1
ILVL
5
7
CC13IR CC13IE
GLVL
0
7
6
5
4
CC14IR CC14IE
GLVL
3
2
1
ILVL
0
GLVL
CC15IC (FF96h / CBh)
CC7IC (FF86h / C3h)
7
0
CC13IC (FF92h / C9h)
ILVL
5
1
ILVL
CC12IR CC12IE
GLVL
CC6IC (FF84h / C2h)
7
2
CC12IC (FF90h / C8h)
CC5IC (FF82h / C1h)
7
3
CC11IC (FF8Eh / C7h)
CC4IC (FF80h / C0h)
7
CC8IE
4
CC10IR CC10IE
CC3IC (FF7Eh / BFh)
7
CC8IR
5
CC10IC (FF8Ch / C6h)
CC2IC (FF7Ch / BEh)
7
6
CC9IC (FF8Ah / C5h)
CC1IC (FF7Ah / BDh)
7
7
4
3
ILVL
2
1
0
7
6
CC15IR CC15IE
GLVL
20/64

5
4
3
ILVL
2
1
0
GLVL
8 - Peripherals
Figure 8-14. Block Diagram of GPT1
Auxiliary Timer T2
System
Clock
Interrupt
Requests
External
Count/
Capture/
Reload
Inputs
Mode
Interrupt
and
and
Input
Core Timer T3
Outp ut
Control
Control
External
Output
External
Up/Down
Control
Input
Auxiliary Timer T4
V R0016 24
Figure 8-15. Block Diagram of GPT2
Auxiliary Timer T5
System
Interrupt
Clock
Requests
Mode
and
Interrupt
CAPREL Register
Output
Control
Control
External
External
Output
To CAPCOM
Capture
Input
and
Input
Timers T0, T1
Core Timer T6
VR0A1624
21/64

8 - Peripherals
8.2.1 GPT1 Block
The current contents of each timer can be read or
espondAll three timers T2, T3, T4 of block GPT1 can run in modified by the CPU by accessing the corr
ing
timer
registers
T2,
T3,
or
T4,
which
are
located
3 basic modes, which are timer, gated timer, and
counter mode, and all timers can either count up or in the non-bit-addressable SFR space. When any
down. Each timer has an alternate input function of the timer registers is written by the CPU in the
pin on port 3 associated with it which serves as the state immediately before a timer increment, reload,
gate control in gated timer mode, or as the count or capture is to be performed, the CPU write operainput in counter mode. As a specific feature of the tion has priority in order to guarantee correct recore timer T3, its count direction may be dynami- sults.
cally altered by a signal at an external input pin, From a programmer’s point of view, the GPT1
and each overflow/underflow may be indicated on block is composed of a set of SFRs as shown in figan alternate output function pin. The
auxiliary timure 8.16. Those portions of port and direction regers T2 and T4 may additionally be concatenated isters which are not used for alternate functions by
with the core timer, or used as capture or reload the GPT1 block are not shaded.
registers for the core timer.
Figure 8-16. SFRs and Port Pins Associated with the GPT1 Block
Ports & Direction Control
Alternate Functions
DP3
P3
T2IN/P3.7
T3IN/P3.6
T4IN/P3.5
T3EUD/P3.4
T3OUT/P3.3
Data
Registers
Control
Registers
Interrupt
Control
T2
T2CON
T2IC
T3
T3CON
T3IC
T4
T4CON
T4IC
VR0A1640
DP3
P3
T2
T3
T4
T2CON
Port 3 Direction Control Register
Port 3 Data Register
GPT1 Timer 2 Register
GPT1 Timer 3 Register
GPT1 Timer 4 Register
GPT1 Timer 2 Control Register
T3CON
T4CON
T2IC
T3IC
T4IC
GPT1
GPT1
GPT1
GPT1
GPT1
Timer 3 Control Register
Timer 4 Control Register
Timer 2 Interrupt control Register
Timer 3 Interrupt Control Register
Timer 4 Interrupt Control Register
In the following, the
individualfeatures of each timer in block GPT1 will be discussed separately.
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8 - Peripherals
8.2.1.1 GPT1 CORE TIMER T3
Table 8-5. Core Timer T3 Mode Control
The configuration of the core timer T3 is deterT3M
Mode
mined by its bit-addressable control register
T3CON, which is shown
below
T3CON (FF42h / A1h)
GPT1 Core Timer T3 Control Register
Reset Value :0000h
15
14
13
12
11
R
10
9
8
T3OTL
T3OE
T3UDE
(1)
(0)
0
0
Timer
0
1
Counter
1
0
Gated Timer (gate is active low)
1
1
Gated Timer (gate is active high)
Timer 3 Run Bit
The timer can be started or stopped by software
T3UD
T3R
R
T3M
T3I
through bit T3R (Timer T3 Run Bit). If T3R= ‘0’, the
timer stops. Setting T3R to ‘1’ will start the timer. In
b15 to b11, b5 =R: Reserved.
gated timer mode, the timer will only run if T3R= ‘1’
b10 =T30TL: Timer Output Toggle Latch.
and the gate is active.
Toggles on each overflow/
underflowof T3.
Count Direction Control
Can be set or reset by software.
The count direction of the core timer can be specib9 = T30E: Alternate Output Function Enable.
fied either by software or by the external input pin
This function is
inabledif T30E=1
T3EUD (Timer T3 External Up/Down Control Inb8 = T3UDE: Timer 3 External Up/Down Control put), which is the alternate input function of port pin
Enable Bit.
P3.4. These options are selected by bits T3UD and
b7 = T3UD: Timer 3 Up/Down Control Bit.
T3UDE in control register T3CON. When the
See table 8.6
up/down control is done by software (bit T3UDE =
‘0’), the count direction can be altered by setting or
b6 = T3R: Timer 3 Run Bit.
If set at ’1’ will run Timer/Counter 3 otherwise stops clearing bit T3UD. When T3UDE = ‘1’, pin T3EUD
is selected to be the controlling source of the count
Timer/Counter 3.
direction. However, bit T3UD can still be used to
b4,b3 =T3M: Timer 3 Mode Control.
reverse the actual count direction, as listed in tab2 to b0 =T3I: Timer 3 Input Selection Bits.
ble 8.6. If T3UD = ‘0’ and pin T3EUD shows a low
See table 8.7 and 8.8 for more details.
level, the timer is counting up. With a high level at
T3EUD the timer is counting down. If T3UD = ‘1’, a
high level at pin T3EUD specifies counting up, and
a low level spec
ifies counting down. The count diTimer 3 Mode Selection
rection can be changed regardles
s of whether the
Bit field T3M (Timer 3 Mode Control) selects the timer is running or not.
basic operating mode for timer T3. The
available
When pin T3EUD/P3.4 is used as external count
options are listed in table 8.5, and will be discussed direction control input, its corres
pondingdirection
in detail in theollowing
f
subsections.
control bit DP3.4 must be set to ‘0’.
7
6
5
4
3
2
1
0
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
8 - Peripherals
Table 8-6. GPT1 Core Timer T3 Count
Direction Control
Pin
T3EUD
Bit
T3UDE
Bit
B3UD
X
0
0
Count Up
X
0
1
Count Down
0
1
0
Count Up
1
1
0
Count Down
0
1
1
Count Down
8.2.1.1.1 Timer Mode
Timer mode is selected for the core timer T3 by
setting bit field T3M in register T3CON to ‘00b’. In
this mode, T3 is clocked with the internal system
clock divided by a programmable prescaler, which
is selected by bit field T3I. The input frequency
T3 f
for timer T3 is sc
aled linearlywith slower oscillator
frequencies OSC
f , as can be seen from the following formula:
Count Direction
fT3 =
fOSC
16 × 2<T3I>
The timer input frequencies, resolution and periods
which result from the selected prescaler option
1
1
1
Count Up
when using a 40MHz oscillator are listed in table 8.7. This table alsoapplies to the gated timer
mode of T3 and to theauxiliarytimers T2 and T4 in
Timer 3 Output Toggle Latch
timer and gated timer mode. Note that some numAn overflow or underflow of timer T3 will clock thebers may be rounded to 3 significant digits.
toggle bit T3OTL in control register T3CON. Figure 8.17 shows a block diagram of timer T3 in
T3OTL can also be set or reset by software. Bit timer mode.
T3OE (Alternate Output Function Enable) in register T3CON enables the state of T3OTL to be an alternate function of the external output pin 8.2.1.1.2 Gated Timer Mode
T3OUT/P3.3. For that purpose, a ‘1’ must be writ- In the gated timer mode, the same options for the
ten into port data latch P3.3 and pin T3OUT/P3.3 input frequency as for the timer mode are
available
must be configured as output by setting direction(see table 8.7). However, the input clock to the
control bit DP3.3 to ‘1’. If T3OE = ‘1’, pin T3OUT timer in this mode is gated by the external input pin
then outputs the state of T3OTL. If T3OE = ‘0’, pin T3IN (Timer T3 External Input), which is an alterT3OUT can be used as a general purpose I/O pin. nate function of P3.6. Figure 8.18 shows a block
In addition, T3OTL can be used in conjunction with diagram of the core timer in this mode.
the timer over/underflows as a trigger source for The gated timer mode is selected by setting bit
the counter or reload functions of the
auxiliarytimT3M.1 (T3CON.4) to ‘1’. Bit T3M.0 (T3CON.3) seers. For this purpose, the state of T3OTL does not lects the active level of the gate. Pin T3IN/P3.6
have to beavailableat pin T3OUT, because an in- must be configured as input, i.e., direction control
ternal connection is provided for this option. Thisbit DP3.6 must contain ‘0’.
feature is described in detail in section 8.2.1.2.3
and 8.2.1.2.4 about theauxiliary timers.
Table 8-7. GPT1 Timer Input Frequencies, Resolution and Periods
Timer Input Selection T2I/T3I/T4I
f osc = 40MHz
Prescaler for OSC
f
000b
001b
010b
011b
100b
101b
16
32
64
128
256
512
Input Frequency
2.5MHz
1.25MHz
625kHz
Resolution
400ns
800ns
1.6
µs
Period
26ms
52.5ms
105ms
24/64

110b
1024
312.5kHz 156.25kHz 78.125kHz 39.06kHz
3.2µs
210ms
6.4µs
420ms
12.8µs
840ms
25.6µs
1.68s
111b
2048
19.53kHz
51.2µs
3.36s
8 - Peripherals
If T3M.0 = ‘0’, the timer isenabled when T3IN
T3R. The timer will only run if T3R= ‘1’ and the gate
shows a low level. A high level at this pin stops the is active; it will stop if either T3R= ‘0’ or the gate is
timer. If T3M.0= ‘1’, pin T3IN must have a high level in active. Note that a transition of the gate signal at
in order to enable theimer
t
to run. In addition, the pin T3IN does not cause an interrupt request.
timer can be turned on or off by software using bit
Figure 8-17. Block Diagram of Core Timer T3 in Timer Mode
Figure 8-18. Block Diagram of Core Timer T3 in Gated Timer Mode
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
8 - Peripherals
8.2.1.1.3 Counter Mode
For counter operation, pin T3IN/P3.6 must be conCounter mode is selected for T3 by programming figured as input by setting direction control bit
bit field T3M in register T3CON to ‘01b’. In counter DP3.6 to ‘0’. The maximum input frequency which
mode, timer T3 is clocked by a transition at the ex- is allowed incounter mode is fosc/16 (1.25MHz at
ternal input pin T3IN, which is an alternate function fOSC = 40MHz). To ensure that a transition of the
is
T3IN is corof P3.6. The event causing an increment or decre- count input signal which appliedto
s
held for at
ment of the timer can be a positive, a negative, or rectly recognized, its levelhouldbe
least
8
state
times
before
it
changes.
Figure 8.19
both a positive and a negative transition at this pin.
shows
a
block
diagram
of
the
core
timer
in this
The options are selected by bit field T3I in control
mode.
register T3CON as shown in table 8.8.
Table 8-8. GPT1 Core Timer T3 Counter Mode Input Selection
T3I
Counter T3 in Incremented/Decremented on :
(2)
(1)
(0)
0
0
0
No Transition Selected, T3 Disabled
0
0
1
Positive External Transition at Pin T3IN
0
1
0
Negative External Transition at Pin T3IN
0
1
1
Positive and Negative Ext. Transition at T3IN
1
X
X
(reserved)
Figure 8-19. Block Diagram of Core Timer T3 in Counter Mode
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
8 - Peripherals
8.2.1.1.4 Interrupt Control for Core Timer T3
T2CON (FF40h / A0h)
When the timer T3 overflows from FFFFh 0000h
to
GPT1 Auxiliary Timers T2 Control Register
(when counting up), or when it underflows from Reset Value :0000h
0000h to FFFFh (when counting down), interrupt
14
13
12
11
10
9
8
request flag T3IR in register T3IC will be set. This 15
will cause an interrupt to the timer T3 interrupt vecR
tor T3INT, or trigger a PEC service if the interrupt
7
6
5
4
3
2
1
0
enable bit (T3IE in register T3IC) is set. The organization of register T3IC is shown below. Refer to T2UD T2R
T2M
T2I
chapter 7 for more details on interrupts.
T3IC (FF62h / B1h)
GPT1 Core Timer T3 Interrupt Control Register
Reset Value :0000h
7
6
T3IR
T3IE
5
4
3
2
1
0
T4CON (FF44h / A2h)
GPT1 Auxiliary Timers T4 Control Register
Reset Value :0000h
15
14
13
12
11
10
9
8
3
2
1
0
R
ILVL
GLVL
7
6
T4UD
T4R
5
4
T4M
T4I
b15 to b8 =R: Reserved.
8.2.1.2 GPT1 AUXILIARY TIMERS T2 AND T4
Both auxiliary timers T2 and T4 have exactly the b7 = TxUD: Timer x Up/Down Control bit.
same functionality. They can be configured for TxUD = 0: Select up counting
timer, gated timer, or counter mode with the same TxUD = 1: Select down counting
options for the timerrequencies
f
and the count sig- b6 = TxR: Timer x Run Bit.
nal as the core timer T3. In addition to these 3 TxR = 0: Timer x Stops
counting modes, the auxiliary timers can be con- TxR = 1: Timer x Runs
catenated with the core timer, or they may be used b5 to b3 =TxM: Timer x Mode Control.
as reload or capture registers in conjunction with See table 8.9.
the core timer. Unlike the core timer, the
auxiliary
timers can not be controlled for up or down countb2 to b0 =TxI: Timer x Input Selection.
by an external signal, nor do they have a toggle bit See table 8.7, 8.10, 8.11 or 8.12 for more details.
or an alternate output function.
The individualconfiguration for timers T2 and T4 is
determined by their bit-addressable control registers T2CON and T4CON, which are both organized identically. Note that functions which are
present in all 3 timers of block GPT1 are controlled
in the same bit positions and in the same manner in
each of the specific control registers. The control
registers for theauxiliarytimers are shown below.
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
8 - Peripherals
Table 8-9. GPT1 Auxiliary Timer T2 and T4 Mode Control
T2M/T4M
Mode
(2)
(1)
(0)
0
0
0
Timer
0
0
1
Counter
0
1
0
Gated Timer (gate is active low)
0
1
1
Gated Timer (gate is active high)
1
0
0
Reload
1
0
1
Capture
1
1
X
(reserved, no function selected)
The operating modes for the auxiliary timers T2 selected for theauxiliary timers T2 or T4 by setting
and T4 are independentlyselectable by bit fields the mode control field T2M or T4M in the respecto
T2M and T4M.The availableoptions for both tim- tive control register T2CON or T4CON ‘000b’.
ers are listed in table 8.9,
and will be dis
cussed in
The input frequenciesT2f and fT4 to T2 and T4 are
detail in thefollowingsubsections.
determined by the contents of the timer input seIn all of the counting modes of operation, the auxil- lection fields T2I and T4I as follows:
iary timers can count up or down
depending on the
fOSC
fOSC
state of their control bits T2UD and T4UD. They fT2 =
, fT4 =
<T2I>
can be started or stopped through their run bits
16 × 2
16 × 2<T4I>
T2R and T4R. In gated timer mode, the respective
timer will only run if T2R= ‘1’ or T4R= ‘1’ and the For an overview of the resulting input
requencies
f
,
gate is active.
resolution, and periods when using a 40MHz oscillator, refer to table 8.7 in section 8.2.1.1.1. The
block diagram of an
auxiliarytimer in timer mode is
8.2.1.2.1 Timer Mode
shown in thefollowingfigure 8.20.
The operation of the auxiliary timers in this mode is
identical to that of the core timer T3. Timer mode is
Figure 8-20. Block Diagram of an Auxiliary Timer in Timer Mode
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
8 - Peripherals
8.2.1.2.2 Gated Timer Mode
The gated timer mode for the auxiliary timers func- for timer T4. T2IN is an alternate function of P3.7,
tions as described for the core timer. For the auxil- while T4IN is an alternate function of P3.5. In order
iary timers, an active low level for the gate is to use these alternate functions, the responding
cor
selected by setting the mode control fields T2M or direction control bits DP3.7 and DP3.5 must be set
T4M to ‘010b’, and an active high level is selected to ‘0’. Figure 8.21 shows a block diagram of an
by the bit c
ombination‘011b’. The gate for timer T2 auxiliarytimer in gated timer mode.
is the external input pin T2IN, and T4IN is the gate
Figure 8-21. Block Diagram of an Auxiliary Timer in Gated Mode
8.2.1.2.3 Counter Mode
Basically, the counter mode for the auxiliary timersThe second count source is the toggle bit T3OTL of
functions as described for the core timer. In addi- the core timer T3. One can also select either a
tion, however, timers T2 and T4 offer the possibility positive, a negative, or both a positive and a negaof selecting between two count sources. The first tive transition of T3OTL to cause an increment or
source is an external input pin, T2IN for timer T2, decrement. Note that only state transitions of
and T4IN for timer T4. One can select either a posi- T3OTL which are caused by the overflows/undertive, a negative, or both a positive and a negative flows of T3 will trigger the counter function of
transition to cause an increment or decrement. T2/T4. Modifications of T3OTL by software will
The direction control bits DP3.7 for T2IN or DP3.5 NOT trigger the counter function of T2/T4. Tafor T4IN must be set to ‘0’, and the input signal ble 8.10 summarizes the different counter modes
should be held at least 8 states for correct edge de- of the auxiliary timers. A block diagram of an auxiliary timer in counter mode is shown in figure 8.22.
tection, which results in a maximum
allowedfrequency for the count input signal of 1.25MHz at Using the toggle bit T3OTL as a clock source for an
fOSC = 40MHz.
auxiliarytimer in counter mode offers the feature of
29/64

8 - Peripherals
Table 8-10. GPT1 Auxiliary Timers Counter Mode Input Selection (x = 2 or 4)
T2I/T4I
Counter T2/T4 is Incremented/Decremented on
(2)
(1)
(0)
0
0
0
No transition Selected, Tx Disabled
0
0
1
Positive External Transition on TxIN
0
1
0
Negative External Transition on TxIN
0
1
1
Positive and Negative External Transition on TxIN
1
0
0
No Transition Selected, Tx Disabled
1
0
1
Positive Transition of T3OTL
1
1
0
Negative Transition of T3OTL
1
1
1
Positive and Negative Transition of T3OTL
Figure 8-22. Block diagram of an Auxiliary Timer in Counter Mode
concatenating the core timer T3 and an
auxiliary
clocked on every second overflow/underflow of the
timer. Dependingon which transition of T3OTL is core timer. This configuration forms a 33-bit timer
selected to clock the auxiliarytimer, one can form a (16-bit core timer+T3OTL+16-bit
auxiliarytimer).
32-bit or 33-bit timer. This is
explainedin the folThe count directions of the two concatenated timlowing:
ers are not required to be the same. This offers a
If both a positive and a negative transition of wide variety of different configurations. A block diaT3OTL is used to clock the auxiliary timer, this gram showing the concatenation of a core timer
timer is clocked one very overflow/underflow of theand an auxiliary timer is shown in Figure 8.23.
core timer T3. Thus, the two timers form a 32-bit
timer.
If either a positive or a negative transition of T3OTL
is selected to clock the
auxiliarytimer, this timer is
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8 - Peripherals
Figure 8-23. Concatenation of Core Timer T3 And an Auxiliary Timer
8.1 chap 1
8.2.1 chap 2.1
8.2.1.1 chap 2.1.1
8.2 chap2
Table 8-11. GPT1 Auxiliary Timers Reload Trigger Selection (x = 2 or 4)
T2I/T4I
Reload on
(2)
(1)
(0)
0
0
0
No transition Selected, Tx Disabled
0
0
1
Positive External Transition on TxIN
0
1
0
Negative External Transition on TxIN
0
1
1
Positive and Negative External Transition on TxIN
1
0
0
No Transition Selected, Tx Disabled
1
0
1
Positive Transition of T3OTL
1
1
0
Negative Transition of T3OTL
1
1
1
Positive and Negative Transition of T3OTL
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8 - Peripherals
8.2.1.2 chap 2.1.2
8.2.1.2.1 chap 2.1.2.1
8.2.1.2.2 chap 2.1.2.2
8.2.1.2.3 Reload Mode
Reload mode is selected by programming the
mode control fields T2M or T4M to‘100b’. In reload
mode, the core timer T3 is reloaded with the con-
tents of an auxiliary timer register. Two different
sources can be selected to cause a reload of the
core timer. The options are programmed by the input selection bits of bit fields T2I and T4I in registers T2CON or T4CON as shown in table 8.11.
When programmed for reload mode, the respective auxiliary timer T2 or T4 stops, independent of
its run flag T2R or T4R.
When bit T2I.2= ‘0’ or bit T4I.2= ‘0’, the source
which can cause a reload is the external input pin
T2IN for timer register T2 or pin T4IN for timer register T4. One can select either a positive, a negative, or both a positive and a negative transition at
these input pins to cause a reload. When a selected transition is detected at the input pin T2IN or
T4IN, the core timer T3 is reloaded with the con-
Figure 8-24. GPT1 Auxiliary Timer in External Reload Mode
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8 - Peripherals
Figure 8-25. GPT1 Auxiliary Timer in Reload Mode Triggered by T30TL
tents of the auxiliary timer, and the interrupt request flag T2IR or T4IR of the auxiliary timer is set.
The direction control bits DP3.7 for T2IN or DP3.5
for T4IN must be set to ‘0’, and the input signal
should hold its level for at least 8 states to ensure
correct recognition of the triggering edge. Figure
below shows a block diagram of this external reload mode.
When bit T2I.2= ‘1’ or bit T4I.2= ‘1’, a transition of
the toggle bit T3OTL which is caused by an overflow/underflow of T3 is the trigger for a reload. Note
that software modifications of T3OTL will NOT trigger the reload function. Again, one can select
either a positive, a negative, or both a positive and
a negative transition of T3OTL to cause a reload.
When a selected transition of T3OTL is detected,
the core timer T3 is reloaded with the contents of
the auxiliary timer, and the interrupt request flag
T2IR or T4IR of the respective auxiliary timer is set.
Note that the interrupt request flag T3IR of the core
timer T3 will also be set, indicating the overflow/underflow of T3. Figure 8.25 shows a block diagram
of this reload mode.
Note: Although it is possible, the user should not
program both of the auxiliary timers to reload the
core timer on the same trigger event, since in this
case both of the reload registers would try to reload
the core timer at the same time. In this case, the
contents of T4 are loaded into the core timer T3.
The reload mode triggered by T3OTL can be used
in a number of different configurations.Depending
on the selection of the active transition, the following functions can be performed:
If both a positive and a negative transition of
T3OTL is selected to trigger a reload, the core
timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows.
This is the ‘normal’ reload mode (reload on overflow/underflow).
If either a positive or a negative transition of T3OTL
is selected to trigger a reload, the core timer T3 will
be reloaded with the contents of the auxiliary timer
on every second overflow or underflow.
Using the latter configuration for both auxiliary timers, one can perform very flexible pulse width
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8 - Peripherals
Figure 8-26. GPT1 Timer Configuration For PWM Generation
modulation (PWM). One of the auxiliary timers is
programmed to reload the core timer on a positive
transition of T3OTL, the other is programmed for a
reload on a negative transition of T3OTL. Thus, the
core timer is alternately reloaded by each of the
auxiliary timers.
Figure 8.26 shows such a configuration of the
GPT1 timers for flexible PWM. T2 is programmed
to reload T3 on a positive transition of T3OTL,
while T4 will reload T3 on a negative transition of
T3OTL. The alternate output function for T3OTL is
enabled (T3OE= ‘1’), and the PWM output signal
will be available at pin T3OUT with the configuration DP3.3= ‘1’ and P3.3= ‘1’ for port pin P3.3, as
explained in section 8.2.1.1. The auxiliary timer T2
holds the value of the high time of the output signal,
while T4 is used to reload T3 with the value of the
low time. With this method, the low and high time of
the PWM signal can be varied in a wide range.
Note that T3OTL is implemented as a bit in SFR
Table 8-12. GPT1 Auxiliary Timers Capture TriggerSelection (x = 2 or 4)
T2I/T4I
Contents of T3 Captured into T2/T4 on
(2)
(1)
(0)
X
0
0
No transition Selected, Tx Disabled
X
0
1
Positive External Transition on TxIN
X
1
0
Negative External Transition on TxIN
X
1
1
Positive and Negative External Transition on TxIN
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8 - Peripherals
T3CON, so that it can be altered by software if required to modify the PWM signal.
8.2.1.2.4 Capture Mode
Capture mode is selected by programming the
mode control fields T2M or T4M to ‘101b’. In capture mode, the contents of the core timer are
latched into an auxiliary timer register in response
to a signal transition at the respective auxiliary
timer’s external input pin, which is T2IN/P3.7 for
timer register T2, or T4IN/P3.5 for timer register
T4. The capture trigger signal can be a positive, a
negative, or both a positive and a negative transition.
The two least significant bits of bit fields T2I or T4I
are used to select the active transition (see table
below), while the most significant bits T2I.2 or
T4I.2 are irrelevant for the capture mode. When
programmed for capture mode, the respective auxiliary timer T2 or T4 stops, independent of its run
flag T2R or T4R.
If a selected transition at the corresponding input
pin T2IN or T4IN is detected, then the contents of
the core timer are loaded into the auxiliary timer
T2IC (FF60h / B0h)
GPT1 Auxiliary Timer 2 Interrupt Control Register
Reset Value : 0000h
7
6
T2IR
T2IE
5
4
3
2
1
ILVL
0
GLVL
T4IC (FF64h / B2h)
GPT1 Auxiliary Timer 4 Interrupt Control Register
Reset Value : 0000h
7
6
T4IR
T4IE
5
4
3
ILVL
2
1
0
GLVL
b7 = TxIR: Timer x Interrupt Request Bit.
This flag can be reset to generate an interrupt or
trigger a PEC service request.
b6 = TxIE: Timer x Interrupt Enable Bit.
If set at ’1’ will enable the timer x interrupt.
b5 to b2 = ILVL: Interrupt Priority Level Bits.
See chapter 7 for more details.
b1 to b0 = GLVL: Interrupt Group Priority bits.
See chapter 7 for more details.
Figure 8-27. GPT1 Auxiliary Timer in Capture Mode
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8 - Peripherals
register and the associated interrupt request flag
T2IR for timer T2 or T4IR for timer T4 will be set.
Note that the direction control bits DP3.7 (for T2IN)
and DP3.5 (for T4IN) must be set to ‘0’, and that
the level of the capture trigger signal should be
held for at least 8 states to ensure correct edge detection. Figure below shows a block diagram of an
auxiliary timer in capture mode.
8.2.1.2.5 Interrupt Control
Upon each overflow/underflow or upon each capture or reload trigger of one of the auxiliary timers
T2 or T4, its corresponding interrupt request flag
(T2IR or T4IR) will be set. This flag may cause an
interrupt to the specific auxiliary timer’s interrupt
vector (T2INT or T4INT), or initiate a PEC transfer,
when the request is enabled. Each of the auxiliary
timers T2 and T4 has its own interrupt control register (T2IC, T4IC), as shown in figure below. Refer
to chapter 7 for further details on interrupts.
8.2.2 GPT2 Block
Block GPT2 supports high precision event control
with a maximum resolution of 200ns (at 40MHz oscillator frequency). It includes the two timers T5
and T6, and the 16-bit capture/reload register
CAPREL. Timer T6 is referred to as the core timer,
and T5 is referred to as the auxiliary timer of GPT2.
Figure 8-28. SFRs And Port Pins Associated with the GPT2 Block
Ports & Direction Control
Alternate Functions
DP3
P3
T6OUT/P3.1
CAPIN/P3.2
Data
Registers
Control
Registers
Interrupt
Control
T5
T5CON
T5IC
T6
T6CON
T6IC
CAPREL
CRIC
VR0B1640
DP3
P3
T5
T6
CAPREL
T5CON
T6CON
T5IC
T6IC
CRIC
Port 3 Direction Control Register
Port 3 Data Register
GPT2 Timer 5 Register
GPT2 Timer 6 Register
GPT2 Capture/Reload Register
GPT2 Timer 5 Control Register
GPT2 Timer 6 Control Register
GPT2 Timer 5 Interrupt Control Register
GPT2 Timer 6 Interrupt Control Register
GPT2 CAPREL Interrupt Control Register
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An overflow/underflow of T6, which can only operate in timer mode, is indicated by a toggle bit
T6OTL whose state may be output on an alternate
function port pin. In addition, T6 may be reloaded
with the contents of CAPREL. The toggle bit also
supports concatenation of T6 with auxiliary timer
T5, while concatenation of T6 with CAPCOM timers T0 and T1 is provided through a direct connection. Based on an external signal, the contents of
T5 can be captured into register CAPREL, and T5
may optionally be cleared. Both timer T6 and T5
can count up or down, and the current timer value
can be read or modified by the CPU in the non-bitaddressable SFRs T5 and T6. Each of the above
features will be described in detail in the following
subsections.
From a programmer’s point of view, the GPT2
block is represented by a set of SFRs as shown in
figure below. Those portions of port and direction
registers which are not used for alternate functions
by the GPT2 block are not shaded.
8.2.2.1 GPT2 CORE TIMER T6
The operation of the core timer T6 is controlled by
the bit-addressable control register T6CON, is
shown below.
The core timer T6 can only run in timer mode. It is
started or stopped by software through bit T6R
(Timer T6 Run Bit). If T6R= ‘0’, the timer stops. Setting T6R to ‘1’ will start the timer. The count direc-
T6CON (FF48h / A4h)
GPT2 Core Timer T6 Control Register T6CON
Reset Value : 0000h
15
14
13
T6SR
12
11
R
7
6
5
T6UD
T6R
4
3
10
9
8
T6OTL
T6OE
R
2
1
0
R
T6I
b15 = T6SR: Timer Reload Mode Enable Bit.
The reload from register CAPREL is enabled if
this bit is set at ’1’.
b14 to b11 and b5 to b3 = R: Reserved.
b10 = T6OTL: Timer 6 Output Toggle Latch.
Toggles on each overflow/underflow of T6.
Can be set or reset by software.
b9 = T6OE: Timer 6 Alternate Output Function enabled if T6OE = 1.
b7 = T6UD: Timer 6 Up/Down Control.
T6UD = 0. Timer 6 is counting up
T6UE = 1. Timer 6 is counting down.
b6 = T6R: Timer 6 Run Bit.
Timer 6 runs if T6R = 1.
b2 to b0 = T6I: Timer 6 Input Selection.
See table 8.13.
b2 to b0 = T6I: Timer 6 Input Selection.
See table 8.13.
Table 8-13. GPT2 Timer Input Frequencies, Resolution and Periods
Timer Input Selection T2I/T3I/T4I
fosc = 40MHz
000b
001b
010b
011b
100b
101b
110b
111b
Prescaler for fosc
8
16
32
64
128
256
512
1024
Input Frequency
5MHz
2.5MHz
1.25kHz
625kHz
Resolution
200ns
400ns
800 ns
1.6µs
3.2µs
6.4µs
12.8µs
25.6µs
Period
13ms
26ms
52.5ms
105ms
210ms
420ms
840ms
1.68s
tion can be controlled by software through bit
T6UD.
tor frequencies and is determined as follows:
fT6 =
8.2.2.1.1 Timer Mode
Timer T6 is clocked with the internal system clock
divided by a programmable prescaler. Eight different prescaler options can be selected by bit field
T6I in control register T6CON. The input frequency
fT6 to timer T6 is scaled linearly with slower oscilla-
312.5kHz 156.25kHz 78.125kHz 39.06kHz
fOSC
8 × 2<T6I>
The resulting input frequency, resolution, and timer
period when using a 40MHz oscillator is illustrated
in table 8.13. This table also applies to GPT2 auxiliary timer T5. Note that the numbers may be
rounded to 3 significant digits.
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8 - Peripherals
An overflow or underflow of timer T6 will clock the
toggle bit T6OTL in control register T6CON.
T6OTL can also be set or reset by software. Bit
T6OE (Alternate Output Function Enable) in register T6CON enables the state of T6OTL to be an alternate function of the external output pin
T6OUT/P3.1. For that purpose, a ‘1’ must be written into port data latch P3.1 and pin T6OUT/P3.1
must be configured as output by setting direction
control bit DP3.1 to ‘1’. If T6OE= ‘1’, pin T6OUT
then outputs the state of T6OTL. If T6OE= ‘0’, pin
T6OUT can be used as a general purpose I/O pin.
In addition, T6OTL can be used as the trigger
source for the counter function of auxiliary timer
T5. For this purpose, the state of T6OTL does not
have to be available at pin T6OUT, because an internal connection is provided for this option. This
feature is described in detail in section 8.2.2.2
about auxiliary timer T5.
A reload of timer T6 on overflow/underflow with the
contents of register CAPREL can be selected
through bit T6SR in register T6CON. A detailed description of this option can be found in section 8.2.2.2.3 about the CAPREL register.
T6IC (FF68h / B4h)
GPT2 Timer T6 Interrupt Control Register
Reset Value : 0000h
7
6
T6IR
T6IE
5

3
ILVL
2
1
0
GLVL
An overflow or underflow of timer T6 can also be
used to clock timers T0 or T1 in the CAPCOM unit.
For this purpose, a direct internal connection between timer T6 and timers T0 and T1 exists. Refer
to section 8.1 (CAPCOM Unit) for more details.
Figure below shows a block diagram of T6 in timer
mode.
8.2.2.1.2 Timer T6 Interrupt Control
When timer T6 overflows from FFFFh to 0000h
(when counting up), or when it underflows from
0000h to FFFFh (when counting down), the interrupt request flag T6IR in register T6IC will be set.
This will cause an interrupt to the timer T6 interrupt
vector T6INT, or will trigger a PEC transfer, if the
Figure 8-29. Block Diagram of GPT2 Core Timer T6 in Timer Mode
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4
8 - Peripherals
T5CON (FF46h / A3h)
GPT2 Auxiliary Timer T5 Control Register
Reset Value : 0000h
15
14
T5SC
T5CLR
7
6
T5UD
T5R
13
12
11
10
CI
5
8
1
0
R
4
R
9
3
T5M
2
T5I
b15 = T5SC: Timer 5 Capture Mode Enable Bit.
Capture into register CAPREL is enabled if
T5SC = 1.
b14 = T5CLR: Timer 5 Clear Bit.
T5CLR = 0. Timer 5 is not cleared on a detected
transition at CAPIN
T5CCR = 1. Timer 5 is clear in a detected transition at CAPIN.
b13,b12 = CI: Register CAPREL Input Selection.
See table 8.15.
b11 to b8 and b5 to b4 = R: Reserved.
b7 = T5UD: Timer 5 Up/Down Control Bit.
T5UD = 0. Timer 5 is counting up
T5UD = 1. Timer 5 is counting down.
b6 = T5R: Timer 5 Run Bit.
Timer 5 runs if T5R = 1 otherwise stops.
b3 = T5M: Timer 5 Mode Control.
If T5M = 0 timer mode is enabled otherwise
counter mode is enabled.
b2 to b0 = T5I: Timer 5 Input Selection.
See table 8.13 and 8.14 for more details.
interrupt enable bit T6IE in register T6IC is set. The
organization of interrupt control register T6IC is
shown below. Refer to chapter 7 for more details
on interrupts.
8.2.2.2 GPT2 AUXILIARY TIMER T5
The auxiliary timer T5 can operate in timer or
counter mode. These two modes are described
below. Unlike the core timer T6, the auxiliary timer
T5 has no toggle bit and no alternate output function. The operation of T5 is controlled by register
T5CON, which is shown in the following subsections.
In both timer and counter mode of operation, the
auxiliary timer T5 can count up or down depending
on the control bit T5UD, and it can be started or
stopped through its run bit T5R (Timer T5 Run Bit).
If T5R= ‘0’, the timer stops. Setting T5R= ‘1’ will
start the timer.
Figure 8-30. Block Diagram of GPT2 Core Auxiliary Timer T5 in Timer Mode
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8 - Peripherals
8.2.2.2.1 Timer Mode
In this mode, selected in register T5CON by setting
bit T5M= ‘0’, the auxiliary timer T5 operates exactly
as described for the core timer T6. It has the same
8 prescaler options, which are selected by bit field
T5I in control register T5CON. The input frequency
fT5 to timer T5 is determined as follows:
fT5 =
no external input pin. In this mode, timer T5 is
clocked by a transition of T6OTL. Note that only
state transitions of T6OTL which are caused by
overflows/underflows of T6 will trigger the counter
function of T5. Modifications of T6OTL by software
will NOT trigger the counter function of T5. Either a
positive, a negative, or both a positive and a negative transition of T6OTL can be selected to cause
an increment or decrement of T5. The options are
selected by bit field T5I in control register T5CON
fOSC
8 × 2<T5I>
The resulting input frequency, resolution, and timer
period when using a 40MHz oscillator is the same
as for T6 (see table 8.13). Figure 8.30 shows a
block diagram of T5 in timer mode.
T5IC (FF66h / B3h)
GPT2 Timer 5 Interrupt Control Register
Reset Value : 0000h
7
6
T5IR
T5IE
5
4
3
ILVL
8.2.2.2.2 Counter Mode
The counter mode of timer T5, selected by T5M=
‘1’, can only be used in conjunction with the toggle
bit T6OTL of the core timer T6, since timer T5 has
Table 8-14. Auxiliary Timer T5 Counter Mode Input Selection
T5I
Counter T5 is Incremented/Decremented on
(2)
(1)
(0)
0
X
X
No Transition Selected, T5 Disabled
1
0
0
No Transition Selected, T5 Disabled
1
0
1
Positive Transition of T6OTL
1
1
0
Negative Transition of T6OTL
1
1
1
Positive and Negative Transition of T6OTL
Figure 8-31. Block Diagram of GPT2 Auxiliary Timer T5 in Counter Mode
40/64

2
1
0
GLVL
8 - Peripherals
as shown in table 8.14. Figure below shows a block
diagram of timer T5 in this mode.
This mode can be used to concatenate the core
timer T6 and the auxiliary timer T5 to form a 32-bit
or a 33-bit timer (16-bit timer T6+T6OTL+16-bit
timer T5, see also section 8.2.1.2.3 ). The count directions of the two timers are not required to be the
same, which offers a wide variety of different configurations. Figure 8.32 shows a block diagram for
the concatenation of timers T5 and T6.
8.2.2.2.3 Timer T5 Interrupt Control
When timer T5 overflows from FFFFh to 0000h
(when counting up), or when it underflows from
0000h to FFFFh (when counting down), the interrupt request flag T5IR in register T5IC will be set.
This will cause an interrupt to the timer T5 interrupt
vector T5INT, or will trigger a PEC transfer, if the
interrupt enable bit T5IE in register T5IC is set. The
organization of interrupt control register T5IC is described below. Refer to Chapter 7 for more details
on interrupts.
Table 8-15. Register CAPREL Capture Trigger Selection
CI
Contents of T5 Captured into CAPREL on
(1)
(0)
0
0
No Transition Selected, Capture Disabled
0
1
Positive External Transition on CAPIN
1
0
Negative External Transition on CAPIN
1
1
Positive and Negative Transition Ext. on CAPIN
Figure 8-32. Concatenation of Timers T5 and T6
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8 - Peripherals
8.2.2.3 GPT2 CAPTURE/RELOAD
REGISTER CAPREL
This 16-bit register can be used as a capture register for the auxiliary timer T5 or as a reload register
for the core timer T6, or as both. These functions
are controlled separately by bits in the two timer
control registers T5CON and T6CON. In the following, the use of register CAPREL in capture and reload mode is described in detail.
8.2.2.3.1 Capture Mode
This mode is selected by setting bit T5SC= ‘1’ in
control register T5CON. The source for a capture
trigger is the external input pin CAPIN, which is an
Figure 8-33. Register CAPREL In Capture Mode
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
alternate input function of port pin P3.2. Either a
positive, a negative, or both a positive and a negative transition at this pin can be selected to trigger
the capture function. The active edge is controlled
by bit field CI in register T5CON according to table below.
For triggering a capture operation on register
CAPREL, pin CAPIN/P3.2 must be configured as
input by setting its direction control bit DP3.2 to ‘0’.
The maximum input frequency for the capture trigger signal at pin CAPIN is fOSC /8 (2.5MHz at fOSC
=40MHz). To ensure that a transition of the capture
trigger signal is correctly recognized, its level
should be held for at least 4 state times before it
changes.
8 - Peripherals
When a selected transition at the external input pin
CAPIN is detected, the contents of the auxiliary
timer T5 are latched into register CAPREL, and interrupt request flag CRIR is set. With the same detected transition at CAPIN, timer T5 can be cleared
to 0000h. This option is controlled by bit T5CLR in
register T5CON. The timer T5 clear function can
be selected regardless of the capture function. To
ensure that a transition of the clear trigger signal is
correctly recognized, its level should be held for at
least 4 state times. Once timer T5 is cleared, the interrupt request flag CRIR in register CRIC is set.
Figure below shows a block diagram of register
CAPREL in capture mode.
Note that bit T5SC only controls whether a capture
is performed or not. If T5SC=‘0’, the input pin
CAPIN can still be used as an external interrupt input (see also section 7.2.7 ). This interrupt is controlled by the CAPREL interrupt control register CR
IC described in section 8.2.2.3.3 .
8.2.2.3.2 Reload Mode
CRIC (FF6Ah / B5h)
CAPREL Register Interrupt Control Register
Reset Value : 0000h
7
6
CRIR
CRIE
5
4
3
ILVL
2
1
0
GLVL
Figure 8-34. Register CAPREL In Reload Mode
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8 - Peripherals
This mode is selected by setting bit T6SR= ‘1’ in
register T6CON. The event causing a reload in this
mode is an overflow or underflow of the core timer
T6.
If T6SR= ‘1’ when timer T6 overflows from FFFFh
to 0000h (when counting up) or when it underflows
from 0000h to FFFFh (when counting down), the
value stored in register CAPREL is loaded into
timer T6. This will not set the interrupt request flag
CRIR associated with the CAPREL register. However, interrupt request flag T6IR will be set indicating the overflow/underflow of T6. Figure below
shows a block diagram of the reload mode of register CAPREL.
8.2.2.3.3 CAPREL Register Interrupt Control
Whenever a transition according to the selection in
bit field CI is detected at pin CAPIN/P3.2, interrupt
request flag CRIR in register CRIC is set. This will
cause an interrupt to the CAPREL register interrupt
vector CRINT, or will trigger a PEC service if the interrupt enable bit CRIE in register CRIC is set. The
organization of register CRIC is described below.
Refer to chapter 7 for more details on interrupts.
8.2.2.3.4 Using the Capture and Reload Mode
Since the reload and the capture mode of register
CAPREL can be configured individually by bits T5SC
and T6SR, one can set both bits to use the two
modes of register CAPREL simultaneously. This
feature can be used to build a digital PLL configuration which generates an output frequency that is a
multiple of the input frequency, as described in the
following. Figure below shows a block diagram of
this configuration.The operation in this mode will be
explained with an example.
Consider the case, where one has to detect consecutive external events which may occur aperiodically, but needs a finer resolution, that means, more
‘ticks’ within the time between two external events.
For this purpose, one measures the time between
the external events using timer T5 and the CAPREL
register. Timer T5 runs in timer mode counting up
(T5UD= ‘0’) with a frequency of for example fOSC /64.
The external events are applied to pin CAPIN. When
Figure 8-35. Register CAPREL In Capture And Reload Mode
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8 - Peripherals
an external event occurs, the timer T5 contents are
latched into register CAPREL, and timer T5 is
cleared (T5CLR= ‘1’). Thus, register CAPREL always contains the correct time between two
events, measured in timer T5 increments. Timer
T6, which runs in timer mode counting down
(T6UD= ‘1’) with a frequency of for example fOSC /8,
uses the value in register CAPREL to perform a reload on underflow. This means, the value in register
CAPREL represents the time between two underflows of timer T6, now measured in timer T6 increments. Since timer T6 runs 8 times faster than timer
T5, it will underflow 8 times within the time between
two external events. Thus, the underflow signal of
timer T6 generates 8 ‘ticks’. Upon each underflow,
interrupt request flag T6IR will be set and bit
T6OTL will be toggled. The state of T6OTL may be
output on pin T6OUT. This signal has 8 times more
transitions than the signal which is applied to pin
CAPIN.
The underflow signal of timer T6 can furthermore be
used to clock the CAPCOM timers T0 and/or T1,
which gives the user the possibility to set compare
events basedon a finer resolution than that of the external events.
8.3 A/D CONVERTER (ADC)
Figure 8-36. A/D Converter Block Diagram
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8 - Peripherals
The ST10x166 provides a 10-bit A/D converter
with 10 multiplexed analog input channels and a
sample & hold circuit on-chip. It supports 4 different conversion modes, including single channel,
single channel continuous, auto scan, and auto
scan continuous conversion. The external analog
reference voltages VAREF and VAGND are fixed.Figure below shows a block diagram of the A/D converter.
In the following Figure 8.37, all SFRs and port pins
are listed which are associated with the A/D converter.
8.3.1 Conversion Modes and Operation
The analog input channels AN0 through AN9 are
alternate functions of port 5, which is a 10-bit input
only port. The port 5 lines may either be used as
analog or digital inputs. No special action is required by the user software to configure the port 5
lines as analog inputs.
The functions of the A/D converter are controlled
by the A/D Converter Control Register ADCON.
This bit-addressable register holds the bits which
specify the analog channel, the conversion mode,
and the status of the converter.
Figure 8-37. SFRs and Port pins Associated with the A/D Converter
Ports
Data
Registers
Control
Registers
P5
ADDAT
ADCON
AN9 ... AN0
P5.9 ... P5.0
P5
ADDAT
ADCON
ADCIC
ADEIC
Interrupt
Control
ADCIR
ADEIR
VR0C1 640
Port 5 Data Register
A/D Converter Result Register
A/D Converter Control Register
A/D Converter End of Conversion Interrupt Control Register
A/D Converter Overrun Error Interrupt Control Register
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8 - Peripherals
Table 8-16. Conversion Mode Selection
ADM
ADCON (FFA0h / D0h)
A/D Converter Control Register
Reset Value: 0000h
Conversion Mode
(1)
(0)
0
0
Single Channel Conversion
0
1
Single Channel
Continuous Conversion
15
1
0
Auto Scan Conversion
1
1
Auto Scan Continuous
Conversion
ADDAT (FEA0h / 50h)
A/D Converter Result Register
Reset Value: 0000h
15
14
13
12
11
CHNR
7
6
10
R
5
4
3
9
8
ADRES [9..8]
2
1
14
13
12
11
10
9
R
7
6
ADST
R
5
4
ADM
8
ADBSY
3
2
1
0
ADCH
b15 to b9 and b6 =R: Reserved.
b8 = ADBSY: ADC Busy Flag
Read only bit.
Indicates if a conversion is in progress or not.
b7 = ADST: Start Bit.
Is used to start or stop the A/D Converter.
b5 to b4 = ADM: Mode Selection bit.
Determines the mode of operation of the A/D
Converter as illustrates in table 8.16.
b3 to b0 = ADCH: ADC Analog Input Channel Selection.
See table 8.17.
0
ADRES [7..0]
b15 to b12 = CHNR: 4-Bit Channel Number.
b11 and b10 = R: Reserved.
b9 to b0 = ADRES: 10-Bit Result of the A/D Conversion.
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8 - Peripherals
Table 8-17. Analog Input Channel Selection
ADCH
Selected Channel
(3)
(2)
(1)
(0)
0
0
0
0
AN0 :
Analog Input Channel 0
0
0
0
1
AN1 :
Analog Input Channel 1
0
0
1
0
AN2 :
Analog Input Channel 2
0
0
1
1
AN3 :
Analog Input Channel 3
0
1
0
0
AN4 :
Analog Input Channel 4
0
1
0
1
AN5 :
Analog Input Channel 5
0
1
1
0
AN6 :
Analog Input Channel 6
0
1
1
1
AN7 :
Analog Input Channel 7
1
0
0
0
AN8 :
Analog Input Channel 8
1
0
0
1
AN9 :
Analog Input Channel 9
1
0
1
X
(reserved, no channel selected)
1
1
X
X
(reserved, no channel selected)
Bit ADST is used to start or stop the A/D converter.
The busy flag ADBSY is a read-only flag which indicates whether a conversion is in progress or not.
Bit field ADM determines the mode of operation of
the A/D converter as illustrated in table 8.16.
These modes will be discussed in detail in the following subsections.
Bit field ADCH in register ADCON specifies the
analog input channel which is to be converted in
the single channel conversion modes, or the channel with which a conversion sequence of different
channels will be started in the auto scan modes.
Table 8.17 shows the reference between the
ADCH field and the selected input channels. Programming ADCH to one of the reserved combinations will produce invalid results.
The A/D Converter Result Register ADDAT,
shown in figure below holds the result of a conversion. The low order 10 bits (ADDAT [9..0]) contain
the converted digital result, while the upper four
bits (ADDAT [15..12]) represent the number of the
channel which was converted. Register ADDAT is
not bit-addressable. The data remains in ADDAT
until it is overwritten by the data of the next conversion.
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In all 4 conversion modes, a conversion is started
by setting bit ADST= ‘1’. This will also set the busy
flag ADBSY. The converter then selects and samples the input channel specified by the channel selection field ADCH in register ADCON. This will
take 1.575µs (at 40MHz oscillator frequency). The
sampled level will then be held internally for the
rest of the conversion, which will require another
8.175µs (at 40 MHz). When the conversion of this
channel is complete, the 10-bit result together with
the number of the converted channel is transferred
into the result register ADDAT, and the interrupt request flag ADCIR will be set. If a previous conversion result was not read out of register ADDAT by
the time a new conversion is complete, then the
A/D overrun error interrupt request flag ADEIR will
also be set. The previous result in register ADDAT
is lost because it is overwritten by the new value.
If bit ADST is reset and then set again while a conversion is in progress, this conversion will be
aborted and the converter will start again. When
setting bit ADST, a different conversion mode and
channel number may be specified. While a conversion is in progress modifications to the mode selection field ADM will not become effective until the
next conversion. Modifications to the channel selection field ADCH will not become effective until
8 - Peripherals
the next conversion in the single channel conversion modes, or the next conversion round in the
auto scan modes.
8.3.1.1 SINGLE CHANNEL CONVERSION MODE
This mode is selected by programming the mode
selection field ADM in register ADCON to ‘00b’. After starting the converter through bit ADST, the
channel specified in bit field ADCH will be converted. After the conversion is complete, interrupt
request flag ADCIR will be set and the converter
will automatically stop and reset bits ADBSY and
ADST. Resetting bit ADST while a conversion is in
progress has no effect.
8.3.1.2 SINGLE CHANNEL CONTINUOUS
CONVERSION
This mode is selected by bit combination ‘01b’ in bit
field ADM. After starting the converter, the specified channel will be converted repeatedly until the
converter is stopped by software. Interrupt request
flag ADCIR is set at the end of each single conversion. When bit ADST is reset by software, the converter will complete the current conversion and
then stop and reset bit ADBSY.
8.3.1.3 AUTO SCAN CONVERSION MODE
With this mode, a set of different analog input
channels can be converted without requiring software to change the channel number. The channels
are converted consecutively, starting with channel
ANn which is specified in bit field ADCH, down to
and including channel AN0. The auto scan conversion mode is selected by ‘10b’ in bit field ADM. After conversion of channel ANn has been
completed, interrupt request flag ADCIR is set and
the converter starts to convert channel ANn-1. This
procedure is repeated until conversion of channel
AN0 is complete. The A/D converter then stops
and resets bits ADST and ADBSY. Resetting bit
ADST while a conversion is in progress has no effect.
8.3.1.4 AUTO SCAN CONTINUOUS CONVERSION
This mode is selected by setting field ADM in register ADCON to ‘11b’. The auto scan continuous
mode differs from the auto scan mode described in
the previous section only in that the converter does
not stop after the conversion of channel AN0 is
completed. The internal channel number counter is
reloaded with the channel number which is specified in register ADCON, and the conversion round
is started again. This procedure is repeated until
the converter is stopped by software. When bit
ADST is reset by software, the converter will continue until the conversion of channel AN0 is complete. It will then stop and reset bit ADBSY.
8.3.2 A/D Converter Interupt Control
At the end of each conversion, interrupt request
flag ADCIR in interrupt control register ADCIC is
set. This end-of-conversion interrupt request may
cause an interrupt to vector ADCINT, or it may trigger a PEC data transfer which stores the conversion result from register ADDAT e.g. into a table in
the internal RAM for later evaluation. Note that the
number of the converted channel is contained in
the four most significant bits in register ADDAT.
When the conversion result has not been read out
of register ADDAT at the time the next conversion
is complete, the previous result will be overwritten
and interrupt request flag ADEIR in register ADEIC
will be set. This overrun error interrupt request of
the A/D converter may be used to cause an interrupt to vector ADEINT. The interrupt control registers which are associated with the A/D converter
are described below. For more details on interrupts
refer to chapter 7.
8.4 SERIAL CHANNELS
For serial communication with other microcontrollers, microprocessors, and external peripherals,
the ST10x166 has two identical serial interfaces
ADCIC (FF98h / CCh)
Interrupt Control Registers
Reset Value: 0000h
7
6
ADCIR
ADCIE
5
4
3
2
1
ILVL
0
GLVL
ADEIC (FF9Ah / CDh)
Interrupt Control Registers
Reset Value: 0000h
7
6
ADEIR
ADEIE
5
4
3
ILVL
2
1
0
GLVL
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8 - Peripherals
Figure 8-38. SFRs And Port Pins Associated With The Serial Channels
Ports & Direction Control
Alternate Functions
DP3
P3
RXD0/P3.11
TXD0/P3.10
RXD1/P3.9
TXD1/P3.8
Data
Registers
Control
Registers
S0BG
S0CON
S0TIC
S0RIC
S0EIC
S1CON
S1TIC
S1RIC
S1EIC
Interrupt
Control
S0TBUF
S0RBUF
S1BG
S1TBUF
S1RBUF
VR 0D1640
DP3
P3
S0BG
S0TBUF
S0RBUF
S1BG
S1TBUF
S1RBUF
S0CON
S1CON
S0TIC
S0RIC
S0EIC
S1TIC
S1RIC
S1EIC
Port 3 Direction Control Register
Port 3 Data Register
Serial Channel 0 Baud Rate Generator/Reload Register
Serial Channel 0 Transmit Buffer Register (write only)
Serial Channel 0 Receive Buffer Register (read only)
Serial Channel 1 Baud Rate Generator/Reload Register
Serial Channel 1 Transmit Buffer Register (write only)
Serial Channel 1 Receive Buffer Register (read only)
Serial Channel 0 Control Register
Serial Channel 1 Control Register
Serial Channel 0 Transmit Interrupt Control Register
Serial Channel 0 Receive Interrupt Control Register
Serial Channel 0 Error Interrupt Control Register
Serial Channel 1 Transmit Interrupt Control Register
Serial Channel 1 Receive Interrupt Control Register
Serial Channel 1 Error Interrupt Control Register
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8 - Peripherals
on-chip, Serial Channel 0 (ASC0) and Serial Channel 1 (ASC1). They support full-duplex asynchronous communication up to 625KBaud and
half-duplex synchronous communication up to
2.5MBaud. In the synchronous mode, data are
transmitted or received synchronous to a shift
clock which is generated by the ST10x166. In the
asynchronous mode, 8 or 9-bit data transfer, parity
generation, and the number of stop bits can be selected. The reception of data is double-buffered.
Parity, framing, and overrun error detection is provided to increase the reliability of data transfers.
For multiprocessor communication, a mechanism
to distinguish address from data bytes is included,
and a loop-back option is available for testing purposes. Each serial channel has separate interrupt
vectors for receive, transmit, and error, and each
channel has its own dedicated baud rate generator. This is a 13-bit timer with a 13-bit reload register which supports a wide range of baud rates
without oscillator tuning.
Figure 8.38 gives an overview of the SFRs and port
pins which are associated with the serial channels.
Those portions of Port 3 and its direction control
register DP3 which are not used for alternate functions by the serial channels are not shaded.
8.4.1 Modes of Operation
The operation of the serial channels ASC0 and
ASC1 is controlled by the bit-addressable control
registers S0CON and S1CON, which are shown
below. They contain control bits for mode and error
S0CON (FFB0h / D8h)
Serial Channel Control Register S0CON
Reset Value: 0000h
15
14
13
12
11
S0R
S0LB
S0BRS
7
6
5
4
3
S0OEN
S0FEN
S0PEN
S0REN
S0STP
R
10
9
8
S0OE
S0FE
S0PE
2
1
0
S0M
S1CON (FFB8h / DCh)
Serial Channel Control Register S1CON
Reset Value: 0000h
15
14
13
12
11
S1R
S1LB
S1BRS
7
6
5
4
3
S1OEN
S1FEN
S1PEN
S1REN
S1STP
R
10
9
8
S1OE
S1FE
S1PE
2
1
0
S1M
b15 = SxR: ASCx Baud Rate Generator Run Bit.
The Baud Rate Generator is enabled if SxR = 1.
b14 = SxLB: Loop Back Mode Enable Bit.
The Loop Back Mode is enabled if SxLB = 1.
b13 = SxBRS: Baud Rate Selection Bit.
The current baud rate is multiplied by 2/3 if
SxBRS=1.
b12 to b11 = R: Reserved.
b10 = Sx0E: Overrun Error Flag.
Set by hardware when an overrun error occurs
and SxOEN = 1. Must be reset by software.
b9 = SxFE: Framing Error Flag.
Set by hardware when a framing error occurs and
SxFEN = 1; Must be reset by software.
b8 = SxPE: Parity Error Flag.
Set by hardware when a parity error occurs and
SxPEN = 1; Must be reset by software.
b7 = SxOEN: Overrun Check Enable Bit.
SxOEN = 0: Overrun Check Disabled
SxOEN = 1: Overrun Check Enabled.
b6 = SxFEN: Framing Check Enable Bit.
SxFEN = 0: Framing Check Disabled
SxFEN = 1: Framing Check Enabled.
b5 = SxPEN: Parity Check Enable Bit.
SxPEN = 0: Parity Check Disabled
SxPEN = 1: Parity Check Enabled.
b4 = SxREN: Receiver Enable Bit.
Used to Initiate Reception. Reset by hardware after a byte in synchronous mode has been received.
b3 = SxSTP: Number of Stop Bits Selection.
SxSTP = 0: One Stop Bit
SxSTP = 1: Two Stop Bits.
b2 to b0 = SxM: ASCx Mode Control.
(see table 8.18 ).
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8 - Peripherals
Table 8-18. Serial Channel Modes of Operation
S0M/S1M
Mode
(2)
(1)
(0)
0
0
1
8-bit data, asynchronous operation
0
1
1
7-bit data + parity bit, asynchronous operation
1
0
0
9-bit data, asynchronous operation
1
0
1
8-bit data + wake-up bit, asynchronous operation
1
1
1
8-bit data + parity bit, asynchronous operation
0
0
0
8-bit data, asynchronous operation
X
1
0
(reserved)
check selection, and status flags for error identification.
Serial data transmission or reception is only possible when the Baud Rate Generator Run Bit S0R or
S1R for the respective channel is set to ‘1’. The individual operating mode for each channel is determined by the mode control fields S0M and S1M in
registers S0CON and S1CON as shown in Table
8.18. These fields may not be programmed to one
of the reserved combinations, otherwise unpredictable results may occur.
A transmission will be performed by writing the
data to be transmitted into the associated Transmit
Buffer register S0TBUF or S1TBUF. In general,
any instruction or PEC data transfer operation
which uses these registers as destination will initiate a transmission. Note that S0TBUF and
S1TBUF are non bit-addressable WRITE ONLY
registers, and that only the number of data bits
which is determined by the selected operating
mode will actually be transmitted. This means that
the bits written to positions 9 through 15 of registers S0TBUF and S1TBUF are always insignifi-
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cant. After a transmission has been completed, the
transmit buffer registers are cleared to 0000h.
Data reception is enabled by the Receiver Enable
Bits S0REN and S1REN, respectively. After reception of a character has been completed, the received data and, if provided by the selected
operating mode, the received parity bit can be read
from the Receive Buffer registers S0RBUF or
S1RBUF of the associated serial channel. These
registers are non bit addressable READ ONLY
registers. Bits in the upper half of S0RBUF and
S1RBUF which are not significant for the selected
operating mode will be read as zeros.
Data reception is double-buffered, so that reception of a second character may already begin before the previously received character has been
read out of the receive buffer register. In all modes,
receive buffer overrun error detection can be selected through bits S0OEN and S1OEN. When enabled, the overrun error status flag S0OE or S1OE
and the error interrupt request flag S0EIR or S1EIR
for the respective channel will be set when the receive buffer register has not been read by the time
reception of a second character is complete. The
8 - Peripherals
Figure 8-39. Serial Channel Asynchronous Mode Block Diagram
previously received character in the receive buffer
is overwritten.
In each of the operating modes provided by the serial channels of the ST10x166, a loop-back option
can be selected through bits S0LB or S1LB. This
option allows to simultaneously receive the data
which are being transmitted by the ST10x166. To
increase the range of programmable baud rates for
the two serial interfaces, a baud rate selection option can be selected through S0BRS or S1BRS.
The current baud rate will be multiplied by 2/3. All
operating modes of the serial channels will be described in detail in the following subsections.
8.4.1.1 ASYNCHRONOUS OPERATION
In asynchronous operation, full-duplex communication is supported. The same operating mode and
baud rate is used for both transmission and reception. Each serial channel of the ST10x166 has two
pins associated with it which are alternate functions
of port 3 pins. RXD0/P3.11 and TXD0/P3.10 are
used by ASC0 in asynchronous operation as re-
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8 - Peripherals
Figure 8-40. 8-Bit Data Frame
Start
Bit
D0
(LSB)
D1
D2
D3
D4
D5
D6
D7
(parity)
1’st
Stop
Bit
2’nd
Stop
Bit
D3
D4
D5
D6
D7
D8
(paritywk-up)
1’st
Stop
Bit
Figure 8-41. 9-Bit Data Frame
Start
Bit
D0
(LSB)
D1
D2
ceive data input and transmit data output pins, respectively, while RXD1/P3.9 and TXD1/P3.8 are
used by ASC1. Figure 8.39 shows a block diagram
of a serial channel in the asynchronous mode of
operation.
Information Frames in Asynchronous Operation
Each information frame that can be transmitted or
received by the serial channels in asynchronous
operation consists of the following elements:
- One start bit
8-bit or 9-bit data frame, selected by bit
- An
fields S0M/S1M
- One or two stop bits, selected by bits
S0STP/S1STP
in
control
registers
S0CON/S1CON
Figure 8.40 shows an information frame with an 8bit data frame. D0 to D6 are data bits. D7 can be
configured as the 8th data bit (8-bit data mode) or
as the parity bit (7 -bit data +parity bit mode).
Figure 8.41 shows an information frame with a 9bit data frame. D0 to D7 are data bits. D8 can be
configured to either be the 9th data bit (9-bit data
mode), the parity bit (8-bit data + parity bit mode),
or the special wake-up bit used in multiprocessor
communication (8-bit data+wake-up bit mode).
Asynchronous Transmission
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2’nd
Stop
Bit
A transmission is initiated by writing the data to be
transmitted into the transmit data buffer register
S0TBUF or S1TBUF, respectively. However, a
transmission will only be performed if the corresponding baud rate generator run bit S0R= ‘1’ or
S1R= ‘1’ at the time the write operation to the
transmit buffer occurs. Transmission then starts at
the next overflow of the divide-by-16 counter (see
figure 8.39). First the start bit will be output on the
associated transmit data output pin TXD0 or TXD1,
followed by the selected number of data bits, LSB
first. In the two modes with parity bit generation,
the parity bit will automatically be generated by
hardware and inserted at the MSB position of the
data frame during transmission.
When one stop bit has been selected for the data
frame (S0STP= ‘0’ or S1STP= ‘0’), the corresponding transmit interrupt request flag S0TIR or S1TIR
will be set after the last bit of the data frame (including the parity or wake-up bit) has been sent out,
otherwise it will be set after the first stop bit has
been sent out.
When a write operation to the transmit data buffer
is performed while a transmission on the respective channel is in progress, the current transmission will be aborted, the associated output pin
TXD0 or TXD1 will go high, and a new character
frame will be sent with the data written to S0TBUF
8 - Peripherals
or S1TBUF at the next overflow of the divide-by-16
counter. Continuous data transfer can be achieved
by using the transmit interrupt request to reload the
transmit data buffer in the interrupt service routine
or by PEC data transfer.
In order to use pin TXD0/P3.10 or TXD1/P3.8 as
transmit data output, the corresponding port data
output latch P3.10 or P3.8 must be set to ‘1’, and
the pin must be configured as output by setting its
direction control bit DP3.10 or DP3.8 to ‘1’.
Asynchronous Reception
Reception is initiated on channel ASC0 by a detected 1-to-0 transition on pin RXD0 if bit S0R= ‘1’
and S0REN= ‘1’, and on ASC1 by a 1-to-0 transition on RXD1 if S1R= ‘1’ and S1REN= ‘1’. The receive data input pins RXD0 and RXD1 are
sampled at 16 times the rate of the selected baud
rate. The 7th, 8th, and 9th sample are examined by
the internal bit detectors. The effective bit value is
determined by a majority decision in order to avoid
erroneous results that may be caused by noise.
If the detected value is not a ‘0’ when the start bit is
sampled, the receive circuit is reset and waits for
the next 1-to-0 transition at pin RXD0 or RXD1, respectively. If the start bit proves valid, the receive
circuit continues sampling and shifts the incoming
data frame into the receive shift register.
When the last stop bit has been received, the contents of the receive shift register are transferred to
the receive data buffer register. Simultaneously,
the receive interrupt request flag S0RIR or S1RIR
is set after the 9th sample in the first stop bit time
slot when one stopbit has been programmed, or in
the second stop bit time slot when two stop bits are
programmed, regardless whether valid stop bits
have been received or not. The receive circuit then
waits for the next start bit (1-to-0 transition) at its
receive data input pin. Note that in the 8-bit
data+wake-up bit mode the data from receive shift
register will only be transferred into SORBUF/S1RBUF and the receive interrupt request
flag will only be set if the 9th data bit received was
a ‘1’.
When the receiver enable bit S0REN or S1REN of
a serial channel in asynchronous operation is reset
to ‘0’ while a reception is in progress, the current
reception will be completed, including generation
of the receive interrupt request and, in case of errors, generation of the error interrupt request and
setting of the error status flags which are described
in the following. Reception then stops for the affected channel, and further start bits at the receive
data input pin will be ignored.
In order to use pin RXD0/P3.11 or RXD1/P3.9 as
receive data input, the corresponding direction
control bit DP3.11 or DP3.9 must be set to ‘0’.
Hardware Error Detection Capabilities
To improve the safety of asynchronous data exchange, the serial channels of the ST10x166 provide selectable hardware error detection
capabilities. For each channel, three error status
flags in the channel‘s control register S0CON or
S1CON indicate whether an error has been detected during reception. Upon completion of a reception, the error interrupt request flag S0EIR or
S1EIR will be set simultaneously with the receive
interrupt request flag S0RIR or S1RIR if one or
more of the following conditions are met:
framing error detection enable bit S0FEN
- Iforthe
S1FEN is set and any of the expected stop
bits is not high, the framing error flag S0FE or
S1FE is set indicating that the error interrupt
request is due to a framing error.
parity error detection enable bit S0PEN
- Ifor the
S1PEN is set in the modes where a parity bit
is received, and the parity check on the received data bits proves false, the parity error
flag S0PE or S1PE is set indicating that the error interrupt request is due to a parity error.
- If the overrun error detection enable bit S0OEN
or S1OEN is set and the last character received was not read out of the receive buffer
by software or PEC transfer at the time reception of a new frame is complete, the overrun error flag S0OE or S1OE is set indicating that the
error interrupt request is due to an overrun error.
In the following subsections, specific characteristics of the individual operating modes for the
asynchronous communication are described in
more detail.
8.4.1.1.1 8-Bit Data Mode
This mode is selected by programming the mode
selection field S0M or S1M in register S0CON or
S1CON to ‘001b’. The data frame which will be
transmitted and/or received consists of 8 data bits.
After a reception, the upper byte of the receive
buffer register contains zero. The parity checking
function upon reception is disabled in this mode,
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8 - Peripherals
independent of the state of S0PEN and S1PEN.
The overrun and framing checks, however, can be
enabled.
8.4.1.1.2 7-Bit Data + Parity Bit Mode
This mode is selected by programming the respective mode selection field S0M or S1M to ‘011b’.
The data frame which will be transmitted and/or received consists of 7 data bits and a parity bit. All error checks may be enabled in this mode.
On transmission, the parity bit is automatically generated by hardware and inserted at the MSB position of the data frame. The parity bit is set to ‘1’ if
the modulo 2 sum of the 7 data bits is 1, otherwise
it is cleared (even parity).
On reception, the parity on the 7 data bits received
is generated by hardware. The result is then compared to the 8th bit received, which is the parity bit.
If the comparison proves false, both the parity error
flag and the error interrupt request flag for the respective serial channel are set, provided the parity
check has been enabled in the serial channel’s
control register. The actual parity bit received is
placed in the 8th bit of the receive data buffer register. The upper byte of the receive buffer register
is always zero in this mode.
8.4.1.1.3 9-Bit Data Mode
This mode is selected by programming the respective mode selection field S0M or S1M to ‘100b’.
The data frame which will be transmitted consists
of the lower 9 bits of the transmit buffer register.
On reception, all 9 data bits received are transferred from the receive shift register to the receive
buffer register, and the remaining 7 bits (9 through
15) of the receive buffer register are cleared to
zero. The parity checking function upon reception
is disabled in this mode, independent of the state
of S0PEN and S1PEN. The overrun and framing
checks, however, can be enabled.
8.4.1.1.4 8-Bit Data + Wake-Up Bit Mode
This is a special mode provided to facilitate multiprocessor communication, and it is selected by
programming the mode selection field S0M or S1M
to ‘101b’. The data frame which will be transmitted
includes the lower 9 bits of the transmit buffer register.
56/64

The operation in this mode is basically the same as
in the 9-bit data mode. However, on reception, if
the 9th data bit received is a ‘0’, the received data
are not transferred into the receive buffer registers
S0RBUF/S1RBUF and no receive interrupt request will be generated. A way to use this feature in
multiprocessor systems is as follows:
When the master processor wants to transmit a
block of data to one of several slaves, it first sends
out an address byte which identifies the target
slave. An address byte differs from a data byte in
that the additional 9th bit is a ‘1’ for an address byte
and a ‘0’ for a data byte. Operating in the 8-bit data
+ wake-up bit mode, no slave will be interrupted by
a data ‘byte’. An address ‘byte’, however, will interrupt all slaves, so that each slave can examine the
8 LSBs of the received character and see if it is being addressed. The addressed slave will switch its
operating mode to the 9-bit data mode (e.g by
clearing bit SxM.0, see table 8.18) and prepare to
receive the data bytes that will be coming. The
slaves that were not being addressed remain in the
8-bit data + wake-up bit mode, ignoring the incoming data bytes.
8.4.1.1.5 8-Bit Data+Parity Bit Mode
This mode is selected by programming the respective mode selection field S0M or S1M to ‘111b’.
The data frame which will be transmitted and/or received consists of 8 data bits and a parity bit. All error checks may be enabled in this mode.
On transmission, the parity bit (even parity) is automatically generated based on the 8 data bits and
inserted at the MSB position of the data frame.
On reception, the parity on the 8 data bits received
is generated and the result is compared to the 9th
bit received, which is the parity bit. If the compared
bits are different, both the parity error flag and the
error interrupt request flag are set, provided the
parity check has been enabled. The actual parity
bit received is placed in the 9th bit of the receive
data buffer register, and the remaining 7 bits (9
through 15) of the receive buffer register are
cleared to zero.
8.4.1.2 SYNCHRONOUS OPERATION
This operating mode of the serial channels ASC0
and ASC1 allows half-duplex communication and
is mainly provided for simple I/Oexpansion via shift
registers. 8 data bits are transmitted or received
synchronous to a shift clock generated by the inter-
8 - Peripherals
nal baud rate generator. The shift clock is only active as long as data bits are transmitted or received. Synchronous operation is selected by
programming the mode control field S0M or S1M of
a serial channel to ‘000b’. Figure 8.42 shows a
block diagram of a serial channel in synchronous
mode.
In synchronous operation, pin TXD0/P3.10 is used
by ASC0 to output the shift clock, while
RXD0/P3.11 either serves as transmit data input or
receive data output. Channel ASC1 uses pins
RXD1/P3.9 and TXD1/P3.8 for these purposes.
8.4.1.2.1 Synchronous Data Transmission
Figure 8-42. Serial Channel Synchronous Mode Block Diagram
57/64

8 - Peripherals
For data transmission, the transmit data buffer register S0TBUF (S1TBUF) is loaded with the byte to
be transmitted. If bit S0R = ‘1’ and S0REN = ‘0’ in
register S0CON (S1R = ‘1’ and S1REN = ‘0’ in
S1CON) at that time, the LSB of the transmit buffer
register will appear at pin RXD0 (RXD1) within 4
state times after this write operation has been executed. Subsequently, the contents of the transmit
buffer register are shifted out synchronous with the
clock at the corresponding shift clock output pin
TXD0 (TXD1). After the bit time for the 8th bit, both
pins TXD0 and RXD0 (TXD1 and RXD1) will go
high, the transmit interrupt request flag S0TIR
(S1TIR) is set, and serial data transmission stops.
While a synchronous data transmission is in progress, any write operation to the transmit buffer
register of this serial channel will abort the current
transmission and start a new transmit process.
When the receiver enable bit S0REN or S1REN is
set to ‘1’ during a transmission, unpredictable results may occur on the affected channel.
In order to configure TXD0/P3.10 or TXD1/P3.8 as
shift clock output, both the corresponding port output bit latch P3.10 or P3.8 and the direction control
bit DP3.10 or DP3.8 must be set to 1. Pin
RXD0/P3.11 or RXD1/P3.9 is each configured as
transmit data output by setting both P3.11 = ‘1’ and
DP3.11 = ‘1’, or P3.9 = ‘1’ and DP3.9 = ‘1’, respectively.
8.4.1.2.2 Synchronous Data Reception
Data reception is initiated by setting bit S0REN =
‘1’ (S1REN = ‘1’). If bit S0R = ‘1’ (S1R = ‘1’), the
data applied at pin RXD0 (RXD1) are clocked into
the receive shift register synchronous to the clock
which is output at pin TXD0 (TXD1). After the 8th
bit has been shifted in, the contents of the receive
shift register are transferred to the receive data
buffer S0RBUF (S1RBUF), the receive interrupt
request flag S0RIR (S1RIR) is set, the receiver enable bit S0REN (S1REN) is reset, and serial data
reception stops. RXD0/P3.11 or RXD1/P3.9 are
configured as receive data input by setting DP3.11
= ‘0’ or DP3.9 = ‘0’.
Once a reception is in progress on a serial channel,
resetting its receiver enable bit S0REN or S1REN
to ‘0’ by software has no effect. Writing to its transmit buffer register while a reception is in progress
has no effect on reception nor will it ever start a
transmission.
58/64

In synchronous operation, the low byte of the receive buffer register represents the received data,
while the high byte is always zero after synchronous reception. If a previously received byte has
not been read out of the receive buffer register at
the time reception of the next byte is complete,
both the error interrupt request flag S0EIR or
S1EIR and the overrun error status flag S0OE or
S1OE will be set, provided the overrun check has
been enabled by bit S0OEN or S1OEN.
8.4.1.2.3 Loop-back Mode
For testing purposes, a special loop-back mode is
provided which allows testing of each serial channel without using the alternate functions of the port
pins associated with this channel. While in loopback mode, instead of receiving data from the RX
D0 or RXD1 pin, the data which are transmitted are
simultaneously clocked into the receive shift register.
A transmission in loop-back mode is initiated for
channel ASC0 by a write operation to S0TBUF
when S0LB = ‘1’, S0REN = ‘1’ and S0R = ‘1’, and
for ASC1 by writing to S1TBUF with S1LB = ‘1’,
S1REN = ‘1’ and S1R = ‘1’. This feature isavailable
for all operating modes (asynchronous and synchronous) of the serial channels.
8.4.2 Baud Rates
Each of the serial channels of the ST10x166 has its
own dedicated 13-bit baud rate generator with 13bit reload capability, allowing independent baud
rate selection for each channel.
Both baud rate generators are 13-bit timers
clocked with the internal system clock divided by 2
(10MHz at 40MHz oscillator frequency). The timers are counting downwards and can be started or
stopped through the Baud Rate Generator Run
Bits S0R or S1R in register S0CON or S1CON.
Each underflow of a timer provides one clock pulse
to a serial channel. The timers are reloaded with
the value stored in their 13-bit reload register each
time they underflow. The baud rate selection bits
S0BRS and S1BRS allow the increase of the baud
rate by a coefficient of 2/3.
8 - Peripherals
Thus, the baud rate of a serial channel is determined by the oscillator frequency, the Baud Rate
Selection Bit, the reload value, and the mode
(asynchronous or synchronous) of the serial channel.
Registers S0BG and S1BG are the dual-function
Baud Rate Generator/Reload registers. Reading
S0BG or S1BG returns the contents of the timer,
while writing to S0BG or S1BG always updates the
reload register. When writing to S0BG or S1BG
(i.e., to the reload registers), the 3 upper bits 13
through 15 are insignificant, while reading S0BG or
S1BG (i.e., the timer registers) always returns zero
in bits 13 through 15.
An auto-reload of the timer with the contents of the
reload register is performed each time S0BG or
S1BG is written to. However, if S0R = ‘0’ or S1R =
‘0’ at the time the write operation to S0BG or S1BG
is performed, the timer will not be reloaded until the
first instruction cycle after S0R = ‘1’ or S1R = ‘1’.
8.4.2.1 ASYNCHRONOUS MODE BAUD RATES
In asynchronous operation, the baud rate generators provide a clock with 16 times the rate of the
established baud rate. The reason for this is that
on reception every bit frame is sampled 16 times.
Thus, the baud rates Basync0 and Basync1 for the
serial channels ASC0 and ASC1 in asynchronous
operation are determined by the following formulas:
Basync0 =
Basync1 =
fOSC
64 × (<S0BRL> + 1)
fOSC
64 × (<S1BRL> + 1)
When SxBRS = ‘1’, these formulas are:
fOSC
Basync0 = 2
3 64 × (<S0BRL> + 1)
fOSC
Basync1 = 2
3 64 × (<S1BRL> + 1)
<S0BRL> and <S1BRL> represent the contents of
the reload registers, taken as unsigned 13-bit integers.
Table 8.19 lists various commonly used baud rates
together with the required reload value. The maxi-
Table 8-19. Asynchronous Modes Baud Rates (Baud Rate SxBRS=0)
Baud Rate
fosc
Reload Value
625
KBaud
40 MHz
0000h
19.2
KBaud
39.3216 MHz
001Fh
9600
Baud
39.3216 MHz
003Fh
4800
Baud
39.3216 MHz
007Fh
2400
Baud
39.3216 MHz
00FFh
1200
Baud
39.3216 MHz
01FFh
600
Baud
39.3216 MHz
03FFh
75
Baud
39.3216 MHz
1FFFh
59/64

8 - Peripherals
Serial Channel Interrupt Control Registers
Reset Value: 0000h
S0TIC (FF6Ch / B6h)
7
6
S0TIR
S0TIE
5
4
3
2
1
ILVL
0
GLVL
S0RIC (FF6Eh / B7h)
7
6
S0RIR
S0RIE
5
4
3
2
1
ILVL
0
GLVL
mum baud rate that can be achieved for the asynchronous modes when using a 40MHz oscillator is
625KBaud.
8.4.2.2 SYNCHRONOUS MODE BAUD RATES
In the synchronous mode, the baud rate generators provide 4 times the rate of the desired baud
rate. Therefore, the underflow rate coming from
the baud rate timers is additionally divided by four.
The maximum baud rate that can be achieved in
synchronous operation when using a 40MHz oscillator is 2.5 MBaud. Generally, the baud rates
Bsync0 and Bsync1 for the serial channels in synchronous operation are determined as follows:
Basync0 =
fOSC
16 × (<S0BRL> + 1)
Basync1 =
fOSC
16 × (<S1BRL> + 1)
S0EIC (FF70h / B8h)
7
6
S0EIR
S0EIE
5
4
3
2
1
ILVL
0
GLVL
When SxBRS = ‘1’, these formulas are:
S1TIC (FF72h / B9h)
7
6
S1TIR
S1TIE
5
4
3
2
1
ILVL
0
GLVL
S1RIC (FF74h / BAh)
7
6
S1RIR
S1RIE
5
4
3
2
1
ILVL
0
GLVL
S1EIC (FF76h / BBh)
7
6
S1EIR
S1EIE
5
4
3
ILVL
2
1
0
GLVL
60/64

fOSC
Basync0 = 2
3 16 × (<S0BRL> + 1)
8 - Peripherals
fOSC
Basync1 = 2
3 16 × (<S1BRL> + 1)
8.4.3 Serial Channels Interrupt Control
Three bit addressable interrupt control registers
are provided for each serial channel. Registers
S0TIC and S1TIC control the transmit interrupt,
registers S0RIC and S1RIC control the receive interrupt, and registers S0EIC and S1EIC control the
error interrupt of serial channel ASC0 and ASC1,
respectively. Each interrupt source also has its
own dedicated interrupt vector. S0TINT is the
transmit interrupt vector, S0RINT is the receive interrupt vector, and S0EINT is the error interrupt
vector for channel ASC0, while S1TINT, S1RINT,
and S1EINT are the corresponding interrupt vectors for ASC1.
The cause of an error interrupt request (framing,
parity, overrun error) can be identified by the error
status flags in control registers S0CON and
S1CON. Note that, unlike the error interrupt request flags S0EIR or S1EIR, the error status flags
S0FE/S0PE/S0OE or S1FE/S1PE/S1OE are not
reset automatically upon entry into the error inter-
Figure 8-43. Watchdog Timer Block Diagram
Figure 8-44. SFRs and Reset Indication Pin Associated with the Watchdog Timer
Reset Indication Pin
RSTOUT
Data Registers
Control Registers
WDT
WDTCON
Watchdog
Timer Register
(read only)
Watchdog
Timer Control
Register
VR0E1640
61/64

8 - Peripherals
rupt service routine, but must be cleared by software.
The organization of the interrupt control registers
associated with the serial channels is shown here.
For more details on interrupts refer to chapter 7.
8.5 WATCHDOG TIMER (WDT)
To allow recovery from software or hardware failure, a Watchdog Timer has been provided in the
ST10x166. If the software fails to service this timer
before an overflow occurs, an internal hardware reset will be initiated. This internal reset will also pull
the RSTOUT pin low (see chapter 11). When the
software has been designed to service the Watchdog Timer before it overflows, the Watchdog Timer
times out if the program does not progress properly. The Watchdog Timer will also time out if a
software error was due to hardware related failures. This prevents the controller from malfunctioning for longer than a user-specified time.
The Watchdog Timer is a 16-bit up counter which
can be clocked with either the oscillator frequency
(fOSC) divided by 4 or with fOSC /256. The upper 8
bits of the Watchdog Timer can be preset to a userprogrammable value in order to vary the watchdog
time. Figure 8.43 shows a block diagram of the
Watchdog Timer, while Figure 8.44 shows the
SFRs and the reset indication pin RSTOUT which
are associated with the Watchdog Timer.
Watchdog Operation
The current count value of the Watchdog Timer is
contained in the Watchdog Timer Register WDT,
which is a non-bit-addressable READ-ONLY regis-
62/64

ter. The operation of the Watchdog Timer is controlled by the bit-addressable Watchdog Timer
Control Register WDTCON shown hereafter.
After any software-, external hardware-, or Watchdog Timer reset, the Watchdog Timer is enabled
and starts counting up from 0000h with the frequency fOSC/4. The Watchdog Timer can be disabled via the instruction DISWDT (Disable
Watchdog Timer). Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during the time between a reset and
execution of either the EINIT (End of Initialization)
or the SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions disables
the execution of DISWDT.
When the Watchdog Timer is not disabled via instruction DISWDT, it will continue counting up,
even during Idle Mode. If it is not serviced via the
instruction SRVWDT by the time the count reaches
FFFFh, the Watchdog Timer will overflow and
cause an internal reset. This reset will pull the external reset indication pin RSTOUT low. It differs
from a software or external hardware reset in that
bit WDTR (Watchdog Timer Reset Indication flag)
of register WDTCON will be set. A hardware reset
or the SRVWDT instruction will clear this bit. Bit
WDTR can then be examined by software in order
to determine the cause of the reset.
To prevent the Watchdog Timer from overflowing,
it must be serviced periodically by the user software. The Watchdog Timer is serviced with the instruction SRVWDT, which is a protected 32-bit
instruction. Servicing the Watchdog Timer clears
the low byte and reloads the high byte of the
8 - Peripherals
Table 8-20. Watchdog Time Ranges
WDTREL
WDTCON (FFAEh / D7h)
Watchdog Timer Control Register
Reset Value: 0000h
Prescaler for fosc
4 (WDTIN = 0)
256 (WDTIN = 1)
FFh
25.6µs
1.6ms
00h
6.55ms
419ms
15
14
13
12
11
10
9
8
2
1
0
WDTR
WDTIN
WDTREL
7
6
5
4
R
3
b15 to b8 = WDTREL: Reload Value for the high
byte of the Watchog Timer.
b7 to b2 = R: Reserved.
b1 = WDTR: Watchdog Timer Reset. Indication
flag, Read only bit, this bit is set by watchdog
overflow. It is cleared by hardware reset or by the
SRVWDT instruction.
b0 = WDTIN: Watchdog Timer Input Frequency
Selection.
WDTIN = 0: fosc/4
WDTIN = 1: fosc/256.
63/64

8 - Peripherals
NOTES:
64/64


CHAPTER 9
EXTERNAL BUS INTERFACE
9. EXTERNAL BUS INTERFACE
The ST10x166 has been architected tobe placed
For this mode, Port 0 is used as interface to the
in a number of different applications and system multiplexed external address/data bus. As long as
designs. In order to meet the needs of designs memory segmentation is not disabled, Port 4 is adwhere more memory is required than provided
is
ditionallyused as an output for the two most signifion the chip, a number of external bus configurationcant bits of the required 18-bit addresses.
modes are supported. These are listed below:
16/18-Bit Address, 16-Bit Data, Non-MultiSingle Chip Mode
plexed Bus
No external bus is configured in this mode. Select- This mode is also provided for accesses to a word
ing this mode during reset implies that program organizedexternal memory. However, two sepaexecution starts from the internal program mem- rate buses are used for the sixteen least significant
ory. No external memory can be accessed as long address bits and the data word. Thus, addresses
as the ST10x166 is in this mode. However, the sin- and data do not have to be time-multiplexed. For
gle chip mode can be left to enter any of the
ollow
f this mode, Port 0 is used as an interface to the exing external bus configuration modes by simplyternal data bus and Port 1 is used as an interface to
reprogramming the System Configuration (SY- the external address bus. As long as memory segSCON) register.
mentation is not disabled, Port 4 is addit
ionally
used
as
an
output
for
the
two
most
significant
bits
16/18-Bit Address, 8-Bit Data, Multiplexed Bus
of the required 18-bit addresses.
This mode is provided for accesses to a byte-organized external memory. The eight least signifi- 16/18-Bit Address, 8-Bit Data, Non-Multiplexed
cant bits of the address and the data byte are Bus
time-multiplexed onthe lower portion of the word- This mode is provided for accesses to a byte-orwide external bus. For this mode, Port 0 is used as ganized external memory. However, two separate
interface to the m
ultiplexedexternal address/data buses are used for the eight least significant bits of
bus. As long as memory segmentation is not dis- the address and the data byte. For this mode, Port
abled, Port 4 is additionally used as an output for 0 is used as an interface to the 8-bit external data
the two most significant bits of the required 18-bitbus and Port 1 is used as an interface to the 16-bit
addresses.
external address bus. No time-mult
iplexingand no
additionaladdress
latch
is
required
in this bus
16/18-Bit Address, 16-Bit Data, Multiplexed
mode.
If
segmentation
is
enabled,
Port
4 is addiBus
tionally used to output the two most significant bits
This mode is provided for accesses to a word-or- of the required 18-bit address.
ganized external memory. The sixteen least significant address bits and the data word are Basically, the ST10x166 supports an 18-bit adtime-multiplexed on the word-wide external bus. dress space. The 16-bit address mode refers to the
case of segmentation being disabled.
1/20
9 - External Bus Interface
Regardless of which external bus mode is se- 9.1 EXTERNAL BUS CONFIGURATION
lected, accesses to addresses from ‘0FA00h’ DURING RESET
through ‘0FFFFh’ are performed internally. In case
of initializingthe ST10166 to the singlechip mode,
Any of the initial external bus configuration modes
internal ROM accesses become basically
enabled,
is selected by means of three External Bus Conand thus accesses to addresses from
‘00000h’
figuration pins (EBC0, EBC1 and
BUSACT). For
through ‘07FFFh’ are performed internally, too. this, the input values on these dedicated pins are
Otherwise, any access to addresses within the first sampled during reset and copied into the BTYP bit
32Kbytes would be performed externally. In any field and the BUSACT bit of the SYSCON register
case, accesses to addresses from‘08000h’
as follows:
through ‘0F9FFh’, or in any segment other than SYSCON.7
= EBC1
zero, would be tried to be made externally. Note,
= EBC0
however, that external memory locations higher SYSCON.6
than ‘0FFFFh’ cannot be accessed if the non-seg- SYSCON.10 = BUSACT
mented memory mode or the single chip mode is Table 9.1 shows the association between the initial
selected. This also
appliesto the ST10F166 device BUSACT, EBC0 and EBC1 input pin values, the
and its Flash memory. For more details about the correspondingexternal bus configuration modes
ST10x166’s memory organization see chapter 3. and the ports used as interface to the external address and/or data bus(es):
Table 9-1. Initial External Bus Configuration During Reset
BUSACT
EBC1
EBC0
Ports used for
External Bus Configuration
A17, A16
A15..A0
D15..D0
1
0
0
Single Chip Mode
No External Bus
-
-
-
1
0
1
Reserved
No External Bus
-
-
-
1
1
0
Reserved
No External Bus
-
-
-
1
1
1
Reserved
No External Bus
-
-
-
0
0
0
18-Bit Address/8-Bit Data
Non-Multiplexed
No Internal ROM
P4
P1
P0(low)
0
0
1
18-Bit Address/8-Bit Data
Time-Multiplexed
No Internal ROM
P4
P0
P0(low)
0
1
0
18-Bit Address/16-Bit Data
Time-multiplexed
No Internal ROM
P4
P0
P0
0
1
1
18-Bit Address/16-Bit Data
Non-Multiplexed
No Internal ROM
P4
P1
P0
2/20

9 - External Bus Interface
As just mentioned, the BUSACT bit and the BTYP SGTDIS bit in the SYSCON register is set to ‘1’. If
field in the SYSCON register are initialized during one of the two 16-bit Data Bus modes is selected
reset. This selected configuration can be modified during reset, the function of the Byte High
Enable
during init
ialization,but ,after the EINIT instruction, pin (BHE) becomes alsoenabled and stays enonly the external bus configuration can be modifiedabled until the BYTDIS bit in the SYSCON register
at any time. Any changes of the configuration is set to ‘1’. This ensures that the External Bus
which affect the on-chip ROM or Flash Memory Controller can properly access the initialization
can only bemade until the endof theinitialization
code in any case. Many of the external bus transfer
instruction (e.g. the mapping of the ROM to seg- characteristicsare controlled via the SYSCON regment 1, the ROMdisabled).
ister in addition. Software programming of the SYTable 9.2 shows all thepossibilit
y of configuration. SCON register allows the user to vary particular
timing parameters in a wide range. During reset, all
If the ST10x166 is initialized to an external bus of the external bus timing parameters areialized
init
configuration mode other than the single chip in a way that even very slow external memories
mode, Port 4 pins are used as an output for the can be accessed properly. For more details on the
most significant address pins (A17 and A16). This programmable external bus timing parameters see
alternate function of Port 4 stay
s enabled until the
section 9.7
Table 9-2. Action/Function Selected At:
BUSACT
BTYP
Reset
During Init
0
After Init
00
ROM enable
Segment 0
No ext. Bus
ROM enable
Segment 0
No action
0
01
(reserved)
ROM enable
Segment 1
No action
0
10
(reserved)
Disable ROM
No action
0
11
(reserved)
Disable ext. Bus
No action
1
00
8-Bit Non-Mux
No ROM
8-Bit Non-Mux
8-But Non-Mux
1
01
8-Bit-Mux
No ROM
8-Bit Mux
8-Bit Mux
1
10
16-Bit-Mux
No ROM
16-Bit-Mux
16-Bit-Mux
1
11
16-Bit Non-Mux
No ROM
16-Bit Non-Mux
16-Bit-Non-Mux
3/20

9 - External Bus Interface
9.2 SINGLE CHIP MODE
BUSACT bit in the SYSCON register (see section 5.3.1.1). In this case, an external memory can
The single chip mode must be selected whenever be accessed and the entire on chip memory reprogram execution shall start from the on-chip pro-mains accessible.
gram memory. If this mode has been selected
once during reset, internal accesses stay
globally
enabled. During reset, the Instruction Pointer (IP) 9.3 16/18-BIT ADDRESS, 8-BIT DATA,
and the Code Segment Pointer (CSP) registers are NON-MULTIPLEXED BUS
both cleared, and thus program execution begins
This external bus mode must be selected if a byte
at the internal ROM location
00000h.
external memory shall be connected to the
As shown in figure 9.1, Port 0, Port 1 and Port 4 ST10x166. As shown in figure 9.2, Port 1 is used
(A17 and A16) can be used as general purpose I/O as a word address output while the lower half of
registers.
Port 0 is used as separated byte data output. Since
Note that any intended access to a location within two independent buses are used, no time multithe external memorypace
s
will caus
e a hardware
plexing and noadditionaladdress latch isrequired
trap to occur if the controller is in the single chipin this case. As long as memory segmentation is
mode.
not disabled, Port 4 is
additionallyused as an outthe
For applications where the on-chip program mem- put for the two most significant bits of required
18-bit
address.
The
upper
half
of
Port
0
can not be
ory is not sufficient, the single chip mode can be
used
for
general
purpose
I/O.
left by simply modifying the BTYP bit field and the
Figure 9-2. 16/18 Bit Address, 8-Bit Data,
Non-Multiplexed Bus
Figure 9-1. Single Chip Mode
4/20

9 - External Bus Interface
9.4 16/18-BIT ADDRESS, 8-BIT DATA,
MULTIPLEXED BUS
dresses. Port 1 can be used for general purpose
I/O functions.
Whenever a word is to be accessed externally in
This external bus mode must be selected if a byte- this mode, the EBC generates two consecutive adwide external memory shall be connected to the dresses and adjusts incoming bytes into words, or
ST10x166.
outgoing wordsinto bytes. The low byte of a word
As shown in the figure 9.3, the lower address byte is accessed first, then the high byte access is perand the data byte are time-multiplexed on the formed.
lower portion of the
word-wideexternal bus. There- The process of transferring two bytes sequentially
fore, an external byte-wide address latch is re- over the external bus for any word access, causes
quired for the eight least significant address bits.the operation of the processor to slow down. In
An Address Latch n
Eable (ALE) signal is gener- fact, this mode is not as fast as the other external
ated by the on-chip External Bus Controller (EBC) memory access modes. However, there is a cost
to signify a valid address beingailable
av
on Port 0.
advantage since inexpensive byte-wide memories
As long as memory segmentation is not disabled, can be used.
Port 4 isadditionallyused as an output for the two
most significant bits of the required 18-bit ad- A detailed application example for this external bus
configuration mode is shownappendix‘C’.
in
Figure 9-3. 16/18-Bit Address, 8-Bit Data, Multiplexed Bus
5/20

9 - External Bus Interface
9.5 16/18-BIT ADDRESS, 16-BIT DATA,
MULTIPLEXED BUS
performance. It is faster than the 8-bit data bus
mode because a memory does not need to be accessed twice in order to fetch a word-wide value.
This external bus mode can be selected if a word- This advantage, however, is not totally utilized
wide external memory is connected to the since addresses and data are time multiplexed on
ST10x166.
the external bus. This time mult
iplexingreduces
bandwidthof the bus.
As shown in the figure 9.4, Port 0 is used as a the overall possible
word-wide output for both the address and data This external bus configuration mode can also be
which are time-m
ultiplexedon the word-wideexselected if the wor
d-organized external memory is
ternal bus. Therefore, an external word wide ad- implemented by two separate 8-bit-wide memodress latch is required. The least significant ries. These two memories can be accessed both
address bit A0 is normally not significant when ac-wordwise, coupled together as one
word-wide
cessing wordorganized memories. An Address memory,and individually as twoindependentbyte
Latch Enable(ALE) signal is generated by the on- memories.
chip External Bus Controller (EBC) to signify a For the case where the two byte-wide memories
valid address being
availableon Port 0. As long as are to be accessed only wordwise, the addressing
memory segmentation is not disabled, Port 4 is ad- scheme is the same as if only one 16-bit wide
ditionallyused as an output for the two most signifi- memory is used. For the case where the two
cant bits of the required 18-bit addresses. Port 1 memories are also to be accessed as indecan be used for general purpose I/O functions. pendentlysuitable byte wide memories, the ExterCompared with the other external bus configura- nal Bus Controller (EBC) must be
enabledto use
tion modes, the 16/18-bit Address, 16 bit Data, the function of the Byte High Enable pin as deMultiplexed Bus mode provides a middle level of scribed in theollowing.
f
Figure 9-4. 16/18-Bit Address, 16-Bit Data, Bus Multiplexed Bus (Word-Wide Memories)
6/20

9 - External Bus Interface
Firstly, the Byte Disable bit (BYTDIS) in the SY- and the A0 address output pin must be connected
SCON register must contain a ‘0’ (this is the default to the chip select input of the memory at the low
after system reset), and secondly a 16-bit Data byte location, as shown in figure 9.5.
Bus mode must have been configured. If these Detailed application examples for the just menpresuppos
itions are fulfilled, the Byte High
Enable
tioned external bus and memory configurations are
(BHE) function which is an alternate active low out- shown inappendix ‘C’.
put function of Port 3 Pin 12 (P3.12) becomes enabled, and will be implicitly used by the External
Bus Controller (EBC) whenever an external mem- Table 9-3. Word or Byte Access to Two
ory access is performed.
Coupled Byte-Wide Memories
Table 9.3 shows which
BHE output is generated by
BHE
A0
Type of Access
the EBC dependent on the least significant address bit (A0) and the type of access desired for
Both byte memories are
the two coupled external byte memories.
0
0
accessed together for word
Note that the EBC places any byte value to be writtransfers
ten to the external memory on both the upper byte
portion and the lower byte portion of the 16-bit exOnly the high byte memory is
0
1
ternal data bus. However, the byte will only be
accessed for byte transfers
stored in that byte memory which is specified by A0
Only the low byte memory is
and BHE.
1
0
accessed for byte transfers
To be correctly used as just described, the
BHE
output pin must be connected to the chip select in1
1
Not used
put (CS) of the memory at the high byte location,
Figure 9-5. 16/18-Bit Address, 16-Bit Data, Bus Multiplexed (Byte-Wide Memories)
7/20

9 - External Bus Interface
9.6 16/18-BIT ADDRESS, 16-BIT DATA,
NON-MULTIPLEXED BUS
twice in order to fetch a word-wide value, and it
also saves theadditionaltime delay caused by address and data mult
iplexing.
This external bus mode can be selected if the As shown in figure 9.7, this external bus configuraST10x166 is to be used incollaborat
ion with a
tion mode can also be selected if the word-organword-wide external memory.
ized external memory is implemented by two
As shown in figure 9.6, Port 1 is used as a word- separate 8-bit wide memory devices. These two
wide address output and Port 0 is used as sepa- memories can be accessed both wordwise, courated word-wide data output. The least significant pled together as one word-wide memory, and indiaddress bit A0 is normally not used when access- vidually as twoindependentbyte memories.
ing word-organized memories. Since two inde- For the case where the two memories are acpendent buses are used, no time-mult
iplexingand
cessed coupled together as one word-wide memno additionaladdress latch is required in this case. ory, the addressing scheme is the same as if only
As long as memory segmentation is not disabled, one 16-bit wide memory was used. For the case
Port 4 isadditionallyused as an output for the two where the memories are also accessed as indemost significant bits of the required 18-bit ad- pendently suitable byte-wide memories, the Exterdresses.
nal Bus Controller EBC must be
enabledto use the
Compared with the other external bus configura- function of the Byte Highnable
E
pin B
( HE) as detion modes, the 16/18-bit Address, 16 bit Data, scribed in the previous section 9.5.
Non-MultiplexedBus mode provides the highest Detailed applicationexamples for the just menlevel of performance. It is faster than other modes tioned external bus and memory configuration are
because it does not have to access the memory shown inappendix‘C’.
Figure 9-6. 16/18-Bit Address, 16-Bit Data, Non-Multiplexed Bus (Word-Wide Memories)
8/20

9 - External Bus Interface
Figure 9-7. 16/18-Bit Address, 16-Bit Data, Non-Multiplexed Bus (Word-Wide Memories)
A memory access is initiated by the controller by
placing an address on the bus and then
generating
the Address Latch Enable signal (ALE). This signal
With regard to timing characteristics, there are ba- triggers an external latch to capture the address.
sically two types of external buses which can be After a period of time during which the address
configured. These are multiplexed and non-multi- must have been latched externally, the address is
plexed buses. Transfer characteristics for these removed from the bus. Note that in the 16/18-bit
two types are described in detail in the following. Address, 8-bit Data, Multiplexed bus mode, only
the lower eight bits of Port 0 are multiplexed on the
external bus betw
een address output and data in9.7.1 Multiplexed Bus Transfer Characteristics
put/output, while the upper eight bits of Port 0 conhroughout
t
In both Multiplexed Bus modes, the resource ‘Ex- tinue to output address bits A15 to A8
ternal Bus’ is time-shared between addresses and the entire memory access cycle. Note also that
data. Figure 9.8 shows the timing sequence of a Port 4 is never time-multiplexed and continues to
memory read and memory write access via a mul- output the two most significant (segment) address
bits A17 and A16.
tiplexed bus.
9.7 EXTERNAL BUS TRANSFER
CHARACTERISTICS
9/20

9 - External Bus Interface
Figure 9-8. Multiplexed External Bu
s Accesses
the bus and the active low memory write signal
9.7.1.1 MULTIPLEXED BUS MEMORY READS
At the same time when the address is removed (WR) is appliedto the memory. This enables the
from the bus which is then tri-stated again, the ac- memory to store the data from the bus onto the adtive low memory read signalRD)
( is applied to the dressed location. After a period of time which is dememory. Thisenablesthe memory to drive data termined by the access time of the memory, the
onto the bus. After a period of time which is deter- data become valid in the addressed memory locamined by the access time of the memory, data be- tion. Then, the controller removes its memory write
signal. The data remain valid on the bus until the
come valid on the bus.
next memory access cycle is started.
Then, the controller latches the valid data from the
bus and removes its memory read signal. This
causes the memory to remove its data from the 9.7.2 Non-Multiplexed Bus Transfer
Characteristics
bus which is then tri-stated again.
In the Non-Multiplexed Bus mode, there are separate buses for both the address and the data. Fig9.7.1.2 MULTIPLEXED BUS MEMORY WRITES
ure 9.9 shows the timing sequence of a memory
After the address has been stored externally and read and memory write access via a non-multiremoved fromhe
t bus again, data are dr
iven onto
plexed bus.
10/20

9 - External Bus Interface
Figure 9-9. Non-Multiplexed External Bu
s Access
9.7.2.1 NON-MULTIPLEXED BUS MEMORY READS
9.7.2.2 NON-MULTIPLEXED BUS MEMORY WRITES
A memory read access is initiated by the controller A memory write access is initiated by the controller
by placing an address on the address bus. This ad- by placing an address on the address bus. This address stays valid on the bus until the next memory dress stays valid on the bus until the next memory
access cycle is started. After a fixed period of time, access cycle is started. After a fixed period of time,
the active low memory read signal
RD)
( isapplied
the controller drives its data onto the data bus and
to the memory. This enables the memory to drive applies the active low memory write signal
WR)
( to
data onto the data bus. After a period of time which the memory. This enables the memory to store the
is determined by the access time of the memory, data from the data bus onto the addressed locadata become valid on the data bus. Then, the con- tion. After a period of time which is determined by
troller latches the valid data from the data bus and the access time of the memory, the data become
removes its memory read signal. This causes the valid in the addressed memory location. Then, the
memory to remove its data from the data bus which controller removes its memory write signal and
is then tri-stated again. Simult
aneouslywith the reputs the address for the next memory access on
moval of theRD signal, the controller puts the ad- the address bus if a subsequent external memory
dress for the next memory access on the address access is required. The data remain valid on the
bus if a subsequent external memory access is re- data bus until the next memory access cycle is
quired.
started.
11/20

9 - External Bus Interface
9.8 USER SELECTABLE BUS
CHARACTERISTICS
If an external memory is too slow, the controller
must slow down in order to allow the memory to
keep pace. The ST10x166 can be slowed down for
Important timing characteristics of the external busexternal memory accesses by introducing wait
interface,includingthe Memory Cycle Time, the states during the access. During these Memory
Memory Tri-State Time, the Read/Write Delay Cycle Time wait states, the CPU is idle. Figure 9.11
Time and the Address Latch Enable length have shows when Memory Cycle Time wait states are
been made user programmable to allow adapting a introduced during the memory access.
wide range of different external bus and memory The ST10x166 allows the user to program Memory
configurationswith different types of memories. Cycle Time wait states in increments of half a maNote that internal memory access time are not ex- chine cycle within a range from 0 to 15 (default aftended by external waitstates.
ter reset). The Memory Cycle Time wait states can
Examples, tables and formulas showing the calcu- be configured via software by modifying the MCTC
lation ofthe user selectablebus characteristicscanfield of the SYSCON register, as shown in table
be found in theappendix,section ‘C’.
9.4. One Memory Cycle Time Wait State requires
half a machine cycle (50ns atOSC
f = 40MHz).
By means of the Memory Cycle Time Wait States,
9.8.1 Programmable Memory Cycle Time
the Memory Cycle Time can be varied as follows:
The ST10x166 allows the user to adjust the controller’s Memory Access Cycle Time to the Memory MultiplexedBus Modes:
Cycle Time of the external memory being used. 150ns - 900ns (at Of SC = 40MHz)
The Memory Cycle Time is the total
ime
t required
Non-Multiplexed Bus Mode:
to perform a memory access. It represents the period of time from the moment when the controller 100ns - 850ns (at Of SC = 40MHz)
puts an address on the bus for the first time until These programmable Memory Cycle Time wait
the next external memory access can be started at states can be specified for all of the external bus
the earliest. As shown in figure 9.10, the Memory configuration modes.
Cycle Time determines how fast the memory can
be accessed in general.
9.8.2 Programmable Memory Tri-State Time
Table 9-4. MCTC Encoding of the Memory Cycle Time Wait States
MCTC
Number of
Wait States
Additional Delay
(at f osc = 40MHz) [ns]
0
15
750
1
14
700
1
0
13
650
0
1
1
12
600
1
0
0
11
550
0
1
0
1
10
500
0
1
1
0
9
450
0
1
1
1
8
400
1
0
0
0
7
350
1
0
0
1
6
300
1
0
1
0
5
250
1
0
1
1
4
200
1
1
0
0
3
150
1
1
0
1
2
100
1
1
1
0
1
50
1
1
1
1
0
0
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
12/20

9 - External Bus Interface
Figure 9-10. Memory Cycle Time
Figure 9-11. Memory Cycle Time Wait States
13/20

9 - External Bus Interface
The ST10x166 allows the user to adjust the time The ST10x166 allows the user to program 0 or 1
between twosubsequentmemory accesses to ac- (default after reset) Memory Tri-State Time wait
count for the Tri-State Time of the external memory state by means of the MTTC bit in the SYSCON
being used. The Tri-State time is the time
required
register as shown in table 9.5. One Memory Triby the memory to release the bus once the mem- State Time Wait State requires half a machine cyory read R
( D) signal has been deasserted. As cle (50ns at O
f SC = 40MHz).
shown in figure 9.12, the Memory Tri-State Time
determines how quickly one memory access can Table 9-5. Encoding of the Memory Tri-State
follow another.
Time Wait State
If an external memory is too slow in releasing the
bus after a memory read access, the controller
MTTC
Wait States
must wait for putting the next address on the bus
0
Introduce One Wait State
until the bus is tri-stated again. Therefore, an additional Memory Tri-State Time wait state must be in1
Introduce No Wait States
troduced before the next memory access. The
CPU is not idle during a Memory Tri-State Time
wait state. Thus, CPU operations will only be These programmable Memory Tri-State Time wait
slowed down if asubsequentexternal instruction states can be specified for all of the external bus
or data fetch operation is required during
the next
configuration modes. Note, however, that one iminstruction cycle. Figure 9.13 shows when a Mem- plicit Memory Tri-State wait state is automatically
ory Tri-State Time wait state is introduced during added for both multiplexed external bus configurathe external memory accesses.
tion modes.
14/20

9 - External Bus Interface
Figure 9-12. Memory Tri-State Time
Figure 9-13. Memory Tri-State Time Wait States
15/20

9 - External Bus Interface
The ST10x166 allows the user to disable enable
or
9.8.3 Read/Write Signal Delay
(default
after
reset)
Memory
Read/Write
ignal
S
The ST10x166 allows the user to adjust the timing
Delays
by
means
of
the
RWDC
bit
in
the
SYSCON
of the data read and write output signals to account
register as shown in table 9.6. One Read/Write
for timing requirements of external
peripherals.As
shown in figur
e 9.14, the Read/Write Delay repre- Signal Delay requires a quarter of a machine cycle
sents the period of time between the falling edge of (25ns at fOSC = 40MHz).
the Address Latch Enable (ALE) signal and the fallTable 9-6. RWDC Encoding of The Read/Write
ing edge of the readRD)
( or write W
( R) signal. If no
additionalRead/Write Delay is programmed, the Signal Delay
falling edges of the ALE,
WR and RD signals are
coincident. With the delay programmed, the falling
RWDC
ALE-RD/WR Delays
edge of the ALE signal leads the falling edges of
0
Enabled
the RD orWR signal by a quarter of a machine cycle. An additional Read/Write Delay does not ex1
Disabled
tend the Memory Cycle Time, and thus it does not
slow down the controller in general.
These programmable Read/Write Signal Delays
can be specified for all of the external bus configuration modes.
Figure 9-14. Memory Read/Write Signal Delay
16/20

9 - External Bus Interface
9.8.4 ALE signal delay
The ST10x166 allows the user to adjust the Ad- must be lengthened. This feature is provided by
dress Latch Enable signal to account for the ad- the ST10x166 with the ALECTL1 bit of BUSCON1
dress setup and hold time of the external register.
components being used. The Address Latch En- When ALECTL1 is set to “1”, any access within the
able signal is required to trigger an external latch address range defined by the ADDRSEL1 register,
which captures the address. Then after a period of is lengthened by one CL
T (TCL= 25ns at 20MHz
time, during which the address has been latched, CPU clock), and the address hold time after ALE is
the address is removed from the ST
10x166’sbus.
lengthenedby one TCL.
If the external component need a longer address Figure 9.15 illustrates the bus cycle timing when
setup and hold times, the ST10x166’s ALE pulse ALECTL1 is set.
Figure 9-15. Timing With ALE Lengthening(Multiplexed Bus)
17/20

9 - External Bus Interface
9.8.5 Switching between the Bus Modes.
As mentioned before, it is possible to switch from
With the features of the ST10x166, the different an 8-bit data bus to a 16-bit data bus and vice
m
anda
bus modes and the BUSCON1 register, it is possi- versa, and to switch between a ultiplexed
ble to switch the bus characteristics ‘on-the-fly’.non-multiplexed bus. There exists one condition,
One can change the number of wait states, switch however, which presents a special case. When
from a multiplexedbus to a non-multiplexed bus or switching from a non-multiplexed bus to a multivice versa, or can use the READY function in a cer- plexed bus, an extra hold state is required due to
tain address range while operating without READY timing constraints. In addition, Port 1, which is
in theremainingaddress range. This can either be used for the address bus, continues to output the
done by using the SYSCON and BUSCON1 regis- address, although the address will also appear at
ters with different parameters in certain address Port 0, time multiplexed with the data. This has the
ranges, or by reprogramming the SYSCON or advantage, that the chip select logic, which is tied
BUSCON1 register prior to an access which to the address bus, does not have to either be
should be performed with different bus charac- switched from Port 1 to Port 0 or vice versa. Figure
teristics. However, it is not recommended or very 9.16 shows a timing diagram for switching from a
useful to modify the SYSCON or BUSCON1 regis- non-multiplexed bus to a multiplexed bus.
ter which is currently being used for instructionNote: As long as any SYSCON or BUSCON1 sefetches, since pipeline effects can make it very dif- lects a non-multiplexed bus, Port 1 is dedicated for
ficult to determine which of the
followingaccesses
the address bus function and can not be used as
will be made with the new configuration. Thus, it is general purpose I/O port. In order to use Port 1 for
recommended to modify bus configuration regis-general purpose I/O, both the SYSCON and the
ters used for instruction fetches while executing in-BUSCON1 register must select one of the multistructions from either internal ROM, RAM, or from plexed bus modes. This is also true for the READY
a different SYSCON or BUSCON1 address range. function. In order to use the
READY pin forgeneral
For example, if one wants to reprogram the purpose I/O, RDYEN in register SYSCON and
BUSCON1 register, one should execute the in- RDYEN1 in register BUSCON1 must be ‘0’.
structions to modify the register from an address
space which is currently controlled by the SYSCON register.
Figure 9-16. Switching From Non-Multiplexed Bus to Multiplexed Bus
18/20

9 - External Bus Interface
9.9 EXTERNAL MEMORY ACCESS VIA THE
DATA READY SIGNAL
An optional Data-Ready function can be used to alinsert the programmed number of wait states
low an external device to determine the duration of
(if any) into the memory cycle, then check the
an external memory access. Note that the
READY
READY line, find that the external device is
input pin must be correctly activated for every exready (READY = ‘0’), and terminate the memternal memory access if the Data-Ready function
ory cycle. If the peripheral device is accessed,
has been enabled. Otherwise, the CPU would be
first the programmed wait states are inserted,
halted until a reset occurs. No time-out protection
and then the READY line is checked. For
other than a Watchdog Timer overflow is provided.
READY = 0, the bus cycle will be terminated.
ForREADY = ‘1’, the CPU will hold the bus cyThe Data-Ready function can be
enabled by setcle untilREADY goes to ‘0’, and then terminate
ting the RDYEN bit in the SYSCON register to ‘1’
the cycle. Since normally
peripheralsoperat(see chapter 5 ).
ing with a READY function are much slower
When the Data-Ready function is
enabled,the duthan memories, even memories requiring wait
ration of all external accessesis determined as folstates, this will have no impact on the access
lows:
time to theperipheral.
- If 0 wait states are programmed in bits 0 to 2 of 2) When using the asynchronous READY functhe MCTC field, the duration is determined by
tion, the first time the
READY line is checked is
the state of theREADY input pin.
near the falling edge of the ALE signal. Thus, in
order to guarantee a correct bus cycle the
1 and 7 wait states are programmed
- Ifinbetween
bits 0 to 2 of the MCTC field, the CPU will
READY line has to present a valid logic level at
first insert the programmed wait states into the
this time point. Some peripherals, however,
hold theREADY line at a low state when they
memory cycle, and after the wait states has exare not accessed, and require some time after
pired it will check the
READY line and delay
the memory accessdependingon the state of
being addressed by the CPU to signal their ‘not
ready’ state, i.e. bring the
READY line to a one.
the READY line. This feature provides the folBut, if theREADY line is still low with the falling
lowing adv
antages for the user:
edge of the ALE signal, the CPU interprets this
1) Memory can be connected, operating with or
as ‘external device is ready’, and inserts no
without wait states, and
peripherals, operating
wait states during the following bus cycle. This
with READY, to the external bus of the
problem is eliminated, since the CPU will first
ST10x166 and use wait states together with
insert the programmed wait states before
the READY function. If the memory is acchecking theREADY line.
cessed, the chip select logic is used to bring
the READY line to a LOW state. The CPU will Figure 9.17 a) and b) illustrate this feature. In this
example, three wait states have been programmed
19/20

9 - External Bus Interface
in field MCTC of register SYSCON in addition to READY line is checked and found to be high. The
chip now continues to hold the memory access cythe READY function. In Figure 9.17 a), the
READY
line goes to zero prior to the execution of the wait cle until theREADY line goes to low. Then the bus
states, but the chip continues to hold the memory cycle is terminated. This example could be the
access cycle until all wait states are performed. case when accessing a slowperipheraldevice
This example could be the case when accessing a (which in this case is slower than a normal bus cymemory, which just requires three wait states, and cle with three wait states).
where theREADY line is brought to low with the
Chip Select signal for the memory. In Figure 9.17
b), after insertion of all three wait states the
Figure 9-17. Using READY And Wait-States
20/20


CHAPTER 10
PARALLEL PORTS
10. PARALLEL PORTS
The ST10x166 provides 76parallelI/O lines organThe followingsubsections first give a general deized into four 16-bit I/O ports (Port 0 through 3), scription of Ports 0 through 4, then each of these
one 2-bit I/O port (Port 4), and one 10-bit input port ports is described in detail. Port 5 will be discussed
(Port 5). All port lines are bit addressable, and all separately in section 10.2.
lines of Port 0 through 4 are individually bit-wise
programmable as inputs or outputs via direction
10.1 PORTS 0 THROUGH 4
registers.
Each port line has one programmable alternate in- Each of the Ports 0 through 4 has its own port data
put or output function associated with it. Port 0 andregister (P0 through P4) and direction register
Port 1 may be used as the address and data lines (DP0 through DP4). The 16-bit data registers P0
when accessing external memory. Port 4 outputs through P3 for Ports 0 through 3, and the correthe additionalsegment address bits A16 and A17 sponding Port Direction control registers DP0
when segment
ation is enabled.The pins of Port 2
through DP3 are described below.
serve as capture inputs or compare outputs for the
CAPCOM unit, or as bus arbitration signals for The 8-bit data register P4 for Port 4 is also decommunication with external DMA functions. Port scribed. Port 4 is actually a 2-bit port, but the data
3 includes alternate input/output functions of CAP-and direction registers of Port 4 are realized as
COM timer T0, the general purpose timer blocks byte-wide registers. Bits 2 through 7 are reserved
unimplement
ed.
GPT1/2, and the serial channels ASC0/1. In addi- bits, while bits 8 through 15 are
ented bits has no effect,
tion, Port 3 provides the bus interface control sig-Writing to theunimplem
nals WR, BHE, READY, and the system clock while reading always returns zero.
CLKOUT. Port 5 is used for the analog input chan- In the following,the symbol Px (x = 0 through 4) for
nels to the A/D converter.
a port data register is also used to refer to the
All ports have Schmitt-Trigger input charac- whole Port x.
teristics, except when used as external data bus
and as analog inputs to the A/D converter.
1/18
10 - Parallel Ports
Ports 0 through 3 Data Registers
P0 (FF00h / 80h)
Reset Value :0000h
Ports 0 through 3 Direction Registers
DP0 (FF02h / 81h)
Reset Value : 0000h
15
14
13
12
11
10
9
8
15
14
13
12
11
10
9
8
P0.15
P0.14
P0.13
P0.12
P0.11
P0.10
P0.9
P0.8
DP0.15
DP0.14
DP0.13
DP0.12
DP0.11
DP0.10
DP0.9
DP0.8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
DP0.7
DP0.6
DP0.5
DP0.4
DP0.3
DP0.2
DP0.1
DP0.0
P1 (FF04h / 82h)
Reset Value :0000h
DP1 (FF06h / 83h)
Reset Value : 0000h
15
14
13
12
11
10
9
8
15
14
13
12
11
10
9
8
P1.15
P1.14
P1.13
P1.12
P1.11
P1.10
P1.9
P1.8
DP1.15
DP1.14
DP1.13
DP1.12
DP1.11
DP1.10
DP1.9
DP1.8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
DP1.7
DP1.6
DP1.5
DP1.4
DP1.3
DP1.2
DP1.1
DP1.0
P2 (FFC0h / E0h)
Reset Value :0000h
DP2 (FFC2h / E1h)
Reset Value : 0000h
15
14
13
12
11
10
9
8
15
14
13
12
11
10
9
8
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
DP2.15
DP2.14
DP2.13
DP2.12
DP2.11
DP2.10
DP2.9
DP2.8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DP2.7
DP2.6
DP2.5
DP2.4
DP2.3
DP2.2
DP2.1
DP2.0
P3 (FFC4h / E2h)
Reset Value :0000h
DP3 (FFC6h / E3h)
Reset Value : 0000h
15
14
13
12
11
10
9
8
15
14
13
12
11
10
9
8
P3.15
P3.14
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
DP3.15
DP3.14
DP3.13
DP3.12
DP3.11
DP3.10
DP3.9
DP3.8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
DP3.7
DP3.6
DP3.5
DP3.4
DP3.3
DP3.2
DP3.1
DP3.0
b15 to b0 =Px.y: Port Px Data Register.
(x = 0 through 3, y = 0 through 15).
b15 to b0 =DPx.y: Port Px Direction Control.
(x = 0 through 3, y = 0 through 15)
DPx.y = 0: Port Line Px.y is Input (high-impedance)
DPx.y = 1: Port Line Px.y is Output.
P4 (FF08h / 84h)
Port 4 Data Register P4
Reset Value 0000h
DP4 (FF0Ah / 85h)
Port 4 Direction Control Register DP4
Reset Value 0000h
7
6
5
4
R
3
2
1
0
P4.1
P4.0
7
6
5
4
R
3
2
1
0
DP4.1
DP4.0
b7 to b2 =R: Reserved.
b1 to b0 =DP4.y: Port P4 Direction Control.
(y = 0 through 1)
DP4.y = 0: Port Line P4.y is Input (high-impedance)
DP4.y = 1: Port Line P4.y is Output.
b7 to b2 =R: Reserved.
b1 to b0 =P4.y: Port P4 Data Register.
(y = 0 through 1)
2/18

10 - Parallel Ports
Using P0 through P4 as General Purpose I/O
corresponding port pins are
switched to the direcPorts
tion required by the selected bus type. This is exWhen the alternate input or output function associ-plainedin detail in thefollowingsections.
ated with a port p
in is not enabled, thepin can be
The logic level of a pin is clocked into the input
used as a general purpose I/O pin. Each port pin latch once per state time,
regardless whether the
consists of a port output latch, an output buffer, anport is configured for input or output.
input latch, an input (read) buffer, and a direction A write operation to a port pin configured as an incontrol latch. Each port pin can be
individuallyproput causes the value to be written into the port outgrammed for input or output via the respective di- put latch, while a read operation returns the
rection control bit DPx.y. Figure 10.1 shows a latched state of the pin itself. A read-modify-write
general block diagram of a port pin as it is config-operation reads the value of the pin, modifies it,
ured when used as a general purpose I/O port.
and writes it back to the output latch.
Port pins selected as inputs (DPx.y = ‘0’) are Writing to a pin configured as an output
placed into a high-im
pedance state since the out- (DPx.y = ‘1’) causes the output latch and the pin to
put buffer is disabled. This is the default configura-have the written value, since the output buffer is
tion after reset. During reset, all port pins are enabled.Readingthis pin returns the value of the
configured for input. When exiting reset while no output latch. A read-modify-write operation reads
external bus function is selected, all port pins re- the value of the output latch, modifies it, and writes
main in input mode unless configured otherwise byit back to the output latch, thus also modifying the
the user. When an external bus is selected, the level at the pin.
Figure 10-1. Block Diagram of a Port 0 through 4 General Purpose I/O Port
3/18

10 - Parallel Ports
Alternate Input and Output Functions of P0
bit addressable, and each line can be programmed
through P4
individually for input or output. When no external
program and/or data memory is connected to the
Each of the 76 port lines of the ST
10x166 has an
alternate input or output function associated with it.chip, Port 0 (P0) and Port 1 (P1) can be used as
34 port lines have both an alternate input and out- general purpose I/O ports.
put function, the other 42 lines have either an alter- As described in Chapter 9, ports P0 and P1 are
nate input or an alternate output function.
used as the address and data lines in the various
If an alternate output function of a pin is to be used, bus configurations which can be selected for conthe direction of this pin must be programmed fornecting external memory to the chip. Port 0 is used
output (DPx.y = ‘1’). Otherwise the pin remains in in all 4 external bus configurations, while P1 is only
the high-impedanc
e state and is not affected by the used as the address bus (A15 - A0) in the 16/18-bit
Address, Non-Multiplexed Bus mode. Port 1 can be
alternate output function.
used as a general purpose I/O port in the multiIf an alternate input function of a pin is used, the di- plexed external bus configuration modes.
rection of the pin must be programmed for input
(DPx.y =‘0’) if an external device is driving the pin. When a multiplexed bus configuration is selected,
The input direction is the default after reset. If no and the CPU accessesexternal memory, Port 0 first
external device is connected to the pin, however, outputs the 16-bit intra-segment address informaone can also set the direction for this pin to output.tion as an alternate output function. Port 0 is then
In this case, the pin reflects the state of the port switched to the high-impedance input mode to read
output latch. Thus, the alternate input function the incoming instruction or data. In the 16/18-bit Adreads the value stored in the port output latch. This dress, 8-bit Data Bus mode, two memory cycles are
can be used for testing purposes to allow a soft- required for word accesses,the first for the low byte
ware trigger of an alternate input function by writingand the second for the high byte of the word. When
data is written to an external memory, Port 0 outputs
to the port output latch.
the data byte or word after outputting the address.
On most of the port lines, the user software is responsible for setting the proper direction when us-In the non-multiplexed bus configuration, Port 1 outing an alternate input or output function of a pin. puts the 16-bit intra-segment address, while Port 0
This is done by setting or clearing the directionreads the incoming instruction or data word or
control bit DPx.y of
the pin before enabling the -al writes the data to the external memory. Therefore,
ternate function. There are port lines, however, Port 0 has both alternate input and alternate output
where the direction of the port line is switched auto-functions, while Port 1 has only an alternate output
matically. For instance, in the multiplexed external function. Figure 10.2 shows the structure of a Port
bus modes of Port 0, the direction must be 0 pin, and figure 10.3 shows the structure of a Port
switched several times for an instruction fetch in 1 pin.
order tooutput the addresses and to input the data. When an external bus mode is enabled, the direcObviously, this can not be done through instruc-tion of the port pin and the data input to the port outtions. In these cases, the direction of the port line is put latch are controlled by the bus controller
switched automatically by hardware if the alternate hardware. The input to the port output latch is disfunction of such a pin enabled.
is
connected from the internal bus and is switched via
There is one basic structure for all port lines with a multiplexer to the line labeled Alternate Data Outonly an alternate input function. Port lines with onlyput. On Port 0, the alternate data can be the 16-bit
an alternate output function, however, have differ- intra-segment address or the 8/16-bit data informaent structures due to the way the direction of the tion. On Port 1, the alternate data is the 16 bit intrapin is switchedand depending onwhether the pin segment address in the non-multiplexed bus mode.
is accessible by the user software or not in the al- The incoming data on Port 0 is read on the line Alternate Data Input. While an external bus mode is
ternate function mode.
enabled, the user software should not write to the
The followingsections describe in detail each of port output latch, otherwise unpredictable results
the ports and its alternate input and output func- may occur. When the external bus modes are again
tions.
disabled, the contents of the direction register last
written by the user become active. While the 16/18Bit Address, 8-Bit Data, Non-Multiplexed Bus mode
10.1.1 Port 0 and Port 1
is enabled, the upper half of Port 0 can not be used
Port 0 and Port 1 are two 16-bit I/O ports. They are for general purpose I/O,
4/18

10 - Parallel Ports
Figure 10-2. Block Diagram of a Port 0 Pin
Figure 10-3. Block Diagram of a Port 1 Pin
5/18

10 - Parallel Ports
10.1.2 Port 2
external device may drive the pin, otherwise conAll of the 16 pins of Port 2 (P2) may be used for the flicts would occur.
alternate input/output functions of the CAPCOM When a Port 2 line is used as a compare output
unit. They serve as an input line for the capture (compare modes 1 and 3; refer to chapter 8.1), the
function or as an output line for the compare func- compare event (or the timer overflow in compare
tions. The alternate symbols CC0IOhrough
t
mode 3) directly affects the port output latch. In
CC15IO have been assigned to Port 2 in
addition
compare mode 1, when a valid compare match octo the standard symbols P2.0 through P2.15 in or- curs, the state of the port output latch is read by the
der to reflect its alternate functions. Figures 10.4 CAPCOM control hardware via the line Alternate
to 10.6 show block diagrams of Port 2 pins.
Latch Data Input, inverted, and written back to the
When a Port 2 line is used as a capture input, the latch via the line Alternate Data Output. The port
state of the input latch, which represents the state output latch is clocked by the signal Compare Trigof the port pin, is directed to the CAPCOM unit via ger which is generated by the CAPCOM unit. In
the line Alternate Pin Data Input. The user software compare mode 3, when a match occurs, the value
must set the direction of the pin to input if an exter-‘1’ is written to the port output latch via the line Alnal capture trigger signal is used. If the direction isternate Data Output. When an overflow of the corset to output, the state of the port output latch willresponding timer occurs, a ‘0’ is written to the port
be read since the pin represents the state of the output latch. In both cases, the output latch is
output latch. This can be used to trigger a capture clocked by the signal Compare Trigger. The direcevent through software by setting or clearing the tion of the pin should be set to output by the user,
impedance
port latch. Note that in the output configuration, nootherwise the pin will be in the highstate and will not reflect the state of the output
latch.
Figure 10-4. Block Diagram of Port 2 Pin 0 to 12
6/18

10 - Parallel Ports
Figure 10-5. Block Diagram of Port 2 Pin 13, 14
Figure 10-6. Block Diagram of Port 2 Pin 15
7/18

10 - Parallel Ports
As can be seen from the block diagram, the user second master that the bus of the ST10x166 is
software always has free access to the port pin now free for use.
even when it is used as a compare output. This is The pin P2.13 is used as second alternate function
useful for setting up the initial level of the pin whenof bus request signal
BREQ. This signal intends to
using compare mode 1 or the double-register give the ST10x166 a chance to flag its own extermode. In these modes, unlike in compare mode 3, nal bus request to the second master. The second
the pin is not set to a specific value when a com- master can then decide whether or not to grant the
pare match occurs. Instead, it is
oggled.
t
ST10x166 the external bus for one or more exterWhen the user wants to write to the port pin at the nal bus accesses.
same time a compare trigger tries to clock the out- To enable these bus arbitration signals, the bit
put latch, the write operation of the user software HLDEN of the PSW register must be set. After rehas priority. Each time a CPU write access to the set, once this bit has been set to ‘1’ these three
port output latch occurs, the input multiplexer of thepins of Port 2 can no longer be used for
general
port output latch is switched to the line connectedpurpose I/O or for the CAPCOM unit, even if this
to the internal bus. The port output latch will re- HLDEN bit is cleared after once being set.
ceive the value from the internal bus. The hardDuring an external HOLD request ack
nowledged,
ware triggered change will be lost.
the ST10x166 set the external address, data, and
In order to support multi-master systems and com- control bus to the following states:
munication with external DMA functions, three pins
Port 0
Tri-state, if an external bus is
of Port 2 provide a bus arbitration.
enabled
The pin P2.15 configured in its alternate function
Tri-state, if a non-m
ultiplexed
HOLD is an input. When brought to low (active Port 1
bus
mode
is
selected
state), this input indicates to the ST10x166 that another master wants to perform one or several ac- Port 4
Tri-state, if an external bus and
cesses on the external bus of the ST10x166. After
segmentation are n
eabled
synchronisation of this signal and complete termi-ALE
Float to ’0’ through high-impednation of the current external bus cycle if any, the
ance pull down
ST10x166 backs off its external bus and activates
Float to ’1’ through high-impedthe signalHLDA to flag the second master that the RD
ance pull up
bus is now free. This condition will be held until the
HOLD line goes back to high. Then the signal WR
Tri-state even when used as
HLDA is disabled and the ST10x166 takes over
general purpose I/O pin
control of the external bus again if required. During
Tri-state, if BHE function
enabled
the HOLD phase, the ST10x166 can still operate BHE
No change
and fetch instruction or data when executing out ofREADY
internal memory. The CPU really stops execution if Figure 10.7 and 10.8 illustrate the timings for entry
external data or instruction fetches are required.
The pin P2.14 used as hold acknowledge signal and exit from HOLD mode.
HLDA is active low. This signal indicates to the
8/18

10 - Parallel Ports
Figure 10-7. Timing For Entry Into Hold (Non-Multiplexed Bus)
Figure 10-8. Timing For Exit From Hold (Non-Multiplexed Bus)
9/18

10 - Parallel Ports
10.1.3 Port 3
When the alternate input or output function of a
Each of the 16 pins of Port 3 (P3) has an alternate Port 3 pin is not used, this pin can be used as a
input or output function associated with it. Sevengeneral purpose I/O pin. When an alternate funcpins have an alternate input function, seven pins tion is used on a Port 3 pin, the configuration of this
have an alternate output function, and two pins, pin dependson the type of the alternate function.
RXD0 and RXD1, have an alternate input or output There are four different configurations described in
functiondependingon the operating mode of the the followingparagraphs.
serialchannel theyare associated with. The alternate functions of Port 3 are listed in table 10.1.
Table 10-1. Port 3 Alternate Input/OutputFunctions
Symbol
Alternate Symbol
Input/Output
P3.0
T0IN
I
Timer 0 Count Input
P3.1
T6OUT
O
Timer 6 Toggle Latch Output
P3.2
CAPIN
I
CAPREL Register Capture Input
P3.3
T3OUT
O
Timer 3 Toggle Latch Output
P3.4
T3EUD
I
Timer 3 External Up / Down Control Input
P3.5
T4IN
I
Timer 4 Count / Gate / Reload / Capture Input
P3.6
T3IN
I
Timer 3 Count / Gate Input
P3.7
T2IN
I
Timer 2 Count / Gate / Reload / Capture Input
P3.8
TXD1
O
Serial Channel 1 Data Output in Asynchronous Mode;
Clock Output in Syncrhonous Mode
P3.9
RXD1
I/O
Serial Channel 1 Data Input in Asynchronous Mode;
Data Input / Output in Synchronous Mode
P3.10
TXD0
O
Serial Channel 0 Data Output in Asynchronous Mode;
Clock Output in Synchronous Mode
P3.11
RXD0
I/O
Serial Channel 0 Data Input in Asynchronous Mode;
Data Input / Output in Synchronous Mode
P3.12
BHE
O
Byte High Enable Control Signal for External Memory
P3.13
WR
O
Write Strobe for External Data Memory
P3.14
READY
I
Ready Input
P3.15
CLKOUT
O
System Clock Output
10/18

Function
10 - Parallel Ports
10.1.3.1 PORT 3 PINS T0IN, T2IN, T3IN, T4IN,
T3EUD, CAPIN, AND READY
When the on-chip peripher
al associated with such
a pin is configured to use the alternate input funcThe basic structure of these seven Port 3 pins, tion, it reads the input latch, which represents the
labeled Alternate Data
which only have an associated alternate input state of the pin, via the line
Input.
If
an
external
device
is driving the pin, the difunction, is identical, as shown in figure 10.9. Note
rection of the pin must be set to input. When no exthat theREADY pin hasan additionalalternate input line which is tied directly to the pin. This line isternal device is connected to the pin, one can set
the direction to output and write to the port output
used for the synchronous Ready function.
latch to trigger the Alternate Data Input line.
Figure 10-9. Block Diagram of a Port 3 Pin With an Alternate Input Function
11/18

10 - Parallel Ports
10.1.3.2 PORT 3 PINS T3OUT, T6OUT, TXD0, TXD1,
WR, CLKOUT
functions, the user must set the direction of the port
line to output (DP3.y = ‘1’) and must write a ‘1’ into
These six of the seven Port 3 pins which have only the port output latch. Otherwise the pin is in its
e state (when configured as input)
an alternate output function associated also have high-impedanc
or
the
pin
is
stuck
at ‘0’ (when writing a ‘0’ into the
an identical structure, shown in figure 10.10. The
Alternate Data Output line, which is controlled by port output latch). When the alternate output functhe respective peripheral unit, is ANDed with the tions are not used, the Alternate Data Output line is
port output latch line. When using these alternate in its inactive state, which is a high level (‘1’).
Figure 10-10. Block Diagram of a Port 3 Pin With an Alternate Output Function
12/18

10 - Parallel Ports
10.1.3.3 PORT 3 PIN BHE
When an external 16-bit data bus mode is selected
Figure 10.11 shows the block diagram of pin AND theBHE function isenabledthrough bit BYTP3.12/BHE, which is the seventh Port 3 pin with DIS = ‘0’ in register SYSCON (default after reset),
the two multiplexers in the port data output line and
only an alternate output function. Since the
BHE
signal might be required directly after reset when the port direction control line are switched. The diolled
an external 16-bit data bus mode (multiplexed or rection is set to ‘1’ (output), and the pin is contr
non-multiplexed) is selected through pins EBC1 by the Alternate Data Output line.
and EBC0, there is no way the user can configure If theBHE pin is not required in an
application, the
the BHE pin. Thus, it will be switched automatically user can disable the function by setting bit BYTDIS
to the alternate function.
to ‘1’. The pin can then be used for general purpose I/O.
Figure 10-11. Block Diagram of Port 3 Pin
BHE
13/18

10 - Parallel Ports
10.1.3.4 PORT 3 PINS RXD0 AND RXD1
nels read the state of pins RXD0 and RXD1 via the
The configuration of the two pins RXD0 and RXD1, line Alternate Data Input.
with both an alternate input and an alternate output In the half-duplex synchronous mode, pins RXD0
function, is shown in figure 10.12. The Alternate and RXD1 are used as either data inputs or outData Output line again is ANDed with the port out- puts. For transmission, the user first must set the
put latch line.
direction to output (DP3.y = ‘1’) and must write a ‘1’
In the asynchronousmodes of the Serial Chan- into the port output latch. For reception, the user
nels, pins RXD0 and RXD1 are always used as must set the direction to input before starting the
data inputs. The direction of these pins must be set reception. When the alternate output function on
to input by the user (DP3.y = ‘0’). The Serial Chan- these pins is not used, the Alternate Data Output
line is in its inactive state, which is a high level (‘1’).
Figure 10-12. Block Diagram of Port 3 Pins RXD0 and RXD1
14/18

10 - Parallel Ports
10.1.4 Port 4
The alternate functions on the two pins of Port 4 and theBHE signal, the alternate function of Port
(P4) are the two segment address lines A16 and 4 might be required directly after reset. Thus, the
A17, shown in table below. As for Port 0, Port 1,
alternate function of Port 4 will be switched automatically.
Table 10-2. Port 4 Alternate Output Functions
Symbol
Alternate Symbol
Input/Output
Function
P4.0
A16
O
Lower Address Line of Segment Address
P4.1
A17
O
Higher Address Line of Segment Address
Figure 10.13 shows a block diagram of a Port 4 pin, whichsuppliesthe segment address. Via a second
which is the same as for a Port 1 pin. When an ex- multiplexer, the output buffer is enabled to drive
ternal bus is selected AND segmentation is en- the segment address.
abled through bit SGTDIS = ‘0’ in register If segmentation is not required in an application,
SYSCON (default after reset), the input to the port the user can disable segmentation by setting bit
output latch is switched via a multiplexer from theSGTDIS to ‘1’. The pins of Port 4 can then be used
internal bus to the Alternate Data Output line, for general purpose I/O.
Figure 10-13. Block Diagram of a Port 4 Pin
15/18

10 - Parallel Ports
10.2 Port 5
result when reading Port 5. Port 5 is actually a 10bit port, but the port register P5 is realized as a
Port 5 (P5) differs from Ports 0 through 4, since it is word register. Positions P5.10 through P5.15 are
a 10-bit input only port. Besides being used as a reserved and will be ead
r as zeros. A write operadigital input port, all lines of Port 5 may be used as tion to P5 has no effect. The value written to it is
the analog input hannels
c
to the A/D converter. lost.
The input buffers to P5 have Schmitt-Trigger char- No special distinction has to be made between
acteristics in order to achieve logic levels from thePort 5 lines being used as analog inputs and Port 5
analog inputs. Figure 10.14 illustrates the structure lines being used as digital inputs. A read operation
of a Port 5 pin.
on Port 5 may be performed on any of the 10 bits.
Since Port 5 is an input only port, it has no port out- The bits corresponding to lines being used as anaput latches and no direction register. However, an log inputs are don’t care bits. An A/D conversion on
address in the bit addressable register address a line being used asa digital inputwill convert the
space is provided in order to be able to read Port 5 logic level applied o
t the pin. Table 10.3 illustrates
by software. Register P5 shows the format of the the Port 5 lines and the corres
pondinganalog input
channels.
Figure 10-14. Block Diagram of a Port 5 Pin
16/18

10 - Parallel Ports
Table 10-3. Alternate Functions of Port 5
Symbol
P5.0
Alternate
Symbol
AN0
P5 (FFA2h / D1h)
Port 5 Register P5
Reset Value: XXXXh
Description
15
14
13
12
11
10
7
6
5
4
3
2
P5.7
PR.6
P5.5
P5.4
P5.3
P5.2
Analog Input Channel 0
P5.1
AN1
Analog Input Channel 1
P5.2
AN2
Analog Input Channel 2
P5.3
AN3
Analog Input Channel 3
P5.4
AN4
Analog Input Channel 4
P5.5
AN5
Analog Input Channel 5
P5.6
AN5
Analog Input Channel 6
P5.7
AN7
Analog Input Channel 7
P5.8
AN8
Analog Input Channel 8
P5.9
AN9
Analog Input Channel 9
R
9
8
P5.9
P5.8
1
0
P5.1
P5.0
b15 to b10 =R: Reserved.
b9 to b0 =P5.y: Port 5 Data Register.
READ ONLY (y = 0 through 9).
17/18

10 - Parallel Ports
NOTES :
18/18


CHAPTER 11
SYSTEM RESET
11. SYSTEM RESET
The internal system reset function provides initiali-In order to obtain an automatic power-on reset, the
zation of the ST10x166 into a defined default state. RSTIN pin can be connected to an external capaciThis internal reset function is invoked by any of thetor, since this pin already has an internal pullup refollowingconditions:
sistor connected to VCC (see figure 11.1a). The
1) By asserting a hardware reset signal on the reset signal onRSTIN first passes a Schmitt-Trigger in order to obtain a fast transition. For a powerRSTIN (Hardware Reset Input) pin
on reset, theRSTIN pin has to be held low for the
2) Upon the execution of the SRST (Software Re- minimum duration of the start-up time of the oscilset) instruction
lator (about 50ms for a quartz crystal). The internal
pullup resistor may vary between 50k
Ω and 150kΩ
3) By an overflow of the Watchdog Timer
Whenever one of these conditions occurs, the mi- therefore the minimum power-on reset time must
crocontroller is reset into its predefined defaultbe determined by the lowest value of this pullup readditionalexternal restate through an internal reset procedure. When a sistor. One may also use an
sistor.
In
the
reset
circuit
shown in figure 11.1b,
reset is initiated,pendinginternal hold states are
reset
source
1
may
be
used
e.g for power-on reset,
cancelled and external memory access cycles are
and
reset
source
2
for
warm
reset. In the case of a
aborted,regardless of an unreturnedREADY sigwarm
reset
where
the
oscillator
is already stabinal. Write operations to the internal RAM, however,
lized,
the
minimum
low
time
of
the
reset signal at
are completed before the internal reset procedure
pin
RSTIN
is
only
2
state
times.
Noise
pulses
begins. After this internal reset has been comlonger
than
2
state
times
will
always
initiate
a completed in case of a software or watchdog timer trigplete
reset
of
the
ST10x166.
Shorter
pulses
will
not
gered reset, or after deassertion of the signal at pin
be
considered
by
the
ST10x166
and
must
be
RSTIN in case of a hardware reset, the microconavoided.
If
RSTIN
is
still
low
by
the
time
the
internal
troller will start program execution from memory location 0000h in code segment zero. Here, one reset sequence is completed, the sequence will
would normally place a branch instruction to thestart again. This procedure continues until a high
level is found at the
RSTIN pin at the end of a reset
start of a software initialization routine forappli
the sequence.
cation specific configuration peripheralsand
of
The RSTOUT pin will be pulled low after a hardCPU Special Function Registers.
ware reset signal has been asserted on the
RSTIN
pin. It is also pulled low whenever the SRST in11.1 RSTIN and RSTOUT Pins
struction is executed or a Watchdog Timer overflow has occurred. The signal on the
RSTOUT pin
Two pins,RSTIN (Reset In) andRSTOUT (Reset
can be used to simult
aneouslyreset external hardOut), are dedicated to the system reset function of ware whenever the ST10x166 is reset. The
the ST10x166. TheRSTIN pin is used for resetting RSTOUT pin stays low until the protected EINIT
the microcontroller through an external hardware (End of Initialization) instruction is executed. Figreset signal. To perform a complete reset se- ure 11.2 shows the relation between the
RSTIN
quence, the ST10x166 requires 1040 state times and theRSTOUT signal.
(52µs at 20MHz CPU clock) withRSTIN low.
1/4
11 - System Reset
Figure 11-1. Reset Circuits
11.2 RESET VALUES FOR ST10x166
REGISTERS
Most SFRs,includingsystem registers and peripheral control and data registers, are forced to zero
once the internal reset has completed. This default
configuration has been selected such that all peripherals and the interrupt system are
disabled
from operation. Only data page pointers DPP1
through DPP3, the CP, SP, STKOV, STKUN, SYSCON, WDTCON, and specific read only registers
may contain defaultvalues other than zero after a
system reset. A complete summary of all
ST10x166 registers and their reset values is contained in Appendix B.
Note that the contents of the internal RAM are not
affected by a system reset. After a power-on reset,
the contents of the internal RAM are undefined.
This implies that the GPRs and the PEC source
and destination pointers (SRCPy, DSTPy, y = 0..7)
which are mapped into the internal RAM are also
undefined after a power-on reset. After a warm reset or a reset which is caused by an overflow of the
Watchdog Timer or by execution of the SRST instruction, the previous contents of the internal
RAM remain unaffected.
The four Data Page Pointers DPP0 through DPP4
are initializedduring a system reset such that they
are pointing to the lowest four consecutive 16 K
data pages. DPP0 points to data page 0, DPP1
points to data page 1, DPP2 points to data page 2,
and DPP3 points to data page 3.
Figure 11-2. Reset Function
2/4

11 - System Reset
11.3 WATCHDOG TIMER OPERATION AFTER
RESET
ter is initialized to the bus configuration that is determined by the state of pins
BUSACT, EBC0 and
EBC1 (External Bus Configuration) at the end of
The Watchdog Timer starts running after the inter- the internal system reset. The Bus Active bit
nal reset has completed. Its default clock fre- (BUSACT) will be cleared to ‘0’ if single-chip mode
quency will be the internal system clock/2 (10MHz has been selectedBUSACT
(
= ‘1’, EBC1/0= 00b),
r
value is
at fOSC = 40MHz), and its default eload
otherwise it is set to ‘1’. The other bits of the SY00h such that a watchdog timer overflow will occurSCON register are forced to zero. This default in= 40MHz) after
131072 states (6.55ms at OSC
f
itialization of the SYSCON register has been
completion of the internal reset. When the system selected such that external memories are acreset was caused by a Watchdog Timer overflow, cessed with the slowest pos
sible configur
ation for
the WDTR (Watchdog Timer Reset Indication) flag the respective bus type. The Ready function is disin register WDTCON will be set to ‘1’. This indi- abled.
cates the cause of the internal reset to the software
When the internal reset has completed, the coninitializ
a tion routine. WDTR is reset to ‘0’ by an exBHE signal
ternal hardware reset or by servicing the watchdog figuration of Ports 0, 1, 4, and of the
(High
Byte
Enable,
alternate
function
of P3.12) detimer.
pends on the bus type which was selected during
After the internal reset has completed, the opera- reset via theBUSACT, EBC0 and EBC1 pins. All
tion of the Watchdog Timer can be
disabledby the
other pins remain in the highimpedancestate until
DISWDT (Disable Watchdog Timer) instruction. they are changed by software or
peripheraloperaThis instruction has been implemented as a pro- tion.
tected instruction. For further security, its execution is only enabled in the time period after a reset When single chip mode was selected, Ports 0, 1,
t high-imuntil either the SRVWDT (Service Watchdog and 4, and P3.12/BHE also remain inhe
pedance
state
until
modified
by
software or
Timer) or the EINIT instruction has occurred. Oththrough
bus
type
reconfiguration
in
register SYerwise, execution of the DISWDT instruction will
SCON.
have no effect. More details about Watchdog
When any of the external bus modes was selected
Timer operation can be found in section 8.5.
during reset, Port 0 and/or Port 1 will operate in the
selected bus mode. The two pins of Port 4 will out11.4 PORTS AND EXTERNAL BUS
put the segment address, since bit SGTDIS in regCONFIGURATION DURING RESET
ister SYSCON is ‘0’ (default after reset). The code
segment pointer (CSP) is initialized to zero, and all
During the internal reset, all of the ST10x166’s port bits of the data page pointers except for the two
pins are configured as inputs through their direc-LSBs are also initialized to zero during reset.
tion registers and are switched to the high imped- Therefore, Port 4 will always output 00b after reset.
ance state (see chapter 10 for details about the When no memory accesses above 64K are to be
internal port structure). This ensures that the performed, segmentation may be
globallydisabled
ST10x166 and external devices will not try to drive by setting bit SGTDIS to ‘1’.
the same pin to different levels. Pin ALE floats to a
When an external 16-bit data bus mode (16/18-bit
low state through a weak internal
pulldown,and pin
address, multiplexed or non-multiplexed) is seRD floats to high.
lected, theBHE pin will be active after a reset. It
The BTYP (Bus Type) field of the SYSCON regis- can be disabledby setting the BYTDIS bit in the
SYSCON register to ‘1’.
3/4

11 - System Reset
In addition, the stack overflow (STKOV) and the
stack underflow (STKUN) registers should be initialized. After reset, the CP, SP, and STKUN registers all contain the same reset value FC00h,
while
To ensure proper entry into the
initializat
ion software routine, a hardware branch to location the STKOV register contains FA00h. With the default resetinitializat
ion, 256 words of system stack
zero/segment zero is made immediately
following
completion of the internal system reset or deasser- are available,where the system stack selected by
the SP growsdownward s from FBFEh, while the
tion of a correct reset signal on pin
RSTIN, respectively. Since location
0000h is the first vector in the register bank selected by the CP grows upwards
trap/interrupt vector table, it is the responsibility offrom FC00h.
the user to place a branch instruction at location Based on the application, the user may wish to inzero which branches to the first instruction of theitialize portions of the internal memory before norinitializ
a tion routine. Note that 8 bytes (locations mal program operation. Once the register bank
0000h through0007h)are provided in this table for has been selected through programming of the CP
the reset function. If single chip mode is selected register, one can easily perform memory zeroing
through pins
BUSACT, EBC1 and EBC0, the inter- through indirect addressing of the desired portions
nal ROM for the ST10166 or the internal Flash of the internal memory.
memory for the ST10F166, is accessed when the
ion, the interrupt system
initial branch is made to location zero. Otherwise, At the end of theinitializat
may
be
globallyenabled
by
moving the approprian external fetch to location zero is made.
ate constant to the PSW register. One must be
After reset, the ROM access or the bus configura- careful not to enable the interrupt system before intion can be modified in the first instruction of theitialization is complete.
software initialization routine. This is normally reation routine should beermit
quired whenever an ext
ernal memory is used, be- The software initializ
nated
with
the
EINIT
instruction.
This
instruction
cause the SYSCON register isinitializ
ed during
reset to the slowest possible memory configura- has been implemented as a protected instruction.
tion. To select the desired memory configuration Execution of the EINIT instruction disables the acand the required access parameters, one simply tion of the DISWDT instruction and causes the
moves a constant to the SYSCON register thus en- RSTOUT pin to go high (see also figure 11.2). This
suring that proper synchronization between the ex-signal can be used to indicate the end of the initialiternal memory and the ST10x166 is achieved. The zation routine and the proper operation of the miexternal bus configuration options are described incrocontroller to external hardware.
detail in section 9.1.
To decrease the number of instructions required to 11.6 THE BOOT-STRAP MODE
initializ
e the ST10x166, each peripheral is programmed to a default configuration upon reset, but On the ST10F166, 256Bytes of ROM (electrically
is disabled from operation. These default configu- programmable) are free to store the Boot-Strap
rations can be found in the descriptions of the indi-Routine. This routine defined by the user, allows to
vidualperipheralsin chapter 8.
pass round the immediate branch at the address
During the software design phase, portions of the 0000h in single chip mode.
internal memory space must be ass
ignedto regisThis program has to be loaded with the Flash Proter banks and system stack. When selecting initiali- gramming Board provided by SGS-THOMSON Mization values for the SP (Stack Pointer) and CP croelectronics.
(Context Pointer) registers, one must ensure that To access this mode, ALE pin must be pulled high
these registers areinitialized before any GPR or
during a hardware resetRSTIN).
(
stack operation is performed. This includes interThis
feature
is
optional,
and
if no program is stored
rupt processing which disabledupon
is
completion
in
this
area,
a
software
reset
instruction
(SRST) will
of the internal reset, and should remain
disabled
select the address 0000h in the program memory.
until the SP isinitializ
ed.
11.5 INITIALIZATION SOFTWARE ROUTINE
4/4


CHAPTER 12
POWER REDUCTION MODES
12. POWER REDUCTION MODES
Two different power reduction modes with differ- This feature can be used in conjunction with an exent levels of power reduction have been imple- ternal power failure signal, which pulls NMI
the pin
mented in the ST10x166 which may be entered low when a power failure is imminent. The microunder software control. In Idle mode, the CPU is controller will enter the NMI trap routine which can
stopped, while the peripherals continue their op- perform saving of the internal state into RAM. After
eration. In Power Down mode, both the CPU and the internal state has been saved, the trap routine
the peripherals are stopped. Idle mode can be may set a flag or write a certain bit pattern into speterminated by any reset or interrupt request, cific RAM locations, and then execute the PWRDN
while Power Down mode can only be terminated instruction. If the
NMI pin is still low at this time, the
by a hardware reset.
Power Down mode will be entered, otherwise program execution continues. During power down, the
voltage at the VCC pins can be lowered to 2.5V
12.1 POWER DOWN MODE
and the contents of the internal RAM will be preserved.
To save power in a system, the microcontroller
ializationroutine
can be placed in Power Down mode. All clocking Later, when a reset occurs, the init
of internal blocks is stopped, but the contents of can check the identification flag or bit pattern in
the internal RAM are preserved through the volt- RAM to determine whether the controller was inage supplied by the VCC pins. The Watchdog itially switched on or whether it was properly reTimer is stopped in Power Down mode. One can started from Power Down mode.
only exit this mode through an external hardware
reset by asserting a low level on the
RSTIN pin
12.2 IDLE MODE
for a specified period of time (at least 2 state
times). This reset will initialize all SFRs and ports One can decrease the power consumption of the
to their default state, but will not change the con- ST10x166 microcontroller by entering Idle mode. If
tents of the internal RAM.
enabled, allperipherals,INCLUDING the WatchThere are two levels of protection against unin- dog Timer, continue to function normally, only the
tentionally entering the Power Down mode. First, CPU operation is halted.
the PWRDN (Power Down) instruction which is The Idle mode is entered after the IDLE instruction
used to enter this mode has been implemented has been executed and the instruction before the
as a protected instruction. Second, this instruc- IDLE instruction has completed. To prevent unintion is effective ONLY if the
NMI (Non Maskable
tentional entry into Idle mode, the IDLE instruction
Interrupt) pin is externally pulled low while the has been implemented as a protected instruction.
PWRDN instruction is executed. The microcontroller will then enter the Power Down mode after The Idle mode is terminated by interrupt requests
from any enabled interrupt source whose individthe PWRDN instruction has completed.
ual Interrupt Enable flag was set before the Idle
mode was entered.
1/4
12 - Power Reduction Modes
For a request which was selected for CPU interrupt 12.3 STATUS OF OUTPUT PINS DURING IDLE
service, the associated interrupt service routine is AND POWER DOWN MODE
entered if the priority level of the requesting source
is higher than the current CPU priority and the in- DuringIdle mode , the CPU clocks are turned off,
terrupt system isgloballyenabled. After the RETI while all peripherals continue their operation in the
(Return from Interrupt) instruction of the interruptnormal way. Therefore, all ports pins which are
service routine is executed, the CPU continues configured as general purpose output pins output
normal program execution with the instruction fol-the last data value which was written to their port
lowing the IDLE instruction. Otherwise, if the inter- output latches. If the alternate output function of a
rupt request can not be serv
iced because of a too
port pin is used by a peripheral, the state of the pin
low priority or
a globallydisabled interrupt system, is determined by the operation of the ipheral
per
the CPU immediately resumes normal program (Port 2, Port 3). In particular, if CLKOUT, the alterexecution with the instruction
ollowing
f
the IDLE innate output function of P3.15, has been enabled, it
struction.
is also active during Idle mode.
For a request which was programmed for PEC Port pins which are used for bus control functions
service, a PEC data transfer is performed if the pri- go into that state which represents the inactive
ority level of this request is higher than the currentstate of the respective function
WR),
( or to a deCPU priority and the interrupt systemglobally
is
fined state which is based on the last bus access
enabled. After the PEC data transfer has been (BHE). Pins which are dedicated for bus control
completed, the CPU returns into Idle mode. Other- functions are also held in the inactive state (ALE,
wise, if the PEC request can not be serviced be- RD). Port pins which are used as external adcause of a too low priority or globallydisabled
a
dress/data bus hold the address/data which was
interrupt system, the CPU does not return to Idle output during the last external memory access bemode but restarts normal program execution with fore entry into Idle mode under the
ollowing
f
condithe instruction
followingthe IDLE instruction.
tions:
The Idle mode can also be terminated by a Non- - On P0[15:8], Port 0 outputs the high byte of the
Maskable Interrupt through a high to low transition last transferred address if the 16/18 bit address, 8-bit data, multiplexed bus mode is
on theNMI pin. After the Idle mode has been terminated by an interrupt or NMI request, the interrupt used, otherwise all pins of Port 0 are floating.
system performs a round of prioritization to deter- Pins P0[7:0] are always floating in Idle mode.
mine the highest priority request. In the case of an Port 1 floats if the non-mult
iplexed bus modeis
NMI request, the NMI trap will always be entered. - used, otherwise Port 1 acts as a general purpose I/O port.
Any interrupt request whose
individualInterrupt
Enable flag was set before the Idle mode was enPort 4 outputs the segment address for the last
- access
tered will terminate the Idle mode
regardlessof the
if segmentation is
enabled, otherwise
current CPU priority. The CPU will NOT go back
Port 4 acts as a general purpose I/O port.
into Idle mode when a CPU interrupt request is detected, even when the interrupt was not serviced DuringPower Down mode , the clocks to the CPU
and to the peripherals are turned off. In the
because of a higher CPU priority or
a globally disabled interrupt system (IEN = ‘0’). The CPU will ST10x166, the oscillator is completely switched
ONLY go back into Idle mode when the interrupt off. Like in Idle mode, all port pins which are configured as general purpose output pins output the last
system is globally enabled EN
(I = ‘1’) AND a PEC
service on a priority level higher than the currentdata value which was written to their port output
latches.
CPU level is requested and executed.
The Watchdog Timer may be used for monitoring When the alternate output function of a port pin is
the Idle mode: an internal reset will be generated if used by a peripheral,the state of this pin is deterperipheral before
no interrupt or NMI request occurs before the mined by the last action of the
the
clocks
were
switched
off.
In particular, if
Watchdog Timer overflows. To prevent the Watchdog Timer from overflowing during Idle mode, it CLKOUT, the alternate output function of P3.15,
had been enabled, it is not active during Power
must be programmed to a reas
onabletime interval
Down mode.
before the Idle mode is entered.
2/4

12 - Power Reduction Modes
All external bus actions are completed before Idle Abbreviations used:
or Power Down mode is entered. However, Idle or AF
State determined by (last) activity
Power Down modes can NOT be entered if
of Alternate Output Function
READY is enabled, but has not been deasserted
ADDR _ H
Address High Byte
during the last bus access.
Data in Port Output Latch
The followingtable 12.1 presents a summary of the DATA
state of all ST10x166 output pins during Idle and 16/8
16/18-bit Address, 8-bit Data,
Power Down modes.
MultiplexedBus
16+16
16/18-bit Address, 16-bit Data,
Non-Multiplexed Bus
non-segm
Segmentation
Disabled
Table 12-1. Output Pins Status during Idle and Power Down Mode
Idle Mode
Outputs
No external
bus enabled
Power Down Mode
External bus
enabled
NO external
bus enabled
External bus
enabled
ALE
L
L
L
L
RD
H
H
H
H
DATA
DATA
FLOAT
last ADDR_H (16/8)
FLOAT otherwise
DATA
DATA
FLOAT
last ADDR_H (16/8)
FLOAT otherwise
Port1
DATA
last ADDR (16 + 16)
DATA otherwise
DATA
last ADDR (16 + 16)
DATA otherwise
Port2
DATA/AF
DATA / AF
DATA/AF
DATA/last AF
Port3
DATA/AF
DATA / AF
DATA/AF
DATA/last AF
BHE/P3.12
DATA
L or H
DATA
L or H
WR/P3.13
DATA
H
DATA
H
CLKOUT/P3.15
(if enabled)
active
active
DATA
DATA (non-segm)
last ADDR otherwise
DATA
1)
1)
1)
Port0
7:0
15.8
Port4
A16, A17
RSTOUT
L
L
DATA (non-segm)
last ADDR otherwise
1)
1) Low if IDLE or PWRDN executed before EINIT, otherwise H
3/4

12 - Power Reduction Modes
NOTES:
4/4

CHAPTER 13

SYSTEM PROGRAMMING
13. SYSTEM PROGRAMMING
To aid in softwaredevelopment, a number of fea- 13.1.1 Directly Substitutable Instructions
tures has been incorporated into the instruction setInstructions known from other microcontrollers can
of the ST10x166. These include constructs for be replaced by the following instructions on the
modularity, loops, and context switching. In manyST10x166 listed table 13.1
cases, commonly used instruction sequences
have been simplified while
providinggreater flexibility. Thefollowingsections cover programming 13.1.2 Modification of System Flags
features and implementations to fully utilize this in-All bit and word instructions can access the PSW
struction set.
register. Thus, to set or clear PSW flags, no
CLEAR CARRY or ENABLE INTERRUPTS instruction is required. These functions are per13.1 INSTRUCTIONS PROVIDED AS
formed using bit set or clear (BSET, BCLR)
SUBSETS OF INSTRUCTIONS
instructions.
In many cases, instructions found in other microcontrollers are provided as subsets of more power- 13.1.3 External Memory Data Access
ful instructions in the ST10x166. This allows the
Byprovidinga Von-Neumann memory architecture
same functionality to be provided
whiledecreasing
and by providing hardware to detect access to inthe hardware required and decreasing
decode
complexity. In order to aid assembly programming, ternal RAM, GPRs, and SFRs, special instructions
these instructions, familiar from other microcontrol-are not required to load data pointers or explicitly
load and store external data. See chapter 6 for a
lers, can be built in macros. The
ollowing
f
subsections describe methods of providing the function ofdetailed description of data addressing modes.
these common instructions.
Table 13-1. Instruction Equivalents
Other µC
ST10x166
Function
CLR
Rn
AND
Rn, #0h
Clear Register
CPLB
Bit
BMOVN
Bit, Bit
DEC
Rn
SUB
Rn, #1h
Decrement Register
INC
Rn
ADD
Rn, #1h
Increment Register
SWAPB
Rn
ROR
Rn, #8h
Swap Bytes in Word
Complement Bit
1/8
13 - System Programming
Note: The above save sequence and the restore
sequence after COPYL are only required if the curMultiplicationand division of words and
double
rent routine could have interrupted a previous rouwords is provided through multiple cycle instruc-tine which contained a MUL or DIV instruction. The
tions implementing a Booth algorithm. Each in- MDC register is also saved because it is possible
struction implicitly uses the 32-bit MD register that a previous routine’s Multiply or Divide instruc(MDL-low 16 bits, MDH-high 16 bits). Whenever tion was interrupted while in progress. In this case
either half of this register is written into, the MDRIU the information about how to restart the instruction
flag (Multiply or Divide Register In Use) in the MDC is contained in this register. The MDC register
register is set. It is cleared whenever the MDL reg- must be cleared to be correctly
initialized for a subister is read. Because an interrupt can be acknow- sequent multiplication or division.
ledged before the MD register contents are saved, START:
MULU R1, R2
this flag is required to alert interrupt routines (which;Multiply
16x 16 unsigned,
Sets
require the use of the multiply
/divide hardware) of ;MDRIV.
state preserved in the MD register. This register,
JNB V, COPYL
however, must only be saved when an interrupt
;Test
for
only
16-bit
result.
routine requiresuse of the MD register and a previous task has not saved the current result. This
MOV R3, MDH
flag is easily tested by the Jump on Bit instructions.;Move high portion of MD.
Multiplicationis simply performed by specifying the COPYL:
MOV R4, MDL
correct signed or unsigned version of the instruc-;Move low portion of MD, Clears
tion. The result is then stored in the MD register. ;MDRIV.
The overflow flag (V) is set if the result from a mul- RESTORE:
JNB SAVED, DONE
tiply or divide instruction is greater than 16 bits.;Test if MD registers were saved.
This flag can then be used to determine whether
POP MDL
both word halves of the MD register must be transferred from the MD register. One must first move ;Restore registers.
the high portion of the MD register into the register
POP MDH
file or memory to ensure that the MDRIU flag rePOP MDC
flects the correct state.
The followinginstruction sequence performs an DONE:
;any instruction
.
unsigned16 by 16-bit mult
iplication:
SAVE:
JNB
MDRIU,START
To perform division, the user must first move the
;Test if MD was in use.
dividendinto the MD register. If a 16/16 bit division
SCXT MDC, #0
is specified, only the low portion of the MD register
;Save and clear control register
must be loaded. The result is also stored in the MD
;(only required if multiply or ;diregister. The low portion of the MD register, MDL,
vide instruction was interrupted).
contains the integer result of the division while the
high portion of the MD register, MDH, contains the
BSET SAVED
remainder.
;Save indication of stored state.
The overflow flag V is set if the result can not be
PUSH MDH
represented in a word data type. One must first
;Save previous MD contents.
copy the high portion of the MD register result into
PUSH MDL
the register file or memory to ensure that the
;on system stack.
MDRIU flag is set correctly, but one may write to
either half of the MD register to set the MDRIU flag.
The followinginstruction sequence performs a 32
by 16 bit division:
13.2 MULTIPLICATION AND DIVISION
2/8

13 - System Programming
Two types of stacks are provided in the ST10x166.
The first type is used implicitly by the system and is
contained in the internal RAM. The second type
provides stack access to the user in either the internal or external memory. Both stack types grow
from high memory addresses to low memory addresses and are described in the
ollowing
f
subsections.
MOV MDH, R1
;Move dividend to MD register,
;Sets MDRIV.
MOV MDL, R2
;Move low portion to MD.
DIV R3
;Divide 32/16 signed, R3 holds
;the divisor.
JB
V, ERROR
;Test for divide overflow.
MOV
R3, MDH
;Move remainder to R3.
MOV R4, MDL
;Move integer result to R4,
;Clears MDRIV.
13.4.1 Internal System Stack
A system stack is provided to store return vectors,
segment pointers, and processor status for procedures and interrupt routines. A system register,
SP, points to the top of the stack. This pointer is decremented when data is pushed onto the stack and
incremented when data is
popped.
Whenever a multiply or divide instruction is inter-The internal system stack can also be used to temrupted while in progress, the MULIP flag in the porarily store data between subroutines or tasks.
PSW of the interrupting routine is set. When the in- Instructions are provided to push or pop registers
terrupt routine is exited with the RETI instruction, on/from the system stack. However, in most cases
this bit is implicitly tested before the old PSW is the register banking scheme provides the best perpoppedfrom the stack. If MULIP = ‘1’, the inter- formance for saving state between multiple tasks.
rupted multiply/divide instruction will then be com-Note: THE SYSTEM STACK PERMITS STORpleted after the RETI instruction has been AGE OF WORDS ONLY. Bytes can be stored on
the system stack, but must be extended to words
executed.
Interrupt routines which require the use of the mul-first. One must also consider that only even byte
tiply/divide hardware MUST first push and then addresses can be stored in the SP register (LSB of
clear the MDC register before starting a multiply/di- SP is always ‘0’).
vide operation if a multiply/ divide instruction was inDetection of stack overflow/underflow is supported
progress in the interrupted routine (MULIP = ‘1’). by two registers, STKOV (Stack Overflow Pointer)
The MDC register holds state of the interrupted and STKUN (Stack Underflow Pointer). Specific
multiply/divide instruction which is necessary in or-system traps (Stack Overflow trap, Stack Underder to complete the instruction properly after the flow trap) will be entered
wheneverthe SP reaches
RETI instruction. The old MDC contents must be either boundaryspecified in these pointer regispopped from the stack before the RETI instruction ters.
is executed.
The contents of the Stack Pointer are always compared to the contents of the Overflow register
wheneverthe SP is DECREMENTED either by a
13.3 BCD CALCULATIONS
Call, Push, or Subtract instruction. An Overflow
Trap will be entered when the SP value is less than
No direct support for BCD calculationsprovided
is
in the ST10x166. BCD calculations are performed the value in the Stack Overflow register
by converting between BCD data types and binary The Stack Pointer value is compared to the contents of the Underflow register whenever the SP is
data types, performing the desired
alculations
c
using standard data types. Due to the
enhanced perINCREMENTED either by a Return, Pop, or Add
formance of division instructions, one can quicklyinstruction. An Underflow Trap will be entered
convert from binary to BCD through divisions by 10when the SP value is greater than the value in the
of binary data types. Conversion from BCD to bi- Stack Underflow register.
nary isenhanced by multiple bit shift instructions. When a value is MOVED into the Stack Pointer,
Thus, similar performance is achieved in compari- NO check against the Overflow/Underflow regisson to instructionshich
w would u
spport BCD data
ters is performed.
types while noadditionalhardware is required.
13.4 STACK OPERATIONS
13.4.1.1 USE OF STACK UNDERFLOW/OVERFLOW
REGISTERS
3/8

13 - System Programming
In many cases, he
t user will place a S
oftware Replete, the boundarypointers are updated to reflect
set (SRST) instruction in the stack underflow and the newly allocated space on the internal stack.
overflow trap service routines indicating a fatal er- Thus, the user is free to write code without concern
ror. However, it is also possible to use the stack un- for the internal stack limits. Only the execution time
derflow and stack overflow registers to cache required by the trap routines is seen by user proportions of a larger external stack. This
echnique
t
grams.
places only the portion of the system stack cur- Because of circular stacking, data accessed at the
rently being used in the internal memory, thus al- boundary limits of the internal stack is accessed as
lowing a greater portion of the internal RAM to be if no boundary existed. When data is pushed beused for program data or register banking.
yond the bottom of the internal memory (location
This basic technique allows data to be pushed untilFA00h), the data actually is pushed at the top of
the overflow boundary of the internal stack is the allocated stack space (e.g. location FBFEh
reached. At this point a portion of the stacked data where 256 words have been allocated for the
must be saved in the external memory to create stack). Thus, the internal access pointer wraps
space for further stack pushes. This is called stack around the internal stack as specified by the stack
flushing. When executing a number of return or size in the SYSCON register. The stack pointer alpop instructions, the upper
boundary(since the
ways points to the virtual location in the external
stack empties upward to higher memory locations)memory. The boundary pointers, STKOV and
is reached. The entriesthat have been previously STKUN, also point to the external virtual stack losaved on the external memory must now be re- cations.
stored. This is called stack filling. Because proce- The followingprocedure is required upon
initializ
adure call instructions do not continue to nesttion of the controller:
indefinitely and return instructions are interspersed
with calls, flushing and filling normally occur very1) Specify in the SYSCON register the size of the
internal RAM to be dedicated to the system
infrequently. If this is not true for a given program
stack.
environment, this technique should not be used
because of the overhead of flushing and filling.
2) Initialize two pointers in the internal data memory which specify the upper
and lower bound
To avoid movement of data that remains internally
ary
of
the
external
stack.
These
values
are
on the stack during flushing and filling, a circular
then tested in the stack underflow and overstack mechanism has been implemented by maskflow trap routines.
ing off the higher bits of the stack pointer. Thus,
only portions of the internal RAM that are flushed 3) Initialize the stack underflow pointer to the botor filled need to be moved. Without this circular
tom of the external stack, and the overflow
stacking, the user would have to move each entry
pointer to the value of the underflow pointer mithat remainedon the stack by the distance of the
nus the size of the internal stack plus six words
space being flushed or filled.
(for the reserved space).
The circular stack technique requires that the inter- Followingthis procedure, the internal stack will fill
nal stack be one of theollowing
f
sizes: 32, 64, 128
until the overf
low pointeris reached. After entry to
or 256 words.
the overflow trap procedure, the top of the stack
When a boundaryis reached, the stack underflow will be copied out to the external RAM. The internal
or overflow trap is entered where the user moves a pointers will then be modified to reflect the newly
predetermined portion of the internal stack to or allocated space. After exiting from the trap procefrom the external stack. The amount of data trans- dure, the internal stack will wrap around to the top
ferred is determined by the average stack space of the internal stack, and continue to grow until the
required by routines and the frequency of calls, new value of the stack overflow pointer is reached.
traps, interrupts, and returns. In most cases, this
willbe approxim
ately one quarter to one tenth the
13.4.2 User Stacks
size of the internal stack. Once the transfer is com-
4/8

13 - System Programming
User stacks provide the ability to create task spe- To support modular coding, a procedure mechacific data stacks and to off-load data from the sys- nism is provided to allow coding of frequently used
tem stack. The user may push both bytes and portions of code into subroutines. The CALL and
words onto a user stack, but is responsible for us- RET instructions store and restore the value of the
ing theappropriat
e instructions when
poppingdata
Instruction Pointer (IP) on the system stack before
from the specific user stack. No hardware detec- and after a subroutine is executed. One must also
tion of overflow or underflow of a user stack is pro-ensure that any data pushed onto the system stack
vided. The o
f llowing addressing modesallow
during execution of the subroutinepoppedbeis
implementation of user stacks:
fore the RET instruction is executed.
Rb, [Rw+] or Rw, [Rw+]:
Post-increment Indirect Addressing: Used to 13.6.1 Passing P arameters on the System
pop one byte or word from a user stack. This Stack
mode is onlyavailablefor MOV instructions,
and can specify any GPR as the user stack Parameters may be passed on the system stack
through PUSH instructions before the subroutine is
pointer.
called, and POP instructions during execution of
the subroutine. Base plus offset indirect address[-Rw], Rb or [-Rw], Rw:
ing also permits access to parameters without popPre-decrement Indirect Addressing: Used to ping these parameters from the stack during
push one byte or word onto a user stack. This execution of the subroutine. Indirect addressing
mode is onlyavailablefor MOV instructions, provides a mechanism of accessing data referand can specify any GPR as the user stack enced by data pointers which are passed to the
pointer.
subroutine.
In addition, two instructions have been impleRb, [Rw+] or Rw, [Rw+]:
mented to allow one parameter to be passed on
Post-increment Index Register Indirect Ad- the system stack without
additionalsoftware overdressing: Used to pop one byte or word from a head.
user stack. This mode is available to most instructions, but only GPRs R0-R3 can be speci- The PCALL (push and call) instruction first pushes
the ‘reg’ operand and the IP contents on the sysfied as the user stack pointer.
tem stack and then passes control to the subroutine specified by the ‘caddr’ operand.
13.5 REGISTER BANKING
When exiting from the subroutine, the RETP (return and pop) instruction first pops the IP and then
Register banking provides the user with an ex- the ‘reg’ operand from the system stack and retremely fast method of switching user context. A turns to the calling program.
single machine cycle instruction saves the old
bank and enters a new register bank. Each register
bank may assign up to 16 registers. Each register 13.6.2 Cross Segment Subroutine Calls
bank should be allocated during coding based on
Calls to subroutines in different segments require
the needs of each task. Once the internal memory use of the CALLS (call inter-segment subroutine)
has been partitioned into a register bank space, ininstruction. This instruction preserves both the
ternal stack space, and a global internal memory
CSP (code segment pointer) and IP on the system
area, each bank pointer is then assigned. Thus,
stack.
upon entry to a new task, the
appropriatebank
pointer is used as the operand of the SCXT (switch Upon return from the subroutine, a RETS (return
context) instruction. Upon exit from a task, a simple from inter-segment subroutine) instruction must be
POP instruction to the context pointer (CP) re- used to restore both the CSP and IP. This ensures
that the next instruction after the CALLS instruction
stores the previous task’s register bank.
is fetched from the correct segment. It is possible
to use CALLS within the same segment, but two
13.6 PROCEDURE CALL ENTRY AND EXIT
words of the stack are still used to store both the IP
and CSP.
13.6.3
5/8

13 - System Programming
Providing Local Registers for Subroutines
For subroutines which require local storage, the
followingmethods are provided:
_ Alternate Bank of Registers: Upon entry to a
subroutine, it is possible to specify a new set of
local registers by executing a SCXT (switch
context) instruction. This mechanism does not
provide a method to recursively call a subroutine.
_ Saving and Restoring of Registers: To provide
local registers, one can push the contents of
the registers which are required for use by the
subroutine, and pop the previous values before returning to the calling routine. This is the
most common echnique
t
used today and it
does provide a mechanism to support recursive procedures. This method, however, requires two machine cycles per register stored
on the system stack (one cycle to PUSH the
register, and one to POP the register).
_
Use of the System Stack for Local Registers: It
is possible to use the SP and CP to set up local
subroutine register frames. This allows subroutines to dynamically allocate local variables
as needed in two machine cycles. To allocate
a local frame one simply subtracts the number
of required local registers from the SP, and
then moves the value of the new SP to the CP.
This operation is supported through the SCXT
(switch context) instruction with the addressing
mode ‘reg, mem’. Using this instruction one
can save the old contents of the CP on the system stack and move the value of the SP into
CP (see example in figure 13.1). Each local
register is then accessed as if it was a normal
register. Note that the system stackgrowing
is
downwards
, while the register bank is
growing
upwards.
Upon exit from the subroutine, one first restores the old CP bypoppingit from the stack,
and then simply adds the number of local registers used to the SP to restore the allocated
local space back to the system stack.
Figure 13-1. Local Registers
Old Stack
Area
Example:
After subroutine entry:
SUB
SP, #10
SCXT CP, SP
Old SP
; 5 Words
R4
Newly
Allocated
Register
Bank
R3
R2
R1
CP
New SP
R0
Old CP contents
Before exiting subroutine:
POP CP
ADD SP, #10
New
Stack Area
6/8

; 5 Words
13 - System Programming
13.7 TABLE SEARCHING
time it requests a PEC transfer or requests CPU
servicing through an interrupt routine. One can
A number of features have been
includedto dealso poll information from peripherals through read
crease the execution time required to search ta- accesses of SFRs or bit operations
including
bles. First, branch delays are eliminated after the branch tests on specific control bits in SFRs. To
first iteration of the loop. Second, in nonsequenensure proper allocation of
peripheralsamong
tially searched tables, the
enhanced performance multiple tasks, a portion of the internal memory has
of the ALU allows more complicated hash algo- been made bit addressable to allow user semarithms to be processed to obtain better table distri-phores. Instructions have also been provided to
bution. For sequentially searched tables, the lock out tasks through software by setting or clearauto-increment indirect addressing mode and the ing of user specific bits and
onditionally
c
branching
E (end of table) flag stored in the PSW decrease based on these specific bits.
the number of overhead instructions executed in It is recommended that fields of bits in control
the loop. Below, two examples illustrate searching SFRs are updated using the BFLDH and BFLDL
ordered tables and non-ordered tables, respec- instructions to avoid undesired intermediate
tively:
modes of operation which can occur when ANDMOV R0, #BASE
OR instruction sequences are used.
;Move table base into R0.
LOOP:
CMP R1, [R0+]
13.9 FLOATING POINT SUPPORT
;Compare target to table entry.
JMPA cc _ SGT, LOOP
All floating point
operationsare performed using
;Test whether target has
software. Standard multiple precision instructions
;not been found.
are used to perform calculations on data types that
exceed the size of the ALU. Multiple bit rotate and
Note: The last entry in the table must be greater logic instructions allow easy masking and extractthan the largest possible target.
ing of portions of floating point numbers.
MOV R0, #BASE
To decrease the time required to perform floating
;Move table base into R0.
pointoperations
, two hardware features have been
implemented in the core CPU. The first aids in norLOOP:
CMP R1, [R0+]
malizing floating point numbers by indicating the
;Compare target to table entry.
position of the first set bit in a GPR. One can then
JMPA cc _ NET, LOOP
use this result to rotate the floating point result ac;Test whether target is not
cordingly. The second feature aids in properly
;found AND the end of table has not
roundingthe result of normalized floating point
;been reached.
numbers through the overflow (V) flag in the PSW.
This flag is set when a one is shifted out of the carry
Note: The last entry in the table must be equal to bit. The overflow flag and the carry flag are then
used to round the floating point result based on the
the lowest signed integer (8000h).
desiredroundingalgorithm.
13.8 PERIPHERAL CONTROL AND
INTERFACE
13.10 TRAP/INTERRUPT ENTRY AND EXIT
Interrupt routines are entered when a requesting
All communication between
peripheralsand the
CPU is performed either by PEC transfers to and interrupt has a priority higher than the current CPU
regardless of the
from the internal memory, or by explicitly address- priority level. Traps are entered
ing the SFRs associated with the specific peripher- current CPU priority. When either a trap or interrupt
als. After resetting the ST10x166, all peripherals routine is entered, the state of the machine is pre(except Watchdog Timer) are disabled and initial- served on the system stack and a branch to the apized to default values. To program a desired con- propriate trap/interrupt vector is made. This
sequence is described in detail in chapter 7.
figuration of a specific
peripheral,one uses MOV
instructions of either constants or memory valuesAll trap and interrupt routines require use of the
to specific SFRs. One can also alter specific con- RETI (return from interrupt) instruction to exit from
trol flags through bit instructions.
the called routine. This instruction restores the sysOnce in operation, the
peripheral operates autono- tem state from the system stack and then branches
mously until an end condition is reached at whichto the location where the trap or interrupt occurred.
7/8

13 - System Programming
NOTES :
8/8


APPENDIX A
INSTRUCTION SET
Α. ΙΝΣΤΡΥΧΤΙΟΝ ΣΕΤ
Section A.2 of theappendix of the ST10x166 User Α.1.3 Οπερατιον / ∆εσχριπτιον
Manual contains a det
ailled description of the This part presents a logical description of the opST10x166 instructions in
alphabetical order. Basic eration performed by an instruction by means of a
items of this descriptional part are defined in the high levellanguageconstruct. A brief verbal defollowingsection A.1
scription of the operation of the instruction is additionally provided.
Α.1 ∆εφινιτιονσ
The followingsymbols are used to represent data
movement, arithmetic or logical operators.
This section defines and explains
items which are ∆ιαδιχ οπερατιονσ:
mentioned in each single instruction description:
(οπΞ)
οπερατορ
(οπΨ)
Instruction name, syntax, operational description,
data type, condition flags, addressing modes, for- ← (opY)
is ΜΟςΕ∆ into
(opX)
mats and number of bytes.
+
(opX)
is Α∆∆Ε∆ to
(opY)
(opY)
is ΣΥΒΤΡΑΧΤΕ∆ from
(opX)
Α.1.1 Ινστρυχτιον Ναµε
*
(opX)
is ΜΥΛΤΙΠΛΙΕ∆ by
(opY)
Specifies the mnemonic opcode of the instruction
/
(opX)
is ∆ΙςΙ∆Ε∆ by
(opY)
in oversized bold letter
ing for easy reference. The
∧
(opX)
is
logically
ΑΝ∆ed
with
(opY)
mnemonics have been chosen with regard to the
particular operation which is performed by the ∨ (opX)
is logicallyΟΡ ed with
(opY)
specified instruction.
⊕ (opX)
is logicallyΕΞΧΛΥΣΙςΕΛΨ
ΟΡ ed with
(opY)
Α.1.2 Σψνταξ
⇔ (opX)
is ΧΟΜΠΑΡΕ∆ against
(opY)
Specifies the mnemonic opcode and the
required
mod (opX)
is divided
ΜΟ∆ΥΛΟ
(opY)
formal operands of the instruction as used in the
followingsubsection ‘Operation’. There are instructions with either none, one, two or three oper- Μοναδιχ οπερατιονσ:
ands which must be separated from each other by
οπερατορ
(οπΞ)
commas :
¬ (opX)
is logicallyΧΟΜΠΛΕΜΕΝΤΕ∆
MNEMONIC {op1 {,op2 {,op3 } } }
Missing or existing parentheses signify whether
The syntax for the actual operands of an instruc- the used operand specifies an immediate constant
tion dependson the selected addressing mode. All value, an address or a pointer to an address as folof the addressing modes av
ailable are summalows:
rized at the end of eac
h single ins
truction descripopX
Specifies the immediate
tion. In contrast to the syntax for the instructions
constant value of opX
described in theollowing,the
f
ST10x166 assembler provides much morelexibility
f
in writing
(opX)
Specifies the contents of opX
ST10x166 programs (e.g. by generic instructions
(opXn)
Specifies the contents of
and by automatically selecting appropriate adbit n of opX
dressing modes whenever possible), and thus it
((opX))
Specifies
the contents of the
eases the use of the instruction set.
contents of opX
(this means that opX is used
as pointer to the actual
operand)
1/84
Α − Ινστρυχτιον Σετ
In addition to the formal
operandsop1, op2 and
Α.1.5 Χονδιτιον Φλαγσ
op3 which have already been introduced in sub- This part reflects the state of the N, C, V, Z and E
section A.1.2 (Syntax),he
t following oper
ands will
flags in the PSW register which is the state after
be used in the operational description:
execution of the corres
pondinginstruction except if
CP
Context Pointer register
the PSW register itself was specified as the destiCSP
Code Segment Pointer register nation operand of that instruction (see Note).
The resulting state of the flags is represented by
IP
Instruction Pointer
symbols as follows:
MD
Multiply/Divide register (32 bits
‘*’ The flag is set due to theollowing
f
standard
wide, consists of MDH and
rules for the corresponding flag:
MDL)
N = 1 : MSB of the result is set
MDL, MDH Multiply/Divide Low and High
registers (each 16 bit wide)
N = 0 : MSB of the result is not set
PSW
Program Status Word register
C = 1 : Carry occured during operation
SP
System Stack Pointer register
C = 0 : No Carry occured during
operation
SYSCON
System Configuration register
V = 1 : Arithmetic Overflow occured during
operation
C
Carry condition flag in the PSW
register
V = 0 : No Arithmetic Overflow occured
during operation
V
Overflow condition flag in the
PSW register
Z = 1 : Result equals zero
SGTDIS
Segmentation Disable bit in the
Z = 0 : Result does not equal zero
SYSCON register
E = 1 : Source operand represents the
count
Temporary variable for an
lowest negative number
intermediate storage of the
(either 8000h for word data or 80h
number of shift or rotate cycles
for byte data)
which remain to complete the
E = 0 : Source operand does not represent
shift or rotate operation
the lowest negative number for the
tmp
Temporary variable for an
specified data type
intermediate result
‘S’
The flag is set due to rules which
0, 1, 2,...
Constant values due to the
deviate from the just described
data format of the specified
standard. For more details
operation
see section A.2 or the description
of the ALU status flags in
section 6.3.2.1
Α.1.4 ∆ατα Τψπεσ
‘-’
The flag is not affected by the
This part specifies the particular data type accordoperation.
ing to the instruction. Basically, the
ollowing
f
data
‘0’
The flag is cleared by the operation.
types are possible:
‘NOR’
The
flag contains the logical
BIT, BYTE, WORD, DOUBLE WORD
NORing of the two specified bit
Except for those instructions which extend byte
operands.
data to word data, all instructions have only one
‘AND’
The flag contains the logical
particular data type. Note that the data types menANDing
of the two specified bit
tioned in this subsection do not consider accesses
operands.
to indirect address pointers or to the system stack
which are always performed with word data. More‘OR’
The flag contains the logical ORing
over, no data type is specified for System Control
of the two specified bit
operands.
Instructions and for those of the branch instructions
which do not access any explicitly addressed data.
2/84

Α − Ινστρυχτιον Σετ
‘XOR’
‘B’
‘B’
The flag contains the logical
XORing of the two specified bit
operands.
The flag contains the original value
of the specified bit operand.
The flag contains theomplemenc
ted value of the specified bit
operand.
selected as destination bits, they stay unc
hanged.
This means that they keep the state after execution
of the previous instruction.
In any case, if the PSW was the dest
ination operand of an instruction, the PSW flags do NOT represent the condition flags of this instruction as usual.
Α.1.6 Αδδρεσσινγ Μοδεσ
Νοτε :
This part specifies which combinations of different
If the PSW register was specified as the destina- addressing modes areavailablefor the required
tion operand of an instruction, the condition flagsoperands. Mostly, the selected addressing mode
can not be interpreted as just described, because combination is specified by the opcode of the corthe PSW register is modified
dependingon the
responding instruction. However, there are some
data format of the instruction as follows:
arithmetic and logical instructions where the adFor word operations, the PSW register is overwrit- dressing mode combination is not specified by the
(identical) opcodes but by particular bits within the
ten with the word result. For byte
operations
, the
operand field.
non-addressed byte iscleared and the addres
sed
byte is overwritten. For bit or bit-field operations onThe addressing modes are described in detail in
the PSW register, only the specified bits are modi- section 6.2
fied. Supposed that the condition flags were not
Φιγυρε Α−1. Ινστρυχτιον Φορµατ Ρεπρεσεντατιον
3/84

Α − Ινστρυχτιον Σετ
#
: 4-bit immediate constant
Α.1.7 Φορµατ
(#data4)
This part specifies the format of the instructions as
it is represented in the ASM166 assembler listing. QQ
: 8-bit word address of the
Figure A.1 shows the reference between the insource bit (bitoff)
struction format representation of the assembler rr
: 8-bit relative target address
and the corr
esponding internal organization of
word offset (rel)
such an instruction format (N = nibble = 4 bits).
RR
: 8-bit word address reg
Symbols are used as follows to describe the inZZ
: 8-bit word address of the
struction formats:
destination bit (bitoff)
00h through FFh : Instruction Opcodes
##
: 8-bit immediate constant
0, 1
: Constant Values
(#data8)
:....
: Each of the 4 characters
@@
: 8-bit immediate constant
immediatelyfollowinga colon
(#mask8)
represents a single bit
MM MM
: 16-bit address (mem or caddr;
:..ii
: 2-bit short GPR address (Rwi)
low byte, high byte)
:..ss
: 2-bit code segment number
## ##
: 16-bit immediate constant
(seg)
(#data16; low byte, high byte)
:.###
: 3-bit immediate constant
(#data3)
Α.1.8 Νυµβερ οφ Βψτεσ
c
: 4-bit condition code specifiSpecifies the size of an instruction in bytes. All
cation (cc)
ST10x166 instructions consist of either 2 or 4
n
: 4-bit short GPR address
bytes. Regardingthe instruction size, all instruc(Rwn or Rbn)
tions can be classified as either single word or double word instructions.
m
: 4-bit short GPR address
(Rwm or Rbm)
q
: 4-bit position of the source
Α.2 ΣΙΝΓΛΕ ΙΝΣΤΡΥΧΤΙΟΝ ∆ΕΣΧΡΙΠΤΙΟΝ
bit within the word specified
by QQ
The following section contains a detailled descripz
: 4-bit position of the destintion of each single instruction of the ST10x166 in
alphabetical order.
ation bit within the word
specified by ZZ
4/84

Α − Ινστρυχτιον Σετ
Α∆∆
Α∆∆
Ιντεγερ Αδδιτιον
Α∆∆
οπ1, οπ2
OPERATION
(op1)⇐ (op1) + (op2)
DATA TYPES WORD
Performs a 2’s complement binary addition of the source operand specified by op2 and the
destination operand specified by op1. The sum is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
*
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the specified data type.
Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ΒΣΟ/Τασκινγ
Μνεµονιχ
ADD
ADD
ADD
ADD
ADD
ADD
ADD
Οπερανδσ
Rwn,Rwm
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn,#data3
reg,#data16
reg,mem
mem,reg
Φορµατ
00 nm
08 n:10ii
08 n:11ii
08 n:0###
06 RR ## ##
02 RR MM MM
04 RR MM MM
Βψτεσ
2
2
2
2
4
4
4
5/84

Α − Ινστρυχτιον Σετ
Α∆∆Β
Α∆∆Β
Ιντεγερ Αδδιτιον
Α∆∆Β
οπ1, οπ2
OPERATION
(op1)⇐ (op1) + (op2)
DATA TYPES BYTE
Performs a 2’s complement binary addition of the source operand specified by op2 and the
destination operand specified by op1. The sum is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
*
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the specified data type.
Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ADDB
ADDB
ADDB
ADDB
ADDB
ADDB
ADDB
ΒΣΟ/Τασκινγ
Μνεµονιχ
ADD
ADD
ADD
ADD
ADD
ADD
ADD
Οπερανδσ
Rwn,Rwm
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn,#data3
reg,#data16
reg,mem
mem,reg
6/84

Φορµατ
01 nm
09 n:10ii
09 n:11ii
09 n:0###
07 RR ## ##
03 RR MM MM
05 RR MM MM
Βψτεσ
2
2
2
2
4
4
4
Α − Ινστρυχτιον Σετ
Α∆∆Χ
Α∆∆Χ
Ιντεγερ Αδδιτιον ωιτη Χαρρψ
Α∆∆Χ
οπ1, οπ2
OPERATION
(op1)⇐ (op1) + (op2) + (C)
DATA TYPES WORD
Performs a 2’s complement binary addition of the source operand specified by op2, the
destination operand specified by op1 and the prev
iously generated carry bit. The sum is
then stored in op1.
This instruction can be used to perform multiple precision arithmetic.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
S
*
*
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and previous Z flag was set. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the specified data type.
Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ΒΣΟ/Τασκινγ
Μνεµονιχ
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
Οπερανδσ
Rwn,Rwm
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn,#data3
reg,#data16
reg,mem
mem,reg
Φορµατ
10 nm
18 n:10ii
18 n:11ii
18 n:0###
16 RR ## ##
12 RR MM MM
12 RR MM MM
Βψτεσ
2
2
2
2
4
4
4
7/84

Α − Ινστρυχτιον Σετ
Α∆∆ΧΒ
Α∆∆ΧΒ
Ιντεγερ Αδδιτιον ωιτη Χαρρψ
Α∆∆ΧΒ οπ1, οπ2
OPERATION
(op1)⇐ (op1) + (op2) + (C)
DATA TYPES BYTE
Performs a 2’s complement binary addition of the source operand specified by op2, the
destination operand specified by op1 and the prev
iously generated carry bit. The sum is
then stored in op1. This instruction can be used to perform multiple precision arithmetic.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
S
*
*
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and previous Z flag was set. Cleared otherwise.
Set if an arithmetic overflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a carry is generated from the most significant bit of the specified data type.
Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ADDCB
ADDCB
ADDCB
ADDCB
ADDCB
ADDCB
ADDCB
ΒΣΟ/Τασκινγ
Μνεµονιχ
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
Οπερανδσ
Rwn,Rwm
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn,#data3
reg,#data
16
reg,mem
mem,reg
8/84

Φορµατ
11 nm
19 n:10ii
19 n:11ii
19 n:0###
17 RR ## ##
13 RR MM MM
15 RR MM MM
Βψτεσ
2
2
2
2
4
4
4
Α − Ινστρυχτιον Σετ
ΑΝ∆
ΑΝ∆
Λογιχαλ ΑΝ∆
ΑΝ∆
οπ1, οπ2
OPERATION
(op1)⇐ (op1)∧ (op2)
DATA TYPES WORD
Performs a bitwise logical AND of the source operand specified by op2 and the destination
operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
0
0
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
AND
AND
AND
AND
AND
AND
AND
ΒΣΟ/Τασκινγ
Μνεµονιχ
AND
AND
AND
AND
AND
AND
AND
Οπερανδσ
Rwn,Rwm
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn,#data3
reg,#data16
reg,mem
mem,reg
Φορµατ
60 nm
68 n:10ii
68 n:11ii
68 n:0###
66 RR ## ##
62 RR MM MM
64 RR MM MM
Βψτεσ
2
2
2
2
4
4
4
9/84

Α − Ινστρυχτιον Σετ
ΑΝ∆Β
ΑΝ∆Β
Λογιχαλ ΑΝ∆
ΑΝ∆Β
οπ1, οπ2
OPERATION
(op1)⇐ (op1)∧ (op2)
DATA TYPES BYTE
Performs a bitwise logical AND of the source operand specified by op2 and the destination
operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
0
0
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ANDB
ANDB
ANDB
ANDB
ANDB
ANDB
ANDB
ΒΣΟ/Τασκινγ
Μνεµονιχ
AND
AND
AND
AND
AND
AND
AND
Οπερανδσ
Rwn,Rwm
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn,#data3
reg,#data16
reg,mem
mem,reg
10/84

Φορµατ
61 nm
69 n:10ii
69 n:11ii
69 n:0###
67 RR ## ##
63 RR MM MM
65 RR MM MM
Βψτεσ
2
2
2
2
4
4
4
Α − Ινστρυχτιον Σετ
ΑΣΗΡ
ΑΣΗΡ
Αριτηµετιχ Σηιφτ Ριγητ
ΑΣΗΡ
οπ1, οπ2
OPERATION
(count)⇐ (op2)
(V) ⇐ 0
(C) ⇐ 0
DO WHILE (count)≠ 0
(V) ⇐ (C) ∨ (V)
(C) ⇐ (op10)
(op1n) ⇐ (op1n+1)n=0 to 14
(count)⇐ (count) - 1
END WHILE
DATA TYPES WORD
Arithmetically shifts the destination word operand op1 right by as many times as specified
in the source operand op2. To preserve the sign oforiginal
the
operand op1, the most significant bits of the result are filled with zeros if the
iginalMSB
or
was a 0 or with ones if the
originalMSB was a 1. The Overflow flag is used asRounding
a
flag. The LSB is shifted into
the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count
control, only the least significant 4 bits are used.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
S
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if in any cycle of the shift operation a 1 is shifted out of the Carry flag. Cleared for
a shift count of zero.
The Carry flag is set according to the last LSB shifted out of op1. Cleared for a shift
count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ASHR
ASHR
ΒΣΟ/Τασκινγ
Μνεµονιχ
ASHR
ASHR
Οπερανδσ
Rwn,Rwm
Rwn,#data4
Φορµατ
AC nm
BC #n
Βψτεσ
2
2
11/84

Α − Ινστρυχτιον Σετ
ΒΑΝ∆
ΒΑΝ∆
Βιτ Λογιχαλ ΑΝ∆
ΒΑΝ∆
οπ1, οπ2
OPERATION
(op1)⇐ (op1)∧ (op2)
DATA TYPES BIT
Performs a single bit logical AND of the source bit specified by operand op2 with the destination bit specified by operand op1. The ANDed result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
NOR
OR
AND
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
INSTRUCTION FORMAT
Μνεµονιχ
BAND
ΒΣΟ/Τασκινγ
Μνεµονιχ
AND
Οπερανδσ
Φορµατ
6A QQ ZZ qz
bitaddr
Z.z,bitaddr
Q.q
12/84

Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΒΧΛΡ
ΒΧΛΡ
Βιτ Χλεαρ
ΒΧΛΡ
οπ1
OPERATION
(op1)⇐ 0
DATA TYPES BIT
Clears the bit specified in operand op1. This instruction is primarily used
peripheral
for
and
system control.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
B
0
0
B
Always cleared.
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
INSTRUCTION FORMAT
Μνεµονιχ
BCLR
ΒΣΟ/Τασκινγ
Μνεµονιχ
BCLR
Οπερανδσ
bitaddr
Q.q
Φορµατ
qE QQ
Βψτεσ
2
13/84

Α − Ινστρυχτιον Σετ
ΒΧΜΠ
ΒΧΜΠ
Βιτ το Βιτ Χοµπαρε
ΒΧΜΠ
οπ1, οπ2
OPERATION
(op1)⇔ (op2)
DATA TYPES BIT
Performs a single bit comparison of the source bit specified by operand op1 to the source
bit specified by operand op2. No result is written by this instruction. Only
condition
the
codes are updated.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
NOR
OR
AND
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
INSTRUCTION FORMAT
Μνεµονιχ
BCMP
ΒΣΟ/Τασκινγ
Μνεµονιχ
CMP
Οπερανδσ
Φορµατ
2A QQ ZZ qz
bitaddr
Z.z, bitaddr
Q.q
14/84

Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΒΦΛ∆Η
ΒΦΛ∆Η
Βιτ Φιελδ Ηιγη Βψτε
ΒΦΛ∆Η οπ1, οπ2, οπ3
OPERATION
(tmp)⇐ (op1)
(high byte (tmp))⇐ ((high byte (tmp)∧ ¬ op2)∨ op3)
(op1)⇐ (tmp)
DATA TYPES WORD
Replaces those bits in the high byte of the destination word operand op1 which are selected by an ‘1’ in the AND mask op2 with the bits at the esponding
corr
positions in the OR
mask specified by op3.
Note: Bits which are masked off by a ‘0’ in the AND mask op2 may be unintent
ionally altered if the corresponding bit in the OR mask op3 contains a ‘1’.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
0
0
*
Always cleared.
Set if the word result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the word result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
BFLDH
ΒΣΟ/Τασκινγ
Μνεµονιχ
BFLDH
Οπερανδσ
Φορµατ
bitoff
Q, #mask8, #data8 1A QQ ## @@
Βψτεσ
4
15/84

Α − Ινστρυχτιον Σετ
ΒΦΛ∆Λ
ΒΦΛ∆Λ
Βιτ Φιελδ Λοω Βψτε
ΒΦΛ∆Λ οπ1, οπ2, οπ3
OPERATION
(tmp)⇐ (op1)
(low byte (tmp))⇐ ((low byte (tmp)∧ ¬ op2)∨ op3)
(op1) ⇐ (tmp)
DATA TYPES WORD
Replaces those bits in the low byte of the destination word operand op1 which are selected
by an ‘1’ in the AND mask op2 with the bits at theresponding
cor
positions in the OR mask
specified by op3.
Note: Bits which are masked off by a ‘0’ in the AND mask op2 may be unintent
ionally altered if the corresponding bit in the OR mask op3 contains a ‘1’.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
0
0
*
Always cleared.
Set if the word result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the word result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
BFLDL
ΒΣΟ/Τασκινγ
Μνεµονιχ
BFLDL
Οπερανδσ
Φορµατ
bitoff
Q, #mask8, #data8 0A QQ @@ ##
16/84

Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΒΜΟς
ΒΜΟς
Βιτ το Βιτ Μοϖε
ΒΜΟς
οπ1, οπ2
OPERATION
(op1)⇐ (op2)
DATA TYPES BIT
Moves a single bit from the source operand specified by op2 into the destination
operand
specified by op1. The source bit is examined and the flags are updated dingl
accor
y.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
B
0
0
B
Always cleared.
Contains the logical negation of the previous state of the source bit.
Always cleared.
Always cleared.
Contains the previous state of the source bit.
INSTRUCTION FORMAT
Μνεµονιχ
BMOV
ΒΣΟ/Τασκινγ
Μνεµονιχ
MOV
Οπερανδσ
Φορµατ
4A QQ ZZ qz
bitaddrZ.z, bitaddrQ.q
Βψτεσ
4
17/84

Α − Ινστρυχτιον Σετ
ΒΜΟςΝ
ΒΜΟςΝ
Βιτ το Βιτ Μοϖε ανδ Νεγατε
ΒΜΟςΝ οπ1, οπ2
OPERATION
(op1)⇐ ¬ (op2)
DATA TYPES BIT
Moves the complement of ainglebit
s
from the source
operand spec
ified by op2 into the
destination operand specified by op1. The source bit is examined and the flags are updated accordingly.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
B
0
0
B
Always cleared.
Contains the logical negation of the previous state of the source bit.
Always cleared.
Always cleared.
Contains the previous state of the source bit.
INSTRUCTION FORMAT
Μνεµονιχ
BMOVN
ΒΣΟ/Τασκινγ
Μνεµονιχ
BMOVN
Οπερανδσ
Φορµατ
3A QQ ZZ qz
bitaddr
Z.z, bitaddr
Q.q
18/84

Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΒΟΡ
ΒΟΡ
Βιτ Λογιχαλ ΟΡ
ΒΟΡ
οπ1, οπ2
OPERATION
(op1)⇐ (op1)∨ (op2)
DATA TYPES BIT
Performs a single bit logical OR of the source bit specified by operand op2 with the destination bit specified by operand op1. The ORed result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
NOR
OR
AND
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
INSTRUCTION FORMAT
Μνεµονιχ
BOR
ΒΣΟ/Τασκινγ
Μνεµονιχ
OR
Οπερανδσ
Φορµατ
5A QQ ZZ qz
bitaddrZ.z, bitaddrQ.q
Βψτεσ
4
19/84

Α − Ινστρυχτιον Σετ
ΒΣΕΤ
ΒΣΕΤ
Βιτ Σετ
ΒΣΕΤ
οπ1
OPERATION
(op1)⇐ 1
DATA TYPES BIT
Sets the bit specified
in operand op1. T
his instruction is primarily used foripheral
per
and
system control.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
B
0
0
B
Always cleared
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
INSTRUCTION FORMAT
Μνεµονιχ
BSET
ΒΣΟ/Τασκινγ
Μνεµονιχ
BSET
Οπερανδσ
bitaddr
Q.q
Φορµατ
qF QQ
20/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΒΞΟΡ
ΒΞΟΡ
Βιτ Λογιχαλ ΞΟΡ
ΒΞΟΡ
οπ1, οπ2
OPERATION
(op1)⇐ (op1)⊕ (op2)
DATA TYPES BIT
Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2
with the destination bit specified by operand op1. The XORed result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
NOR
OR
AND
XOR
Always cleared.
Contains the logical NOR of the two specified bits.
Contains the logical OR of the two specified bits.
Contains the logical AND of the two specified bits.
Contains the logical XOR of the two specified bits.
INSTRUCTION FORMAT
Μνεµονιχ
BXOR
ΒΣΟ/Τασκινγ
Μνεµονιχ
XOR
Οπερανδσ
Φορµατ
7A QQ ZZ qz
bitaddrZ.z, bitaddrQ.q
Βψτεσ
4
21/84

Α − Ινστρυχτιον Σετ
ΧΑΛΛΑ
ΧΑΛΛΑ
Χαλλ Συβρουτινε Αβσολυτε
ΧΑΛΛΑ οπ1, οπ2
OPERATION
IF (op1) THEN
(SP) ⇐ (SP) - 2
((SP)) ⇐ (IP)
(IP) ⇐ op2
ELSE
next instruction
END IF
If the condition specified by op1 is met, a branch to the absolute memory location specified
by the second operand op2 is taken. The value of the instruction pointer, IP, is placed onto
the system stack. Because the IP always points to the instruction
ollowing
f
he
t branch instruction, the value stored on the system stack represents the return addresscalling
of the
routine. If the o
cndition isnot met, no action is taken and the next instruction is executed
normally.
CONDITION CODES See Table A.1.
FLAGS
E
Z
V
C
N
-
-
-
-
-
E
Z
V
C
N
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
CALLA
ΒΣΟ/Τασκινγ
Μνεµονιχ
CALL
Οπερανδσ
cc,caddr
22/84

Φορµατ
CA c0 MM MM
Βψτεσ
4
Α − Ινστρυχτιον Σετ
Χονδιτιον Χοδεσ
Α−1. Χονδιτιον Χοδε Τεστσ φορ Βρανχη ανδ Χαλλ Ινστρυχτιονσ
Χονδιτιον
Χοδε
Μνεµονιχσ
χχ
Τεστ
∆εσχριπτιον
Χονδιτιον
Χοδε
Νυµβερ
χ
cc_UC
1 =1
Uncondit
ional
0h
cc_Z
Z =1
Zero
2h
cc_NZ
Z =0
Not zero
3h
cc_V
V =1
Overflow
4h
cc_NV
V =0
No overflow
5h
cc_N
N =1
Negative
6h
cc_NN
N=0
Not negative
7h
cc_C
C =1
Carry
8h
cc_NC
C=0
No carry
9h
cc_EQ
Z =1
Equal
2h
cc_NE
Z=0
Notequal
cc_ULT
C =1
Unsigned less than
cc_ULE
(ZVC) = 1
Unsigned less than or
equal
Fh
cc_UGE
C =0
Unsigned greater than or
equal
9h
cc_UGT
(ZVC) = 0
Unsigned greater than
Eh
cc_SLT
(N⊕V) = 1
Signed less than
Ch
cc_SLE
(ZV(N⊕V)) = 1
Signed less than or
equal
Bh
cc_SGE
(N⊕V) = 0
Signed greater than or
equal
Dh
cc_SGT
(ZV(N⊕V)) = 0
Signed greater than
cc_NET
(ZVE) = 0
Not equal AND not end of table
3h
8h
Ah
1h
23/84

Α − Ινστρυχτιον Σετ
ΧΑΛΛΙ
ΧΑΛΛΙ
Χαλλ Συβρουτινε Ινδιρεχτ
CALLI
op1, op2
OPERATION
IF (op1) THEN
(SP) ⇐ (SP) - 2
((SP)) ⇐ (IP)
(IP) ⇐ (op2)
ELSE
next instruction
END IF
If the condition specified by op1 is met, a branch to the location specified indirectly by the
second operand, op2, is taken. The value of the instruction pointer, IP, is placed onto the
system stack. Because the IP always points to the instruction
followingthe branch instruction, the value stored on the system stack represents the return address of the calling routine. If the condition is not met, no action is taken and the next instruction is executed
normally.
Condition Codes
See Table A.1.
FLAGS
E
Z
V
C
N
-
-
-
-
-
E
Z
V
C
N
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
CALLI
ΒΣΟ/Τασκινγ
Μνεµονιχ
CALL
Οπερανδσ
cc,[Rw
n]
Φορµατ
AB cn
24/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΧΑΛΛΡ
ΧΑΛΛΡ
Χαλλ Συβρουτινε Ρελατιϖε
ΧΑΛΛΡ οπ1
OPERATION
(SP) ⇐ (SP) - 2
((SP)) ⇐ (IP)
(IP) ⇐ (IP) + sign_extend (op1)
A branch is taken to the location specified by the instruction pointer, IP, plus the relative
displacement, op1. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value of the instruction pointer (IP)
is placed onto the system stack. Because the IP always points to the instruction
following
the branch instruction, the value stored on the system stack represents the return address
of the calling routine. The value of the IP used in the target address calculation is the address of the instruction
ollowing
f
the CALLR instruction.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
CALLR
ΒΣΟ/Τασκινγ
Μνεµονιχ
CALL
Οπερανδσ
rel
Φορµατ
BB rr
Βψτεσ
2
25/84

Α − Ινστρυχτιον Σετ
ΧΑΛΛΣ
ΧΑΛΛΣ
Χαλλ Ιντερ−σεγµεντ Συβρουτινε
ΧΑΛΛΣ οπ1, οπ2
OPERATION
(SP) ⇐ (SP) - 2
((SP)) ⇐ (CSP)
(SP) ⇐ (SP) - 2
((SP)) ⇐ (IP)
(CSP) ⇐ op1
(IP) ⇐ op2
A branch is taken to the absolute location specified by op2 within the segment specified by
op1. The value of the instruction pointer (IP) is placed onto the system stack. Because the
IP always points to the instruction
ollowing
f
the branch instruction, the value stored on the
system stack represents the return address to the
alling
c routine. The previous value of the
CSP is also placed on the system stack to insure correct return to the calling segment.
FLAGS
C
N
V
Z
E
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
CALLS
ΒΣΟ/Τασκινγ
Μνεµονιχ
CALL
Οπερανδσ
seg,caddr
26/84

Φορµατ
DA 0:00ss MM MM
Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΧΜΠ
ΧΜΠ
Ιντεγερ Χοµπαρε
ΧΜΠ
οπ1, οπ2
OPERATION
(op1)⇔ (op2)
DATA TYPES WORD
The source operand specified by op1 is compared to the source operand specified by op2
by performing a 2’s complement binary subtraction of op2 from op1. The flags are set according to the rules of subtraction. The
operandsremainunchanged.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if the result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CMP
CMP
CMP
CMP
CMP
CMP
ΒΣΟ/Τασκινγ
Μνεµονιχ
CMP
CMP
CMP
CMP
CMP
CMP
Οπερανδσ
Rwn,Rwm
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn,#data3
reg,#data16
reg,mem
Φορµατ
40 nm
48 n:10ii
48 n:11ii
48 n:0###
46 RR ## ##
42 RR MM MM
Βψτεσ
2
2
2
2
4
4
27/84

Α − Ινστρυχτιον Σετ
ΧΜΠΒ
ΧΜΠΒ
Ιντεγερ Χοµπαρε
ΧΜΠΒ
οπ1, οπ2
OPERATION
(op1)⇔ (op2)
DATA TYPES BYTE
The source operand specified by op1 is compared to the source operand specified by op2
by performing a 2’s complement binary subtraction of op2 from op1. The flags are set according to the rules of subtraction. The
operandsremainunchanged.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if the result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CMPB
CMPB
CMPB
CMPB
CMPB
CMPB
ΒΣΟ/Τασκινγ
Μνεµονιχ
CMP
CMP
CMP
CMP
CMP
CMP
Οπερανδσ
Rbn,Rbm
Rbn,[Rwi]
Rbn,[Rwi+]
Rbn,#data3
reg,#data16
reg,mem
28/84

Φορµατ
41 nm
49 n:10ii
49 n:11ii
49 n:0###
47 RR ## ##
43 RR MM MM
Βψτεσ
2
2
2
2
4
4
Α − Ινστρυχτιον Σετ
ΧΜΠ∆1
ΧΜΠ∆1
Ιντεγερ Χοµπαρε ανδ ∆εχρεµεντ βψ 1
ΧΜΠ∆1 οπ1, οπ2
OPERATION
(op1)⇔ (op2)
(op1)⇐ (op1) - 1
DATA TYPES WORD
This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing
a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY
GPR registers. Once the subtraction has completed,
he operandop1
t
is decremented by
one. Using the set flags, a branch instruction can then be used
onjun
in cction with this instruction to form common high level
languageFOR loops of any range.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if the result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CMPD1
CMPD1
CMPD1
ΒΣΟ/Τασκινγ
Μνεµονιχ
CMPD1
CMPD1
CMPD1
Οπερανδσ
Rwn,#data4
Rwn,#data16
Rwn,mem
Φορµατ
A0 #n
A6 Fn ## ##
A2 Fn MM MM
Βψτεσ
2
4
4
29/84

Α − Ινστρυχτιον Σετ
ΧΜΠ∆2
ΧΜΠ∆2
Ιντεγερ Χοµπαρε ανδ ∆εχρεµεντ βψ 2
ΧΜΠ∆2 οπ1, οπ2
OPERATION
(op1)⇔ (op2)
(op1)⇐ (op1) - 2
DATA TYPES WORD
This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing
a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY
GPR registers. Once the subtraction has completed,
he operandop1
t
is decremented by
two. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level
languageFOR loops of any range.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if the result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CMPD2
CMPD2
CMPD2
ΒΣΟ/Τασκινγ
Μνεµονιχ
CMPD2
CMPD2
CMPD2
Οπερανδσ
Rwn,#data4
Rwn,#data16
Rwn,mem
30/84

Φορµατ
B0 #n
B6 Fn ## ##
B2 Fn MM MM
Βψτεσ
2
4
4
Α − Ινστρυχτιον Σετ
ΧΜΠΙ1
ΧΜΠΙ1
Ιντεγερ Χοµπαρε ανδ Ινχρεµεντ βψ 1
ΧΜΠΙ1
οπ1, οπ2
OPERATION
(op1)⇔ (op2)
(op1)⇐ (op1) + 1
DATA TYPES WORD
This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing
a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY
GPR registers. Once the subtraction has com
pleted, the operandop1 is incremented by
one. Using the set flags, a branch instruction can then be used
onjun
in cction with this instruction to form common high level
languageFOR loops of any range.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CMPI1
CMPI1
CMPI1
ΒΣΟ/Τασκινγ
Μνεµονιχ
CMPI1
CMPI1
CMPI1
Οπερανδσ
Rwn,#data4
Rwn,#data16
Rwn,mem
Φορµατ
80 #n
86 Fn ## ##
82 Fn MM MM
Βψτεσ
2
4
4
31/84

Α − Ινστρυχτιον Σετ
ΧΜΠΙ2
ΧΜΠΙ2
Ιντεγερ Χοµπαρε ανδ Ινχρεµεντ βψ 2
ΧΜΠΙ2
οπ1, οπ2
OPERATION
(op1)⇔ (op2)
(op1)⇐ (op1) + 2
DATA TYPES WORD
This instruction is used to enhance the performance and flexibility of loops. The source operand specified by op1 is compared to the source operand specified by op2 by performing
a 2’s complement binary subtraction of op2 from op1. Operand op1 may specify ONLY
GPR registers. Once the subtraction has com
pleted, the operandop1 is incremented by
two. Using the set flags, a branch instruction can then be used in conjunction with this instruction to form common high level
languageFOR loops of any range.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CMPI2
CMPI2
CMPI2
ΒΣΟ/Τασκινγ
Μνεµονιχ
CMPI2
CMPI2
CMPI2
Οπερανδσ
Rwn,#data4
Rwn,#data16
Rwn,mem
32/84

Φορµατ
90 #n
96 Fn ## ##
92 Fn MM MM
Βψτεσ
2
4
4
Α − Ινστρυχτιον Σετ
ΧΠΛ
ΧΠΛ
Ιντεγερ Ονεσ Χοµπλεµεντ
ΧΠΛ
οπ1
OPERATION
(op1)⇐ ¬ (op1)
DATA TYPES WORD
Performs a 1’s complement of the source operand specified by op1. The result is stored
back into op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
0
0
*
Set if the value of the source operand op1 represents the lowest possible negative
number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CPL
ΒΣΟ/Τασκινγ
Μνεµονιχ
CPL
Οπερανδσ
Rwn
Φορµατ
91 n0
Βψτεσ
2
33/84

Α − Ινστρυχτιον Σετ
ΧΠΛΒ
ΧΠΛΒ
Ιντεγερ Ονεσ Χοµπλεµεντ
ΧΠΛΒ
οπ1
OPERATION
(op1)⇐ ¬ (op1)
DATA TYPES BYTE
Performs a 1’s complement of the source operand specified by op1. The result is stored
back into op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
0
0
*
Set if the value of the source operand op1 represents the lowest possible negative
number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
CPLB
ΒΣΟ/Τασκινγ
Μνεµονιχ
CPL
Οπερανδσ
Rbn
Φορµατ
B1 n0
34/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
∆ΙΣΩ∆Τ
∆ΙΣΩ∆Τ
∆ισαβλε Ωατχηδογ Τιµερ
∆ΙΣΩ∆Τ
OPERATION
Disable Watchdog Timer
This instruction disables the Watchdog Timer. The Watchdog Timer
enabledby
is
a reset.
The DISWDT instruction allows the Watchdog Timer todisabledfor
be
applications which
do not require a watchdog function.
Followinga reset, this instruction can be executed at
any time until either a Service Watchdog Timer instruction (SRVWDT) or an End of Initialization instruction (EINIT) are executed. Once one of these instructions has been executed, the DISWDT instruction will have no effect. To insure that this instruction is not
accidentally executed, it is implemented as a protected instruction.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
DISWDT
ΒΣΟ/Τασκινγ
Μνεµονιχ
DISWDT
Οπερανδσ
Φορµατ
A5 5A A5 A5
Βψτεσ
4
35/84

Α − Ινστρυχτιον Σετ
∆Ις
∆Ις
16/16 Σιγνεδ ∆ιϖισιον
∆Ις
οπ1
OPERATION
(MDL)⇐ (MDL) / (op1)
(MDH) ⇐ (MDL) mod (op1)
DATA TYPES WORD
Performs a signed 16-bit by 16-bit division of the low order word stored in the MD register
by the source word operand op1. The quotient is then stored in the low order word of the
MD register, MDL, and the rem
ainder is stored in the high order word of the MD register,
MDH.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
0
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred. Overflow occurs when the result can not be
represented in a word data type or if the divisor, op1, was 0. Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
DIV
ΒΣΟ/Τασκινγ
Μνεµονιχ
DIV
Οπερανδσ
Rwn
Φορµατ
4B nn
36/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
∆ΙςΛ
∆ΙςΛ
32/16 Σιγνεδ ∆ιϖισιον
∆ΙςΛ
οπ1
OPERATION
(MDL)⇐ (MD) / (op1)
(MDH) ⇐ (MD) mod (op1)
DATA TYPES WORD, DOUBLE WORD
Performs an extended signed 32-bit by 16-bit division of the two words stored in the MD
register by the source word operand op1. The signed quotient is then stored in the low order word of the MD register, MDL, and the remainder is stored in the high order word of the
MD register, MDH.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
0
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred. Overflow occurs when the result can not be
represented in a word data type or if the divisor, op1, was 0. Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
DIVL
ΒΣΟ/Τασκινγ
Μνεµονιχ
DIVL
Οπερανδσ
Rwn
Φορµατ
6B nn
Βψτεσ
2
37/84

Α − Ινστρυχτιον Σετ
∆ΙςΛΥ
∆ΙςΛΥ
32/16 Υνσιγνεδ ∆ιϖισιον
∆ΙςΛΥ
οπ1
OPERATION
(MDL)⇐ (MD) / (op1)
(MDH) ⇐ (MD) mod (op1)
DATA TYPES WORD, DOUBLE WORD
Performs an extended
unsigned32-bit by 16-bit division of the two words stored in the MD
register by the source word operand op1. The unsigned quotient is then stored in the low
order word of the MD register, MDL, and the remainder is stored in the high order word of
the MD register, MDH.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
0
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred. Overflow occurs when the result can not be
represented in a word data type or if the divisor, op1, was 0. Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
DIVLU
ΒΣΟ/Τασκινγ
Μνεµονιχ
DIVLU
Οπερανδσ
Rwn
Φορµατ
7B nn
38/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
∆ΙςΥ
∆ΙςΥ
16/16 Υνσιγνεδ ∆ιϖισιον
∆ΙςΥ
οπ1
OPERATION
(MDL)⇐ (MDL) / (op1)
(MDH) ⇐ (MDL) mod (op1)
DATA TYPES WORD
Performs anunsigned16-bit by 16-bit division of the low order word stored in the MD register by the source word operand op1. The
unsignedquotient is then stored in the low order
word of the MD register, MDL, and the remainder is stored in the high order word in the MD
register, MDH.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
0
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurred. Overflow occurs when the result can not be
represented in a word data type or if the divisor, op1, was 0. Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
DIVU
ΒΣΟ/Τασκινγ
Μνεµονιχ
DIVU
Οπερανδσ
Rwn
Φορµατ
5B nn
Βψτεσ
2
39/84

Α − Ινστρυχτιον Σετ
ΕΙΝΙΤ
ΕΙΝΙΤ
Ενδ οφ Ινιτιαλιζατιον
ΕΙΝΙΤ
OPERATION
END of INITIALIZATION
This instruc
tion is used to signal
the end of the initialization portion of a program. After a
reset, the reset output pin RSTOUT is pulled low. It remains low until the EINIT instruction
has been executed at which time it goes high. This enables the program to signal the external circuitrythat it has successfully
initializedthe microcontroller. After the EINIT instruction has been executed, exec
ution of the DisableWatchdog Timer instruction (DISWDT)
has no effect. To insure that this instruction is not accidentally executed, it is implemented
as a protected instruction.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
EINIT
ΒΣΟ/Τασκινγ
Μνεµονιχ
EINIT
Οπερανδσ
Φορµατ
B5 4A B5 B5
40/84

Βψτεσ
4
Α − Ινστρυχτιον Σετ
Ι∆ΛΕ
Ι∆ΛΕ
Εντερ Ιδλε Μοδε
Ι∆ΛΕ
OPERATION
Enter Idle Mode
This instruction causes the part to enter the idle mode. In this mode, the CPU
powered
is
down while theperipheralsremain u
r nning. It remains powered down untilperipheral
a
interrupt or external interrupt occurs. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
IDLE
ΒΣΟ/Τασκινγ
Μνεµονιχ
IDLE
Οπερανδσ
Φορµατ
87 78 87 87
Βψτεσ
4
41/84

Α − Ινστρυχτιον Σετ
ϑΒ
ϑΒ
Ρελατιϖε ϑυµπ ιφ Βιτ Σετ
ϑΒ
οπ1, οπ2
OPERATION
IF (op1) = 1 THEN
(IP) ⇐ (IP) + sign_extend (op2)
ELSE
next instruction
END IF
DATA TYPES BIT
If the bit specified by op1 is set, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value
of the IP in the target address calculation is the address of the instruction
ollowing
f the JB
instruction. If the specified bit is clear, the instruction
ollowingthe
f
JB instruction is executed.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
JB
ΒΣΟ/Τασκινγ
Μνεµονιχ
JB
Οπερανδσ
bitaddr
Q.q, rel
42/84

Φορµατ
8A QQ rr q0
Βψτεσ
4
Α − Ινστρυχτιον Σετ
ϑΒΧ
ϑΒΧ
Ρελατιϖε ϑυµπ ιφ Βιτ Σετ ανδ Χλεαρ Βιτ
ϑΒΧ
οπ1, οπ2
OPERATION
IF (op1) = 1 THEN
(op1)⇐ 0
(IP) ⇐ (IP) + sign_extend (op2)
ELSE
(op1)⇐ 0
next instruction
END IF
DATA TYPES BIT
If the bit specified by op1 is set, program execution continues at the location of the instruction pointer, IP, plus the specified displacement,op2. The bit specified by op1 is cleared
allowing implementation of semaphore operations. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value
of the IP used in the target addressalculation
c
isthe address of the instruc
tion followi
ng
the JBC instruction. If the specified bit was clear, the instruction
ollowing
f the JBC instruction is executed.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
B
0
0
B
Always cleared.
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
INSTRUCTION FORMAT
Μνεµονιχ
JBC
ΒΣΟ/Τασκινγ
Μνεµονιχ
JBC
Οπερανδσ
bitaddr
Q.q, rel
Φορµατ
AA QQ rr q0
Βψτεσ
4
43/84

Α − Ινστρυχτιον Σετ
ϑΜΠΑ
ϑΜΠΑ
Αβσολυτε Χονδιτιοναλ ϑυµπ
ϑΜΠΑ
οπ1, οπ2
OPERATION
IF (op1) THEN
(IP) ⇐ op2
ELSE
next instruction
END IF
If the condition specified by op1 is met, a branch to the absolute address specified by op2
is taken. If the condition is not met, no action is taken, and the instruction following the
JMPA instruction is executed normally.
CONDITION CODES See Table A.2.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
JMPA
ΒΣΟ/Τασκινγ
Μνεµονιχ
JMP
Οπερανδσ
cc,caddr
44/84

Φορµατ
EA c0 MM MM
Βψτεσ
4
Α − Ινστρυχτιον Σετ
Χονδιτιον Χοδεσ
Α−2. Χονδιτιον Χοδε Τεστσ φορ Βρανχη ανδ Χαλλ Ινστρυχτιονσ
Χονδιτιον
Χοδε
Μνεµονιχσ
χχ
Τεστ
∆εσχριπτιον
Χονδιτιον
Χοδε
Νυµβερ
χ
cc_UC
1 =1
Uncondit
ional
0h
cc_Z
Z =1
Zero
2h
cc_NZ
Z =0
Not zero
3h
cc_V
V =1
Overflow
4h
cc_NV
V =0
No overflow
5h
cc_N
N =1
Negative
6h
cc_NN
N=0
Not negative
7h
cc_C
C =1
Carry
8h
cc_NC
C=0
No carry
9h
cc_EQ
Z =1
Equal
2h
cc_NE
Z=0
Notequal
cc_ULT
C =1
Unsigned less than
cc_ULE
(ZVC) = 1
Unsigned less than or
equal
Fh
cc_UGE
C =0
Unsigned greater than or
equal
9h
cc_UGT
(ZVC) = 0
Unsigned greater than
Eh
cc_SLT
(N⊕V) = 1
Signed less than
Ch
cc_SLE
(ZV(N⊕V)) = 1
Signed less than or
equal
Bh
cc_SGE
(N⊕V) = 0
Signed greater than or
equal
Dh
cc_SGT
(ZV(N⊕V)) = 0
Signed greater than
cc_NET
(ZVE) = 0
Not equal AND not end of table
3h
8h
Ah
1h
45/84

Α − Ινστρυχτιον Σετ
ϑΜΠΙ
ϑΜΠΙ
Ινδιρεχτ Χονδιτιοναλ ϑυµπ
ϑΜΠΙ
οπ1, οπ2
OPERATION
IF (op1) THEN
(IP) ⇐ (op2)
ELSE
next instruction
END IF
If the condition specified by op1 is met, a branch to the location specified indirectly by op2
is taken. If the condition is not met, no action is taken, and the next instruction is executed
normally.
CONDITION CODES See Table A.2. or A.1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
JMPI
ΒΣΟ/Τασκινγ
Μνεµονιχ
JMP
Οπερανδσ
cc,[Rwn]
Φορµατ
9C cn
46/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ϑΜΠΡ
ϑΜΠΡ
Ρελατιϖε Χονδιτιοναλ ϑυµπ
ϑΜΠΡ
οπ1, οπ2
OPERATION
IF (op1) THEN
(IP) ⇐ (IP) + sign_extend (op2)
ELSE
next instruction
END IF
If the condition specified by op1 is met, program execution continues at the location of the
instruction pointer, IP, plus the specified displacement, op2.
he displacem
T
ent is a two’s
complement number which is sign extended and counts the relative distance in words. The
value of the IP used in the target address calculation is the address of the instruction following the JMPR instruction. If the specified condition is not met, program execution continues normally with the instruction
followingthe JMPR instruction.
CONDITION CODES See Table A.2 or A.1
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
JMPR
ΒΣΟ/Τασκινγ
Μνεµονιχ
JMP
Οπερανδσ
cc, rel
Φορµατ
cD rr
Βψτεσ
2
47/84

Α − Ινστρυχτιον Σετ
ϑΜΠΣ
ϑΜΠΣ
Αβσολυτε Ιντερ−σεγµεντ ϑυµπ
ϑΜΠΣ
οπ1, οπ2
OPERATION
(CSP) ⇐ op1
(IP) ⇐ op2
Branches unconditionally to the absolute address specified by op2 within the segment
specified by op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
JMPS
ΒΣΟ/Τασκινγ
Μνεµονιχ
JMP
Οπερανδσ
seg,caddr
48/84

Φορµατ
FA 0:00ss MM MM
Βψτεσ
4
Α − Ινστρυχτιον Σετ
ϑΝΒ
ϑΝΒ
Ρελατιϖε ϑυµπ ιφ Βιτ Χλεαρ
ϑΝΒ
οπ1, οπ2
OPERATION
IF (op1)=0 THEN
(IP) ⇐ (IP) + sign_extend (op2)
ELSE
next instruction
END IF
DATA TYPES BIT
If the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, IP, plus the specified displacement, op2. The displacement is a two’s
complement number which is sign extended and counts the relative distance in words. The
value of the IP used in the target address calculation is the address of the instruction following the JNB instruction. If the specified bit is set , the instruct
ion following the JNB
instruction is executed.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
JNB
ΒΣΟ/Τασκινγ
Μνεµονιχ
JNB
Οπερανδσ
bitaddr
Q.q, rel
Φορµατ
9A QQ rr q0
Βψτεσ
4
49/84

Α − Ινστρυχτιον Σετ
ϑΝΒΣ
ϑΝΒΣ
Ρελατιϖε ϑυµπ ιφ Βιτ Χλεαρ ανδ Σετ Βιτ
ϑΝΒΣ
οπ1, οπ2
OPERATION
IF (op1)=0 THEN
(op1)⇐ 1
(IP) ⇐ (IP) + sign_extend (op2)
ELSE
(op1)⇐ 1
next instruction
END IF
DATA TYPES BIT
If the bit specified by op1 is clear, program execution continues at the location of the instruction pointer, IP, plus the spec
ified displac
ement, op2. The bit specified by op1 is set
allowing implementation of semaphore operations. The displacement is a two’s complement number which is sign extended and counts the relative distance in words. The value
of the IP used in the target address calculation is the address of the instruction
ollowinfg
the JNBS instruction. If the specified bit is set, the instruction
ollowing
f the JNBS instruction
is executed.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
B
0
0
B
Always cleared.
Contains the logical negation of the previous state of the specified bit.
Always cleared.
Always cleared.
Contains the previous state of the specified bit.
INSTRUCTION FORMAT
Μνεµονιχ
JNBS
ΒΣΟ/Τασκινγ
Μνεµονιχ
JNBS
Οπερανδσ
bitaddr
Q.q, rel
50/84

Φορµατ
BA QQ rr q0
Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΜΟς
ΜΟς
Μοϖε ∆ατα
ΜΟς
οπ1, οπ2
OPERATION
(op1)⇐ (op2)
DATA TYPES WORD
Moves the contents of the source operand specified by op2 to the location specified by the
destination operandop1. The contents of the moved data is examined, and condition
the
codes are updated accordingly.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
-
-
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if the value of the source operand op2 equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the source operand op2 is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ΒΣΟ/Τασκινγ
Μνεµονιχ
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Οπερανδσ
Rwn,Rwm
Rwn,#data4
reg,#data16
Rwn,[Rwm]
Rwn,[Rwm+]
[Rwm],Rwn
[-Rwm],Rwn
[Rwn],[Rwm]
[Rwn+],[Rwm]
[Rwn],[Rwm+]
Rwn,[Rwm+#d16]
[Rwm+#d16],Rwn
[Rwn],mem
mem,[Rwn]
reg,mem
mem,reg
Φορµατ
F0 nm
E0 #n
E6 RR ## ##
A8 nm
98 nm
B8 nm
88 nm
C8 nm
D8 nm
E8 nm
D4 nm ## ##
C4 nm ## ##
84 0n MM MM
94 0n MM MM
F2 RR MM MM
F6 RR MM MM
Βψτεσ
2
2
4
2
2
2
2
2
2
2
4
4
4
4
4
4
51/84

Α − Ινστρυχτιον Σετ
ΜΟςΒ
ΜΟςΒ
Μοϖε ∆ατα
ΜΟςΒ
οπ1, οπ2
OPERATION
(op1)⇐ (op2)
DATA TYPES BYTE
Moves the contents of the source operand specified by op2 to the location specified by the
destination operandop1. The contents of the moved data is examined, and condition
the
flags are updated accordingly.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
-
-
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if the value of the source operand op2 equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the source operand op2 is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
ΒΣΟ/Τασκινγ
Μνεµονιχ
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Οπερανδσ
Rbn,Rbm
Rbn,#data4
reg,#data16
Rbn,[Rwm]
Rbn,[Rwm+]
[Rwm],Rbn
[-Rwm],Rbn
[Rwn],[Rwm]
[Rwn+],[Rwm]
[Rwn],[Rwm+]
Rbn,[Rwm+#d16 ]
[Rwm+#d16],Rbn
[Rwn],mem
mem,[Rwn]
reg,mem
mem,reg
52/84

Φορµατ
F1 nm
E1 #n
E7 RR ## ##
A9 nm
99 nm
B9 nm
89 nm
C9 nm
D9 nm
E9 nm
F4 nm ## ##
E4 nm ## ##
A4 0n MM MM
B4 0n MM MM
F3 RR MM MM
F7 RR MM MM
Βψτεσ
2
2
4
2
2
2
2
2
2
2
4
4
4
4
4
4
Α − Ινστρυχτιον Σετ
ΜΟςΒΣ
ΜΟςΒΣ
Μοϖε Βψτε Σιγν Εξτενδ
ΜΟςΒΣ οπ1, οπ2
OPERATION
(low byte op1)⇐ (op2)
IF (op27)=1 THEN
(high byte op1)⇐ 0FFh
ELSE
(high byte op1)⇐ 00h
END IF
DATA TYPES WORD, BYTE
Moves and sign extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. The contents of the moved data are examined, and the condition flags are updated accordingly.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
-
-
*
Always cleared.
Set if the value of the source operand op2 equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the source operand op2 is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
MOVBS
MOVBS
MOVBS
ΒΣΟ/Τασκινγ
Μνεµονιχ
MOVBS
MOVBS
MOVBS
Οπερανδσ
Rbn,Rbm
reg,mem
mem,reg
Φορµατ
D0 mn
D2 RR MM MM
D5 RR MM MM
Βψτεσ
2
4
4
53/84

Α − Ινστρυχτιον Σετ
ΜΟςΒΖ
ΜΟςΒΖ
Μοϖε Βψτε Ζερο Εξτενδ
ΜΟςΒΖ οπ1, οπ2
OPERATION
(low byte op1)⇐ (op2)
(high byte op1)⇐ 00h
DATA TYPES WORD, BYTE
Moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1. The contents of the moved data are examined, and the condition flags are updated accordingly.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
-
-
0
Always cleared.
Set if the value of the source operand op2 equals zero. Cleared otherwise.
Not affected.
Not affected.
Always cleared.
INSTRUCTION FORMAT
Μνεµονιχ
MOVBZ
MOVBZ
MOVBZ
ΒΣΟ/Τασκινγ
Μνεµονιχ
MOVBZ
MOVBZ
MOVBZ
Οπερανδσ
Rbn, Rbm
reg,mem
mem,reg
54/84

Φορµατ
C0 mn
C2 RR MM MM
C5 RR MM MM
Βψτεσ
2
4
4
Α − Ινστρυχτιον Σετ
ΜΥΛ
ΜΥΛ
Σιγνεδ Μυλτιπλιχατιον
ΜΥΛ
οπ1, οπ2
OPERATION
(MD) ⇐ (op1) x (op2)
DATA TYPES WORD
Performs a 16-bit by 16-bit signed multiplication using the two words specified by operands op1 and op2 respectively. The signed 32-bit result is placed in the MD register.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
0
*
Always cleared.
Set if result equals zero. Cleared otherwise.
This bit is set if the result cannot be represented in a word data type. Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
MUL
ΒΣΟ/Τασκινγ
Μνεµονιχ
MUL
Οπερανδσ
Rwn,Rwm
Φορµατ
0B nm
Βψτεσ
2
55/84

Α − Ινστρυχτιον Σετ
ΜΥΛΥ
ΜΥΛΥ
Υνσιγνεδ Μυλτιπλιχατιον
ΜΥΛΥ
οπ1, οπ2
OPERATION
(MD) ⇐ (op1) x (op2)
DATA TYPES WORD
Performs a 16-bit by 16-bit
unsignedmultiplication using the two words specified by operands op1 and op2 respectively. The uns
igned32-bit result is placed in the MD register.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
0
*
Always cleared.
Set if result equals zero. Cleared otherwise.
This bit is set if the result cannot be represented in a word data type. Cleared otherwise.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
MULU
ΒΣΟ/Τασκινγ
Μνεµονιχ
MULU
Οπερανδσ
Rwn,Rwm
Φορµατ
1B nm
56/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΝΕΓ
ΝΕΓ
Ιντεγερ Τωοσ Χοµπλεµεντ
ΝΕΓ
οπ1
OPERATION
(op1)⇐ 0 - (op1)
DATA TYPES WORD
Performs a binary 2’s complement of the source operand specified by op1. The result is
then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
NEG
ΒΣΟ/Τασκινγ
Μνεµονιχ
NEG
Οπερανδσ
Rwn
Φορµατ
81 n0
Βψτεσ
2
57/84

Α − Ινστρυχτιον Σετ
ΝΕΓΒ
ΝΕΓΒ
Ιντεγερ Τωοσ Χοµπλεµεντ
ΝΕΓΒ
οπ1
OPERATION
(op1)⇐ 0 - (op1)
DATA TYPES BYTE
Performs a binary 2’s complement of the source operand specified by op1. The result is
then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op1 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
NEGB
ΒΣΟ/Τασκινγ
Μνεµονιχ
NEG
Οπερανδσ
Rbn
Φορµατ
A1 n0
58/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΝΟΠ
ΝΟΠ
Νο Οπερατιον
ΝΟΠ
OPERATION
No Operation
This instruction causes a null operation to be performed. A null operation causes no
change in the status of the flags.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
NOP
ΒΣΟ/Τασκινγ
Μνεµονιχ
NOP
Οπερανδσ
Φορµατ
CC 00
Βψτεσ
2
59/84

Α − Ινστρυχτιον Σετ
ΟΡ
ΟΡ
Λογιχαλ ΟΡ
ΟΡ
οπ1, οπ2
OPERATION
(op1)⇐ (op1)∨ (op2)
DATA TYPES WORD
Performs a bit-wise logical OR of the source operand specified by op2 and the destination
operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
0
0
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
OR
OR
OR
OR
OR
OR
OR
ΒΣΟ/Τασκινγ
Μνεµονιχ
OR
OR
OR
OR
OR
OR
OR
Οπερανδσ
Rwn, Rwm
Rwn,#data3
reg,#data16
Rwn,[Rwi]
Rwn,[Rwi+]
reg,mem
mem,reg
60/84

Φορµατ
70 nm
78 n:0###
76 RR ## ##
78 n:10ii
78 n:11ii
72 RR MM MM
74 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
Α − Ινστρυχτιον Σετ
ΟΡΒ
ΟΡΒ
Λογιχαλ ΟΡ
ΟΡΒ
οπ1, οπ2
OPERATION
(op1)⇐ (op1)∨ (op2)
DATA TYPES BYTE
Performs a bit-wise logical OR of the source operand specified by op2 and the destination
operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
0
0
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ORB
ORB
ORB
ORB
ORB
ORB
ORB
ΒΣΟ/Τασκινγ
Μνεµονιχ
OR
OR
OR
OR
OR
OR
OR
Οπερανδσ
Rbn,Rbm
Rbn,#data3
reg,#data16
Rbn,[Rwi]
Rbn,[Rwi+]
reg,mem
mem,reg
Φορµατ
71 nm
79 n:0###
77 RR ## ##
79 n:10ii
79 n:11ii
73 RR MM MM
75 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
61/84

Α − Ινστρυχτιον Σετ
ΠΧΑΛΛ
ΠΧΑΛΛ
Πυση Ωορδ ανδ Χαλλ Συβρουτινε Αβσολυτε
ΠΧΑΛΛ οπ1, οπ2
OPERATION
(tmp)⇐ (op1)
(SP) ⇐ (SP) - 2
((SP)) ⇐ (tmp)
(SP) ⇐ (SP) - 2
((SP)) ⇐ (IP)
(IP) ⇐ op2
DATA TYPES WORD
Pushes the word specified by operand op1 and the value of the instruction pointer, IP, onto
the system stack, and branches to the absolute memory location specified by the second
operand op2. Because the IP always points to the instruction
ollowing
f the branch instruction, the value stored on the system stack represents the return address of the calling routine.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
-
-
*
Set if the value of the pus
hed operandop1 represents the lowest possible negative
number. Cleared otherwise. Used to signal the end of a table.
Set if the value of the pushed operand op1 equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the pushed operand op1 is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
PCALL
ΒΣΟ/Τασκινγ
Μνεµονιχ
PCALL
Οπερανδσ
reg,caddr
62/84

Φορµατ
E2 RR MM MM
Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΠΟΠ
ΠΟΠ
Ποπ Ωορδ φροµ Σψστεµ Σταχκ
ΠΟΠ
οπ1
OPERATION
(tmp)⇐ ((SP))
(SP) ⇐ (SP) + 2
(op1)⇐ (tmp)
DATA TYPES WORD
Pops one word from the system stack specified by the Stack Pointer into
operand
the
specified by op1. The Stack Pointer is then incremented by two.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
-
-
*
Set if the value of thepoppedword represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if the value of thepoppedword equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the
poppedword is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
POP
ΒΣΟ/Τασκινγ
Μνεµονιχ
POP
Οπερανδσ
reg
Φορµατ
FC RR
Βψτεσ
2
63/84

Α − Ινστρυχτιον Σετ
ΠΡΙΟΡ
ΠΡΙΟΡ
Πριοριτιζε Ρεγιστερ
ΠΡΙΟΡ
οπ1, οπ2
OPERATION
(tmp)⇐ (op2)
(count)⇐ 0
DO WHILE (tmp15) ≠ 1 AND count≠ 15 AND op2≠ 0
(tmpn) ⇐ (tmpn-1)
(count)⇐ (count) +1
END WHILE
(op1)⇐ (count)
DATA TYPES WORD
This instruction stores a count value in the word
operand specif
ied by op1 indicating the
number of single bit shifts required to normalize the operand op2 so that its MSB
equalis
to one. If the source operand op2 equals zero, a zero is written to operand op1 and the
zero flag is set. Otherwise the zero flag is cleared.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
S
0
0
0
Always cleared.
Set if the source operand op2 equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Always cleared.
INSTRUCTION FORMAT
Μνεµονιχ
PRIOR
ΒΣΟ/Τασκινγ
Μνεµονιχ
PRIOR
Οπερανδσ
Rwn,Rwm
Φορµατ
2B nm
64/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΠΥΣΗ
ΠΥΣΗ
Πυση Ωορδ ον Σψστεµ Σταχκ
ΠΥΣΗ
οπ1
OPERATION
(tmp)⇐ (op1)
(SP) ⇐ (SP) - 2
((SP)) ⇐ (tmp)
DATA TYPES WORD
Moves the word specified by operand op1 to the location in the internal system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
-
-
*
Set if the value of the pushed word represents the lowest possible negative number.
Cleared otherwise. Used to signal the end of a table.
Set if the pushed word is equal to zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the pushed word is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
PUSH
ΒΣΟ/Τασκινγ
Μνεµονιχ
PUSH
Οπερανδσ
reg
Φορµατ
EC RR
Βψτεσ
2
65/84

Α − Ινστρυχτιον Σετ
ΠΩΡ∆Ν
ΠΩΡ∆Ν
Εντερ Ποωερ ∆οων Μοδε
ΠΩΡ∆Ν
OPERATION
Enter Power Down Mode
This instruction causes the part to enter the power down mode. In this mode, all peripherals and the CPU are powered down until the part is externally reset. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction. To
further control the action of this instruction, the PWRDN instruction
onlyisenabled when
the non-maskable interrupt pin
NMI)
( is in the low state. Otherwise, this instruction has no
effect.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
PWRDN
ΒΣΟ/Τασκινγ
Μνεµονιχ
PWRDN
Οπερανδσ
Φορµατ
97 68 97 97
66/84

Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΡΕΤ
ΡΕΤ
Ρετυρν φροµ Συβρουτινε
ΡΕΤ
OPERATION
(IP) ⇐ ((SP))
(SP) ⇐ (SP) + 2
Returns from a subroutine. The IPpoppedfrom
is
the system stack. Execution resumes at
the instructionollowing
f
the CALL instruction in the
alling
c routine.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
RET
ΒΣΟ/Τασκινγ
Μνεµονιχ
RET
Οπερανδσ
Φορµατ
CB 00
Βψτεσ
2
67/84

Α − Ινστρυχτιον Σετ
ΡΕΤΙ
ΡΕΤΙ
Ρετυρν φροµ Ιντερρυπτ Ρουτινε
ΡΕΤΙ
OPERATION
(IP) ⇐ ((SP))
(SP) ⇐ (SP) + 2
IF (SYSCON.SGTDIS=0) THEN
(CSP) ⇐ ((SP))
(SP) ⇐ (SP) + 2
END IF
(PSW) ⇐ ((SP))
(SP) ⇐ (SP) + 2
Returns from an interrupt routine. The PSW, IP, and CSP are popped off the system stack.
Execution resumes at the instruction which had been interrupted. The previous system
state is restored after the PSW has been
popped.The CSP is onlypoppedif segmentation
is enabled. This is indicated by the SGTDIS bit in the SYSCON register.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
S
S
S
S
S
Restored from the PSWpoppedfrom the stack.
Restored from the PSWpoppedfrom the stack.
Restored from the PSWpoppedfrom the stack.
Restored from the PSWpoppedfrom the stack.
Restored from the PSWpoppedfrom the stack.
INSTRUCTION FORMAT
Μνεµονιχ
RETI
ΒΣΟ/Τασκινγ
Μνεµονιχ
RET
Οπερανδσ
Φορµατ
FB 88
68/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΡΕΤΠ
ΡΕΤΠ
Ρετυρν φροµ Συβρουτινε ανδ Ποπ Ωορδ
ΡΕΤΠ
οπ1
OPERATION
(IP) ⇐ ((SP))
(SP) ⇐ (SP) + 2
(tmp)⇐ ((SP))
(SP) ⇐ (SP) + 2
(op1)⇐ (tmp)
DATA TYPES WORD
Returns from a subroutine. The IP is first popped from the system stack and then the next
word is popped from the system stack into the operand specified by op1. Execution resumes at the instruction
ollowing
f
the CALL instruction in the calling routine.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
-
-
-
Set if the value of the word popped into operand op1 represents the lowest possible
negative number. Cleared otherwise. Used to signal the end of a table.
Set if the value of the word
poppedinto operand op1 equals zero. Cleared otherwise.
Not affected.
Not affected.
Set if the most significant bit of the word
popped into operand op1 is set.
Cleared
otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
RETP
ΒΣΟ/Τασκινγ
Μνεµονιχ
RETP
Οπερανδσ
reg
Φορµατ
EB RR
Βψτεσ
2
69/84

Α − Ινστρυχτιον Σετ
ΡΕΤΣ
ΡΕΤΣ
Ρετυρν φροµ Ιντερ−Σεγµεντ Συβρουτινε
ΡΕΤΣ
OPERATION
(IP) ⇐ ((SP))
(SP) ⇐ (SP) + 2
(CSP) ⇐ ((SP))
(SP) ⇐ (SP) + 2
Returns from an inter-segment subroutine. The IP and CSP are popped from the system
stack. Execution resumes at the instruct
ion following the CA
LLS instruc
tion in the calling
routine.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
RETS
ΒΣΟ/Τασκινγ
Μνεµονιχ
RET
Οπερανδσ
Φορµατ
DB 00
70/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΡΟΛ
ΡΟΛ
Ροτατε Λεφτ
ΡΟΛ
οπ1, οπ2
OPERATION
(count)⇐ (op2)
(C) ⇐ 0
DO WHILE count≠ 0
(C) ⇐ (op115)
(op1n) ⇐ (op1n-1)n=1 to 15
(op10) ⇐ (C)
(count)⇐ (count) - 1
END WHILE
DATA TYPES WORD
Rotates the destination word operand op1 left by as many times as specified by the source
operand op2. Bit 15 is rotated into Bit 0 and into the Carry. Only shift values between 0 and
15 are allowed. When using a GPR as the count control, only the least significant 4 bits are
used.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
0
S
*
Always cleared.
Set if the result equals zero. Cleared otherwise.
Always cleared.
The Carry flag is set according to the last MSB shifted out of op1. Cleared for a rotate
count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ROL
ROL
ΒΣΟ/Τασκινγ
Μνεµονιχ
ROL
ROL
Οπερανδσ
Rwn,Rwm
Rwn,#data4
Φορµατ
0C nm
1C #n
Βψτεσ
2
2
71/84

Α − Ινστρυχτιον Σετ
ΡΟΡ
ΡΟΡ
Ροτατε Ριγητ
ΡΟΡ
οπ1, οπ2
OPERATION
(count)⇐ (op2)
(C) ⇐ 0
(V) ⇐ 0
DO WHILE count≠ 0
(V) ⇐ (V) v (C)
(C) ⇐ (op10)
(op1n) ⇐ (op1n+1)n=0 to 14
(op115) ⇐ (C)
(count)⇐ (count) - 1
END WHILE
DATA TYPES WORD
Rotates the destination word operand op1 right by as many times as specified by the
source operand op2. Bit 0 is rotated into Bit 15 and into the Carry. Only shift values between 0 and 15 are allowed. When using a GPR as the count control, only the least significant 4 bits are used.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
S
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if in any cycle of the shift operation, a 1 is shifted out of the Carry flag. Cleared for
a rotate count of zero.
The Carry flag is set according to the last LSB shifted out of op1. Cleared for a rotate
count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
ROR
ROR
ΒΣΟ/Τασκινγ
Μνεµονιχ
ROR
ROR
Οπερανδσ
Rwn,Rwm
Rwn,#data4
72/84

Φορµατ
2C nm
3C #n
Βψτεσ
2
2
Α − Ινστρυχτιον Σετ
ΣΧΞΤ
ΣΧΞΤ
Σωιτχη Χοντεξτ
ΣΧΞΤ
οπ1, οπ2
OPERATION
(tmp1)⇐ (op1)
(tmp2)⇐ (op2)
(SP) ⇐ (SP) - 2
((SP)) ⇐ (tmp1)
(op1)⇐ (tmp2)
Used to switch contexts for any register. Switching context is a push and load operation.
The contents of the register specified by the first operand, op1, are pushed onto the stack.
That register is then
loadedwith the value specified by the second operand, op2.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
SCXT
SCXT
ΒΣΟ/Τασκινγ
Μνεµονιχ
SCXT
SCXT
Οπερανδσ
reg,#data16
reg,mem
Φορµατ
C6 RR ## ##
D6 RR MM MM
Βψτεσ
4
4
73/84

Α − Ινστρυχτιον Σετ
ΣΗΛ
ΣΗΛ
Σηιφτ Λεφτ
ΣΗΛ
οπ1, οπ2
OPERATION
(count)⇐ (op2)
(C) ⇐ 0
DO WHILE count≠ 0
(C) ⇐ (op115)
(op1n) ⇐ (op1n-1)n=1 to 15
(op10) ⇐ 0
(count)⇐ (count) - 1
END WHILE
DATA TYPES WORD
Shifts the dest
ination wor
d operand op1 left by as many times as specified by the source
operand op2. The least significant bits of the result are filled with zeros accordingly. The
MSB is shifted into the Carry. Only shift values between 0 and 15 are allowed. When using
a GPR as the count control, only the least significant 4 bits are used.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
0
S
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Always cleared.
The Carry flag is set according to the last MSB shifted out of op1. Cleared for a shift
count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
SHL
SHL
ΒΣΟ/Τασκινγ
Μνεµονιχ
SHL
SHL
Οπερανδσ
Rwn,Rwm
Rwn,#data4
74/84

Φορµατ
4C nm
5C #n
Βψτεσ
2
2
Α − Ινστρυχτιον Σετ
ΣΗΡ
ΣΗΡ
Σηιφτ Ριγητ
ΣΗΡ
οπ1, οπ2
OPERATION
(count)⇐ (op2)
(C) ⇐ 0
(V) ⇐ 0
DO WHILE count≠ 0
(V) ⇐ (C) ∨ (V)
(C) ⇐ (op10)
(op1n) ⇐ (op1n+1)n= 0 to 14
(op115) ⇐ 0
(count)⇐ (count) - 1
END WHILE
DATA TYPES WORD
Shifts the destination word operand op1 right by as many times as specified by the source
operand op2. The most significant bits of the result are filled with zeros
cordingly
ac . Since
the bits shifted out effectively represent the ainder,
rem the Overflow flag is used instead as
a Roundingflag. This flag together with the Carry flag helps the user to determine whether
the remainder bits lost were greater than, less than or equal to one half an LSB. Only shift
values between 0 and 15 are allowed. When using a GPR as the count control, only the
least significant 4 bits are used.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
*
S
S
*
Always cleared.
Set if result equals zero. Cleared otherwise.
Set if in any cycle of the shift operation, a 1 is shifted out of the Carry flag. Cleared for
a shift count of zero.
The Carry flag is set according to the last LSB bit shifted out of op1. Cleared for a shift
count of zero.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
SHR
SHR
ΒΣΟ/Τασκινγ
Μνεµονιχ
SHR
SHR
Οπερανδσ
Rwn,Rwm
Rwn,#data4
Φορµατ
6C nm
7C #n
Βψτεσ
2
2
75/84

Α − Ινστρυχτιον Σετ
ΣΡΣΤ
ΣΡΣΤ
Σοφτωαρε Ρεσετ
ΣΡΣΤ
OPERATION
Software Reset
This instruction is used to perform a software reset. A software reset has the same effect
on the microcontroller as an externally applied hardware reset. To insure that this instruction is not accidentally executed, it is implemented as a protected instruction.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
0
0
0
0
0
Always cleared.
Always cleared.
Always cleared.
Always cleared.
Always cleared.
INSTRUCTION FORMAT
Μνεµονιχ
SRST
ΒΣΟ/Τασκινγ
Μνεµονιχ
SRST
Φορµατ
B7 48 B7 B7
76/84

Βψτεσ
4
Α − Ινστρυχτιον Σετ
ΣΡςΩ∆Τ
ΣΡςΩ∆Τ
Σερϖιχε Ωατχηδογ Τιµερ
ΣΡςΩ∆Τ
OPERATION
Service Watchdog Timer
This instruction services the Watchdog Timer. It reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence. Once this instruction has been executed, the watchdog timer cannot be disabled. To insure that this
instruction is not accidentally executed, it is implemented as a protected instruction.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
SRVWDT
ΒΣΟ/Τασκινγ
Μνεµονιχ
SRVWDT
Φορµατ
A7 58 A7 A7
Βψτεσ
4
77/84

Α − Ινστρυχτιον Σετ
ΣΥΒ
ΣΥΒ
Ιντεγερ Συβτραχτιον
ΣΥΒ
οπ1, οπ2
OPERATION
(op1)⇐ (op1) - (op2)
DATA TYPES WORD
Performs a 2’s complement binary subtraction of the source operand specified by op2 from
the destination operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
SUB
SUB
SUB
SUB
SUB
SUB
SUB
ΒΣΟ/Τασκινγ
Μνεµονιχ
SUB
SUB
SUB
SUB
SUB
SUB
SUB
Οπερανδσ
Rwn,Rwm
Rwn,#data3
reg,#data16
Rwn,[Rwi]
Rwn,[Rwi+]
reg,mem
mem,reg
78/84

Φορµατ
20 nm
28 n:0###
26 RR ## ##
28 n:10ii
28 n:11ii
22 RR MM MM
24 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
Α − Ινστρυχτιον Σετ
ΣΥΒΒ
ΣΥΒΒ
Ιντεγερ Συβτραχτιον
ΣΥΒΒ
οπ1, οπ2
OPERATION
(op1)⇐ (op1) - (op2)
DATA TYPES BYTE
Performs a 2’s complement binary subtraction of the source operand specified by op2 from
the destination operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ΒΣΟ/Τασκινγ
Μνεµονιχ
SUB
SUB
SUB
SUB
SUB
SUB
SUB
Οπερανδσ
Rbn,Rbm
Rbn,#data3
reg,#data16
Rbn,[Rwi]
Rbn,[Rwi+]
reg,mem
mem,reg
Φορµατ
21 nm
29 n:0###
27 RR ## ##
29 n:10ii
29 n:11ii
23 RR MM MM
25 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
79/84

Α − Ινστρυχτιον Σετ
ΣΥΒΧ
ΣΥΒΧ
Ιντεγερ Συβτραχτιον ωιτη Χαρρψ
ΣΥΒΧ
οπ1, οπ2
OPERATION
(op1)⇐ (op1) - (op2) - (C)
DATA TYPES WORD
Performs a 2’s complement binary subtraction of the source operand specified by op2 and
the previously generated carry bit from the destination operand specified by op1. The result is then stored in op1. This instruction can be used to perform multiple precision arithmetic.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
S
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and previous Z flag was set. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
ΒΣΟ/Τασκινγ
Μνεµονιχ
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
Οπερανδσ
Rwn,Rwm
Rwn,#data3
reg,#data16
Rwn,[Rwi]
Rwn,[Rwi+]
reg,mem
mem,reg
80/84

Φορµατ
30 nm
38 n:0###
36 RR ##
38 n:10ii
38 n:11ii
32 RR MM MM
34 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
Α − Ινστρυχτιον Σετ
ΣΥΒΧΒ
ΣΥΒΧΒ
Ιντεγερ Συβτραχτιον ωιτη Χαρρψ
ΣΥΒΧΒ οπ1, οπ2
OPERATION
(op1)⇐ (op1) - (op2) - (C)
DATA TYPES BYTE
Performs a 2’s complement binary subtraction of the source operand specified by op2 and
the previously generated carry bit from the destination operand specified by op1. The result is then stored in op1. This instruction can be used to perform multiple precision arithmetic.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
S
*
S
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero and previous Z flag was set. Cleared otherwise.
Set if an arithmetic underflow occurred, i.e. the result can not be represented in the
specified data type. Cleared otherwise.
Set if a borrow is generated. Cleared otherwise.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
SUBCB
SUBCB
SUBCB
SUBCB
SUBCB
SUBCB
SUBCB
ΒΣΟ/Τασκινγ
Μνεµονιχ
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
SUBC
Οπερανδσ
Rbn,Rbm
Rbn,#data3
reg,#data16
Rbn,[Rwi]
Rbn,[Rwi+]
reg,mem
mem,reg
Φορµατ
31 nm
39 n:0###
37 RR ## ##
39 n:10ii
39 n:11ii
33 RR MM MM
35 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
81/84

Α − Ινστρυχτιον Σετ
ΤΡΑΠ
ΤΡΑΠ
Σοφτωαρε Τραπ
ΤΡΑΠ
οπ1
OPERATION
(SP) ⇐ (SP) - 2
((SP)) ⇐ (PSW)
IF (SYSCON.SGTDIS = 0) THEN
(SP) ⇐ (SP) - 2
((SP)) ⇐ (CSP)
(CSP) ⇐ 0
END IF
(SP) ⇐ (SP) - 2
((SP)) ⇐ (IP)
(IP) ⇐ zero extend (op1× 4)
Invokes a trap or interrupt routine based on the specified operand, op1. The invoked routine is determined by branc
hing to the specified vector table entry point. This routine has
no indication of whether it was called by software or hardware. System state is preserved
identically to hardware interrupt entry except that the CPU priority level is not affected. The
RETI, return from interrupt, instruction is used to resume execution after the trap or interrupt routine has completed. The CSP is pushed if segmentation
enabled.This
is
is indicated by the SGTDIS bit in the SYSCON register.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
-
-
-
-
-
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
INSTRUCTION FORMAT
Μνεµονιχ
TRAP
ΒΣΟ/Τασκινγ
Μνεµονιχ
TRAP
Οπερανδσ
#trap7
Φορµατ
9B t:ttt0
82/84

Βψτεσ
2
Α − Ινστρυχτιον Σετ
ΞΟΡ
ΞΟΡ
Λογιχαλ Εξχλυσιϖε ΟΡ
ΞΟΡ
οπ1, οπ2
OPERATION
(op1)⇐ (op1)⊕ (op2)
DATA TYPES WORD
Performs a bitwise logical EXCLUSIVE OR on each bit of the source operand specified by
op2 and the destination operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
E
Z
V
C
N
*
*
0
0
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
INSTRUCTION FORMAT
Μνεµονιχ
XOR
XOR
XOR
XOR
XOR
XOR
XOR
ΒΣΟ/Τασκινγ
Μνεµονιχ
XOR
XOR
XOR
XOR
XOR
XOR
XOR
Οπερανδσ
Rwn,Rwm
Rwn,#data3
reg,#data16
Rwn,[Rwi]
Rwn,[Rwi+]
reg,mem
mem,reg
Φορµατ
50 nm
58 n:0###
56 RR ## ##
58 n:10ii
58 n:11ii
52 RR MM MM
54 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
83/84

Α − Ινστρυχτιον Σετ
ΞΟΡΒ
ΞΟΡΒ
Λογιχαλ Εξχλυσιϖε ΟΡ
ΞΟΡ
οπ1, οπ2
OPERATION
(op1)⇐ (op1)⊕ (op2)
DATA TYPES BYTE
Performs a bitwise logical EXCLUSIVE OR on each bit of the source operand specified by
op2 and the destination operand specified by op1. The result is then stored in op1.
FLAGS
E
Z
V
C
N
Μνεµονιχ
XORB
XORB
XORB
XORB
XORB
XORB
XORB
E
Z
V
C
N
*
*
0
0
*
Set if the value of op2 represents the lowest possible negative number. Cleared otherwise. Used to signal the end of a table.
Set if result equals zero. Cleared otherwise.
Always cleared.
Always cleared.
Set if the most significant bit of the result is set. Cleared otherwise.
ΒΣΟ/Τασκινγ
Μνεµονιχ
XOR
XOR
XOR
XOR
XOR
XOR
XOR
Οπερανδσ
Rbn,Rbm
Rbn,#data3
reg,#data16
Rbn,[Rwi]
Rbn,[Rwi+]
reg,mem
mem,reg
84/84

Φορµατ
51 nm
59 n:0###
57 RR ## ##
59 n:10ii
59 n:11ii
53 RR MM MM
55 RR MM MM
Βψτεσ
2
2
4
2
2
4
4
APPENDIX B

ST10x166 REGISTERS
B. ST10x166 REGISTERS
This part of the A
appendix contains a summary of tion Registers are summarized and ordered by adall registers incorpored in the ST10x166. Section dress, while Section B.3 lists all Special Function
B.1 lists all CPU General Purpose Registers. In Registers inalphabetic
al order.
Section B.2, all ST10x166 Specific Special FuncB.1 CPU GENERAL PURPOSE REGISTERS
(GPRs)
must be programmed such that the accessed
GPRs are always located in the internal RAM
space. All GPRs are always located in the internal
CPU General Purpose Registers are accessed via RAM space. All GPRs are bit addressable.
the Context Pointer (CP). The Context Pointer
Word Registers
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
R0
(CP) + 0
F0h
CPU General Purpose Register
R0
XXXXh
R1
(CP) + 2
F1h
CPU General Purpose Register
R1
XXXXh
R2
(CP) + 4
F2h
CPU General Purpose Register
R2
XXXXh
R3
(CP) + 6
F3h
CPU General Purpose Register
R3
XXXXh
R4
(CP) + 8
F4h
CPU General Purpose Register
R4
XXXXh
R5
(CP) + 10
F5h
CPU General Purpose Register
R5
XXXXh
R6
(CP) + 12
F6h
CPU General Purpose Register
R6
XXXXh
R7
(CP) + 14
F7h
CPU General Purpose Register
R7
XXXXh
R8
(CP) + 16
F8h
CPU General Purpose Register
R8
XXXXh
R9
(CP) + 18
F9h
CPU General Purpose Register
R9
XXXXh
R10
(CP) + 20
FAh
CPU General Purpose Register
R10
XXXXh
R11
(CP) + 22
FBh
CPU General Purpose Register
R11
XXXXh
R12
(CP) + 24
FCh
CPU General Purpose Register
R12
XXXXh
R13
(CP) + 26
FDh
CPU General Purpose Register
R13
XXXXh
R14
(CP) + 28
FEh
CPU General Purpose Register
R14
XXXXh
R15
(CP) + 30
FFh
CPU General Purpose Register
R15
XXXXh
1/16
B. ST10x166 Registers
Byte Registers
Name
Physical
Address
8-Bit
Address
Description
RL0
(CP) + 0
F0h
CPU General Purpose Register
RL0
XXh
RH0
(CP) + 1
F1h
CPU General Purpose Register
RH0
XXh
RL1
(CP) + 2
F2h
CPU General Purpose Register
RL1
XXh
RH1
(CP) + 3
F3h
CPU General Purpose Register
RH1
XXh
RL2
(CP) + 4
F4h
CPU General Purpose Register
RL2
XXh
RH2
(CP) + 5
F5h
CPU General Purpose Register
RH2
XXh
RL3
(CP) + 6
F6h
CPU General Purpose Register
RL3
XXh
RH3
(CP) + 7
F7h
CPU General Purpose Register
RH3
XXh
RL4
(CP) + 8
F8h
CPU General Purpose Register
RL4
XXh
RH4
(CP) + 9
F9h
CPU General Purpose Register
RH4
XXh
RL5
(CP) + 10
FAh
CPU General Purpose Register
RL5
XXh
RH5
(CP) + 11
FBh
CPU General Purpose Register
RH5
XXh
RL6
(CP) + 12
FCh
CPU General Purpose Register
RL6
XXh
RH6
(CP) + 13
FDh
CPU General Purpose Register
RH6
XXh
RL7
(CP) + 14
FEh
CPU General Purpose Register
RL7
XXh
RH7
(CP) + 15
FFh
CPU General Purpose Register
RH7
XXh
2/16

Reset
Value
B. ST10x166 Registers
SPECIAL FUNCTION REGISTERS Ordered by Address
Non-Bit Addressable Special Function Registers
Name
Physcial
Address
8-Bit
Address
Description
Reset
Value
DPP0
FE00h
00h
CPU Data Page Pointer 0 Register (4 bits)
0000h
DPP1
FE02h
01h
CPU Data Page Pointer 1 Register (4 bits)
0001h
DPP2
FE04h
02h
CPU Data Page Pointer 2 Register (4 bits)
0002h
DPP3
FE06h
03h
CPU Data Page Pointer 3 Register (4 bits)
0003h
CSP
FE08h
04h
CPU Code Segment Pointer Register (2 bits, read only)
FE0Ah
05h
(reserved)
MDH
FE0Ch
06h
CPU Multiply/Divide Register - High Word
0000h
MDL
FE0Eh
07h
CPU Multiply/Divide Register - Low Word
0000h
CP
FE10h
08h
CPU Context Pointer Register
FC00h
SP
FE12h
09h
CPU System Stack Pointer Register
FC00h
STKOV
FE14h
0Ah
CPU Stack Overflow Pointer Register
FA00h
STKUN
FE16h
0Bh
CPU Stack Underflow Pointer Register
FC00h
ADDRSEL1
FE18h
0Ch
Address Select Register
0000h
•
•
•
•
•
•
FE3Eh
1Fh
(reserved)
T2
FE40h
20h
GPT1 Timer 2 Register
0000h
T3
FE42h
21h
GPT1 Timer 3 Register
0000h
T4
FE44h
22h
GPT1 Timer 4 Register
0000h
T5
FE46h
23h
GPT2 Timer 5 Register
0000h
T6
FE48h
24h
GPT2 Timer 6 Register
0000h
CAPREL
FE4Ah
25h
GPT2 Capture/Reload Register
FE4Ch
26h
(reserved)
FE4Eh
27h
(reserved)
0000h
0000h
3/16

B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
T0
FE50h
28h
CAPCOM Timer 0 Register
0000h
T1
FE52h
29h
CAPCOM Timer 1 Register
0000h
T0REL
FE54h
2Ah
CAPCOM Timer 0 Reload Register
0000h
T1REL
FE56h
2Bh
CAPCOM Timer 1 Reload Register
0000h
FE58h
2Ch
(reserved)
•
•
•
•
•
•
FE7Eh
3Fh
(reserved)
CC0
FE80h
40h
CAPCOM Register 0
0000h
CC1
FE82h
41h
CAPCOM Register 1
0000h
CC2
FE84h
42h
CAPCOM Register 2
0000h
CC3
FE86h
43h
CAPCOM Register 3
0000h
CC4
FE88h
44h
CAPCOM Register 4
0000h
CC5
FE8Ah
45h
CAPCOM Register 5
0000h
CC6
FE8Ch
46h
CAPCOM Register 6
0000h
CC7
FE8Eh
47h
CAPCOM Register 7
0000h
CC8
FE90h
48h
CAPCOM Register 8
0000h
CC9
FE92h
49h
CAPCOM Register 9
0000h
CC10
FE94h
4Ah
CAPCOM Register 10
0000h
CC11
FE96h
4Bh
CAPCOM Register 11
0000h
CC12
FE98h
4Ch
CAPCOM Register 12
0000h
CC13
FE9Ah
4Dh
CAPCOM Register 13
0000h
CC14
FE9Ch
4Eh
CAPCOM Register 14
0000h
CC15
FE9Eh
4Fh
CAPCOM Register 15
4/16

Reset
Value
B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
ADDAT
FEA0h
50h
A/D Converter Result Register
FEA2h
51h
(reserved)
•
ù
•
•
ù
•
FEACh
56h
(reserved)
WDT
FEAEh
57h
Watchdog Timer Register (read only)
S0TBUF
FEB0h
58h
Serial Channel 0 Transmit Buffer Register
(write only)
0000h
S0RBUF
FEB2h
59h
Serial Channel 0 Receive Buffer Register
(read only)
XXXXh
S0BG
FEB4h
5Ah
Serial Channel 0 Baud Rate Generator/
Reload Register
0000h
FEB6h
5Bh
(reserved)
S1TBUF
FEB8h
5Ch
Serial Channel 1 Transmit Buffer Register
(write only)
0000h
S1RBUF
FEBAh
5Dh
Serial Channel 1 Receive Buffer Register
(read only)
XXXXh
S1BG
FEBCh
5Eh
Serial Channel 1 Baud Rate (Generator/
Reload Register
0000h
FEBEh
5Fh
(reserved)
PECC0
FEC0h
60h
PEC Channel 0 Control Register
0000h
PECC1
FEC2h
61h
PEC Channel 1 Control Register
0000h
PECC2
FEC4h
62h
PEC Channel 2 Control Register
0000h
PECC3
FEC6h
63h
PEC Channel 3 Control Register
0000h
PECC4
FEC8h
64h
PEC Channel 4 Control Register
0000h
PECC5
FECAh
65h
PEC Channel 5 Control Register
0000h
PECC6
FECCh
66h
PEC Channel 6 Control Register
0000h
PECC7
FECEh
67h
PEC Channel 7 Control Register
0000h
FED0h
68h
(reserved)
•
ù
•
•
ù
•
FEFEh
7Fh
(reserved)
0000h
0000h
5/16

B. ST10x166 Registers
Bit Addressable Special Function Registers
Name
Physical
Address
8-Bit
Address
Description
P0
FF00h
80h
Port 0 Register
DP0
FF02h
81h
Port 0 Direction Control Register
P1
FF04h
82h
Port 1 Register
DP1
FF06h
83h
Port 1 Direction Control Register
P4
FF08h
84h
Port 4 Register (2 Bits)
DP4
FF0Ah
85h
Port 4 Direction Control Register (2 Bits)
SYSCON
FF0Ch
86h
CPU System Configuration Register
* system configuration selected during reset
MDC
FF0Eh
87h
CPU Multiply/Divide Control Register
PSW
FF10h
88h
CPU Program Status Word
FF12h
89h
(reserved)
FF14h
8Ah
Bus Configuration Register
•
•
•
•
•
•
FF1Ah
8Dh
(reserved)
ZEROS
FF1Ch
8Eh
Constant Value 0’s Register (read only)
0000h
ONES
FF1Eh
8Fh
Constant Value 1’s Register (read only)
FFFFh
FF20h
90h
(reserved)
•
•
•
•
•
•
FF3Eh
9Fh
(reserved)
BUSCON1
6/16

Reset
Value
0000h
0000h
0000h
0000h
0000h
0000h
0XX0h*
0000h
0000h
0000h
B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
T2CON
FF40h
A0h
GPT1 Timer 2 Control Register
0000h
T3CON
FF42h
A1h
GPT1 Timer 3 Control Register
0000h
T4CON
FF44h
A2h
GPT1 Timer 4 Control Register
0000h
T5CON
FF46h
A3h
GPT1 Timer 5 Control Register
0000h
T6CON
FF48h
A4h
GPT1 Timer 6 Control Register
0000h
FF4Ah
A5h
(reserved)
FF4Ch
A6h
(reserved)
FF4Eh
A7h
(reserved)
T01CON
FF50h
A8h
CAPCOM Timer 0 and Timer 1 Control Register
CCM0
FF52h
A9h
CAPCOM Mode Control Register 0
0000h
CCM1
FF54h
AAH
CAPCOM Mode Control Register 1
0000h
CCM2
FF56h
ABh
CAPCOM Mode Control Register 2
0000h
CCM3
FF58h
ACh
CAPCOM Mode Control Register 3
0000h
FF5Ah
ADh
(reserved)
FF5Ch
AEh
(reserved)
FF5Eh
AFh
(reserved)
T2IC
FF60h
B0h
GPT1 Timer 2 Interrupt Control Register
0000h
T3IC
FF62h
B1h
GPT1 Timer 3 Interrupt Control Register
0000h
T4IC
FF64h
B2h
GPT1 Timer 4 Interrupt Control Register
0000h
T5IC
FF66h
B3h
GPT2 Timer 5 Interrupt Control Register
0000h
T6IC
FF68h
B4h
GPT2 Timer 6 Interrupt Control Register
0000h
CRIC
FF6Ah
B5h
GPT2 CAPREL Interrupt Control Register
0000h
0000h
7/16

B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
S0TIC
FF6Ch
B6h
Serial Channel 0 Transmit Interrupt Control
Register
0000h
S0RIC
FF6Eh
B7h
Serial Channel 0 Receive Interrupt Control
Register
0000h
S0EIC
FF70h
B8h
Serial Channel 0 Error Interrupt Control
Register
0000h
S1TIC
FF72h
B9h
Serial Channel 1 Transmit Interrupt Control
Register
0000h
S1RIC
FF74h
BAh
Serial Channel 1 Receive Interrupt Control
Register
0000h
S1EIC
FF76h
BBh
Serial Channel 1 Error Interrupt Control Register
0000h
CC0IC
FF78h
BCh
CAPCOM Register 0 Interrupt Control Register
0000h
CC1IC
FF7Ah
BDh
CAPCOM Register 1 Interrupt Control Register
0000h
CC2IC
FF7Ch
BEh
CAPCOM Register 2 Interrupt Control Register
0000h
CC3IC
FF7Eh
BFh
CAPCOM Register 3 Interrupt Control Register
0000h
CC4IC
FF80h
C0h
CAPCOM Register 4 Interrupt Control Register
0000h
CC5IC
FF82h
C1h
CAPCOM Register 5 Interrupt Control Register
0000h
CC6IC
FF84h
C2h
CAPCOM Register 6 Interrupt Control Register
0000h
CC7IC
FF86h
C3h
CAPCOM Register 7 Interrupt Control Register
0000h
CC8IC
FF88h
C4h
CAPCOM Register 8 Interrupt Control Register
0000h
CC9IC
FF8Ah
C5h
CAPCOM Register 9 Interrupt Control Register
0000h
CC10IC
FF8Ch
C6h
CAPCOM Register 10 Interrupt Control Register
0000h
CC11IC
FF8Eh
C7h
CAPCOM Register 11 Interrupt Control Register
0000h
CC12IC
FF90h
C8h
CAPCOM Register 12 Interrupt Control Register
0000h
CC13IC
FF92h
C9h
CAPCOM Register 13 Interrupt Control Register
0000h
CC14IC
FF94h
CAh
CAPCOM Register 14 Interrupt Control Register
0000h
CC15IC
FF96h
CBh
CAPCOM Register 15 Interrupt Control Register
0000h
8/16

Reset
Value
B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
ADCIC
FF98h
CCh
A/D Converter End of Conversion Interrupt
Control Register
ADEIC
FF9Ah
CDh
A/D Converter Overrun Error Interrupt Control
0000h
Register
T0IC
FF9Ch
CEh
CAPCOM TImer 0 Interrupt Control Register
0000h
T1IC
FF9Eh
CFh
CAPCOM Timer 1 Interrupt Control Register
0000h
ADCON
FFA0h
D0h
A/D Converter Control Register
0000h
P5
FFA2h
D1h
Port 5 Register (10 Bits, read only)
XXXXh
FFA4h
D2h
(reserved)
•
•
•
•
•
•
FFAAh
D5h
(reserved)
TFR
FFACh
D6h
Trap Flag Register
WDTCON
FFAEh
D7h
Watchdog Timer Control Register
for Watchdog Timer overflow
0000h
0000h
0000h
0002h
9/16

B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
S0CON
FFB0h
D8h
Serial Channel 0 Control Register
FFB2h
D9h
(reserved)
FFB4h
DAh
(reserved)
FFB6h
DBh
(reserved)
FFB8h
DCh
Serial Channel 1 Control Register
FFBAh
DDh
(reserved)
FFBCh
DEh
(reserved)
FFBEh
DFh
(reserved)
P2
FFC0h
E0h
Port 2 Register
DP2
FFC2h
E1h
Port 2 Direction Control Register
P3
FFC4h
E2h
Port 3 Register
DP3
FFC6h
E3h
Port 3 Direction Control Register
FFC8h
E4h
(reserved)
•
•
ù
•
ù
•
FFDEh
EFh
(reserved)
S1CON
10/16

Reset
Value
0000h
0000h
0000h
0000h
0000h
0000h
B. ST10x166 Registers
SPECIAL FUNCTION REGISTERS ALPHABETICAL ORDER
The following table lists all SFRs which are imple- Bit addressable SFRs are marked with the letter
mented in the ST10x166 inalphabetical order.
“b” in column “Name”.
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
ADCIC
b
FF98h
CCh
A/D Converter End of Conversion
Interrupt Control Register
0000h
ADCON
b
FFA0h
D0h
A/D Converter Control Register
0000h
ADDAT
FEA0h
50h
A/D Converter Result Register
0000h
ADDRSEL1
FE18h
0Ch
Address Select Register
0000h
ADEIC
b
FF9Ah
CDh
A/D Converter Overrun Error Interrupt Control
0000h
Register
BUSCON1
b
FF14h
8Ah
Bus Configuration Register
0000h
CAPREL
FE4Ah
25h
GPT2 Capture/Reload Register
0000h
CC0
FE80h
40h
CAPCOM Register 0
FF78h
BCh
CAPCOM Register 0 Interrupt Control
Register
FE82h
41h
CAPCOM Register 1
FF7Ah
BDh
CAPCOM Register 1 Interrupt Control
Register
FE84h
42h
CAPCOM Register 2
FF7Ch
BEh
CAPCOM Register 2 Interrupt Control
Register
FE86h
43h
CAPCOM Register 3
FF7Eh
BFh
CAPCOM Register 3 Interrupt Control
Register
FE88h
44h
CAPCOM Register 4
FF80h
C0h
CAPCOM Register 4 Interrupt Control
Register
CC0IC
b
CC1
CC1IC
b
CC2
CC2IC
b
CC3
CC3IC
b
CC4
CC4IC
b
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
11/16

B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
CC5
FE8Ah
45h
CAPCOM Register 5
FF82h
C1h
CAPCOM Register 5 Interrupt Control
Register
FE8Ch
46h
CAPCOM Register 6
FF84h
C2h
CAPCOM Register 6 Interrupt Control
Register
FE8Eh
47h
CAPCOM Register 7
FF86h
C3h
CAPCOM Register 7 Interrupt Control
Register
FE90h
48h
CAPCOM Register 8
FF88h
C4h
CAPCOM Register 8 Interrupt Control
Register
FE92h
49h
CAPCOM Register 9
FF8Ah
C5h
CAPCOM Register 9 Interrupt Control
Register
FE94h
4Ah
CAPCOM Register 10
FF8Ch
C6h
CAPCOM Register 10 Interrupt Control
Register
FE96h
4Bh
CAPCOM Register 11
FF8Eh
C7h
CAPCOM Register 11 Interrupt Control
Register
FE98h
4Ch
CAPCOM Register 12
FF90h
C8h
CAPCOM Register 12 Interrupt Control
Register
FE9Ah
4Dh
CAPCOM Register 13
FF92h
C9h
CAPCOM Register 13 Interrupt Control
Register
CC5IC
b
CC6
CC6IC
b
CC7
CC7IC
b
CC8
CC8IC
b
CC9
CC9IC
b
CC10
CC10IC
b
CC11
CC11IC
b
CC12
CC12IC
b
CC13
CC13IC
b
12/16

Reset
Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
CC14
FE9Ch
4Eh
CAPCOM Register 14
FF94h
CAh
CAPCOM Register 14 Interrupt Control
Register
FE9Eh
4Fh
CAPCOM Register 15
CC14IC
b
CC15
Reset
Value
0000h
0000h
0000h
CC15IC
b
FF96h
CBh
CAPCOM Register 15 Interrupt Control
Register
CCM0
b
FF52h
A9h
CAPCOM Mode Control Register 0
0000h
CCM1
b
FF54h
AAh
CAPCOM Mode Control Register 1
0000h
CCM2
b
FF56h
ABh
CAPCOM Mode Control Register 2
0000h
CCM3
b
FF58h
ACh
CAPCOM Mode Control Register 3
0000h
FE10h
08h
CPU Context Pointer Register
FC00h
FF6Ah
B5h
GPT2 CAPREL Interrupt Control Register
FE08h
04h
CPU Code Segment Pointer Register
(2 Bits, read only)
CP
CRIC
b
CSP
0000h
0000h
0000h
DP0
b
FF02h
81h
Port 0 Direction Control Register
0000h
DP1
b
FF06h
83h
Port 1 Direction Control Register
0000h
DP2
b
FFC2h
E1h
Port 2 Direction Control Register
0000h
DP3
b
FFC6h
E3h
Port 3 Direction Control Register
0000h
DP4
b
FF0Ah
85h
Port 4 Direction Control Register (2 Bits)
0000h
DPP0
FE00h
00h
CPU Data Page Pointer 0 Register (4 Bits)
0000h
DPP1
FE02h
01h
CPU Data Page Pointer 1 Register (4 Bits)
0001h
DPP2
FE04h
02h
CPU Data Page Pointer 2 Register (4 Bits)
0002h
DPP3
FE06h
03h
CPU Data Page Pointer 3 Register (4 Bits)
0003h
FF0Eh
87h
CPU Multiply/Divide Control Register
0000h
MDH
FE0Ch
06h
CPU Multiply/Divide Register - High Word
0000h
MDL
FE0Eh
07h
CPU Multiply/Divide Register - Low Word
0000h
FF1Eh
8Fh
Constant Value 1’s Register (read only)
FFFFh
MDC
ONES
b
b
13/16

B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
P0
b
FF00h
80h
Port 0 Register
0000h
P1
b
FF04h
82h
Port 1 Register
0000h
P2
b
FFC0h
E0h
Port 2 Register
0000h
P3
b
FFC4h
E2h
Port 3 Register
0000h
P4
b
FF08h
84h
Port 4 Register (2 Bits)
0000h
P5
b
FFA2h
D1h
Port 5 Register (10 Bits, read only)
XXXXh
PECC0
FEC0h
60h
PEC Channel 0 Control Register
0000h
PECC1
FEC2h
61h
PEC Channel 1 Control Register
0000h
PECC2
FEC4h
62h
PEC Channel 2 Control Register
0000h
PECC3
FEC6h
63h
PEC Channel 3 Control Register
0000h
PECC4
FEC8h
64h
PEC Channel 4 Control Register
0000h
PECC5
FECAh
65h
PEC Channel 5 Control Register
0000h
PECC6
FECCh
66h
PEC Channel 6 Control Register
0000h
PECC7
FECEh
67h
PEC Channel 7 Control Register
0000h
FF10h
88h
CPU Program Status Word
0000h
FEB4h
5Ah
Serial Channel 0 Baud Rate Generator/
Reload Register
PSW
b
S0BG
S0CON
b
FFB0h
D8h
Serial Channel 0 Control Register
S0EIC
b
FF70h
B8h
Serial Channel 0 Error Interrupt Control
Register
FEB2h
59
FF6Eh
S0RBUF
S0RIC
b
S0TBUF
S0TIC
b
0000h
0000h
0000h
Serial Channel 0 Receive Buffer Register
(read only)
XXXXh
B7h
Serial Channel 0 Receive Interrupt Control
Register
0000h
FEB0h
58h
Serial Channel 0 Transmit Buffer Register
(write only)
0000h
FF6Ch
B6h
Serial Channel 0 Transmit Interrupt Control 0000h
Register
14/16

B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
S1BG
FEBCh
5Eh
Serial Channel 1 Baud Rate Generator/
Reload Register
Reset
Value
0000h
S1CON
b
FFB8h
DCh
Serial Channel 1 Control Register
S1EIC
b
FF76h
BBh
Serial Channel 1 Error Interrupt Control
Register
0000h
FEBAh
5Dh
Serial Channel 1 Receive Buffer Register
(read only)
XXXXh
FF74h
BAh
Serial Channel 1 Receive Interrupt Control 0000h
Register
FEB8h
5Ch
Serial Channel 1 Transmit Buffer Register
(write only)
FF72h
B9h
Serial Channel 1 Transmit Interrupt Control 0000h
Register
SP
FE12h
09h
CPU System Stack Pointer Register
FC00h
STKOV
FE14h
0Ah
CPU Stack Overflow Pointer Register
FA00h
STKUN
FE16h
0Bh
CPU Stack Underflow Pointer Register
FC00h
FF0Ch
86h
CPU System Configuration Register
0XX0h*
* system configuration selected during reset
FE50h
28h
CAPCOM Timer 0 Register
S1RBUF
S1RIC
b
S1TBUF
S1TIC
SYSCON
b
b
T0
0000h
0000h
0000h
T01CON
b
FF50h
A8h
CAPCOM Timer 0 and Timer 1 Control
Register
T0IC
b
FF9Ch
CEh
CAPCOM Timer 0 Interrupt Control Register
T0REL
FE54h
2Ah
CAPCOM Timer 0 Reload Register
0000h
T1
FE52h
29h
CAPCOM Timer 1 Register
0000h
FF9Eh
CFh
CAPCOM Timer 1 Interrupt Control Register
FE56h
2Bh
CAPCOM Timer 1 Reload Register
T1IC
T1REL
b
0000h
0000h
0000h
0000h
15/16

B. ST10x166 Registers
Name
Physical
Address
8-Bit
Address
Description
T2
FE40h
20h
GPT1 Timer 2 Register
T2CON
b
FF40h
A0h
GPT1 Timer 2 Control Register
T2IC
b
FF60h
B0h
GPT1 Timer 2 Interrupt Control Register
FE42h
21h
GPT1 Timer 3 Register
T3
T3CON
b
FF42h
A1h
GPT1 Timer 3 Control Register
T3IC
b
FF62h
B1h
GPT1 Timer 3 Interrupt Control Register
FE44h
22h
GPT1 Timer 4 Register
T4
T4CON
b
FF44h
A2h
GPT1 Timer 4 Control Register
T4IC
b
FF64h
B2h
GPT1 Timer 4 Interrupt Control Register
FE46h
23h
GPT1 Timer 5 Register
T5
T5CON
b
FF46h
A3h
GPT1 Timer 5 Control Register
T5IC
b
FF66h
B3h
GPT1 Timer 5 Interrupt Control Register
FE48h
24h
GPT2 Timer 6 Register
T6
T6CON
b
FF48h
A4h
GPT2 Timer 6 Control Register
T6IC
b
FF68h
B4h
GPT2 Timer 6 Interrupt Control Register
TFR
b
FFACh
D6h
Trap Flag Register
FEAEh
57h
Watchdog Timer Register (read only)
WDT
WDTCON
b
FFAEh
D7h
Watchdog Timer Control Register
for Watchdog Timer overflow
ZEROS
b
FF1Ch
8Eh
Constant Value 0’s Register (read only)
16/16

Reset
Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h

APPENDIX C
APPLICATION EXAMPLE
C. APPLICATION EXAMPLE
This portion of theppendixis
a
subdividedinto two
3)
sections. Section C.1 shows examples for the use
of different types of memories connected to the
ST10x166 in different external bus conf
igurations
.
Section C.2 contains formulas, tables and examples for programming the ST10x166 wait states
described in detail in section 9.7.
C.1 EXTERNAL BUS AND MEMORY
CONFIGURATIONS
16-bit Addresses, 16-bit Data, Multiplexed
Bus
(External RAM/ROM: Both Word- and ByteOrganized Memories)
This configuration is shown in figure C.3. The
external memory is implemented by one
32Kx16 EPROM and by two 8Kx8 RAMs. The
connected external bus is used for both 16-bit
addresses and 16-bit data. Because of timemultiplexing, two external address latches are
A description of the possible ST10x166 external
required. The EPROM can only be accessed
bus configuration modes which are determined by
wordwise, while the RAMs can also be acthe state of the EBC1, EBC0 andBUSACT input
cessed bytewise, provided that the function of
pins during reset can be found in chapter 9. Note
theBHE output pin is not disabled. In this case,
that the o
f llowingexamples refer to the non-segthe address signal A0 selects the lower byte
mented memory model which supports only
memory and the active low
BHE signal selects
64Kbytes of memory space. Thus, port pins P4.1
the upper byte memory.
and P4.0 are not required as outputs
of additional
4) 16-bit Addresses, 16-bit Data, Non-Multisegment address bits (A17 and A16).
plexed Buses
1) 16-bit Addresses, 8-bit Data, Multiplexed
(External RAM/ROM: Both Word- and ByteBus
Organized Memories)
(External RAM/ROM: Byte-Organized Memories)
This configuration shown in figure C.4 is the
This configuration is shown in figure C.1. An
fastest external memory access mode. The
external memory is implemented by a 32Kx8
external memory is implemented by one
EPROM and an 8Kx8 RAM. The connected
32Kx16 EPROM and by two 8Kx8 RAMs. Beexternal bus is used for both 16-bit addresses
cause two separate 16-bit data and 16-bit adand 8-bit data. Because of time-multiplexing,
dress buses are used, no external address
an external address latch is required for the
latch is required. The EPROM can only be aclower byte of the address.
cessed wordwise, while the RAMs can also be
accessed bytewise, provided that the function
2) 16-bit Addresses, 8-bit Data, Non-Multiof the BHE output pin is not
disabled.In this
plexed Buses
case,
the
address
signal
A0
selects the lower
(External RAM/ROM: Byte-Organized Memories)
byte memory and the active low
BHE signal
This configuration is shown in figure C.2. The
selects the upper byte memory.
external memory is implemented by a 32Kx8
EPROM and an 8Kx8 RAM. Because two
separate 8-bit Data and 16-bit Address buses
are used, no external address latch is required.
1/10
C - Application Examples
Figure C-1. 16-Bit Addresses, 8-Bit Data, Multiplexed Bus Configuration
VC C
EBC0
VS S
EBC1
P0.8 -15
A8-A15
P0.0 -7
AD0-AD7
74HC573
Address
Latc h
A0-A7
LE
ALE
A15
OE
ST10x166
AD0-AD7
32K x 8
EPROM
M27C256B
RD
OE
P3.13/WR
WE
AD0-AD7
BUSACT
VS S
CE
A8-A14
A0-A7
A15
CS2
CS1
8K x 8
RAM
A8-A12
Example with Byte-Organized Memory Devices (Data Multip lexed)
2/10

A0-A7
VR00 1646
C - Application Example
Figure C-2. 16-Bit Addresses, 8-Bit Data, Non-Multiplexed Bus Configuration
VS S
EBC0
VS S
EBC1
P1.0 -15
P0.0 -7
A0-A15
D0-D7
OE
ST10x166
D0-D7
32K x 8
EPROM
M27C256B
RD
OE
P3.13/WR
WE
D0-D 7
BUSACT
VS S
CE
CS2
CS1
8K x 8
RAM
A15
A0-A14
A15
A0-A12
Example with Byte-Organized Memory Devices (Data Non-Multiplexed) VR0A164 6
3/10

C - Application Examples
Figure C-3. 16-Bit Addresses, 16-Bit Data, Multiplexed Bus Configuration
VS S
VCC
AD8-AD15
EBC1
P0.0-15
AD0-AD7
74H C573
Address
Latch
LE
LE
ALE
OE
D0-D15
ST10x166
RD
CE
32K x 16
EPROM
M27C516
C S2
C S1
OE
WE
P3.13/WR
D0-D7
BUSACT
74HC573
Ad dress
Latch
A0-A7
8K x 8
RAM
VS S
A8-A15
EBC0
A15
A15
A8-A14
A1-A7
A15
OE
A0
WE
A8-A13
A8-A13
A1-A7
A1-A7
CS 2
C S1
8K x 8
RAM
BHE
P3.12/BHE
D8-D 15
Example with Byte and Word-Organized Memory Devices (Data Multiplexed)
4/10

VR0 B1646
C - Application Example
Figure C-4. 16-Bit Addresses, 16-Bit Data, Non-Multiplexed Bus Configuration
VC C
EBC0
V CC
EBC1
P1.0 -15
A0-A15
BHE
P3.12/BHE
P0.0-15
D0-D15
D8-D15
CS1
CS2
8K x 8
RAM
OE
A15
A1-A13
WE
OE
ST10x166
D0-D15
32K x 16
EPROM
M27C516
RD
OE
P3.13 /WR
WE
D0-D 7
BUSACT
VS S
CE
CS2
CS1
8K x 8
RAM
A15
A1-A14
A15
A0
A1-A13
Example with Byte and Word-Organized Memory Devices (Data Non-Multiplexed)
VR0C1646
5/10

C - Application Examples
C.2 CALCULATION OF THE USER
SELECTABLE BUS TIMING PARAMETERS
n2:
Number of wait states required to match
‘RD to Valid Data In Time’
0 ≤ n2 ≤ 15; n2 integer
This section provides tables which ease the calcu- n3:
Number of wait states required to match
lation of the number of the ST10x166’s wait states
‘Data Float AfterRD Time’
which must be programmed into the MCTC bit field
0 ≤ n3 ≤ 1; n3 integer
and/or MTTC bit of the SYSCON register to match
n:
Total
number of resulting wait states
the external memory timing specifications.
n = max{n1, n2}+n3
The followingparticular memory accesses are
For memory write accesses:
considered in this section:
n1:
Number of wait states required to match
1) Memory Read via a Multiplexed Bus with
‘Write Pulse Low Time’
Read/Write Delay
0 ≤ n1 ≤ 15; n1 integer
2) Memory Write via a Multiplexed Bus with
n2:
Number of wait states required to match
Read/Write Delay
‘Data Valid toWR Time’
3) Memory Read via a Non-Multiplexed Bus
0 ≤ n2 ≤ 15; n2 integer
with Read/Write Delay
n:
Total number of resulting wait states
4) Memory Write via a Non-Multiplexed Bus
required
with Read/Write Delay
n = max{n1, n2}
Two types of tables exist for each of these memory Note: The ST10x166’s wait states can be proaccesses. The tables signified by an extension ‘.a’ grammed in increments of one. To get the number
contain formulas for the determination of both theof required wait states to be programmed, any
maximum values of particular timing parameters at value (n1, n2, n3) calculated by means of the forgiven numbers of wait states and of the numbers of mulas in tables ‘.a’ must be rounded up to the next
required wait states at given timing parameter val- integer value (e.g. 1.2→2). If a calculation already
ues. These tables consist of columns, as follows: suppliesan integer result (e.g. 1.0), one has to perSpecifies commonly used symbols of form a worst case evaluation of the selected
appli- Symbol:
the particular timing parameters.
cation (signal delays, etc.) to decide whether an
c
not. If
Provides a short explanation of the additionalwait state must be onsideredor
- Meaning:
wait state calculations supply different values for
symbolic timing parameters.
the same programmable parameter, the worst
- 40MHz Clock: Specifies formulas to be used case (maximum) value must always be considat a fixed oscillator frequency of 40MHz.
ered. Then the SYSCON register has to be programmed, as follows:
Variable
Timing:
Specifies
formulas
to
be
- used at a variable oscillator frequency.
MTTC: 1 - n3
MCTC: 15 - max{n1,n2}
Other so called ‘Quick Tables’, signified by an extension ‘.b’, contain results calc
ulated by inser
ting
Note: For some memories, the Chip Select Time
typical values into the formulas represented in the (tcs) may be as long as the Address to Valid Data In
correspondingtable ‘.a’.
Time (tacc). Formulas within this document do not
The required number
s of wait states are specified consider any signal delay caused by the chip sein all subsequent tables by symbols, as follows: lecting logic.
All times are specified in nanoseconds [ns], unless
For memory read accesses:
noted otherwise.
n1:
Number of wait states required to match
‘Address to Valid Data In Time’
0 ≤ n1 ≤ 15; n1 integer
6/10

C - Application Example
Table C-1. Multiplexed Memory Read With Read/Write Delay
Symbol
tacc
toe
tdf
t
Meaning
40MHz Clock
Variable Timing
Address to Valid Data In
t ≤ = t17 + n1 x 50
acc
n1 ≥ = tacc /50 - 1.5
tacc ≤ = 4TCL - 25 + n1 x 2TCL
n1 ≥ = (tacc + 25) /2TCL - 2
RD to Valid Data In
t
oe
n2
≤ = t14 + n2 x 50
≥ = toe /50 - 0.7
toe
n2
≤ = 2TCL - 15 + n2 x 2TCL
≥ = (toe + 15) /2TCL - 1
Data Float AfterRD
tdf
n3
≤ = t19 + n3 x 50
≥ = tdf /50 - 0.7
tdf
n3
≤ = 2TCL - 15 + n3 x 2TCL
≥ = (tdf + 15) /2TCL - 1
t
= 150 + n x 50
t
ALE Cycle Time
= 6TCL + n x 2TCL
Note :
- TCL = 1/fOSC (25ns at 40MHz)
- ALE Cycle Time (= Memory Cycle Time) = 6TCL (150ns at 40MHz) for 0 wait state operation
- An address float time of 5ns must be permissible
- t14,t17,t19: See Device Specification Section
Table C-2. Multiplexed Memory Read with Read/Write Delay (Quick Table)
t acc
t oe
n1
≤ = 75
0
≥ = 75 . .
≤ = 125
1
≥ = 125 . .
≤ = 175
≥ = 175 . .
≤ = 35
0
≥ = 35 . .
≤ = 85
1
2
≥ = 85 . .
≤ = 135
2
≤ = 225
3
≥ = 135 . .
≤ = 185
3
≥ = 225 . .
≤ = 275
4
≥ = 185 . .
≤ = 235
4
≥ = 275 . .
≤ = 325
5
≥ = 235 . .
≤ = 285
5
.. ..
..
.
.. ..
t df
n2
..
≥ = 35 . .
n3
≤ = 35
0
≤ = 85
1
.
7/10

C - Application Examples
Table C-3. Multiplexed Memory Write With Read/Write Delay
Symbol
Meaning
40MHz Clock
Variable Timing
twr
Write Pulse Low Time
t ≤ = t12 + n1 x 50
wr
n1 ≥ = twr /50 - 0.8
twr ≤ = 2TCL - 10 + n1 x 2TCL
n1 ≥ = (twr + 10) /2TCL - 1
tdw
Data Valid toWR
tdw ≤ = t22 + n2 x 50
n2 ≥ = tdw /50 - 0.7
tdw ≤ = 2TCL - 15 + n2 x 2TCL
n2 ≥ = (tdw + 15) /2TCL - 1
tdh
Data Hold afterWR
tdh ≤ = t23
tdh ≤ = 35
tdh ≤ = 2TCL - 15
tas
Address Setup
t ≤ = t6 + t8
as
tas ≤ = 25
tas ≤ = 2TCL - 15
t
ALE Cycle Time
t = 150 + n x 50
t = 6TCL + n x 2TCL
Note :
- TCL = 1/ fosc (25ns at 40MHz)
- ALE Cycle Time (= Memory Cycle Time) = 6TCL (150ns at 40MHz) for 0 wait state operation
- An address float time of 5ns must be permissible
- t6,t8,t12,t22,t23 : See Device Specification Section
- Take care of dt h and tas ! These times cannotbe prolonged bywait states.
Table C-4. Multiplexed Memory Write With Read/Write Delay (Quick Table)
t wr
t dw
n1
≤ = 40
0
≥ = 40 . .
≤ = 90
1
≥ = 90 . .
≤ = 140
≥ = 140 . .
n2
≤ = 35
0
≥ = 35 . .
≤ = 85
1
2
≥ = 85 . .
≤ = 135
2
≤ = 190
3
≥ = 135 . .
≤ = 185
3
≥ = 190 . .
≤ = 240
4
≥ = 185 . .
≤ = 235
4
≥ = 240 . .
≤ = 290
5
≥ = 235 . .
≤ = 285
5
. . ..
. .
.
.. ..
8/10

. .
.
C - Application Example
Table C-5. Non-Multiplexed Memory Read With Read/Write Delay
Symbol
Meaning
40MHz Clock
Variable Timing
tacc
Address to Valid Data In
t ≤ = t17 + n1 x 50
acc
n1 ≥ = twr /50 - 1.5
tacc ≤ = 4TCL - 25 + n1 x 2TCL
n1 ≥ = (tacc + 25) /2TCL - 2
toe
RD to Valid Data In
ot e ≤ = t14 + n2 x 50
n2 ≥ = tdw /50 - 0.7
toe ≤ = 2TCL - 15 + n2 x 2TCL
n2 ≥ = (toe + 15) /2TCL - 1
Data Float afterRD
tdf ≤ = t20 +n3 x 50
n3 ≤ = tdf /50 - 0.7
tdf ≤ = 2TCL - 15+ n3 x 2TCL
n3 ≥ = (tdf + 15) /2TCL - 1
tdf
1)
t1)
ALE Cycle Time
t = 100 + n x 50
t = 4TCL + n x 2TCL
Note:
the external memory is only used for code storage,
t be longer than specified here. In this
df may
- Ifcase,
n = max{n1, n2} because n3 = 0.
- ALE Cycle Time (= Memory Cycle Time) = 4TCL (100ns at 40MHz)
- t14,t17,t20: See Device Specification Section
Table C-6. Non-Multiplexed Memory Read With Read/Write Delay (Quick Table)
t acc
t oe
n1
≤ = 75
0
≥ = 75 . .
≤ = 125
1
≥ = 125 . .
≤ = 175
≥ = 175 . .
≤ = 35
0
≥ = 35 . .
≤ = 85
1
2
≥ = 85 . .
≤ = 135
2
≤ = 225
3
≥ = 135 . .
≤ = 185
3
≥ = 225 . .
≤ = 275
4
≥ = 185 . .
≤ = 235
4
≥ = 275 . .
≤ = 325
5
≥ = 235 . .
≤ = 285
5
.. ..
..
.
.. ..
t df
n2
..
≥ = 35 . .
n3
≤ = 35
0
≤ = 85
1
.
9/10

C - Application Examples
Table C-7. Non-Multiplexed Memory Write With Read/Write Delay
Symbol
Meaning
40MHz Clock
Variable Timing
twr
Write Pulse Low Time
t ≤ = t12 + n1 x 50
wr
n1 ≥ = twr/50 - 0.8
twr ≤ = 2TCL - 10 + n1 x 2TCL
n1 ≥ = (twr + 10) /2TCL - 1
tdw
Data Valid toWR
tdw ≤ = t22 + n2 x 50
n2 ≥ = tdw/50 - 0.7
tdw ≤ = 2TCL - 15 + n2 x 2TCL
n2 ≥ = (tdw + 15) /2TCL - 1
tdh
Data Hold afterWR
tdh ≤ = t24
= 15
tdh ≤ = 2TCL - 10
t ≤ = t6 + t8
as
tas ≤ = 25
tas ≤ = 2TCL - 25
td h ≤
tas
Address Setup
t
ALE Cycle Time
t = 100 + n x 50
t = 4TCL + n x 2TCL
Note:
- ALE Cycle Time (= Memory Cycle Time) = 4TCL (100ns at 40MHz) for 0 wait state operation
- t6,t8,t12,t22,t24: See Device Specification Section
- Take care of tdh and tas ! These times cannot beprolonged bywait states.
Table C-8. Non-Multiplexed Memory Write With Read/Write Delay (Quick Table)
t ac c
n1
≤ = 40
0
≥ = 40 . .
≤ = 90
1
≥ = 90 . .
≤ = 140
≥ = 140 . .
t oe
n2
≤ = 35
0
≥ = 35 . .
≤ = 85
1
2
≥ = 85 . .
≤ = 135
2
≤ = 190
3
≥ = 135 . .
≤ = 185
3
≥ = 190 . .
≤ = 240
4
≥ = 185 . .
≤ = 235
4
≥ = 240 . .
≤ = 290
5
≥ = 235 . .
≤ = 285
5
. . ..
. .
.
.. ..
10/10

. .
.
ΑΠΠΕΝ∆ΙΞ ∆
ΑΠΠΛΙΧΑΤΙΟΝ ΝΟΤΕ

PROGRAMMING
FLASH MEMORY OF THE ST10F166
ΙΝΤΡΟ∆ΥΧΤΙΟΝ
The ST10F166 high end microcontroller with on-chip Flash Memory fulfills the requirements of applications
requiring an updat
e to a part or all the program code. The block eras
e capability is also of use during the
applicationdevelopmentstage or for program updating. For data acquisition, the ST10F166 allows the programming of 16 or 32 bits datadependent
in
ly.
Operations on the Flash memory are under software control. Erasure or programming is a simple procedure, however precautions must be taken to prevent damage to the ST10F166.
This applicat
ion note describes the basic characteristics of the Flash memory cell, and the different algorithms used for erasure and programming.
ΦΥΝ∆ΑΜΕΝΤΑΛΣ ΟΦ ΦΛΑΣΗ ΜΕΜΟΡΨ
The Flash memoryincluded inthe ST10F166 combines the EPROM programming mechanism with electrical erasability (like EEPROM) to create a highly
reliableand cost effective memory. A Flash memory cell
consists of a single transistor with a floating gate for charge storage like EPROM, the main difference
being
that Flash memory uses a thinner gate oxide.
Φιγυρε 1. ΣΓΣ−ΤΗΟΜΣΟΝ Φλαση Χελλ ςΣ Επροµ Χελλ
PROGRAMMATION : HOT e INJECTION
ERASURE : THROUGH TUNNEL OXIDE
F N MECHANISM
BULK ERASURE OF ENTIRE
MEMORY IN 1SEC RANGE
PROGRAMMATION : HOT e INJECTION
ERASURE : UV
AN490 / 10,91
This isadvance information from SGS-THOMSON. Details are subject to change without notice.
1/19
ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
The programming mechanism of a cell is based on hot electron injection. This means that the cell control
gate and drain are set to a high voltage and the cell source
grounded.The
is
high voltage on the drain
generates “hot” electrons through the channel, and the high voltage on the control gate traps the free electrons into the floating gate.
Φιγυρε 2. Φλαση Μεµορψ Χελλ Προγραµµινγ Μεχηανισµ
The cell erase mechanism is based onowler-Nor
“F
dheim” tunneling. This means that the cell control gate
is grounded, the cell drain is disconnected and the high voltage
appliedto
is
the cell source. The high electric field between the floating gate and the source removes electrons from the floating gate.
Φιγυρε 3. Φλαση Μεµορψ Χελλ Ερασε Μεχηανισµ
Unlike standard EEPROM memory, where
individualbytes can be erased, the Flash memory of the
ST10F166 performs erase on blocks where the high voltage
appliedto
is
all cells sim
ultaneously.
2/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
A difficulty with Flash memory concerns the requirement to set all the cells of a block to a minimum threshold level suitable for programming and erase operations. Applying a new erasing pulse to a block with a
different storage level on each cell (a different threshold level), can bedangerous
very
for the u
f nctionalit
y
of the Flash memory.
Φιγυρε 4. Φλαση Ερασυρε
CELL THRESHOLD
CELL READ AT ”0”
Programming curve
~ 6V
VERY SMALL DISPERSION
Erasin g curve s
CELL READ AT ”1” (eras ed )
FORBIDDEN AREA
TIME (ms)
ERASING A CELL SET TO 1 = PROBLEM
ALL CELLS MUST BE SET TO 0 BEFORE ERASING
V R00 164 4
A fast erasing cell may have a threshold voltage too low or negative, in this case the transistor is always on
and is read at “one”. This has the effect of leakage on other cells placed on the same array column. Thus
all cells of the column will be read at “one” instead of “zero”.
To avoid this, the user must
equalizethe amount of charge on each cell by programming to “0” all cells of
the bank before every erasure.
For increasedreliability
, the SGS-THOMSON Flash memoryechnology
t
, combined with the use of the
Erase-verify PRESTO F algorithm, provides a tight erase threshold voltage distribution, generating sufficient margin to the faster erasing cell and the minimum threshold level required to read a “one” data value.
ΕΡΑΣΕ & ΠΡΟΓΡΑΜΜΙΝΓ ΧΟΝΤΡΟΛ
To simplify control of the Flash operation modes, the ST10F166 Flash memory includes a Flash Control
Register (FCR) used for all programming or erase operations. Mapped virtually into the Flash address
space, FCR is not accessible during normal memory access modes and must be unlocked by a special
instruction sequence.
To avoid unpredictable programming or erase operation on the Flash memory, the ST10F166 provides
several levels of security:
Φιρστ λεϖελ:
the user must perform a special sequence to enable the FCR and to enter into the writing mode.
Σεχονδ λεϖελ: to operate on the Flash memory, two steps are necessary. First the user must set up the
FCR in the desired configuration, second the operation begins ONLY with the appropriate command.
Τηιρδ λεϖελ:during the writing mode, two bits of FCR (VPPRIV & FCVPP) indicate to the user the status of
VPP (the high voltage) before and during an operation. It is advisable for the user to test them in the erase
or programming routine.
3/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
ΤΗΕ ΠΡΕΣΤΟ Φ ΠΡΟΓΡΑΜ ΩΡΙΤΕ ΑΛΓΟΡΙΤΗΜ
The followingsection explains the Presto F Program Write Algorithm shown in figure 5 for a better understanding of the user. For high
reliability
, it is necessary to follow this algorithm to program the Flash memory.
It is consideredthat the EBC1/VPP pin has been switched to the VPP supply after reset, and the write mode
has been unlocked.
− ΡΕΑ∆ ςΠΠΡΙς
After setting the program mode, a delay ofµs
10must be inserted to allow the device to set its internal high
voltage signals. Then, before starting the proper programming operation, the VPP level must be checked.
VPPRIV is at the “one” level if VPP is correct. If it is not the programming algorithm must be held until VPP
reaches its correct value or until the VPP supply is set correctly.
mov
jnb
fcrrd,
vppriv,
FCR
vpp _fail
;
;
read FCR
test if VPP is high
− Ν=0
Initializationof N variableto zero. The Presto F Program Write algorithm consist of applying several
µs100
pulses o
t each word until a cor
rect verify occurs. The maximum number of programming pulse is fixed to
25, if this limit is reached the word will never be programmed.
In case of several words to program, an Address variable can
initializ
be ed.
mov
lp cnt,
#ALL0
;
reset algo. l
oop count er
− Ωριτε Προγραµµινγ σετυπ χοµµανδ ιντο ΦΧΡ
First step for programming: set FCR with the desired value.
Set FWE bit to enable programming mode.
Clear CKCTL0 & CKCTL1 bits to define a 100
µs programming time.
Choose the configuration:
Set WDWW bit for double word programming.
Clear WDWW bit for word programming.
Set FWMSET bit for write mode.
Take care at this point as this step prepares the device for programming but does not activate the process.
mov
fcrval,
bset
bclr
fwe
ckctl0
bclr
bset
bset
ckctl1
wdww
fw mset
mov
FCR,
#ALL0
;
;
reset FCR data value
FWE=1def ine progr amming op erati on
; CKCTL0=0 )
; CKCTL1=0 ) de fine a 100 µs pulse
; WDWW=
1 de fine 32-b it c onfig urati on
; FWMSE
T=1 enabl e pr ogram mode
fcrva l
;
load FCR with the
desi red value
− Ωριτε ϖαλιδ δατα αδδρεσσ
The followingcommand starts automatically the programming process.
For word programming:
mov
[addrev ],dat al
;
progr amming co mmand
For double word programming:
mov
mov
[addrev ],dat al
[addrev ],dat ah
4/19

;
progr amming co mmand
, even word
; progr amming co mmand
, odd word
ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
Φιγυρε 5. ΠΡΕΣΤΟ Φ Προγραµ Ωριτε Αλγοριτηµ
5/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
− ΩΑΙΤ ΠΤ
The programming time (PT)
dependson the bits CKCTL0 & CKCTL1 of FCR (see setting of FCR). The end
of programming can be detected by polling on the FBUSY bit of FCR.
FBUSY set to “1” indicates programming is in progress.
FBUSY cleared indicates programming has ended.
w
aitp r:
mov
jb
bu
fc rrd,
sy,
FCR
w aitpr
; read FCR
; jump if
progr amming is not
ended
− ΦΧςΠΠ = 0∀ ?
To have a well programmed word, it is important to check if VPP was at the correct value during programming. This is indicated by the status of the FCVPP bit of FCR.
If FCVPP = “0” there was no problem, continue with the algorithm.
If FCVPP = “1” VPP was notenoughhigh during programming, jump to the user defined VPP-fail routine.
An example of this routine could be a reset of FCR, then a new test of the VPPRIV bit and, if all is correct,
redo a programming operation, otherwise exit the programming routine.
jb
fc vpp,
vp p_fai l
;
jump if
FCVPPis set
− ΠΡΟΓΡΑΜ ςΕΡΙΦΨ ΡΕΑ∆
To check if the word is correctly programmed, a comparison must be performed with the data expected. A
Program Verify Read will check the cell margin of the word.
Perform twice the same reading instruction separated by a timeµs.
of 4
This sequence must be made to get a correct reading of the word. This time corresponds to an internal
switching of signals.
− ΧΟΜΠΑΡΕ ΩΙΤΗ ∆ΑΤΑ ΕΞΠΕΧΤΕ∆
This step can be merged with the Program Verify Read step as the comparison instruction is a read instruction. If the data programmed at the address given is different from the data expected, an extra programming
operation must be performed (the next step).
cmp
call a
cmp
jmpr
datal,
cc _UC,
datal,
cc_NZ,
[a ddrev ]
wa it4
[a ddrev ]
prog
; first ins truct ion for PVM (even )
; 4 µs
; secon d in struc tion for PVM
;
jump if the word is not c orrec tly
cmp
call a
cmp
jmpr
datah,
cc _UC,
datah,
cc_NZ,
[a ddrod ]
wa it4
[a ddrod ]
prog
; progr ammed, re start pro gramming
; first ins truct ion for PVM (odd)
; 4 µs
; secon d in struc tion for PVM
;
jump if the word is not c orrec tly
; progr ammed, re start
6/19

pro gramming
ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
− Ν = 25 ?
For each new programming operation the N variable must be incremented; at this point, it must be tested
to verify whether the 25 limit has been reached or not. If yes, the word will never be programmed and the
algorithm should be exited from. In this case a possible solution is to change the address of the word to
program.
add
cmp
lp cnt,
lp cnt,
jmpr
cc_Z,
#01h
#MAXLOOP1
p rg_fa il
;
;
incre ment the algo . loop c
; compare to the limit
jump if
limit
ounte r
has been rea ched
− ΛΑΣΤ Α∆∆ΡΕΣΣ
In case of consecutives words to program, check the address variable to know if the last address has been
reached. If not, increment the address variable and start another programming operation from the beginning of the algorithm.
− ΩΡΙΤΕ ΦΩΕ = 0∀
All the words are programmed, exit the presto F program Write algorithm. All programming or program verify read operation are stopped by a reset of FCR register (especially FWE bit cleared).al
Norm
readingof
the Flash memory can be performed only after this step.
mov
mov
FCR,
#ALL0
FCR, fc rval
; reset FCR and exit pro
gram mode
7/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
ΤΗΕ ΠΡΕΣΤΟ Φ ΕΡΑΣΕ ΑΛΓΟΡΙΤΗΜ
The followingsection explains the Presto F Erase Algorithm shown in figure 6 but all parts already described in the previous section will notexplainedagain.
be
Note that an entire block will be erased instead
of one or two words as programming.
− ΑΛΛ ΩΟΡ∆Σ ΑΤ 0000η
Prior to erasure, program all block addresses to 0000h. This step
equalizesthe charge on each memory
cell of the block. Erasure removes charge from all memory cells regardless of their previous state, and not
performing this programming will drive cells previously at a “one” to be stuck at “one”
lained
(as exp
inthe
Fundamentals of Flash memory section).
The Presto F Program Write Algorithm is used for this block programming. (refer to the previous section).
− ςΑΡΙΑΒΛΕ ΙΝΙΤΙΑΛΙΖΑΤΙΟΝ
Initialize two var
iables:
N = 0 for the pulse count, and the address variable to the first address of the block. N can be incremented
from 0 to 3000.
Note: with each pulse, all the block will be erased.
− ΩΡΙΤΕ ΕΡΑΣΕ ΣΕΤΥΠ ΧΟΜΜΑΝ∆ ΙΝΤΟ ΦΧΡ
As for programming, this step only prepares the device for erasure.
Set FWE,FEE bits to enable erasure.
Clear CKCTL0 & set CKCTL1 bits to define a 10 ms erasing time.
Choose the block configuration for erasure (BE0,BE1).
Clear WDWW bit.
Set FWMSET bit for program mode.
− ΩΡΙΤΕ ΕΡΑΣΕ ΧΟΜΜΑΝ∆
Perform the specific instruction to start automatically the erase process.
mov
[f l_sca n],fl
_scan
;
erase command, era sure star t
− ΩΑΙΤ ΕΤ
The erasing time (ET) depends on the bits CKCTL0 & CKCTL1 of FCR (see setting of FCR). The end of
programming can be detected by
pollingon the FBUSY bit of FCR.
FBUSY set to “1” indicates erase is in progress.
FBUSY cleared indicates erase has ended.
− ΦΧςΠΠ = 0∀ ?
Test VPP to detect any discontinuity in VPP during erasure (see previous section).
8/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
Φιγυρε 6. ΠΡΕΣΤΟ Φ Ερασε Αλγοριτηµ
9/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
• ΕΡΑΣΕ ςΕΡΙΦΨ ΡΕΑ∆
This mode,equivalentto the Program Verify Read,
guaranteesa improved cell margin of a word.
Read the data at the address given by the address variable twice with the same instruction separated by a
time of 4µs.
• ΧΟΜΠΑΡΕ ∆ΑΤΑ = ΦΦΦΦη
Compare the data read to FFFFh. If it equals FFFFh, this address has been erased; continue verification
until the last address of the block has been verified. If not, increment N variable. Apply a new erasing pulse
to the block, and continue until the data is correctly checked or the maximum erase pulse count (3000) has
been reached.
read _ff:
cmp
call a
cmp
al l1,
[ fl_sc an]
cc _UC, wa it4
al l1,
[ fl_sc an]
jmpr
cc_NZ,
erase
; first ins truct ion for EVM
; 4 µs
; secon d in struc tion for EVM
;
jump if
the word is not e
rased
• ΛΑΣΤ Α∆∆ΡΕΣΣ
Check the address variable to see if the last address of the block has been reached. If not, increment the
address variable and start another
Erase Verify Read.
add
cmp
jmpr
fl _scan ,#02h
fl _scan ,#FL_ SIZE
cc_NZ, re ad_ff
; incre ment the bank poi nter
; compare to the last bank a
ddres s
; jump to verif y the next ad
dress
• ΩΡΙΤΕ ΦΩΕ = 0∀
All the block is erased, exit the Presto F Erase algorithm
oppingall
st
erasure or erase verify read operations
with a reset of FCR register (especially FWE, FEE bits cleared)
Normal reading of Flash memory can be performed only after this step.
ΡΥΛΕΣ ΦΟΡ ΥΣΙΝΓ ΤΗΕ ΦΛΑΣΗ ΜΕΜΟΡΨ
- Follow the Presto F Algorithm and verify its correct implementation. This will ensure that all the block has
been programmed before erasure to minimize internal stresses on the memory cells, and to perform writing
operation in a fast and
reliableway.
- Verify VPP status before and after every writing operation.
ΒΑΣΙΧ ΡΟΥΤΙΝΕΣ ΦΟΡ ΕΡΑΣΥΡΕ ΑΝ∆ ΠΡΟΓΡΑΜΜΙΝΓ
This section describes basic routines which can be helpful for the user. Erasure, 32-bit programming and
16-bit programming routines are written as subroutines to allow easy inclusion in a user program.
The followingroutines are written in a way to clarify the operations as well as possible.
The initial conditions are described at the head of the routine,
needed.
if
10/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
;
V ARIABLE D EFINI TIONSFOR THE FLASH M EMORYROUTINES
ALL0
ALL1
equ
equ
0000 0h
0FFFFh
; con stant 0
; con stant FFFF
BLK_START
FL_SIZ E
equ
equ
0300 0h
0300 0h
; first a
ddres s of bank 1
; size of bank 1
FCR
ADDREV
ADDROD
DATAH
DATAL
equ
equ
equ
equ
equ
07FFEh
0000 Ch
0000 Eh
0975 3h
0864 2h
; dummy a ddres s ch osen for FCR
; add ress even (le ast signi fican t bit)
; add ress odd (most si gnifi cant bit)
; data to pro
gram to odd addre ss
; data to pro
gram to even addr ess
MAXLOO
P1
MAXLOO
P2
UNLOCK
WAIT4
WAIT10
equ
equ
equ
equ
equ
0001 Ah
00BB9h
0100 0h
0000 Bh
0001 Fh
; limit of the pr
ogramming loop
; limit of the er
ase loop
; data to unl
ock the writi ng mode
; loop 4 µs
; loop 10 µs
addrev
f crval
LIT
LIT
’R0’
’R1’
; even ad dress poi nter
; reg ister for FCR wri
ting
addrod
datal
datah
LIT
LIT
LIT
’R2’
’R3’
’R4’
; odd add ress poin ter
; reg ister with fi
rst data
; reg ister with se cond data
l pcnt
all1
unlock
val10u
val4u
LIT
LIT
LIT
LIT
LIT
’R5’
’R6’
’R7’
’R8’
’R9’
; alg
; reg
; reg
; cou
; cou
orith m loop c ounte r
ister used in EVM
ister used to unlock
nter 10 µs
nter 4µs
wait_c nt
f l_sca n
LIT
LIT
’R10 ’
’R13 ’
; reg ister to cont rol wait loop
; bank ad dress poi nter
f crrd
LIT
’R15 ’
; reg
fwe
fee
ckctl0
LIT
LIT
LIT
’R1. 0’
’R1. 1’
’R1. 5’
; FCR FWE bit
; FCR FEE bit
; FCR CKC TL0 bit
ckctl1
wdww
be0
be1
busy
LIT
LIT
LIT
LIT
LIT
’R1. 6’
’R1. 7’
’R1. 8’
’R1. 9’
’R15 .2’
; FCR CKC TL1 bit
; FCR WDWW bit
; FCR BE0 bit
; FCR BE1 bit
; FCR BUSY bit
f cvpp
vppriv
LIT
LIT
’R15 .3’
’R15 .4’
; FCR FCVPP bit
; FCR VPP RIV bit
ister
for FCR rea
ding
11/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
; ERASEROUTINE: era sure of bank 1, t his routi ne a ssumes that the bank
; _____ _____ ____ was prev iousl y pr ogrammed to 0 000h befo re e rasur e
; *****
;
;
;
;
; *****
*****
***
INITI AL CONDITIONS: *** *****
ALL WORD
S IN BANK 1
*****
*****
*****
*****
*****
***
HAVETO BE PROGR
A MMED
AT “ZERO”
WITH THE PRE STO F PR OGRAM
WRITE A LGORITHM
*****
*****
*****
*****
*****
*****
*****
f _eras e:
;
; REG ISTERS IN ITIAL IZATI ON
;
mov
lp cnt,
#ALL0
*****
*****
*****
; reset a
*****
lgo.
*****
*****
*
loop cou nter
mov
mov
fcrval, #ALL0
unlock, #UNLOCK
; reset FCR d
ata value
; load un lock data
mov
mov
mov
mov
mov
val10u, #WAIT10
val4u,
#WAIT4
wait_cn t,#AL L0
all1,
#ALL1
fl _scan , #BLK_START
; load 10 µs l oop data
; load 4 µs loop data
; reset w ait loop counter
; set R2 to
FFFF
; load fi
rst bank addr ess
;
; UNL OCK SEQUE
NCE FOR ENTERING IN THE WR ITE MODE
;
mov
FCR,
unlo ck
; first i
nstru ction
mov
[unlock ],unl ock
; sec ond instr uctio n of unlock
calla
cc_UC,
; seq uence to ente r in the write
; mode
; time out 10
µs to set in
terna l
; sig nals
wait 10
;
; FCR SET UP FOR ERASU
RE
;
bset
fwe
bset
fee
bclr
ck ctl0
bset
bclr
ck ctl1
wdww
bset
bclr
bset
mov
be0
be1
fw mset
FCR,
; FWE=1 ) these two i
nstru ction s
; FEE=1 ) def
ine the erasu re
; CKC TL0=0 )
; CKC TL1=1 )
; WDWW=0
defin e a 10ms pulse
; BE0=1 )
; BE1=0 ) sel
ect bank 1
; FWM SET=1 con firm writ e mode
; load FCR set up
fcrv al
12/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
;
; TEST VPP
;
mov
jnb
fcrrd,
vp priv,
FCR
vpp _fail
; read FCR
; test if VPP is
high
;
; FLASH E RASUR
E
;
erase:
add
cmp
jmpr
mov
waiter : mov
jb
;
; TEST VPP
lp cnt,
lp cnt,
cc_Z,
#01h
#MAXLOOP2
eras _fail
; inc rement the al
go. loop counter
; com pare to the limit
; jump if limit has b
een reach ed
[f l_sca n],fl _scan
fc rrd,
FCR
busy,
waiter
; erase c omman
d, e rasur e start
; read FCR
; jump if era
sure is not ended
;
jb
fc vpp,
vpp_fail
; jump if FCVPP is set, to know if
; a fail
occured becau se VPP did not
; have the co
rrect value d uring
; era sure
;
; ERASE V ERIFY MODE
;
r ead_f f:cmp
all1,
calla
cc_UC,
[fl_ scan]
wait 4
; first i
nstru ction for EVM
; time out 4
µs
[fl_ scan]
eras e
; sec ond instr uctio n for EVM
; jump if the word is not erased
cmp
jmpr
all1,
cc _NZ,
add
cmp
jmpr
fl _scan ,#02h
fl _scan ,#FL_ SIZE
cc _NZ, read _ff
; inc rement the bank p
ointe r
; com pare to the last bank add ress
; jump to ver
ify the next addr ess
;
; EXIT OF WRITE MODE
;
mov
mov
ret
fcrval,
FCR;
#ALL0
fcrv al
; reset FCR and e
xit write mode
; ret
urn to m ain progr am
13/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
; 32-BI T PR OGRAM
M ING ROUTINE:
progr amming of add ress 0000 Ch with 0
; _____ _____ _____ _____ _____ __ and ad
dress 000 0Eh with 0975 3h
8642h
bit32p rg:
;
; REG ISTER INI TIALI ZATION
;
mov
mov
mov
mov
mov
lp cnt,
#ALL0
fcrval, #ALL0
unlock, #UNLOCK
val10u, #WAIT10
val4u,
#WAIT4
; reset a
lgo. loop cou nter
; reset FCR d
ata value
; load un lock data
; load 10 µs l oop data
; load 4 µs loop data
mov
mov
mov
mov
mov
wait_cn t,#AL L0
all1,
#ALL1
datal,
#DATAL
datah,
#DATAH
addrev, #ADDREV
; reset w ait loop counter
; set R2 to
FFFF
; load data for e
ven addre ss
; load data for odd a
ddres s
; load even a
ddres s
mov
addrod, #ADDROD
; load odd ad
dress
;
; UNL OCK SEQUE
NCE FOR ENTERING IN THE WR ITE MODE
;
mov
FCR,
unlo ck
; first i
mov
calla
;
; FCR SET UP
[unlock ],unl ock
cc_UC,
nstru ction
; sec ond instr uctio n of unlock
; seq uence to ente r in the write
; mode
; time out 10
µs to set in
terna l
; sig nals
wait 10
FOR PROGR
A MMING
;
bset
bclr
bclr
bset
fwe
ck ctl0
ck ctl1
wdww
; FWE=1 d efine pro gramming opera tion
; CKC TL0=0 )
; CKC TL1=0 ) defin e a 100 µs pulse
; WDWW=1 defin e 32 -bit conf igura tion
bset
mov
fw mset
FCR,
fcrv al
fcrrd,
vp priv,
FCR
vpp _fail
; FWM SET=1 ena ble write mode
; load FCR set up
;
; TEST VPP
;
mov
jnb
; read FCR
; test if VPP is
;
14/19

high
ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
; FLASH P ROGRA
M MING
;
prog:
add
cmp
lp cnt,
lp cnt,
jmpr
mov
cc_Z,
prg_ fail
[addrev ],dat al
; jump if limit has b
een reach ed
; pro gramming command, even word
[addrev ],dat ah
fc rrd,
FCR
busy,
wait pr
; pro gramming command, odd word
; read FCR
; jump if pro
gramming is not e nded
fc vpp,
vpp_fail
; jump if FCVPP is set, to know if
; a fail
occured becau se VPP did not
; have the co
rrect value d uring
; pro gramming
mov
waitpr : mov
jb
;
; TEST VPP
#01h
#MAXLOOP1
; inc rement the al
go. loop counter
; com pare to the limit
;
jb
;
; PRO GRAMVERIFY MODE
;
cmp
calla
datal,
cc_UC,
[add rev]
wait 4
; first i
nstru ction for PVM (even)
; time out 4
µs
cmp
jmpr
datal,
cc _NZ,
[add rev]
prog
cmp
calla
datah,
cc_UC,
[add rod]
wait 4
; sec ond instr uctio n for PVM
; jump if the word is not cor
rectl y
; pro grammed, resta rt p rogra mming
; first i
nstru ction for PVM (odd)
; time out 4
µs
cmp
jmpr
datah,
cc _NZ,
[add rod]
prog
; sec ond instr uctio n for PVM
; jump if the word is not cor
rectl y
; pro grammed, resta rt p rogra mming
;
; EXIT OF WRITE MODE
;
mov
fcrval,
mov
ret
FCR,
#ALL0
fcrv al
; reset FCR and e
xit write mode
; ret
urn to m ain progr am
15/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
; 16-BI T PR OGRAM
M ING ROUTINE: pr ogramming of addre ss 0 000Ch with 08
; _____ _____ _____ _____ _____ ___
642h
bit16p rg:
;
; REG ISTERS IN ITIAL IZATI ON
;
mov
lp cnt,
#ALL0
mov
fcrval, #ALL0
mov
unlock, #UNLOCK
mov
mov
mov
mov
mov
; reset a
lgo. loop cou nter
; reset FCR d
ata value
; load un lock data
; load 10 µs l oop data
; load 4 µs loop data
; reset w ait loop counter
; set R2 to
FFFF
; load data
val10u, #WAIT10
val4u,
#WAIT4
wait_cn t,#AL L0
all1,
#ALL1
datal,
#DATAL
mov
addrev, #ADDREV
; load ad
;
; UNL OCK SEQUE
NCE FOR ENTERING IN THE WR ITE MODE
;
mov
FCR,
unlo ck
; first i
mov
calla
;
; FCR SET UP
[unlock ],unl ock
cc_UC,
dress
nstru ction
; sec ond instr uctio n of unlock
; seq uence to ente r into the w
; mode
; time out 10
; sig nals
wait 10
µs to set in
rite
terna l
FOR PROGR
A MMING
;
bset
bclr
fwe
ck ctl0
; FWE=1 d efine pro gramming opera tion
; CKC TL0=0 )
bclr
bclr
ck ctl1
wdww
; CKC TL1=0 ) defin e a 100 µs pulse
; WDWW=0 defin e 16 -bit conf igura tion
bset
mov
fw mset
FCR,
fcrv al
fcrrd,
vp priv,
FCR
vpp _fail
; FWM SET=1 ena ble progr am mode
; load FCR set up
;
; TEST VPP
;
mov
jnb
; read FCR
; test if VPP is
;
16/19

high
ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
;
; FLASH P ROGRA
M MING
;
progw:
add
lp cnt,
cmp
jmpr
lp cnt,
cc_Z,
mov
waitpr w: mov
jb
;
; TEST VPP
#01h
; inc rement the al
#MAXLOOP1
prg _fail
go. loop counter
; com pare to the limit
; jump if limit has b
een reach ed
[addrev ], d atal
fc rrd,
FCR
busy,
wait prw
; pro gramming command
; read FCR
; jump if pro
gramming is not e
fc vpp,
vpp_fail
; jump if FCVPP is set, to know if
; a fail
occured becau se VPP did not
; have the co
rrect value d uring
; pro gramming
nded
;
jb
;
; PRO GRAMVERIFY MODE
;
cmp
calla
datal,
cc_UC,
[add rev]
wait 4
; first i
nstru ction for PVM
; time out 4
µs
cmp
jmpr
datal,
cc _NZ,
[add rev]
prog w
; sec ond instr uctio n for PVM
; jump if the word is not cor
rectl y
; pro grammed, resta rt p rogra mming
;
; EXIT OF WRITE MODE
;
mov
fcrval,
#ALL0
mov
ret
FCR,
fcrv al
; reset FCR and e
xit write mode
; ret
urn to m ain progr am
SUBROUTINES USED IN W RITIN G OPERATION
____ _____ _____ _____ _____ _____ _____ ___
wait4:
add
cmp
wait_cn t,#01 h
wait_cn t,val 4u
; inc rement co unter
; com pare with final v
jmpr
mov
ret
cc _NZ, wait 4
wait_cn t,#AL L0
; jump if not equal
; reset c
ounte r
alue
17/19

ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
wait10 : add
cmp
jmpr
mov
ret
wa it_cn t,#01 h
wait_cn t,val 10u
; inc rement co unter
; com pare with final v
cc _NZ, wait 10
wait_cn t,#AL L0
; jump if not equal
; reset c
ounte r
vpp_fa il:
; VPP FAIL RO
UTINE DEFINED BY THE USER
prg_fa il:
; PRO GRAMFAIL ROUTINE DEFINED BY THE USER
eras_f ail:
; ERASE F AIL ROUTINE DEFINED BY THE USER
18/19

alue
ΠΡΟΓΡΑΜΜΙΝΓ ΦΛΑΣΗ ΜΕΜΟΡΨ
THE SOFTWARE INCLUDED IN THIS NOTE IS FOR GUIDANCE ONLY. SGS-THOMSON SHALL NOT
BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT
TO ANY CLAIMS ARISING FROM USE OF THE SOFTWARE.
19/19


ΑΠΠΕΝ∆ΙΞ Ε
Εξαµπλε Βοοτ−Στραπ Λοαδερ φορ τηε ΣΤ10Φ166
ιν Σινγλε−Χηιπ Μοδε
ΙΝΤΡΟ∆ΥΧΤΙΟΝ
Ωιτη ιτσ ον−χηιπ Φλαση µεµορψ, τηε ΣΤ10Φ166 ισ ΣΤ10Φ166 σεριαλ πορτ Π0, ιντο τηε ιντερναλ ΡΑΜ ανδ
τηε ιδεαλ δεϖιχε φορ προτοτψπινγ, πρεπροδυχτιον,αφτερ ρεχειϖινγ α δεφινεδ νυµβερ οφ βψτεσ ϕυµπσ το
µεδιυµ ϖολυµε προδυχτιον ορ ρεπρογραµµαβλε α δεφινεδ ΡΑΜ αδδρεσσ εξεχυτινγ τηε λοαδεδ προ−
αππλιχατιονσ. Τηισ νοτε γιϖεσ αν εξαµπλε οφ τηε ιµ− γραµ. Οτηερ προγραµ φυνχτιοναλιτψ ισ ποσσιβλε.
πλεµεντατιον οφ αν ον−χηιπ λοαδερ φορ εντερινγ προ−Ηοωεϖερ, τηε εξαµπλε προποσεδ ωιλλ βε συιταβλε φορ
γραµ ορ χοδε ιντο τηε Φλαση µεµορψ φορ α µοστ αππλιχατιονσ.
ΣΤ10Φ166 χονφιγυρεδ ιν σινγλε χηιπ µοδε (νο εξ−
τερναλ µεµορψ).
Αχχεσσ το τηε Βοοτ−Στραπ Λοαδερ
Ωηεν τηε ΣΤ10Φ166 ισ χονφιγυρεδ ιν σινγλε χηιπ
µοδε, τηε ΣΤ10Φ166 προγραµ ωιλλ σταρτ ατ αδδρεσσ Ιν ορδερ το εξεχυτε τηε Βοοτ−Στραπ λοαδερ, τηε
0000η οφ τηε µεµορψ σπαχε (ωιτηιν τηε ΦΛΑΣΗ ΣΤ10Φ166 ηασ το βε φορχεδ ιντο τηε βοοτ−στραπ
µεµορψ). Τηερεφορε ιν τηε χασε οφ α τοταλλψ ερασεδ µοδε. Τηισ ισ δονε ωιτη α πυλλ υπ ρεσιστορ χον−
νεχτεδ το τηε ΑΛΕ πιν ωηιλε α ηαρδωαρε ρεσετ
Φλαση µεµορψ, ορ ωηενυπγραδινγ τηε χοδε ινσιδε
τηε Φλαση µεµορψ, ανοτηερ µεανσ το σταρτ ανδ προ− (ΡΣΤΙΝ) ισ αππλιεδ το τηε δεϖιχε. Τηισ ισ ποσσιβλε
δυε το τηε φαχτ τηατ δυρινγ ρεσετ, ΑΛΕ πιν ισ υσεδ ασ
γραµ τηε δεϖιχε µυστ βε υσεδ το πασσ ρουνδ τηε
αν ινπυτ ανδ ισιντερναλλψ
πυλλεδ δοων τηρουγη α
Φλαση µεµορψ.
ωεακ πυλλδοων.Τηεν ωιτη τηε δεαχτιϖατιον οφ τηε
ρεσετ, τηισ χονδιτιον ισ ιντερναλλψ λατχηεδ ανδ ιµµε−
Ον−Χηιπ Βοοτ−Στραπ Λοαδερ
διατελψ τηε ΣΤ10Φ166 σταρτσ τηε εξεχυτιον οφ τηε ιν−
Α ΡΟΜ αρεα οφ 256 βψτεσ εξιστσ ον τηε ΣΤ10Φ166 τερναλ ρουτινε ωαιτινγ φορ τηε Βοοτ Στραπ τριγγερ
ιν αδδιτιον το τηε Φλαση µεµορψ ωηιχη χαν βε προ− χονδιτιον το ινϖοκε τηε Βοοτ−Στραπ ρουτινε.
γραµµεδ ασ τηε Φλαση µεµορψ βυτ νοτ ερασεδ.
Ιν τηισ εξαµπλε τηισ χονδιτιον ισΝΜΙ
α ιντερρυπτ απ−
Τηισ ΡΟΜ αρεα ισ αχχεσσεδ ιν α σπεχιαλ µοδε τηατ πλιεδ το τηε ΣΤ10Φ166 βεφορε τηε ιντερναλ ρουτινε
ωιλλ βε δεταιλεδ ιν τηε
φολλοωινγ
σεχτιονσ.
ωιλλ ενδεδ. Ιφ τηε χονδιτιον ισ νοτ φυλφ
ιλλεδτηεν α σοφτ−
ωαρε
ρεσετ
ινστρυχτιον
(ΣΡΣΤ)
ισ
εξεχυτεδ ανδ ασ
Τηε Βοοτ−ΣτραπΛοαδερ, δεφινεδ βψ τηε υσερ, µαψ
τηε σινγλε χηιπ µοδε ισ σελεχτεδ τηρουγη τηε ΕΒΧ1,
βε προγραµµεδ ιντο τηισ ΡΟΜ αρεα αλλοωινγτηε
ΦΛΑΣΗ µεµορψ το βε λοαδεδ φροµ αν εξτερναλ σψσ− ΕΒΧ0 ανδ ΒΥΣΑΧΤ πινσ, τηε ΣΤ10Φ166 προγραµ
τεµ. Τηισ ρεπρεσεντσ τηε ονλψ ωαψ το αχχεσσ τηε ιν− ωιλλ σταρτ ατ αδδρεσσ 0000η οφ τηε Φλαση µεµορψ.
τερναλ ΡΑΜ ιν ορδερ το προγραµ τηε ΦΛΑΣΗ Σινχε τηε ΦΛΑΣΗ µεµορψ ισ στιλλ υνπρογραµµεδ,
υνεξπεχτεδ προγραµ εξεχυτιον ωιλλ οχχυρ.
µεµορψ (ωηιχη χαν νοτ βε προγραµµεδ φροµ α
προγραµ ωιτηιν τηε ΦΛΑΣΗ µεµορψ ιτσελφ). Τηισ Ιτ ισ ρεχοµµενδεδ το εντερ τηε βοοτ−στραπ µοδε
ρουτινε ισ λοαδεδ ον τηε δεϖιχε ωιτη τηε Προγραµ− ωιτη ΕΒΧ1, ΕΒΧ0 γρουνδεδ, ΒΥΣΑΧΤ τιεδ το 1∀
µινγ Βοαρδ προϖιδεδ βψ ΣΓΣ−ΤΗΟΜΣΟΝ Μιχρο− ανδ ΑΛΕ πυλλεδ ηιγη δυε το τηε φαχτ τηατ τηε στατε οφ
ελεχτρονιχσ ανδ ισ νοτ αχχεσσιβλε φροµ ανψ οτηερΑΛΕ πιν ισ νοτ σαµπλεδ βψ α σοφτωαρε ρεσετ. Α ηαρδ−
ιντερναλ ορ εξτερναλ µεµορψ.
ωαρε ρεσετ (ονΡΣΤΙΝ) ωιλλ τηεν σταρτ τηε δεϖιχε ιν
Τηε φολλοωινγεξαµπλε δεσχριβεσ τηε λοαδερ οφ α τηισ σπεχιαλ µοδε, ωηιχη ωιλλ ενδ ωιτη α σοφτωαρε
σηορτ προγραµ ανδ τηε τεχηνιθυε το αχχεσσ ιτ. Τηε ρεσετ το αδδρεσσ0000η οφ τηε Φλαση µεµορψ.
λοαδερ ρεχειϖεσ δατα φροµ α ηοστ σψστεµ, ϖια τηεΤηε ωινδοω φορ τηε αχτιϖατιον ΝΜΙ
οφ ιντερρυπτ ισ
αππροξιµατελψ 1µσ το 10 µσ αφτερ τηε δεαχτιϖατιον
οφΡΣΤΙΝ.
1/4
Ε − Βοοτ−Στραπ Λοαδερ
Φιγυρε Ε−1. ΣΤ10Φ166 Μοδε Φλοω
Οπερατιον οφ τηε εξαµπλε Βοοτ−Στραπ Λοαδερ
Ιν συµµαρψ, τηισ προχεδυρε ρεθυιρεσ
τηε φολλοωινγ
Ωηεν τηε Βοοτ−Στραπλοαδερ ισ ινϖοκεδ ωιτη τηε αχτιονσ φροµ τηε ηοστ σψστεµ:
ΝΜΙ ιντερρυπτ, φιρστ τηε ΣΤ10Φ166 ισ ιαλιζεδ
ινιτ
1. Σενδ α ζερο βψτε (8 βιτ δατα, νο παριτψ, ονε στοπ
(Ω∆Τ δισαβλεδ,ΣΨΣΧΟΝ σετ, ΧΠ,ΣΠ). Τηεν τηε
βιτ, στανδαρδ βαυδ ρατε)
δεϖιχε ωαιτσ φορ τηε ρεχεπτιον οφ 00 βψτε ατ πιν
νοωλεδγε βψτε55η
Ρξ∆0. Τηισ βψτε (8 βιτ δατα, νο παριτψ, ονε στοπ βιτ 2. Ωαιτ φορ ανδ ϖεριφψ τηε αχκ
ανδ α στανδαρδ βαυδ ρατε: 9600 Βαυδ ορ λεσσ) ισ 3. Τρανσµιτ 960 βψτεσ
σεντ βψ τηε χοννεχτεδ ηοστ. Τηε τιµε λενγτη οφ Ιφ λεσσ τηαν 960 βψτ
εσ αρε νεεδεδ φορ τηε προγραµ
τηεσε 9 0 βιτσ ισ µεασυρεδ ανδ υσεδ το χαλχυλατε χοδε, τηε ηοστ ηασ το τρανσµιτ δυµµψ δατα το φιλλ
τηε πρεσχαλερ φορ τηε βαυδ ρατε γενερατορ. Σεριαλτηε φρεε βψτεσ, σινχε τηε λοοπ ωιλλ νοτ τερµινατε υντιλ
πορτ 0 ισ τηενινιτιαλιζ
εδ, ανδ τηε αχκνοωλεδγε βψτε
960 βψτεσ αρε ρεχειϖεδ.
55η ισ τρανσµιττεδ το τηε ηοστ το χονφιρµ τηατ τηε
Ωηεν τηε Βοοτ−Στραπ ρουτινε ισ
υσεδ το λοαδ αδδι−
χοµµυνιχατιον ισ προπερλψ εσταβλισηεδ.
τιοναλ προγραµ ιν τηε ιντερναλ ΡΑΜ, χαρε µυστ βε
Τηε ρουτινε εξεχυτεσ τηεν α λοοπ, ωαιτινγ φορ 960 τακεν ωιτη τηε πηψσιχαλ αδδρεσσεσ ανδ νεχεσσαρψ
βψτεσ ϖια πορτ Π0. Τηεσε βψτεσ αρε στορεδ χονσεχυ− ρεσουρχεσ οφ τηε ιντερναλ ΡΑΜ, σπαχε µυστ βε ρε−
τιϖελψ ιντο τηε ιντερναλ ΡΑΜ, σταρτινγ φροµ αδδρεσσ
σερϖεδ φορ ρεγιστερ βανκσ, σταχκ αρεα ανδ ϖαρι−
0ΦΑ40η. Αφτερ τηατ τηε λοοπ ισ εξιτεδ, ανδ α ϕυµπ το αβλεσ.
αδδρεσσ 0ΦΑ40η ισ περφορµεδ. Τηε δατα στορεδ ιν
ΡΑΜ ισ τηεν εξεχυτεδ ασ προγραµ χοδε. Τηισ προ− Τηε Βοοτ Στραπ µοδε µυστ βε εξιτεδ φροµ βψ εξε−
γραµ, δετερµινεδ βψ τηε υσερ, µαψ αλλοω τηε φυλλ χυτινγ αν ΣΡΣΤ ινστρυχτιον.
δοωνλοαδανδ προγραµµινγ οφ φυρτηερ χοδε ορ δατα ΩΑΡΝΙΝΓ: Ιφ τηε ΦΛΑΣΗ µεµορψ προτεχτιον ηασ
ιντο τηε ΦΛΑΣΗ µεµορψ.
βεεν εναβλεδ ωιτη τηε προγραµµινγ βοαρδ, ιτ ισ
νεχεσσαρψ το φιρστ δισαβλε τηε προτεχτιον υσινγ τηε
ΡΠΡΟΤ βιτ οφ ΦΧΡ ιν τηε λοαδεδ προγραµ. Τηισ ισ το
αλλοω τηε ινιτιαλ σοφτωαρε ρουτινεσ ιν τηε ΡΑΜ το προ−
γραµ ανδ ερασε τηε ΦΛΑΣΗ µεµορψ.
2/4

Ε − Βοοτ−Στραπ Λοαδερ
Φιγυρε Ε−2. Βοοτ−Στραπ Λοαδερ Οπερατιον
Φιγυρε Ε−3. Ασσεµβλερ Εξαµπλε
TOS
StartA ddres s
EndAddress
RamRoutineS tart
equ
equ
equ
equ near
0FA40h
0FA40h
0FDFFh
0FA40h
;
;
;
;
Top of s tack, 64 byte s max
Start Add ress of RAM area
End Addre ss of RAM area
Start Add ress of RAM routi ne
REGBAS
equ
ss kdef
0FA00h
0
; Regis ter bank decl arati
; Stack res ervat ion
BTLCODE
section
code
MOV
SYSCON,#SYSCNF
on
BTL_IN IT:
; initi
alize
system
; con figur ation reg ister
; SYS CNF Defin ed by the user
; disab le w atchd og t imer
; set regis terba nk
;set stack poi nter
DI SWDT
MOV
CP,# REGBAS
MOV
SP,# TOS
3/4

Ε − Βοοτ−Στραπ Λοαδερ
Ασσεµβλερ Εξαµπλε (Χοντδ)
GetBau dRate :
WaitSt artBi t:
JB
P3.1 1,Wai tStar tBit
; wait
BSET
T6R
;start
for
star t bit at RXD0
JNB
BCLR
MOV
P3.1 1,Wai tStop Bit
T6R
R1,# 36
MOV
DIVU
MOV
ROR
JMPR
MDL,T6
R1
R2,MDL
R2,# 1
CC_C,Init
SUB
R2,# 1
; adjus t by one for baud
; rate ge
nerat or
MOV
BSET
S0BG,R2
P3.1 0
; load
; initi
baud rate gene rator
alize TXD0 ou tput
BSET
MOV
DP3. 10
S0CON,#80 11h
; initi
alize
timer T6
WaitSt opBit :
I nitSe rialP
; wait
;stop
; load
for stop bit at
time r T6
divi de f actor
RXD0
; baudr ate = (( T6/36 )/2); get divis ion
; round result
1
resul t
Seria lPort
ort:
ser ial
; 8bit data ,no parit
; recei ver enabl ed
port
0:
y,one stop bit
SendAcknowl edge:
MOV
S0TBUF,#5 5h
; send ackn owled ge byte
; for baudr ate check
MOV
R0,# Start Addre ss
JNB
MOVB
S0RI R,Rec eiveL oop
[R0] ,S0RBUF
BCLR
CMPI1
JMPR
JMPA
S0RI R
; clear rec eive inte rrupt
R0,# EndAddress
; all bytes rec eived ?
CC_NE,Rec eiveL oop
;if not c
ontin ue loop
CC_UC,RamRouti neSta rt ; yes: jump to RAM routi
Receiv eData :
Receiv eLoop :
BTLCODE ENDS
END
4/4

; wait for rece ive inter
; store rec eived byte
rupt
requ est
req uest
ne
bit
APPENDIX F

DATASHEET OVERVIEW
This Appendix presents an overview of the ST10x166 product range:
ST10F166
ST10166
ST10R166
: 16 BIT MCU WITH 256K FLASH MEMORY AND A/D CONVERTER
: 16 BIT MCU WITH 32K INTERNAL ROM AND A/D CONVERTER
: 16 BIT MCU WITH A/D CONVERTER, ROMLESS


ST10F166

16 BIT MCU WITH 256K FLASH MEMORY
AND A/D CONVERTER
ADVANCE DATA
High-Performance 16-bit CPU with 4-Stage
Pipeline
100ns Instruction Cycle Time at 20MHz CPU
Clock
500ns Multiplication (16x16 bits), 1µs Division
(32/16 bits)
Enhanced Boolean Bit Manipulation Facilities
Register-Based Design with Multiple Variable
Register Banks
Single-Cycle Context Switching Support
256 Kbyte Linear Address Space for Code and
Data
1Kbyte On-Chip RAM
32 KBYTE ON-CHIP FLASH MEMORY WITH
BANK ERASE
512 byte On-Chip Special Function Register
Area
8-Channel Interrupt-Driven Single-Cycle Data
Transfer Facilities via Peripheral Event Controller (PEC)
16-Priority-Level Interrupt System
10-Channel 10-bit A/D Converter with 9.75µs
Conversion Time
16-Channel Capture/Compare Unit
2 Multi-Functional General Purpose Timer Units
2 Serial Channels (USARTs)
Programmable Watchdog Timer
76 General Purpose I/O Lines
Temperature Range: 0 to 70 °C, -40 to 85 °C, -40
to 110 °C)
1.2 micron multifunctional CMOS technology
100 Pin Metric Plastic Quad Flat Pack (PQFP)
Rectangular Package
FLASH MEMORY PROTECTION OPTIONAL
PQFP100
(Ordering Information at the end of the datasheet)
A complete set of development tools is also available including:
- ’C’-Compiler
- Assembler, Linker/Locater
- Librarian
- Emulator
- Flash Programming Board
- Starter Kit
January 1992
This is advance information from SGS-THOMSON. Details are subject to change without notice.
1/17
ST10F166
Figure 1. ST10F166 Pin Configuration
Table 1. PINOUT Description ST10F166
Pin
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin
name
P0.3
P0.4
P0.5
P0.6
P0.7
VSS
VCC
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P4.0
P4.1
VCC
XTAL2
XTAL1
VSS
BUSACT
EBC1/VPP
EBC0
ALE
RD
RSTIN
RSTOUT
NMI
P1.0
Pin
number
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin
name
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VCC
VSS
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
P5.0
P5.1
P5.2
2/17

Pin
number
Pin
name
Pin
number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P5.3
P5.4
P5.5
VAREF
VAGND
P5.6
P5.7
P5.8
P5.9
VSS
VCC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
VSS
VCC
P3.0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
name
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
VCC
VSS
P3.13
P3.14
P3.15
P0.0
P0.1
P0.2
ST10F166
ABSOLUTE MAXIMUM RATINGS
Ambient temperature
under bias (TA)
0 to + 70 °C
- 65 to + 125 °C
Storage temperature (TST)
+ 6.5 V
Supply Voltage (VCC)
Input Voltage (VIN min. = -3.0 V
for pulse width less than 15ns)- 0.5 to VCC + 0.5 V
-0.6 to 13.5V
VPP Voltage
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note:The ST10F166 is also offered in the temperature range -40° to
105°C and -40° to 85°C.
All the following time specifications refer to a CPU clock of
20MHz which is identical to an oscillator frequency (f osc) of
40MHz.
DC CHARACTERISTICS
TA = 0 to + 70 °C; VCC = 5 V ± 10%; VSS = 0 V
Symbol
Limit Values
Parameter
min.
max.
- 0.5
0.2 VCC
- 0.1
Unit
Test Condition
V
-
V
-
VIL
Input Low Voltage
VIH
Input High Voltage
(all except RSTIN and XTAL1)
0.2 VCC
+ 0.9
VCC + 0.5
VIH1
Input High Voltage RSTIN
0.6 VCC
VCC + 0.5
V
-
VIH2
Input High Voltage XTAL1
0.7 VCC
VCC + 0.5
V
-
VOL
Output Low Voltage
(Ports 0, 1, 4, ALE, RD, WR,
BHE, CLKOUT, RSTOUT
-
0.4
V
IOL = 2.4mA
VOL1
Output Low Voltage
(all other outputs)
-
0.4
V
IOL1 = 1.6mA
VOH
Output High Voltage
(Ports 0, 1, 4, ALE, RD, WR,
BHE, CLKOUT, RSTOUT)
0.9 VCC
2.4
-
V
VOH1
Output High Voltage
(all other outputs)
0.9 VCC
2.4
−
V
V
IOH = - 50µA
IOH = - 1.6mA
IOZ
Input Leakage Current (Ports 0,
1,2,3,4, NMI, EBC0, BUSACT)
-
±1
mA
0 V<Vin<VCC
±10
mA
VPP < VCC
IPPS
Vpp leakage Current
(EBC1/Vpp)
IOH = - 100µA
IOH = - 2.4mA
3/17

ST10F166
DC Characteristics (Continued)
Symbol
Limit Values
Parameter
min.
max.
Unit
Test Condition
RRST
Reset Pullup Resistor
50
150
kΩ
-
IIL
XTAL1 Input Current
-
tbd
µA
0 V<Vin<VCC
CIO
Pin Capacitance
(digital inputs/outputs)
-
10
pF
f= 1MHz
TA = 25 °C
ICC1
Power Supply Current
-
240
mA
1/TCL = 40MHz
IID
Idle Mode Supply Current
-
25
mA
1/TCL = 40MHz
IPD
Power Down Mode Supply
Current
-
150
µA
ICC2
VCC writing current
-
240
mA
IPP1
VPP read current
-
200
±10
µA
IPP2
VPP writing current
VPP
VPP durint write/read op.
11.4
50
mA
12.6
V
VCC = 2.5 V 1)
1/TCL = 40MHz
32 bit
programming
VPP > VCC
VPP < VCC
1/TCL = 40MHz
32 bit
programming
VPP = 12V
A/D CONVERTER CHARACTERISTICS
TA = 0 to + 70 °C; VCC = 5 V ± 10%; VSS = 0 V; VAREF = VCC ± 0.2 V; VAGND = VSS ± 0.2 V
Symbol
VAIN
CI
tS
tC
TUE
IREF
IAIN
Limit Values
Parameter
Analog Input Voltage
Analog Input Capacitance
Sample Time
Conversion Time
Total Unadjusted Error
VAREF Supply Current
Analog Input Current
min.
max.
VSS - 0.2
±500
VCC + 0.2
70
63 TCL
390 TCL
±2
5
Notes:
1) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V CC - 0.1 V to
VCC, VREF = 0 V, all outputs (including pins configured as outputs)
disconnected.
2) This parameter specifies the time during which the input capacitance CI can be charged/decharged by the external source. It must
be guaranteed, that the input capacitance CI is fully loaded within
these 63 TCLs.
4/17

Unit
Test Condition
V
pF
2)
3)
4)
5)
LSB
mA
nA
63 TCL is 1.575µs at 20MHz CPU clock. After the end of the sample
time t s, changes of the analog input voltage have no effect on the
conversion result.
3) This parameter includes the sample time t s. 390 TCL is 9.75µs at
20MHz CPU clock.
4) IREF in Power Down Mode: TBD
5) This parameter specifies the static input current for an analog input channel, e.g. when the channel is not selected for conversion.
ST10F166
AC CHARACTERISTICS
Testing Waveforms
Figure 8. Input Output Waveforms
AC Inputs during testing are driven at 2.4 V for a
logic ’1’ and 0.4 V for a logic ’0’.
Timing measurements are made at VIH min for a
logic ’1’ and VIL max for a logic ’0’.
Figure 9. Float Waveforms
For timing purposes a port pin is no longer floating
when a 100mV change from load voltage occurs,
but begins to float when a 100mV change from the
loaded VOH/VOL level occurs (IOH/IOL=20mA)
5/17

ST10F166
AC CHARACTERISTICS (Continued)
In the AC Characteristicswaveforms, the mid-point
of a signal transition is mostly used as the timing
reference point.
Figure 10. Timing Reference Points
6/17

If not specifically specified in the drawings, the exact timing reference points are given by the parameter description according to the following
figures (test voltage levels and float state references shown on previous page):
ST10F166
AC CHARACTERISTICS (Continued)
External Clock Drive XTAL1
TA=0 to + 70°C; VCC=5 V ± 10%; VSS=0 V
Symbol
CPU Clock
20MHz
Parameter
Variable TIming
1/TCL = 2 to 40MHz
min.
max.
min.
max.
Unit
TCL
Oscillator Period
25
25
25
500
ns
t1
High Time
6
-
6
-
ns
t2
Low TIme
6
-
6
-
ns
t3
Rise TIme
_
5
-
5
ns
t4
Fail Time
_
5
-
5
ns
Figure 11. External Clock Drive XTAL1
7/17

ST10F166
AC CHARACTERISTICS (Continued)
CLKOUT and READY
TA=0 to + 70°C; VCC=5 V ± 10%; VSS=0 V;
CL (for Ports 0, 1 and 4, ALE, RD, WR, BHE, CLKOUT)=100pF
Symbol
CPU Clock
20MHz
Parameter
Variable Timing
1/TCL = 2 to 40MHz
min.
max.
min.
max.
Unit
t29
CLKOUT Cycle Time
50
50
2TCL
2TCL
ns
t30
CLKOUT High Time
15
-
TCL - 10
-
ns
t31
CLKOUT Low Time
15
-
TCL - 10
-
ns
t32
CLKOUT Rise TIme
-
5
-
5
ns
t33
CLKOUT Fall Time
-
5
-
5
ns
t34
ALE Rising to CLKOUT
Falling Edge
0
10
0
10
ns
t35
Synchronous READY
Setup Time to CLKOUT
10
-
10
-
ns
t36
Synchronous READY
Hold Time to CLKOUT
10
-
10
-
ns
t37
Asynchronous READY
Hold TIme
65
-
2TCL + 15
-
ns
Figure 12. CLKOUT and READY
8/17

ST10F166
AC CHARACTERISTICS (Continued)
Multiplexed Bus with Read/Write Delay
TA=0 to + 70°C; VCC=5 V ± 10%; VSS=0 V;
CL (for Ports 0, 1 and 4, ALE, RD, WR, BHE, CLKOUT)=100pF
ALE cycle time = 6TCL (150ns at 20MHz CPU clock)
Symbol
CPU Clock
20MHz
Parameter
Variable Timing
1/TCL = 2 to 40MHz
Unit
min.
max.
min.
max.
t5
ALE High Time
15
-
TCL - 10
-
ns
t6
Address Setup to ALE
10
-
TCL - 15
-
ns
t7
Address Hold after ALE
15
-
TCL - 10
-
ns
t8
ALE Falling Edge to RD, WR
15
-
TCL - 10
-
ns
t10
Address Float after RD, WR
-
5
-
5
ns
t12
RD, WR Low Time
40
-
2TCL - 10
-
ns
t14
RD to Valid Data In
-
35
-
2TCL - 15
ns
t16
ALE Low to Valid Data In
-
60
-
3TCL - 15
ns
t17
Address to Valid Data In
-
75
-
4TCL - 25
ns
t18
Data Hold after RD Rising Edge
0
-
0
-
ns
t19
Data Float after RD
-
35
-
2TCL - 15
ns
t22
Data Valid to WR
35
-
2TCL - 15
-
ns
t23
Data Hold after WR
35
-
2TCL - 15
-
ns
t25
ALE rising edge after RD, WR
35
-
2TCL - 15
-
ns
t27
Address Hold after RD, WR
35
-
2TCL - 15
-
ns
9/17

ST10F166
Figure 13. External Memory Read Cycle
Figure 14. External Memory Write Cycle
10/17

ST10F166
AC CHARACTERISTICS (Continued)
Multiplexed Bus without Read/Write Delay
TA=0 to + 70°C; VCC=5 V ± 10%; VSS=0 V;
CL (for Ports 0, 1 and 4, ALE, RD, WR, BHE, CLKOUT)=100pF
ALE cycle time = 6TCL (150ns at 20MHz CPU clock)
Symbol
CPU Clock
20MHz
Parameter
Variable Timing
1/TCL = 2 to 40MHz
Unit
min.
max.
min.
max.
t5
ALE High Time
15
-
TCL - 10
-
ns
t6
Address Setup to ALE
10
-
TCL - 15
-
ns
t7
Address Hold after ALE
15
-
TCL - 10
-
ns
t9
ALE Falling Edge to RD, WR
- 10
-
- 10
-
ns
t11
Address Float after RD, WR
-
30
-
TCL + 5
ns
t13
RD, WR Low Time
65
-
3TCL - 30
-
ns
t15
RD to Valid Data In
-
60
-
3TCL - 15
ns
t16
ALE Low to Valid Data In
-
60
-
3TCL - 15
ns
t17
Address to Valid Data In
-
75
-
4TCL - 25
ns
t18
Data Hold after RD Rising Edge
0
-
0
-
ns
t19
Data Float after RD
-
35
-
2TCL - 15
ns
t22
Data Valid to WR
35
-
2TCL - 15
-
ns
t23
Data Hold after WR
35
-
2TCL - 15
-
ns
t25
ALE rising edge after RD, WR
35
-
2TCL - 15
-
ns
t27
Address Hold after RD, WR
35
-
2TCL - 15
-
ns
11/17

ST10F166
Figure 15. External Memory Read Cycle
Figure 16. External Memory Write Cycle
12/17

ST10F166
AC CHARACTERISTICS (Continued)
Non-Multiplexed Bus with Read/Write Delay
TA=0 to + 70°C; VCC=5 V ± 10%; VSS=0 V;
CL (for Ports 0, 1 and 4, ALE, RD, WR, BHE, CLKOUT)=100pF
ALE cycle time = 4TCL (100ns at 20MHz CPU clock)
Symbol
CPU Clock
20MHz
Parameter
Variable Timing
1/TCL = 2 to 40MHz
min.
max.
min.
Unit
max.
t5
ALE High Time
15
-
TCL - 10
-
ns
t6
Address Setup to ALE
10
-
TCL - 15
-
ns
t8
ALE Falling Edge to RD, WR
15
-
TCL - 10
-
ns
t12
RD, WR Low Time
40
-
2TCL - 10
-
ns
t14
RD to Valid Data In
-
35
-
2TCL - 15
ns
t16
ALE Low to Valid Data In
-
60
-
3TCL - 15
ns
t17
Address to Valid Data In
-
75
-
4TCL - 25
ns
t18
Data Hold after RD Rising Edge
0
-
0
-
ns
t20
Data Float after RD *)
-
35
-
2TCL - 15
ns
t22
Data Valid to WR
35
-
2TCL - 15
-
ns
t24
Data Hold after WR
15
-
TCL - 10
-
ns
t26
ALE rising edge after RD, WR
- 10
-
- 10
-
ns
t28
Address Hold after RD, WR
0
-
0
-
ns
*) This time may be longer if no external bus conflict can occur. For example, this requirement is always met if only code but no data are accessed
externally.
13/17

ST10F166
Figure 17. External Memory Read Cycle
Figure 18. External Memory Write Cycle
14/17

ST10F166
AC CHARACTERISTICS (Continued)
Non-Multiplexed Bus without Read/Write Delay
TA=0 to + 70°C; VCC=5 V ± 10%; VSS=0 V;
CL (for Ports 0, 1 and 4, ALE, RD, WR, BHE, CLKOUT)=100pF
ALE cycle time = 4TCL (100ns at 20MHz CPU clock)
Symbol
CPU Clock
20MHz
Parameter
Variable Timing
1/TCL = 2 to 40MHz
min.
max.
min.
Unit
max.
t5
ALE High Time
15
-
TCL - 10
-
ns
t6
Address Setup to ALE
10
-
TCL - 15
-
ns
t9
ALE Falling Edge to RD, WR
- 10
-
- 10
-
ns
t13
RD, WR Low Time
65
-
3TCL - 10
-
ns
t15
RD to Valid Data In
-
60
-
3TCL - 15
ns
t16
ALE Low to Valid Data In
-
60
-
3TCL - 15
ns
t17
Address to Valid Data In
-
75
-
4TCL - 25
ns
t18
Data Hold after RD Rising Edge
0
-
0
-
ns
t21
Data Float after RD *)
t22
Data Valid to WR
t24
t26
t28
Address Hold after RD, WR
-
15
-
TCL - 10
ns
35
-
2TCL - 15
-
ns
Data Hold after WR
15
-
TCL - 10
-
ns
ALE rising edge after RD, WR
- 10
-
- 10
-
ns
0
-
0
-
ns
*) This time may be longer if no external bus conflict can occur. For example, this requirement is always met if only code but no data are accessed
externally.
15/17

ST10F166
Figure 19. External Memory Read Cycle
Figure 20. External Memory Write Cycle
16/17

ST10F166
PACKAGE MECHANICAL DATA
Dim.
mm
Min
Typ
A2
2.55
2.80
D
22.95
D1
19.90
inches
Min
Typ
3.05
0.100
0.110
0.120
23.20
23.45
0.904
0.913
0.923
20.00
20.10
0.783
0.787
0.791
A
Max
3.40
D3
0.134
18.85
ZD
Max
0.742
0.58
0.023
E
16.95
17.20
17.45
0.667
0.667
0.687
E1
13.90
14.00
14.10
0.547
0.551
0.555
E3
12.35
0.486
ZE
0.83
0.033
e
0.65
0.026
N
100
100
ORDERING INFORMATION
Sales type
Frequency
Temperature Range
ST10F166AQ1
ST10F166AQ6
0 to 70°C
40MHz
-40 to 85°C
ST10F166AQ7
-40 to 105°C
ST10F166BQ1
0 to 70°C
ST10F166BQ6
32MHz
-40 to 85°C
ST10F166BQ7
-40 to 105°C
ST10F166CQ1
0 to 70°C
ST10F166CQ6
Package
24MHz
-40 to 85°C
ST10F166CQ7
PQFP100
PQFP100
PQFP100
-40 to 105°C
17/17

ST10F166
NOTES:

ST10166
ST10R166

16 BIT MCU WITH A/D CONVERTER
PRELIMINARY DATA
High-Performance 16-bit CPU with 4-Stage
Pipeline
100ns Instruction Cycle Time at 20MHz CPU
Clock
500ns Multiplication (16x16 bits), 1µs Division
(32/16 bits)
Enhanced Boolean Bit Manipulation Facilities
Register-Based Design with Multiple Variable
Register Banks
Single-Cycle Context Switching Support
256 Kbyte Linear Address Space for Code and
Data
1Kbyte On-Chip RAM
32 KBYTE ON-CHIP ROM (ST10166 ONLY)
512 byte On-Chip Special Function Register
Area
8-Channel Interrupt-Driven Single-Cycle Data
Transfer Facilities via Peripheral Event Controller (PEC)
16-Priority-Level Interrupt System
10-Channel 10-bit A/D Converter with 9.75µs
Conversion Time
16-Channel Capture/Compare Unit
2 Multi-Functional General Purpose Timer Units
2 Serial Channels (USARTs)
Programmable Watchdog Timer
76 General Purpose I/O Lines
Temperature Range: 0 to 70 °C, -40 to 85 °C, -40
to 125 °C)
1.2 micron multifunctional CMOS technology
100 Pin Metric Plastic Quad Flat Pack (PQFP)
Rectangular Package
PQFP100
(Ordering Information at the end of the datasheet)
A complete set of development tools is also available including:
- ’C’-Compiler
- Assembler, Linker/Locater
- Librarian
- Emulator
- Starter Kit
April 1992
This is advance information from SGS-THOMSON. Details are subject to change without notice.
1/6
ST10166 / ST10R166
Figure 1. ST10166/ST10R166 Pin Configuration
Table 1. PINOUT Description ST10166/ST10R166
Pin
number
Pin
name
Pin
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.3
P0.4
P0.5
P0.6
P0.7
VSS
VCC
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P4.0
P4.1
VCC
XTAL2
XTAL1
VSS
BUSACT
EBC1
EBC0
ALE
RD
RSTIN
RSTOUT
NMI
P1.0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin
name
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VCC
VSS
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
P5.0
P5.1
P5.2
2/6

Pin
number
Pin
name
Pin
number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P5.3
P5.4
P5.5
VAREF
VAGND
P5.6
P5.7
P5.8
P5.9
VSS
VCC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
VSS
VCC
P3.0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
name
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
VCC
VSS
P3.13
P3.14
P3.15
P0.0
P0.1
P0.2
ST10166 / ST10R166
ABSOLUTE MAXIMUM RATINGS
Ambient temperature
under bias (TA)
0 to + 70 °C
- 65 to + 125 °C
Storage temperature (TST)
+ 6.5 V
Supply Voltage (VCC)
Input Voltage (VIN min. = -3.0 V
for pulse width less than 15ns)- 0.5 to VCC + 0.5 V
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note:The ST10166/ST10R166 is also offered in the temperature
range -40° to 125°C and -40° to 85°C.
All the following time specifications refer to a CPU clock of
20MHz which is identical to an oscillator frequency (fosc) of
40MHz.
Symbol
Limit Values
Parameter
min.
max.
- 0.5
0.2 VCC
- 0.1
Unit
Test Condition
V
-
V
-
VIL
Input Low Voltage
VIH
Input High Voltage
(all except RSTIN and XTAL1)
0.2 VCC
+ 0.9
VCC + 0.5
VIH1
Input High Voltage RSTIN
0.6 VCC
VCC + 0.5
V
-
VIH2
Input High Voltage XTAL1
0.7 VCC
VCC + 0.5
V
-
VOL
Output Low Voltage
(Ports 0, 1, 4, ALE RD, WR,
BHE, CLKOUT, RSTOUT
-
0.4
V
IOL = 2.4mA
VOL1
Output Low Voltage
(all other outputs)
-
0.4
V
IOL1 = 1.6mA
VOH
Output High Voltage
(Ports 0, 1, 4, ALE RD, WR,
BHE, CLKOUT, RSTOUT
0.9 VCC
2.4
-
V
VOH1
Output High Voltage
(all other outputs)
0.9 VCC
2.4
−
V
V
IOH = - 50µA
IOH = - 1.6mA
-
±1
mA
0 V<Vin<VCC
IOZ
Input Leakage Current (Ports 0,
1,2,3,4, NMI, EBC0, EBC1,
BUSACT)
IOH = - 100µA
IOH = - 2.4mA
3/6

ST10166 / ST10R166
DC Characteristics (Continued)
Symbol
Limit Values
Parameter
min.
max.
Unit
Test Condition
RRST
Reset Pullup Resistor
50
150
kΩ
-
IIL
XTAL1 Input Current
-
tbd
µA
0 V<Vin<VCC
CIO
Pin Capacitance
(digital inputs/outputs)
-
10
pF
f= 1MHz
TA = 25 °C
ICC
Power Supply Current
-
180
mA
1/TCL = 40MHz
IID
Idle Mode Supply Current
-
20
mA
1/TCL = 40MHz
IPD
Power Down Mode Supply
Current
-
100
µA
VCC = 2.5 V 1)
A/D CONVERTER CHARACTERISTICS
TA = 0 to + 70 °C; VCC = 5 V ± 10%; VSS = 0 V; VAREF = VCC ± 0.2 V; VAGND = VSS ± 0.2 V
Symbol
VAIN
CI
tS
tC
TUE
IREF
IAIN
Limit Values
Parameter
Analog Input Voltage
Analog Input Capacitance
Sample TIme
Converstion Time
Total Unadjusted Error
VAREF Supply Current
Analog Input Current
min.
max.
VSS - 0.2
±500
VCC + 0.2
70
63 TCL
390 TCL
±2
5
Notes:
1) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V CC - 0.1 V to
VCC, VREF = 0 V, all outputs (including pins configured as outputs)
disconnected.
2) This parameter specifies the time during which the input capacitance CI can be charged/decharged by the external source. It must
be guaranteed, that the input capacitance CI is fully loaded within
these 63 TCLs.
AC CHARACTERISTICS
Refer to the ST10F166 Data Sheet for AC characteristics
4/6

Unit
Test Condition
V
pF
2)
3)
4)
5)
LSB
mA
nA
63 TCL is 1.575µs at 20MHz CPU clock. After the end of the sample
time ts, changes of the analog input voltage have no effect on the
conversion result.
3) This parameter includes the sample time t s. 390 TCL is 9.75µs at
20MHz CPU clock.
4) IREF in Power Down Mode: TBD
5) This parameter specifies the static input current for an analog input channel, e.g. when the channel is not selected for conversion.
ST10166 / ST10R166
PACKAGE MECHANICAL DATA
Dim.
mm
inches
Min
Typ
Max
Min
Typ
A2
2.55
2.80
3.05
0.100
0.110
D
22.95
0.120
23.20
23.45
0.904
0.913
0.923
D1
19.90
20.00
20.10
0.783
0.787
0.791
A
3.40
Max
0.134
D3
18.85
0.742
ZD
0.58
0.023
E
16.95
17.20
17.45
0.667
0.667
0.687
E1
13.90
14.00
14.10
0.547
0.551
0.555
E3
12.35
ZE
0.83
0.486
0.033
e
0.65
0.026
N
100
100
ORDERING INFORMATION
Sales type
ST10166AQ1
Frequency
Temperature Range
0 to 70°C
40MHz
ST10166AQ6
ST10R166AQ1
0 to 70°C
40MHz
0 to 70°C
32MHz
0 to 70°C
32MHz
PQFP100
-40 to 85°C
0 to 70°C
24MHz
ST10166CQ6
ST10R166CQ1
PQFP100
-40 to 85°C
ST10R166BQ6
ST10166CQ1
PQFP100
-40 to 85°C
ST10166BQ6
ST10R166BQ1
PQFP100
-40 to 85°C
ST10R166AQ6
ST10166BQ1
Package
PQFP100
-40 to 85°C
0 to 70°C
24MHz
ST10R166CQ6
PQFP100
-40 to 85°C
5/6

ST10166 / ST10R166
NOTES:
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This
publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All rights reserved.
Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I 2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips.
SGS-THOMSON Microelectronics Group of Companies
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6/6

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