Aeroflex UT8MR8M8-EVB User manual

Standard Products

UT8MR8M8-EVB

64Megabit Non-

Volatile MRAM

Evaluation Board

User Manual

July 2012 www.aeroflex.com/memories

1.0 INTRODUCTION

The Aeroflex 64Megabit Non-Volatile magnetoresistive random access memory (MRAM) is a highperformance memory multichip module (MCM) compatible with traditional asynchronous SRAM operations, organized as four individual 16,777,216 words by 8 bits. The MRAM is equipped with five chip enables (/En), a single write enable (/W), and a single output enable (/G) pin, allowing for significant system design flexibility without bus contention. Data is non-volatile for > 15 years at temperature and data is automatically protected against power loss by a low voltage write inhibit.

The UT8MR8M8-EVB allows the user access to most all the features of the 64Mb MRAM via bench top evaluation or using the UT699 LEON-3FT evaluation board.

2.0 SCOPE

This document describes the features and necessary steps to set-up and operate the Aeroflex Colorado Springs

64Megabit Non-Volatile MRAM Evaluation Board. Users must be familiar with the UT699 LEON-3FT Processor and the 64Megabit Non-Volatile MRAM datasheets.

3.0 REFERENCE DOCUMENTS

Aeroflex Colorado Springs, “UT8MR8M8 64Megabit Non-Volatile MRAM” Datasheet, www.aeroflex.com/memories

Aeroflex Gaisler “GR-CPCI-UT699 LEON3-FT CPCI Development Board” User Manual, www.aeroflex.com/LEON

Aeroflex Colorado Springs, “UT699 32-bit Fault Tolerant SPARC

TM

V8/LEON3FT Processor” Datasheet, www.aeroflex.com/LEON

1

4.0 FUNCTIONAL DIAGRAM

Figure 1. Notional UT8MR8M8-EVB block diagram

2

5.0 FEATURES AND GENERAL OPERATION

The Aeroflex 64Megabit Non-Volatile MRAM Evaluation Board provides the user with a flexible means to configure, control, access, and read/write data to the UT8MR8M8 device. Power to the board may be provided through the J9 connector on the GR-UT699 CPCI Development Board or through the 100 mil connector J8 on the

UT8MR8M8-EVB. Only one power source should be used at a time.

5.1 Power

5.1.1 External Power

Power to the UT8MR8M8-EVB may be provided externally using 3.3V if using in a bench top only configuration.

Figure 2. External Power Jumper Configuration Settings

3

5.1.2 Aeroflex Gaisler Board Power

Power to the UT8MR8M8-EVB is also provided from the J9 connector on the GR-CPCI-UT699 LEON3-

FT CPCI Development Board. J7, the 120 pin connector, is located on the back side of the EVB.

Use caution when mating the 64Megabit Non-Volatile MRAM Evaluation Board to the LEON-3FT evaluation board. Ensure that the mating connectors are lined up and that the power is removed from the

GR-cPCI-UT699 eval board prior to plugging in the MRAM evaluation board.

Table 1. LEON-3FT-EVB Power Pins (J9) Table 2. LEON-3FT-EVB Ground pins (J9)

LEON-3FT connector LEON-3FT connector

Pin

10

20

30

40

51

71

81

91

101

111

Signal

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

Pin

1

3

5

7

11

21

31

41

50

60

61

70

80

90

100

110

114

116

118

120

Signal

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

4

Figure 3. Aeroflex Gaisler LEON-3FT J7 to J9 connector

5

5.2 Address Inputs

Table 3. Address Inputs J7 pin out

LEON-3FT connector

(J9)

Pin

UT8MR8M8 Device

(J7)

Signal Pin Signal

45 A0 10 A0

76 A1 9 A1

44 A2 8 A2

77 A3 7 A3

43 A4 6 A4

78 A5 28 A5

42 A6 27 A6

79 A7 26 A7

39 A8 25 A8

82 A9 24 A9

38 A10 41 A10

83 A11 40 A11

37 A12 39 A12

84 A13 38 A13

36 A14 37 A14

85 A15 58 A15

35 A16 57 A16

86 A17 56 A17

34 A18 55 A18

87 A19 11 A19

33 A20 59 A20

88 A21 22 A21

32 A22 23 A22

6

5.3 Data I/O

The UT8MR8M8 has eight bidirectional data lines, DQ[7:0]. The data inputs/outputs are connected to J7 as shown in table 4.

Table 4. Data I/O J7 pin out

LEON-3FT connector

(J9)

Pin

UT8MR8M8 Device

Signal Pin

(J7)

Signal

95 D24 46 DATA0

97 D25 47 DATA1

99 D26 50 DATA2

103 D27 51 DATA3

105 D28 14 DATA4

107 D29 15 DATA5

109 D30 18 DATA6

113 D31 19 DATA7

7

5.4 Chip Enable

Asserting /E_All allows the device to be addressed as a single, 64Mb memory using address bits A21 and

A22 to decode and select 1 of 4 MRAM die.

Table 5. Enable Signals LEON-3FT (J5)

LEON-3FT connector

(J9)

UT8MR8M8 Device

(J7)

Pin

48 ROMSN0

21

Can be jumpered to /E_ALL for LEON-3FT to control the

UT8MR8M8

74 IOSN 21 Can be jumpered to /E_ALL

The user can exercise either the IOSN or ROMSN0 pin on the LEON-3FT to exercise the /E_All pin on the

MRAM. There is a three pin header, J5, that allows the user to select IOSN or ROMSN0 to control the

/E_All pin.

Figure 6. /E_All header control

5.4.1 Use as an External Memory with LEON

Set J5 to ROMSN0 on the UT8MR8M8-EVB and uninstall JP6 on the UT699-EVB.

5.4.2 Use as IO Space

Set J5 to IOSN option on the UT8MR8M8-EVB and install JP6 on the UT699-EVB.

5.5 Write Enable (/W)

8

/W controls read and write operation. During a read cycle, /G must be asserted to enable the outputs.

Table 6. Write Enable LEON-3FT J7 to J9 connector

LEON-3FT connector

(J9)

UT8MR8M8 Device

(J7)

Pin Signal Pin Signal

46 WEB 42 /W

5.6 Output Enable (/G)

/W controls read and write operation. During a read cycle, /G must be asserted to enable the outputs.

Table 7. Output Enable LEON-3FT J7 to J9 connector

LEON-3FT connector

(J9)

UT8MR8M8 Device

(J7)

Pin Signal Pin Signal

47 OEB 53 /G

5.7 Deep Sleep Power Down (ZZ)

ZZ controls the sleep mode operation. Enabling sleep mode causes all other inputs to be do not cares. ZZ places all die into internal low power even while system power is still applied to VDD. Pin 12 on the

UT8MR8M8 are routed to a three pin header J2. The center pin on the three pin J2 header is tied to the ZZ pin, the other pins are tied to VDD and VSS. Please refer to the UT8MR8M8 datasheet for further information.

UT8MR8M8

Dee p Pow er D own

5.8 Multi-Bit Error Flag (MBE)

Figure 7. ZZ pin

9

The open drain MBE pin drives low when ECC logic detects two bit errors during the current read cycle. It allows for wired-or of multiple MBE signals when using multiple MRAMs. The MBE signal is routed to the one pin J6 header. This pin can be monitored if the user chooses to do so.

MBE

UT8MR8M8

Figure 8. MBE pin

6.0

Quick Start Guide

The following steps describe how the user to get the UT8MR8M8-EVB up and running with the

UT699 LEON-3FT EVB.

1. Connect J5to the UT8MR8M8-EVB to ROMSN0 for using MRAM as PROM

- or -

Connect J5to the UT8MR8M8-EVB to IOSN for using MRAM as IO Space

2. Disconnect power to the UT699-EVB

3. Plug the UT8MR8M8-EVB J7 to J9 on the UT699-EVB

4. Configure DIP switches S3 and S4 as shown in Table 9 and 10.

5. Reference Section 3 “SETTING UP AND USING THE BOARD” in the user’s manual for the GR-UT699 board. Install the jumpers as indicated in Table 11.

10

Table 8. Quick Start LEON-3FT S3 8-bit mode Configuration

DIP Switch S3

Switch Function Value

1 PIO0 0 8-bit Mode (Closed)

2 PIO1 0 8-bit Mode (Closed)

3 PIO2 0 PROM EDAC disabled (Closed)

4

5

6

7

8

Table 9. Quick Start LEON-3FT S4 Configuration

DIP Switch S4

Switch Function Value

1

2

3

4

5

6

7

8

11

Table 10. Quick Start LEON-3FT Jumper settings for ROMSN0 or IOSN

Jumper Jumper Setting Comment

JP1

1-2: Do Not Install

3-4: Do Not Install

5-6: Do Not Install

7-8: Do Not Install

JP2 Do Not Install

ASIC TEST mode pin not enabled DSU is enabled JTAG interface is enabled.

Watchdog output can cause board reset

Ethernet MDIO interface interrupt is not connected to GPIO4

JP3 1-3: Install End-stub termination enabled – see section 2.4.1

JP4 1-3: Install End-stub termination enabled – see section 2.4.1

JP5

JP6

1-2: Install

3-4: Install

5-6: Install

7-8: Install

Do Not Install

1-2: Install

Connects RAMSN0 and RAMSN1 to on board SRAM banks

Connects ROMSN0 to on board MRAM on UT8MR8M8-EVB

Connects IOSN to on board MRAM on UT8MR8M8-EVB

JP7

1-2: Install

3-4: Install

PCI Host Mode clocks to backplane – see section 2.11

JP8

JP9

JP10

1-2: Install

3-4: Install

5-6: Install

7-8: Install

9-10: Install

11-12: Install

13-14: Install

15-16: Install

17-18: Install

19-20: Install

1-2: Install

3-4: Install

1-2: Install

3-4: Install

PCI Host Mode- Pull ups enabled – see section 2.11

PCI Host Mode – see section 2.11

PCI Host Mode – see section 2.11

JP11 Install Connects to Front Panel LED indicators

JP12 1-2: Install See section 2.9

JP13 1-2: Install See section 2.9

JP14 Install Can be used as current measure point for Vcore supply to ASIC

JP15 Install Can be used as current measure point for 3.3V supply to ASIC

JP16 Install

JP17 1-2: Install

JP18

1-2: Install

Connected to Front Panel push buttons for RESET and BREAK

Main Processor Clock is also source for SPW_CLK

Board RESETN also generated PCI_RSTN for PCI Host

6. Power on the UT699-EVB

7. Using GRMON: a. MRAM as PROM: The following commands need to be run to set up memory configuration register 1 to allow reading and writing the MRAM when it is configured as the PROM for the UT699. i. wmem 0x80000000 0x1803c811 ii. mcfg1 0x1803c811 iii. User code

12

b. MRAM as I/O space: The following commands need to be run to set up memory configuration register 1 to allow reading and writing the MRAM when it is configured as I/O space for the UT699. i. wmem 0x80000000 0x001BC811 ii. mcfg1 0x001BC811 iii. User code

7.0 COMPATIBILITY WITH GR-UT699 EVALUATION BOARD

The UT8MR8M8-EVB can plug directly into the J9 connector on the LEON-3FT evaluation board. J9 on the GR-UT699 evaluation board is pinned out as listed in table 12 below.

For further information on interfacing the UT8MR8M8-EVB with the GR-UT699 Evaluation board please see the Aeroflex Gaisler GR-UT699 Development Board User Manual.

Table 11. UT8MR8M8-EVB to UT699-3FT LEON connections

LEON-3FT connector UT8MR8M8 Device

Pin Signal Pin

1 VSS

2 +5V

3 VSS

4 -12V

5 VSS

6 +12V

7 VSS

8 D15

9 D7

10

11

3.3V

VSS

12 D14

13 D6

14 D13

15 D5

16 D12

17 D4

18 D11

19 D3

20 3.3V

21 VSS

22 D10

23 D2

24 D9

25 D1

13

26 D8

27 D0

28 A26

29 A14

30

31

32 A22

33 A20

34 A18

35 A16

36 A14

37 A12

38 A10

23

59

55

57

37

39

41

3.3V

VSS

A22

A20

A18

A16

A14

A12

A10

39 A8

40

41

42 A6

25

27

A8

3.3V

VSS

A6

43 A4

44 A2

45 A0

6

8

10

A4

A2

A0

46 WEB

50

42 WEB

47 OEB

48 ROMSN0

53 OEB

ROMSN0

49 RAMSN4

VSS

51 3.3V

52 RAMSN3

53 RAMSN2

54 RAMSN1

55 RAMSN0

56 RWEN2

57 RWEN0

58 BRDYN

59 RESETN

60

61

VSS

VSS

62 CLK

63 BEXCN

64 RWEN1

65 RWEN3

66 RAMOEN0

67 RAMOEN1

68 RAMOEN2

69 RAMOEN3

70 VSS

14

71 3.3V

72 RAMOEN4

73 RAMSN1

74 IOSN

75 READ

76 A1

77 A3

78 A5

79 A7

9

7

28

26

A1

A3

A5

A7

80

81

82 A9

83 A11

24

40

VSS

3.3V

A9

A11

84 A13

85 A15

86 A17

38

58

56

A13

A15

A17

87 A19

91

11 A19

88 A21

90

22 A21

89 A23

VSS

3.3V

92 A25

93 A27

94 D16

95 D24 46 DATA0

96 D17

97 D25 47 DATA1

98 D18

99 D26

103 D27

50

100

101

VSS

3.3V

102 D19

51

DATA2

DATA3

104 D20

105 D28 14 DATA4

106 D21

107 D29

111

15 DATA5

108 D22

109 D30

110

18 DATA6

VSS

3.3V

112 D23

113 D31

114

19 DATA7

VSS

115 +12V

15

116

120

VSS

117 -12V

118 VSS

119 +5V

VSS

16

8.0

BOARD SCHEMATICS

The schematics are for reference ONLY.

17

5 4 3 2

Change Block

1 MQ11

D

VDD3_3V

Silkscreen

VDD

Silkscreen

ZZ SLEEPY

J2

Silkscreen

VSS

1

2

3

HEADER 3

C

Silkscreen

IOSN

J5

ROMSN0

1

2

3

HEADER 3

IOSN

E1_138_CS

ROMSN0

VDD3_3V

CEB_1

ADR4

ADR3

ADR2

ADR1

ADR0

ADR19

DATA4

DATA5

DATA6

DATA7

CEB_2

ADR21_138

ADR22_138

ADR9

ADR8

ADR7

ADR6

ADR5

Silkscreen UT8MR8M8(P)

U2

19

20

21

22

23

24

13

14

15

16

17

18

9

10

11

12

7

8

3

4

5

6

1

2

25

26

27

28

29

30

31

32

VSS

VDD

NC1

NC2

E0_B

A4

A3

A2

A1

A0

A19

ZZ_NUIL

NC3

DQ4

DQ5

VDD

VSS

DQ6

DQ7

E1_B

VDD

DQ1

DQ0

E2_B

E_B_ALL_NUIH

A21_NUIL

VSS

MBE_NUO

A22_NUIL

A9

A8

A7

A6

A5

W_B

A10

A11

A12

A13

A14

VSS

VSS

VSS

VDD

VSS

VSS

VDD

VSS

VDD

VSS

NC4

NC5

E3_B

A20

A15

A16

A17

A18

NC6

G_B

NC7

DQ3

DQ2

VSS

46

45

44

43

42

41

52

51

50

49

48

47

58

57

56

55

54

53

64

63

62

61

60

59

40

39

38

37

36

35

34

33

UT8MR8M8_MQ9_10

ADR21_138

VDD3_3V

ADR22_138

E1_138_CS

VDD3_3V

U1

4

5

6

1

2

3

A0

A1

A2

E1

E2

E3

54AC138/FP

O0

O1

O2

O3

O4

O5

O6

O7

15

14

9

7

13

12

11

10

CEB_1

CEB_2

CEB_3

CEB_4

CEB_4

ADR20

ADR15

ADR16

ADR17

ADR18

DATA3

DATA2

DATA1

DATA0

CEB_3

ADR10

ADR11

ADR12

ADR13

ADR14

OEB

VDD3_3V

VDD3_3V

Silkscreen

VDD

Silkscreen

VSS

Silkscreen

UT54ACS138E pin G1

J11

1

2

3

HEADER 3

WEB

HEADER 1

VDD3_3V

B

Silkscreen

3.3V POWER

J8

HEADER 2

VDD3_3V

VDD3_3V

C1 C2 C3 C4 C5 C6

+

C7

47uF

J9

Silkscreen

GND

HEADER 2

J10

HEADER 2

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

IOSN

ADR1

ADR3

ADR5

ADR7

ADR9

ADR11

ADR13

ADR15

ADR17

ADR19

ADR21_138

Silkscreen

TO LEON-3FT UT699 EVAL board

J7

A11

A13

A15

A17

A19

A21

A3

A5

A7

DGND

3.3V

A9

A23

DGND

3.3V

A25

A27

D16

D24

D17

D25

D18

D26

DGND

3.3V

D19

D27

D20

D28

D21

D29

D22

D30

DGND

3.3V

D23

D31

DGND

+12V

DGND

-12V

DGND

+5V

DGND

DGND

CLK

BEXCN

RWEN1

RWEN3

RAMOEN0

RAMOEN1

RAMOEN2

RAMOEN3

DGND

3.3V

RAMOEN4

ROMSN1

IOSN

READ

A1

A2

A4

A6

DGND

3.3V

A8

A10

A12

A14

A16

A18

A20

A22

DGND

3.3V

A24

A26

D0

D8

D1

D9

D2

D10

DGND

3.3V

D3

D11

D4

D12

D5

D13

D6

D14

DGND

3.3V

D7

D15

DGND

+12V

DGND

-12V

DGND

5V

DGND

DGND

RESETN

BRDYN

RWEN0

RWEN2

RAMSN0

RAMSN1

RAMSN2

RAMSN3

DGND

3.3V

RAMSN4

ROMSN0

OEN

WRITEN

A0

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

67

68

69

70

71

72

73

74

75

76

77

78

61

62

63

64

65

66

79

80

81

82

83

84

85

86

87

88

89

90

CONN_MEZ120

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

7

6

5

9

8

4

3

2

1

54

53

52

51

50

49

48

47

46

45

44

43

60

59

58

57

56

55

42

41

40

39

38

37

36

35

34

33

32

31

ROMSN0

OEB

WEB

ADR0

ADR2

ADR4

ADR6

ADR8

ADR10

ADR12

ADR14

ADR16

ADR18

ADR20

ADR22_138

A

5 4 3 2

Larsen

1

1

VDD3_3V

D

C

B

A

ORDERING INFORMATION

Device Type:

8MR8M8-EVB = 64Megabit Non-Volatile MRAM Evaluation Board

18

Aeroflex Colorado Springs - Datasheet Definition

Advanced Datasheet - Product In Development

Preliminary Datasheet - Shipping Prototype

Datasheet - Shipping QML & Reduced Hi – Rel

19